2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
29 #define MASK(n) ((1ULL<<(n))-1)
30 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
32 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
34 #define CRB_BLK(off) ((off >> 20) & 0x3f)
35 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
36 #define CRB_WINDOW_2M (0x130060)
37 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
38 #define CRB_INDIRECT_2M (0x1e0000UL)
42 static inline u64
readq(void __iomem
*addr
)
44 return readl(addr
) | (((u64
) readl(addr
+ 4)) << 32LL);
49 static inline void writeq(u64 val
, void __iomem
*addr
)
51 writel(((u32
) (val
)), (addr
));
52 writel(((u32
) (val
>> 32)), (addr
+ 4));
56 static const struct crb_128M_2M_block_map
57 crb_128M_2M_map
[64] __cacheline_aligned_in_smp
= {
58 {{{0, 0, 0, 0} } }, /* 0: PCI */
59 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
60 {1, 0x0110000, 0x0120000, 0x130000},
61 {1, 0x0120000, 0x0122000, 0x124000},
62 {1, 0x0130000, 0x0132000, 0x126000},
63 {1, 0x0140000, 0x0142000, 0x128000},
64 {1, 0x0150000, 0x0152000, 0x12a000},
65 {1, 0x0160000, 0x0170000, 0x110000},
66 {1, 0x0170000, 0x0172000, 0x12e000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {0, 0x0000000, 0x0000000, 0x000000},
72 {0, 0x0000000, 0x0000000, 0x000000},
73 {1, 0x01e0000, 0x01e0800, 0x122000},
74 {0, 0x0000000, 0x0000000, 0x000000} } },
75 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
76 {{{0, 0, 0, 0} } }, /* 3: */
77 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
78 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
79 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
80 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
81 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {1, 0x08f0000, 0x08f2000, 0x172000} } },
97 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {1, 0x09f0000, 0x09f2000, 0x176000} } },
113 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
129 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
145 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
146 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
147 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
148 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
149 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
150 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
151 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
152 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
153 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
154 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
155 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
156 {{{0, 0, 0, 0} } }, /* 23: */
157 {{{0, 0, 0, 0} } }, /* 24: */
158 {{{0, 0, 0, 0} } }, /* 25: */
159 {{{0, 0, 0, 0} } }, /* 26: */
160 {{{0, 0, 0, 0} } }, /* 27: */
161 {{{0, 0, 0, 0} } }, /* 28: */
162 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
163 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
164 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
165 {{{0} } }, /* 32: PCI */
166 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
167 {1, 0x2110000, 0x2120000, 0x130000},
168 {1, 0x2120000, 0x2122000, 0x124000},
169 {1, 0x2130000, 0x2132000, 0x126000},
170 {1, 0x2140000, 0x2142000, 0x128000},
171 {1, 0x2150000, 0x2152000, 0x12a000},
172 {1, 0x2160000, 0x2170000, 0x110000},
173 {1, 0x2170000, 0x2172000, 0x12e000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000} } },
182 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
188 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
189 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
190 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
191 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
192 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
193 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
194 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
195 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
196 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
197 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
198 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
199 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
201 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
202 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
203 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
204 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
205 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
206 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
207 {{{0} } }, /* 59: I2C0 */
208 {{{0} } }, /* 60: I2C1 */
209 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
210 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
211 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
215 * top 12 bits of crb internal address (hub, agent)
217 static const unsigned crb_hub_agt
[64] = {
219 QLCNIC_HW_CRB_HUB_AGT_ADR_PS
,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_MN
,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_MS
,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE
,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU
,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN
,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0
,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1
,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2
,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3
,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q
,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR
,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB
,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4
,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA
,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0
,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1
,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2
,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3
,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND
,
240 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI
,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0
,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1
,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2
,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3
,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI
,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_SN
,
249 QLCNIC_HW_CRB_HUB_AGT_ADR_EG
,
251 QLCNIC_HW_CRB_HUB_AGT_ADR_PS
,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM
,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR
,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1
,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2
,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3
,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4
,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5
,
265 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6
,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7
,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA
,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q
,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB
,
271 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0
,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8
,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9
,
274 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0
,
276 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB
,
277 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0
,
278 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1
,
280 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC
,
284 /* PCI Windowing for DDR regions. */
286 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
289 qlcnic_pcie_sem_lock(struct qlcnic_adapter
*adapter
, int sem
, u32 id_reg
)
291 int done
= 0, timeout
= 0;
294 done
= QLCRD32(adapter
, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem
)));
297 if (++timeout
>= QLCNIC_PCIE_SEM_TIMEOUT
) {
298 dev_err(&adapter
->pdev
->dev
,
299 "Failed to acquire sem=%d lock;reg_id=%d\n",
307 QLCWR32(adapter
, id_reg
, adapter
->portnum
);
313 qlcnic_pcie_sem_unlock(struct qlcnic_adapter
*adapter
, int sem
)
315 QLCRD32(adapter
, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem
)));
319 qlcnic_send_cmd_descs(struct qlcnic_adapter
*adapter
,
320 struct cmd_desc_type0
*cmd_desc_arr
, int nr_desc
)
322 u32 i
, producer
, consumer
;
323 struct qlcnic_cmd_buffer
*pbuf
;
324 struct cmd_desc_type0
*cmd_desc
;
325 struct qlcnic_host_tx_ring
*tx_ring
;
329 if (adapter
->is_up
!= QLCNIC_ADAPTER_UP_MAGIC
)
332 tx_ring
= adapter
->tx_ring
;
333 __netif_tx_lock_bh(tx_ring
->txq
);
335 producer
= tx_ring
->producer
;
336 consumer
= tx_ring
->sw_consumer
;
338 if (nr_desc
>= qlcnic_tx_avail(tx_ring
)) {
339 netif_tx_stop_queue(tx_ring
->txq
);
340 __netif_tx_unlock_bh(tx_ring
->txq
);
341 adapter
->stats
.xmit_off
++;
346 cmd_desc
= &cmd_desc_arr
[i
];
348 pbuf
= &tx_ring
->cmd_buf_arr
[producer
];
350 pbuf
->frag_count
= 0;
352 memcpy(&tx_ring
->desc_head
[producer
],
353 &cmd_desc_arr
[i
], sizeof(struct cmd_desc_type0
));
355 producer
= get_next_index(producer
, tx_ring
->num_desc
);
358 } while (i
!= nr_desc
);
360 tx_ring
->producer
= producer
;
362 qlcnic_update_cmd_producer(adapter
, tx_ring
);
364 __netif_tx_unlock_bh(tx_ring
->txq
);
370 qlcnic_sre_macaddr_change(struct qlcnic_adapter
*adapter
, u8
*addr
,
373 struct qlcnic_nic_req req
;
374 struct qlcnic_mac_req
*mac_req
;
377 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
378 req
.qhdr
= cpu_to_le64(QLCNIC_REQUEST
<< 23);
380 word
= QLCNIC_MAC_EVENT
| ((u64
)adapter
->portnum
<< 16);
381 req
.req_hdr
= cpu_to_le64(word
);
383 mac_req
= (struct qlcnic_mac_req
*)&req
.words
[0];
385 memcpy(mac_req
->mac_addr
, addr
, 6);
387 return qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
390 static int qlcnic_nic_add_mac(struct qlcnic_adapter
*adapter
, u8
*addr
)
392 struct list_head
*head
;
393 struct qlcnic_mac_list_s
*cur
;
395 /* look up if already exists */
396 list_for_each(head
, &adapter
->mac_list
) {
397 cur
= list_entry(head
, struct qlcnic_mac_list_s
, list
);
398 if (memcmp(addr
, cur
->mac_addr
, ETH_ALEN
) == 0)
402 cur
= kzalloc(sizeof(struct qlcnic_mac_list_s
), GFP_ATOMIC
);
404 dev_err(&adapter
->netdev
->dev
,
405 "failed to add mac address filter\n");
408 memcpy(cur
->mac_addr
, addr
, ETH_ALEN
);
409 list_add_tail(&cur
->list
, &adapter
->mac_list
);
411 return qlcnic_sre_macaddr_change(adapter
,
412 cur
->mac_addr
, QLCNIC_MAC_ADD
);
415 void qlcnic_set_multi(struct net_device
*netdev
)
417 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
418 struct netdev_hw_addr
*ha
;
419 u8 bcast_addr
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
420 u32 mode
= VPORT_MISS_MODE_DROP
;
422 qlcnic_nic_add_mac(adapter
, adapter
->mac_addr
);
423 qlcnic_nic_add_mac(adapter
, bcast_addr
);
425 if (netdev
->flags
& IFF_PROMISC
) {
426 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
430 if ((netdev
->flags
& IFF_ALLMULTI
) ||
431 (netdev_mc_count(netdev
) > adapter
->max_mc_count
)) {
432 mode
= VPORT_MISS_MODE_ACCEPT_MULTI
;
436 if (!netdev_mc_empty(netdev
)) {
437 netdev_for_each_mc_addr(ha
, netdev
) {
438 qlcnic_nic_add_mac(adapter
, ha
->addr
);
443 qlcnic_nic_set_promisc(adapter
, mode
);
446 int qlcnic_nic_set_promisc(struct qlcnic_adapter
*adapter
, u32 mode
)
448 struct qlcnic_nic_req req
;
451 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
453 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
455 word
= QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE
|
456 ((u64
)adapter
->portnum
<< 16);
457 req
.req_hdr
= cpu_to_le64(word
);
459 req
.words
[0] = cpu_to_le64(mode
);
461 return qlcnic_send_cmd_descs(adapter
,
462 (struct cmd_desc_type0
*)&req
, 1);
465 void qlcnic_free_mac_list(struct qlcnic_adapter
*adapter
)
467 struct qlcnic_mac_list_s
*cur
;
468 struct list_head
*head
= &adapter
->mac_list
;
470 while (!list_empty(head
)) {
471 cur
= list_entry(head
->next
, struct qlcnic_mac_list_s
, list
);
472 qlcnic_sre_macaddr_change(adapter
,
473 cur
->mac_addr
, QLCNIC_MAC_DEL
);
474 list_del(&cur
->list
);
479 #define QLCNIC_CONFIG_INTR_COALESCE 3
482 * Send the interrupt coalescing parameter set by ethtool to the card.
484 int qlcnic_config_intr_coalesce(struct qlcnic_adapter
*adapter
)
486 struct qlcnic_nic_req req
;
490 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
492 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
494 word
[0] = QLCNIC_CONFIG_INTR_COALESCE
| ((u64
)adapter
->portnum
<< 16);
495 req
.req_hdr
= cpu_to_le64(word
[0]);
497 memcpy(&word
[0], &adapter
->coal
, sizeof(adapter
->coal
));
498 for (i
= 0; i
< 6; i
++)
499 req
.words
[i
] = cpu_to_le64(word
[i
]);
501 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
503 dev_err(&adapter
->netdev
->dev
,
504 "Could not send interrupt coalescing parameters\n");
509 int qlcnic_config_hw_lro(struct qlcnic_adapter
*adapter
, int enable
)
511 struct qlcnic_nic_req req
;
515 if ((adapter
->flags
& QLCNIC_LRO_ENABLED
) == enable
)
518 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
520 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
522 word
= QLCNIC_H2C_OPCODE_CONFIG_HW_LRO
| ((u64
)adapter
->portnum
<< 16);
523 req
.req_hdr
= cpu_to_le64(word
);
525 req
.words
[0] = cpu_to_le64(enable
);
527 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
529 dev_err(&adapter
->netdev
->dev
,
530 "Could not send configure hw lro request\n");
532 adapter
->flags
^= QLCNIC_LRO_ENABLED
;
537 int qlcnic_config_bridged_mode(struct qlcnic_adapter
*adapter
, int enable
)
539 struct qlcnic_nic_req req
;
543 if (!!(adapter
->flags
& QLCNIC_BRIDGE_ENABLED
) == enable
)
546 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
548 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
550 word
= QLCNIC_H2C_OPCODE_CONFIG_BRIDGING
|
551 ((u64
)adapter
->portnum
<< 16);
552 req
.req_hdr
= cpu_to_le64(word
);
554 req
.words
[0] = cpu_to_le64(enable
);
556 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
558 dev_err(&adapter
->netdev
->dev
,
559 "Could not send configure bridge mode request\n");
561 adapter
->flags
^= QLCNIC_BRIDGE_ENABLED
;
567 #define RSS_HASHTYPE_IP_TCP 0x3
569 int qlcnic_config_rss(struct qlcnic_adapter
*adapter
, int enable
)
571 struct qlcnic_nic_req req
;
575 const u64 key
[] = { 0xbeac01fa6a42b73bULL
, 0x8030f20c77cb2da3ULL
,
576 0xae7b30b4d0ca2bcbULL
, 0x43a38fb04167253dULL
,
577 0x255b0ec26d5a56daULL
};
580 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
581 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
583 word
= QLCNIC_H2C_OPCODE_CONFIG_RSS
| ((u64
)adapter
->portnum
<< 16);
584 req
.req_hdr
= cpu_to_le64(word
);
588 * bits 3-0: hash_method
589 * 5-4: hash_type_ipv4
590 * 7-6: hash_type_ipv6
592 * 9: use indirection table
594 * 63-48: indirection table mask
596 word
= ((u64
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 4) |
597 ((u64
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 6) |
598 ((u64
)(enable
& 0x1) << 8) |
600 req
.words
[0] = cpu_to_le64(word
);
601 for (i
= 0; i
< 5; i
++)
602 req
.words
[i
+1] = cpu_to_le64(key
[i
]);
604 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
606 dev_err(&adapter
->netdev
->dev
, "could not configure RSS\n");
611 int qlcnic_config_ipaddr(struct qlcnic_adapter
*adapter
, u32 ip
, int cmd
)
613 struct qlcnic_nic_req req
;
617 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
618 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
620 word
= QLCNIC_H2C_OPCODE_CONFIG_IPADDR
| ((u64
)adapter
->portnum
<< 16);
621 req
.req_hdr
= cpu_to_le64(word
);
623 req
.words
[0] = cpu_to_le64(cmd
);
624 req
.words
[1] = cpu_to_le64(ip
);
626 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
628 dev_err(&adapter
->netdev
->dev
,
629 "could not notify %s IP 0x%x reuqest\n",
630 (cmd
== QLCNIC_IP_UP
) ? "Add" : "Remove", ip
);
635 int qlcnic_linkevent_request(struct qlcnic_adapter
*adapter
, int enable
)
637 struct qlcnic_nic_req req
;
641 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
642 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
644 word
= QLCNIC_H2C_OPCODE_GET_LINKEVENT
| ((u64
)adapter
->portnum
<< 16);
645 req
.req_hdr
= cpu_to_le64(word
);
646 req
.words
[0] = cpu_to_le64(enable
| (enable
<< 8));
648 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
650 dev_err(&adapter
->netdev
->dev
,
651 "could not configure link notification\n");
656 int qlcnic_send_lro_cleanup(struct qlcnic_adapter
*adapter
)
658 struct qlcnic_nic_req req
;
662 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
663 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
665 word
= QLCNIC_H2C_OPCODE_LRO_REQUEST
|
666 ((u64
)adapter
->portnum
<< 16) |
667 ((u64
)QLCNIC_LRO_REQUEST_CLEANUP
<< 56) ;
669 req
.req_hdr
= cpu_to_le64(word
);
671 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
673 dev_err(&adapter
->netdev
->dev
,
674 "could not cleanup lro flows\n");
680 * qlcnic_change_mtu - Change the Maximum Transfer Unit
681 * @returns 0 on success, negative on failure
684 int qlcnic_change_mtu(struct net_device
*netdev
, int mtu
)
686 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
689 if (mtu
> P3_MAX_MTU
) {
690 dev_err(&adapter
->netdev
->dev
, "mtu > %d bytes unsupported\n",
695 rc
= qlcnic_fw_cmd_set_mtu(adapter
, mtu
);
703 int qlcnic_get_mac_addr(struct qlcnic_adapter
*adapter
, u64
*mac
)
705 u32 crbaddr
, mac_hi
, mac_lo
;
706 int pci_func
= adapter
->ahw
.pci_func
;
708 crbaddr
= CRB_MAC_BLOCK_START
+
709 (4 * ((pci_func
/2) * 3)) + (4 * (pci_func
& 1));
711 mac_lo
= QLCRD32(adapter
, crbaddr
);
712 mac_hi
= QLCRD32(adapter
, crbaddr
+4);
715 *mac
= le64_to_cpu((mac_lo
>> 16) | ((u64
)mac_hi
<< 16));
717 *mac
= le64_to_cpu((u64
)mac_lo
| ((u64
)mac_hi
<< 32));
723 * Changes the CRB window to the specified window.
725 /* Returns < 0 if off is not valid,
726 * 1 if window access is needed. 'off' is set to offset from
727 * CRB space in 128M pci map
728 * 0 if no window access is needed. 'off' is set to 2M addr
729 * In: 'off' is offset from base in 128M pci map
732 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter
*adapter
,
733 ulong off
, void __iomem
**addr
)
735 const struct crb_128M_2M_sub_block_map
*m
;
737 if ((off
>= QLCNIC_CRB_MAX
) || (off
< QLCNIC_PCI_CRBSPACE
))
740 off
-= QLCNIC_PCI_CRBSPACE
;
745 m
= &crb_128M_2M_map
[CRB_BLK(off
)].sub_block
[CRB_SUBBLK(off
)];
747 if (m
->valid
&& (m
->start_128M
<= off
) && (m
->end_128M
> off
)) {
748 *addr
= adapter
->ahw
.pci_base0
+ m
->start_2M
+
749 (off
- m
->start_128M
);
754 * Not in direct map, use crb window
756 *addr
= adapter
->ahw
.pci_base0
+ CRB_INDIRECT_2M
+ (off
& MASK(16));
761 * In: 'off' is offset from CRB space in 128M pci map
762 * Out: 'off' is 2M pci map addr
763 * side effect: lock crb window
766 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter
*adapter
, ulong off
)
769 void __iomem
*addr
= adapter
->ahw
.pci_base0
+ CRB_WINDOW_2M
;
771 off
-= QLCNIC_PCI_CRBSPACE
;
773 window
= CRB_HI(off
);
775 if (adapter
->ahw
.crb_win
== window
)
778 writel(window
, addr
);
779 if (readl(addr
) != window
) {
780 if (printk_ratelimit())
781 dev_warn(&adapter
->pdev
->dev
,
782 "failed to set CRB window to %d off 0x%lx\n",
785 adapter
->ahw
.crb_win
= window
;
789 qlcnic_hw_write_wx_2M(struct qlcnic_adapter
*adapter
, ulong off
, u32 data
)
793 void __iomem
*addr
= NULL
;
795 rv
= qlcnic_pci_get_crb_addr_2M(adapter
, off
, &addr
);
803 /* indirect access */
804 write_lock_irqsave(&adapter
->ahw
.crb_lock
, flags
);
805 crb_win_lock(adapter
);
806 qlcnic_pci_set_crbwindow_2M(adapter
, off
);
808 crb_win_unlock(adapter
);
809 write_unlock_irqrestore(&adapter
->ahw
.crb_lock
, flags
);
813 dev_err(&adapter
->pdev
->dev
,
814 "%s: invalid offset: 0x%016lx\n", __func__
, off
);
820 qlcnic_hw_read_wx_2M(struct qlcnic_adapter
*adapter
, ulong off
)
825 void __iomem
*addr
= NULL
;
827 rv
= qlcnic_pci_get_crb_addr_2M(adapter
, off
, &addr
);
833 /* indirect access */
834 write_lock_irqsave(&adapter
->ahw
.crb_lock
, flags
);
835 crb_win_lock(adapter
);
836 qlcnic_pci_set_crbwindow_2M(adapter
, off
);
838 crb_win_unlock(adapter
);
839 write_unlock_irqrestore(&adapter
->ahw
.crb_lock
, flags
);
843 dev_err(&adapter
->pdev
->dev
,
844 "%s: invalid offset: 0x%016lx\n", __func__
, off
);
851 qlcnic_get_ioaddr(struct qlcnic_adapter
*adapter
, u32 offset
)
853 void __iomem
*addr
= NULL
;
855 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter
, offset
, &addr
));
862 qlcnic_pci_set_window_2M(struct qlcnic_adapter
*adapter
,
863 u64 addr
, u32
*start
)
867 window
= OCM_WIN_P3P(addr
);
869 writel(window
, adapter
->ahw
.ocm_win_crb
);
870 /* read back to flush */
871 readl(adapter
->ahw
.ocm_win_crb
);
873 adapter
->ahw
.ocm_win
= window
;
874 *start
= QLCNIC_PCI_OCM0_2M
+ GET_MEM_OFFS_2M(addr
);
879 qlcnic_pci_mem_access_direct(struct qlcnic_adapter
*adapter
, u64 off
,
886 mutex_lock(&adapter
->ahw
.mem_lock
);
888 ret
= qlcnic_pci_set_window_2M(adapter
, off
, &start
);
892 addr
= adapter
->ahw
.pci_base0
+ start
;
894 if (op
== 0) /* read */
900 mutex_unlock(&adapter
->ahw
.mem_lock
);
906 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter
*adapter
, u64 off
, u64
*data
)
908 void __iomem
*addr
= adapter
->ahw
.pci_base0
+
909 QLCNIC_PCI_CAMQM_2M_BASE
+ (off
- QLCNIC_PCI_CAMQM
);
911 mutex_lock(&adapter
->ahw
.mem_lock
);
913 mutex_unlock(&adapter
->ahw
.mem_lock
);
917 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter
*adapter
, u64 off
, u64 data
)
919 void __iomem
*addr
= adapter
->ahw
.pci_base0
+
920 QLCNIC_PCI_CAMQM_2M_BASE
+ (off
- QLCNIC_PCI_CAMQM
);
922 mutex_lock(&adapter
->ahw
.mem_lock
);
924 mutex_unlock(&adapter
->ahw
.mem_lock
);
927 #define MAX_CTL_CHECK 1000
930 qlcnic_pci_mem_write_2M(struct qlcnic_adapter
*adapter
,
935 void __iomem
*mem_crb
;
937 /* Only 64-bit aligned access */
941 /* P3 onward, test agent base for MIU and SIU is same */
942 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_QDR_NET
,
943 QLCNIC_ADDR_QDR_NET_MAX
)) {
944 mem_crb
= qlcnic_get_ioaddr(adapter
,
945 QLCNIC_CRB_QDR_NET
+MIU_TEST_AGT_BASE
);
949 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_DDR_NET
, QLCNIC_ADDR_DDR_NET_MAX
)) {
950 mem_crb
= qlcnic_get_ioaddr(adapter
,
951 QLCNIC_CRB_DDR_NET
+MIU_TEST_AGT_BASE
);
955 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_OCM0
, QLCNIC_ADDR_OCM0_MAX
))
956 return qlcnic_pci_mem_access_direct(adapter
, off
, &data
, 1);
963 mutex_lock(&adapter
->ahw
.mem_lock
);
965 writel(off8
, (mem_crb
+ MIU_TEST_AGT_ADDR_LO
));
966 writel(0, (mem_crb
+ MIU_TEST_AGT_ADDR_HI
));
969 writel(TA_CTL_ENABLE
, (mem_crb
+ TEST_AGT_CTRL
));
970 writel((TA_CTL_START
| TA_CTL_ENABLE
),
971 (mem_crb
+ TEST_AGT_CTRL
));
973 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
974 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
975 if ((temp
& TA_CTL_BUSY
) == 0)
979 if (j
>= MAX_CTL_CHECK
) {
984 i
= (off
& 0xf) ? 0 : 2;
985 writel(readl(mem_crb
+ MIU_TEST_AGT_RDDATA(i
)),
986 mem_crb
+ MIU_TEST_AGT_WRDATA(i
));
987 writel(readl(mem_crb
+ MIU_TEST_AGT_RDDATA(i
+1)),
988 mem_crb
+ MIU_TEST_AGT_WRDATA(i
+1));
989 i
= (off
& 0xf) ? 2 : 0;
991 writel(data
& 0xffffffff,
992 mem_crb
+ MIU_TEST_AGT_WRDATA(i
));
993 writel((data
>> 32) & 0xffffffff,
994 mem_crb
+ MIU_TEST_AGT_WRDATA(i
+1));
996 writel((TA_CTL_ENABLE
| TA_CTL_WRITE
), (mem_crb
+ TEST_AGT_CTRL
));
997 writel((TA_CTL_START
| TA_CTL_ENABLE
| TA_CTL_WRITE
),
998 (mem_crb
+ TEST_AGT_CTRL
));
1000 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1001 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
1002 if ((temp
& TA_CTL_BUSY
) == 0)
1006 if (j
>= MAX_CTL_CHECK
) {
1007 if (printk_ratelimit())
1008 dev_err(&adapter
->pdev
->dev
,
1009 "failed to write through agent\n");
1015 mutex_unlock(&adapter
->ahw
.mem_lock
);
1021 qlcnic_pci_mem_read_2M(struct qlcnic_adapter
*adapter
,
1027 void __iomem
*mem_crb
;
1029 /* Only 64-bit aligned access */
1033 /* P3 onward, test agent base for MIU and SIU is same */
1034 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_QDR_NET
,
1035 QLCNIC_ADDR_QDR_NET_MAX
)) {
1036 mem_crb
= qlcnic_get_ioaddr(adapter
,
1037 QLCNIC_CRB_QDR_NET
+MIU_TEST_AGT_BASE
);
1041 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_DDR_NET
, QLCNIC_ADDR_DDR_NET_MAX
)) {
1042 mem_crb
= qlcnic_get_ioaddr(adapter
,
1043 QLCNIC_CRB_DDR_NET
+MIU_TEST_AGT_BASE
);
1047 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_OCM0
, QLCNIC_ADDR_OCM0_MAX
)) {
1048 return qlcnic_pci_mem_access_direct(adapter
,
1057 mutex_lock(&adapter
->ahw
.mem_lock
);
1059 writel(off8
, (mem_crb
+ MIU_TEST_AGT_ADDR_LO
));
1060 writel(0, (mem_crb
+ MIU_TEST_AGT_ADDR_HI
));
1061 writel(TA_CTL_ENABLE
, (mem_crb
+ TEST_AGT_CTRL
));
1062 writel((TA_CTL_START
| TA_CTL_ENABLE
), (mem_crb
+ TEST_AGT_CTRL
));
1064 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1065 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
1066 if ((temp
& TA_CTL_BUSY
) == 0)
1070 if (j
>= MAX_CTL_CHECK
) {
1071 if (printk_ratelimit())
1072 dev_err(&adapter
->pdev
->dev
,
1073 "failed to read through agent\n");
1076 off8
= MIU_TEST_AGT_RDDATA_LO
;
1078 off8
= MIU_TEST_AGT_RDDATA_UPPER_LO
;
1080 temp
= readl(mem_crb
+ off8
+ 4);
1081 val
= (u64
)temp
<< 32;
1082 val
|= readl(mem_crb
+ off8
);
1087 mutex_unlock(&adapter
->ahw
.mem_lock
);
1092 int qlcnic_get_board_info(struct qlcnic_adapter
*adapter
)
1094 int offset
, board_type
, magic
;
1095 struct pci_dev
*pdev
= adapter
->pdev
;
1097 offset
= QLCNIC_FW_MAGIC_OFFSET
;
1098 if (qlcnic_rom_fast_read(adapter
, offset
, &magic
))
1101 if (magic
!= QLCNIC_BDINFO_MAGIC
) {
1102 dev_err(&pdev
->dev
, "invalid board config, magic=%08x\n",
1107 offset
= QLCNIC_BRDTYPE_OFFSET
;
1108 if (qlcnic_rom_fast_read(adapter
, offset
, &board_type
))
1111 adapter
->ahw
.board_type
= board_type
;
1113 if (board_type
== QLCNIC_BRDTYPE_P3_4_GB_MM
) {
1114 u32 gpio
= QLCRD32(adapter
, QLCNIC_ROMUSB_GLB_PAD_GPIO_I
);
1115 if ((gpio
& 0x8000) == 0)
1116 board_type
= QLCNIC_BRDTYPE_P3_10G_TP
;
1119 switch (board_type
) {
1120 case QLCNIC_BRDTYPE_P3_HMEZ
:
1121 case QLCNIC_BRDTYPE_P3_XG_LOM
:
1122 case QLCNIC_BRDTYPE_P3_10G_CX4
:
1123 case QLCNIC_BRDTYPE_P3_10G_CX4_LP
:
1124 case QLCNIC_BRDTYPE_P3_IMEZ
:
1125 case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS
:
1126 case QLCNIC_BRDTYPE_P3_10G_SFP_CT
:
1127 case QLCNIC_BRDTYPE_P3_10G_SFP_QT
:
1128 case QLCNIC_BRDTYPE_P3_10G_XFP
:
1129 case QLCNIC_BRDTYPE_P3_10000_BASE_T
:
1130 adapter
->ahw
.port_type
= QLCNIC_XGBE
;
1132 case QLCNIC_BRDTYPE_P3_REF_QG
:
1133 case QLCNIC_BRDTYPE_P3_4_GB
:
1134 case QLCNIC_BRDTYPE_P3_4_GB_MM
:
1135 adapter
->ahw
.port_type
= QLCNIC_GBE
;
1137 case QLCNIC_BRDTYPE_P3_10G_TP
:
1138 adapter
->ahw
.port_type
= (adapter
->portnum
< 2) ?
1139 QLCNIC_XGBE
: QLCNIC_GBE
;
1142 dev_err(&pdev
->dev
, "unknown board type %x\n", board_type
);
1143 adapter
->ahw
.port_type
= QLCNIC_XGBE
;
1151 qlcnic_wol_supported(struct qlcnic_adapter
*adapter
)
1155 wol_cfg
= QLCRD32(adapter
, QLCNIC_WOL_CONFIG_NV
);
1156 if (wol_cfg
& (1UL << adapter
->portnum
)) {
1157 wol_cfg
= QLCRD32(adapter
, QLCNIC_WOL_CONFIG
);
1158 if (wol_cfg
& (1 << adapter
->portnum
))
1165 int qlcnic_config_led(struct qlcnic_adapter
*adapter
, u32 state
, u32 rate
)
1167 struct qlcnic_nic_req req
;
1171 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
1172 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
1174 word
= QLCNIC_H2C_OPCODE_CONFIG_LED
| ((u64
)adapter
->portnum
<< 16);
1175 req
.req_hdr
= cpu_to_le64(word
);
1177 req
.words
[0] = cpu_to_le64((u64
)rate
<< 32);
1178 req
.words
[1] = cpu_to_le64(state
);
1180 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
1182 dev_err(&adapter
->pdev
->dev
, "LED configuration failed.\n");
1187 static int qlcnic_set_fw_loopback(struct qlcnic_adapter
*adapter
, u32 flag
)
1189 struct qlcnic_nic_req req
;
1193 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
1194 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
1196 word
= QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK
|
1197 ((u64
)adapter
->portnum
<< 16);
1198 req
.req_hdr
= cpu_to_le64(word
);
1199 req
.words
[0] = cpu_to_le64(flag
);
1201 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
1203 dev_err(&adapter
->pdev
->dev
,
1204 "%sting loopback mode failed.\n",
1205 flag
? "Set" : "Reset");
1209 int qlcnic_set_ilb_mode(struct qlcnic_adapter
*adapter
)
1211 if (qlcnic_set_fw_loopback(adapter
, 1))
1214 if (qlcnic_nic_set_promisc(adapter
,
1215 VPORT_MISS_MODE_ACCEPT_ALL
)) {
1216 qlcnic_set_fw_loopback(adapter
, 0);
1224 void qlcnic_clear_ilb_mode(struct qlcnic_adapter
*adapter
)
1226 int mode
= VPORT_MISS_MODE_DROP
;
1227 struct net_device
*netdev
= adapter
->netdev
;
1229 qlcnic_set_fw_loopback(adapter
, 0);
1231 if (netdev
->flags
& IFF_PROMISC
)
1232 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
1233 else if (netdev
->flags
& IFF_ALLMULTI
)
1234 mode
= VPORT_MISS_MODE_ACCEPT_MULTI
;
1236 qlcnic_nic_set_promisc(adapter
, mode
);