2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
27 #include <linux/slab.h>
30 #define MASK(n) ((1ULL<<(n))-1)
31 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
33 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
35 #define CRB_BLK(off) ((off >> 20) & 0x3f)
36 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
37 #define CRB_WINDOW_2M (0x130060)
38 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
39 #define CRB_INDIRECT_2M (0x1e0000UL)
43 static inline u64
readq(void __iomem
*addr
)
45 return readl(addr
) | (((u64
) readl(addr
+ 4)) << 32LL);
50 static inline void writeq(u64 val
, void __iomem
*addr
)
52 writel(((u32
) (val
)), (addr
));
53 writel(((u32
) (val
>> 32)), (addr
+ 4));
57 static const struct crb_128M_2M_block_map
58 crb_128M_2M_map
[64] __cacheline_aligned_in_smp
= {
59 {{{0, 0, 0, 0} } }, /* 0: PCI */
60 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
61 {1, 0x0110000, 0x0120000, 0x130000},
62 {1, 0x0120000, 0x0122000, 0x124000},
63 {1, 0x0130000, 0x0132000, 0x126000},
64 {1, 0x0140000, 0x0142000, 0x128000},
65 {1, 0x0150000, 0x0152000, 0x12a000},
66 {1, 0x0160000, 0x0170000, 0x110000},
67 {1, 0x0170000, 0x0172000, 0x12e000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {0, 0x0000000, 0x0000000, 0x000000},
72 {0, 0x0000000, 0x0000000, 0x000000},
73 {0, 0x0000000, 0x0000000, 0x000000},
74 {1, 0x01e0000, 0x01e0800, 0x122000},
75 {0, 0x0000000, 0x0000000, 0x000000} } },
76 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
77 {{{0, 0, 0, 0} } }, /* 3: */
78 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
79 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
80 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
81 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
82 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {1, 0x08f0000, 0x08f2000, 0x172000} } },
98 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {1, 0x09f0000, 0x09f2000, 0x176000} } },
114 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
130 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
146 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
147 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
148 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
149 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
150 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
151 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
152 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
153 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
154 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
155 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
156 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
157 {{{0, 0, 0, 0} } }, /* 23: */
158 {{{0, 0, 0, 0} } }, /* 24: */
159 {{{0, 0, 0, 0} } }, /* 25: */
160 {{{0, 0, 0, 0} } }, /* 26: */
161 {{{0, 0, 0, 0} } }, /* 27: */
162 {{{0, 0, 0, 0} } }, /* 28: */
163 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
164 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
165 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
166 {{{0} } }, /* 32: PCI */
167 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
168 {1, 0x2110000, 0x2120000, 0x130000},
169 {1, 0x2120000, 0x2122000, 0x124000},
170 {1, 0x2130000, 0x2132000, 0x126000},
171 {1, 0x2140000, 0x2142000, 0x128000},
172 {1, 0x2150000, 0x2152000, 0x12a000},
173 {1, 0x2160000, 0x2170000, 0x110000},
174 {1, 0x2170000, 0x2172000, 0x12e000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000} } },
183 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
189 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
190 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
191 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
192 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
193 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
194 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
195 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
196 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
197 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
198 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
199 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
200 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
202 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
203 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
204 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
205 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
206 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
207 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
208 {{{0} } }, /* 59: I2C0 */
209 {{{0} } }, /* 60: I2C1 */
210 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
211 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
212 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
216 * top 12 bits of crb internal address (hub, agent)
218 static const unsigned crb_hub_agt
[64] = {
220 QLCNIC_HW_CRB_HUB_AGT_ADR_PS
,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_MN
,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_MS
,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE
,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU
,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN
,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0
,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1
,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2
,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3
,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q
,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR
,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB
,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4
,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA
,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0
,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1
,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2
,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3
,
240 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND
,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI
,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0
,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1
,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2
,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3
,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI
,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_SN
,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_EG
,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_PS
,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM
,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR
,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1
,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2
,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3
,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4
,
265 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5
,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6
,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7
,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA
,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q
,
270 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB
,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0
,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8
,
274 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9
,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0
,
277 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB
,
278 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0
,
279 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1
,
281 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC
,
285 /* PCI Windowing for DDR regions. */
287 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
290 qlcnic_pcie_sem_lock(struct qlcnic_adapter
*adapter
, int sem
, u32 id_reg
)
292 int done
= 0, timeout
= 0;
295 done
= QLCRD32(adapter
, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem
)));
298 if (++timeout
>= QLCNIC_PCIE_SEM_TIMEOUT
) {
299 dev_err(&adapter
->pdev
->dev
,
300 "Failed to acquire sem=%d lock;reg_id=%d\n",
308 QLCWR32(adapter
, id_reg
, adapter
->portnum
);
314 qlcnic_pcie_sem_unlock(struct qlcnic_adapter
*adapter
, int sem
)
316 QLCRD32(adapter
, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem
)));
320 qlcnic_send_cmd_descs(struct qlcnic_adapter
*adapter
,
321 struct cmd_desc_type0
*cmd_desc_arr
, int nr_desc
)
323 u32 i
, producer
, consumer
;
324 struct qlcnic_cmd_buffer
*pbuf
;
325 struct cmd_desc_type0
*cmd_desc
;
326 struct qlcnic_host_tx_ring
*tx_ring
;
330 if (!test_bit(__QLCNIC_FW_ATTACHED
, &adapter
->state
))
333 tx_ring
= adapter
->tx_ring
;
334 __netif_tx_lock_bh(tx_ring
->txq
);
336 producer
= tx_ring
->producer
;
337 consumer
= tx_ring
->sw_consumer
;
339 if (nr_desc
>= qlcnic_tx_avail(tx_ring
)) {
340 netif_tx_stop_queue(tx_ring
->txq
);
342 if (qlcnic_tx_avail(tx_ring
) > nr_desc
) {
343 if (qlcnic_tx_avail(tx_ring
) > TX_STOP_THRESH
)
344 netif_tx_wake_queue(tx_ring
->txq
);
346 adapter
->stats
.xmit_off
++;
347 __netif_tx_unlock_bh(tx_ring
->txq
);
353 cmd_desc
= &cmd_desc_arr
[i
];
355 pbuf
= &tx_ring
->cmd_buf_arr
[producer
];
357 pbuf
->frag_count
= 0;
359 memcpy(&tx_ring
->desc_head
[producer
],
360 &cmd_desc_arr
[i
], sizeof(struct cmd_desc_type0
));
362 producer
= get_next_index(producer
, tx_ring
->num_desc
);
365 } while (i
!= nr_desc
);
367 tx_ring
->producer
= producer
;
369 qlcnic_update_cmd_producer(adapter
, tx_ring
);
371 __netif_tx_unlock_bh(tx_ring
->txq
);
377 qlcnic_sre_macaddr_change(struct qlcnic_adapter
*adapter
, u8
*addr
,
380 struct qlcnic_nic_req req
;
381 struct qlcnic_mac_req
*mac_req
;
384 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
385 req
.qhdr
= cpu_to_le64(QLCNIC_REQUEST
<< 23);
387 word
= QLCNIC_MAC_EVENT
| ((u64
)adapter
->portnum
<< 16);
388 req
.req_hdr
= cpu_to_le64(word
);
390 mac_req
= (struct qlcnic_mac_req
*)&req
.words
[0];
392 memcpy(mac_req
->mac_addr
, addr
, 6);
394 return qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
397 static int qlcnic_nic_add_mac(struct qlcnic_adapter
*adapter
, u8
*addr
)
399 struct list_head
*head
;
400 struct qlcnic_mac_list_s
*cur
;
402 /* look up if already exists */
403 list_for_each(head
, &adapter
->mac_list
) {
404 cur
= list_entry(head
, struct qlcnic_mac_list_s
, list
);
405 if (memcmp(addr
, cur
->mac_addr
, ETH_ALEN
) == 0)
409 cur
= kzalloc(sizeof(struct qlcnic_mac_list_s
), GFP_ATOMIC
);
411 dev_err(&adapter
->netdev
->dev
,
412 "failed to add mac address filter\n");
415 memcpy(cur
->mac_addr
, addr
, ETH_ALEN
);
417 if (qlcnic_sre_macaddr_change(adapter
,
418 cur
->mac_addr
, QLCNIC_MAC_ADD
)) {
423 list_add_tail(&cur
->list
, &adapter
->mac_list
);
427 void qlcnic_set_multi(struct net_device
*netdev
)
429 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
430 struct netdev_hw_addr
*ha
;
431 u8 bcast_addr
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
432 u32 mode
= VPORT_MISS_MODE_DROP
;
434 if (!test_bit(__QLCNIC_FW_ATTACHED
, &adapter
->state
))
437 qlcnic_nic_add_mac(adapter
, adapter
->mac_addr
);
438 qlcnic_nic_add_mac(adapter
, bcast_addr
);
440 if (netdev
->flags
& IFF_PROMISC
) {
441 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
445 if ((netdev
->flags
& IFF_ALLMULTI
) ||
446 (netdev_mc_count(netdev
) > adapter
->max_mc_count
)) {
447 mode
= VPORT_MISS_MODE_ACCEPT_MULTI
;
451 if (!netdev_mc_empty(netdev
)) {
452 netdev_for_each_mc_addr(ha
, netdev
) {
453 qlcnic_nic_add_mac(adapter
, ha
->addr
);
458 qlcnic_nic_set_promisc(adapter
, mode
);
461 int qlcnic_nic_set_promisc(struct qlcnic_adapter
*adapter
, u32 mode
)
463 struct qlcnic_nic_req req
;
466 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
468 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
470 word
= QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE
|
471 ((u64
)adapter
->portnum
<< 16);
472 req
.req_hdr
= cpu_to_le64(word
);
474 req
.words
[0] = cpu_to_le64(mode
);
476 return qlcnic_send_cmd_descs(adapter
,
477 (struct cmd_desc_type0
*)&req
, 1);
480 void qlcnic_free_mac_list(struct qlcnic_adapter
*adapter
)
482 struct qlcnic_mac_list_s
*cur
;
483 struct list_head
*head
= &adapter
->mac_list
;
485 while (!list_empty(head
)) {
486 cur
= list_entry(head
->next
, struct qlcnic_mac_list_s
, list
);
487 qlcnic_sre_macaddr_change(adapter
,
488 cur
->mac_addr
, QLCNIC_MAC_DEL
);
489 list_del(&cur
->list
);
494 #define QLCNIC_CONFIG_INTR_COALESCE 3
497 * Send the interrupt coalescing parameter set by ethtool to the card.
499 int qlcnic_config_intr_coalesce(struct qlcnic_adapter
*adapter
)
501 struct qlcnic_nic_req req
;
505 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
507 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
509 word
[0] = QLCNIC_CONFIG_INTR_COALESCE
| ((u64
)adapter
->portnum
<< 16);
510 req
.req_hdr
= cpu_to_le64(word
[0]);
512 memcpy(&word
[0], &adapter
->coal
, sizeof(adapter
->coal
));
513 for (i
= 0; i
< 6; i
++)
514 req
.words
[i
] = cpu_to_le64(word
[i
]);
516 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
518 dev_err(&adapter
->netdev
->dev
,
519 "Could not send interrupt coalescing parameters\n");
524 int qlcnic_config_hw_lro(struct qlcnic_adapter
*adapter
, int enable
)
526 struct qlcnic_nic_req req
;
530 if ((adapter
->flags
& QLCNIC_LRO_ENABLED
) == enable
)
533 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
535 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
537 word
= QLCNIC_H2C_OPCODE_CONFIG_HW_LRO
| ((u64
)adapter
->portnum
<< 16);
538 req
.req_hdr
= cpu_to_le64(word
);
540 req
.words
[0] = cpu_to_le64(enable
);
542 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
544 dev_err(&adapter
->netdev
->dev
,
545 "Could not send configure hw lro request\n");
547 adapter
->flags
^= QLCNIC_LRO_ENABLED
;
552 int qlcnic_config_bridged_mode(struct qlcnic_adapter
*adapter
, u32 enable
)
554 struct qlcnic_nic_req req
;
558 if (!!(adapter
->flags
& QLCNIC_BRIDGE_ENABLED
) == enable
)
561 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
563 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
565 word
= QLCNIC_H2C_OPCODE_CONFIG_BRIDGING
|
566 ((u64
)adapter
->portnum
<< 16);
567 req
.req_hdr
= cpu_to_le64(word
);
569 req
.words
[0] = cpu_to_le64(enable
);
571 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
573 dev_err(&adapter
->netdev
->dev
,
574 "Could not send configure bridge mode request\n");
576 adapter
->flags
^= QLCNIC_BRIDGE_ENABLED
;
582 #define RSS_HASHTYPE_IP_TCP 0x3
584 int qlcnic_config_rss(struct qlcnic_adapter
*adapter
, int enable
)
586 struct qlcnic_nic_req req
;
590 const u64 key
[] = { 0xbeac01fa6a42b73bULL
, 0x8030f20c77cb2da3ULL
,
591 0xae7b30b4d0ca2bcbULL
, 0x43a38fb04167253dULL
,
592 0x255b0ec26d5a56daULL
};
595 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
596 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
598 word
= QLCNIC_H2C_OPCODE_CONFIG_RSS
| ((u64
)adapter
->portnum
<< 16);
599 req
.req_hdr
= cpu_to_le64(word
);
603 * bits 3-0: hash_method
604 * 5-4: hash_type_ipv4
605 * 7-6: hash_type_ipv6
607 * 9: use indirection table
609 * 63-48: indirection table mask
611 word
= ((u64
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 4) |
612 ((u64
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 6) |
613 ((u64
)(enable
& 0x1) << 8) |
615 req
.words
[0] = cpu_to_le64(word
);
616 for (i
= 0; i
< 5; i
++)
617 req
.words
[i
+1] = cpu_to_le64(key
[i
]);
619 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
621 dev_err(&adapter
->netdev
->dev
, "could not configure RSS\n");
626 int qlcnic_config_ipaddr(struct qlcnic_adapter
*adapter
, u32 ip
, int cmd
)
628 struct qlcnic_nic_req req
;
632 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
633 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
635 word
= QLCNIC_H2C_OPCODE_CONFIG_IPADDR
| ((u64
)adapter
->portnum
<< 16);
636 req
.req_hdr
= cpu_to_le64(word
);
638 req
.words
[0] = cpu_to_le64(cmd
);
639 req
.words
[1] = cpu_to_le64(ip
);
641 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
643 dev_err(&adapter
->netdev
->dev
,
644 "could not notify %s IP 0x%x reuqest\n",
645 (cmd
== QLCNIC_IP_UP
) ? "Add" : "Remove", ip
);
650 int qlcnic_linkevent_request(struct qlcnic_adapter
*adapter
, int enable
)
652 struct qlcnic_nic_req req
;
656 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
657 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
659 word
= QLCNIC_H2C_OPCODE_GET_LINKEVENT
| ((u64
)adapter
->portnum
<< 16);
660 req
.req_hdr
= cpu_to_le64(word
);
661 req
.words
[0] = cpu_to_le64(enable
| (enable
<< 8));
663 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
665 dev_err(&adapter
->netdev
->dev
,
666 "could not configure link notification\n");
671 int qlcnic_send_lro_cleanup(struct qlcnic_adapter
*adapter
)
673 struct qlcnic_nic_req req
;
677 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
678 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
680 word
= QLCNIC_H2C_OPCODE_LRO_REQUEST
|
681 ((u64
)adapter
->portnum
<< 16) |
682 ((u64
)QLCNIC_LRO_REQUEST_CLEANUP
<< 56) ;
684 req
.req_hdr
= cpu_to_le64(word
);
686 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
688 dev_err(&adapter
->netdev
->dev
,
689 "could not cleanup lro flows\n");
695 * qlcnic_change_mtu - Change the Maximum Transfer Unit
696 * @returns 0 on success, negative on failure
699 int qlcnic_change_mtu(struct net_device
*netdev
, int mtu
)
701 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
704 if (mtu
> P3_MAX_MTU
) {
705 dev_err(&adapter
->netdev
->dev
, "mtu > %d bytes unsupported\n",
710 rc
= qlcnic_fw_cmd_set_mtu(adapter
, mtu
);
718 int qlcnic_get_mac_addr(struct qlcnic_adapter
*adapter
, u8
*mac
)
721 int pci_func
= adapter
->ahw
.pci_func
;
723 crbaddr
= CRB_MAC_BLOCK_START
+
724 (4 * ((pci_func
/2) * 3)) + (4 * (pci_func
& 1));
726 qlcnic_fetch_mac(adapter
, crbaddr
, crbaddr
+4, pci_func
& 1, mac
);
732 * Changes the CRB window to the specified window.
734 /* Returns < 0 if off is not valid,
735 * 1 if window access is needed. 'off' is set to offset from
736 * CRB space in 128M pci map
737 * 0 if no window access is needed. 'off' is set to 2M addr
738 * In: 'off' is offset from base in 128M pci map
741 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter
*adapter
,
742 ulong off
, void __iomem
**addr
)
744 const struct crb_128M_2M_sub_block_map
*m
;
746 if ((off
>= QLCNIC_CRB_MAX
) || (off
< QLCNIC_PCI_CRBSPACE
))
749 off
-= QLCNIC_PCI_CRBSPACE
;
754 m
= &crb_128M_2M_map
[CRB_BLK(off
)].sub_block
[CRB_SUBBLK(off
)];
756 if (m
->valid
&& (m
->start_128M
<= off
) && (m
->end_128M
> off
)) {
757 *addr
= adapter
->ahw
.pci_base0
+ m
->start_2M
+
758 (off
- m
->start_128M
);
763 * Not in direct map, use crb window
765 *addr
= adapter
->ahw
.pci_base0
+ CRB_INDIRECT_2M
+ (off
& MASK(16));
770 * In: 'off' is offset from CRB space in 128M pci map
771 * Out: 'off' is 2M pci map addr
772 * side effect: lock crb window
775 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter
*adapter
, ulong off
)
778 void __iomem
*addr
= adapter
->ahw
.pci_base0
+ CRB_WINDOW_2M
;
780 off
-= QLCNIC_PCI_CRBSPACE
;
782 window
= CRB_HI(off
);
784 dev_err(&adapter
->pdev
->dev
, "Invalid offset 0x%lx\n", off
);
788 writel(window
, addr
);
789 if (readl(addr
) != window
) {
790 if (printk_ratelimit())
791 dev_warn(&adapter
->pdev
->dev
,
792 "failed to set CRB window to %d off 0x%lx\n",
800 qlcnic_hw_write_wx_2M(struct qlcnic_adapter
*adapter
, ulong off
, u32 data
)
804 void __iomem
*addr
= NULL
;
806 rv
= qlcnic_pci_get_crb_addr_2M(adapter
, off
, &addr
);
814 /* indirect access */
815 write_lock_irqsave(&adapter
->ahw
.crb_lock
, flags
);
816 crb_win_lock(adapter
);
817 rv
= qlcnic_pci_set_crbwindow_2M(adapter
, off
);
820 crb_win_unlock(adapter
);
821 write_unlock_irqrestore(&adapter
->ahw
.crb_lock
, flags
);
825 dev_err(&adapter
->pdev
->dev
,
826 "%s: invalid offset: 0x%016lx\n", __func__
, off
);
832 qlcnic_hw_read_wx_2M(struct qlcnic_adapter
*adapter
, ulong off
)
837 void __iomem
*addr
= NULL
;
839 rv
= qlcnic_pci_get_crb_addr_2M(adapter
, off
, &addr
);
845 /* indirect access */
846 write_lock_irqsave(&adapter
->ahw
.crb_lock
, flags
);
847 crb_win_lock(adapter
);
848 if (!qlcnic_pci_set_crbwindow_2M(adapter
, off
))
850 crb_win_unlock(adapter
);
851 write_unlock_irqrestore(&adapter
->ahw
.crb_lock
, flags
);
855 dev_err(&adapter
->pdev
->dev
,
856 "%s: invalid offset: 0x%016lx\n", __func__
, off
);
863 qlcnic_get_ioaddr(struct qlcnic_adapter
*adapter
, u32 offset
)
865 void __iomem
*addr
= NULL
;
867 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter
, offset
, &addr
));
874 qlcnic_pci_set_window_2M(struct qlcnic_adapter
*adapter
,
875 u64 addr
, u32
*start
)
879 window
= OCM_WIN_P3P(addr
);
881 writel(window
, adapter
->ahw
.ocm_win_crb
);
882 /* read back to flush */
883 readl(adapter
->ahw
.ocm_win_crb
);
885 *start
= QLCNIC_PCI_OCM0_2M
+ GET_MEM_OFFS_2M(addr
);
890 qlcnic_pci_mem_access_direct(struct qlcnic_adapter
*adapter
, u64 off
,
897 mutex_lock(&adapter
->ahw
.mem_lock
);
899 ret
= qlcnic_pci_set_window_2M(adapter
, off
, &start
);
903 addr
= adapter
->ahw
.pci_base0
+ start
;
905 if (op
== 0) /* read */
911 mutex_unlock(&adapter
->ahw
.mem_lock
);
917 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter
*adapter
, u64 off
, u64
*data
)
919 void __iomem
*addr
= adapter
->ahw
.pci_base0
+
920 QLCNIC_PCI_CAMQM_2M_BASE
+ (off
- QLCNIC_PCI_CAMQM
);
922 mutex_lock(&adapter
->ahw
.mem_lock
);
924 mutex_unlock(&adapter
->ahw
.mem_lock
);
928 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter
*adapter
, u64 off
, u64 data
)
930 void __iomem
*addr
= adapter
->ahw
.pci_base0
+
931 QLCNIC_PCI_CAMQM_2M_BASE
+ (off
- QLCNIC_PCI_CAMQM
);
933 mutex_lock(&adapter
->ahw
.mem_lock
);
935 mutex_unlock(&adapter
->ahw
.mem_lock
);
938 #define MAX_CTL_CHECK 1000
941 qlcnic_pci_mem_write_2M(struct qlcnic_adapter
*adapter
,
946 void __iomem
*mem_crb
;
948 /* Only 64-bit aligned access */
952 /* P3 onward, test agent base for MIU and SIU is same */
953 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_QDR_NET
,
954 QLCNIC_ADDR_QDR_NET_MAX
)) {
955 mem_crb
= qlcnic_get_ioaddr(adapter
,
956 QLCNIC_CRB_QDR_NET
+MIU_TEST_AGT_BASE
);
960 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_DDR_NET
, QLCNIC_ADDR_DDR_NET_MAX
)) {
961 mem_crb
= qlcnic_get_ioaddr(adapter
,
962 QLCNIC_CRB_DDR_NET
+MIU_TEST_AGT_BASE
);
966 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_OCM0
, QLCNIC_ADDR_OCM0_MAX
))
967 return qlcnic_pci_mem_access_direct(adapter
, off
, &data
, 1);
974 mutex_lock(&adapter
->ahw
.mem_lock
);
976 writel(off8
, (mem_crb
+ MIU_TEST_AGT_ADDR_LO
));
977 writel(0, (mem_crb
+ MIU_TEST_AGT_ADDR_HI
));
980 writel(TA_CTL_ENABLE
, (mem_crb
+ TEST_AGT_CTRL
));
981 writel((TA_CTL_START
| TA_CTL_ENABLE
),
982 (mem_crb
+ TEST_AGT_CTRL
));
984 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
985 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
986 if ((temp
& TA_CTL_BUSY
) == 0)
990 if (j
>= MAX_CTL_CHECK
) {
995 i
= (off
& 0xf) ? 0 : 2;
996 writel(readl(mem_crb
+ MIU_TEST_AGT_RDDATA(i
)),
997 mem_crb
+ MIU_TEST_AGT_WRDATA(i
));
998 writel(readl(mem_crb
+ MIU_TEST_AGT_RDDATA(i
+1)),
999 mem_crb
+ MIU_TEST_AGT_WRDATA(i
+1));
1000 i
= (off
& 0xf) ? 2 : 0;
1002 writel(data
& 0xffffffff,
1003 mem_crb
+ MIU_TEST_AGT_WRDATA(i
));
1004 writel((data
>> 32) & 0xffffffff,
1005 mem_crb
+ MIU_TEST_AGT_WRDATA(i
+1));
1007 writel((TA_CTL_ENABLE
| TA_CTL_WRITE
), (mem_crb
+ TEST_AGT_CTRL
));
1008 writel((TA_CTL_START
| TA_CTL_ENABLE
| TA_CTL_WRITE
),
1009 (mem_crb
+ TEST_AGT_CTRL
));
1011 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1012 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
1013 if ((temp
& TA_CTL_BUSY
) == 0)
1017 if (j
>= MAX_CTL_CHECK
) {
1018 if (printk_ratelimit())
1019 dev_err(&adapter
->pdev
->dev
,
1020 "failed to write through agent\n");
1026 mutex_unlock(&adapter
->ahw
.mem_lock
);
1032 qlcnic_pci_mem_read_2M(struct qlcnic_adapter
*adapter
,
1038 void __iomem
*mem_crb
;
1040 /* Only 64-bit aligned access */
1044 /* P3 onward, test agent base for MIU and SIU is same */
1045 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_QDR_NET
,
1046 QLCNIC_ADDR_QDR_NET_MAX
)) {
1047 mem_crb
= qlcnic_get_ioaddr(adapter
,
1048 QLCNIC_CRB_QDR_NET
+MIU_TEST_AGT_BASE
);
1052 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_DDR_NET
, QLCNIC_ADDR_DDR_NET_MAX
)) {
1053 mem_crb
= qlcnic_get_ioaddr(adapter
,
1054 QLCNIC_CRB_DDR_NET
+MIU_TEST_AGT_BASE
);
1058 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_OCM0
, QLCNIC_ADDR_OCM0_MAX
)) {
1059 return qlcnic_pci_mem_access_direct(adapter
,
1068 mutex_lock(&adapter
->ahw
.mem_lock
);
1070 writel(off8
, (mem_crb
+ MIU_TEST_AGT_ADDR_LO
));
1071 writel(0, (mem_crb
+ MIU_TEST_AGT_ADDR_HI
));
1072 writel(TA_CTL_ENABLE
, (mem_crb
+ TEST_AGT_CTRL
));
1073 writel((TA_CTL_START
| TA_CTL_ENABLE
), (mem_crb
+ TEST_AGT_CTRL
));
1075 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1076 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
1077 if ((temp
& TA_CTL_BUSY
) == 0)
1081 if (j
>= MAX_CTL_CHECK
) {
1082 if (printk_ratelimit())
1083 dev_err(&adapter
->pdev
->dev
,
1084 "failed to read through agent\n");
1087 off8
= MIU_TEST_AGT_RDDATA_LO
;
1089 off8
= MIU_TEST_AGT_RDDATA_UPPER_LO
;
1091 temp
= readl(mem_crb
+ off8
+ 4);
1092 val
= (u64
)temp
<< 32;
1093 val
|= readl(mem_crb
+ off8
);
1098 mutex_unlock(&adapter
->ahw
.mem_lock
);
1103 int qlcnic_get_board_info(struct qlcnic_adapter
*adapter
)
1105 int offset
, board_type
, magic
;
1106 struct pci_dev
*pdev
= adapter
->pdev
;
1108 offset
= QLCNIC_FW_MAGIC_OFFSET
;
1109 if (qlcnic_rom_fast_read(adapter
, offset
, &magic
))
1112 if (magic
!= QLCNIC_BDINFO_MAGIC
) {
1113 dev_err(&pdev
->dev
, "invalid board config, magic=%08x\n",
1118 offset
= QLCNIC_BRDTYPE_OFFSET
;
1119 if (qlcnic_rom_fast_read(adapter
, offset
, &board_type
))
1122 adapter
->ahw
.board_type
= board_type
;
1124 if (board_type
== QLCNIC_BRDTYPE_P3_4_GB_MM
) {
1125 u32 gpio
= QLCRD32(adapter
, QLCNIC_ROMUSB_GLB_PAD_GPIO_I
);
1126 if ((gpio
& 0x8000) == 0)
1127 board_type
= QLCNIC_BRDTYPE_P3_10G_TP
;
1130 switch (board_type
) {
1131 case QLCNIC_BRDTYPE_P3_HMEZ
:
1132 case QLCNIC_BRDTYPE_P3_XG_LOM
:
1133 case QLCNIC_BRDTYPE_P3_10G_CX4
:
1134 case QLCNIC_BRDTYPE_P3_10G_CX4_LP
:
1135 case QLCNIC_BRDTYPE_P3_IMEZ
:
1136 case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS
:
1137 case QLCNIC_BRDTYPE_P3_10G_SFP_CT
:
1138 case QLCNIC_BRDTYPE_P3_10G_SFP_QT
:
1139 case QLCNIC_BRDTYPE_P3_10G_XFP
:
1140 case QLCNIC_BRDTYPE_P3_10000_BASE_T
:
1141 adapter
->ahw
.port_type
= QLCNIC_XGBE
;
1143 case QLCNIC_BRDTYPE_P3_REF_QG
:
1144 case QLCNIC_BRDTYPE_P3_4_GB
:
1145 case QLCNIC_BRDTYPE_P3_4_GB_MM
:
1146 adapter
->ahw
.port_type
= QLCNIC_GBE
;
1148 case QLCNIC_BRDTYPE_P3_10G_TP
:
1149 adapter
->ahw
.port_type
= (adapter
->portnum
< 2) ?
1150 QLCNIC_XGBE
: QLCNIC_GBE
;
1153 dev_err(&pdev
->dev
, "unknown board type %x\n", board_type
);
1154 adapter
->ahw
.port_type
= QLCNIC_XGBE
;
1162 qlcnic_wol_supported(struct qlcnic_adapter
*adapter
)
1166 wol_cfg
= QLCRD32(adapter
, QLCNIC_WOL_CONFIG_NV
);
1167 if (wol_cfg
& (1UL << adapter
->portnum
)) {
1168 wol_cfg
= QLCRD32(adapter
, QLCNIC_WOL_CONFIG
);
1169 if (wol_cfg
& (1 << adapter
->portnum
))
1176 int qlcnic_config_led(struct qlcnic_adapter
*adapter
, u32 state
, u32 rate
)
1178 struct qlcnic_nic_req req
;
1182 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
1183 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
1185 word
= QLCNIC_H2C_OPCODE_CONFIG_LED
| ((u64
)adapter
->portnum
<< 16);
1186 req
.req_hdr
= cpu_to_le64(word
);
1188 req
.words
[0] = cpu_to_le64((u64
)rate
<< 32);
1189 req
.words
[1] = cpu_to_le64(state
);
1191 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
1193 dev_err(&adapter
->pdev
->dev
, "LED configuration failed.\n");
1198 static int qlcnic_set_fw_loopback(struct qlcnic_adapter
*adapter
, u32 flag
)
1200 struct qlcnic_nic_req req
;
1204 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
1205 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
1207 word
= QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK
|
1208 ((u64
)adapter
->portnum
<< 16);
1209 req
.req_hdr
= cpu_to_le64(word
);
1210 req
.words
[0] = cpu_to_le64(flag
);
1212 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
1214 dev_err(&adapter
->pdev
->dev
,
1215 "%sting loopback mode failed.\n",
1216 flag
? "Set" : "Reset");
1220 int qlcnic_set_ilb_mode(struct qlcnic_adapter
*adapter
)
1222 if (qlcnic_set_fw_loopback(adapter
, 1))
1225 if (qlcnic_nic_set_promisc(adapter
,
1226 VPORT_MISS_MODE_ACCEPT_ALL
)) {
1227 qlcnic_set_fw_loopback(adapter
, 0);
1235 void qlcnic_clear_ilb_mode(struct qlcnic_adapter
*adapter
)
1237 int mode
= VPORT_MISS_MODE_DROP
;
1238 struct net_device
*netdev
= adapter
->netdev
;
1240 qlcnic_set_fw_loopback(adapter
, 0);
1242 if (netdev
->flags
& IFF_PROMISC
)
1243 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
1244 else if (netdev
->flags
& IFF_ALLMULTI
)
1245 mode
= VPORT_MISS_MODE_ACCEPT_MULTI
;
1247 qlcnic_nic_set_promisc(adapter
, mode
);