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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ericvh...
[deliverable/linux.git] / drivers / net / qlcnic / qlcnic_hw.c
1 /*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25 #include "qlcnic.h"
26
27 #include <net/ip.h>
28
29 #define MASK(n) ((1ULL<<(n))-1)
30 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
31
32 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
33
34 #define CRB_BLK(off) ((off >> 20) & 0x3f)
35 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
36 #define CRB_WINDOW_2M (0x130060)
37 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
38 #define CRB_INDIRECT_2M (0x1e0000UL)
39
40
41 #ifndef readq
42 static inline u64 readq(void __iomem *addr)
43 {
44 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
45 }
46 #endif
47
48 #ifndef writeq
49 static inline void writeq(u64 val, void __iomem *addr)
50 {
51 writel(((u32) (val)), (addr));
52 writel(((u32) (val >> 32)), (addr + 4));
53 }
54 #endif
55
56 #define ADDR_IN_RANGE(addr, low, high) \
57 (((addr) < (high)) && ((addr) >= (low)))
58
59 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
60 ((adapter)->ahw.pci_base0 + (off))
61
62 static void __iomem *pci_base_offset(struct qlcnic_adapter *adapter,
63 unsigned long off)
64 {
65 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
66 return PCI_OFFSET_FIRST_RANGE(adapter, off);
67
68 return NULL;
69 }
70
71 static const struct crb_128M_2M_block_map
72 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
73 {{{0, 0, 0, 0} } }, /* 0: PCI */
74 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
75 {1, 0x0110000, 0x0120000, 0x130000},
76 {1, 0x0120000, 0x0122000, 0x124000},
77 {1, 0x0130000, 0x0132000, 0x126000},
78 {1, 0x0140000, 0x0142000, 0x128000},
79 {1, 0x0150000, 0x0152000, 0x12a000},
80 {1, 0x0160000, 0x0170000, 0x110000},
81 {1, 0x0170000, 0x0172000, 0x12e000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {1, 0x01e0000, 0x01e0800, 0x122000},
89 {0, 0x0000000, 0x0000000, 0x000000} } },
90 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
91 {{{0, 0, 0, 0} } }, /* 3: */
92 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
93 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
94 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
95 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
96 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {1, 0x08f0000, 0x08f2000, 0x172000} } },
112 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x09f0000, 0x09f2000, 0x176000} } },
128 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
144 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
160 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
161 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
162 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
163 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
164 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
165 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
166 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
167 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
168 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
169 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
170 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
171 {{{0, 0, 0, 0} } }, /* 23: */
172 {{{0, 0, 0, 0} } }, /* 24: */
173 {{{0, 0, 0, 0} } }, /* 25: */
174 {{{0, 0, 0, 0} } }, /* 26: */
175 {{{0, 0, 0, 0} } }, /* 27: */
176 {{{0, 0, 0, 0} } }, /* 28: */
177 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
178 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
179 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
180 {{{0} } }, /* 32: PCI */
181 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
182 {1, 0x2110000, 0x2120000, 0x130000},
183 {1, 0x2120000, 0x2122000, 0x124000},
184 {1, 0x2130000, 0x2132000, 0x126000},
185 {1, 0x2140000, 0x2142000, 0x128000},
186 {1, 0x2150000, 0x2152000, 0x12a000},
187 {1, 0x2160000, 0x2170000, 0x110000},
188 {1, 0x2170000, 0x2172000, 0x12e000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000} } },
197 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
198 {{{0} } }, /* 35: */
199 {{{0} } }, /* 36: */
200 {{{0} } }, /* 37: */
201 {{{0} } }, /* 38: */
202 {{{0} } }, /* 39: */
203 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
204 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
205 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
206 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
207 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
208 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
209 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
210 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
211 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
212 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
213 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
214 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
215 {{{0} } }, /* 52: */
216 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
217 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
218 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
219 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
220 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
221 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
222 {{{0} } }, /* 59: I2C0 */
223 {{{0} } }, /* 60: I2C1 */
224 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
225 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
226 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
227 };
228
229 /*
230 * top 12 bits of crb internal address (hub, agent)
231 */
232 static const unsigned crb_hub_agt[64] = {
233 0,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
237 0,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
240 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
249 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
251 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
254 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
260 0,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
263 0,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
265 0,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
268 0,
269 0,
270 0,
271 0,
272 0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
274 0,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
276 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
277 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
278 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
279 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
280 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
281 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
282 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
283 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
284 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
285 0,
286 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
287 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
288 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
289 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
290 0,
291 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
292 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
293 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
294 0,
295 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
296 0,
297 };
298
299 /* PCI Windowing for DDR regions. */
300
301 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
302
303 int
304 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
305 {
306 int done = 0, timeout = 0;
307
308 while (!done) {
309 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
310 if (done == 1)
311 break;
312 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT)
313 return -EIO;
314 msleep(1);
315 }
316
317 if (id_reg)
318 QLCWR32(adapter, id_reg, adapter->portnum);
319
320 return 0;
321 }
322
323 void
324 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
325 {
326 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
327 }
328
329 static int
330 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
331 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
332 {
333 u32 i, producer, consumer;
334 struct qlcnic_cmd_buffer *pbuf;
335 struct cmd_desc_type0 *cmd_desc;
336 struct qlcnic_host_tx_ring *tx_ring;
337
338 i = 0;
339
340 if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
341 return -EIO;
342
343 tx_ring = adapter->tx_ring;
344 __netif_tx_lock_bh(tx_ring->txq);
345
346 producer = tx_ring->producer;
347 consumer = tx_ring->sw_consumer;
348
349 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
350 netif_tx_stop_queue(tx_ring->txq);
351 __netif_tx_unlock_bh(tx_ring->txq);
352 adapter->stats.xmit_off++;
353 return -EBUSY;
354 }
355
356 do {
357 cmd_desc = &cmd_desc_arr[i];
358
359 pbuf = &tx_ring->cmd_buf_arr[producer];
360 pbuf->skb = NULL;
361 pbuf->frag_count = 0;
362
363 memcpy(&tx_ring->desc_head[producer],
364 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
365
366 producer = get_next_index(producer, tx_ring->num_desc);
367 i++;
368
369 } while (i != nr_desc);
370
371 tx_ring->producer = producer;
372
373 qlcnic_update_cmd_producer(adapter, tx_ring);
374
375 __netif_tx_unlock_bh(tx_ring->txq);
376
377 return 0;
378 }
379
380 static int
381 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
382 unsigned op)
383 {
384 struct qlcnic_nic_req req;
385 struct qlcnic_mac_req *mac_req;
386 u64 word;
387
388 memset(&req, 0, sizeof(struct qlcnic_nic_req));
389 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
390
391 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
392 req.req_hdr = cpu_to_le64(word);
393
394 mac_req = (struct qlcnic_mac_req *)&req.words[0];
395 mac_req->op = op;
396 memcpy(mac_req->mac_addr, addr, 6);
397
398 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
399 }
400
401 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
402 {
403 struct list_head *head;
404 struct qlcnic_mac_list_s *cur;
405
406 /* look up if already exists */
407 list_for_each(head, &adapter->mac_list) {
408 cur = list_entry(head, struct qlcnic_mac_list_s, list);
409 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
410 return 0;
411 }
412
413 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
414 if (cur == NULL) {
415 dev_err(&adapter->netdev->dev,
416 "failed to add mac address filter\n");
417 return -ENOMEM;
418 }
419 memcpy(cur->mac_addr, addr, ETH_ALEN);
420 list_add_tail(&cur->list, &adapter->mac_list);
421
422 return qlcnic_sre_macaddr_change(adapter,
423 cur->mac_addr, QLCNIC_MAC_ADD);
424 }
425
426 void qlcnic_set_multi(struct net_device *netdev)
427 {
428 struct qlcnic_adapter *adapter = netdev_priv(netdev);
429 struct dev_mc_list *mc_ptr;
430 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
431 u32 mode = VPORT_MISS_MODE_DROP;
432
433 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
434 qlcnic_nic_add_mac(adapter, bcast_addr);
435
436 if (netdev->flags & IFF_PROMISC) {
437 mode = VPORT_MISS_MODE_ACCEPT_ALL;
438 goto send_fw_cmd;
439 }
440
441 if ((netdev->flags & IFF_ALLMULTI) ||
442 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
443 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
444 goto send_fw_cmd;
445 }
446
447 if (!netdev_mc_empty(netdev)) {
448 netdev_for_each_mc_addr(mc_ptr, netdev) {
449 qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr);
450 }
451 }
452
453 send_fw_cmd:
454 qlcnic_nic_set_promisc(adapter, mode);
455 }
456
457 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
458 {
459 struct qlcnic_nic_req req;
460 u64 word;
461
462 memset(&req, 0, sizeof(struct qlcnic_nic_req));
463
464 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
465
466 word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
467 ((u64)adapter->portnum << 16);
468 req.req_hdr = cpu_to_le64(word);
469
470 req.words[0] = cpu_to_le64(mode);
471
472 return qlcnic_send_cmd_descs(adapter,
473 (struct cmd_desc_type0 *)&req, 1);
474 }
475
476 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
477 {
478 struct qlcnic_mac_list_s *cur;
479 struct list_head *head = &adapter->mac_list;
480
481 while (!list_empty(head)) {
482 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
483 qlcnic_sre_macaddr_change(adapter,
484 cur->mac_addr, QLCNIC_MAC_DEL);
485 list_del(&cur->list);
486 kfree(cur);
487 }
488 }
489
490 #define QLCNIC_CONFIG_INTR_COALESCE 3
491
492 /*
493 * Send the interrupt coalescing parameter set by ethtool to the card.
494 */
495 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
496 {
497 struct qlcnic_nic_req req;
498 u64 word[6];
499 int rv, i;
500
501 memset(&req, 0, sizeof(struct qlcnic_nic_req));
502
503 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
504
505 word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
506 req.req_hdr = cpu_to_le64(word[0]);
507
508 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
509 for (i = 0; i < 6; i++)
510 req.words[i] = cpu_to_le64(word[i]);
511
512 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
513 if (rv != 0)
514 dev_err(&adapter->netdev->dev,
515 "Could not send interrupt coalescing parameters\n");
516
517 return rv;
518 }
519
520 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
521 {
522 struct qlcnic_nic_req req;
523 u64 word;
524 int rv;
525
526 if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
527 return 0;
528
529 memset(&req, 0, sizeof(struct qlcnic_nic_req));
530
531 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
532
533 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
534 req.req_hdr = cpu_to_le64(word);
535
536 req.words[0] = cpu_to_le64(enable);
537
538 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
539 if (rv != 0)
540 dev_err(&adapter->netdev->dev,
541 "Could not send configure hw lro request\n");
542
543 adapter->flags ^= QLCNIC_LRO_ENABLED;
544
545 return rv;
546 }
547
548 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable)
549 {
550 struct qlcnic_nic_req req;
551 u64 word;
552 int rv;
553
554 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
555 return 0;
556
557 memset(&req, 0, sizeof(struct qlcnic_nic_req));
558
559 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
560
561 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
562 ((u64)adapter->portnum << 16);
563 req.req_hdr = cpu_to_le64(word);
564
565 req.words[0] = cpu_to_le64(enable);
566
567 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
568 if (rv != 0)
569 dev_err(&adapter->netdev->dev,
570 "Could not send configure bridge mode request\n");
571
572 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
573
574 return rv;
575 }
576
577
578 #define RSS_HASHTYPE_IP_TCP 0x3
579
580 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
581 {
582 struct qlcnic_nic_req req;
583 u64 word;
584 int i, rv;
585
586 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
587 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
588 0x255b0ec26d5a56daULL };
589
590
591 memset(&req, 0, sizeof(struct qlcnic_nic_req));
592 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
593
594 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
595 req.req_hdr = cpu_to_le64(word);
596
597 /*
598 * RSS request:
599 * bits 3-0: hash_method
600 * 5-4: hash_type_ipv4
601 * 7-6: hash_type_ipv6
602 * 8: enable
603 * 9: use indirection table
604 * 47-10: reserved
605 * 63-48: indirection table mask
606 */
607 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
608 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
609 ((u64)(enable & 0x1) << 8) |
610 ((0x7ULL) << 48);
611 req.words[0] = cpu_to_le64(word);
612 for (i = 0; i < 5; i++)
613 req.words[i+1] = cpu_to_le64(key[i]);
614
615 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
616 if (rv != 0)
617 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
618
619 return rv;
620 }
621
622 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
623 {
624 struct qlcnic_nic_req req;
625 u64 word;
626 int rv;
627
628 memset(&req, 0, sizeof(struct qlcnic_nic_req));
629 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
630
631 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
632 req.req_hdr = cpu_to_le64(word);
633
634 req.words[0] = cpu_to_le64(cmd);
635 req.words[1] = cpu_to_le64(ip);
636
637 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
638 if (rv != 0)
639 dev_err(&adapter->netdev->dev,
640 "could not notify %s IP 0x%x reuqest\n",
641 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
642
643 return rv;
644 }
645
646 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
647 {
648 struct qlcnic_nic_req req;
649 u64 word;
650 int rv;
651
652 memset(&req, 0, sizeof(struct qlcnic_nic_req));
653 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
654
655 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
656 req.req_hdr = cpu_to_le64(word);
657 req.words[0] = cpu_to_le64(enable | (enable << 8));
658
659 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
660 if (rv != 0)
661 dev_err(&adapter->netdev->dev,
662 "could not configure link notification\n");
663
664 return rv;
665 }
666
667 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
668 {
669 struct qlcnic_nic_req req;
670 u64 word;
671 int rv;
672
673 memset(&req, 0, sizeof(struct qlcnic_nic_req));
674 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
675
676 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
677 ((u64)adapter->portnum << 16) |
678 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
679
680 req.req_hdr = cpu_to_le64(word);
681
682 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
683 if (rv != 0)
684 dev_err(&adapter->netdev->dev,
685 "could not cleanup lro flows\n");
686
687 return rv;
688 }
689
690 /*
691 * qlcnic_change_mtu - Change the Maximum Transfer Unit
692 * @returns 0 on success, negative on failure
693 */
694
695 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
696 {
697 struct qlcnic_adapter *adapter = netdev_priv(netdev);
698 int rc = 0;
699
700 if (mtu > P3_MAX_MTU) {
701 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
702 P3_MAX_MTU);
703 return -EINVAL;
704 }
705
706 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
707
708 if (!rc)
709 netdev->mtu = mtu;
710
711 return rc;
712 }
713
714 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac)
715 {
716 u32 crbaddr, mac_hi, mac_lo;
717 int pci_func = adapter->ahw.pci_func;
718
719 crbaddr = CRB_MAC_BLOCK_START +
720 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
721
722 mac_lo = QLCRD32(adapter, crbaddr);
723 mac_hi = QLCRD32(adapter, crbaddr+4);
724
725 if (pci_func & 1)
726 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
727 else
728 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
729
730 return 0;
731 }
732
733 /*
734 * Changes the CRB window to the specified window.
735 */
736 /* Returns < 0 if off is not valid,
737 * 1 if window access is needed. 'off' is set to offset from
738 * CRB space in 128M pci map
739 * 0 if no window access is needed. 'off' is set to 2M addr
740 * In: 'off' is offset from base in 128M pci map
741 */
742 static int
743 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
744 ulong off, void __iomem **addr)
745 {
746 const struct crb_128M_2M_sub_block_map *m;
747
748 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
749 return -EINVAL;
750
751 off -= QLCNIC_PCI_CRBSPACE;
752
753 /*
754 * Try direct map
755 */
756 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
757
758 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
759 *addr = adapter->ahw.pci_base0 + m->start_2M +
760 (off - m->start_128M);
761 return 0;
762 }
763
764 /*
765 * Not in direct map, use crb window
766 */
767 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
768 return 1;
769 }
770
771 /*
772 * In: 'off' is offset from CRB space in 128M pci map
773 * Out: 'off' is 2M pci map addr
774 * side effect: lock crb window
775 */
776 static void
777 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
778 {
779 u32 window;
780 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
781
782 off -= QLCNIC_PCI_CRBSPACE;
783
784 window = CRB_HI(off);
785
786 if (adapter->ahw.crb_win == window)
787 return;
788
789 writel(window, addr);
790 if (readl(addr) != window) {
791 if (printk_ratelimit())
792 dev_warn(&adapter->pdev->dev,
793 "failed to set CRB window to %d off 0x%lx\n",
794 window, off);
795 }
796 adapter->ahw.crb_win = window;
797 }
798
799 int
800 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
801 {
802 unsigned long flags;
803 int rv;
804 void __iomem *addr = NULL;
805
806 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
807
808 if (rv == 0) {
809 writel(data, addr);
810 return 0;
811 }
812
813 if (rv > 0) {
814 /* indirect access */
815 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
816 crb_win_lock(adapter);
817 qlcnic_pci_set_crbwindow_2M(adapter, off);
818 writel(data, addr);
819 crb_win_unlock(adapter);
820 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
821 return 0;
822 }
823
824 dev_err(&adapter->pdev->dev,
825 "%s: invalid offset: 0x%016lx\n", __func__, off);
826 dump_stack();
827 return -EIO;
828 }
829
830 u32
831 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
832 {
833 unsigned long flags;
834 int rv;
835 u32 data;
836 void __iomem *addr = NULL;
837
838 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
839
840 if (rv == 0)
841 return readl(addr);
842
843 if (rv > 0) {
844 /* indirect access */
845 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
846 crb_win_lock(adapter);
847 qlcnic_pci_set_crbwindow_2M(adapter, off);
848 data = readl(addr);
849 crb_win_unlock(adapter);
850 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
851 return data;
852 }
853
854 dev_err(&adapter->pdev->dev,
855 "%s: invalid offset: 0x%016lx\n", __func__, off);
856 dump_stack();
857 return -1;
858 }
859
860
861 void __iomem *
862 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
863 {
864 void __iomem *addr = NULL;
865
866 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
867
868 return addr;
869 }
870
871
872 static int
873 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
874 u64 addr, u32 *start)
875 {
876 u32 window;
877 struct pci_dev *pdev = adapter->pdev;
878
879 if ((addr & 0x00ff800) == 0xff800) {
880 if (printk_ratelimit())
881 dev_warn(&pdev->dev, "QM access not handled\n");
882 return -EIO;
883 }
884
885 window = OCM_WIN_P3P(addr);
886
887 writel(window, adapter->ahw.ocm_win_crb);
888 /* read back to flush */
889 readl(adapter->ahw.ocm_win_crb);
890
891 adapter->ahw.ocm_win = window;
892 *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
893 return 0;
894 }
895
896 static int
897 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
898 u64 *data, int op)
899 {
900 void __iomem *addr, *mem_ptr = NULL;
901 resource_size_t mem_base;
902 int ret;
903 u32 start;
904
905 mutex_lock(&adapter->ahw.mem_lock);
906
907 ret = qlcnic_pci_set_window_2M(adapter, off, &start);
908 if (ret != 0)
909 goto unlock;
910
911 addr = pci_base_offset(adapter, start);
912 if (addr)
913 goto noremap;
914
915 mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
916
917 mem_ptr = ioremap(mem_base, PAGE_SIZE);
918 if (mem_ptr == NULL) {
919 ret = -EIO;
920 goto unlock;
921 }
922
923 addr = mem_ptr + (start & (PAGE_SIZE - 1));
924
925 noremap:
926 if (op == 0) /* read */
927 *data = readq(addr);
928 else /* write */
929 writeq(*data, addr);
930
931 unlock:
932 mutex_unlock(&adapter->ahw.mem_lock);
933
934 if (mem_ptr)
935 iounmap(mem_ptr);
936 return ret;
937 }
938
939 #define MAX_CTL_CHECK 1000
940
941 int
942 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
943 u64 off, u64 data)
944 {
945 int i, j, ret;
946 u32 temp, off8;
947 u64 stride;
948 void __iomem *mem_crb;
949
950 /* Only 64-bit aligned access */
951 if (off & 7)
952 return -EIO;
953
954 /* P3 onward, test agent base for MIU and SIU is same */
955 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
956 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
957 mem_crb = qlcnic_get_ioaddr(adapter,
958 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
959 goto correct;
960 }
961
962 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
963 mem_crb = qlcnic_get_ioaddr(adapter,
964 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
965 goto correct;
966 }
967
968 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
969 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
970
971 return -EIO;
972
973 correct:
974 stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
975
976 off8 = off & ~(stride-1);
977
978 mutex_lock(&adapter->ahw.mem_lock);
979
980 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
981 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
982
983 i = 0;
984 if (stride == 16) {
985 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
986 writel((TA_CTL_START | TA_CTL_ENABLE),
987 (mem_crb + TEST_AGT_CTRL));
988
989 for (j = 0; j < MAX_CTL_CHECK; j++) {
990 temp = readl(mem_crb + TEST_AGT_CTRL);
991 if ((temp & TA_CTL_BUSY) == 0)
992 break;
993 }
994
995 if (j >= MAX_CTL_CHECK) {
996 ret = -EIO;
997 goto done;
998 }
999
1000 i = (off & 0xf) ? 0 : 2;
1001 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1002 mem_crb + MIU_TEST_AGT_WRDATA(i));
1003 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1004 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1005 i = (off & 0xf) ? 2 : 0;
1006 }
1007
1008 writel(data & 0xffffffff,
1009 mem_crb + MIU_TEST_AGT_WRDATA(i));
1010 writel((data >> 32) & 0xffffffff,
1011 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1012
1013 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1014 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1015 (mem_crb + TEST_AGT_CTRL));
1016
1017 for (j = 0; j < MAX_CTL_CHECK; j++) {
1018 temp = readl(mem_crb + TEST_AGT_CTRL);
1019 if ((temp & TA_CTL_BUSY) == 0)
1020 break;
1021 }
1022
1023 if (j >= MAX_CTL_CHECK) {
1024 if (printk_ratelimit())
1025 dev_err(&adapter->pdev->dev,
1026 "failed to write through agent\n");
1027 ret = -EIO;
1028 } else
1029 ret = 0;
1030
1031 done:
1032 mutex_unlock(&adapter->ahw.mem_lock);
1033
1034 return ret;
1035 }
1036
1037 int
1038 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1039 u64 off, u64 *data)
1040 {
1041 int j, ret;
1042 u32 temp, off8;
1043 u64 val, stride;
1044 void __iomem *mem_crb;
1045
1046 /* Only 64-bit aligned access */
1047 if (off & 7)
1048 return -EIO;
1049
1050 /* P3 onward, test agent base for MIU and SIU is same */
1051 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1052 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
1053 mem_crb = qlcnic_get_ioaddr(adapter,
1054 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1055 goto correct;
1056 }
1057
1058 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1059 mem_crb = qlcnic_get_ioaddr(adapter,
1060 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1061 goto correct;
1062 }
1063
1064 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1065 return qlcnic_pci_mem_access_direct(adapter,
1066 off, data, 0);
1067 }
1068
1069 return -EIO;
1070
1071 correct:
1072 stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1073
1074 off8 = off & ~(stride-1);
1075
1076 mutex_lock(&adapter->ahw.mem_lock);
1077
1078 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1079 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1080 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1081 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1082
1083 for (j = 0; j < MAX_CTL_CHECK; j++) {
1084 temp = readl(mem_crb + TEST_AGT_CTRL);
1085 if ((temp & TA_CTL_BUSY) == 0)
1086 break;
1087 }
1088
1089 if (j >= MAX_CTL_CHECK) {
1090 if (printk_ratelimit())
1091 dev_err(&adapter->pdev->dev,
1092 "failed to read through agent\n");
1093 ret = -EIO;
1094 } else {
1095 off8 = MIU_TEST_AGT_RDDATA_LO;
1096 if ((stride == 16) && (off & 0xf))
1097 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1098
1099 temp = readl(mem_crb + off8 + 4);
1100 val = (u64)temp << 32;
1101 val |= readl(mem_crb + off8);
1102 *data = val;
1103 ret = 0;
1104 }
1105
1106 mutex_unlock(&adapter->ahw.mem_lock);
1107
1108 return ret;
1109 }
1110
1111 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1112 {
1113 int offset, board_type, magic;
1114 struct pci_dev *pdev = adapter->pdev;
1115
1116 offset = QLCNIC_FW_MAGIC_OFFSET;
1117 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1118 return -EIO;
1119
1120 if (magic != QLCNIC_BDINFO_MAGIC) {
1121 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1122 magic);
1123 return -EIO;
1124 }
1125
1126 offset = QLCNIC_BRDTYPE_OFFSET;
1127 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1128 return -EIO;
1129
1130 adapter->ahw.board_type = board_type;
1131
1132 if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1133 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1134 if ((gpio & 0x8000) == 0)
1135 board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1136 }
1137
1138 switch (board_type) {
1139 case QLCNIC_BRDTYPE_P3_HMEZ:
1140 case QLCNIC_BRDTYPE_P3_XG_LOM:
1141 case QLCNIC_BRDTYPE_P3_10G_CX4:
1142 case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1143 case QLCNIC_BRDTYPE_P3_IMEZ:
1144 case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1145 case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1146 case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1147 case QLCNIC_BRDTYPE_P3_10G_XFP:
1148 case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1149 adapter->ahw.port_type = QLCNIC_XGBE;
1150 break;
1151 case QLCNIC_BRDTYPE_P3_REF_QG:
1152 case QLCNIC_BRDTYPE_P3_4_GB:
1153 case QLCNIC_BRDTYPE_P3_4_GB_MM:
1154 adapter->ahw.port_type = QLCNIC_GBE;
1155 break;
1156 case QLCNIC_BRDTYPE_P3_10G_TP:
1157 adapter->ahw.port_type = (adapter->portnum < 2) ?
1158 QLCNIC_XGBE : QLCNIC_GBE;
1159 break;
1160 default:
1161 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1162 adapter->ahw.port_type = QLCNIC_XGBE;
1163 break;
1164 }
1165
1166 return 0;
1167 }
1168
1169 int
1170 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1171 {
1172 u32 wol_cfg;
1173
1174 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1175 if (wol_cfg & (1UL << adapter->portnum)) {
1176 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1177 if (wol_cfg & (1 << adapter->portnum))
1178 return 1;
1179 }
1180
1181 return 0;
1182 }
1183
1184 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1185 {
1186 struct qlcnic_nic_req req;
1187 int rv;
1188 u64 word;
1189
1190 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1191 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1192
1193 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1194 req.req_hdr = cpu_to_le64(word);
1195
1196 req.words[0] = cpu_to_le64((u64)rate << 32);
1197 req.words[1] = cpu_to_le64(state);
1198
1199 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1200 if (rv)
1201 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1202
1203 return rv;
1204 }
1205
1206 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1207 {
1208 struct qlcnic_nic_req req;
1209 int rv;
1210 u64 word;
1211
1212 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1213 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1214
1215 word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1216 ((u64)adapter->portnum << 16);
1217 req.req_hdr = cpu_to_le64(word);
1218 req.words[0] = cpu_to_le64(flag);
1219
1220 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1221 if (rv)
1222 dev_err(&adapter->pdev->dev,
1223 "%sting loopback mode failed.\n",
1224 flag ? "Set" : "Reset");
1225 return rv;
1226 }
1227
1228 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1229 {
1230 if (qlcnic_set_fw_loopback(adapter, 1))
1231 return -EIO;
1232
1233 if (qlcnic_nic_set_promisc(adapter,
1234 VPORT_MISS_MODE_ACCEPT_ALL)) {
1235 qlcnic_set_fw_loopback(adapter, 0);
1236 return -EIO;
1237 }
1238
1239 msleep(1000);
1240 return 0;
1241 }
1242
1243 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1244 {
1245 int mode = VPORT_MISS_MODE_DROP;
1246 struct net_device *netdev = adapter->netdev;
1247
1248 qlcnic_set_fw_loopback(adapter, 0);
1249
1250 if (netdev->flags & IFF_PROMISC)
1251 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1252 else if (netdev->flags & IFF_ALLMULTI)
1253 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1254
1255 qlcnic_nic_set_promisc(adapter, mode);
1256 }
Linux kernel - Deliverables
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