2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name
[] = DRV_NAME
;
47 const char qlge_driver_version
[] = DRV_VERSION
;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING
" ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION
);
54 static const u32 default_msg
=
55 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
|
56 /* NETIF_MSG_TIMER | */
62 NETIF_MSG_INTR
| NETIF_MSG_TX_DONE
| NETIF_MSG_RX_STATUS
|
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW
| NETIF_MSG_WOL
| 0;
66 static int debug
= 0x00007fff; /* defaults above */
67 module_param(debug
, int, 0);
68 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
73 static int irq_type
= MSIX_IRQ
;
74 module_param(irq_type
, int, MSIX_IRQ
);
75 MODULE_PARM_DESC(irq_type
, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static struct pci_device_id qlge_pci_tbl
[] __devinitdata
= {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC
, QLGE_DEVICE_ID
)},
79 /* required last entry */
83 MODULE_DEVICE_TABLE(pci
, qlge_pci_tbl
);
85 /* This hardware semaphore causes exclusive access to
86 * resources shared between the NIC driver, MPI firmware,
87 * FCOE firmware and the FC driver.
89 static int ql_sem_trylock(struct ql_adapter
*qdev
, u32 sem_mask
)
95 sem_bits
= SEM_SET
<< SEM_XGMAC0_SHIFT
;
98 sem_bits
= SEM_SET
<< SEM_XGMAC1_SHIFT
;
101 sem_bits
= SEM_SET
<< SEM_ICB_SHIFT
;
103 case SEM_MAC_ADDR_MASK
:
104 sem_bits
= SEM_SET
<< SEM_MAC_ADDR_SHIFT
;
107 sem_bits
= SEM_SET
<< SEM_FLASH_SHIFT
;
110 sem_bits
= SEM_SET
<< SEM_PROBE_SHIFT
;
112 case SEM_RT_IDX_MASK
:
113 sem_bits
= SEM_SET
<< SEM_RT_IDX_SHIFT
;
115 case SEM_PROC_REG_MASK
:
116 sem_bits
= SEM_SET
<< SEM_PROC_REG_SHIFT
;
119 QPRINTK(qdev
, PROBE
, ALERT
, "Bad Semaphore mask!.\n");
123 ql_write32(qdev
, SEM
, sem_bits
| sem_mask
);
124 return !(ql_read32(qdev
, SEM
) & sem_bits
);
127 int ql_sem_spinlock(struct ql_adapter
*qdev
, u32 sem_mask
)
129 unsigned int wait_count
= 30;
131 if (!ql_sem_trylock(qdev
, sem_mask
))
134 } while (--wait_count
);
138 void ql_sem_unlock(struct ql_adapter
*qdev
, u32 sem_mask
)
140 ql_write32(qdev
, SEM
, sem_mask
);
141 ql_read32(qdev
, SEM
); /* flush */
144 /* This function waits for a specific bit to come ready
145 * in a given register. It is used mostly by the initialize
146 * process, but is also used in kernel thread API such as
147 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149 int ql_wait_reg_rdy(struct ql_adapter
*qdev
, u32 reg
, u32 bit
, u32 err_bit
)
152 int count
= UDELAY_COUNT
;
155 temp
= ql_read32(qdev
, reg
);
157 /* check for errors */
158 if (temp
& err_bit
) {
159 QPRINTK(qdev
, PROBE
, ALERT
,
160 "register 0x%.08x access error, value = 0x%.08x!.\n",
163 } else if (temp
& bit
)
165 udelay(UDELAY_DELAY
);
168 QPRINTK(qdev
, PROBE
, ALERT
,
169 "Timed out waiting for reg %x to come ready.\n", reg
);
173 /* The CFG register is used to download TX and RX control blocks
174 * to the chip. This function waits for an operation to complete.
176 static int ql_wait_cfg(struct ql_adapter
*qdev
, u32 bit
)
178 int count
= UDELAY_COUNT
;
182 temp
= ql_read32(qdev
, CFG
);
187 udelay(UDELAY_DELAY
);
194 /* Used to issue init control blocks to hw. Maps control block,
195 * sets address, triggers download, waits for completion.
197 int ql_write_cfg(struct ql_adapter
*qdev
, void *ptr
, int size
, u32 bit
,
207 (bit
& (CFG_LRQ
| CFG_LR
| CFG_LCQ
)) ? PCI_DMA_TODEVICE
:
210 map
= pci_map_single(qdev
->pdev
, ptr
, size
, direction
);
211 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
212 QPRINTK(qdev
, IFUP
, ERR
, "Couldn't map DMA area.\n");
216 status
= ql_wait_cfg(qdev
, bit
);
218 QPRINTK(qdev
, IFUP
, ERR
,
219 "Timed out waiting for CFG to come ready.\n");
223 status
= ql_sem_spinlock(qdev
, SEM_ICB_MASK
);
226 ql_write32(qdev
, ICB_L
, (u32
) map
);
227 ql_write32(qdev
, ICB_H
, (u32
) (map
>> 32));
228 ql_sem_unlock(qdev
, SEM_ICB_MASK
); /* does flush too */
230 mask
= CFG_Q_MASK
| (bit
<< 16);
231 value
= bit
| (q_id
<< CFG_Q_SHIFT
);
232 ql_write32(qdev
, CFG
, (mask
| value
));
235 * Wait for the bit to clear after signaling hw.
237 status
= ql_wait_cfg(qdev
, bit
);
239 pci_unmap_single(qdev
->pdev
, map
, size
, direction
);
243 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
244 int ql_get_mac_addr_reg(struct ql_adapter
*qdev
, u32 type
, u16 index
,
250 status
= ql_sem_spinlock(qdev
, SEM_MAC_ADDR_MASK
);
254 case MAC_ADDR_TYPE_MULTI_MAC
:
255 case MAC_ADDR_TYPE_CAM_MAC
:
258 ql_wait_reg_rdy(qdev
,
259 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
262 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
263 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
264 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
266 ql_wait_reg_rdy(qdev
,
267 MAC_ADDR_IDX
, MAC_ADDR_MR
, 0);
270 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
272 ql_wait_reg_rdy(qdev
,
273 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
276 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
277 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
278 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
280 ql_wait_reg_rdy(qdev
,
281 MAC_ADDR_IDX
, MAC_ADDR_MR
, 0);
284 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
285 if (type
== MAC_ADDR_TYPE_CAM_MAC
) {
287 ql_wait_reg_rdy(qdev
,
288 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
291 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
292 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
293 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
295 ql_wait_reg_rdy(qdev
, MAC_ADDR_IDX
,
299 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
303 case MAC_ADDR_TYPE_VLAN
:
304 case MAC_ADDR_TYPE_MULTI_FLTR
:
306 QPRINTK(qdev
, IFUP
, CRIT
,
307 "Address type %d not yet supported.\n", type
);
311 ql_sem_unlock(qdev
, SEM_MAC_ADDR_MASK
);
315 /* Set up a MAC, multicast or VLAN address for the
316 * inbound frame matching.
318 static int ql_set_mac_addr_reg(struct ql_adapter
*qdev
, u8
*addr
, u32 type
,
324 status
= ql_sem_spinlock(qdev
, SEM_MAC_ADDR_MASK
);
328 case MAC_ADDR_TYPE_MULTI_MAC
:
329 case MAC_ADDR_TYPE_CAM_MAC
:
332 u32 upper
= (addr
[0] << 8) | addr
[1];
334 (addr
[2] << 24) | (addr
[3] << 16) | (addr
[4] << 8) |
337 QPRINTK(qdev
, IFUP
, INFO
,
338 "Adding %s address %pM"
339 " at index %d in the CAM.\n",
341 MAC_ADDR_TYPE_MULTI_MAC
) ? "MULTICAST" :
342 "UNICAST"), addr
, index
);
345 ql_wait_reg_rdy(qdev
,
346 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
349 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
350 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
352 ql_write32(qdev
, MAC_ADDR_DATA
, lower
);
354 ql_wait_reg_rdy(qdev
,
355 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
358 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
359 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
361 ql_write32(qdev
, MAC_ADDR_DATA
, upper
);
363 ql_wait_reg_rdy(qdev
,
364 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
367 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
) | /* offset */
368 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
370 /* This field should also include the queue id
371 and possibly the function id. Right now we hardcode
372 the route field to NIC core.
374 if (type
== MAC_ADDR_TYPE_CAM_MAC
) {
375 cam_output
= (CAM_OUT_ROUTE_NIC
|
377 func
<< CAM_OUT_FUNC_SHIFT
) |
379 rss_ring_first_cq_id
<<
380 CAM_OUT_CQ_ID_SHIFT
));
382 cam_output
|= CAM_OUT_RV
;
383 /* route to NIC core */
384 ql_write32(qdev
, MAC_ADDR_DATA
, cam_output
);
388 case MAC_ADDR_TYPE_VLAN
:
390 u32 enable_bit
= *((u32
*) &addr
[0]);
391 /* For VLAN, the addr actually holds a bit that
392 * either enables or disables the vlan id we are
393 * addressing. It's either MAC_ADDR_E on or off.
394 * That's bit-27 we're talking about.
396 QPRINTK(qdev
, IFUP
, INFO
, "%s VLAN ID %d %s the CAM.\n",
397 (enable_bit
? "Adding" : "Removing"),
398 index
, (enable_bit
? "to" : "from"));
401 ql_wait_reg_rdy(qdev
,
402 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
405 ql_write32(qdev
, MAC_ADDR_IDX
, offset
| /* offset */
406 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
408 enable_bit
); /* enable/disable */
411 case MAC_ADDR_TYPE_MULTI_FLTR
:
413 QPRINTK(qdev
, IFUP
, CRIT
,
414 "Address type %d not yet supported.\n", type
);
418 ql_sem_unlock(qdev
, SEM_MAC_ADDR_MASK
);
422 /* Get a specific frame routing value from the CAM.
423 * Used for debug and reg dump.
425 int ql_get_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32
*value
)
429 status
= ql_sem_spinlock(qdev
, SEM_RT_IDX_MASK
);
433 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MW
, 0);
437 ql_write32(qdev
, RT_IDX
,
438 RT_IDX_TYPE_NICQ
| RT_IDX_RS
| (index
<< RT_IDX_IDX_SHIFT
));
439 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MR
, 0);
442 *value
= ql_read32(qdev
, RT_DATA
);
444 ql_sem_unlock(qdev
, SEM_RT_IDX_MASK
);
448 /* The NIC function for this chip has 16 routing indexes. Each one can be used
449 * to route different frame types to various inbound queues. We send broadcast/
450 * multicast/error frames to the default queue for slow handling,
451 * and CAM hit/RSS frames to the fast handling queues.
453 static int ql_set_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32 mask
,
459 status
= ql_sem_spinlock(qdev
, SEM_RT_IDX_MASK
);
463 QPRINTK(qdev
, IFUP
, DEBUG
,
464 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
465 (enable
? "Adding" : "Removing"),
466 ((index
== RT_IDX_ALL_ERR_SLOT
) ? "MAC ERROR/ALL ERROR" : ""),
467 ((index
== RT_IDX_IP_CSUM_ERR_SLOT
) ? "IP CSUM ERROR" : ""),
469 RT_IDX_TCP_UDP_CSUM_ERR_SLOT
) ? "TCP/UDP CSUM ERROR" : ""),
470 ((index
== RT_IDX_BCAST_SLOT
) ? "BROADCAST" : ""),
471 ((index
== RT_IDX_MCAST_MATCH_SLOT
) ? "MULTICAST MATCH" : ""),
472 ((index
== RT_IDX_ALLMULTI_SLOT
) ? "ALL MULTICAST MATCH" : ""),
473 ((index
== RT_IDX_UNUSED6_SLOT
) ? "UNUSED6" : ""),
474 ((index
== RT_IDX_UNUSED7_SLOT
) ? "UNUSED7" : ""),
475 ((index
== RT_IDX_RSS_MATCH_SLOT
) ? "RSS ALL/IPV4 MATCH" : ""),
476 ((index
== RT_IDX_RSS_IPV6_SLOT
) ? "RSS IPV6" : ""),
477 ((index
== RT_IDX_RSS_TCP4_SLOT
) ? "RSS TCP4" : ""),
478 ((index
== RT_IDX_RSS_TCP6_SLOT
) ? "RSS TCP6" : ""),
479 ((index
== RT_IDX_CAM_HIT_SLOT
) ? "CAM HIT" : ""),
480 ((index
== RT_IDX_UNUSED013
) ? "UNUSED13" : ""),
481 ((index
== RT_IDX_UNUSED014
) ? "UNUSED14" : ""),
482 ((index
== RT_IDX_PROMISCUOUS_SLOT
) ? "PROMISCUOUS" : ""),
483 (enable
? "to" : "from"));
488 value
= RT_IDX_DST_CAM_Q
| /* dest */
489 RT_IDX_TYPE_NICQ
| /* type */
490 (RT_IDX_CAM_HIT_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
493 case RT_IDX_VALID
: /* Promiscuous Mode frames. */
495 value
= RT_IDX_DST_DFLT_Q
| /* dest */
496 RT_IDX_TYPE_NICQ
| /* type */
497 (RT_IDX_PROMISCUOUS_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
500 case RT_IDX_ERR
: /* Pass up MAC,IP,TCP/UDP error frames. */
502 value
= RT_IDX_DST_DFLT_Q
| /* dest */
503 RT_IDX_TYPE_NICQ
| /* type */
504 (RT_IDX_ALL_ERR_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
507 case RT_IDX_BCAST
: /* Pass up Broadcast frames to default Q. */
509 value
= RT_IDX_DST_DFLT_Q
| /* dest */
510 RT_IDX_TYPE_NICQ
| /* type */
511 (RT_IDX_BCAST_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
514 case RT_IDX_MCAST
: /* Pass up All Multicast frames. */
516 value
= RT_IDX_DST_CAM_Q
| /* dest */
517 RT_IDX_TYPE_NICQ
| /* type */
518 (RT_IDX_ALLMULTI_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
521 case RT_IDX_MCAST_MATCH
: /* Pass up matched Multicast frames. */
523 value
= RT_IDX_DST_CAM_Q
| /* dest */
524 RT_IDX_TYPE_NICQ
| /* type */
525 (RT_IDX_MCAST_MATCH_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
528 case RT_IDX_RSS_MATCH
: /* Pass up matched RSS frames. */
530 value
= RT_IDX_DST_RSS
| /* dest */
531 RT_IDX_TYPE_NICQ
| /* type */
532 (RT_IDX_RSS_MATCH_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
535 case 0: /* Clear the E-bit on an entry. */
537 value
= RT_IDX_DST_DFLT_Q
| /* dest */
538 RT_IDX_TYPE_NICQ
| /* type */
539 (index
<< RT_IDX_IDX_SHIFT
);/* index */
543 QPRINTK(qdev
, IFUP
, ERR
, "Mask type %d not yet supported.\n",
550 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MW
, 0);
553 value
|= (enable
? RT_IDX_E
: 0);
554 ql_write32(qdev
, RT_IDX
, value
);
555 ql_write32(qdev
, RT_DATA
, enable
? mask
: 0);
558 ql_sem_unlock(qdev
, SEM_RT_IDX_MASK
);
562 static void ql_enable_interrupts(struct ql_adapter
*qdev
)
564 ql_write32(qdev
, INTR_EN
, (INTR_EN_EI
<< 16) | INTR_EN_EI
);
567 static void ql_disable_interrupts(struct ql_adapter
*qdev
)
569 ql_write32(qdev
, INTR_EN
, (INTR_EN_EI
<< 16));
572 /* If we're running with multiple MSI-X vectors then we enable on the fly.
573 * Otherwise, we may have multiple outstanding workers and don't want to
574 * enable until the last one finishes. In this case, the irq_cnt gets
575 * incremented everytime we queue a worker and decremented everytime
576 * a worker finishes. Once it hits zero we enable the interrupt.
578 u32
ql_enable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
)
581 unsigned long hw_flags
= 0;
582 struct intr_context
*ctx
= qdev
->intr_context
+ intr
;
584 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) && intr
)) {
585 /* Always enable if we're MSIX multi interrupts and
586 * it's not the default (zeroeth) interrupt.
588 ql_write32(qdev
, INTR_EN
,
590 var
= ql_read32(qdev
, STS
);
594 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
595 if (atomic_dec_and_test(&ctx
->irq_cnt
)) {
596 ql_write32(qdev
, INTR_EN
,
598 var
= ql_read32(qdev
, STS
);
600 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
604 static u32
ql_disable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
)
607 unsigned long hw_flags
;
608 struct intr_context
*ctx
;
610 /* HW disables for us if we're MSIX multi interrupts and
611 * it's not the default (zeroeth) interrupt.
613 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) && intr
))
616 ctx
= qdev
->intr_context
+ intr
;
617 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
618 if (!atomic_read(&ctx
->irq_cnt
)) {
619 ql_write32(qdev
, INTR_EN
,
621 var
= ql_read32(qdev
, STS
);
623 atomic_inc(&ctx
->irq_cnt
);
624 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
628 static void ql_enable_all_completion_interrupts(struct ql_adapter
*qdev
)
631 for (i
= 0; i
< qdev
->intr_count
; i
++) {
632 /* The enable call does a atomic_dec_and_test
633 * and enables only if the result is zero.
634 * So we precharge it here.
636 if (unlikely(!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) ||
638 atomic_set(&qdev
->intr_context
[i
].irq_cnt
, 1);
639 ql_enable_completion_interrupt(qdev
, i
);
644 static int ql_read_flash_word(struct ql_adapter
*qdev
, int offset
, u32
*data
)
647 /* wait for reg to come ready */
648 status
= ql_wait_reg_rdy(qdev
,
649 FLASH_ADDR
, FLASH_ADDR_RDY
, FLASH_ADDR_ERR
);
652 /* set up for reg read */
653 ql_write32(qdev
, FLASH_ADDR
, FLASH_ADDR_R
| offset
);
654 /* wait for reg to come ready */
655 status
= ql_wait_reg_rdy(qdev
,
656 FLASH_ADDR
, FLASH_ADDR_RDY
, FLASH_ADDR_ERR
);
660 *data
= ql_read32(qdev
, FLASH_DATA
);
665 static int ql_get_flash_params(struct ql_adapter
*qdev
)
669 u32
*p
= (u32
*)&qdev
->flash
;
671 if (ql_sem_spinlock(qdev
, SEM_FLASH_MASK
))
674 for (i
= 0; i
< sizeof(qdev
->flash
) / sizeof(u32
); i
++, p
++) {
675 status
= ql_read_flash_word(qdev
, i
, p
);
677 QPRINTK(qdev
, IFUP
, ERR
, "Error reading flash.\n");
683 ql_sem_unlock(qdev
, SEM_FLASH_MASK
);
687 /* xgmac register are located behind the xgmac_addr and xgmac_data
688 * register pair. Each read/write requires us to wait for the ready
689 * bit before reading/writing the data.
691 static int ql_write_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32 data
)
694 /* wait for reg to come ready */
695 status
= ql_wait_reg_rdy(qdev
,
696 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
699 /* write the data to the data reg */
700 ql_write32(qdev
, XGMAC_DATA
, data
);
701 /* trigger the write */
702 ql_write32(qdev
, XGMAC_ADDR
, reg
);
706 /* xgmac register are located behind the xgmac_addr and xgmac_data
707 * register pair. Each read/write requires us to wait for the ready
708 * bit before reading/writing the data.
710 int ql_read_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32
*data
)
713 /* wait for reg to come ready */
714 status
= ql_wait_reg_rdy(qdev
,
715 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
718 /* set up for reg read */
719 ql_write32(qdev
, XGMAC_ADDR
, reg
| XGMAC_ADDR_R
);
720 /* wait for reg to come ready */
721 status
= ql_wait_reg_rdy(qdev
,
722 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
726 *data
= ql_read32(qdev
, XGMAC_DATA
);
731 /* This is used for reading the 64-bit statistics regs. */
732 int ql_read_xgmac_reg64(struct ql_adapter
*qdev
, u32 reg
, u64
*data
)
738 status
= ql_read_xgmac_reg(qdev
, reg
, &lo
);
742 status
= ql_read_xgmac_reg(qdev
, reg
+ 4, &hi
);
746 *data
= (u64
) lo
| ((u64
) hi
<< 32);
752 /* Take the MAC Core out of reset.
753 * Enable statistics counting.
754 * Take the transmitter/receiver out of reset.
755 * This functionality may be done in the MPI firmware at a
758 static int ql_port_initialize(struct ql_adapter
*qdev
)
763 if (ql_sem_trylock(qdev
, qdev
->xg_sem_mask
)) {
764 /* Another function has the semaphore, so
765 * wait for the port init bit to come ready.
767 QPRINTK(qdev
, LINK
, INFO
,
768 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
769 status
= ql_wait_reg_rdy(qdev
, STS
, qdev
->port_init
, 0);
771 QPRINTK(qdev
, LINK
, CRIT
,
772 "Port initialize timed out.\n");
777 QPRINTK(qdev
, LINK
, INFO
, "Got xgmac semaphore!.\n");
778 /* Set the core reset. */
779 status
= ql_read_xgmac_reg(qdev
, GLOBAL_CFG
, &data
);
782 data
|= GLOBAL_CFG_RESET
;
783 status
= ql_write_xgmac_reg(qdev
, GLOBAL_CFG
, data
);
787 /* Clear the core reset and turn on jumbo for receiver. */
788 data
&= ~GLOBAL_CFG_RESET
; /* Clear core reset. */
789 data
|= GLOBAL_CFG_JUMBO
; /* Turn on jumbo. */
790 data
|= GLOBAL_CFG_TX_STAT_EN
;
791 data
|= GLOBAL_CFG_RX_STAT_EN
;
792 status
= ql_write_xgmac_reg(qdev
, GLOBAL_CFG
, data
);
796 /* Enable transmitter, and clear it's reset. */
797 status
= ql_read_xgmac_reg(qdev
, TX_CFG
, &data
);
800 data
&= ~TX_CFG_RESET
; /* Clear the TX MAC reset. */
801 data
|= TX_CFG_EN
; /* Enable the transmitter. */
802 status
= ql_write_xgmac_reg(qdev
, TX_CFG
, data
);
806 /* Enable receiver and clear it's reset. */
807 status
= ql_read_xgmac_reg(qdev
, RX_CFG
, &data
);
810 data
&= ~RX_CFG_RESET
; /* Clear the RX MAC reset. */
811 data
|= RX_CFG_EN
; /* Enable the receiver. */
812 status
= ql_write_xgmac_reg(qdev
, RX_CFG
, data
);
818 ql_write_xgmac_reg(qdev
, MAC_TX_PARAMS
, MAC_TX_PARAMS_JUMBO
| (0x2580 << 16));
822 ql_write_xgmac_reg(qdev
, MAC_RX_PARAMS
, 0x2580);
826 /* Signal to the world that the port is enabled. */
827 ql_write32(qdev
, STS
, ((qdev
->port_init
<< 16) | qdev
->port_init
));
829 ql_sem_unlock(qdev
, qdev
->xg_sem_mask
);
833 /* Get the next large buffer. */
834 static struct bq_desc
*ql_get_curr_lbuf(struct rx_ring
*rx_ring
)
836 struct bq_desc
*lbq_desc
= &rx_ring
->lbq
[rx_ring
->lbq_curr_idx
];
837 rx_ring
->lbq_curr_idx
++;
838 if (rx_ring
->lbq_curr_idx
== rx_ring
->lbq_len
)
839 rx_ring
->lbq_curr_idx
= 0;
840 rx_ring
->lbq_free_cnt
++;
844 /* Get the next small buffer. */
845 static struct bq_desc
*ql_get_curr_sbuf(struct rx_ring
*rx_ring
)
847 struct bq_desc
*sbq_desc
= &rx_ring
->sbq
[rx_ring
->sbq_curr_idx
];
848 rx_ring
->sbq_curr_idx
++;
849 if (rx_ring
->sbq_curr_idx
== rx_ring
->sbq_len
)
850 rx_ring
->sbq_curr_idx
= 0;
851 rx_ring
->sbq_free_cnt
++;
855 /* Update an rx ring index. */
856 static void ql_update_cq(struct rx_ring
*rx_ring
)
858 rx_ring
->cnsmr_idx
++;
859 rx_ring
->curr_entry
++;
860 if (unlikely(rx_ring
->cnsmr_idx
== rx_ring
->cq_len
)) {
861 rx_ring
->cnsmr_idx
= 0;
862 rx_ring
->curr_entry
= rx_ring
->cq_base
;
866 static void ql_write_cq_idx(struct rx_ring
*rx_ring
)
868 ql_write_db_reg(rx_ring
->cnsmr_idx
, rx_ring
->cnsmr_idx_db_reg
);
871 /* Process (refill) a large buffer queue. */
872 static void ql_update_lbq(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
874 int clean_idx
= rx_ring
->lbq_clean_idx
;
875 struct bq_desc
*lbq_desc
;
879 while (rx_ring
->lbq_free_cnt
> 16) {
880 for (i
= 0; i
< 16; i
++) {
881 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
882 "lbq: try cleaning clean_idx = %d.\n",
884 lbq_desc
= &rx_ring
->lbq
[clean_idx
];
885 if (lbq_desc
->p
.lbq_page
== NULL
) {
886 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
887 "lbq: getting new page for index %d.\n",
889 lbq_desc
->p
.lbq_page
= alloc_page(GFP_ATOMIC
);
890 if (lbq_desc
->p
.lbq_page
== NULL
) {
891 QPRINTK(qdev
, RX_STATUS
, ERR
,
892 "Couldn't get a page.\n");
895 map
= pci_map_page(qdev
->pdev
,
896 lbq_desc
->p
.lbq_page
,
899 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
900 QPRINTK(qdev
, RX_STATUS
, ERR
,
901 "PCI mapping failed.\n");
904 pci_unmap_addr_set(lbq_desc
, mapaddr
, map
);
905 pci_unmap_len_set(lbq_desc
, maplen
, PAGE_SIZE
);
906 *lbq_desc
->addr
= cpu_to_le64(map
);
909 if (clean_idx
== rx_ring
->lbq_len
)
913 rx_ring
->lbq_clean_idx
= clean_idx
;
914 rx_ring
->lbq_prod_idx
+= 16;
915 if (rx_ring
->lbq_prod_idx
== rx_ring
->lbq_len
)
916 rx_ring
->lbq_prod_idx
= 0;
917 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
918 "lbq: updating prod idx = %d.\n",
919 rx_ring
->lbq_prod_idx
);
920 ql_write_db_reg(rx_ring
->lbq_prod_idx
,
921 rx_ring
->lbq_prod_idx_db_reg
);
922 rx_ring
->lbq_free_cnt
-= 16;
926 /* Process (refill) a small buffer queue. */
927 static void ql_update_sbq(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
929 int clean_idx
= rx_ring
->sbq_clean_idx
;
930 struct bq_desc
*sbq_desc
;
934 while (rx_ring
->sbq_free_cnt
> 16) {
935 for (i
= 0; i
< 16; i
++) {
936 sbq_desc
= &rx_ring
->sbq
[clean_idx
];
937 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
938 "sbq: try cleaning clean_idx = %d.\n",
940 if (sbq_desc
->p
.skb
== NULL
) {
941 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
942 "sbq: getting new skb for index %d.\n",
945 netdev_alloc_skb(qdev
->ndev
,
946 rx_ring
->sbq_buf_size
);
947 if (sbq_desc
->p
.skb
== NULL
) {
948 QPRINTK(qdev
, PROBE
, ERR
,
949 "Couldn't get an skb.\n");
950 rx_ring
->sbq_clean_idx
= clean_idx
;
953 skb_reserve(sbq_desc
->p
.skb
, QLGE_SB_PAD
);
954 map
= pci_map_single(qdev
->pdev
,
955 sbq_desc
->p
.skb
->data
,
956 rx_ring
->sbq_buf_size
/
957 2, PCI_DMA_FROMDEVICE
);
958 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
959 QPRINTK(qdev
, IFUP
, ERR
, "PCI mapping failed.\n");
960 rx_ring
->sbq_clean_idx
= clean_idx
;
963 pci_unmap_addr_set(sbq_desc
, mapaddr
, map
);
964 pci_unmap_len_set(sbq_desc
, maplen
,
965 rx_ring
->sbq_buf_size
/ 2);
966 *sbq_desc
->addr
= cpu_to_le64(map
);
970 if (clean_idx
== rx_ring
->sbq_len
)
973 rx_ring
->sbq_clean_idx
= clean_idx
;
974 rx_ring
->sbq_prod_idx
+= 16;
975 if (rx_ring
->sbq_prod_idx
== rx_ring
->sbq_len
)
976 rx_ring
->sbq_prod_idx
= 0;
977 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
978 "sbq: updating prod idx = %d.\n",
979 rx_ring
->sbq_prod_idx
);
980 ql_write_db_reg(rx_ring
->sbq_prod_idx
,
981 rx_ring
->sbq_prod_idx_db_reg
);
983 rx_ring
->sbq_free_cnt
-= 16;
987 static void ql_update_buffer_queues(struct ql_adapter
*qdev
,
988 struct rx_ring
*rx_ring
)
990 ql_update_sbq(qdev
, rx_ring
);
991 ql_update_lbq(qdev
, rx_ring
);
994 /* Unmaps tx buffers. Can be called from send() if a pci mapping
995 * fails at some stage, or from the interrupt when a tx completes.
997 static void ql_unmap_send(struct ql_adapter
*qdev
,
998 struct tx_ring_desc
*tx_ring_desc
, int mapped
)
1001 for (i
= 0; i
< mapped
; i
++) {
1002 if (i
== 0 || (i
== 7 && mapped
> 7)) {
1004 * Unmap the skb->data area, or the
1005 * external sglist (AKA the Outbound
1006 * Address List (OAL)).
1007 * If its the zeroeth element, then it's
1008 * the skb->data area. If it's the 7th
1009 * element and there is more than 6 frags,
1013 QPRINTK(qdev
, TX_DONE
, DEBUG
,
1014 "unmapping OAL area.\n");
1016 pci_unmap_single(qdev
->pdev
,
1017 pci_unmap_addr(&tx_ring_desc
->map
[i
],
1019 pci_unmap_len(&tx_ring_desc
->map
[i
],
1023 QPRINTK(qdev
, TX_DONE
, DEBUG
, "unmapping frag %d.\n",
1025 pci_unmap_page(qdev
->pdev
,
1026 pci_unmap_addr(&tx_ring_desc
->map
[i
],
1028 pci_unmap_len(&tx_ring_desc
->map
[i
],
1029 maplen
), PCI_DMA_TODEVICE
);
1035 /* Map the buffers for this transmit. This will return
1036 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1038 static int ql_map_send(struct ql_adapter
*qdev
,
1039 struct ob_mac_iocb_req
*mac_iocb_ptr
,
1040 struct sk_buff
*skb
, struct tx_ring_desc
*tx_ring_desc
)
1042 int len
= skb_headlen(skb
);
1044 int frag_idx
, err
, map_idx
= 0;
1045 struct tx_buf_desc
*tbd
= mac_iocb_ptr
->tbd
;
1046 int frag_cnt
= skb_shinfo(skb
)->nr_frags
;
1049 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "frag_cnt = %d.\n", frag_cnt
);
1052 * Map the skb buffer first.
1054 map
= pci_map_single(qdev
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1056 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1058 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1059 "PCI mapping failed with error: %d\n", err
);
1061 return NETDEV_TX_BUSY
;
1064 tbd
->len
= cpu_to_le32(len
);
1065 tbd
->addr
= cpu_to_le64(map
);
1066 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
, map
);
1067 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
, len
);
1071 * This loop fills the remainder of the 8 address descriptors
1072 * in the IOCB. If there are more than 7 fragments, then the
1073 * eighth address desc will point to an external list (OAL).
1074 * When this happens, the remainder of the frags will be stored
1077 for (frag_idx
= 0; frag_idx
< frag_cnt
; frag_idx
++, map_idx
++) {
1078 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[frag_idx
];
1080 if (frag_idx
== 6 && frag_cnt
> 7) {
1081 /* Let's tack on an sglist.
1082 * Our control block will now
1084 * iocb->seg[0] = skb->data
1085 * iocb->seg[1] = frag[0]
1086 * iocb->seg[2] = frag[1]
1087 * iocb->seg[3] = frag[2]
1088 * iocb->seg[4] = frag[3]
1089 * iocb->seg[5] = frag[4]
1090 * iocb->seg[6] = frag[5]
1091 * iocb->seg[7] = ptr to OAL (external sglist)
1092 * oal->seg[0] = frag[6]
1093 * oal->seg[1] = frag[7]
1094 * oal->seg[2] = frag[8]
1095 * oal->seg[3] = frag[9]
1096 * oal->seg[4] = frag[10]
1099 /* Tack on the OAL in the eighth segment of IOCB. */
1100 map
= pci_map_single(qdev
->pdev
, &tx_ring_desc
->oal
,
1103 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1105 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1106 "PCI mapping outbound address list with error: %d\n",
1111 tbd
->addr
= cpu_to_le64(map
);
1113 * The length is the number of fragments
1114 * that remain to be mapped times the length
1115 * of our sglist (OAL).
1118 cpu_to_le32((sizeof(struct tx_buf_desc
) *
1119 (frag_cnt
- frag_idx
)) | TX_DESC_C
);
1120 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
,
1122 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
,
1123 sizeof(struct oal
));
1124 tbd
= (struct tx_buf_desc
*)&tx_ring_desc
->oal
;
1129 pci_map_page(qdev
->pdev
, frag
->page
,
1130 frag
->page_offset
, frag
->size
,
1133 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1135 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1136 "PCI mapping frags failed with error: %d.\n",
1141 tbd
->addr
= cpu_to_le64(map
);
1142 tbd
->len
= cpu_to_le32(frag
->size
);
1143 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
, map
);
1144 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
,
1148 /* Save the number of segments we've mapped. */
1149 tx_ring_desc
->map_cnt
= map_idx
;
1150 /* Terminate the last segment. */
1151 tbd
->len
= cpu_to_le32(le32_to_cpu(tbd
->len
) | TX_DESC_E
);
1152 return NETDEV_TX_OK
;
1156 * If the first frag mapping failed, then i will be zero.
1157 * This causes the unmap of the skb->data area. Otherwise
1158 * we pass in the number of frags that mapped successfully
1159 * so they can be umapped.
1161 ql_unmap_send(qdev
, tx_ring_desc
, map_idx
);
1162 return NETDEV_TX_BUSY
;
1165 static void ql_realign_skb(struct sk_buff
*skb
, int len
)
1167 void *temp_addr
= skb
->data
;
1169 /* Undo the skb_reserve(skb,32) we did before
1170 * giving to hardware, and realign data on
1171 * a 2-byte boundary.
1173 skb
->data
-= QLGE_SB_PAD
- NET_IP_ALIGN
;
1174 skb
->tail
-= QLGE_SB_PAD
- NET_IP_ALIGN
;
1175 skb_copy_to_linear_data(skb
, temp_addr
,
1180 * This function builds an skb for the given inbound
1181 * completion. It will be rewritten for readability in the near
1182 * future, but for not it works well.
1184 static struct sk_buff
*ql_build_rx_skb(struct ql_adapter
*qdev
,
1185 struct rx_ring
*rx_ring
,
1186 struct ib_mac_iocb_rsp
*ib_mac_rsp
)
1188 struct bq_desc
*lbq_desc
;
1189 struct bq_desc
*sbq_desc
;
1190 struct sk_buff
*skb
= NULL
;
1191 u32 length
= le32_to_cpu(ib_mac_rsp
->data_len
);
1192 u32 hdr_len
= le32_to_cpu(ib_mac_rsp
->hdr_len
);
1195 * Handle the header buffer if present.
1197 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HV
&&
1198 ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1199 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Header of %d bytes in small buffer.\n", hdr_len
);
1201 * Headers fit nicely into a small buffer.
1203 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1204 pci_unmap_single(qdev
->pdev
,
1205 pci_unmap_addr(sbq_desc
, mapaddr
),
1206 pci_unmap_len(sbq_desc
, maplen
),
1207 PCI_DMA_FROMDEVICE
);
1208 skb
= sbq_desc
->p
.skb
;
1209 ql_realign_skb(skb
, hdr_len
);
1210 skb_put(skb
, hdr_len
);
1211 sbq_desc
->p
.skb
= NULL
;
1215 * Handle the data buffer(s).
1217 if (unlikely(!length
)) { /* Is there data too? */
1218 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1219 "No Data buffer in this packet.\n");
1223 if (ib_mac_rsp
->flags3
& IB_MAC_IOCB_RSP_DS
) {
1224 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1225 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1226 "Headers in small, data of %d bytes in small, combine them.\n", length
);
1228 * Data is less than small buffer size so it's
1229 * stuffed in a small buffer.
1230 * For this case we append the data
1231 * from the "data" small buffer to the "header" small
1234 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1235 pci_dma_sync_single_for_cpu(qdev
->pdev
,
1237 (sbq_desc
, mapaddr
),
1240 PCI_DMA_FROMDEVICE
);
1241 memcpy(skb_put(skb
, length
),
1242 sbq_desc
->p
.skb
->data
, length
);
1243 pci_dma_sync_single_for_device(qdev
->pdev
,
1250 PCI_DMA_FROMDEVICE
);
1252 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1253 "%d bytes in a single small buffer.\n", length
);
1254 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1255 skb
= sbq_desc
->p
.skb
;
1256 ql_realign_skb(skb
, length
);
1257 skb_put(skb
, length
);
1258 pci_unmap_single(qdev
->pdev
,
1259 pci_unmap_addr(sbq_desc
,
1261 pci_unmap_len(sbq_desc
,
1263 PCI_DMA_FROMDEVICE
);
1264 sbq_desc
->p
.skb
= NULL
;
1266 } else if (ib_mac_rsp
->flags3
& IB_MAC_IOCB_RSP_DL
) {
1267 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1268 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1269 "Header in small, %d bytes in large. Chain large to small!\n", length
);
1271 * The data is in a single large buffer. We
1272 * chain it to the header buffer's skb and let
1275 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1276 pci_unmap_page(qdev
->pdev
,
1277 pci_unmap_addr(lbq_desc
,
1279 pci_unmap_len(lbq_desc
, maplen
),
1280 PCI_DMA_FROMDEVICE
);
1281 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1282 "Chaining page to skb.\n");
1283 skb_fill_page_desc(skb
, 0, lbq_desc
->p
.lbq_page
,
1286 skb
->data_len
+= length
;
1287 skb
->truesize
+= length
;
1288 lbq_desc
->p
.lbq_page
= NULL
;
1291 * The headers and data are in a single large buffer. We
1292 * copy it to a new skb and let it go. This can happen with
1293 * jumbo mtu on a non-TCP/UDP frame.
1295 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1296 skb
= netdev_alloc_skb(qdev
->ndev
, length
);
1298 QPRINTK(qdev
, PROBE
, DEBUG
,
1299 "No skb available, drop the packet.\n");
1302 pci_unmap_page(qdev
->pdev
,
1303 pci_unmap_addr(lbq_desc
,
1305 pci_unmap_len(lbq_desc
, maplen
),
1306 PCI_DMA_FROMDEVICE
);
1307 skb_reserve(skb
, NET_IP_ALIGN
);
1308 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1309 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length
);
1310 skb_fill_page_desc(skb
, 0, lbq_desc
->p
.lbq_page
,
1313 skb
->data_len
+= length
;
1314 skb
->truesize
+= length
;
1316 lbq_desc
->p
.lbq_page
= NULL
;
1317 __pskb_pull_tail(skb
,
1318 (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
) ?
1319 VLAN_ETH_HLEN
: ETH_HLEN
);
1323 * The data is in a chain of large buffers
1324 * pointed to by a small buffer. We loop
1325 * thru and chain them to the our small header
1327 * frags: There are 18 max frags and our small
1328 * buffer will hold 32 of them. The thing is,
1329 * we'll use 3 max for our 9000 byte jumbo
1330 * frames. If the MTU goes up we could
1331 * eventually be in trouble.
1333 int size
, offset
, i
= 0;
1334 __le64
*bq
, bq_array
[8];
1335 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1336 pci_unmap_single(qdev
->pdev
,
1337 pci_unmap_addr(sbq_desc
, mapaddr
),
1338 pci_unmap_len(sbq_desc
, maplen
),
1339 PCI_DMA_FROMDEVICE
);
1340 if (!(ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
)) {
1342 * This is an non TCP/UDP IP frame, so
1343 * the headers aren't split into a small
1344 * buffer. We have to use the small buffer
1345 * that contains our sg list as our skb to
1346 * send upstairs. Copy the sg list here to
1347 * a local buffer and use it to find the
1350 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1351 "%d bytes of headers & data in chain of large.\n", length
);
1352 skb
= sbq_desc
->p
.skb
;
1354 memcpy(bq
, skb
->data
, sizeof(bq_array
));
1355 sbq_desc
->p
.skb
= NULL
;
1356 skb_reserve(skb
, NET_IP_ALIGN
);
1358 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1359 "Headers in small, %d bytes of data in chain of large.\n", length
);
1360 bq
= (__le64
*)sbq_desc
->p
.skb
->data
;
1362 while (length
> 0) {
1363 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1364 pci_unmap_page(qdev
->pdev
,
1365 pci_unmap_addr(lbq_desc
,
1367 pci_unmap_len(lbq_desc
,
1369 PCI_DMA_FROMDEVICE
);
1370 size
= (length
< PAGE_SIZE
) ? length
: PAGE_SIZE
;
1373 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1374 "Adding page %d to skb for %d bytes.\n",
1376 skb_fill_page_desc(skb
, i
, lbq_desc
->p
.lbq_page
,
1379 skb
->data_len
+= size
;
1380 skb
->truesize
+= size
;
1382 lbq_desc
->p
.lbq_page
= NULL
;
1386 __pskb_pull_tail(skb
, (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
) ?
1387 VLAN_ETH_HLEN
: ETH_HLEN
);
1392 /* Process an inbound completion from an rx ring. */
1393 static void ql_process_mac_rx_intr(struct ql_adapter
*qdev
,
1394 struct rx_ring
*rx_ring
,
1395 struct ib_mac_iocb_rsp
*ib_mac_rsp
)
1397 struct net_device
*ndev
= qdev
->ndev
;
1398 struct sk_buff
*skb
= NULL
;
1400 QL_DUMP_IB_MAC_RSP(ib_mac_rsp
);
1402 skb
= ql_build_rx_skb(qdev
, rx_ring
, ib_mac_rsp
);
1403 if (unlikely(!skb
)) {
1404 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1405 "No skb available, drop packet.\n");
1409 prefetch(skb
->data
);
1411 if (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) {
1412 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "%s%s%s Multicast.\n",
1413 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1414 IB_MAC_IOCB_RSP_M_HASH
? "Hash" : "",
1415 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1416 IB_MAC_IOCB_RSP_M_REG
? "Registered" : "",
1417 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1418 IB_MAC_IOCB_RSP_M_PROM
? "Promiscuous" : "");
1420 if (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_P
) {
1421 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Promiscuous Packet.\n");
1423 if (ib_mac_rsp
->flags1
& (IB_MAC_IOCB_RSP_IE
| IB_MAC_IOCB_RSP_TE
)) {
1424 QPRINTK(qdev
, RX_STATUS
, ERR
,
1425 "Bad checksum for this %s packet.\n",
1427 flags2
& IB_MAC_IOCB_RSP_T
) ? "TCP" : "UDP"));
1428 skb
->ip_summed
= CHECKSUM_NONE
;
1429 } else if (qdev
->rx_csum
&&
1430 ((ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_T
) ||
1431 ((ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_U
) &&
1432 !(ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_NU
)))) {
1433 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "RX checksum done!\n");
1434 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1436 qdev
->stats
.rx_packets
++;
1437 qdev
->stats
.rx_bytes
+= skb
->len
;
1438 skb
->protocol
= eth_type_trans(skb
, ndev
);
1439 if (qdev
->vlgrp
&& (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
)) {
1440 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1441 "Passing a VLAN packet upstream.\n");
1442 vlan_hwaccel_rx(skb
, qdev
->vlgrp
,
1443 le16_to_cpu(ib_mac_rsp
->vlan_id
));
1445 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1446 "Passing a normal packet upstream.\n");
1451 /* Process an outbound completion from an rx ring. */
1452 static void ql_process_mac_tx_intr(struct ql_adapter
*qdev
,
1453 struct ob_mac_iocb_rsp
*mac_rsp
)
1455 struct tx_ring
*tx_ring
;
1456 struct tx_ring_desc
*tx_ring_desc
;
1458 QL_DUMP_OB_MAC_RSP(mac_rsp
);
1459 tx_ring
= &qdev
->tx_ring
[mac_rsp
->txq_idx
];
1460 tx_ring_desc
= &tx_ring
->q
[mac_rsp
->tid
];
1461 ql_unmap_send(qdev
, tx_ring_desc
, tx_ring_desc
->map_cnt
);
1462 qdev
->stats
.tx_bytes
+= tx_ring_desc
->map_cnt
;
1463 qdev
->stats
.tx_packets
++;
1464 dev_kfree_skb(tx_ring_desc
->skb
);
1465 tx_ring_desc
->skb
= NULL
;
1467 if (unlikely(mac_rsp
->flags1
& (OB_MAC_IOCB_RSP_E
|
1470 OB_MAC_IOCB_RSP_P
| OB_MAC_IOCB_RSP_B
))) {
1471 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_E
) {
1472 QPRINTK(qdev
, TX_DONE
, WARNING
,
1473 "Total descriptor length did not match transfer length.\n");
1475 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_S
) {
1476 QPRINTK(qdev
, TX_DONE
, WARNING
,
1477 "Frame too short to be legal, not sent.\n");
1479 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_L
) {
1480 QPRINTK(qdev
, TX_DONE
, WARNING
,
1481 "Frame too long, but sent anyway.\n");
1483 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_B
) {
1484 QPRINTK(qdev
, TX_DONE
, WARNING
,
1485 "PCI backplane error. Frame not sent.\n");
1488 atomic_inc(&tx_ring
->tx_count
);
1491 /* Fire up a handler to reset the MPI processor. */
1492 void ql_queue_fw_error(struct ql_adapter
*qdev
)
1494 netif_stop_queue(qdev
->ndev
);
1495 netif_carrier_off(qdev
->ndev
);
1496 queue_delayed_work(qdev
->workqueue
, &qdev
->mpi_reset_work
, 0);
1499 void ql_queue_asic_error(struct ql_adapter
*qdev
)
1501 netif_stop_queue(qdev
->ndev
);
1502 netif_carrier_off(qdev
->ndev
);
1503 ql_disable_interrupts(qdev
);
1504 queue_delayed_work(qdev
->workqueue
, &qdev
->asic_reset_work
, 0);
1507 static void ql_process_chip_ae_intr(struct ql_adapter
*qdev
,
1508 struct ib_ae_iocb_rsp
*ib_ae_rsp
)
1510 switch (ib_ae_rsp
->event
) {
1511 case MGMT_ERR_EVENT
:
1512 QPRINTK(qdev
, RX_ERR
, ERR
,
1513 "Management Processor Fatal Error.\n");
1514 ql_queue_fw_error(qdev
);
1517 case CAM_LOOKUP_ERR_EVENT
:
1518 QPRINTK(qdev
, LINK
, ERR
,
1519 "Multiple CAM hits lookup occurred.\n");
1520 QPRINTK(qdev
, DRV
, ERR
, "This event shouldn't occur.\n");
1521 ql_queue_asic_error(qdev
);
1524 case SOFT_ECC_ERROR_EVENT
:
1525 QPRINTK(qdev
, RX_ERR
, ERR
, "Soft ECC error detected.\n");
1526 ql_queue_asic_error(qdev
);
1529 case PCI_ERR_ANON_BUF_RD
:
1530 QPRINTK(qdev
, RX_ERR
, ERR
,
1531 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1533 ql_queue_asic_error(qdev
);
1537 QPRINTK(qdev
, DRV
, ERR
, "Unexpected event %d.\n",
1539 ql_queue_asic_error(qdev
);
1544 static int ql_clean_outbound_rx_ring(struct rx_ring
*rx_ring
)
1546 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1547 u32 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1548 struct ob_mac_iocb_rsp
*net_rsp
= NULL
;
1551 /* While there are entries in the completion queue. */
1552 while (prod
!= rx_ring
->cnsmr_idx
) {
1554 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1555 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring
->cq_id
,
1556 prod
, rx_ring
->cnsmr_idx
);
1558 net_rsp
= (struct ob_mac_iocb_rsp
*)rx_ring
->curr_entry
;
1560 switch (net_rsp
->opcode
) {
1562 case OPCODE_OB_MAC_TSO_IOCB
:
1563 case OPCODE_OB_MAC_IOCB
:
1564 ql_process_mac_tx_intr(qdev
, net_rsp
);
1567 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1568 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1572 ql_update_cq(rx_ring
);
1573 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1575 ql_write_cq_idx(rx_ring
);
1576 if (netif_queue_stopped(qdev
->ndev
) && net_rsp
!= NULL
) {
1577 struct tx_ring
*tx_ring
= &qdev
->tx_ring
[net_rsp
->txq_idx
];
1578 if (atomic_read(&tx_ring
->queue_stopped
) &&
1579 (atomic_read(&tx_ring
->tx_count
) > (tx_ring
->wq_len
/ 4)))
1581 * The queue got stopped because the tx_ring was full.
1582 * Wake it up, because it's now at least 25% empty.
1584 netif_wake_queue(qdev
->ndev
);
1590 static int ql_clean_inbound_rx_ring(struct rx_ring
*rx_ring
, int budget
)
1592 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1593 u32 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1594 struct ql_net_rsp_iocb
*net_rsp
;
1597 /* While there are entries in the completion queue. */
1598 while (prod
!= rx_ring
->cnsmr_idx
) {
1600 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1601 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring
->cq_id
,
1602 prod
, rx_ring
->cnsmr_idx
);
1604 net_rsp
= rx_ring
->curr_entry
;
1606 switch (net_rsp
->opcode
) {
1607 case OPCODE_IB_MAC_IOCB
:
1608 ql_process_mac_rx_intr(qdev
, rx_ring
,
1609 (struct ib_mac_iocb_rsp
*)
1613 case OPCODE_IB_AE_IOCB
:
1614 ql_process_chip_ae_intr(qdev
, (struct ib_ae_iocb_rsp
*)
1619 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1620 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1625 ql_update_cq(rx_ring
);
1626 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1627 if (count
== budget
)
1630 ql_update_buffer_queues(qdev
, rx_ring
);
1631 ql_write_cq_idx(rx_ring
);
1635 static int ql_napi_poll_msix(struct napi_struct
*napi
, int budget
)
1637 struct rx_ring
*rx_ring
= container_of(napi
, struct rx_ring
, napi
);
1638 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1639 int work_done
= ql_clean_inbound_rx_ring(rx_ring
, budget
);
1641 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Enter, NAPI POLL cq_id = %d.\n",
1644 if (work_done
< budget
) {
1645 __netif_rx_complete(napi
);
1646 ql_enable_completion_interrupt(qdev
, rx_ring
->irq
);
1651 static void ql_vlan_rx_register(struct net_device
*ndev
, struct vlan_group
*grp
)
1653 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1657 QPRINTK(qdev
, IFUP
, DEBUG
, "Turning on VLAN in NIC_RCV_CFG.\n");
1658 ql_write32(qdev
, NIC_RCV_CFG
, NIC_RCV_CFG_VLAN_MASK
|
1659 NIC_RCV_CFG_VLAN_MATCH_AND_NON
);
1661 QPRINTK(qdev
, IFUP
, DEBUG
,
1662 "Turning off VLAN in NIC_RCV_CFG.\n");
1663 ql_write32(qdev
, NIC_RCV_CFG
, NIC_RCV_CFG_VLAN_MASK
);
1667 static void ql_vlan_rx_add_vid(struct net_device
*ndev
, u16 vid
)
1669 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1670 u32 enable_bit
= MAC_ADDR_E
;
1672 spin_lock(&qdev
->hw_lock
);
1673 if (ql_set_mac_addr_reg
1674 (qdev
, (u8
*) &enable_bit
, MAC_ADDR_TYPE_VLAN
, vid
)) {
1675 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init vlan address.\n");
1677 spin_unlock(&qdev
->hw_lock
);
1680 static void ql_vlan_rx_kill_vid(struct net_device
*ndev
, u16 vid
)
1682 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1685 spin_lock(&qdev
->hw_lock
);
1686 if (ql_set_mac_addr_reg
1687 (qdev
, (u8
*) &enable_bit
, MAC_ADDR_TYPE_VLAN
, vid
)) {
1688 QPRINTK(qdev
, IFUP
, ERR
, "Failed to clear vlan address.\n");
1690 spin_unlock(&qdev
->hw_lock
);
1694 /* Worker thread to process a given rx_ring that is dedicated
1695 * to outbound completions.
1697 static void ql_tx_clean(struct work_struct
*work
)
1699 struct rx_ring
*rx_ring
=
1700 container_of(work
, struct rx_ring
, rx_work
.work
);
1701 ql_clean_outbound_rx_ring(rx_ring
);
1702 ql_enable_completion_interrupt(rx_ring
->qdev
, rx_ring
->irq
);
1706 /* Worker thread to process a given rx_ring that is dedicated
1707 * to inbound completions.
1709 static void ql_rx_clean(struct work_struct
*work
)
1711 struct rx_ring
*rx_ring
=
1712 container_of(work
, struct rx_ring
, rx_work
.work
);
1713 ql_clean_inbound_rx_ring(rx_ring
, 64);
1714 ql_enable_completion_interrupt(rx_ring
->qdev
, rx_ring
->irq
);
1717 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1718 static irqreturn_t
qlge_msix_tx_isr(int irq
, void *dev_id
)
1720 struct rx_ring
*rx_ring
= dev_id
;
1721 queue_delayed_work_on(rx_ring
->cpu
, rx_ring
->qdev
->q_workqueue
,
1722 &rx_ring
->rx_work
, 0);
1726 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1727 static irqreturn_t
qlge_msix_rx_isr(int irq
, void *dev_id
)
1729 struct rx_ring
*rx_ring
= dev_id
;
1730 netif_rx_schedule(&rx_ring
->napi
);
1734 /* This handles a fatal error, MPI activity, and the default
1735 * rx_ring in an MSI-X multiple vector environment.
1736 * In MSI/Legacy environment it also process the rest of
1739 static irqreturn_t
qlge_isr(int irq
, void *dev_id
)
1741 struct rx_ring
*rx_ring
= dev_id
;
1742 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1743 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
1748 spin_lock(&qdev
->hw_lock
);
1749 if (atomic_read(&qdev
->intr_context
[0].irq_cnt
)) {
1750 QPRINTK(qdev
, INTR
, DEBUG
, "Shared Interrupt, Not ours!\n");
1751 spin_unlock(&qdev
->hw_lock
);
1754 spin_unlock(&qdev
->hw_lock
);
1756 var
= ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1759 * Check for fatal error.
1762 ql_queue_asic_error(qdev
);
1763 QPRINTK(qdev
, INTR
, ERR
, "Got fatal error, STS = %x.\n", var
);
1764 var
= ql_read32(qdev
, ERR_STS
);
1765 QPRINTK(qdev
, INTR
, ERR
,
1766 "Resetting chip. Error Status Register = 0x%x\n", var
);
1771 * Check MPI processor activity.
1775 * We've got an async event or mailbox completion.
1776 * Handle it and clear the source of the interrupt.
1778 QPRINTK(qdev
, INTR
, ERR
, "Got MPI processor interrupt.\n");
1779 ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1780 queue_delayed_work_on(smp_processor_id(), qdev
->workqueue
,
1781 &qdev
->mpi_work
, 0);
1786 * Check the default queue and wake handler if active.
1788 rx_ring
= &qdev
->rx_ring
[0];
1789 if (ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
) != rx_ring
->cnsmr_idx
) {
1790 QPRINTK(qdev
, INTR
, INFO
, "Waking handler for rx_ring[0].\n");
1791 ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1792 queue_delayed_work_on(smp_processor_id(), qdev
->q_workqueue
,
1793 &rx_ring
->rx_work
, 0);
1797 if (!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
1799 * Start the DPC for each active queue.
1801 for (i
= 1; i
< qdev
->rx_ring_count
; i
++) {
1802 rx_ring
= &qdev
->rx_ring
[i
];
1803 if (ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
) !=
1804 rx_ring
->cnsmr_idx
) {
1805 QPRINTK(qdev
, INTR
, INFO
,
1806 "Waking handler for rx_ring[%d].\n", i
);
1807 ql_disable_completion_interrupt(qdev
,
1810 if (i
< qdev
->rss_ring_first_cq_id
)
1811 queue_delayed_work_on(rx_ring
->cpu
,
1816 netif_rx_schedule(&rx_ring
->napi
);
1821 ql_enable_completion_interrupt(qdev
, intr_context
->intr
);
1822 return work_done
? IRQ_HANDLED
: IRQ_NONE
;
1825 static int ql_tso(struct sk_buff
*skb
, struct ob_mac_tso_iocb_req
*mac_iocb_ptr
)
1828 if (skb_is_gso(skb
)) {
1830 if (skb_header_cloned(skb
)) {
1831 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
1836 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_TSO_IOCB
;
1837 mac_iocb_ptr
->flags3
|= OB_MAC_TSO_IOCB_IC
;
1838 mac_iocb_ptr
->frame_len
= cpu_to_le32((u32
) skb
->len
);
1839 mac_iocb_ptr
->total_hdrs_len
=
1840 cpu_to_le16(skb_transport_offset(skb
) + tcp_hdrlen(skb
));
1841 mac_iocb_ptr
->net_trans_offset
=
1842 cpu_to_le16(skb_network_offset(skb
) |
1843 skb_transport_offset(skb
)
1844 << OB_MAC_TRANSPORT_HDR_SHIFT
);
1845 mac_iocb_ptr
->mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
);
1846 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_LSO
;
1847 if (likely(skb
->protocol
== htons(ETH_P_IP
))) {
1848 struct iphdr
*iph
= ip_hdr(skb
);
1850 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP4
;
1851 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
1855 } else if (skb
->protocol
== htons(ETH_P_IPV6
)) {
1856 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP6
;
1857 tcp_hdr(skb
)->check
=
1858 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
1859 &ipv6_hdr(skb
)->daddr
,
1867 static void ql_hw_csum_setup(struct sk_buff
*skb
,
1868 struct ob_mac_tso_iocb_req
*mac_iocb_ptr
)
1871 struct iphdr
*iph
= ip_hdr(skb
);
1873 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_TSO_IOCB
;
1874 mac_iocb_ptr
->frame_len
= cpu_to_le32((u32
) skb
->len
);
1875 mac_iocb_ptr
->net_trans_offset
=
1876 cpu_to_le16(skb_network_offset(skb
) |
1877 skb_transport_offset(skb
) << OB_MAC_TRANSPORT_HDR_SHIFT
);
1879 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP4
;
1880 len
= (ntohs(iph
->tot_len
) - (iph
->ihl
<< 2));
1881 if (likely(iph
->protocol
== IPPROTO_TCP
)) {
1882 check
= &(tcp_hdr(skb
)->check
);
1883 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_TC
;
1884 mac_iocb_ptr
->total_hdrs_len
=
1885 cpu_to_le16(skb_transport_offset(skb
) +
1886 (tcp_hdr(skb
)->doff
<< 2));
1888 check
= &(udp_hdr(skb
)->check
);
1889 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_UC
;
1890 mac_iocb_ptr
->total_hdrs_len
=
1891 cpu_to_le16(skb_transport_offset(skb
) +
1892 sizeof(struct udphdr
));
1894 *check
= ~csum_tcpudp_magic(iph
->saddr
,
1895 iph
->daddr
, len
, iph
->protocol
, 0);
1898 static int qlge_send(struct sk_buff
*skb
, struct net_device
*ndev
)
1900 struct tx_ring_desc
*tx_ring_desc
;
1901 struct ob_mac_iocb_req
*mac_iocb_ptr
;
1902 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1904 struct tx_ring
*tx_ring
;
1905 u32 tx_ring_idx
= (u32
) QL_TXQ_IDX(qdev
, skb
);
1907 tx_ring
= &qdev
->tx_ring
[tx_ring_idx
];
1909 if (unlikely(atomic_read(&tx_ring
->tx_count
) < 2)) {
1910 QPRINTK(qdev
, TX_QUEUED
, INFO
,
1911 "%s: shutting down tx queue %d du to lack of resources.\n",
1912 __func__
, tx_ring_idx
);
1913 netif_stop_queue(ndev
);
1914 atomic_inc(&tx_ring
->queue_stopped
);
1915 return NETDEV_TX_BUSY
;
1917 tx_ring_desc
= &tx_ring
->q
[tx_ring
->prod_idx
];
1918 mac_iocb_ptr
= tx_ring_desc
->queue_entry
;
1919 memset((void *)mac_iocb_ptr
, 0, sizeof(mac_iocb_ptr
));
1920 if (ql_map_send(qdev
, mac_iocb_ptr
, skb
, tx_ring_desc
) != NETDEV_TX_OK
) {
1921 QPRINTK(qdev
, TX_QUEUED
, ERR
, "Could not map the segments.\n");
1922 return NETDEV_TX_BUSY
;
1925 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_IOCB
;
1926 mac_iocb_ptr
->tid
= tx_ring_desc
->index
;
1927 /* We use the upper 32-bits to store the tx queue for this IO.
1928 * When we get the completion we can use it to establish the context.
1930 mac_iocb_ptr
->txq_idx
= tx_ring_idx
;
1931 tx_ring_desc
->skb
= skb
;
1933 mac_iocb_ptr
->frame_len
= cpu_to_le16((u16
) skb
->len
);
1935 if (qdev
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1936 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "Adding a vlan tag %d.\n",
1937 vlan_tx_tag_get(skb
));
1938 mac_iocb_ptr
->flags3
|= OB_MAC_IOCB_V
;
1939 mac_iocb_ptr
->vlan_tci
= cpu_to_le16(vlan_tx_tag_get(skb
));
1941 tso
= ql_tso(skb
, (struct ob_mac_tso_iocb_req
*)mac_iocb_ptr
);
1943 dev_kfree_skb_any(skb
);
1944 return NETDEV_TX_OK
;
1945 } else if (unlikely(!tso
) && (skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
1946 ql_hw_csum_setup(skb
,
1947 (struct ob_mac_tso_iocb_req
*)mac_iocb_ptr
);
1949 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr
);
1950 tx_ring
->prod_idx
++;
1951 if (tx_ring
->prod_idx
== tx_ring
->wq_len
)
1952 tx_ring
->prod_idx
= 0;
1955 ql_write_db_reg(tx_ring
->prod_idx
, tx_ring
->prod_idx_db_reg
);
1956 ndev
->trans_start
= jiffies
;
1957 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "tx queued, slot %d, len %d\n",
1958 tx_ring
->prod_idx
, skb
->len
);
1960 atomic_dec(&tx_ring
->tx_count
);
1961 return NETDEV_TX_OK
;
1964 static void ql_free_shadow_space(struct ql_adapter
*qdev
)
1966 if (qdev
->rx_ring_shadow_reg_area
) {
1967 pci_free_consistent(qdev
->pdev
,
1969 qdev
->rx_ring_shadow_reg_area
,
1970 qdev
->rx_ring_shadow_reg_dma
);
1971 qdev
->rx_ring_shadow_reg_area
= NULL
;
1973 if (qdev
->tx_ring_shadow_reg_area
) {
1974 pci_free_consistent(qdev
->pdev
,
1976 qdev
->tx_ring_shadow_reg_area
,
1977 qdev
->tx_ring_shadow_reg_dma
);
1978 qdev
->tx_ring_shadow_reg_area
= NULL
;
1982 static int ql_alloc_shadow_space(struct ql_adapter
*qdev
)
1984 qdev
->rx_ring_shadow_reg_area
=
1985 pci_alloc_consistent(qdev
->pdev
,
1986 PAGE_SIZE
, &qdev
->rx_ring_shadow_reg_dma
);
1987 if (qdev
->rx_ring_shadow_reg_area
== NULL
) {
1988 QPRINTK(qdev
, IFUP
, ERR
,
1989 "Allocation of RX shadow space failed.\n");
1992 qdev
->tx_ring_shadow_reg_area
=
1993 pci_alloc_consistent(qdev
->pdev
, PAGE_SIZE
,
1994 &qdev
->tx_ring_shadow_reg_dma
);
1995 if (qdev
->tx_ring_shadow_reg_area
== NULL
) {
1996 QPRINTK(qdev
, IFUP
, ERR
,
1997 "Allocation of TX shadow space failed.\n");
1998 goto err_wqp_sh_area
;
2003 pci_free_consistent(qdev
->pdev
,
2005 qdev
->rx_ring_shadow_reg_area
,
2006 qdev
->rx_ring_shadow_reg_dma
);
2010 static void ql_init_tx_ring(struct ql_adapter
*qdev
, struct tx_ring
*tx_ring
)
2012 struct tx_ring_desc
*tx_ring_desc
;
2014 struct ob_mac_iocb_req
*mac_iocb_ptr
;
2016 mac_iocb_ptr
= tx_ring
->wq_base
;
2017 tx_ring_desc
= tx_ring
->q
;
2018 for (i
= 0; i
< tx_ring
->wq_len
; i
++) {
2019 tx_ring_desc
->index
= i
;
2020 tx_ring_desc
->skb
= NULL
;
2021 tx_ring_desc
->queue_entry
= mac_iocb_ptr
;
2025 atomic_set(&tx_ring
->tx_count
, tx_ring
->wq_len
);
2026 atomic_set(&tx_ring
->queue_stopped
, 0);
2029 static void ql_free_tx_resources(struct ql_adapter
*qdev
,
2030 struct tx_ring
*tx_ring
)
2032 if (tx_ring
->wq_base
) {
2033 pci_free_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2034 tx_ring
->wq_base
, tx_ring
->wq_base_dma
);
2035 tx_ring
->wq_base
= NULL
;
2041 static int ql_alloc_tx_resources(struct ql_adapter
*qdev
,
2042 struct tx_ring
*tx_ring
)
2045 pci_alloc_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2046 &tx_ring
->wq_base_dma
);
2048 if ((tx_ring
->wq_base
== NULL
)
2049 || tx_ring
->wq_base_dma
& (tx_ring
->wq_size
- 1)) {
2050 QPRINTK(qdev
, IFUP
, ERR
, "tx_ring alloc failed.\n");
2054 kmalloc(tx_ring
->wq_len
* sizeof(struct tx_ring_desc
), GFP_KERNEL
);
2055 if (tx_ring
->q
== NULL
)
2060 pci_free_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2061 tx_ring
->wq_base
, tx_ring
->wq_base_dma
);
2065 static void ql_free_lbq_buffers(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2068 struct bq_desc
*lbq_desc
;
2070 for (i
= 0; i
< rx_ring
->lbq_len
; i
++) {
2071 lbq_desc
= &rx_ring
->lbq
[i
];
2072 if (lbq_desc
->p
.lbq_page
) {
2073 pci_unmap_page(qdev
->pdev
,
2074 pci_unmap_addr(lbq_desc
, mapaddr
),
2075 pci_unmap_len(lbq_desc
, maplen
),
2076 PCI_DMA_FROMDEVICE
);
2078 put_page(lbq_desc
->p
.lbq_page
);
2079 lbq_desc
->p
.lbq_page
= NULL
;
2085 * Allocate and map a page for each element of the lbq.
2087 static int ql_alloc_lbq_buffers(struct ql_adapter
*qdev
,
2088 struct rx_ring
*rx_ring
)
2091 struct bq_desc
*lbq_desc
;
2093 __le64
*bq
= rx_ring
->lbq_base
;
2095 for (i
= 0; i
< rx_ring
->lbq_len
; i
++) {
2096 lbq_desc
= &rx_ring
->lbq
[i
];
2097 memset(lbq_desc
, 0, sizeof(lbq_desc
));
2098 lbq_desc
->addr
= bq
;
2099 lbq_desc
->index
= i
;
2100 lbq_desc
->p
.lbq_page
= alloc_page(GFP_ATOMIC
);
2101 if (unlikely(!lbq_desc
->p
.lbq_page
)) {
2102 QPRINTK(qdev
, IFUP
, ERR
, "failed alloc_page().\n");
2105 map
= pci_map_page(qdev
->pdev
,
2106 lbq_desc
->p
.lbq_page
,
2107 0, PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
2108 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
2109 QPRINTK(qdev
, IFUP
, ERR
,
2110 "PCI mapping failed.\n");
2113 pci_unmap_addr_set(lbq_desc
, mapaddr
, map
);
2114 pci_unmap_len_set(lbq_desc
, maplen
, PAGE_SIZE
);
2115 *lbq_desc
->addr
= cpu_to_le64(map
);
2121 ql_free_lbq_buffers(qdev
, rx_ring
);
2125 static void ql_free_sbq_buffers(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2128 struct bq_desc
*sbq_desc
;
2130 for (i
= 0; i
< rx_ring
->sbq_len
; i
++) {
2131 sbq_desc
= &rx_ring
->sbq
[i
];
2132 if (sbq_desc
== NULL
) {
2133 QPRINTK(qdev
, IFUP
, ERR
, "sbq_desc %d is NULL.\n", i
);
2136 if (sbq_desc
->p
.skb
) {
2137 pci_unmap_single(qdev
->pdev
,
2138 pci_unmap_addr(sbq_desc
, mapaddr
),
2139 pci_unmap_len(sbq_desc
, maplen
),
2140 PCI_DMA_FROMDEVICE
);
2141 dev_kfree_skb(sbq_desc
->p
.skb
);
2142 sbq_desc
->p
.skb
= NULL
;
2147 /* Allocate and map an skb for each element of the sbq. */
2148 static int ql_alloc_sbq_buffers(struct ql_adapter
*qdev
,
2149 struct rx_ring
*rx_ring
)
2152 struct bq_desc
*sbq_desc
;
2153 struct sk_buff
*skb
;
2155 __le64
*bq
= rx_ring
->sbq_base
;
2157 for (i
= 0; i
< rx_ring
->sbq_len
; i
++) {
2158 sbq_desc
= &rx_ring
->sbq
[i
];
2159 memset(sbq_desc
, 0, sizeof(sbq_desc
));
2160 sbq_desc
->index
= i
;
2161 sbq_desc
->addr
= bq
;
2162 skb
= netdev_alloc_skb(qdev
->ndev
, rx_ring
->sbq_buf_size
);
2163 if (unlikely(!skb
)) {
2164 /* Better luck next round */
2165 QPRINTK(qdev
, IFUP
, ERR
,
2166 "small buff alloc failed for %d bytes at index %d.\n",
2167 rx_ring
->sbq_buf_size
, i
);
2170 skb_reserve(skb
, QLGE_SB_PAD
);
2171 sbq_desc
->p
.skb
= skb
;
2173 * Map only half the buffer. Because the
2174 * other half may get some data copied to it
2175 * when the completion arrives.
2177 map
= pci_map_single(qdev
->pdev
,
2179 rx_ring
->sbq_buf_size
/ 2,
2180 PCI_DMA_FROMDEVICE
);
2181 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
2182 QPRINTK(qdev
, IFUP
, ERR
, "PCI mapping failed.\n");
2185 pci_unmap_addr_set(sbq_desc
, mapaddr
, map
);
2186 pci_unmap_len_set(sbq_desc
, maplen
, rx_ring
->sbq_buf_size
/ 2);
2187 *sbq_desc
->addr
= cpu_to_le64(map
);
2192 ql_free_sbq_buffers(qdev
, rx_ring
);
2196 static void ql_free_rx_resources(struct ql_adapter
*qdev
,
2197 struct rx_ring
*rx_ring
)
2199 if (rx_ring
->sbq_len
)
2200 ql_free_sbq_buffers(qdev
, rx_ring
);
2201 if (rx_ring
->lbq_len
)
2202 ql_free_lbq_buffers(qdev
, rx_ring
);
2204 /* Free the small buffer queue. */
2205 if (rx_ring
->sbq_base
) {
2206 pci_free_consistent(qdev
->pdev
,
2208 rx_ring
->sbq_base
, rx_ring
->sbq_base_dma
);
2209 rx_ring
->sbq_base
= NULL
;
2212 /* Free the small buffer queue control blocks. */
2213 kfree(rx_ring
->sbq
);
2214 rx_ring
->sbq
= NULL
;
2216 /* Free the large buffer queue. */
2217 if (rx_ring
->lbq_base
) {
2218 pci_free_consistent(qdev
->pdev
,
2220 rx_ring
->lbq_base
, rx_ring
->lbq_base_dma
);
2221 rx_ring
->lbq_base
= NULL
;
2224 /* Free the large buffer queue control blocks. */
2225 kfree(rx_ring
->lbq
);
2226 rx_ring
->lbq
= NULL
;
2228 /* Free the rx queue. */
2229 if (rx_ring
->cq_base
) {
2230 pci_free_consistent(qdev
->pdev
,
2232 rx_ring
->cq_base
, rx_ring
->cq_base_dma
);
2233 rx_ring
->cq_base
= NULL
;
2237 /* Allocate queues and buffers for this completions queue based
2238 * on the values in the parameter structure. */
2239 static int ql_alloc_rx_resources(struct ql_adapter
*qdev
,
2240 struct rx_ring
*rx_ring
)
2244 * Allocate the completion queue for this rx_ring.
2247 pci_alloc_consistent(qdev
->pdev
, rx_ring
->cq_size
,
2248 &rx_ring
->cq_base_dma
);
2250 if (rx_ring
->cq_base
== NULL
) {
2251 QPRINTK(qdev
, IFUP
, ERR
, "rx_ring alloc failed.\n");
2255 if (rx_ring
->sbq_len
) {
2257 * Allocate small buffer queue.
2260 pci_alloc_consistent(qdev
->pdev
, rx_ring
->sbq_size
,
2261 &rx_ring
->sbq_base_dma
);
2263 if (rx_ring
->sbq_base
== NULL
) {
2264 QPRINTK(qdev
, IFUP
, ERR
,
2265 "Small buffer queue allocation failed.\n");
2270 * Allocate small buffer queue control blocks.
2273 kmalloc(rx_ring
->sbq_len
* sizeof(struct bq_desc
),
2275 if (rx_ring
->sbq
== NULL
) {
2276 QPRINTK(qdev
, IFUP
, ERR
,
2277 "Small buffer queue control block allocation failed.\n");
2281 if (ql_alloc_sbq_buffers(qdev
, rx_ring
)) {
2282 QPRINTK(qdev
, IFUP
, ERR
,
2283 "Small buffer allocation failed.\n");
2288 if (rx_ring
->lbq_len
) {
2290 * Allocate large buffer queue.
2293 pci_alloc_consistent(qdev
->pdev
, rx_ring
->lbq_size
,
2294 &rx_ring
->lbq_base_dma
);
2296 if (rx_ring
->lbq_base
== NULL
) {
2297 QPRINTK(qdev
, IFUP
, ERR
,
2298 "Large buffer queue allocation failed.\n");
2302 * Allocate large buffer queue control blocks.
2305 kmalloc(rx_ring
->lbq_len
* sizeof(struct bq_desc
),
2307 if (rx_ring
->lbq
== NULL
) {
2308 QPRINTK(qdev
, IFUP
, ERR
,
2309 "Large buffer queue control block allocation failed.\n");
2314 * Allocate the buffers.
2316 if (ql_alloc_lbq_buffers(qdev
, rx_ring
)) {
2317 QPRINTK(qdev
, IFUP
, ERR
,
2318 "Large buffer allocation failed.\n");
2326 ql_free_rx_resources(qdev
, rx_ring
);
2330 static void ql_tx_ring_clean(struct ql_adapter
*qdev
)
2332 struct tx_ring
*tx_ring
;
2333 struct tx_ring_desc
*tx_ring_desc
;
2337 * Loop through all queues and free
2340 for (j
= 0; j
< qdev
->tx_ring_count
; j
++) {
2341 tx_ring
= &qdev
->tx_ring
[j
];
2342 for (i
= 0; i
< tx_ring
->wq_len
; i
++) {
2343 tx_ring_desc
= &tx_ring
->q
[i
];
2344 if (tx_ring_desc
&& tx_ring_desc
->skb
) {
2345 QPRINTK(qdev
, IFDOWN
, ERR
,
2346 "Freeing lost SKB %p, from queue %d, index %d.\n",
2347 tx_ring_desc
->skb
, j
,
2348 tx_ring_desc
->index
);
2349 ql_unmap_send(qdev
, tx_ring_desc
,
2350 tx_ring_desc
->map_cnt
);
2351 dev_kfree_skb(tx_ring_desc
->skb
);
2352 tx_ring_desc
->skb
= NULL
;
2358 static void ql_free_mem_resources(struct ql_adapter
*qdev
)
2362 for (i
= 0; i
< qdev
->tx_ring_count
; i
++)
2363 ql_free_tx_resources(qdev
, &qdev
->tx_ring
[i
]);
2364 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2365 ql_free_rx_resources(qdev
, &qdev
->rx_ring
[i
]);
2366 ql_free_shadow_space(qdev
);
2369 static int ql_alloc_mem_resources(struct ql_adapter
*qdev
)
2373 /* Allocate space for our shadow registers and such. */
2374 if (ql_alloc_shadow_space(qdev
))
2377 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
2378 if (ql_alloc_rx_resources(qdev
, &qdev
->rx_ring
[i
]) != 0) {
2379 QPRINTK(qdev
, IFUP
, ERR
,
2380 "RX resource allocation failed.\n");
2384 /* Allocate tx queue resources */
2385 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
2386 if (ql_alloc_tx_resources(qdev
, &qdev
->tx_ring
[i
]) != 0) {
2387 QPRINTK(qdev
, IFUP
, ERR
,
2388 "TX resource allocation failed.\n");
2395 ql_free_mem_resources(qdev
);
2399 /* Set up the rx ring control block and pass it to the chip.
2400 * The control block is defined as
2401 * "Completion Queue Initialization Control Block", or cqicb.
2403 static int ql_start_rx_ring(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2405 struct cqicb
*cqicb
= &rx_ring
->cqicb
;
2406 void *shadow_reg
= qdev
->rx_ring_shadow_reg_area
+
2407 (rx_ring
->cq_id
* sizeof(u64
) * 4);
2408 u64 shadow_reg_dma
= qdev
->rx_ring_shadow_reg_dma
+
2409 (rx_ring
->cq_id
* sizeof(u64
) * 4);
2410 void __iomem
*doorbell_area
=
2411 qdev
->doorbell_area
+ (DB_PAGE_SIZE
* (128 + rx_ring
->cq_id
));
2415 /* Set up the shadow registers for this ring. */
2416 rx_ring
->prod_idx_sh_reg
= shadow_reg
;
2417 rx_ring
->prod_idx_sh_reg_dma
= shadow_reg_dma
;
2418 shadow_reg
+= sizeof(u64
);
2419 shadow_reg_dma
+= sizeof(u64
);
2420 rx_ring
->lbq_base_indirect
= shadow_reg
;
2421 rx_ring
->lbq_base_indirect_dma
= shadow_reg_dma
;
2422 shadow_reg
+= sizeof(u64
);
2423 shadow_reg_dma
+= sizeof(u64
);
2424 rx_ring
->sbq_base_indirect
= shadow_reg
;
2425 rx_ring
->sbq_base_indirect_dma
= shadow_reg_dma
;
2427 /* PCI doorbell mem area + 0x00 for consumer index register */
2428 rx_ring
->cnsmr_idx_db_reg
= (u32 __iomem
*) doorbell_area
;
2429 rx_ring
->cnsmr_idx
= 0;
2430 rx_ring
->curr_entry
= rx_ring
->cq_base
;
2432 /* PCI doorbell mem area + 0x04 for valid register */
2433 rx_ring
->valid_db_reg
= doorbell_area
+ 0x04;
2435 /* PCI doorbell mem area + 0x18 for large buffer consumer */
2436 rx_ring
->lbq_prod_idx_db_reg
= (u32 __iomem
*) (doorbell_area
+ 0x18);
2438 /* PCI doorbell mem area + 0x1c */
2439 rx_ring
->sbq_prod_idx_db_reg
= (u32 __iomem
*) (doorbell_area
+ 0x1c);
2441 memset((void *)cqicb
, 0, sizeof(struct cqicb
));
2442 cqicb
->msix_vect
= rx_ring
->irq
;
2444 bq_len
= (rx_ring
->cq_len
== 65536) ? 0 : (u16
) rx_ring
->cq_len
;
2445 cqicb
->len
= cpu_to_le16(bq_len
| LEN_V
| LEN_CPP_CONT
);
2447 cqicb
->addr
= cpu_to_le64(rx_ring
->cq_base_dma
);
2449 cqicb
->prod_idx_addr
= cpu_to_le64(rx_ring
->prod_idx_sh_reg_dma
);
2452 * Set up the control block load flags.
2454 cqicb
->flags
= FLAGS_LC
| /* Load queue base address */
2455 FLAGS_LV
| /* Load MSI-X vector */
2456 FLAGS_LI
; /* Load irq delay values */
2457 if (rx_ring
->lbq_len
) {
2458 cqicb
->flags
|= FLAGS_LL
; /* Load lbq values */
2459 *((u64
*) rx_ring
->lbq_base_indirect
) = rx_ring
->lbq_base_dma
;
2461 cpu_to_le64(rx_ring
->lbq_base_indirect_dma
);
2462 bq_len
= (rx_ring
->lbq_buf_size
== 65536) ? 0 :
2463 (u16
) rx_ring
->lbq_buf_size
;
2464 cqicb
->lbq_buf_size
= cpu_to_le16(bq_len
);
2465 bq_len
= (rx_ring
->lbq_len
== 65536) ? 0 :
2466 (u16
) rx_ring
->lbq_len
;
2467 cqicb
->lbq_len
= cpu_to_le16(bq_len
);
2468 rx_ring
->lbq_prod_idx
= rx_ring
->lbq_len
- 16;
2469 rx_ring
->lbq_curr_idx
= 0;
2470 rx_ring
->lbq_clean_idx
= rx_ring
->lbq_prod_idx
;
2471 rx_ring
->lbq_free_cnt
= 16;
2473 if (rx_ring
->sbq_len
) {
2474 cqicb
->flags
|= FLAGS_LS
; /* Load sbq values */
2475 *((u64
*) rx_ring
->sbq_base_indirect
) = rx_ring
->sbq_base_dma
;
2477 cpu_to_le64(rx_ring
->sbq_base_indirect_dma
);
2478 cqicb
->sbq_buf_size
=
2479 cpu_to_le16(((rx_ring
->sbq_buf_size
/ 2) + 8) & 0xfffffff8);
2480 bq_len
= (rx_ring
->sbq_len
== 65536) ? 0 :
2481 (u16
) rx_ring
->sbq_len
;
2482 cqicb
->sbq_len
= cpu_to_le16(bq_len
);
2483 rx_ring
->sbq_prod_idx
= rx_ring
->sbq_len
- 16;
2484 rx_ring
->sbq_curr_idx
= 0;
2485 rx_ring
->sbq_clean_idx
= rx_ring
->sbq_prod_idx
;
2486 rx_ring
->sbq_free_cnt
= 16;
2488 switch (rx_ring
->type
) {
2490 /* If there's only one interrupt, then we use
2491 * worker threads to process the outbound
2492 * completion handling rx_rings. We do this so
2493 * they can be run on multiple CPUs. There is
2494 * room to play with this more where we would only
2495 * run in a worker if there are more than x number
2496 * of outbound completions on the queue and more
2497 * than one queue active. Some threshold that
2498 * would indicate a benefit in spite of the cost
2499 * of a context switch.
2500 * If there's more than one interrupt, then the
2501 * outbound completions are processed in the ISR.
2503 if (!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
))
2504 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_tx_clean
);
2506 /* With all debug warnings on we see a WARN_ON message
2507 * when we free the skb in the interrupt context.
2509 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_tx_clean
);
2511 cqicb
->irq_delay
= cpu_to_le16(qdev
->tx_coalesce_usecs
);
2512 cqicb
->pkt_delay
= cpu_to_le16(qdev
->tx_max_coalesced_frames
);
2515 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_rx_clean
);
2516 cqicb
->irq_delay
= 0;
2517 cqicb
->pkt_delay
= 0;
2520 /* Inbound completion handling rx_rings run in
2521 * separate NAPI contexts.
2523 netif_napi_add(qdev
->ndev
, &rx_ring
->napi
, ql_napi_poll_msix
,
2525 cqicb
->irq_delay
= cpu_to_le16(qdev
->rx_coalesce_usecs
);
2526 cqicb
->pkt_delay
= cpu_to_le16(qdev
->rx_max_coalesced_frames
);
2529 QPRINTK(qdev
, IFUP
, DEBUG
, "Invalid rx_ring->type = %d.\n",
2532 QPRINTK(qdev
, IFUP
, INFO
, "Initializing rx work queue.\n");
2533 err
= ql_write_cfg(qdev
, cqicb
, sizeof(struct cqicb
),
2534 CFG_LCQ
, rx_ring
->cq_id
);
2536 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load CQICB.\n");
2539 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded CQICB.\n");
2541 * Advance the producer index for the buffer queues.
2544 if (rx_ring
->lbq_len
)
2545 ql_write_db_reg(rx_ring
->lbq_prod_idx
,
2546 rx_ring
->lbq_prod_idx_db_reg
);
2547 if (rx_ring
->sbq_len
)
2548 ql_write_db_reg(rx_ring
->sbq_prod_idx
,
2549 rx_ring
->sbq_prod_idx_db_reg
);
2553 static int ql_start_tx_ring(struct ql_adapter
*qdev
, struct tx_ring
*tx_ring
)
2555 struct wqicb
*wqicb
= (struct wqicb
*)tx_ring
;
2556 void __iomem
*doorbell_area
=
2557 qdev
->doorbell_area
+ (DB_PAGE_SIZE
* tx_ring
->wq_id
);
2558 void *shadow_reg
= qdev
->tx_ring_shadow_reg_area
+
2559 (tx_ring
->wq_id
* sizeof(u64
));
2560 u64 shadow_reg_dma
= qdev
->tx_ring_shadow_reg_dma
+
2561 (tx_ring
->wq_id
* sizeof(u64
));
2565 * Assign doorbell registers for this tx_ring.
2567 /* TX PCI doorbell mem area for tx producer index */
2568 tx_ring
->prod_idx_db_reg
= (u32 __iomem
*) doorbell_area
;
2569 tx_ring
->prod_idx
= 0;
2570 /* TX PCI doorbell mem area + 0x04 */
2571 tx_ring
->valid_db_reg
= doorbell_area
+ 0x04;
2574 * Assign shadow registers for this tx_ring.
2576 tx_ring
->cnsmr_idx_sh_reg
= shadow_reg
;
2577 tx_ring
->cnsmr_idx_sh_reg_dma
= shadow_reg_dma
;
2579 wqicb
->len
= cpu_to_le16(tx_ring
->wq_len
| Q_LEN_V
| Q_LEN_CPP_CONT
);
2580 wqicb
->flags
= cpu_to_le16(Q_FLAGS_LC
|
2581 Q_FLAGS_LB
| Q_FLAGS_LI
| Q_FLAGS_LO
);
2582 wqicb
->cq_id_rss
= cpu_to_le16(tx_ring
->cq_id
);
2584 wqicb
->addr
= cpu_to_le64(tx_ring
->wq_base_dma
);
2586 wqicb
->cnsmr_idx_addr
= cpu_to_le64(tx_ring
->cnsmr_idx_sh_reg_dma
);
2588 ql_init_tx_ring(qdev
, tx_ring
);
2590 err
= ql_write_cfg(qdev
, wqicb
, sizeof(wqicb
), CFG_LRQ
,
2591 (u16
) tx_ring
->wq_id
);
2593 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load tx_ring.\n");
2596 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded WQICB.\n");
2600 static void ql_disable_msix(struct ql_adapter
*qdev
)
2602 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2603 pci_disable_msix(qdev
->pdev
);
2604 clear_bit(QL_MSIX_ENABLED
, &qdev
->flags
);
2605 kfree(qdev
->msi_x_entry
);
2606 qdev
->msi_x_entry
= NULL
;
2607 } else if (test_bit(QL_MSI_ENABLED
, &qdev
->flags
)) {
2608 pci_disable_msi(qdev
->pdev
);
2609 clear_bit(QL_MSI_ENABLED
, &qdev
->flags
);
2613 static void ql_enable_msix(struct ql_adapter
*qdev
)
2617 qdev
->intr_count
= 1;
2618 /* Get the MSIX vectors. */
2619 if (irq_type
== MSIX_IRQ
) {
2620 /* Try to alloc space for the msix struct,
2621 * if it fails then go to MSI/legacy.
2623 qdev
->msi_x_entry
= kcalloc(qdev
->rx_ring_count
,
2624 sizeof(struct msix_entry
),
2626 if (!qdev
->msi_x_entry
) {
2631 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2632 qdev
->msi_x_entry
[i
].entry
= i
;
2634 if (!pci_enable_msix
2635 (qdev
->pdev
, qdev
->msi_x_entry
, qdev
->rx_ring_count
)) {
2636 set_bit(QL_MSIX_ENABLED
, &qdev
->flags
);
2637 qdev
->intr_count
= qdev
->rx_ring_count
;
2638 QPRINTK(qdev
, IFUP
, INFO
,
2639 "MSI-X Enabled, got %d vectors.\n",
2643 kfree(qdev
->msi_x_entry
);
2644 qdev
->msi_x_entry
= NULL
;
2645 QPRINTK(qdev
, IFUP
, WARNING
,
2646 "MSI-X Enable failed, trying MSI.\n");
2651 if (irq_type
== MSI_IRQ
) {
2652 if (!pci_enable_msi(qdev
->pdev
)) {
2653 set_bit(QL_MSI_ENABLED
, &qdev
->flags
);
2654 QPRINTK(qdev
, IFUP
, INFO
,
2655 "Running with MSI interrupts.\n");
2660 QPRINTK(qdev
, IFUP
, DEBUG
, "Running with legacy interrupts.\n");
2664 * Here we build the intr_context structures based on
2665 * our rx_ring count and intr vector count.
2666 * The intr_context structure is used to hook each vector
2667 * to possibly different handlers.
2669 static void ql_resolve_queues_to_irqs(struct ql_adapter
*qdev
)
2672 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2674 ql_enable_msix(qdev
);
2676 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
))) {
2677 /* Each rx_ring has it's
2678 * own intr_context since we have separate
2679 * vectors for each queue.
2680 * This only true when MSI-X is enabled.
2682 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2683 qdev
->rx_ring
[i
].irq
= i
;
2684 intr_context
->intr
= i
;
2685 intr_context
->qdev
= qdev
;
2687 * We set up each vectors enable/disable/read bits so
2688 * there's no bit/mask calculations in the critical path.
2690 intr_context
->intr_en_mask
=
2691 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2692 INTR_EN_TYPE_ENABLE
| INTR_EN_IHD_MASK
| INTR_EN_IHD
2694 intr_context
->intr_dis_mask
=
2695 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2696 INTR_EN_TYPE_DISABLE
| INTR_EN_IHD_MASK
|
2698 intr_context
->intr_read_mask
=
2699 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2700 INTR_EN_TYPE_READ
| INTR_EN_IHD_MASK
| INTR_EN_IHD
|
2705 * Default queue handles bcast/mcast plus
2706 * async events. Needs buffers.
2708 intr_context
->handler
= qlge_isr
;
2709 sprintf(intr_context
->name
, "%s-default-queue",
2711 } else if (i
< qdev
->rss_ring_first_cq_id
) {
2713 * Outbound queue is for outbound completions only.
2715 intr_context
->handler
= qlge_msix_tx_isr
;
2716 sprintf(intr_context
->name
, "%s-tx-%d",
2717 qdev
->ndev
->name
, i
);
2720 * Inbound queues handle unicast frames only.
2722 intr_context
->handler
= qlge_msix_rx_isr
;
2723 sprintf(intr_context
->name
, "%s-rx-%d",
2724 qdev
->ndev
->name
, i
);
2729 * All rx_rings use the same intr_context since
2730 * there is only one vector.
2732 intr_context
->intr
= 0;
2733 intr_context
->qdev
= qdev
;
2735 * We set up each vectors enable/disable/read bits so
2736 * there's no bit/mask calculations in the critical path.
2738 intr_context
->intr_en_mask
=
2739 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
| INTR_EN_TYPE_ENABLE
;
2740 intr_context
->intr_dis_mask
=
2741 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2742 INTR_EN_TYPE_DISABLE
;
2743 intr_context
->intr_read_mask
=
2744 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
| INTR_EN_TYPE_READ
;
2746 * Single interrupt means one handler for all rings.
2748 intr_context
->handler
= qlge_isr
;
2749 sprintf(intr_context
->name
, "%s-single_irq", qdev
->ndev
->name
);
2750 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2751 qdev
->rx_ring
[i
].irq
= 0;
2755 static void ql_free_irq(struct ql_adapter
*qdev
)
2758 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2760 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2761 if (intr_context
->hooked
) {
2762 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2763 free_irq(qdev
->msi_x_entry
[i
].vector
,
2765 QPRINTK(qdev
, IFDOWN
, ERR
,
2766 "freeing msix interrupt %d.\n", i
);
2768 free_irq(qdev
->pdev
->irq
, &qdev
->rx_ring
[0]);
2769 QPRINTK(qdev
, IFDOWN
, ERR
,
2770 "freeing msi interrupt %d.\n", i
);
2774 ql_disable_msix(qdev
);
2777 static int ql_request_irq(struct ql_adapter
*qdev
)
2781 struct pci_dev
*pdev
= qdev
->pdev
;
2782 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2784 ql_resolve_queues_to_irqs(qdev
);
2786 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2787 atomic_set(&intr_context
->irq_cnt
, 0);
2788 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2789 status
= request_irq(qdev
->msi_x_entry
[i
].vector
,
2790 intr_context
->handler
,
2795 QPRINTK(qdev
, IFUP
, ERR
,
2796 "Failed request for MSIX interrupt %d.\n",
2800 QPRINTK(qdev
, IFUP
, INFO
,
2801 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2803 qdev
->rx_ring
[i
].type
==
2804 DEFAULT_Q
? "DEFAULT_Q" : "",
2805 qdev
->rx_ring
[i
].type
==
2807 qdev
->rx_ring
[i
].type
==
2808 RX_Q
? "RX_Q" : "", intr_context
->name
);
2811 QPRINTK(qdev
, IFUP
, DEBUG
,
2812 "trying msi or legacy interrupts.\n");
2813 QPRINTK(qdev
, IFUP
, DEBUG
,
2814 "%s: irq = %d.\n", __func__
, pdev
->irq
);
2815 QPRINTK(qdev
, IFUP
, DEBUG
,
2816 "%s: context->name = %s.\n", __func__
,
2817 intr_context
->name
);
2818 QPRINTK(qdev
, IFUP
, DEBUG
,
2819 "%s: dev_id = 0x%p.\n", __func__
,
2822 request_irq(pdev
->irq
, qlge_isr
,
2823 test_bit(QL_MSI_ENABLED
,
2825 flags
) ? 0 : IRQF_SHARED
,
2826 intr_context
->name
, &qdev
->rx_ring
[0]);
2830 QPRINTK(qdev
, IFUP
, ERR
,
2831 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2833 qdev
->rx_ring
[0].type
==
2834 DEFAULT_Q
? "DEFAULT_Q" : "",
2835 qdev
->rx_ring
[0].type
== TX_Q
? "TX_Q" : "",
2836 qdev
->rx_ring
[0].type
== RX_Q
? "RX_Q" : "",
2837 intr_context
->name
);
2839 intr_context
->hooked
= 1;
2843 QPRINTK(qdev
, IFUP
, ERR
, "Failed to get the interrupts!!!/n");
2848 static int ql_start_rss(struct ql_adapter
*qdev
)
2850 struct ricb
*ricb
= &qdev
->ricb
;
2853 u8
*hash_id
= (u8
*) ricb
->hash_cq_id
;
2855 memset((void *)ricb
, 0, sizeof(ricb
));
2857 ricb
->base_cq
= qdev
->rss_ring_first_cq_id
| RSS_L4K
;
2859 (RSS_L6K
| RSS_LI
| RSS_LB
| RSS_LM
| RSS_RI4
| RSS_RI6
| RSS_RT4
|
2861 ricb
->mask
= cpu_to_le16(qdev
->rss_ring_count
- 1);
2864 * Fill out the Indirection Table.
2866 for (i
= 0; i
< 32; i
++)
2870 * Random values for the IPv6 and IPv4 Hash Keys.
2872 get_random_bytes((void *)&ricb
->ipv6_hash_key
[0], 40);
2873 get_random_bytes((void *)&ricb
->ipv4_hash_key
[0], 16);
2875 QPRINTK(qdev
, IFUP
, INFO
, "Initializing RSS.\n");
2877 status
= ql_write_cfg(qdev
, ricb
, sizeof(ricb
), CFG_LR
, 0);
2879 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load RICB.\n");
2882 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded RICB.\n");
2886 /* Initialize the frame-to-queue routing. */
2887 static int ql_route_initialize(struct ql_adapter
*qdev
)
2892 /* Clear all the entries in the routing table. */
2893 for (i
= 0; i
< 16; i
++) {
2894 status
= ql_set_routing_reg(qdev
, i
, 0, 0);
2896 QPRINTK(qdev
, IFUP
, ERR
,
2897 "Failed to init routing register for CAM packets.\n");
2902 status
= ql_set_routing_reg(qdev
, RT_IDX_ALL_ERR_SLOT
, RT_IDX_ERR
, 1);
2904 QPRINTK(qdev
, IFUP
, ERR
,
2905 "Failed to init routing register for error packets.\n");
2908 status
= ql_set_routing_reg(qdev
, RT_IDX_BCAST_SLOT
, RT_IDX_BCAST
, 1);
2910 QPRINTK(qdev
, IFUP
, ERR
,
2911 "Failed to init routing register for broadcast packets.\n");
2914 /* If we have more than one inbound queue, then turn on RSS in the
2917 if (qdev
->rss_ring_count
> 1) {
2918 status
= ql_set_routing_reg(qdev
, RT_IDX_RSS_MATCH_SLOT
,
2919 RT_IDX_RSS_MATCH
, 1);
2921 QPRINTK(qdev
, IFUP
, ERR
,
2922 "Failed to init routing register for MATCH RSS packets.\n");
2927 status
= ql_set_routing_reg(qdev
, RT_IDX_CAM_HIT_SLOT
,
2930 QPRINTK(qdev
, IFUP
, ERR
,
2931 "Failed to init routing register for CAM packets.\n");
2937 static int ql_adapter_initialize(struct ql_adapter
*qdev
)
2944 * Set up the System register to halt on errors.
2946 value
= SYS_EFE
| SYS_FAE
;
2948 ql_write32(qdev
, SYS
, mask
| value
);
2950 /* Set the default queue. */
2951 value
= NIC_RCV_CFG_DFQ
;
2952 mask
= NIC_RCV_CFG_DFQ_MASK
;
2953 ql_write32(qdev
, NIC_RCV_CFG
, (mask
| value
));
2955 /* Set the MPI interrupt to enabled. */
2956 ql_write32(qdev
, INTR_MASK
, (INTR_MASK_PI
<< 16) | INTR_MASK_PI
);
2958 /* Enable the function, set pagesize, enable error checking. */
2959 value
= FSC_FE
| FSC_EPC_INBOUND
| FSC_EPC_OUTBOUND
|
2960 FSC_EC
| FSC_VM_PAGE_4K
| FSC_SH
;
2962 /* Set/clear header splitting. */
2963 mask
= FSC_VM_PAGESIZE_MASK
|
2964 FSC_DBL_MASK
| FSC_DBRST_MASK
| (value
<< 16);
2965 ql_write32(qdev
, FSC
, mask
| value
);
2967 ql_write32(qdev
, SPLT_HDR
, SPLT_HDR_EP
|
2968 min(SMALL_BUFFER_SIZE
, MAX_SPLIT_SIZE
));
2970 /* Start up the rx queues. */
2971 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
2972 status
= ql_start_rx_ring(qdev
, &qdev
->rx_ring
[i
]);
2974 QPRINTK(qdev
, IFUP
, ERR
,
2975 "Failed to start rx ring[%d].\n", i
);
2980 /* If there is more than one inbound completion queue
2981 * then download a RICB to configure RSS.
2983 if (qdev
->rss_ring_count
> 1) {
2984 status
= ql_start_rss(qdev
);
2986 QPRINTK(qdev
, IFUP
, ERR
, "Failed to start RSS.\n");
2991 /* Start up the tx queues. */
2992 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
2993 status
= ql_start_tx_ring(qdev
, &qdev
->tx_ring
[i
]);
2995 QPRINTK(qdev
, IFUP
, ERR
,
2996 "Failed to start tx ring[%d].\n", i
);
3001 status
= ql_port_initialize(qdev
);
3003 QPRINTK(qdev
, IFUP
, ERR
, "Failed to start port.\n");
3007 status
= ql_set_mac_addr_reg(qdev
, (u8
*) qdev
->ndev
->perm_addr
,
3008 MAC_ADDR_TYPE_CAM_MAC
, qdev
->func
);
3010 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init mac address.\n");
3014 status
= ql_route_initialize(qdev
);
3016 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init routing table.\n");
3020 /* Start NAPI for the RSS queues. */
3021 for (i
= qdev
->rss_ring_first_cq_id
; i
< qdev
->rx_ring_count
; i
++) {
3022 QPRINTK(qdev
, IFUP
, INFO
, "Enabling NAPI for rx_ring[%d].\n",
3024 napi_enable(&qdev
->rx_ring
[i
].napi
);
3030 /* Issue soft reset to chip. */
3031 static int ql_adapter_reset(struct ql_adapter
*qdev
)
3038 #define MAX_RESET_CNT 1
3041 QPRINTK(qdev
, IFDOWN
, DEBUG
, "Issue soft reset to chip.\n");
3042 ql_write32(qdev
, RST_FO
, (RST_FO_FR
<< 16) | RST_FO_FR
);
3043 /* Wait for reset to complete. */
3045 QPRINTK(qdev
, IFDOWN
, DEBUG
, "Wait %d seconds for reset to complete.\n",
3048 value
= ql_read32(qdev
, RST_FO
);
3049 if ((value
& RST_FO_FR
) == 0)
3053 } while ((--max_wait_time
));
3054 if (value
& RST_FO_FR
) {
3055 QPRINTK(qdev
, IFDOWN
, ERR
,
3056 "Stuck in SoftReset: FSC_SR:0x%08x\n", value
);
3057 if (resetCnt
< MAX_RESET_CNT
)
3060 if (max_wait_time
== 0) {
3061 status
= -ETIMEDOUT
;
3062 QPRINTK(qdev
, IFDOWN
, ERR
,
3063 "ETIMEOUT!!! errored out of resetting the chip!\n");
3069 static void ql_display_dev_info(struct net_device
*ndev
)
3071 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3073 QPRINTK(qdev
, PROBE
, INFO
,
3074 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3075 "XG Roll = %d, XG Rev = %d.\n",
3077 qdev
->chip_rev_id
& 0x0000000f,
3078 qdev
->chip_rev_id
>> 4 & 0x0000000f,
3079 qdev
->chip_rev_id
>> 8 & 0x0000000f,
3080 qdev
->chip_rev_id
>> 12 & 0x0000000f);
3081 QPRINTK(qdev
, PROBE
, INFO
, "MAC address %pM\n", ndev
->dev_addr
);
3084 static int ql_adapter_down(struct ql_adapter
*qdev
)
3086 struct net_device
*ndev
= qdev
->ndev
;
3088 struct rx_ring
*rx_ring
;
3090 netif_stop_queue(ndev
);
3091 netif_carrier_off(ndev
);
3093 cancel_delayed_work_sync(&qdev
->asic_reset_work
);
3094 cancel_delayed_work_sync(&qdev
->mpi_reset_work
);
3095 cancel_delayed_work_sync(&qdev
->mpi_work
);
3097 /* The default queue at index 0 is always processed in
3100 cancel_delayed_work_sync(&qdev
->rx_ring
[0].rx_work
);
3102 /* The rest of the rx_rings are processed in
3103 * a workqueue only if it's a single interrupt
3104 * environment (MSI/Legacy).
3106 for (i
= 1; i
< qdev
->rx_ring_count
; i
++) {
3107 rx_ring
= &qdev
->rx_ring
[i
];
3108 /* Only the RSS rings use NAPI on multi irq
3109 * environment. Outbound completion processing
3110 * is done in interrupt context.
3112 if (i
>= qdev
->rss_ring_first_cq_id
) {
3113 napi_disable(&rx_ring
->napi
);
3115 cancel_delayed_work_sync(&rx_ring
->rx_work
);
3119 clear_bit(QL_ADAPTER_UP
, &qdev
->flags
);
3121 ql_disable_interrupts(qdev
);
3123 ql_tx_ring_clean(qdev
);
3125 spin_lock(&qdev
->hw_lock
);
3126 status
= ql_adapter_reset(qdev
);
3128 QPRINTK(qdev
, IFDOWN
, ERR
, "reset(func #%d) FAILED!\n",
3130 spin_unlock(&qdev
->hw_lock
);
3134 static int ql_adapter_up(struct ql_adapter
*qdev
)
3138 spin_lock(&qdev
->hw_lock
);
3139 err
= ql_adapter_initialize(qdev
);
3141 QPRINTK(qdev
, IFUP
, INFO
, "Unable to initialize adapter.\n");
3142 spin_unlock(&qdev
->hw_lock
);
3145 spin_unlock(&qdev
->hw_lock
);
3146 set_bit(QL_ADAPTER_UP
, &qdev
->flags
);
3147 ql_enable_interrupts(qdev
);
3148 ql_enable_all_completion_interrupts(qdev
);
3149 if ((ql_read32(qdev
, STS
) & qdev
->port_init
)) {
3150 netif_carrier_on(qdev
->ndev
);
3151 netif_start_queue(qdev
->ndev
);
3156 ql_adapter_reset(qdev
);
3160 static int ql_cycle_adapter(struct ql_adapter
*qdev
)
3164 status
= ql_adapter_down(qdev
);
3168 status
= ql_adapter_up(qdev
);
3174 QPRINTK(qdev
, IFUP
, ALERT
,
3175 "Driver up/down cycle failed, closing device\n");
3177 dev_close(qdev
->ndev
);
3182 static void ql_release_adapter_resources(struct ql_adapter
*qdev
)
3184 ql_free_mem_resources(qdev
);
3188 static int ql_get_adapter_resources(struct ql_adapter
*qdev
)
3192 if (ql_alloc_mem_resources(qdev
)) {
3193 QPRINTK(qdev
, IFUP
, ERR
, "Unable to allocate memory.\n");
3196 status
= ql_request_irq(qdev
);
3201 ql_free_mem_resources(qdev
);
3205 static int qlge_close(struct net_device
*ndev
)
3207 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3210 * Wait for device to recover from a reset.
3211 * (Rarely happens, but possible.)
3213 while (!test_bit(QL_ADAPTER_UP
, &qdev
->flags
))
3215 ql_adapter_down(qdev
);
3216 ql_release_adapter_resources(qdev
);
3220 static int ql_configure_rings(struct ql_adapter
*qdev
)
3223 struct rx_ring
*rx_ring
;
3224 struct tx_ring
*tx_ring
;
3225 int cpu_cnt
= num_online_cpus();
3228 * For each processor present we allocate one
3229 * rx_ring for outbound completions, and one
3230 * rx_ring for inbound completions. Plus there is
3231 * always the one default queue. For the CPU
3232 * counts we end up with the following rx_rings:
3234 * one default queue +
3235 * (CPU count * outbound completion rx_ring) +
3236 * (CPU count * inbound (RSS) completion rx_ring)
3237 * To keep it simple we limit the total number of
3238 * queues to < 32, so we truncate CPU to 8.
3239 * This limitation can be removed when requested.
3242 if (cpu_cnt
> MAX_CPUS
)
3246 * rx_ring[0] is always the default queue.
3248 /* Allocate outbound completion ring for each CPU. */
3249 qdev
->tx_ring_count
= cpu_cnt
;
3250 /* Allocate inbound completion (RSS) ring for each CPU. */
3251 qdev
->rss_ring_count
= cpu_cnt
;
3252 /* cq_id for the first inbound ring handler. */
3253 qdev
->rss_ring_first_cq_id
= cpu_cnt
+ 1;
3255 * qdev->rx_ring_count:
3256 * Total number of rx_rings. This includes the one
3257 * default queue, a number of outbound completion
3258 * handler rx_rings, and the number of inbound
3259 * completion handler rx_rings.
3261 qdev
->rx_ring_count
= qdev
->tx_ring_count
+ qdev
->rss_ring_count
+ 1;
3263 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
3264 tx_ring
= &qdev
->tx_ring
[i
];
3265 memset((void *)tx_ring
, 0, sizeof(tx_ring
));
3266 tx_ring
->qdev
= qdev
;
3268 tx_ring
->wq_len
= qdev
->tx_ring_size
;
3270 tx_ring
->wq_len
* sizeof(struct ob_mac_iocb_req
);
3273 * The completion queue ID for the tx rings start
3274 * immediately after the default Q ID, which is zero.
3276 tx_ring
->cq_id
= i
+ 1;
3279 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
3280 rx_ring
= &qdev
->rx_ring
[i
];
3281 memset((void *)rx_ring
, 0, sizeof(rx_ring
));
3282 rx_ring
->qdev
= qdev
;
3284 rx_ring
->cpu
= i
% cpu_cnt
; /* CPU to run handler on. */
3285 if (i
== 0) { /* Default queue at index 0. */
3287 * Default queue handles bcast/mcast plus
3288 * async events. Needs buffers.
3290 rx_ring
->cq_len
= qdev
->rx_ring_size
;
3292 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3293 rx_ring
->lbq_len
= NUM_LARGE_BUFFERS
;
3295 rx_ring
->lbq_len
* sizeof(__le64
);
3296 rx_ring
->lbq_buf_size
= LARGE_BUFFER_SIZE
;
3297 rx_ring
->sbq_len
= NUM_SMALL_BUFFERS
;
3299 rx_ring
->sbq_len
* sizeof(__le64
);
3300 rx_ring
->sbq_buf_size
= SMALL_BUFFER_SIZE
* 2;
3301 rx_ring
->type
= DEFAULT_Q
;
3302 } else if (i
< qdev
->rss_ring_first_cq_id
) {
3304 * Outbound queue handles outbound completions only.
3306 /* outbound cq is same size as tx_ring it services. */
3307 rx_ring
->cq_len
= qdev
->tx_ring_size
;
3309 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3310 rx_ring
->lbq_len
= 0;
3311 rx_ring
->lbq_size
= 0;
3312 rx_ring
->lbq_buf_size
= 0;
3313 rx_ring
->sbq_len
= 0;
3314 rx_ring
->sbq_size
= 0;
3315 rx_ring
->sbq_buf_size
= 0;
3316 rx_ring
->type
= TX_Q
;
3317 } else { /* Inbound completions (RSS) queues */
3319 * Inbound queues handle unicast frames only.
3321 rx_ring
->cq_len
= qdev
->rx_ring_size
;
3323 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3324 rx_ring
->lbq_len
= NUM_LARGE_BUFFERS
;
3326 rx_ring
->lbq_len
* sizeof(__le64
);
3327 rx_ring
->lbq_buf_size
= LARGE_BUFFER_SIZE
;
3328 rx_ring
->sbq_len
= NUM_SMALL_BUFFERS
;
3330 rx_ring
->sbq_len
* sizeof(__le64
);
3331 rx_ring
->sbq_buf_size
= SMALL_BUFFER_SIZE
* 2;
3332 rx_ring
->type
= RX_Q
;
3338 static int qlge_open(struct net_device
*ndev
)
3341 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3343 err
= ql_configure_rings(qdev
);
3347 err
= ql_get_adapter_resources(qdev
);
3351 err
= ql_adapter_up(qdev
);
3358 ql_release_adapter_resources(qdev
);
3362 static int qlge_change_mtu(struct net_device
*ndev
, int new_mtu
)
3364 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3366 if (ndev
->mtu
== 1500 && new_mtu
== 9000) {
3367 QPRINTK(qdev
, IFUP
, ERR
, "Changing to jumbo MTU.\n");
3368 } else if (ndev
->mtu
== 9000 && new_mtu
== 1500) {
3369 QPRINTK(qdev
, IFUP
, ERR
, "Changing to normal MTU.\n");
3370 } else if ((ndev
->mtu
== 1500 && new_mtu
== 1500) ||
3371 (ndev
->mtu
== 9000 && new_mtu
== 9000)) {
3375 ndev
->mtu
= new_mtu
;
3379 static struct net_device_stats
*qlge_get_stats(struct net_device
3382 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3383 return &qdev
->stats
;
3386 static void qlge_set_multicast_list(struct net_device
*ndev
)
3388 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3389 struct dev_mc_list
*mc_ptr
;
3392 spin_lock(&qdev
->hw_lock
);
3394 * Set or clear promiscuous mode if a
3395 * transition is taking place.
3397 if (ndev
->flags
& IFF_PROMISC
) {
3398 if (!test_bit(QL_PROMISCUOUS
, &qdev
->flags
)) {
3399 if (ql_set_routing_reg
3400 (qdev
, RT_IDX_PROMISCUOUS_SLOT
, RT_IDX_VALID
, 1)) {
3401 QPRINTK(qdev
, HW
, ERR
,
3402 "Failed to set promiscous mode.\n");
3404 set_bit(QL_PROMISCUOUS
, &qdev
->flags
);
3408 if (test_bit(QL_PROMISCUOUS
, &qdev
->flags
)) {
3409 if (ql_set_routing_reg
3410 (qdev
, RT_IDX_PROMISCUOUS_SLOT
, RT_IDX_VALID
, 0)) {
3411 QPRINTK(qdev
, HW
, ERR
,
3412 "Failed to clear promiscous mode.\n");
3414 clear_bit(QL_PROMISCUOUS
, &qdev
->flags
);
3420 * Set or clear all multicast mode if a
3421 * transition is taking place.
3423 if ((ndev
->flags
& IFF_ALLMULTI
) ||
3424 (ndev
->mc_count
> MAX_MULTICAST_ENTRIES
)) {
3425 if (!test_bit(QL_ALLMULTI
, &qdev
->flags
)) {
3426 if (ql_set_routing_reg
3427 (qdev
, RT_IDX_ALLMULTI_SLOT
, RT_IDX_MCAST
, 1)) {
3428 QPRINTK(qdev
, HW
, ERR
,
3429 "Failed to set all-multi mode.\n");
3431 set_bit(QL_ALLMULTI
, &qdev
->flags
);
3435 if (test_bit(QL_ALLMULTI
, &qdev
->flags
)) {
3436 if (ql_set_routing_reg
3437 (qdev
, RT_IDX_ALLMULTI_SLOT
, RT_IDX_MCAST
, 0)) {
3438 QPRINTK(qdev
, HW
, ERR
,
3439 "Failed to clear all-multi mode.\n");
3441 clear_bit(QL_ALLMULTI
, &qdev
->flags
);
3446 if (ndev
->mc_count
) {
3447 for (i
= 0, mc_ptr
= ndev
->mc_list
; mc_ptr
;
3448 i
++, mc_ptr
= mc_ptr
->next
)
3449 if (ql_set_mac_addr_reg(qdev
, (u8
*) mc_ptr
->dmi_addr
,
3450 MAC_ADDR_TYPE_MULTI_MAC
, i
)) {
3451 QPRINTK(qdev
, HW
, ERR
,
3452 "Failed to loadmulticast address.\n");
3455 if (ql_set_routing_reg
3456 (qdev
, RT_IDX_MCAST_MATCH_SLOT
, RT_IDX_MCAST_MATCH
, 1)) {
3457 QPRINTK(qdev
, HW
, ERR
,
3458 "Failed to set multicast match mode.\n");
3460 set_bit(QL_ALLMULTI
, &qdev
->flags
);
3464 spin_unlock(&qdev
->hw_lock
);
3467 static int qlge_set_mac_address(struct net_device
*ndev
, void *p
)
3469 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3470 struct sockaddr
*addr
= p
;
3473 if (netif_running(ndev
))
3476 if (!is_valid_ether_addr(addr
->sa_data
))
3477 return -EADDRNOTAVAIL
;
3478 memcpy(ndev
->dev_addr
, addr
->sa_data
, ndev
->addr_len
);
3480 spin_lock(&qdev
->hw_lock
);
3481 if (ql_set_mac_addr_reg(qdev
, (u8
*) ndev
->dev_addr
,
3482 MAC_ADDR_TYPE_CAM_MAC
, qdev
->func
)) {/* Unicast */
3483 QPRINTK(qdev
, HW
, ERR
, "Failed to load MAC address.\n");
3486 spin_unlock(&qdev
->hw_lock
);
3491 static void qlge_tx_timeout(struct net_device
*ndev
)
3493 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3494 queue_delayed_work(qdev
->workqueue
, &qdev
->asic_reset_work
, 0);
3497 static void ql_asic_reset_work(struct work_struct
*work
)
3499 struct ql_adapter
*qdev
=
3500 container_of(work
, struct ql_adapter
, asic_reset_work
.work
);
3501 ql_cycle_adapter(qdev
);
3504 static void ql_get_board_info(struct ql_adapter
*qdev
)
3507 (ql_read32(qdev
, STS
) & STS_FUNC_ID_MASK
) >> STS_FUNC_ID_SHIFT
;
3509 qdev
->xg_sem_mask
= SEM_XGMAC1_MASK
;
3510 qdev
->port_link_up
= STS_PL1
;
3511 qdev
->port_init
= STS_PI1
;
3512 qdev
->mailbox_in
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC2_MBI
;
3513 qdev
->mailbox_out
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC2_MBO
;
3515 qdev
->xg_sem_mask
= SEM_XGMAC0_MASK
;
3516 qdev
->port_link_up
= STS_PL0
;
3517 qdev
->port_init
= STS_PI0
;
3518 qdev
->mailbox_in
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC0_MBI
;
3519 qdev
->mailbox_out
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC0_MBO
;
3521 qdev
->chip_rev_id
= ql_read32(qdev
, REV_ID
);
3524 static void ql_release_all(struct pci_dev
*pdev
)
3526 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3527 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3529 if (qdev
->workqueue
) {
3530 destroy_workqueue(qdev
->workqueue
);
3531 qdev
->workqueue
= NULL
;
3533 if (qdev
->q_workqueue
) {
3534 destroy_workqueue(qdev
->q_workqueue
);
3535 qdev
->q_workqueue
= NULL
;
3538 iounmap(qdev
->reg_base
);
3539 if (qdev
->doorbell_area
)
3540 iounmap(qdev
->doorbell_area
);
3541 pci_release_regions(pdev
);
3542 pci_set_drvdata(pdev
, NULL
);
3545 static int __devinit
ql_init_device(struct pci_dev
*pdev
,
3546 struct net_device
*ndev
, int cards_found
)
3548 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3552 memset((void *)qdev
, 0, sizeof(qdev
));
3553 err
= pci_enable_device(pdev
);
3555 dev_err(&pdev
->dev
, "PCI device enable failed.\n");
3559 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3561 dev_err(&pdev
->dev
, PFX
"Cannot find PCI Express capability, "
3565 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
3566 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
3567 val16
|= (PCI_EXP_DEVCTL_CERE
|
3568 PCI_EXP_DEVCTL_NFERE
|
3569 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
3570 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
3573 err
= pci_request_regions(pdev
, DRV_NAME
);
3575 dev_err(&pdev
->dev
, "PCI region request failed.\n");
3579 pci_set_master(pdev
);
3580 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3581 set_bit(QL_DMA64
, &qdev
->flags
);
3582 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3584 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3586 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3590 dev_err(&pdev
->dev
, "No usable DMA configuration.\n");
3594 pci_set_drvdata(pdev
, ndev
);
3596 ioremap_nocache(pci_resource_start(pdev
, 1),
3597 pci_resource_len(pdev
, 1));
3598 if (!qdev
->reg_base
) {
3599 dev_err(&pdev
->dev
, "Register mapping failed.\n");
3604 qdev
->doorbell_area_size
= pci_resource_len(pdev
, 3);
3605 qdev
->doorbell_area
=
3606 ioremap_nocache(pci_resource_start(pdev
, 3),
3607 pci_resource_len(pdev
, 3));
3608 if (!qdev
->doorbell_area
) {
3609 dev_err(&pdev
->dev
, "Doorbell register mapping failed.\n");
3614 ql_get_board_info(qdev
);
3617 qdev
->msg_enable
= netif_msg_init(debug
, default_msg
);
3618 spin_lock_init(&qdev
->hw_lock
);
3619 spin_lock_init(&qdev
->stats_lock
);
3621 /* make sure the EEPROM is good */
3622 err
= ql_get_flash_params(qdev
);
3624 dev_err(&pdev
->dev
, "Invalid FLASH.\n");
3628 if (!is_valid_ether_addr(qdev
->flash
.mac_addr
))
3631 memcpy(ndev
->dev_addr
, qdev
->flash
.mac_addr
, ndev
->addr_len
);
3632 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3634 /* Set up the default ring sizes. */
3635 qdev
->tx_ring_size
= NUM_TX_RING_ENTRIES
;
3636 qdev
->rx_ring_size
= NUM_RX_RING_ENTRIES
;
3638 /* Set up the coalescing parameters. */
3639 qdev
->rx_coalesce_usecs
= DFLT_COALESCE_WAIT
;
3640 qdev
->tx_coalesce_usecs
= DFLT_COALESCE_WAIT
;
3641 qdev
->rx_max_coalesced_frames
= DFLT_INTER_FRAME_WAIT
;
3642 qdev
->tx_max_coalesced_frames
= DFLT_INTER_FRAME_WAIT
;
3645 * Set up the operating parameters.
3649 qdev
->q_workqueue
= create_workqueue(ndev
->name
);
3650 qdev
->workqueue
= create_singlethread_workqueue(ndev
->name
);
3651 INIT_DELAYED_WORK(&qdev
->asic_reset_work
, ql_asic_reset_work
);
3652 INIT_DELAYED_WORK(&qdev
->mpi_reset_work
, ql_mpi_reset_work
);
3653 INIT_DELAYED_WORK(&qdev
->mpi_work
, ql_mpi_work
);
3656 dev_info(&pdev
->dev
, "%s\n", DRV_STRING
);
3657 dev_info(&pdev
->dev
, "Driver name: %s, Version: %s.\n",
3658 DRV_NAME
, DRV_VERSION
);
3662 ql_release_all(pdev
);
3663 pci_disable_device(pdev
);
3668 static const struct net_device_ops qlge_netdev_ops
= {
3669 .ndo_open
= qlge_open
,
3670 .ndo_stop
= qlge_close
,
3671 .ndo_start_xmit
= qlge_send
,
3672 .ndo_change_mtu
= qlge_change_mtu
,
3673 .ndo_get_stats
= qlge_get_stats
,
3674 .ndo_set_multicast_list
= qlge_set_multicast_list
,
3675 .ndo_set_mac_address
= qlge_set_mac_address
,
3676 .ndo_validate_addr
= eth_validate_addr
,
3677 .ndo_tx_timeout
= qlge_tx_timeout
,
3678 .ndo_vlan_rx_register
= ql_vlan_rx_register
,
3679 .ndo_vlan_rx_add_vid
= ql_vlan_rx_add_vid
,
3680 .ndo_vlan_rx_kill_vid
= ql_vlan_rx_kill_vid
,
3683 static int __devinit
qlge_probe(struct pci_dev
*pdev
,
3684 const struct pci_device_id
*pci_entry
)
3686 struct net_device
*ndev
= NULL
;
3687 struct ql_adapter
*qdev
= NULL
;
3688 static int cards_found
= 0;
3691 ndev
= alloc_etherdev(sizeof(struct ql_adapter
));
3695 err
= ql_init_device(pdev
, ndev
, cards_found
);
3701 qdev
= netdev_priv(ndev
);
3702 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
3709 | NETIF_F_HW_VLAN_TX
3710 | NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_FILTER
);
3712 if (test_bit(QL_DMA64
, &qdev
->flags
))
3713 ndev
->features
|= NETIF_F_HIGHDMA
;
3716 * Set up net_device structure.
3718 ndev
->tx_queue_len
= qdev
->tx_ring_size
;
3719 ndev
->irq
= pdev
->irq
;
3721 ndev
->netdev_ops
= &qlge_netdev_ops
;
3722 SET_ETHTOOL_OPS(ndev
, &qlge_ethtool_ops
);
3723 ndev
->watchdog_timeo
= 10 * HZ
;
3725 err
= register_netdev(ndev
);
3727 dev_err(&pdev
->dev
, "net device registration failed.\n");
3728 ql_release_all(pdev
);
3729 pci_disable_device(pdev
);
3732 netif_carrier_off(ndev
);
3733 netif_stop_queue(ndev
);
3734 ql_display_dev_info(ndev
);
3739 static void __devexit
qlge_remove(struct pci_dev
*pdev
)
3741 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3742 unregister_netdev(ndev
);
3743 ql_release_all(pdev
);
3744 pci_disable_device(pdev
);
3749 * This callback is called by the PCI subsystem whenever
3750 * a PCI bus error is detected.
3752 static pci_ers_result_t
qlge_io_error_detected(struct pci_dev
*pdev
,
3753 enum pci_channel_state state
)
3755 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3756 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3758 if (netif_running(ndev
))
3759 ql_adapter_down(qdev
);
3761 pci_disable_device(pdev
);
3763 /* Request a slot reset. */
3764 return PCI_ERS_RESULT_NEED_RESET
;
3768 * This callback is called after the PCI buss has been reset.
3769 * Basically, this tries to restart the card from scratch.
3770 * This is a shortened version of the device probe/discovery code,
3771 * it resembles the first-half of the () routine.
3773 static pci_ers_result_t
qlge_io_slot_reset(struct pci_dev
*pdev
)
3775 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3776 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3778 if (pci_enable_device(pdev
)) {
3779 QPRINTK(qdev
, IFUP
, ERR
,
3780 "Cannot re-enable PCI device after reset.\n");
3781 return PCI_ERS_RESULT_DISCONNECT
;
3784 pci_set_master(pdev
);
3786 netif_carrier_off(ndev
);
3787 netif_stop_queue(ndev
);
3788 ql_adapter_reset(qdev
);
3790 /* Make sure the EEPROM is good */
3791 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3793 if (!is_valid_ether_addr(ndev
->perm_addr
)) {
3794 QPRINTK(qdev
, IFUP
, ERR
, "After reset, invalid MAC address.\n");
3795 return PCI_ERS_RESULT_DISCONNECT
;
3798 return PCI_ERS_RESULT_RECOVERED
;
3801 static void qlge_io_resume(struct pci_dev
*pdev
)
3803 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3804 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3806 pci_set_master(pdev
);
3808 if (netif_running(ndev
)) {
3809 if (ql_adapter_up(qdev
)) {
3810 QPRINTK(qdev
, IFUP
, ERR
,
3811 "Device initialization failed after reset.\n");
3816 netif_device_attach(ndev
);
3819 static struct pci_error_handlers qlge_err_handler
= {
3820 .error_detected
= qlge_io_error_detected
,
3821 .slot_reset
= qlge_io_slot_reset
,
3822 .resume
= qlge_io_resume
,
3825 static int qlge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3827 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3828 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3831 netif_device_detach(ndev
);
3833 if (netif_running(ndev
)) {
3834 err
= ql_adapter_down(qdev
);
3839 err
= pci_save_state(pdev
);
3843 pci_disable_device(pdev
);
3845 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3851 static int qlge_resume(struct pci_dev
*pdev
)
3853 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3854 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3857 pci_set_power_state(pdev
, PCI_D0
);
3858 pci_restore_state(pdev
);
3859 err
= pci_enable_device(pdev
);
3861 QPRINTK(qdev
, IFUP
, ERR
, "Cannot enable PCI device from suspend\n");
3864 pci_set_master(pdev
);
3866 pci_enable_wake(pdev
, PCI_D3hot
, 0);
3867 pci_enable_wake(pdev
, PCI_D3cold
, 0);
3869 if (netif_running(ndev
)) {
3870 err
= ql_adapter_up(qdev
);
3875 netif_device_attach(ndev
);
3879 #endif /* CONFIG_PM */
3881 static void qlge_shutdown(struct pci_dev
*pdev
)
3883 qlge_suspend(pdev
, PMSG_SUSPEND
);
3886 static struct pci_driver qlge_driver
= {
3888 .id_table
= qlge_pci_tbl
,
3889 .probe
= qlge_probe
,
3890 .remove
= __devexit_p(qlge_remove
),
3892 .suspend
= qlge_suspend
,
3893 .resume
= qlge_resume
,
3895 .shutdown
= qlge_shutdown
,
3896 .err_handler
= &qlge_err_handler
3899 static int __init
qlge_init_module(void)
3901 return pci_register_driver(&qlge_driver
);
3904 static void __exit
qlge_exit(void)
3906 pci_unregister_driver(&qlge_driver
);
3909 module_init(qlge_init_module
);
3910 module_exit(qlge_exit
);