2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name
[] = DRV_NAME
;
47 const char qlge_driver_version
[] = DRV_VERSION
;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING
" ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION
);
54 static const u32 default_msg
=
55 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
|
56 /* NETIF_MSG_TIMER | */
62 NETIF_MSG_INTR
| NETIF_MSG_TX_DONE
| NETIF_MSG_RX_STATUS
|
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW
| NETIF_MSG_WOL
| 0;
66 static int debug
= 0x00007fff; /* defaults above */
67 module_param(debug
, int, 0);
68 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
73 static int irq_type
= MSIX_IRQ
;
74 module_param(irq_type
, int, MSIX_IRQ
);
75 MODULE_PARM_DESC(irq_type
, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static struct pci_device_id qlge_pci_tbl
[] __devinitdata
= {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC
, QLGE_DEVICE_ID
)},
79 /* required last entry */
83 MODULE_DEVICE_TABLE(pci
, qlge_pci_tbl
);
85 /* This hardware semaphore causes exclusive access to
86 * resources shared between the NIC driver, MPI firmware,
87 * FCOE firmware and the FC driver.
89 static int ql_sem_trylock(struct ql_adapter
*qdev
, u32 sem_mask
)
95 sem_bits
= SEM_SET
<< SEM_XGMAC0_SHIFT
;
98 sem_bits
= SEM_SET
<< SEM_XGMAC1_SHIFT
;
101 sem_bits
= SEM_SET
<< SEM_ICB_SHIFT
;
103 case SEM_MAC_ADDR_MASK
:
104 sem_bits
= SEM_SET
<< SEM_MAC_ADDR_SHIFT
;
107 sem_bits
= SEM_SET
<< SEM_FLASH_SHIFT
;
110 sem_bits
= SEM_SET
<< SEM_PROBE_SHIFT
;
112 case SEM_RT_IDX_MASK
:
113 sem_bits
= SEM_SET
<< SEM_RT_IDX_SHIFT
;
115 case SEM_PROC_REG_MASK
:
116 sem_bits
= SEM_SET
<< SEM_PROC_REG_SHIFT
;
119 QPRINTK(qdev
, PROBE
, ALERT
, "Bad Semaphore mask!.\n");
123 ql_write32(qdev
, SEM
, sem_bits
| sem_mask
);
124 return !(ql_read32(qdev
, SEM
) & sem_bits
);
127 int ql_sem_spinlock(struct ql_adapter
*qdev
, u32 sem_mask
)
129 unsigned int wait_count
= 30;
131 if (!ql_sem_trylock(qdev
, sem_mask
))
134 } while (--wait_count
);
138 void ql_sem_unlock(struct ql_adapter
*qdev
, u32 sem_mask
)
140 ql_write32(qdev
, SEM
, sem_mask
);
141 ql_read32(qdev
, SEM
); /* flush */
144 /* This function waits for a specific bit to come ready
145 * in a given register. It is used mostly by the initialize
146 * process, but is also used in kernel thread API such as
147 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149 int ql_wait_reg_rdy(struct ql_adapter
*qdev
, u32 reg
, u32 bit
, u32 err_bit
)
152 int count
= UDELAY_COUNT
;
155 temp
= ql_read32(qdev
, reg
);
157 /* check for errors */
158 if (temp
& err_bit
) {
159 QPRINTK(qdev
, PROBE
, ALERT
,
160 "register 0x%.08x access error, value = 0x%.08x!.\n",
163 } else if (temp
& bit
)
165 udelay(UDELAY_DELAY
);
168 QPRINTK(qdev
, PROBE
, ALERT
,
169 "Timed out waiting for reg %x to come ready.\n", reg
);
173 /* The CFG register is used to download TX and RX control blocks
174 * to the chip. This function waits for an operation to complete.
176 static int ql_wait_cfg(struct ql_adapter
*qdev
, u32 bit
)
178 int count
= UDELAY_COUNT
;
182 temp
= ql_read32(qdev
, CFG
);
187 udelay(UDELAY_DELAY
);
194 /* Used to issue init control blocks to hw. Maps control block,
195 * sets address, triggers download, waits for completion.
197 int ql_write_cfg(struct ql_adapter
*qdev
, void *ptr
, int size
, u32 bit
,
207 (bit
& (CFG_LRQ
| CFG_LR
| CFG_LCQ
)) ? PCI_DMA_TODEVICE
:
210 map
= pci_map_single(qdev
->pdev
, ptr
, size
, direction
);
211 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
212 QPRINTK(qdev
, IFUP
, ERR
, "Couldn't map DMA area.\n");
216 status
= ql_wait_cfg(qdev
, bit
);
218 QPRINTK(qdev
, IFUP
, ERR
,
219 "Timed out waiting for CFG to come ready.\n");
223 status
= ql_sem_spinlock(qdev
, SEM_ICB_MASK
);
226 ql_write32(qdev
, ICB_L
, (u32
) map
);
227 ql_write32(qdev
, ICB_H
, (u32
) (map
>> 32));
228 ql_sem_unlock(qdev
, SEM_ICB_MASK
); /* does flush too */
230 mask
= CFG_Q_MASK
| (bit
<< 16);
231 value
= bit
| (q_id
<< CFG_Q_SHIFT
);
232 ql_write32(qdev
, CFG
, (mask
| value
));
235 * Wait for the bit to clear after signaling hw.
237 status
= ql_wait_cfg(qdev
, bit
);
239 pci_unmap_single(qdev
->pdev
, map
, size
, direction
);
243 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
244 int ql_get_mac_addr_reg(struct ql_adapter
*qdev
, u32 type
, u16 index
,
250 status
= ql_sem_spinlock(qdev
, SEM_MAC_ADDR_MASK
);
254 case MAC_ADDR_TYPE_MULTI_MAC
:
255 case MAC_ADDR_TYPE_CAM_MAC
:
258 ql_wait_reg_rdy(qdev
,
259 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
262 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
263 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
264 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
266 ql_wait_reg_rdy(qdev
,
267 MAC_ADDR_IDX
, MAC_ADDR_MR
, 0);
270 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
272 ql_wait_reg_rdy(qdev
,
273 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
276 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
277 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
278 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
280 ql_wait_reg_rdy(qdev
,
281 MAC_ADDR_IDX
, MAC_ADDR_MR
, 0);
284 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
285 if (type
== MAC_ADDR_TYPE_CAM_MAC
) {
287 ql_wait_reg_rdy(qdev
,
288 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
291 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
292 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
293 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
295 ql_wait_reg_rdy(qdev
, MAC_ADDR_IDX
,
299 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
303 case MAC_ADDR_TYPE_VLAN
:
304 case MAC_ADDR_TYPE_MULTI_FLTR
:
306 QPRINTK(qdev
, IFUP
, CRIT
,
307 "Address type %d not yet supported.\n", type
);
311 ql_sem_unlock(qdev
, SEM_MAC_ADDR_MASK
);
315 /* Set up a MAC, multicast or VLAN address for the
316 * inbound frame matching.
318 static int ql_set_mac_addr_reg(struct ql_adapter
*qdev
, u8
*addr
, u32 type
,
324 status
= ql_sem_spinlock(qdev
, SEM_MAC_ADDR_MASK
);
328 case MAC_ADDR_TYPE_MULTI_MAC
:
329 case MAC_ADDR_TYPE_CAM_MAC
:
332 u32 upper
= (addr
[0] << 8) | addr
[1];
334 (addr
[2] << 24) | (addr
[3] << 16) | (addr
[4] << 8) |
337 QPRINTK(qdev
, IFUP
, INFO
,
338 "Adding %s address %pM"
339 " at index %d in the CAM.\n",
341 MAC_ADDR_TYPE_MULTI_MAC
) ? "MULTICAST" :
342 "UNICAST"), addr
, index
);
345 ql_wait_reg_rdy(qdev
,
346 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
349 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
350 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
352 ql_write32(qdev
, MAC_ADDR_DATA
, lower
);
354 ql_wait_reg_rdy(qdev
,
355 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
358 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
359 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
361 ql_write32(qdev
, MAC_ADDR_DATA
, upper
);
363 ql_wait_reg_rdy(qdev
,
364 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
367 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
) | /* offset */
368 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
370 /* This field should also include the queue id
371 and possibly the function id. Right now we hardcode
372 the route field to NIC core.
374 if (type
== MAC_ADDR_TYPE_CAM_MAC
) {
375 cam_output
= (CAM_OUT_ROUTE_NIC
|
377 func
<< CAM_OUT_FUNC_SHIFT
) |
379 rss_ring_first_cq_id
<<
380 CAM_OUT_CQ_ID_SHIFT
));
382 cam_output
|= CAM_OUT_RV
;
383 /* route to NIC core */
384 ql_write32(qdev
, MAC_ADDR_DATA
, cam_output
);
388 case MAC_ADDR_TYPE_VLAN
:
390 u32 enable_bit
= *((u32
*) &addr
[0]);
391 /* For VLAN, the addr actually holds a bit that
392 * either enables or disables the vlan id we are
393 * addressing. It's either MAC_ADDR_E on or off.
394 * That's bit-27 we're talking about.
396 QPRINTK(qdev
, IFUP
, INFO
, "%s VLAN ID %d %s the CAM.\n",
397 (enable_bit
? "Adding" : "Removing"),
398 index
, (enable_bit
? "to" : "from"));
401 ql_wait_reg_rdy(qdev
,
402 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
405 ql_write32(qdev
, MAC_ADDR_IDX
, offset
| /* offset */
406 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
408 enable_bit
); /* enable/disable */
411 case MAC_ADDR_TYPE_MULTI_FLTR
:
413 QPRINTK(qdev
, IFUP
, CRIT
,
414 "Address type %d not yet supported.\n", type
);
418 ql_sem_unlock(qdev
, SEM_MAC_ADDR_MASK
);
422 /* Get a specific frame routing value from the CAM.
423 * Used for debug and reg dump.
425 int ql_get_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32
*value
)
429 status
= ql_sem_spinlock(qdev
, SEM_RT_IDX_MASK
);
433 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MW
, 0);
437 ql_write32(qdev
, RT_IDX
,
438 RT_IDX_TYPE_NICQ
| RT_IDX_RS
| (index
<< RT_IDX_IDX_SHIFT
));
439 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MR
, 0);
442 *value
= ql_read32(qdev
, RT_DATA
);
444 ql_sem_unlock(qdev
, SEM_RT_IDX_MASK
);
448 /* The NIC function for this chip has 16 routing indexes. Each one can be used
449 * to route different frame types to various inbound queues. We send broadcast/
450 * multicast/error frames to the default queue for slow handling,
451 * and CAM hit/RSS frames to the fast handling queues.
453 static int ql_set_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32 mask
,
459 status
= ql_sem_spinlock(qdev
, SEM_RT_IDX_MASK
);
463 QPRINTK(qdev
, IFUP
, DEBUG
,
464 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
465 (enable
? "Adding" : "Removing"),
466 ((index
== RT_IDX_ALL_ERR_SLOT
) ? "MAC ERROR/ALL ERROR" : ""),
467 ((index
== RT_IDX_IP_CSUM_ERR_SLOT
) ? "IP CSUM ERROR" : ""),
469 RT_IDX_TCP_UDP_CSUM_ERR_SLOT
) ? "TCP/UDP CSUM ERROR" : ""),
470 ((index
== RT_IDX_BCAST_SLOT
) ? "BROADCAST" : ""),
471 ((index
== RT_IDX_MCAST_MATCH_SLOT
) ? "MULTICAST MATCH" : ""),
472 ((index
== RT_IDX_ALLMULTI_SLOT
) ? "ALL MULTICAST MATCH" : ""),
473 ((index
== RT_IDX_UNUSED6_SLOT
) ? "UNUSED6" : ""),
474 ((index
== RT_IDX_UNUSED7_SLOT
) ? "UNUSED7" : ""),
475 ((index
== RT_IDX_RSS_MATCH_SLOT
) ? "RSS ALL/IPV4 MATCH" : ""),
476 ((index
== RT_IDX_RSS_IPV6_SLOT
) ? "RSS IPV6" : ""),
477 ((index
== RT_IDX_RSS_TCP4_SLOT
) ? "RSS TCP4" : ""),
478 ((index
== RT_IDX_RSS_TCP6_SLOT
) ? "RSS TCP6" : ""),
479 ((index
== RT_IDX_CAM_HIT_SLOT
) ? "CAM HIT" : ""),
480 ((index
== RT_IDX_UNUSED013
) ? "UNUSED13" : ""),
481 ((index
== RT_IDX_UNUSED014
) ? "UNUSED14" : ""),
482 ((index
== RT_IDX_PROMISCUOUS_SLOT
) ? "PROMISCUOUS" : ""),
483 (enable
? "to" : "from"));
488 value
= RT_IDX_DST_CAM_Q
| /* dest */
489 RT_IDX_TYPE_NICQ
| /* type */
490 (RT_IDX_CAM_HIT_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
493 case RT_IDX_VALID
: /* Promiscuous Mode frames. */
495 value
= RT_IDX_DST_DFLT_Q
| /* dest */
496 RT_IDX_TYPE_NICQ
| /* type */
497 (RT_IDX_PROMISCUOUS_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
500 case RT_IDX_ERR
: /* Pass up MAC,IP,TCP/UDP error frames. */
502 value
= RT_IDX_DST_DFLT_Q
| /* dest */
503 RT_IDX_TYPE_NICQ
| /* type */
504 (RT_IDX_ALL_ERR_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
507 case RT_IDX_BCAST
: /* Pass up Broadcast frames to default Q. */
509 value
= RT_IDX_DST_DFLT_Q
| /* dest */
510 RT_IDX_TYPE_NICQ
| /* type */
511 (RT_IDX_BCAST_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
514 case RT_IDX_MCAST
: /* Pass up All Multicast frames. */
516 value
= RT_IDX_DST_CAM_Q
| /* dest */
517 RT_IDX_TYPE_NICQ
| /* type */
518 (RT_IDX_ALLMULTI_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
521 case RT_IDX_MCAST_MATCH
: /* Pass up matched Multicast frames. */
523 value
= RT_IDX_DST_CAM_Q
| /* dest */
524 RT_IDX_TYPE_NICQ
| /* type */
525 (RT_IDX_MCAST_MATCH_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
528 case RT_IDX_RSS_MATCH
: /* Pass up matched RSS frames. */
530 value
= RT_IDX_DST_RSS
| /* dest */
531 RT_IDX_TYPE_NICQ
| /* type */
532 (RT_IDX_RSS_MATCH_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
535 case 0: /* Clear the E-bit on an entry. */
537 value
= RT_IDX_DST_DFLT_Q
| /* dest */
538 RT_IDX_TYPE_NICQ
| /* type */
539 (index
<< RT_IDX_IDX_SHIFT
);/* index */
543 QPRINTK(qdev
, IFUP
, ERR
, "Mask type %d not yet supported.\n",
550 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MW
, 0);
553 value
|= (enable
? RT_IDX_E
: 0);
554 ql_write32(qdev
, RT_IDX
, value
);
555 ql_write32(qdev
, RT_DATA
, enable
? mask
: 0);
558 ql_sem_unlock(qdev
, SEM_RT_IDX_MASK
);
562 static void ql_enable_interrupts(struct ql_adapter
*qdev
)
564 ql_write32(qdev
, INTR_EN
, (INTR_EN_EI
<< 16) | INTR_EN_EI
);
567 static void ql_disable_interrupts(struct ql_adapter
*qdev
)
569 ql_write32(qdev
, INTR_EN
, (INTR_EN_EI
<< 16));
572 /* If we're running with multiple MSI-X vectors then we enable on the fly.
573 * Otherwise, we may have multiple outstanding workers and don't want to
574 * enable until the last one finishes. In this case, the irq_cnt gets
575 * incremented everytime we queue a worker and decremented everytime
576 * a worker finishes. Once it hits zero we enable the interrupt.
578 u32
ql_enable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
)
581 unsigned long hw_flags
= 0;
582 struct intr_context
*ctx
= qdev
->intr_context
+ intr
;
584 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) && intr
)) {
585 /* Always enable if we're MSIX multi interrupts and
586 * it's not the default (zeroeth) interrupt.
588 ql_write32(qdev
, INTR_EN
,
590 var
= ql_read32(qdev
, STS
);
594 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
595 if (atomic_dec_and_test(&ctx
->irq_cnt
)) {
596 ql_write32(qdev
, INTR_EN
,
598 var
= ql_read32(qdev
, STS
);
600 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
604 static u32
ql_disable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
)
607 unsigned long hw_flags
;
608 struct intr_context
*ctx
;
610 /* HW disables for us if we're MSIX multi interrupts and
611 * it's not the default (zeroeth) interrupt.
613 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) && intr
))
616 ctx
= qdev
->intr_context
+ intr
;
617 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
618 if (!atomic_read(&ctx
->irq_cnt
)) {
619 ql_write32(qdev
, INTR_EN
,
621 var
= ql_read32(qdev
, STS
);
623 atomic_inc(&ctx
->irq_cnt
);
624 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
628 static void ql_enable_all_completion_interrupts(struct ql_adapter
*qdev
)
631 for (i
= 0; i
< qdev
->intr_count
; i
++) {
632 /* The enable call does a atomic_dec_and_test
633 * and enables only if the result is zero.
634 * So we precharge it here.
636 if (unlikely(!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) ||
638 atomic_set(&qdev
->intr_context
[i
].irq_cnt
, 1);
639 ql_enable_completion_interrupt(qdev
, i
);
644 static int ql_read_flash_word(struct ql_adapter
*qdev
, int offset
, __le32
*data
)
647 /* wait for reg to come ready */
648 status
= ql_wait_reg_rdy(qdev
,
649 FLASH_ADDR
, FLASH_ADDR_RDY
, FLASH_ADDR_ERR
);
652 /* set up for reg read */
653 ql_write32(qdev
, FLASH_ADDR
, FLASH_ADDR_R
| offset
);
654 /* wait for reg to come ready */
655 status
= ql_wait_reg_rdy(qdev
,
656 FLASH_ADDR
, FLASH_ADDR_RDY
, FLASH_ADDR_ERR
);
659 /* This data is stored on flash as an array of
660 * __le32. Since ql_read32() returns cpu endian
661 * we need to swap it back.
663 *data
= cpu_to_le32(ql_read32(qdev
, FLASH_DATA
));
668 static int ql_get_flash_params(struct ql_adapter
*qdev
)
672 __le32
*p
= (__le32
*)&qdev
->flash
;
675 /* Second function's parameters follow the first
679 offset
= sizeof(qdev
->flash
) / sizeof(u32
);
681 if (ql_sem_spinlock(qdev
, SEM_FLASH_MASK
))
684 for (i
= 0; i
< sizeof(qdev
->flash
) / sizeof(u32
); i
++, p
++) {
685 status
= ql_read_flash_word(qdev
, i
+offset
, p
);
687 QPRINTK(qdev
, IFUP
, ERR
, "Error reading flash.\n");
693 ql_sem_unlock(qdev
, SEM_FLASH_MASK
);
697 /* xgmac register are located behind the xgmac_addr and xgmac_data
698 * register pair. Each read/write requires us to wait for the ready
699 * bit before reading/writing the data.
701 static int ql_write_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32 data
)
704 /* wait for reg to come ready */
705 status
= ql_wait_reg_rdy(qdev
,
706 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
709 /* write the data to the data reg */
710 ql_write32(qdev
, XGMAC_DATA
, data
);
711 /* trigger the write */
712 ql_write32(qdev
, XGMAC_ADDR
, reg
);
716 /* xgmac register are located behind the xgmac_addr and xgmac_data
717 * register pair. Each read/write requires us to wait for the ready
718 * bit before reading/writing the data.
720 int ql_read_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32
*data
)
723 /* wait for reg to come ready */
724 status
= ql_wait_reg_rdy(qdev
,
725 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
728 /* set up for reg read */
729 ql_write32(qdev
, XGMAC_ADDR
, reg
| XGMAC_ADDR_R
);
730 /* wait for reg to come ready */
731 status
= ql_wait_reg_rdy(qdev
,
732 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
736 *data
= ql_read32(qdev
, XGMAC_DATA
);
741 /* This is used for reading the 64-bit statistics regs. */
742 int ql_read_xgmac_reg64(struct ql_adapter
*qdev
, u32 reg
, u64
*data
)
748 status
= ql_read_xgmac_reg(qdev
, reg
, &lo
);
752 status
= ql_read_xgmac_reg(qdev
, reg
+ 4, &hi
);
756 *data
= (u64
) lo
| ((u64
) hi
<< 32);
762 /* Take the MAC Core out of reset.
763 * Enable statistics counting.
764 * Take the transmitter/receiver out of reset.
765 * This functionality may be done in the MPI firmware at a
768 static int ql_port_initialize(struct ql_adapter
*qdev
)
773 if (ql_sem_trylock(qdev
, qdev
->xg_sem_mask
)) {
774 /* Another function has the semaphore, so
775 * wait for the port init bit to come ready.
777 QPRINTK(qdev
, LINK
, INFO
,
778 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
779 status
= ql_wait_reg_rdy(qdev
, STS
, qdev
->port_init
, 0);
781 QPRINTK(qdev
, LINK
, CRIT
,
782 "Port initialize timed out.\n");
787 QPRINTK(qdev
, LINK
, INFO
, "Got xgmac semaphore!.\n");
788 /* Set the core reset. */
789 status
= ql_read_xgmac_reg(qdev
, GLOBAL_CFG
, &data
);
792 data
|= GLOBAL_CFG_RESET
;
793 status
= ql_write_xgmac_reg(qdev
, GLOBAL_CFG
, data
);
797 /* Clear the core reset and turn on jumbo for receiver. */
798 data
&= ~GLOBAL_CFG_RESET
; /* Clear core reset. */
799 data
|= GLOBAL_CFG_JUMBO
; /* Turn on jumbo. */
800 data
|= GLOBAL_CFG_TX_STAT_EN
;
801 data
|= GLOBAL_CFG_RX_STAT_EN
;
802 status
= ql_write_xgmac_reg(qdev
, GLOBAL_CFG
, data
);
806 /* Enable transmitter, and clear it's reset. */
807 status
= ql_read_xgmac_reg(qdev
, TX_CFG
, &data
);
810 data
&= ~TX_CFG_RESET
; /* Clear the TX MAC reset. */
811 data
|= TX_CFG_EN
; /* Enable the transmitter. */
812 status
= ql_write_xgmac_reg(qdev
, TX_CFG
, data
);
816 /* Enable receiver and clear it's reset. */
817 status
= ql_read_xgmac_reg(qdev
, RX_CFG
, &data
);
820 data
&= ~RX_CFG_RESET
; /* Clear the RX MAC reset. */
821 data
|= RX_CFG_EN
; /* Enable the receiver. */
822 status
= ql_write_xgmac_reg(qdev
, RX_CFG
, data
);
828 ql_write_xgmac_reg(qdev
, MAC_TX_PARAMS
, MAC_TX_PARAMS_JUMBO
| (0x2580 << 16));
832 ql_write_xgmac_reg(qdev
, MAC_RX_PARAMS
, 0x2580);
836 /* Signal to the world that the port is enabled. */
837 ql_write32(qdev
, STS
, ((qdev
->port_init
<< 16) | qdev
->port_init
));
839 ql_sem_unlock(qdev
, qdev
->xg_sem_mask
);
843 /* Get the next large buffer. */
844 static struct bq_desc
*ql_get_curr_lbuf(struct rx_ring
*rx_ring
)
846 struct bq_desc
*lbq_desc
= &rx_ring
->lbq
[rx_ring
->lbq_curr_idx
];
847 rx_ring
->lbq_curr_idx
++;
848 if (rx_ring
->lbq_curr_idx
== rx_ring
->lbq_len
)
849 rx_ring
->lbq_curr_idx
= 0;
850 rx_ring
->lbq_free_cnt
++;
854 /* Get the next small buffer. */
855 static struct bq_desc
*ql_get_curr_sbuf(struct rx_ring
*rx_ring
)
857 struct bq_desc
*sbq_desc
= &rx_ring
->sbq
[rx_ring
->sbq_curr_idx
];
858 rx_ring
->sbq_curr_idx
++;
859 if (rx_ring
->sbq_curr_idx
== rx_ring
->sbq_len
)
860 rx_ring
->sbq_curr_idx
= 0;
861 rx_ring
->sbq_free_cnt
++;
865 /* Update an rx ring index. */
866 static void ql_update_cq(struct rx_ring
*rx_ring
)
868 rx_ring
->cnsmr_idx
++;
869 rx_ring
->curr_entry
++;
870 if (unlikely(rx_ring
->cnsmr_idx
== rx_ring
->cq_len
)) {
871 rx_ring
->cnsmr_idx
= 0;
872 rx_ring
->curr_entry
= rx_ring
->cq_base
;
876 static void ql_write_cq_idx(struct rx_ring
*rx_ring
)
878 ql_write_db_reg(rx_ring
->cnsmr_idx
, rx_ring
->cnsmr_idx_db_reg
);
881 /* Process (refill) a large buffer queue. */
882 static void ql_update_lbq(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
884 int clean_idx
= rx_ring
->lbq_clean_idx
;
885 struct bq_desc
*lbq_desc
;
889 while (rx_ring
->lbq_free_cnt
> 16) {
890 for (i
= 0; i
< 16; i
++) {
891 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
892 "lbq: try cleaning clean_idx = %d.\n",
894 lbq_desc
= &rx_ring
->lbq
[clean_idx
];
895 if (lbq_desc
->p
.lbq_page
== NULL
) {
896 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
897 "lbq: getting new page for index %d.\n",
899 lbq_desc
->p
.lbq_page
= alloc_page(GFP_ATOMIC
);
900 if (lbq_desc
->p
.lbq_page
== NULL
) {
901 QPRINTK(qdev
, RX_STATUS
, ERR
,
902 "Couldn't get a page.\n");
905 map
= pci_map_page(qdev
->pdev
,
906 lbq_desc
->p
.lbq_page
,
909 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
910 put_page(lbq_desc
->p
.lbq_page
);
911 lbq_desc
->p
.lbq_page
= NULL
;
912 QPRINTK(qdev
, RX_STATUS
, ERR
,
913 "PCI mapping failed.\n");
916 pci_unmap_addr_set(lbq_desc
, mapaddr
, map
);
917 pci_unmap_len_set(lbq_desc
, maplen
, PAGE_SIZE
);
918 *lbq_desc
->addr
= cpu_to_le64(map
);
921 if (clean_idx
== rx_ring
->lbq_len
)
925 rx_ring
->lbq_clean_idx
= clean_idx
;
926 rx_ring
->lbq_prod_idx
+= 16;
927 if (rx_ring
->lbq_prod_idx
== rx_ring
->lbq_len
)
928 rx_ring
->lbq_prod_idx
= 0;
929 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
930 "lbq: updating prod idx = %d.\n",
931 rx_ring
->lbq_prod_idx
);
932 ql_write_db_reg(rx_ring
->lbq_prod_idx
,
933 rx_ring
->lbq_prod_idx_db_reg
);
934 rx_ring
->lbq_free_cnt
-= 16;
938 /* Process (refill) a small buffer queue. */
939 static void ql_update_sbq(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
941 int clean_idx
= rx_ring
->sbq_clean_idx
;
942 struct bq_desc
*sbq_desc
;
946 while (rx_ring
->sbq_free_cnt
> 16) {
947 for (i
= 0; i
< 16; i
++) {
948 sbq_desc
= &rx_ring
->sbq
[clean_idx
];
949 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
950 "sbq: try cleaning clean_idx = %d.\n",
952 if (sbq_desc
->p
.skb
== NULL
) {
953 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
954 "sbq: getting new skb for index %d.\n",
957 netdev_alloc_skb(qdev
->ndev
,
958 rx_ring
->sbq_buf_size
);
959 if (sbq_desc
->p
.skb
== NULL
) {
960 QPRINTK(qdev
, PROBE
, ERR
,
961 "Couldn't get an skb.\n");
962 rx_ring
->sbq_clean_idx
= clean_idx
;
965 skb_reserve(sbq_desc
->p
.skb
, QLGE_SB_PAD
);
966 map
= pci_map_single(qdev
->pdev
,
967 sbq_desc
->p
.skb
->data
,
968 rx_ring
->sbq_buf_size
/
969 2, PCI_DMA_FROMDEVICE
);
970 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
971 QPRINTK(qdev
, IFUP
, ERR
, "PCI mapping failed.\n");
972 rx_ring
->sbq_clean_idx
= clean_idx
;
975 pci_unmap_addr_set(sbq_desc
, mapaddr
, map
);
976 pci_unmap_len_set(sbq_desc
, maplen
,
977 rx_ring
->sbq_buf_size
/ 2);
978 *sbq_desc
->addr
= cpu_to_le64(map
);
982 if (clean_idx
== rx_ring
->sbq_len
)
985 rx_ring
->sbq_clean_idx
= clean_idx
;
986 rx_ring
->sbq_prod_idx
+= 16;
987 if (rx_ring
->sbq_prod_idx
== rx_ring
->sbq_len
)
988 rx_ring
->sbq_prod_idx
= 0;
989 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
990 "sbq: updating prod idx = %d.\n",
991 rx_ring
->sbq_prod_idx
);
992 ql_write_db_reg(rx_ring
->sbq_prod_idx
,
993 rx_ring
->sbq_prod_idx_db_reg
);
995 rx_ring
->sbq_free_cnt
-= 16;
999 static void ql_update_buffer_queues(struct ql_adapter
*qdev
,
1000 struct rx_ring
*rx_ring
)
1002 ql_update_sbq(qdev
, rx_ring
);
1003 ql_update_lbq(qdev
, rx_ring
);
1006 /* Unmaps tx buffers. Can be called from send() if a pci mapping
1007 * fails at some stage, or from the interrupt when a tx completes.
1009 static void ql_unmap_send(struct ql_adapter
*qdev
,
1010 struct tx_ring_desc
*tx_ring_desc
, int mapped
)
1013 for (i
= 0; i
< mapped
; i
++) {
1014 if (i
== 0 || (i
== 7 && mapped
> 7)) {
1016 * Unmap the skb->data area, or the
1017 * external sglist (AKA the Outbound
1018 * Address List (OAL)).
1019 * If its the zeroeth element, then it's
1020 * the skb->data area. If it's the 7th
1021 * element and there is more than 6 frags,
1025 QPRINTK(qdev
, TX_DONE
, DEBUG
,
1026 "unmapping OAL area.\n");
1028 pci_unmap_single(qdev
->pdev
,
1029 pci_unmap_addr(&tx_ring_desc
->map
[i
],
1031 pci_unmap_len(&tx_ring_desc
->map
[i
],
1035 QPRINTK(qdev
, TX_DONE
, DEBUG
, "unmapping frag %d.\n",
1037 pci_unmap_page(qdev
->pdev
,
1038 pci_unmap_addr(&tx_ring_desc
->map
[i
],
1040 pci_unmap_len(&tx_ring_desc
->map
[i
],
1041 maplen
), PCI_DMA_TODEVICE
);
1047 /* Map the buffers for this transmit. This will return
1048 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1050 static int ql_map_send(struct ql_adapter
*qdev
,
1051 struct ob_mac_iocb_req
*mac_iocb_ptr
,
1052 struct sk_buff
*skb
, struct tx_ring_desc
*tx_ring_desc
)
1054 int len
= skb_headlen(skb
);
1056 int frag_idx
, err
, map_idx
= 0;
1057 struct tx_buf_desc
*tbd
= mac_iocb_ptr
->tbd
;
1058 int frag_cnt
= skb_shinfo(skb
)->nr_frags
;
1061 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "frag_cnt = %d.\n", frag_cnt
);
1064 * Map the skb buffer first.
1066 map
= pci_map_single(qdev
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1068 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1070 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1071 "PCI mapping failed with error: %d\n", err
);
1073 return NETDEV_TX_BUSY
;
1076 tbd
->len
= cpu_to_le32(len
);
1077 tbd
->addr
= cpu_to_le64(map
);
1078 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
, map
);
1079 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
, len
);
1083 * This loop fills the remainder of the 8 address descriptors
1084 * in the IOCB. If there are more than 7 fragments, then the
1085 * eighth address desc will point to an external list (OAL).
1086 * When this happens, the remainder of the frags will be stored
1089 for (frag_idx
= 0; frag_idx
< frag_cnt
; frag_idx
++, map_idx
++) {
1090 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[frag_idx
];
1092 if (frag_idx
== 6 && frag_cnt
> 7) {
1093 /* Let's tack on an sglist.
1094 * Our control block will now
1096 * iocb->seg[0] = skb->data
1097 * iocb->seg[1] = frag[0]
1098 * iocb->seg[2] = frag[1]
1099 * iocb->seg[3] = frag[2]
1100 * iocb->seg[4] = frag[3]
1101 * iocb->seg[5] = frag[4]
1102 * iocb->seg[6] = frag[5]
1103 * iocb->seg[7] = ptr to OAL (external sglist)
1104 * oal->seg[0] = frag[6]
1105 * oal->seg[1] = frag[7]
1106 * oal->seg[2] = frag[8]
1107 * oal->seg[3] = frag[9]
1108 * oal->seg[4] = frag[10]
1111 /* Tack on the OAL in the eighth segment of IOCB. */
1112 map
= pci_map_single(qdev
->pdev
, &tx_ring_desc
->oal
,
1115 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1117 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1118 "PCI mapping outbound address list with error: %d\n",
1123 tbd
->addr
= cpu_to_le64(map
);
1125 * The length is the number of fragments
1126 * that remain to be mapped times the length
1127 * of our sglist (OAL).
1130 cpu_to_le32((sizeof(struct tx_buf_desc
) *
1131 (frag_cnt
- frag_idx
)) | TX_DESC_C
);
1132 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
,
1134 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
,
1135 sizeof(struct oal
));
1136 tbd
= (struct tx_buf_desc
*)&tx_ring_desc
->oal
;
1141 pci_map_page(qdev
->pdev
, frag
->page
,
1142 frag
->page_offset
, frag
->size
,
1145 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1147 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1148 "PCI mapping frags failed with error: %d.\n",
1153 tbd
->addr
= cpu_to_le64(map
);
1154 tbd
->len
= cpu_to_le32(frag
->size
);
1155 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
, map
);
1156 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
,
1160 /* Save the number of segments we've mapped. */
1161 tx_ring_desc
->map_cnt
= map_idx
;
1162 /* Terminate the last segment. */
1163 tbd
->len
= cpu_to_le32(le32_to_cpu(tbd
->len
) | TX_DESC_E
);
1164 return NETDEV_TX_OK
;
1168 * If the first frag mapping failed, then i will be zero.
1169 * This causes the unmap of the skb->data area. Otherwise
1170 * we pass in the number of frags that mapped successfully
1171 * so they can be umapped.
1173 ql_unmap_send(qdev
, tx_ring_desc
, map_idx
);
1174 return NETDEV_TX_BUSY
;
1177 static void ql_realign_skb(struct sk_buff
*skb
, int len
)
1179 void *temp_addr
= skb
->data
;
1181 /* Undo the skb_reserve(skb,32) we did before
1182 * giving to hardware, and realign data on
1183 * a 2-byte boundary.
1185 skb
->data
-= QLGE_SB_PAD
- NET_IP_ALIGN
;
1186 skb
->tail
-= QLGE_SB_PAD
- NET_IP_ALIGN
;
1187 skb_copy_to_linear_data(skb
, temp_addr
,
1192 * This function builds an skb for the given inbound
1193 * completion. It will be rewritten for readability in the near
1194 * future, but for not it works well.
1196 static struct sk_buff
*ql_build_rx_skb(struct ql_adapter
*qdev
,
1197 struct rx_ring
*rx_ring
,
1198 struct ib_mac_iocb_rsp
*ib_mac_rsp
)
1200 struct bq_desc
*lbq_desc
;
1201 struct bq_desc
*sbq_desc
;
1202 struct sk_buff
*skb
= NULL
;
1203 u32 length
= le32_to_cpu(ib_mac_rsp
->data_len
);
1204 u32 hdr_len
= le32_to_cpu(ib_mac_rsp
->hdr_len
);
1207 * Handle the header buffer if present.
1209 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HV
&&
1210 ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1211 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Header of %d bytes in small buffer.\n", hdr_len
);
1213 * Headers fit nicely into a small buffer.
1215 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1216 pci_unmap_single(qdev
->pdev
,
1217 pci_unmap_addr(sbq_desc
, mapaddr
),
1218 pci_unmap_len(sbq_desc
, maplen
),
1219 PCI_DMA_FROMDEVICE
);
1220 skb
= sbq_desc
->p
.skb
;
1221 ql_realign_skb(skb
, hdr_len
);
1222 skb_put(skb
, hdr_len
);
1223 sbq_desc
->p
.skb
= NULL
;
1227 * Handle the data buffer(s).
1229 if (unlikely(!length
)) { /* Is there data too? */
1230 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1231 "No Data buffer in this packet.\n");
1235 if (ib_mac_rsp
->flags3
& IB_MAC_IOCB_RSP_DS
) {
1236 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1237 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1238 "Headers in small, data of %d bytes in small, combine them.\n", length
);
1240 * Data is less than small buffer size so it's
1241 * stuffed in a small buffer.
1242 * For this case we append the data
1243 * from the "data" small buffer to the "header" small
1246 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1247 pci_dma_sync_single_for_cpu(qdev
->pdev
,
1249 (sbq_desc
, mapaddr
),
1252 PCI_DMA_FROMDEVICE
);
1253 memcpy(skb_put(skb
, length
),
1254 sbq_desc
->p
.skb
->data
, length
);
1255 pci_dma_sync_single_for_device(qdev
->pdev
,
1262 PCI_DMA_FROMDEVICE
);
1264 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1265 "%d bytes in a single small buffer.\n", length
);
1266 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1267 skb
= sbq_desc
->p
.skb
;
1268 ql_realign_skb(skb
, length
);
1269 skb_put(skb
, length
);
1270 pci_unmap_single(qdev
->pdev
,
1271 pci_unmap_addr(sbq_desc
,
1273 pci_unmap_len(sbq_desc
,
1275 PCI_DMA_FROMDEVICE
);
1276 sbq_desc
->p
.skb
= NULL
;
1278 } else if (ib_mac_rsp
->flags3
& IB_MAC_IOCB_RSP_DL
) {
1279 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1280 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1281 "Header in small, %d bytes in large. Chain large to small!\n", length
);
1283 * The data is in a single large buffer. We
1284 * chain it to the header buffer's skb and let
1287 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1288 pci_unmap_page(qdev
->pdev
,
1289 pci_unmap_addr(lbq_desc
,
1291 pci_unmap_len(lbq_desc
, maplen
),
1292 PCI_DMA_FROMDEVICE
);
1293 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1294 "Chaining page to skb.\n");
1295 skb_fill_page_desc(skb
, 0, lbq_desc
->p
.lbq_page
,
1298 skb
->data_len
+= length
;
1299 skb
->truesize
+= length
;
1300 lbq_desc
->p
.lbq_page
= NULL
;
1303 * The headers and data are in a single large buffer. We
1304 * copy it to a new skb and let it go. This can happen with
1305 * jumbo mtu on a non-TCP/UDP frame.
1307 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1308 skb
= netdev_alloc_skb(qdev
->ndev
, length
);
1310 QPRINTK(qdev
, PROBE
, DEBUG
,
1311 "No skb available, drop the packet.\n");
1314 pci_unmap_page(qdev
->pdev
,
1315 pci_unmap_addr(lbq_desc
,
1317 pci_unmap_len(lbq_desc
, maplen
),
1318 PCI_DMA_FROMDEVICE
);
1319 skb_reserve(skb
, NET_IP_ALIGN
);
1320 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1321 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length
);
1322 skb_fill_page_desc(skb
, 0, lbq_desc
->p
.lbq_page
,
1325 skb
->data_len
+= length
;
1326 skb
->truesize
+= length
;
1328 lbq_desc
->p
.lbq_page
= NULL
;
1329 __pskb_pull_tail(skb
,
1330 (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
) ?
1331 VLAN_ETH_HLEN
: ETH_HLEN
);
1335 * The data is in a chain of large buffers
1336 * pointed to by a small buffer. We loop
1337 * thru and chain them to the our small header
1339 * frags: There are 18 max frags and our small
1340 * buffer will hold 32 of them. The thing is,
1341 * we'll use 3 max for our 9000 byte jumbo
1342 * frames. If the MTU goes up we could
1343 * eventually be in trouble.
1345 int size
, offset
, i
= 0;
1346 __le64
*bq
, bq_array
[8];
1347 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1348 pci_unmap_single(qdev
->pdev
,
1349 pci_unmap_addr(sbq_desc
, mapaddr
),
1350 pci_unmap_len(sbq_desc
, maplen
),
1351 PCI_DMA_FROMDEVICE
);
1352 if (!(ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
)) {
1354 * This is an non TCP/UDP IP frame, so
1355 * the headers aren't split into a small
1356 * buffer. We have to use the small buffer
1357 * that contains our sg list as our skb to
1358 * send upstairs. Copy the sg list here to
1359 * a local buffer and use it to find the
1362 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1363 "%d bytes of headers & data in chain of large.\n", length
);
1364 skb
= sbq_desc
->p
.skb
;
1366 memcpy(bq
, skb
->data
, sizeof(bq_array
));
1367 sbq_desc
->p
.skb
= NULL
;
1368 skb_reserve(skb
, NET_IP_ALIGN
);
1370 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1371 "Headers in small, %d bytes of data in chain of large.\n", length
);
1372 bq
= (__le64
*)sbq_desc
->p
.skb
->data
;
1374 while (length
> 0) {
1375 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1376 pci_unmap_page(qdev
->pdev
,
1377 pci_unmap_addr(lbq_desc
,
1379 pci_unmap_len(lbq_desc
,
1381 PCI_DMA_FROMDEVICE
);
1382 size
= (length
< PAGE_SIZE
) ? length
: PAGE_SIZE
;
1385 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1386 "Adding page %d to skb for %d bytes.\n",
1388 skb_fill_page_desc(skb
, i
, lbq_desc
->p
.lbq_page
,
1391 skb
->data_len
+= size
;
1392 skb
->truesize
+= size
;
1394 lbq_desc
->p
.lbq_page
= NULL
;
1398 __pskb_pull_tail(skb
, (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
) ?
1399 VLAN_ETH_HLEN
: ETH_HLEN
);
1404 /* Process an inbound completion from an rx ring. */
1405 static void ql_process_mac_rx_intr(struct ql_adapter
*qdev
,
1406 struct rx_ring
*rx_ring
,
1407 struct ib_mac_iocb_rsp
*ib_mac_rsp
)
1409 struct net_device
*ndev
= qdev
->ndev
;
1410 struct sk_buff
*skb
= NULL
;
1412 QL_DUMP_IB_MAC_RSP(ib_mac_rsp
);
1414 skb
= ql_build_rx_skb(qdev
, rx_ring
, ib_mac_rsp
);
1415 if (unlikely(!skb
)) {
1416 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1417 "No skb available, drop packet.\n");
1421 prefetch(skb
->data
);
1423 if (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) {
1424 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "%s%s%s Multicast.\n",
1425 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1426 IB_MAC_IOCB_RSP_M_HASH
? "Hash" : "",
1427 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1428 IB_MAC_IOCB_RSP_M_REG
? "Registered" : "",
1429 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1430 IB_MAC_IOCB_RSP_M_PROM
? "Promiscuous" : "");
1432 if (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_P
) {
1433 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Promiscuous Packet.\n");
1435 if (ib_mac_rsp
->flags1
& (IB_MAC_IOCB_RSP_IE
| IB_MAC_IOCB_RSP_TE
)) {
1436 QPRINTK(qdev
, RX_STATUS
, ERR
,
1437 "Bad checksum for this %s packet.\n",
1439 flags2
& IB_MAC_IOCB_RSP_T
) ? "TCP" : "UDP"));
1440 skb
->ip_summed
= CHECKSUM_NONE
;
1441 } else if (qdev
->rx_csum
&&
1442 ((ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_T
) ||
1443 ((ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_U
) &&
1444 !(ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_NU
)))) {
1445 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "RX checksum done!\n");
1446 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1448 qdev
->stats
.rx_packets
++;
1449 qdev
->stats
.rx_bytes
+= skb
->len
;
1450 skb
->protocol
= eth_type_trans(skb
, ndev
);
1451 if (qdev
->vlgrp
&& (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
)) {
1452 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1453 "Passing a VLAN packet upstream.\n");
1454 vlan_hwaccel_receive_skb(skb
, qdev
->vlgrp
,
1455 le16_to_cpu(ib_mac_rsp
->vlan_id
));
1457 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1458 "Passing a normal packet upstream.\n");
1459 netif_receive_skb(skb
);
1463 /* Process an outbound completion from an rx ring. */
1464 static void ql_process_mac_tx_intr(struct ql_adapter
*qdev
,
1465 struct ob_mac_iocb_rsp
*mac_rsp
)
1467 struct tx_ring
*tx_ring
;
1468 struct tx_ring_desc
*tx_ring_desc
;
1470 QL_DUMP_OB_MAC_RSP(mac_rsp
);
1471 tx_ring
= &qdev
->tx_ring
[mac_rsp
->txq_idx
];
1472 tx_ring_desc
= &tx_ring
->q
[mac_rsp
->tid
];
1473 ql_unmap_send(qdev
, tx_ring_desc
, tx_ring_desc
->map_cnt
);
1474 qdev
->stats
.tx_bytes
+= tx_ring_desc
->map_cnt
;
1475 qdev
->stats
.tx_packets
++;
1476 dev_kfree_skb(tx_ring_desc
->skb
);
1477 tx_ring_desc
->skb
= NULL
;
1479 if (unlikely(mac_rsp
->flags1
& (OB_MAC_IOCB_RSP_E
|
1482 OB_MAC_IOCB_RSP_P
| OB_MAC_IOCB_RSP_B
))) {
1483 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_E
) {
1484 QPRINTK(qdev
, TX_DONE
, WARNING
,
1485 "Total descriptor length did not match transfer length.\n");
1487 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_S
) {
1488 QPRINTK(qdev
, TX_DONE
, WARNING
,
1489 "Frame too short to be legal, not sent.\n");
1491 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_L
) {
1492 QPRINTK(qdev
, TX_DONE
, WARNING
,
1493 "Frame too long, but sent anyway.\n");
1495 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_B
) {
1496 QPRINTK(qdev
, TX_DONE
, WARNING
,
1497 "PCI backplane error. Frame not sent.\n");
1500 atomic_inc(&tx_ring
->tx_count
);
1503 /* Fire up a handler to reset the MPI processor. */
1504 void ql_queue_fw_error(struct ql_adapter
*qdev
)
1506 netif_stop_queue(qdev
->ndev
);
1507 netif_carrier_off(qdev
->ndev
);
1508 queue_delayed_work(qdev
->workqueue
, &qdev
->mpi_reset_work
, 0);
1511 void ql_queue_asic_error(struct ql_adapter
*qdev
)
1513 netif_stop_queue(qdev
->ndev
);
1514 netif_carrier_off(qdev
->ndev
);
1515 ql_disable_interrupts(qdev
);
1516 /* Clear adapter up bit to signal the recovery
1517 * process that it shouldn't kill the reset worker
1520 clear_bit(QL_ADAPTER_UP
, &qdev
->flags
);
1521 queue_delayed_work(qdev
->workqueue
, &qdev
->asic_reset_work
, 0);
1524 static void ql_process_chip_ae_intr(struct ql_adapter
*qdev
,
1525 struct ib_ae_iocb_rsp
*ib_ae_rsp
)
1527 switch (ib_ae_rsp
->event
) {
1528 case MGMT_ERR_EVENT
:
1529 QPRINTK(qdev
, RX_ERR
, ERR
,
1530 "Management Processor Fatal Error.\n");
1531 ql_queue_fw_error(qdev
);
1534 case CAM_LOOKUP_ERR_EVENT
:
1535 QPRINTK(qdev
, LINK
, ERR
,
1536 "Multiple CAM hits lookup occurred.\n");
1537 QPRINTK(qdev
, DRV
, ERR
, "This event shouldn't occur.\n");
1538 ql_queue_asic_error(qdev
);
1541 case SOFT_ECC_ERROR_EVENT
:
1542 QPRINTK(qdev
, RX_ERR
, ERR
, "Soft ECC error detected.\n");
1543 ql_queue_asic_error(qdev
);
1546 case PCI_ERR_ANON_BUF_RD
:
1547 QPRINTK(qdev
, RX_ERR
, ERR
,
1548 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1550 ql_queue_asic_error(qdev
);
1554 QPRINTK(qdev
, DRV
, ERR
, "Unexpected event %d.\n",
1556 ql_queue_asic_error(qdev
);
1561 static int ql_clean_outbound_rx_ring(struct rx_ring
*rx_ring
)
1563 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1564 u32 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1565 struct ob_mac_iocb_rsp
*net_rsp
= NULL
;
1568 /* While there are entries in the completion queue. */
1569 while (prod
!= rx_ring
->cnsmr_idx
) {
1571 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1572 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring
->cq_id
,
1573 prod
, rx_ring
->cnsmr_idx
);
1575 net_rsp
= (struct ob_mac_iocb_rsp
*)rx_ring
->curr_entry
;
1577 switch (net_rsp
->opcode
) {
1579 case OPCODE_OB_MAC_TSO_IOCB
:
1580 case OPCODE_OB_MAC_IOCB
:
1581 ql_process_mac_tx_intr(qdev
, net_rsp
);
1584 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1585 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1589 ql_update_cq(rx_ring
);
1590 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1592 ql_write_cq_idx(rx_ring
);
1593 if (netif_queue_stopped(qdev
->ndev
) && net_rsp
!= NULL
) {
1594 struct tx_ring
*tx_ring
= &qdev
->tx_ring
[net_rsp
->txq_idx
];
1595 if (atomic_read(&tx_ring
->queue_stopped
) &&
1596 (atomic_read(&tx_ring
->tx_count
) > (tx_ring
->wq_len
/ 4)))
1598 * The queue got stopped because the tx_ring was full.
1599 * Wake it up, because it's now at least 25% empty.
1601 netif_wake_queue(qdev
->ndev
);
1607 static int ql_clean_inbound_rx_ring(struct rx_ring
*rx_ring
, int budget
)
1609 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1610 u32 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1611 struct ql_net_rsp_iocb
*net_rsp
;
1614 /* While there are entries in the completion queue. */
1615 while (prod
!= rx_ring
->cnsmr_idx
) {
1617 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1618 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring
->cq_id
,
1619 prod
, rx_ring
->cnsmr_idx
);
1621 net_rsp
= rx_ring
->curr_entry
;
1623 switch (net_rsp
->opcode
) {
1624 case OPCODE_IB_MAC_IOCB
:
1625 ql_process_mac_rx_intr(qdev
, rx_ring
,
1626 (struct ib_mac_iocb_rsp
*)
1630 case OPCODE_IB_AE_IOCB
:
1631 ql_process_chip_ae_intr(qdev
, (struct ib_ae_iocb_rsp
*)
1636 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1637 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1642 ql_update_cq(rx_ring
);
1643 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1644 if (count
== budget
)
1647 ql_update_buffer_queues(qdev
, rx_ring
);
1648 ql_write_cq_idx(rx_ring
);
1652 static int ql_napi_poll_msix(struct napi_struct
*napi
, int budget
)
1654 struct rx_ring
*rx_ring
= container_of(napi
, struct rx_ring
, napi
);
1655 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1656 int work_done
= ql_clean_inbound_rx_ring(rx_ring
, budget
);
1658 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Enter, NAPI POLL cq_id = %d.\n",
1661 if (work_done
< budget
) {
1662 __netif_rx_complete(napi
);
1663 ql_enable_completion_interrupt(qdev
, rx_ring
->irq
);
1668 static void ql_vlan_rx_register(struct net_device
*ndev
, struct vlan_group
*grp
)
1670 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1674 QPRINTK(qdev
, IFUP
, DEBUG
, "Turning on VLAN in NIC_RCV_CFG.\n");
1675 ql_write32(qdev
, NIC_RCV_CFG
, NIC_RCV_CFG_VLAN_MASK
|
1676 NIC_RCV_CFG_VLAN_MATCH_AND_NON
);
1678 QPRINTK(qdev
, IFUP
, DEBUG
,
1679 "Turning off VLAN in NIC_RCV_CFG.\n");
1680 ql_write32(qdev
, NIC_RCV_CFG
, NIC_RCV_CFG_VLAN_MASK
);
1684 static void ql_vlan_rx_add_vid(struct net_device
*ndev
, u16 vid
)
1686 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1687 u32 enable_bit
= MAC_ADDR_E
;
1689 spin_lock(&qdev
->hw_lock
);
1690 if (ql_set_mac_addr_reg
1691 (qdev
, (u8
*) &enable_bit
, MAC_ADDR_TYPE_VLAN
, vid
)) {
1692 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init vlan address.\n");
1694 spin_unlock(&qdev
->hw_lock
);
1697 static void ql_vlan_rx_kill_vid(struct net_device
*ndev
, u16 vid
)
1699 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1702 spin_lock(&qdev
->hw_lock
);
1703 if (ql_set_mac_addr_reg
1704 (qdev
, (u8
*) &enable_bit
, MAC_ADDR_TYPE_VLAN
, vid
)) {
1705 QPRINTK(qdev
, IFUP
, ERR
, "Failed to clear vlan address.\n");
1707 spin_unlock(&qdev
->hw_lock
);
1711 /* Worker thread to process a given rx_ring that is dedicated
1712 * to outbound completions.
1714 static void ql_tx_clean(struct work_struct
*work
)
1716 struct rx_ring
*rx_ring
=
1717 container_of(work
, struct rx_ring
, rx_work
.work
);
1718 ql_clean_outbound_rx_ring(rx_ring
);
1719 ql_enable_completion_interrupt(rx_ring
->qdev
, rx_ring
->irq
);
1723 /* Worker thread to process a given rx_ring that is dedicated
1724 * to inbound completions.
1726 static void ql_rx_clean(struct work_struct
*work
)
1728 struct rx_ring
*rx_ring
=
1729 container_of(work
, struct rx_ring
, rx_work
.work
);
1730 ql_clean_inbound_rx_ring(rx_ring
, 64);
1731 ql_enable_completion_interrupt(rx_ring
->qdev
, rx_ring
->irq
);
1734 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1735 static irqreturn_t
qlge_msix_tx_isr(int irq
, void *dev_id
)
1737 struct rx_ring
*rx_ring
= dev_id
;
1738 queue_delayed_work_on(rx_ring
->cpu
, rx_ring
->qdev
->q_workqueue
,
1739 &rx_ring
->rx_work
, 0);
1743 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1744 static irqreturn_t
qlge_msix_rx_isr(int irq
, void *dev_id
)
1746 struct rx_ring
*rx_ring
= dev_id
;
1747 netif_rx_schedule(&rx_ring
->napi
);
1751 /* This handles a fatal error, MPI activity, and the default
1752 * rx_ring in an MSI-X multiple vector environment.
1753 * In MSI/Legacy environment it also process the rest of
1756 static irqreturn_t
qlge_isr(int irq
, void *dev_id
)
1758 struct rx_ring
*rx_ring
= dev_id
;
1759 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1760 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
1765 spin_lock(&qdev
->hw_lock
);
1766 if (atomic_read(&qdev
->intr_context
[0].irq_cnt
)) {
1767 QPRINTK(qdev
, INTR
, DEBUG
, "Shared Interrupt, Not ours!\n");
1768 spin_unlock(&qdev
->hw_lock
);
1771 spin_unlock(&qdev
->hw_lock
);
1773 var
= ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1776 * Check for fatal error.
1779 ql_queue_asic_error(qdev
);
1780 QPRINTK(qdev
, INTR
, ERR
, "Got fatal error, STS = %x.\n", var
);
1781 var
= ql_read32(qdev
, ERR_STS
);
1782 QPRINTK(qdev
, INTR
, ERR
,
1783 "Resetting chip. Error Status Register = 0x%x\n", var
);
1788 * Check MPI processor activity.
1792 * We've got an async event or mailbox completion.
1793 * Handle it and clear the source of the interrupt.
1795 QPRINTK(qdev
, INTR
, ERR
, "Got MPI processor interrupt.\n");
1796 ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1797 queue_delayed_work_on(smp_processor_id(), qdev
->workqueue
,
1798 &qdev
->mpi_work
, 0);
1803 * Check the default queue and wake handler if active.
1805 rx_ring
= &qdev
->rx_ring
[0];
1806 if (ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
) != rx_ring
->cnsmr_idx
) {
1807 QPRINTK(qdev
, INTR
, INFO
, "Waking handler for rx_ring[0].\n");
1808 ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1809 queue_delayed_work_on(smp_processor_id(), qdev
->q_workqueue
,
1810 &rx_ring
->rx_work
, 0);
1814 if (!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
1816 * Start the DPC for each active queue.
1818 for (i
= 1; i
< qdev
->rx_ring_count
; i
++) {
1819 rx_ring
= &qdev
->rx_ring
[i
];
1820 if (ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
) !=
1821 rx_ring
->cnsmr_idx
) {
1822 QPRINTK(qdev
, INTR
, INFO
,
1823 "Waking handler for rx_ring[%d].\n", i
);
1824 ql_disable_completion_interrupt(qdev
,
1827 if (i
< qdev
->rss_ring_first_cq_id
)
1828 queue_delayed_work_on(rx_ring
->cpu
,
1833 netif_rx_schedule(&rx_ring
->napi
);
1838 ql_enable_completion_interrupt(qdev
, intr_context
->intr
);
1839 return work_done
? IRQ_HANDLED
: IRQ_NONE
;
1842 static int ql_tso(struct sk_buff
*skb
, struct ob_mac_tso_iocb_req
*mac_iocb_ptr
)
1845 if (skb_is_gso(skb
)) {
1847 if (skb_header_cloned(skb
)) {
1848 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
1853 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_TSO_IOCB
;
1854 mac_iocb_ptr
->flags3
|= OB_MAC_TSO_IOCB_IC
;
1855 mac_iocb_ptr
->frame_len
= cpu_to_le32((u32
) skb
->len
);
1856 mac_iocb_ptr
->total_hdrs_len
=
1857 cpu_to_le16(skb_transport_offset(skb
) + tcp_hdrlen(skb
));
1858 mac_iocb_ptr
->net_trans_offset
=
1859 cpu_to_le16(skb_network_offset(skb
) |
1860 skb_transport_offset(skb
)
1861 << OB_MAC_TRANSPORT_HDR_SHIFT
);
1862 mac_iocb_ptr
->mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
);
1863 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_LSO
;
1864 if (likely(skb
->protocol
== htons(ETH_P_IP
))) {
1865 struct iphdr
*iph
= ip_hdr(skb
);
1867 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP4
;
1868 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
1872 } else if (skb
->protocol
== htons(ETH_P_IPV6
)) {
1873 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP6
;
1874 tcp_hdr(skb
)->check
=
1875 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
1876 &ipv6_hdr(skb
)->daddr
,
1884 static void ql_hw_csum_setup(struct sk_buff
*skb
,
1885 struct ob_mac_tso_iocb_req
*mac_iocb_ptr
)
1888 struct iphdr
*iph
= ip_hdr(skb
);
1890 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_TSO_IOCB
;
1891 mac_iocb_ptr
->frame_len
= cpu_to_le32((u32
) skb
->len
);
1892 mac_iocb_ptr
->net_trans_offset
=
1893 cpu_to_le16(skb_network_offset(skb
) |
1894 skb_transport_offset(skb
) << OB_MAC_TRANSPORT_HDR_SHIFT
);
1896 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP4
;
1897 len
= (ntohs(iph
->tot_len
) - (iph
->ihl
<< 2));
1898 if (likely(iph
->protocol
== IPPROTO_TCP
)) {
1899 check
= &(tcp_hdr(skb
)->check
);
1900 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_TC
;
1901 mac_iocb_ptr
->total_hdrs_len
=
1902 cpu_to_le16(skb_transport_offset(skb
) +
1903 (tcp_hdr(skb
)->doff
<< 2));
1905 check
= &(udp_hdr(skb
)->check
);
1906 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_UC
;
1907 mac_iocb_ptr
->total_hdrs_len
=
1908 cpu_to_le16(skb_transport_offset(skb
) +
1909 sizeof(struct udphdr
));
1911 *check
= ~csum_tcpudp_magic(iph
->saddr
,
1912 iph
->daddr
, len
, iph
->protocol
, 0);
1915 static int qlge_send(struct sk_buff
*skb
, struct net_device
*ndev
)
1917 struct tx_ring_desc
*tx_ring_desc
;
1918 struct ob_mac_iocb_req
*mac_iocb_ptr
;
1919 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1921 struct tx_ring
*tx_ring
;
1922 u32 tx_ring_idx
= (u32
) QL_TXQ_IDX(qdev
, skb
);
1924 tx_ring
= &qdev
->tx_ring
[tx_ring_idx
];
1926 if (unlikely(atomic_read(&tx_ring
->tx_count
) < 2)) {
1927 QPRINTK(qdev
, TX_QUEUED
, INFO
,
1928 "%s: shutting down tx queue %d du to lack of resources.\n",
1929 __func__
, tx_ring_idx
);
1930 netif_stop_queue(ndev
);
1931 atomic_inc(&tx_ring
->queue_stopped
);
1932 return NETDEV_TX_BUSY
;
1934 tx_ring_desc
= &tx_ring
->q
[tx_ring
->prod_idx
];
1935 mac_iocb_ptr
= tx_ring_desc
->queue_entry
;
1936 memset((void *)mac_iocb_ptr
, 0, sizeof(mac_iocb_ptr
));
1937 if (ql_map_send(qdev
, mac_iocb_ptr
, skb
, tx_ring_desc
) != NETDEV_TX_OK
) {
1938 QPRINTK(qdev
, TX_QUEUED
, ERR
, "Could not map the segments.\n");
1939 return NETDEV_TX_BUSY
;
1942 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_IOCB
;
1943 mac_iocb_ptr
->tid
= tx_ring_desc
->index
;
1944 /* We use the upper 32-bits to store the tx queue for this IO.
1945 * When we get the completion we can use it to establish the context.
1947 mac_iocb_ptr
->txq_idx
= tx_ring_idx
;
1948 tx_ring_desc
->skb
= skb
;
1950 mac_iocb_ptr
->frame_len
= cpu_to_le16((u16
) skb
->len
);
1952 if (qdev
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1953 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "Adding a vlan tag %d.\n",
1954 vlan_tx_tag_get(skb
));
1955 mac_iocb_ptr
->flags3
|= OB_MAC_IOCB_V
;
1956 mac_iocb_ptr
->vlan_tci
= cpu_to_le16(vlan_tx_tag_get(skb
));
1958 tso
= ql_tso(skb
, (struct ob_mac_tso_iocb_req
*)mac_iocb_ptr
);
1960 dev_kfree_skb_any(skb
);
1961 return NETDEV_TX_OK
;
1962 } else if (unlikely(!tso
) && (skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
1963 ql_hw_csum_setup(skb
,
1964 (struct ob_mac_tso_iocb_req
*)mac_iocb_ptr
);
1966 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr
);
1967 tx_ring
->prod_idx
++;
1968 if (tx_ring
->prod_idx
== tx_ring
->wq_len
)
1969 tx_ring
->prod_idx
= 0;
1972 ql_write_db_reg(tx_ring
->prod_idx
, tx_ring
->prod_idx_db_reg
);
1973 ndev
->trans_start
= jiffies
;
1974 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "tx queued, slot %d, len %d\n",
1975 tx_ring
->prod_idx
, skb
->len
);
1977 atomic_dec(&tx_ring
->tx_count
);
1978 return NETDEV_TX_OK
;
1981 static void ql_free_shadow_space(struct ql_adapter
*qdev
)
1983 if (qdev
->rx_ring_shadow_reg_area
) {
1984 pci_free_consistent(qdev
->pdev
,
1986 qdev
->rx_ring_shadow_reg_area
,
1987 qdev
->rx_ring_shadow_reg_dma
);
1988 qdev
->rx_ring_shadow_reg_area
= NULL
;
1990 if (qdev
->tx_ring_shadow_reg_area
) {
1991 pci_free_consistent(qdev
->pdev
,
1993 qdev
->tx_ring_shadow_reg_area
,
1994 qdev
->tx_ring_shadow_reg_dma
);
1995 qdev
->tx_ring_shadow_reg_area
= NULL
;
1999 static int ql_alloc_shadow_space(struct ql_adapter
*qdev
)
2001 qdev
->rx_ring_shadow_reg_area
=
2002 pci_alloc_consistent(qdev
->pdev
,
2003 PAGE_SIZE
, &qdev
->rx_ring_shadow_reg_dma
);
2004 if (qdev
->rx_ring_shadow_reg_area
== NULL
) {
2005 QPRINTK(qdev
, IFUP
, ERR
,
2006 "Allocation of RX shadow space failed.\n");
2009 qdev
->tx_ring_shadow_reg_area
=
2010 pci_alloc_consistent(qdev
->pdev
, PAGE_SIZE
,
2011 &qdev
->tx_ring_shadow_reg_dma
);
2012 if (qdev
->tx_ring_shadow_reg_area
== NULL
) {
2013 QPRINTK(qdev
, IFUP
, ERR
,
2014 "Allocation of TX shadow space failed.\n");
2015 goto err_wqp_sh_area
;
2020 pci_free_consistent(qdev
->pdev
,
2022 qdev
->rx_ring_shadow_reg_area
,
2023 qdev
->rx_ring_shadow_reg_dma
);
2027 static void ql_init_tx_ring(struct ql_adapter
*qdev
, struct tx_ring
*tx_ring
)
2029 struct tx_ring_desc
*tx_ring_desc
;
2031 struct ob_mac_iocb_req
*mac_iocb_ptr
;
2033 mac_iocb_ptr
= tx_ring
->wq_base
;
2034 tx_ring_desc
= tx_ring
->q
;
2035 for (i
= 0; i
< tx_ring
->wq_len
; i
++) {
2036 tx_ring_desc
->index
= i
;
2037 tx_ring_desc
->skb
= NULL
;
2038 tx_ring_desc
->queue_entry
= mac_iocb_ptr
;
2042 atomic_set(&tx_ring
->tx_count
, tx_ring
->wq_len
);
2043 atomic_set(&tx_ring
->queue_stopped
, 0);
2046 static void ql_free_tx_resources(struct ql_adapter
*qdev
,
2047 struct tx_ring
*tx_ring
)
2049 if (tx_ring
->wq_base
) {
2050 pci_free_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2051 tx_ring
->wq_base
, tx_ring
->wq_base_dma
);
2052 tx_ring
->wq_base
= NULL
;
2058 static int ql_alloc_tx_resources(struct ql_adapter
*qdev
,
2059 struct tx_ring
*tx_ring
)
2062 pci_alloc_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2063 &tx_ring
->wq_base_dma
);
2065 if ((tx_ring
->wq_base
== NULL
)
2066 || tx_ring
->wq_base_dma
& (tx_ring
->wq_size
- 1)) {
2067 QPRINTK(qdev
, IFUP
, ERR
, "tx_ring alloc failed.\n");
2071 kmalloc(tx_ring
->wq_len
* sizeof(struct tx_ring_desc
), GFP_KERNEL
);
2072 if (tx_ring
->q
== NULL
)
2077 pci_free_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2078 tx_ring
->wq_base
, tx_ring
->wq_base_dma
);
2082 static void ql_free_lbq_buffers(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2085 struct bq_desc
*lbq_desc
;
2087 for (i
= 0; i
< rx_ring
->lbq_len
; i
++) {
2088 lbq_desc
= &rx_ring
->lbq
[i
];
2089 if (lbq_desc
->p
.lbq_page
) {
2090 pci_unmap_page(qdev
->pdev
,
2091 pci_unmap_addr(lbq_desc
, mapaddr
),
2092 pci_unmap_len(lbq_desc
, maplen
),
2093 PCI_DMA_FROMDEVICE
);
2095 put_page(lbq_desc
->p
.lbq_page
);
2096 lbq_desc
->p
.lbq_page
= NULL
;
2102 * Allocate and map a page for each element of the lbq.
2104 static int ql_alloc_lbq_buffers(struct ql_adapter
*qdev
,
2105 struct rx_ring
*rx_ring
)
2108 struct bq_desc
*lbq_desc
;
2110 __le64
*bq
= rx_ring
->lbq_base
;
2112 for (i
= 0; i
< rx_ring
->lbq_len
; i
++) {
2113 lbq_desc
= &rx_ring
->lbq
[i
];
2114 memset(lbq_desc
, 0, sizeof(lbq_desc
));
2115 lbq_desc
->addr
= bq
;
2116 lbq_desc
->index
= i
;
2117 lbq_desc
->p
.lbq_page
= alloc_page(GFP_ATOMIC
);
2118 if (unlikely(!lbq_desc
->p
.lbq_page
)) {
2119 QPRINTK(qdev
, IFUP
, ERR
, "failed alloc_page().\n");
2122 map
= pci_map_page(qdev
->pdev
,
2123 lbq_desc
->p
.lbq_page
,
2124 0, PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
2125 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
2126 QPRINTK(qdev
, IFUP
, ERR
,
2127 "PCI mapping failed.\n");
2130 pci_unmap_addr_set(lbq_desc
, mapaddr
, map
);
2131 pci_unmap_len_set(lbq_desc
, maplen
, PAGE_SIZE
);
2132 *lbq_desc
->addr
= cpu_to_le64(map
);
2138 ql_free_lbq_buffers(qdev
, rx_ring
);
2142 static void ql_free_sbq_buffers(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2145 struct bq_desc
*sbq_desc
;
2147 for (i
= 0; i
< rx_ring
->sbq_len
; i
++) {
2148 sbq_desc
= &rx_ring
->sbq
[i
];
2149 if (sbq_desc
== NULL
) {
2150 QPRINTK(qdev
, IFUP
, ERR
, "sbq_desc %d is NULL.\n", i
);
2153 if (sbq_desc
->p
.skb
) {
2154 pci_unmap_single(qdev
->pdev
,
2155 pci_unmap_addr(sbq_desc
, mapaddr
),
2156 pci_unmap_len(sbq_desc
, maplen
),
2157 PCI_DMA_FROMDEVICE
);
2158 dev_kfree_skb(sbq_desc
->p
.skb
);
2159 sbq_desc
->p
.skb
= NULL
;
2164 /* Allocate and map an skb for each element of the sbq. */
2165 static int ql_alloc_sbq_buffers(struct ql_adapter
*qdev
,
2166 struct rx_ring
*rx_ring
)
2169 struct bq_desc
*sbq_desc
;
2170 struct sk_buff
*skb
;
2172 __le64
*bq
= rx_ring
->sbq_base
;
2174 for (i
= 0; i
< rx_ring
->sbq_len
; i
++) {
2175 sbq_desc
= &rx_ring
->sbq
[i
];
2176 memset(sbq_desc
, 0, sizeof(sbq_desc
));
2177 sbq_desc
->index
= i
;
2178 sbq_desc
->addr
= bq
;
2179 skb
= netdev_alloc_skb(qdev
->ndev
, rx_ring
->sbq_buf_size
);
2180 if (unlikely(!skb
)) {
2181 /* Better luck next round */
2182 QPRINTK(qdev
, IFUP
, ERR
,
2183 "small buff alloc failed for %d bytes at index %d.\n",
2184 rx_ring
->sbq_buf_size
, i
);
2187 skb_reserve(skb
, QLGE_SB_PAD
);
2188 sbq_desc
->p
.skb
= skb
;
2190 * Map only half the buffer. Because the
2191 * other half may get some data copied to it
2192 * when the completion arrives.
2194 map
= pci_map_single(qdev
->pdev
,
2196 rx_ring
->sbq_buf_size
/ 2,
2197 PCI_DMA_FROMDEVICE
);
2198 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
2199 QPRINTK(qdev
, IFUP
, ERR
, "PCI mapping failed.\n");
2202 pci_unmap_addr_set(sbq_desc
, mapaddr
, map
);
2203 pci_unmap_len_set(sbq_desc
, maplen
, rx_ring
->sbq_buf_size
/ 2);
2204 *sbq_desc
->addr
= cpu_to_le64(map
);
2209 ql_free_sbq_buffers(qdev
, rx_ring
);
2213 static void ql_free_rx_resources(struct ql_adapter
*qdev
,
2214 struct rx_ring
*rx_ring
)
2216 if (rx_ring
->sbq_len
)
2217 ql_free_sbq_buffers(qdev
, rx_ring
);
2218 if (rx_ring
->lbq_len
)
2219 ql_free_lbq_buffers(qdev
, rx_ring
);
2221 /* Free the small buffer queue. */
2222 if (rx_ring
->sbq_base
) {
2223 pci_free_consistent(qdev
->pdev
,
2225 rx_ring
->sbq_base
, rx_ring
->sbq_base_dma
);
2226 rx_ring
->sbq_base
= NULL
;
2229 /* Free the small buffer queue control blocks. */
2230 kfree(rx_ring
->sbq
);
2231 rx_ring
->sbq
= NULL
;
2233 /* Free the large buffer queue. */
2234 if (rx_ring
->lbq_base
) {
2235 pci_free_consistent(qdev
->pdev
,
2237 rx_ring
->lbq_base
, rx_ring
->lbq_base_dma
);
2238 rx_ring
->lbq_base
= NULL
;
2241 /* Free the large buffer queue control blocks. */
2242 kfree(rx_ring
->lbq
);
2243 rx_ring
->lbq
= NULL
;
2245 /* Free the rx queue. */
2246 if (rx_ring
->cq_base
) {
2247 pci_free_consistent(qdev
->pdev
,
2249 rx_ring
->cq_base
, rx_ring
->cq_base_dma
);
2250 rx_ring
->cq_base
= NULL
;
2254 /* Allocate queues and buffers for this completions queue based
2255 * on the values in the parameter structure. */
2256 static int ql_alloc_rx_resources(struct ql_adapter
*qdev
,
2257 struct rx_ring
*rx_ring
)
2261 * Allocate the completion queue for this rx_ring.
2264 pci_alloc_consistent(qdev
->pdev
, rx_ring
->cq_size
,
2265 &rx_ring
->cq_base_dma
);
2267 if (rx_ring
->cq_base
== NULL
) {
2268 QPRINTK(qdev
, IFUP
, ERR
, "rx_ring alloc failed.\n");
2272 if (rx_ring
->sbq_len
) {
2274 * Allocate small buffer queue.
2277 pci_alloc_consistent(qdev
->pdev
, rx_ring
->sbq_size
,
2278 &rx_ring
->sbq_base_dma
);
2280 if (rx_ring
->sbq_base
== NULL
) {
2281 QPRINTK(qdev
, IFUP
, ERR
,
2282 "Small buffer queue allocation failed.\n");
2287 * Allocate small buffer queue control blocks.
2290 kmalloc(rx_ring
->sbq_len
* sizeof(struct bq_desc
),
2292 if (rx_ring
->sbq
== NULL
) {
2293 QPRINTK(qdev
, IFUP
, ERR
,
2294 "Small buffer queue control block allocation failed.\n");
2298 if (ql_alloc_sbq_buffers(qdev
, rx_ring
)) {
2299 QPRINTK(qdev
, IFUP
, ERR
,
2300 "Small buffer allocation failed.\n");
2305 if (rx_ring
->lbq_len
) {
2307 * Allocate large buffer queue.
2310 pci_alloc_consistent(qdev
->pdev
, rx_ring
->lbq_size
,
2311 &rx_ring
->lbq_base_dma
);
2313 if (rx_ring
->lbq_base
== NULL
) {
2314 QPRINTK(qdev
, IFUP
, ERR
,
2315 "Large buffer queue allocation failed.\n");
2319 * Allocate large buffer queue control blocks.
2322 kmalloc(rx_ring
->lbq_len
* sizeof(struct bq_desc
),
2324 if (rx_ring
->lbq
== NULL
) {
2325 QPRINTK(qdev
, IFUP
, ERR
,
2326 "Large buffer queue control block allocation failed.\n");
2331 * Allocate the buffers.
2333 if (ql_alloc_lbq_buffers(qdev
, rx_ring
)) {
2334 QPRINTK(qdev
, IFUP
, ERR
,
2335 "Large buffer allocation failed.\n");
2343 ql_free_rx_resources(qdev
, rx_ring
);
2347 static void ql_tx_ring_clean(struct ql_adapter
*qdev
)
2349 struct tx_ring
*tx_ring
;
2350 struct tx_ring_desc
*tx_ring_desc
;
2354 * Loop through all queues and free
2357 for (j
= 0; j
< qdev
->tx_ring_count
; j
++) {
2358 tx_ring
= &qdev
->tx_ring
[j
];
2359 for (i
= 0; i
< tx_ring
->wq_len
; i
++) {
2360 tx_ring_desc
= &tx_ring
->q
[i
];
2361 if (tx_ring_desc
&& tx_ring_desc
->skb
) {
2362 QPRINTK(qdev
, IFDOWN
, ERR
,
2363 "Freeing lost SKB %p, from queue %d, index %d.\n",
2364 tx_ring_desc
->skb
, j
,
2365 tx_ring_desc
->index
);
2366 ql_unmap_send(qdev
, tx_ring_desc
,
2367 tx_ring_desc
->map_cnt
);
2368 dev_kfree_skb(tx_ring_desc
->skb
);
2369 tx_ring_desc
->skb
= NULL
;
2375 static void ql_free_mem_resources(struct ql_adapter
*qdev
)
2379 for (i
= 0; i
< qdev
->tx_ring_count
; i
++)
2380 ql_free_tx_resources(qdev
, &qdev
->tx_ring
[i
]);
2381 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2382 ql_free_rx_resources(qdev
, &qdev
->rx_ring
[i
]);
2383 ql_free_shadow_space(qdev
);
2386 static int ql_alloc_mem_resources(struct ql_adapter
*qdev
)
2390 /* Allocate space for our shadow registers and such. */
2391 if (ql_alloc_shadow_space(qdev
))
2394 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
2395 if (ql_alloc_rx_resources(qdev
, &qdev
->rx_ring
[i
]) != 0) {
2396 QPRINTK(qdev
, IFUP
, ERR
,
2397 "RX resource allocation failed.\n");
2401 /* Allocate tx queue resources */
2402 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
2403 if (ql_alloc_tx_resources(qdev
, &qdev
->tx_ring
[i
]) != 0) {
2404 QPRINTK(qdev
, IFUP
, ERR
,
2405 "TX resource allocation failed.\n");
2412 ql_free_mem_resources(qdev
);
2416 /* Set up the rx ring control block and pass it to the chip.
2417 * The control block is defined as
2418 * "Completion Queue Initialization Control Block", or cqicb.
2420 static int ql_start_rx_ring(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2422 struct cqicb
*cqicb
= &rx_ring
->cqicb
;
2423 void *shadow_reg
= qdev
->rx_ring_shadow_reg_area
+
2424 (rx_ring
->cq_id
* sizeof(u64
) * 4);
2425 u64 shadow_reg_dma
= qdev
->rx_ring_shadow_reg_dma
+
2426 (rx_ring
->cq_id
* sizeof(u64
) * 4);
2427 void __iomem
*doorbell_area
=
2428 qdev
->doorbell_area
+ (DB_PAGE_SIZE
* (128 + rx_ring
->cq_id
));
2432 /* Set up the shadow registers for this ring. */
2433 rx_ring
->prod_idx_sh_reg
= shadow_reg
;
2434 rx_ring
->prod_idx_sh_reg_dma
= shadow_reg_dma
;
2435 shadow_reg
+= sizeof(u64
);
2436 shadow_reg_dma
+= sizeof(u64
);
2437 rx_ring
->lbq_base_indirect
= shadow_reg
;
2438 rx_ring
->lbq_base_indirect_dma
= shadow_reg_dma
;
2439 shadow_reg
+= sizeof(u64
);
2440 shadow_reg_dma
+= sizeof(u64
);
2441 rx_ring
->sbq_base_indirect
= shadow_reg
;
2442 rx_ring
->sbq_base_indirect_dma
= shadow_reg_dma
;
2444 /* PCI doorbell mem area + 0x00 for consumer index register */
2445 rx_ring
->cnsmr_idx_db_reg
= (u32 __iomem
*) doorbell_area
;
2446 rx_ring
->cnsmr_idx
= 0;
2447 rx_ring
->curr_entry
= rx_ring
->cq_base
;
2449 /* PCI doorbell mem area + 0x04 for valid register */
2450 rx_ring
->valid_db_reg
= doorbell_area
+ 0x04;
2452 /* PCI doorbell mem area + 0x18 for large buffer consumer */
2453 rx_ring
->lbq_prod_idx_db_reg
= (u32 __iomem
*) (doorbell_area
+ 0x18);
2455 /* PCI doorbell mem area + 0x1c */
2456 rx_ring
->sbq_prod_idx_db_reg
= (u32 __iomem
*) (doorbell_area
+ 0x1c);
2458 memset((void *)cqicb
, 0, sizeof(struct cqicb
));
2459 cqicb
->msix_vect
= rx_ring
->irq
;
2461 bq_len
= (rx_ring
->cq_len
== 65536) ? 0 : (u16
) rx_ring
->cq_len
;
2462 cqicb
->len
= cpu_to_le16(bq_len
| LEN_V
| LEN_CPP_CONT
);
2464 cqicb
->addr
= cpu_to_le64(rx_ring
->cq_base_dma
);
2466 cqicb
->prod_idx_addr
= cpu_to_le64(rx_ring
->prod_idx_sh_reg_dma
);
2469 * Set up the control block load flags.
2471 cqicb
->flags
= FLAGS_LC
| /* Load queue base address */
2472 FLAGS_LV
| /* Load MSI-X vector */
2473 FLAGS_LI
; /* Load irq delay values */
2474 if (rx_ring
->lbq_len
) {
2475 cqicb
->flags
|= FLAGS_LL
; /* Load lbq values */
2476 *((u64
*) rx_ring
->lbq_base_indirect
) = rx_ring
->lbq_base_dma
;
2478 cpu_to_le64(rx_ring
->lbq_base_indirect_dma
);
2479 bq_len
= (rx_ring
->lbq_buf_size
== 65536) ? 0 :
2480 (u16
) rx_ring
->lbq_buf_size
;
2481 cqicb
->lbq_buf_size
= cpu_to_le16(bq_len
);
2482 bq_len
= (rx_ring
->lbq_len
== 65536) ? 0 :
2483 (u16
) rx_ring
->lbq_len
;
2484 cqicb
->lbq_len
= cpu_to_le16(bq_len
);
2485 rx_ring
->lbq_prod_idx
= rx_ring
->lbq_len
- 16;
2486 rx_ring
->lbq_curr_idx
= 0;
2487 rx_ring
->lbq_clean_idx
= rx_ring
->lbq_prod_idx
;
2488 rx_ring
->lbq_free_cnt
= 16;
2490 if (rx_ring
->sbq_len
) {
2491 cqicb
->flags
|= FLAGS_LS
; /* Load sbq values */
2492 *((u64
*) rx_ring
->sbq_base_indirect
) = rx_ring
->sbq_base_dma
;
2494 cpu_to_le64(rx_ring
->sbq_base_indirect_dma
);
2495 cqicb
->sbq_buf_size
=
2496 cpu_to_le16(((rx_ring
->sbq_buf_size
/ 2) + 8) & 0xfffffff8);
2497 bq_len
= (rx_ring
->sbq_len
== 65536) ? 0 :
2498 (u16
) rx_ring
->sbq_len
;
2499 cqicb
->sbq_len
= cpu_to_le16(bq_len
);
2500 rx_ring
->sbq_prod_idx
= rx_ring
->sbq_len
- 16;
2501 rx_ring
->sbq_curr_idx
= 0;
2502 rx_ring
->sbq_clean_idx
= rx_ring
->sbq_prod_idx
;
2503 rx_ring
->sbq_free_cnt
= 16;
2505 switch (rx_ring
->type
) {
2507 /* If there's only one interrupt, then we use
2508 * worker threads to process the outbound
2509 * completion handling rx_rings. We do this so
2510 * they can be run on multiple CPUs. There is
2511 * room to play with this more where we would only
2512 * run in a worker if there are more than x number
2513 * of outbound completions on the queue and more
2514 * than one queue active. Some threshold that
2515 * would indicate a benefit in spite of the cost
2516 * of a context switch.
2517 * If there's more than one interrupt, then the
2518 * outbound completions are processed in the ISR.
2520 if (!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
))
2521 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_tx_clean
);
2523 /* With all debug warnings on we see a WARN_ON message
2524 * when we free the skb in the interrupt context.
2526 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_tx_clean
);
2528 cqicb
->irq_delay
= cpu_to_le16(qdev
->tx_coalesce_usecs
);
2529 cqicb
->pkt_delay
= cpu_to_le16(qdev
->tx_max_coalesced_frames
);
2532 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_rx_clean
);
2533 cqicb
->irq_delay
= 0;
2534 cqicb
->pkt_delay
= 0;
2537 /* Inbound completion handling rx_rings run in
2538 * separate NAPI contexts.
2540 netif_napi_add(qdev
->ndev
, &rx_ring
->napi
, ql_napi_poll_msix
,
2542 cqicb
->irq_delay
= cpu_to_le16(qdev
->rx_coalesce_usecs
);
2543 cqicb
->pkt_delay
= cpu_to_le16(qdev
->rx_max_coalesced_frames
);
2546 QPRINTK(qdev
, IFUP
, DEBUG
, "Invalid rx_ring->type = %d.\n",
2549 QPRINTK(qdev
, IFUP
, INFO
, "Initializing rx work queue.\n");
2550 err
= ql_write_cfg(qdev
, cqicb
, sizeof(struct cqicb
),
2551 CFG_LCQ
, rx_ring
->cq_id
);
2553 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load CQICB.\n");
2556 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded CQICB.\n");
2558 * Advance the producer index for the buffer queues.
2561 if (rx_ring
->lbq_len
)
2562 ql_write_db_reg(rx_ring
->lbq_prod_idx
,
2563 rx_ring
->lbq_prod_idx_db_reg
);
2564 if (rx_ring
->sbq_len
)
2565 ql_write_db_reg(rx_ring
->sbq_prod_idx
,
2566 rx_ring
->sbq_prod_idx_db_reg
);
2570 static int ql_start_tx_ring(struct ql_adapter
*qdev
, struct tx_ring
*tx_ring
)
2572 struct wqicb
*wqicb
= (struct wqicb
*)tx_ring
;
2573 void __iomem
*doorbell_area
=
2574 qdev
->doorbell_area
+ (DB_PAGE_SIZE
* tx_ring
->wq_id
);
2575 void *shadow_reg
= qdev
->tx_ring_shadow_reg_area
+
2576 (tx_ring
->wq_id
* sizeof(u64
));
2577 u64 shadow_reg_dma
= qdev
->tx_ring_shadow_reg_dma
+
2578 (tx_ring
->wq_id
* sizeof(u64
));
2582 * Assign doorbell registers for this tx_ring.
2584 /* TX PCI doorbell mem area for tx producer index */
2585 tx_ring
->prod_idx_db_reg
= (u32 __iomem
*) doorbell_area
;
2586 tx_ring
->prod_idx
= 0;
2587 /* TX PCI doorbell mem area + 0x04 */
2588 tx_ring
->valid_db_reg
= doorbell_area
+ 0x04;
2591 * Assign shadow registers for this tx_ring.
2593 tx_ring
->cnsmr_idx_sh_reg
= shadow_reg
;
2594 tx_ring
->cnsmr_idx_sh_reg_dma
= shadow_reg_dma
;
2596 wqicb
->len
= cpu_to_le16(tx_ring
->wq_len
| Q_LEN_V
| Q_LEN_CPP_CONT
);
2597 wqicb
->flags
= cpu_to_le16(Q_FLAGS_LC
|
2598 Q_FLAGS_LB
| Q_FLAGS_LI
| Q_FLAGS_LO
);
2599 wqicb
->cq_id_rss
= cpu_to_le16(tx_ring
->cq_id
);
2601 wqicb
->addr
= cpu_to_le64(tx_ring
->wq_base_dma
);
2603 wqicb
->cnsmr_idx_addr
= cpu_to_le64(tx_ring
->cnsmr_idx_sh_reg_dma
);
2605 ql_init_tx_ring(qdev
, tx_ring
);
2607 err
= ql_write_cfg(qdev
, wqicb
, sizeof(wqicb
), CFG_LRQ
,
2608 (u16
) tx_ring
->wq_id
);
2610 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load tx_ring.\n");
2613 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded WQICB.\n");
2617 static void ql_disable_msix(struct ql_adapter
*qdev
)
2619 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2620 pci_disable_msix(qdev
->pdev
);
2621 clear_bit(QL_MSIX_ENABLED
, &qdev
->flags
);
2622 kfree(qdev
->msi_x_entry
);
2623 qdev
->msi_x_entry
= NULL
;
2624 } else if (test_bit(QL_MSI_ENABLED
, &qdev
->flags
)) {
2625 pci_disable_msi(qdev
->pdev
);
2626 clear_bit(QL_MSI_ENABLED
, &qdev
->flags
);
2630 static void ql_enable_msix(struct ql_adapter
*qdev
)
2634 qdev
->intr_count
= 1;
2635 /* Get the MSIX vectors. */
2636 if (irq_type
== MSIX_IRQ
) {
2637 /* Try to alloc space for the msix struct,
2638 * if it fails then go to MSI/legacy.
2640 qdev
->msi_x_entry
= kcalloc(qdev
->rx_ring_count
,
2641 sizeof(struct msix_entry
),
2643 if (!qdev
->msi_x_entry
) {
2648 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2649 qdev
->msi_x_entry
[i
].entry
= i
;
2651 if (!pci_enable_msix
2652 (qdev
->pdev
, qdev
->msi_x_entry
, qdev
->rx_ring_count
)) {
2653 set_bit(QL_MSIX_ENABLED
, &qdev
->flags
);
2654 qdev
->intr_count
= qdev
->rx_ring_count
;
2655 QPRINTK(qdev
, IFUP
, INFO
,
2656 "MSI-X Enabled, got %d vectors.\n",
2660 kfree(qdev
->msi_x_entry
);
2661 qdev
->msi_x_entry
= NULL
;
2662 QPRINTK(qdev
, IFUP
, WARNING
,
2663 "MSI-X Enable failed, trying MSI.\n");
2668 if (irq_type
== MSI_IRQ
) {
2669 if (!pci_enable_msi(qdev
->pdev
)) {
2670 set_bit(QL_MSI_ENABLED
, &qdev
->flags
);
2671 QPRINTK(qdev
, IFUP
, INFO
,
2672 "Running with MSI interrupts.\n");
2677 QPRINTK(qdev
, IFUP
, DEBUG
, "Running with legacy interrupts.\n");
2681 * Here we build the intr_context structures based on
2682 * our rx_ring count and intr vector count.
2683 * The intr_context structure is used to hook each vector
2684 * to possibly different handlers.
2686 static void ql_resolve_queues_to_irqs(struct ql_adapter
*qdev
)
2689 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2691 ql_enable_msix(qdev
);
2693 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
))) {
2694 /* Each rx_ring has it's
2695 * own intr_context since we have separate
2696 * vectors for each queue.
2697 * This only true when MSI-X is enabled.
2699 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2700 qdev
->rx_ring
[i
].irq
= i
;
2701 intr_context
->intr
= i
;
2702 intr_context
->qdev
= qdev
;
2704 * We set up each vectors enable/disable/read bits so
2705 * there's no bit/mask calculations in the critical path.
2707 intr_context
->intr_en_mask
=
2708 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2709 INTR_EN_TYPE_ENABLE
| INTR_EN_IHD_MASK
| INTR_EN_IHD
2711 intr_context
->intr_dis_mask
=
2712 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2713 INTR_EN_TYPE_DISABLE
| INTR_EN_IHD_MASK
|
2715 intr_context
->intr_read_mask
=
2716 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2717 INTR_EN_TYPE_READ
| INTR_EN_IHD_MASK
| INTR_EN_IHD
|
2722 * Default queue handles bcast/mcast plus
2723 * async events. Needs buffers.
2725 intr_context
->handler
= qlge_isr
;
2726 sprintf(intr_context
->name
, "%s-default-queue",
2728 } else if (i
< qdev
->rss_ring_first_cq_id
) {
2730 * Outbound queue is for outbound completions only.
2732 intr_context
->handler
= qlge_msix_tx_isr
;
2733 sprintf(intr_context
->name
, "%s-tx-%d",
2734 qdev
->ndev
->name
, i
);
2737 * Inbound queues handle unicast frames only.
2739 intr_context
->handler
= qlge_msix_rx_isr
;
2740 sprintf(intr_context
->name
, "%s-rx-%d",
2741 qdev
->ndev
->name
, i
);
2746 * All rx_rings use the same intr_context since
2747 * there is only one vector.
2749 intr_context
->intr
= 0;
2750 intr_context
->qdev
= qdev
;
2752 * We set up each vectors enable/disable/read bits so
2753 * there's no bit/mask calculations in the critical path.
2755 intr_context
->intr_en_mask
=
2756 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
| INTR_EN_TYPE_ENABLE
;
2757 intr_context
->intr_dis_mask
=
2758 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2759 INTR_EN_TYPE_DISABLE
;
2760 intr_context
->intr_read_mask
=
2761 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
| INTR_EN_TYPE_READ
;
2763 * Single interrupt means one handler for all rings.
2765 intr_context
->handler
= qlge_isr
;
2766 sprintf(intr_context
->name
, "%s-single_irq", qdev
->ndev
->name
);
2767 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2768 qdev
->rx_ring
[i
].irq
= 0;
2772 static void ql_free_irq(struct ql_adapter
*qdev
)
2775 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2777 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2778 if (intr_context
->hooked
) {
2779 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2780 free_irq(qdev
->msi_x_entry
[i
].vector
,
2782 QPRINTK(qdev
, IFDOWN
, ERR
,
2783 "freeing msix interrupt %d.\n", i
);
2785 free_irq(qdev
->pdev
->irq
, &qdev
->rx_ring
[0]);
2786 QPRINTK(qdev
, IFDOWN
, ERR
,
2787 "freeing msi interrupt %d.\n", i
);
2791 ql_disable_msix(qdev
);
2794 static int ql_request_irq(struct ql_adapter
*qdev
)
2798 struct pci_dev
*pdev
= qdev
->pdev
;
2799 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2801 ql_resolve_queues_to_irqs(qdev
);
2803 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2804 atomic_set(&intr_context
->irq_cnt
, 0);
2805 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2806 status
= request_irq(qdev
->msi_x_entry
[i
].vector
,
2807 intr_context
->handler
,
2812 QPRINTK(qdev
, IFUP
, ERR
,
2813 "Failed request for MSIX interrupt %d.\n",
2817 QPRINTK(qdev
, IFUP
, INFO
,
2818 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2820 qdev
->rx_ring
[i
].type
==
2821 DEFAULT_Q
? "DEFAULT_Q" : "",
2822 qdev
->rx_ring
[i
].type
==
2824 qdev
->rx_ring
[i
].type
==
2825 RX_Q
? "RX_Q" : "", intr_context
->name
);
2828 QPRINTK(qdev
, IFUP
, DEBUG
,
2829 "trying msi or legacy interrupts.\n");
2830 QPRINTK(qdev
, IFUP
, DEBUG
,
2831 "%s: irq = %d.\n", __func__
, pdev
->irq
);
2832 QPRINTK(qdev
, IFUP
, DEBUG
,
2833 "%s: context->name = %s.\n", __func__
,
2834 intr_context
->name
);
2835 QPRINTK(qdev
, IFUP
, DEBUG
,
2836 "%s: dev_id = 0x%p.\n", __func__
,
2839 request_irq(pdev
->irq
, qlge_isr
,
2840 test_bit(QL_MSI_ENABLED
,
2842 flags
) ? 0 : IRQF_SHARED
,
2843 intr_context
->name
, &qdev
->rx_ring
[0]);
2847 QPRINTK(qdev
, IFUP
, ERR
,
2848 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2850 qdev
->rx_ring
[0].type
==
2851 DEFAULT_Q
? "DEFAULT_Q" : "",
2852 qdev
->rx_ring
[0].type
== TX_Q
? "TX_Q" : "",
2853 qdev
->rx_ring
[0].type
== RX_Q
? "RX_Q" : "",
2854 intr_context
->name
);
2856 intr_context
->hooked
= 1;
2860 QPRINTK(qdev
, IFUP
, ERR
, "Failed to get the interrupts!!!/n");
2865 static int ql_start_rss(struct ql_adapter
*qdev
)
2867 struct ricb
*ricb
= &qdev
->ricb
;
2870 u8
*hash_id
= (u8
*) ricb
->hash_cq_id
;
2872 memset((void *)ricb
, 0, sizeof(ricb
));
2874 ricb
->base_cq
= qdev
->rss_ring_first_cq_id
| RSS_L4K
;
2876 (RSS_L6K
| RSS_LI
| RSS_LB
| RSS_LM
| RSS_RI4
| RSS_RI6
| RSS_RT4
|
2878 ricb
->mask
= cpu_to_le16(qdev
->rss_ring_count
- 1);
2881 * Fill out the Indirection Table.
2883 for (i
= 0; i
< 32; i
++)
2887 * Random values for the IPv6 and IPv4 Hash Keys.
2889 get_random_bytes((void *)&ricb
->ipv6_hash_key
[0], 40);
2890 get_random_bytes((void *)&ricb
->ipv4_hash_key
[0], 16);
2892 QPRINTK(qdev
, IFUP
, INFO
, "Initializing RSS.\n");
2894 status
= ql_write_cfg(qdev
, ricb
, sizeof(ricb
), CFG_LR
, 0);
2896 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load RICB.\n");
2899 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded RICB.\n");
2903 /* Initialize the frame-to-queue routing. */
2904 static int ql_route_initialize(struct ql_adapter
*qdev
)
2909 /* Clear all the entries in the routing table. */
2910 for (i
= 0; i
< 16; i
++) {
2911 status
= ql_set_routing_reg(qdev
, i
, 0, 0);
2913 QPRINTK(qdev
, IFUP
, ERR
,
2914 "Failed to init routing register for CAM packets.\n");
2919 status
= ql_set_routing_reg(qdev
, RT_IDX_ALL_ERR_SLOT
, RT_IDX_ERR
, 1);
2921 QPRINTK(qdev
, IFUP
, ERR
,
2922 "Failed to init routing register for error packets.\n");
2925 status
= ql_set_routing_reg(qdev
, RT_IDX_BCAST_SLOT
, RT_IDX_BCAST
, 1);
2927 QPRINTK(qdev
, IFUP
, ERR
,
2928 "Failed to init routing register for broadcast packets.\n");
2931 /* If we have more than one inbound queue, then turn on RSS in the
2934 if (qdev
->rss_ring_count
> 1) {
2935 status
= ql_set_routing_reg(qdev
, RT_IDX_RSS_MATCH_SLOT
,
2936 RT_IDX_RSS_MATCH
, 1);
2938 QPRINTK(qdev
, IFUP
, ERR
,
2939 "Failed to init routing register for MATCH RSS packets.\n");
2944 status
= ql_set_routing_reg(qdev
, RT_IDX_CAM_HIT_SLOT
,
2947 QPRINTK(qdev
, IFUP
, ERR
,
2948 "Failed to init routing register for CAM packets.\n");
2954 static int ql_adapter_initialize(struct ql_adapter
*qdev
)
2961 * Set up the System register to halt on errors.
2963 value
= SYS_EFE
| SYS_FAE
;
2965 ql_write32(qdev
, SYS
, mask
| value
);
2967 /* Set the default queue. */
2968 value
= NIC_RCV_CFG_DFQ
;
2969 mask
= NIC_RCV_CFG_DFQ_MASK
;
2970 ql_write32(qdev
, NIC_RCV_CFG
, (mask
| value
));
2972 /* Set the MPI interrupt to enabled. */
2973 ql_write32(qdev
, INTR_MASK
, (INTR_MASK_PI
<< 16) | INTR_MASK_PI
);
2975 /* Enable the function, set pagesize, enable error checking. */
2976 value
= FSC_FE
| FSC_EPC_INBOUND
| FSC_EPC_OUTBOUND
|
2977 FSC_EC
| FSC_VM_PAGE_4K
| FSC_SH
;
2979 /* Set/clear header splitting. */
2980 mask
= FSC_VM_PAGESIZE_MASK
|
2981 FSC_DBL_MASK
| FSC_DBRST_MASK
| (value
<< 16);
2982 ql_write32(qdev
, FSC
, mask
| value
);
2984 ql_write32(qdev
, SPLT_HDR
, SPLT_HDR_EP
|
2985 min(SMALL_BUFFER_SIZE
, MAX_SPLIT_SIZE
));
2987 /* Start up the rx queues. */
2988 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
2989 status
= ql_start_rx_ring(qdev
, &qdev
->rx_ring
[i
]);
2991 QPRINTK(qdev
, IFUP
, ERR
,
2992 "Failed to start rx ring[%d].\n", i
);
2997 /* If there is more than one inbound completion queue
2998 * then download a RICB to configure RSS.
3000 if (qdev
->rss_ring_count
> 1) {
3001 status
= ql_start_rss(qdev
);
3003 QPRINTK(qdev
, IFUP
, ERR
, "Failed to start RSS.\n");
3008 /* Start up the tx queues. */
3009 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
3010 status
= ql_start_tx_ring(qdev
, &qdev
->tx_ring
[i
]);
3012 QPRINTK(qdev
, IFUP
, ERR
,
3013 "Failed to start tx ring[%d].\n", i
);
3018 status
= ql_port_initialize(qdev
);
3020 QPRINTK(qdev
, IFUP
, ERR
, "Failed to start port.\n");
3024 status
= ql_set_mac_addr_reg(qdev
, (u8
*) qdev
->ndev
->perm_addr
,
3025 MAC_ADDR_TYPE_CAM_MAC
, qdev
->func
);
3027 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init mac address.\n");
3031 status
= ql_route_initialize(qdev
);
3033 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init routing table.\n");
3037 /* Start NAPI for the RSS queues. */
3038 for (i
= qdev
->rss_ring_first_cq_id
; i
< qdev
->rx_ring_count
; i
++) {
3039 QPRINTK(qdev
, IFUP
, INFO
, "Enabling NAPI for rx_ring[%d].\n",
3041 napi_enable(&qdev
->rx_ring
[i
].napi
);
3047 /* Issue soft reset to chip. */
3048 static int ql_adapter_reset(struct ql_adapter
*qdev
)
3055 #define MAX_RESET_CNT 1
3058 QPRINTK(qdev
, IFDOWN
, DEBUG
, "Issue soft reset to chip.\n");
3059 ql_write32(qdev
, RST_FO
, (RST_FO_FR
<< 16) | RST_FO_FR
);
3060 /* Wait for reset to complete. */
3062 QPRINTK(qdev
, IFDOWN
, DEBUG
, "Wait %d seconds for reset to complete.\n",
3065 value
= ql_read32(qdev
, RST_FO
);
3066 if ((value
& RST_FO_FR
) == 0)
3070 } while ((--max_wait_time
));
3071 if (value
& RST_FO_FR
) {
3072 QPRINTK(qdev
, IFDOWN
, ERR
,
3073 "Stuck in SoftReset: FSC_SR:0x%08x\n", value
);
3074 if (resetCnt
< MAX_RESET_CNT
)
3077 if (max_wait_time
== 0) {
3078 status
= -ETIMEDOUT
;
3079 QPRINTK(qdev
, IFDOWN
, ERR
,
3080 "ETIMEOUT!!! errored out of resetting the chip!\n");
3086 static void ql_display_dev_info(struct net_device
*ndev
)
3088 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3090 QPRINTK(qdev
, PROBE
, INFO
,
3091 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3092 "XG Roll = %d, XG Rev = %d.\n",
3094 qdev
->chip_rev_id
& 0x0000000f,
3095 qdev
->chip_rev_id
>> 4 & 0x0000000f,
3096 qdev
->chip_rev_id
>> 8 & 0x0000000f,
3097 qdev
->chip_rev_id
>> 12 & 0x0000000f);
3098 QPRINTK(qdev
, PROBE
, INFO
, "MAC address %pM\n", ndev
->dev_addr
);
3101 static int ql_adapter_down(struct ql_adapter
*qdev
)
3103 struct net_device
*ndev
= qdev
->ndev
;
3105 struct rx_ring
*rx_ring
;
3107 netif_stop_queue(ndev
);
3108 netif_carrier_off(ndev
);
3110 /* Don't kill the reset worker thread if we
3111 * are in the process of recovery.
3113 if (test_bit(QL_ADAPTER_UP
, &qdev
->flags
))
3114 cancel_delayed_work_sync(&qdev
->asic_reset_work
);
3115 cancel_delayed_work_sync(&qdev
->mpi_reset_work
);
3116 cancel_delayed_work_sync(&qdev
->mpi_work
);
3118 /* The default queue at index 0 is always processed in
3121 cancel_delayed_work_sync(&qdev
->rx_ring
[0].rx_work
);
3123 /* The rest of the rx_rings are processed in
3124 * a workqueue only if it's a single interrupt
3125 * environment (MSI/Legacy).
3127 for (i
= 1; i
< qdev
->rx_ring_count
; i
++) {
3128 rx_ring
= &qdev
->rx_ring
[i
];
3129 /* Only the RSS rings use NAPI on multi irq
3130 * environment. Outbound completion processing
3131 * is done in interrupt context.
3133 if (i
>= qdev
->rss_ring_first_cq_id
) {
3134 napi_disable(&rx_ring
->napi
);
3136 cancel_delayed_work_sync(&rx_ring
->rx_work
);
3140 clear_bit(QL_ADAPTER_UP
, &qdev
->flags
);
3142 ql_disable_interrupts(qdev
);
3144 ql_tx_ring_clean(qdev
);
3146 spin_lock(&qdev
->hw_lock
);
3147 status
= ql_adapter_reset(qdev
);
3149 QPRINTK(qdev
, IFDOWN
, ERR
, "reset(func #%d) FAILED!\n",
3151 spin_unlock(&qdev
->hw_lock
);
3155 static int ql_adapter_up(struct ql_adapter
*qdev
)
3159 spin_lock(&qdev
->hw_lock
);
3160 err
= ql_adapter_initialize(qdev
);
3162 QPRINTK(qdev
, IFUP
, INFO
, "Unable to initialize adapter.\n");
3163 spin_unlock(&qdev
->hw_lock
);
3166 spin_unlock(&qdev
->hw_lock
);
3167 set_bit(QL_ADAPTER_UP
, &qdev
->flags
);
3168 ql_enable_interrupts(qdev
);
3169 ql_enable_all_completion_interrupts(qdev
);
3170 if ((ql_read32(qdev
, STS
) & qdev
->port_init
)) {
3171 netif_carrier_on(qdev
->ndev
);
3172 netif_start_queue(qdev
->ndev
);
3177 ql_adapter_reset(qdev
);
3181 static int ql_cycle_adapter(struct ql_adapter
*qdev
)
3185 status
= ql_adapter_down(qdev
);
3189 status
= ql_adapter_up(qdev
);
3195 QPRINTK(qdev
, IFUP
, ALERT
,
3196 "Driver up/down cycle failed, closing device\n");
3198 dev_close(qdev
->ndev
);
3203 static void ql_release_adapter_resources(struct ql_adapter
*qdev
)
3205 ql_free_mem_resources(qdev
);
3209 static int ql_get_adapter_resources(struct ql_adapter
*qdev
)
3213 if (ql_alloc_mem_resources(qdev
)) {
3214 QPRINTK(qdev
, IFUP
, ERR
, "Unable to allocate memory.\n");
3217 status
= ql_request_irq(qdev
);
3222 ql_free_mem_resources(qdev
);
3226 static int qlge_close(struct net_device
*ndev
)
3228 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3231 * Wait for device to recover from a reset.
3232 * (Rarely happens, but possible.)
3234 while (!test_bit(QL_ADAPTER_UP
, &qdev
->flags
))
3236 ql_adapter_down(qdev
);
3237 ql_release_adapter_resources(qdev
);
3241 static int ql_configure_rings(struct ql_adapter
*qdev
)
3244 struct rx_ring
*rx_ring
;
3245 struct tx_ring
*tx_ring
;
3246 int cpu_cnt
= num_online_cpus();
3249 * For each processor present we allocate one
3250 * rx_ring for outbound completions, and one
3251 * rx_ring for inbound completions. Plus there is
3252 * always the one default queue. For the CPU
3253 * counts we end up with the following rx_rings:
3255 * one default queue +
3256 * (CPU count * outbound completion rx_ring) +
3257 * (CPU count * inbound (RSS) completion rx_ring)
3258 * To keep it simple we limit the total number of
3259 * queues to < 32, so we truncate CPU to 8.
3260 * This limitation can be removed when requested.
3263 if (cpu_cnt
> MAX_CPUS
)
3267 * rx_ring[0] is always the default queue.
3269 /* Allocate outbound completion ring for each CPU. */
3270 qdev
->tx_ring_count
= cpu_cnt
;
3271 /* Allocate inbound completion (RSS) ring for each CPU. */
3272 qdev
->rss_ring_count
= cpu_cnt
;
3273 /* cq_id for the first inbound ring handler. */
3274 qdev
->rss_ring_first_cq_id
= cpu_cnt
+ 1;
3276 * qdev->rx_ring_count:
3277 * Total number of rx_rings. This includes the one
3278 * default queue, a number of outbound completion
3279 * handler rx_rings, and the number of inbound
3280 * completion handler rx_rings.
3282 qdev
->rx_ring_count
= qdev
->tx_ring_count
+ qdev
->rss_ring_count
+ 1;
3284 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
3285 tx_ring
= &qdev
->tx_ring
[i
];
3286 memset((void *)tx_ring
, 0, sizeof(tx_ring
));
3287 tx_ring
->qdev
= qdev
;
3289 tx_ring
->wq_len
= qdev
->tx_ring_size
;
3291 tx_ring
->wq_len
* sizeof(struct ob_mac_iocb_req
);
3294 * The completion queue ID for the tx rings start
3295 * immediately after the default Q ID, which is zero.
3297 tx_ring
->cq_id
= i
+ 1;
3300 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
3301 rx_ring
= &qdev
->rx_ring
[i
];
3302 memset((void *)rx_ring
, 0, sizeof(rx_ring
));
3303 rx_ring
->qdev
= qdev
;
3305 rx_ring
->cpu
= i
% cpu_cnt
; /* CPU to run handler on. */
3306 if (i
== 0) { /* Default queue at index 0. */
3308 * Default queue handles bcast/mcast plus
3309 * async events. Needs buffers.
3311 rx_ring
->cq_len
= qdev
->rx_ring_size
;
3313 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3314 rx_ring
->lbq_len
= NUM_LARGE_BUFFERS
;
3316 rx_ring
->lbq_len
* sizeof(__le64
);
3317 rx_ring
->lbq_buf_size
= LARGE_BUFFER_SIZE
;
3318 rx_ring
->sbq_len
= NUM_SMALL_BUFFERS
;
3320 rx_ring
->sbq_len
* sizeof(__le64
);
3321 rx_ring
->sbq_buf_size
= SMALL_BUFFER_SIZE
* 2;
3322 rx_ring
->type
= DEFAULT_Q
;
3323 } else if (i
< qdev
->rss_ring_first_cq_id
) {
3325 * Outbound queue handles outbound completions only.
3327 /* outbound cq is same size as tx_ring it services. */
3328 rx_ring
->cq_len
= qdev
->tx_ring_size
;
3330 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3331 rx_ring
->lbq_len
= 0;
3332 rx_ring
->lbq_size
= 0;
3333 rx_ring
->lbq_buf_size
= 0;
3334 rx_ring
->sbq_len
= 0;
3335 rx_ring
->sbq_size
= 0;
3336 rx_ring
->sbq_buf_size
= 0;
3337 rx_ring
->type
= TX_Q
;
3338 } else { /* Inbound completions (RSS) queues */
3340 * Inbound queues handle unicast frames only.
3342 rx_ring
->cq_len
= qdev
->rx_ring_size
;
3344 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3345 rx_ring
->lbq_len
= NUM_LARGE_BUFFERS
;
3347 rx_ring
->lbq_len
* sizeof(__le64
);
3348 rx_ring
->lbq_buf_size
= LARGE_BUFFER_SIZE
;
3349 rx_ring
->sbq_len
= NUM_SMALL_BUFFERS
;
3351 rx_ring
->sbq_len
* sizeof(__le64
);
3352 rx_ring
->sbq_buf_size
= SMALL_BUFFER_SIZE
* 2;
3353 rx_ring
->type
= RX_Q
;
3359 static int qlge_open(struct net_device
*ndev
)
3362 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3364 err
= ql_configure_rings(qdev
);
3368 err
= ql_get_adapter_resources(qdev
);
3372 err
= ql_adapter_up(qdev
);
3379 ql_release_adapter_resources(qdev
);
3383 static int qlge_change_mtu(struct net_device
*ndev
, int new_mtu
)
3385 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3387 if (ndev
->mtu
== 1500 && new_mtu
== 9000) {
3388 QPRINTK(qdev
, IFUP
, ERR
, "Changing to jumbo MTU.\n");
3389 } else if (ndev
->mtu
== 9000 && new_mtu
== 1500) {
3390 QPRINTK(qdev
, IFUP
, ERR
, "Changing to normal MTU.\n");
3391 } else if ((ndev
->mtu
== 1500 && new_mtu
== 1500) ||
3392 (ndev
->mtu
== 9000 && new_mtu
== 9000)) {
3396 ndev
->mtu
= new_mtu
;
3400 static struct net_device_stats
*qlge_get_stats(struct net_device
3403 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3404 return &qdev
->stats
;
3407 static void qlge_set_multicast_list(struct net_device
*ndev
)
3409 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3410 struct dev_mc_list
*mc_ptr
;
3413 spin_lock(&qdev
->hw_lock
);
3415 * Set or clear promiscuous mode if a
3416 * transition is taking place.
3418 if (ndev
->flags
& IFF_PROMISC
) {
3419 if (!test_bit(QL_PROMISCUOUS
, &qdev
->flags
)) {
3420 if (ql_set_routing_reg
3421 (qdev
, RT_IDX_PROMISCUOUS_SLOT
, RT_IDX_VALID
, 1)) {
3422 QPRINTK(qdev
, HW
, ERR
,
3423 "Failed to set promiscous mode.\n");
3425 set_bit(QL_PROMISCUOUS
, &qdev
->flags
);
3429 if (test_bit(QL_PROMISCUOUS
, &qdev
->flags
)) {
3430 if (ql_set_routing_reg
3431 (qdev
, RT_IDX_PROMISCUOUS_SLOT
, RT_IDX_VALID
, 0)) {
3432 QPRINTK(qdev
, HW
, ERR
,
3433 "Failed to clear promiscous mode.\n");
3435 clear_bit(QL_PROMISCUOUS
, &qdev
->flags
);
3441 * Set or clear all multicast mode if a
3442 * transition is taking place.
3444 if ((ndev
->flags
& IFF_ALLMULTI
) ||
3445 (ndev
->mc_count
> MAX_MULTICAST_ENTRIES
)) {
3446 if (!test_bit(QL_ALLMULTI
, &qdev
->flags
)) {
3447 if (ql_set_routing_reg
3448 (qdev
, RT_IDX_ALLMULTI_SLOT
, RT_IDX_MCAST
, 1)) {
3449 QPRINTK(qdev
, HW
, ERR
,
3450 "Failed to set all-multi mode.\n");
3452 set_bit(QL_ALLMULTI
, &qdev
->flags
);
3456 if (test_bit(QL_ALLMULTI
, &qdev
->flags
)) {
3457 if (ql_set_routing_reg
3458 (qdev
, RT_IDX_ALLMULTI_SLOT
, RT_IDX_MCAST
, 0)) {
3459 QPRINTK(qdev
, HW
, ERR
,
3460 "Failed to clear all-multi mode.\n");
3462 clear_bit(QL_ALLMULTI
, &qdev
->flags
);
3467 if (ndev
->mc_count
) {
3468 for (i
= 0, mc_ptr
= ndev
->mc_list
; mc_ptr
;
3469 i
++, mc_ptr
= mc_ptr
->next
)
3470 if (ql_set_mac_addr_reg(qdev
, (u8
*) mc_ptr
->dmi_addr
,
3471 MAC_ADDR_TYPE_MULTI_MAC
, i
)) {
3472 QPRINTK(qdev
, HW
, ERR
,
3473 "Failed to loadmulticast address.\n");
3476 if (ql_set_routing_reg
3477 (qdev
, RT_IDX_MCAST_MATCH_SLOT
, RT_IDX_MCAST_MATCH
, 1)) {
3478 QPRINTK(qdev
, HW
, ERR
,
3479 "Failed to set multicast match mode.\n");
3481 set_bit(QL_ALLMULTI
, &qdev
->flags
);
3485 spin_unlock(&qdev
->hw_lock
);
3488 static int qlge_set_mac_address(struct net_device
*ndev
, void *p
)
3490 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3491 struct sockaddr
*addr
= p
;
3494 if (netif_running(ndev
))
3497 if (!is_valid_ether_addr(addr
->sa_data
))
3498 return -EADDRNOTAVAIL
;
3499 memcpy(ndev
->dev_addr
, addr
->sa_data
, ndev
->addr_len
);
3501 spin_lock(&qdev
->hw_lock
);
3502 if (ql_set_mac_addr_reg(qdev
, (u8
*) ndev
->dev_addr
,
3503 MAC_ADDR_TYPE_CAM_MAC
, qdev
->func
)) {/* Unicast */
3504 QPRINTK(qdev
, HW
, ERR
, "Failed to load MAC address.\n");
3507 spin_unlock(&qdev
->hw_lock
);
3512 static void qlge_tx_timeout(struct net_device
*ndev
)
3514 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3515 ql_queue_asic_error(qdev
);
3518 static void ql_asic_reset_work(struct work_struct
*work
)
3520 struct ql_adapter
*qdev
=
3521 container_of(work
, struct ql_adapter
, asic_reset_work
.work
);
3522 ql_cycle_adapter(qdev
);
3525 static void ql_get_board_info(struct ql_adapter
*qdev
)
3528 (ql_read32(qdev
, STS
) & STS_FUNC_ID_MASK
) >> STS_FUNC_ID_SHIFT
;
3530 qdev
->xg_sem_mask
= SEM_XGMAC1_MASK
;
3531 qdev
->port_link_up
= STS_PL1
;
3532 qdev
->port_init
= STS_PI1
;
3533 qdev
->mailbox_in
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC2_MBI
;
3534 qdev
->mailbox_out
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC2_MBO
;
3536 qdev
->xg_sem_mask
= SEM_XGMAC0_MASK
;
3537 qdev
->port_link_up
= STS_PL0
;
3538 qdev
->port_init
= STS_PI0
;
3539 qdev
->mailbox_in
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC0_MBI
;
3540 qdev
->mailbox_out
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC0_MBO
;
3542 qdev
->chip_rev_id
= ql_read32(qdev
, REV_ID
);
3545 static void ql_release_all(struct pci_dev
*pdev
)
3547 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3548 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3550 if (qdev
->workqueue
) {
3551 destroy_workqueue(qdev
->workqueue
);
3552 qdev
->workqueue
= NULL
;
3554 if (qdev
->q_workqueue
) {
3555 destroy_workqueue(qdev
->q_workqueue
);
3556 qdev
->q_workqueue
= NULL
;
3559 iounmap(qdev
->reg_base
);
3560 if (qdev
->doorbell_area
)
3561 iounmap(qdev
->doorbell_area
);
3562 pci_release_regions(pdev
);
3563 pci_set_drvdata(pdev
, NULL
);
3566 static int __devinit
ql_init_device(struct pci_dev
*pdev
,
3567 struct net_device
*ndev
, int cards_found
)
3569 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3573 memset((void *)qdev
, 0, sizeof(qdev
));
3574 err
= pci_enable_device(pdev
);
3576 dev_err(&pdev
->dev
, "PCI device enable failed.\n");
3580 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3582 dev_err(&pdev
->dev
, PFX
"Cannot find PCI Express capability, "
3586 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
3587 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
3588 val16
|= (PCI_EXP_DEVCTL_CERE
|
3589 PCI_EXP_DEVCTL_NFERE
|
3590 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
3591 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
3594 err
= pci_request_regions(pdev
, DRV_NAME
);
3596 dev_err(&pdev
->dev
, "PCI region request failed.\n");
3600 pci_set_master(pdev
);
3601 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3602 set_bit(QL_DMA64
, &qdev
->flags
);
3603 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3605 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3607 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3611 dev_err(&pdev
->dev
, "No usable DMA configuration.\n");
3615 pci_set_drvdata(pdev
, ndev
);
3617 ioremap_nocache(pci_resource_start(pdev
, 1),
3618 pci_resource_len(pdev
, 1));
3619 if (!qdev
->reg_base
) {
3620 dev_err(&pdev
->dev
, "Register mapping failed.\n");
3625 qdev
->doorbell_area_size
= pci_resource_len(pdev
, 3);
3626 qdev
->doorbell_area
=
3627 ioremap_nocache(pci_resource_start(pdev
, 3),
3628 pci_resource_len(pdev
, 3));
3629 if (!qdev
->doorbell_area
) {
3630 dev_err(&pdev
->dev
, "Doorbell register mapping failed.\n");
3635 ql_get_board_info(qdev
);
3638 qdev
->msg_enable
= netif_msg_init(debug
, default_msg
);
3639 spin_lock_init(&qdev
->hw_lock
);
3640 spin_lock_init(&qdev
->stats_lock
);
3642 /* make sure the EEPROM is good */
3643 err
= ql_get_flash_params(qdev
);
3645 dev_err(&pdev
->dev
, "Invalid FLASH.\n");
3649 if (!is_valid_ether_addr(qdev
->flash
.mac_addr
))
3652 memcpy(ndev
->dev_addr
, qdev
->flash
.mac_addr
, ndev
->addr_len
);
3653 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3655 /* Set up the default ring sizes. */
3656 qdev
->tx_ring_size
= NUM_TX_RING_ENTRIES
;
3657 qdev
->rx_ring_size
= NUM_RX_RING_ENTRIES
;
3659 /* Set up the coalescing parameters. */
3660 qdev
->rx_coalesce_usecs
= DFLT_COALESCE_WAIT
;
3661 qdev
->tx_coalesce_usecs
= DFLT_COALESCE_WAIT
;
3662 qdev
->rx_max_coalesced_frames
= DFLT_INTER_FRAME_WAIT
;
3663 qdev
->tx_max_coalesced_frames
= DFLT_INTER_FRAME_WAIT
;
3666 * Set up the operating parameters.
3670 qdev
->q_workqueue
= create_workqueue(ndev
->name
);
3671 qdev
->workqueue
= create_singlethread_workqueue(ndev
->name
);
3672 INIT_DELAYED_WORK(&qdev
->asic_reset_work
, ql_asic_reset_work
);
3673 INIT_DELAYED_WORK(&qdev
->mpi_reset_work
, ql_mpi_reset_work
);
3674 INIT_DELAYED_WORK(&qdev
->mpi_work
, ql_mpi_work
);
3677 dev_info(&pdev
->dev
, "%s\n", DRV_STRING
);
3678 dev_info(&pdev
->dev
, "Driver name: %s, Version: %s.\n",
3679 DRV_NAME
, DRV_VERSION
);
3683 ql_release_all(pdev
);
3684 pci_disable_device(pdev
);
3689 static const struct net_device_ops qlge_netdev_ops
= {
3690 .ndo_open
= qlge_open
,
3691 .ndo_stop
= qlge_close
,
3692 .ndo_start_xmit
= qlge_send
,
3693 .ndo_change_mtu
= qlge_change_mtu
,
3694 .ndo_get_stats
= qlge_get_stats
,
3695 .ndo_set_multicast_list
= qlge_set_multicast_list
,
3696 .ndo_set_mac_address
= qlge_set_mac_address
,
3697 .ndo_validate_addr
= eth_validate_addr
,
3698 .ndo_tx_timeout
= qlge_tx_timeout
,
3699 .ndo_vlan_rx_register
= ql_vlan_rx_register
,
3700 .ndo_vlan_rx_add_vid
= ql_vlan_rx_add_vid
,
3701 .ndo_vlan_rx_kill_vid
= ql_vlan_rx_kill_vid
,
3704 static int __devinit
qlge_probe(struct pci_dev
*pdev
,
3705 const struct pci_device_id
*pci_entry
)
3707 struct net_device
*ndev
= NULL
;
3708 struct ql_adapter
*qdev
= NULL
;
3709 static int cards_found
= 0;
3712 ndev
= alloc_etherdev(sizeof(struct ql_adapter
));
3716 err
= ql_init_device(pdev
, ndev
, cards_found
);
3722 qdev
= netdev_priv(ndev
);
3723 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
3730 | NETIF_F_HW_VLAN_TX
3731 | NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_FILTER
);
3733 if (test_bit(QL_DMA64
, &qdev
->flags
))
3734 ndev
->features
|= NETIF_F_HIGHDMA
;
3737 * Set up net_device structure.
3739 ndev
->tx_queue_len
= qdev
->tx_ring_size
;
3740 ndev
->irq
= pdev
->irq
;
3742 ndev
->netdev_ops
= &qlge_netdev_ops
;
3743 SET_ETHTOOL_OPS(ndev
, &qlge_ethtool_ops
);
3744 ndev
->watchdog_timeo
= 10 * HZ
;
3746 err
= register_netdev(ndev
);
3748 dev_err(&pdev
->dev
, "net device registration failed.\n");
3749 ql_release_all(pdev
);
3750 pci_disable_device(pdev
);
3753 netif_carrier_off(ndev
);
3754 netif_stop_queue(ndev
);
3755 ql_display_dev_info(ndev
);
3760 static void __devexit
qlge_remove(struct pci_dev
*pdev
)
3762 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3763 unregister_netdev(ndev
);
3764 ql_release_all(pdev
);
3765 pci_disable_device(pdev
);
3770 * This callback is called by the PCI subsystem whenever
3771 * a PCI bus error is detected.
3773 static pci_ers_result_t
qlge_io_error_detected(struct pci_dev
*pdev
,
3774 enum pci_channel_state state
)
3776 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3777 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3779 if (netif_running(ndev
))
3780 ql_adapter_down(qdev
);
3782 pci_disable_device(pdev
);
3784 /* Request a slot reset. */
3785 return PCI_ERS_RESULT_NEED_RESET
;
3789 * This callback is called after the PCI buss has been reset.
3790 * Basically, this tries to restart the card from scratch.
3791 * This is a shortened version of the device probe/discovery code,
3792 * it resembles the first-half of the () routine.
3794 static pci_ers_result_t
qlge_io_slot_reset(struct pci_dev
*pdev
)
3796 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3797 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3799 if (pci_enable_device(pdev
)) {
3800 QPRINTK(qdev
, IFUP
, ERR
,
3801 "Cannot re-enable PCI device after reset.\n");
3802 return PCI_ERS_RESULT_DISCONNECT
;
3805 pci_set_master(pdev
);
3807 netif_carrier_off(ndev
);
3808 netif_stop_queue(ndev
);
3809 ql_adapter_reset(qdev
);
3811 /* Make sure the EEPROM is good */
3812 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3814 if (!is_valid_ether_addr(ndev
->perm_addr
)) {
3815 QPRINTK(qdev
, IFUP
, ERR
, "After reset, invalid MAC address.\n");
3816 return PCI_ERS_RESULT_DISCONNECT
;
3819 return PCI_ERS_RESULT_RECOVERED
;
3822 static void qlge_io_resume(struct pci_dev
*pdev
)
3824 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3825 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3827 pci_set_master(pdev
);
3829 if (netif_running(ndev
)) {
3830 if (ql_adapter_up(qdev
)) {
3831 QPRINTK(qdev
, IFUP
, ERR
,
3832 "Device initialization failed after reset.\n");
3837 netif_device_attach(ndev
);
3840 static struct pci_error_handlers qlge_err_handler
= {
3841 .error_detected
= qlge_io_error_detected
,
3842 .slot_reset
= qlge_io_slot_reset
,
3843 .resume
= qlge_io_resume
,
3846 static int qlge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3848 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3849 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3852 netif_device_detach(ndev
);
3854 if (netif_running(ndev
)) {
3855 err
= ql_adapter_down(qdev
);
3860 for (i
= qdev
->rss_ring_first_cq_id
; i
< qdev
->rx_ring_count
; i
++)
3861 netif_napi_del(&qdev
->rx_ring
[i
].napi
);
3863 err
= pci_save_state(pdev
);
3867 pci_disable_device(pdev
);
3869 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3875 static int qlge_resume(struct pci_dev
*pdev
)
3877 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3878 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3881 pci_set_power_state(pdev
, PCI_D0
);
3882 pci_restore_state(pdev
);
3883 err
= pci_enable_device(pdev
);
3885 QPRINTK(qdev
, IFUP
, ERR
, "Cannot enable PCI device from suspend\n");
3888 pci_set_master(pdev
);
3890 pci_enable_wake(pdev
, PCI_D3hot
, 0);
3891 pci_enable_wake(pdev
, PCI_D3cold
, 0);
3893 if (netif_running(ndev
)) {
3894 err
= ql_adapter_up(qdev
);
3899 netif_device_attach(ndev
);
3903 #endif /* CONFIG_PM */
3905 static void qlge_shutdown(struct pci_dev
*pdev
)
3907 qlge_suspend(pdev
, PMSG_SUSPEND
);
3910 static struct pci_driver qlge_driver
= {
3912 .id_table
= qlge_pci_tbl
,
3913 .probe
= qlge_probe
,
3914 .remove
= __devexit_p(qlge_remove
),
3916 .suspend
= qlge_suspend
,
3917 .resume
= qlge_resume
,
3919 .shutdown
= qlge_shutdown
,
3920 .err_handler
= &qlge_err_handler
3923 static int __init
qlge_init_module(void)
3925 return pci_register_driver(&qlge_driver
);
3928 static void __exit
qlge_exit(void)
3930 pci_unregister_driver(&qlge_driver
);
3933 module_init(qlge_init_module
);
3934 module_exit(qlge_exit
);