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6a6329e641233383a35aff009c7d61ace132c9eb
[deliverable/linux.git] / drivers / net / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
49
50 #include <asm/processor.h>
51
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.16"
54 #define DRV_RELDATE "10Nov2007"
55
56 /* PHY CHIP Address */
57 #define PHY1_ADDR 1 /* For MAC1 */
58 #define PHY2_ADDR 2 /* For MAC2 */
59 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (6000 * HZ / 1000)
64 #define TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
65
66 /* RDC MAC I/O Size */
67 #define R6040_IO_SIZE 256
68
69 /* MAX RDC MAC */
70 #define MAX_MAC 2
71
72 /* MAC registers */
73 #define MCR0 0x00 /* Control register 0 */
74 #define MCR1 0x04 /* Control register 1 */
75 #define MAC_RST 0x0001 /* Reset the MAC */
76 #define MBCR 0x08 /* Bus control */
77 #define MT_ICR 0x0C /* TX interrupt control */
78 #define MR_ICR 0x10 /* RX interrupt control */
79 #define MTPR 0x14 /* TX poll command register */
80 #define MR_BSR 0x18 /* RX buffer size */
81 #define MR_DCR 0x1A /* RX descriptor control */
82 #define MLSR 0x1C /* Last status */
83 #define MMDIO 0x20 /* MDIO control register */
84 #define MDIO_WRITE 0x4000 /* MDIO write */
85 #define MDIO_READ 0x2000 /* MDIO read */
86 #define MMRD 0x24 /* MDIO read data register */
87 #define MMWD 0x28 /* MDIO write data register */
88 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
89 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
90 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
91 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
92 #define MISR 0x3C /* Status register */
93 #define MIER 0x40 /* INT enable register */
94 #define MSK_INT 0x0000 /* Mask off interrupts */
95 #define ME_CISR 0x44 /* Event counter INT status */
96 #define ME_CIER 0x48 /* Event counter INT enable */
97 #define MR_CNT 0x50 /* Successfully received packet counter */
98 #define ME_CNT0 0x52 /* Event counter 0 */
99 #define ME_CNT1 0x54 /* Event counter 1 */
100 #define ME_CNT2 0x56 /* Event counter 2 */
101 #define ME_CNT3 0x58 /* Event counter 3 */
102 #define MT_CNT 0x5A /* Successfully transmit packet counter */
103 #define ME_CNT4 0x5C /* Event counter 4 */
104 #define MP_CNT 0x5E /* Pause frame counter register */
105 #define MAR0 0x60 /* Hash table 0 */
106 #define MAR1 0x62 /* Hash table 1 */
107 #define MAR2 0x64 /* Hash table 2 */
108 #define MAR3 0x66 /* Hash table 3 */
109 #define MID_0L 0x68 /* Multicast address MID0 Low */
110 #define MID_0M 0x6A /* Multicast address MID0 Medium */
111 #define MID_0H 0x6C /* Multicast address MID0 High */
112 #define MID_1L 0x70 /* MID1 Low */
113 #define MID_1M 0x72 /* MID1 Medium */
114 #define MID_1H 0x74 /* MID1 High */
115 #define MID_2L 0x78 /* MID2 Low */
116 #define MID_2M 0x7A /* MID2 Medium */
117 #define MID_2H 0x7C /* MID2 High */
118 #define MID_3L 0x80 /* MID3 Low */
119 #define MID_3M 0x82 /* MID3 Medium */
120 #define MID_3H 0x84 /* MID3 High */
121 #define PHY_CC 0x88 /* PHY status change configuration register */
122 #define PHY_ST 0x8A /* PHY status register */
123 #define MAC_SM 0xAC /* MAC status machine */
124 #define MAC_ID 0xBE /* Identifier register */
125
126 #define TX_DCNT 0x80 /* TX descriptor count */
127 #define RX_DCNT 0x80 /* RX descriptor count */
128 #define MAX_BUF_SIZE 0x600
129 #define ALLOC_DESC_SIZE ((TX_DCNT+RX_DCNT) * \
130 sizeof(struct r6040_descriptor) + 0x10)
131 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
132 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
133
134 /* PHY settings */
135 #define ICPLUS_PHY_ID 0x0243
136
137 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
138 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
139 "Florian Fainelli <florian@openwrt.org>");
140 MODULE_LICENSE("GPL");
141 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
142
143 #define RX_INT 0x0001
144 #define TX_INT 0x0010
145 #define RX_NO_DESC_INT 0x0002
146 #define INT_MASK (RX_INT | TX_INT)
147
148 struct r6040_descriptor {
149 u16 status, len; /* 0-3 */
150 __le32 buf; /* 4-7 */
151 __le32 ndesc; /* 8-B */
152 u32 rev1; /* C-F */
153 char *vbufp; /* 10-13 */
154 struct r6040_descriptor *vndescp; /* 14-17 */
155 struct sk_buff *skb_ptr; /* 18-1B */
156 u32 rev2; /* 1C-1F */
157 } __attribute__((aligned(32)));
158
159 struct r6040_private {
160 spinlock_t lock; /* driver lock */
161 struct timer_list timer;
162 struct pci_dev *pdev;
163 struct r6040_descriptor *rx_insert_ptr;
164 struct r6040_descriptor *rx_remove_ptr;
165 struct r6040_descriptor *tx_insert_ptr;
166 struct r6040_descriptor *tx_remove_ptr;
167 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
168 u16 mcr0, mcr1;
169 dma_addr_t desc_dma;
170 char *desc_pool;
171 u16 switch_sig;
172 struct net_device *dev;
173 struct mii_if_info mii_if;
174 struct napi_struct napi;
175 struct net_device_stats stats;
176 u16 napi_rx_running;
177 void __iomem *base;
178 };
179
180 static char version[] __devinitdata = KERN_INFO DRV_NAME
181 ": RDC R6040 NAPI net driver,"
182 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
183
184 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
185
186 /* Read a word data from PHY Chip */
187 static int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
188 {
189 int limit = 2048;
190 u16 cmd;
191
192 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
193 /* Wait for the read bit to be cleared */
194 while (limit--) {
195 cmd = ioread16(ioaddr + MMDIO);
196 if (cmd & MDIO_READ)
197 break;
198 }
199
200 return ioread16(ioaddr + MMRD);
201 }
202
203 /* Write a word data from PHY Chip */
204 static void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
205 {
206 int limit = 2048;
207 u16 cmd;
208
209 iowrite16(val, ioaddr + MMWD);
210 /* Write the command to the MDIO bus */
211 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
212 /* Wait for the write bit to be cleared */
213 while (limit--) {
214 cmd = ioread16(ioaddr + MMDIO);
215 if (cmd & MDIO_WRITE)
216 break;
217 }
218 }
219
220 static int mdio_read(struct net_device *dev, int mii_id, int reg)
221 {
222 struct r6040_private *lp = netdev_priv(dev);
223 void __iomem *ioaddr = lp->base;
224
225 return (phy_read(ioaddr, lp->phy_addr, reg));
226 }
227
228 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
229 {
230 struct r6040_private *lp = netdev_priv(dev);
231 void __iomem *ioaddr = lp->base;
232
233 phy_write(ioaddr, lp->phy_addr, reg, val);
234 }
235
236 static void
237 r6040_tx_timeout(struct net_device *dev)
238 {
239 struct r6040_private *priv = netdev_priv(dev);
240
241 disable_irq(dev->irq);
242 napi_disable(&priv->napi);
243 spin_lock(&priv->lock);
244 dev->stats.tx_errors++;
245 spin_unlock(&priv->lock);
246
247 netif_stop_queue(dev);
248 }
249
250 /* Allocate skb buffer for rx descriptor */
251 static void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
252 {
253 struct r6040_descriptor *descptr;
254 void __iomem *ioaddr = lp->base;
255
256 descptr = lp->rx_insert_ptr;
257 while (lp->rx_free_desc < RX_DCNT) {
258 descptr->skb_ptr = dev_alloc_skb(MAX_BUF_SIZE);
259
260 if (!descptr->skb_ptr)
261 break;
262 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
263 descptr->skb_ptr->data,
264 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
265 descptr->status = 0x8000;
266 descptr = descptr->vndescp;
267 lp->rx_free_desc++;
268 /* Trigger RX DMA */
269 iowrite16(lp->mcr0 | 0x0002, ioaddr);
270 }
271 lp->rx_insert_ptr = descptr;
272 }
273
274
275 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
276 {
277 struct r6040_private *priv = netdev_priv(dev);
278 void __iomem *ioaddr = priv->base;
279 unsigned long flags;
280
281 spin_lock_irqsave(&priv->lock, flags);
282 priv->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
283 priv->stats.multicast += ioread8(ioaddr + ME_CNT0);
284 spin_unlock_irqrestore(&priv->lock, flags);
285
286 return &priv->stats;
287 }
288
289 /* Stop RDC MAC and Free the allocated resource */
290 static void r6040_down(struct net_device *dev)
291 {
292 struct r6040_private *lp = netdev_priv(dev);
293 void __iomem *ioaddr = lp->base;
294 int i;
295 int limit = 2048;
296 u16 *adrp;
297 u16 cmd;
298
299 /* Stop MAC */
300 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
301 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
302 while (limit--) {
303 cmd = ioread16(ioaddr + MCR1);
304 if (cmd & 0x1)
305 break;
306 }
307
308 /* Restore MAC Address to MIDx */
309 adrp = (u16 *) dev->dev_addr;
310 iowrite16(adrp[0], ioaddr + MID_0L);
311 iowrite16(adrp[1], ioaddr + MID_0M);
312 iowrite16(adrp[2], ioaddr + MID_0H);
313 free_irq(dev->irq, dev);
314 /* Free RX buffer */
315 for (i = 0; i < RX_DCNT; i++) {
316 if (lp->rx_insert_ptr->skb_ptr) {
317 pci_unmap_single(lp->pdev, lp->rx_insert_ptr->buf,
318 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
319 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
320 lp->rx_insert_ptr->skb_ptr = NULL;
321 }
322 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
323 }
324
325 /* Free TX buffer */
326 for (i = 0; i < TX_DCNT; i++) {
327 if (lp->tx_insert_ptr->skb_ptr) {
328 pci_unmap_single(lp->pdev, lp->tx_insert_ptr->buf,
329 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
330 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
331 lp->rx_insert_ptr->skb_ptr = NULL;
332 }
333 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
334 }
335
336 /* Free Descriptor memory */
337 pci_free_consistent(lp->pdev, ALLOC_DESC_SIZE,
338 lp->desc_pool, lp->desc_dma);
339 }
340
341 static int
342 r6040_close(struct net_device *dev)
343 {
344 struct r6040_private *lp = netdev_priv(dev);
345
346 /* deleted timer */
347 del_timer_sync(&lp->timer);
348
349 spin_lock_irq(&lp->lock);
350 netif_stop_queue(dev);
351 r6040_down(dev);
352 spin_unlock_irq(&lp->lock);
353
354 return 0;
355 }
356
357 /* Status of PHY CHIP */
358 static int phy_mode_chk(struct net_device *dev)
359 {
360 struct r6040_private *lp = netdev_priv(dev);
361 void __iomem *ioaddr = lp->base;
362 int phy_dat;
363
364 /* PHY Link Status Check */
365 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
366 if (!(phy_dat & 0x4))
367 phy_dat = 0x8000; /* Link Failed, full duplex */
368
369 /* PHY Chip Auto-Negotiation Status */
370 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
371 if (phy_dat & 0x0020) {
372 /* Auto Negotiation Mode */
373 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
374 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
375 if (phy_dat & 0x140)
376 /* Force full duplex */
377 phy_dat = 0x8000;
378 else
379 phy_dat = 0;
380 } else {
381 /* Force Mode */
382 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
383 if (phy_dat & 0x100)
384 phy_dat = 0x8000;
385 else
386 phy_dat = 0x0000;
387 }
388
389 return phy_dat;
390 };
391
392 static void r6040_set_carrier(struct mii_if_info *mii)
393 {
394 if (phy_mode_chk(mii->dev)) {
395 /* autoneg is off: Link is always assumed to be up */
396 if (!netif_carrier_ok(mii->dev))
397 netif_carrier_on(mii->dev);
398 } else
399 phy_mode_chk(mii->dev);
400 }
401
402 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
403 {
404 struct r6040_private *lp = netdev_priv(dev);
405 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &rq->ifr_data;
406 int rc;
407
408 if (!netif_running(dev))
409 return -EINVAL;
410 spin_lock_irq(&lp->lock);
411 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
412 spin_unlock_irq(&lp->lock);
413 r6040_set_carrier(&lp->mii_if);
414 return rc;
415 }
416
417 static int r6040_rx(struct net_device *dev, int limit)
418 {
419 struct r6040_private *priv = netdev_priv(dev);
420 int count;
421 void __iomem *ioaddr = priv->base;
422 u16 err;
423
424 for (count = 0; count < limit; ++count) {
425 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
426 struct sk_buff *skb_ptr;
427
428 /* Disable RX interrupt */
429 iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
430 descptr = priv->rx_remove_ptr;
431
432 /* Check for errors */
433 err = ioread16(ioaddr + MLSR);
434 if (err & 0x0400) priv->stats.rx_errors++;
435 /* RX FIFO over-run */
436 if (err & 0x8000) priv->stats.rx_fifo_errors++;
437 /* RX descriptor unavailable */
438 if (err & 0x0080) priv->stats.rx_frame_errors++;
439 /* Received packet with length over buffer lenght */
440 if (err & 0x0020) priv->stats.rx_over_errors++;
441 /* Received packet with too long or short */
442 if (err & (0x0010|0x0008)) priv->stats.rx_length_errors++;
443 /* Received packet with CRC errors */
444 if (err & 0x0004) {
445 spin_lock(&priv->lock);
446 priv->stats.rx_crc_errors++;
447 spin_unlock(&priv->lock);
448 }
449
450 while (priv->rx_free_desc) {
451 /* No RX packet */
452 if (descptr->status & 0x8000)
453 break;
454 skb_ptr = descptr->skb_ptr;
455 if (!skb_ptr) {
456 printk(KERN_ERR "%s: Inconsistent RX"
457 "descriptor chain\n",
458 dev->name);
459 break;
460 }
461 descptr->skb_ptr = NULL;
462 skb_ptr->dev = priv->dev;
463 /* Do not count the CRC */
464 skb_put(skb_ptr, descptr->len - 4);
465 pci_unmap_single(priv->pdev, descptr->buf,
466 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
467 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
468 /* Send to upper layer */
469 netif_receive_skb(skb_ptr);
470 dev->last_rx = jiffies;
471 priv->dev->stats.rx_packets++;
472 priv->dev->stats.rx_bytes += descptr->len;
473 /* To next descriptor */
474 descptr = descptr->vndescp;
475 priv->rx_free_desc--;
476 }
477 priv->rx_remove_ptr = descptr;
478 }
479 /* Allocate new RX buffer */
480 if (priv->rx_free_desc < RX_DCNT)
481 rx_buf_alloc(priv, priv->dev);
482
483 return count;
484 }
485
486 static void r6040_tx(struct net_device *dev)
487 {
488 struct r6040_private *priv = netdev_priv(dev);
489 struct r6040_descriptor *descptr;
490 void __iomem *ioaddr = priv->base;
491 struct sk_buff *skb_ptr;
492 u16 err;
493
494 spin_lock(&priv->lock);
495 descptr = priv->tx_remove_ptr;
496 while (priv->tx_free_desc < TX_DCNT) {
497 /* Check for errors */
498 err = ioread16(ioaddr + MLSR);
499
500 if (err & 0x0200) priv->stats.rx_fifo_errors++;
501 if (err & (0x2000 | 0x4000)) priv->stats.tx_carrier_errors++;
502
503 if (descptr->status & 0x8000)
504 break; /* Not complte */
505 skb_ptr = descptr->skb_ptr;
506 pci_unmap_single(priv->pdev, descptr->buf,
507 skb_ptr->len, PCI_DMA_TODEVICE);
508 /* Free buffer */
509 dev_kfree_skb_irq(skb_ptr);
510 descptr->skb_ptr = NULL;
511 /* To next descriptor */
512 descptr = descptr->vndescp;
513 priv->tx_free_desc++;
514 }
515 priv->tx_remove_ptr = descptr;
516
517 if (priv->tx_free_desc)
518 netif_wake_queue(dev);
519 spin_unlock(&priv->lock);
520 }
521
522 static int r6040_poll(struct napi_struct *napi, int budget)
523 {
524 struct r6040_private *priv =
525 container_of(napi, struct r6040_private, napi);
526 struct net_device *dev = priv->dev;
527 void __iomem *ioaddr = priv->base;
528 int work_done;
529
530 work_done = r6040_rx(dev, budget);
531
532 if (work_done < budget) {
533 netif_rx_complete(dev, napi);
534 /* Enable RX interrupt */
535 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
536 }
537 return work_done;
538 }
539
540 /* The RDC interrupt handler. */
541 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
542 {
543 struct net_device *dev = dev_id;
544 struct r6040_private *lp = netdev_priv(dev);
545 void __iomem *ioaddr = lp->base;
546 u16 status;
547 int handled = 1;
548
549 /* Mask off RDC MAC interrupt */
550 iowrite16(MSK_INT, ioaddr + MIER);
551 /* Read MISR status and clear */
552 status = ioread16(ioaddr + MISR);
553
554 if (status == 0x0000 || status == 0xffff)
555 return IRQ_NONE;
556
557 /* RX interrupt request */
558 if (status & 0x01) {
559 netif_rx_schedule(dev, &lp->napi);
560 iowrite16(TX_INT, ioaddr + MIER);
561 }
562
563 /* TX interrupt request */
564 if (status & 0x10)
565 r6040_tx(dev);
566
567 return IRQ_RETVAL(handled);
568 }
569
570 #ifdef CONFIG_NET_POLL_CONTROLLER
571 static void r6040_poll_controller(struct net_device *dev)
572 {
573 disable_irq(dev->irq);
574 r6040_interrupt(dev->irq, (void *)dev);
575 enable_irq(dev->irq);
576 }
577 #endif
578
579
580 /* Init RDC MAC */
581 static void r6040_up(struct net_device *dev)
582 {
583 struct r6040_private *lp = netdev_priv(dev);
584 struct r6040_descriptor *descptr;
585 void __iomem *ioaddr = lp->base;
586 int i;
587 __le32 tmp_addr;
588 dma_addr_t desc_dma, start_dma;
589
590 /* Initialize */
591 lp->tx_free_desc = TX_DCNT;
592 lp->rx_free_desc = 0;
593 /* Init descriptor */
594 memset(lp->desc_pool, 0, ALLOC_DESC_SIZE); /* Let all descriptor = 0 */
595 lp->tx_insert_ptr = (struct r6040_descriptor *)lp->desc_pool;
596 lp->tx_remove_ptr = lp->tx_insert_ptr;
597 lp->rx_insert_ptr = (struct r6040_descriptor *)lp->tx_insert_ptr +
598 TX_DCNT;
599 lp->rx_remove_ptr = lp->rx_insert_ptr;
600 /* Init TX descriptor */
601 descptr = lp->tx_insert_ptr;
602 desc_dma = lp->desc_dma;
603 start_dma = desc_dma;
604 for (i = 0; i < TX_DCNT; i++) {
605 descptr->ndesc = cpu_to_le32(desc_dma +
606 sizeof(struct r6040_descriptor));
607 descptr->vndescp = (descptr + 1);
608 descptr = (descptr + 1);
609 desc_dma += sizeof(struct r6040_descriptor);
610 }
611 (descptr - 1)->ndesc = cpu_to_le32(start_dma);
612 (descptr - 1)->vndescp = lp->tx_insert_ptr;
613
614 /* Init RX descriptor */
615 start_dma = desc_dma;
616 descptr = lp->rx_insert_ptr;
617 for (i = 0; i < RX_DCNT; i++) {
618 descptr->ndesc = cpu_to_le32(desc_dma +
619 sizeof(struct r6040_descriptor));
620 descptr->vndescp = (descptr + 1);
621 descptr = (descptr + 1);
622 desc_dma += sizeof(struct r6040_descriptor);
623 }
624 (descptr - 1)->ndesc = cpu_to_le32(start_dma);
625 (descptr - 1)->vndescp = lp->rx_insert_ptr;
626
627 /* Allocate buffer for RX descriptor */
628 rx_buf_alloc(lp, dev);
629
630 /* TX and RX descriptor start Register */
631 tmp_addr = cpu_to_le32((u32)lp->tx_insert_ptr);
632 tmp_addr = virt_to_bus((volatile void *)tmp_addr);
633 /* Lower 16-bits to MTD_SA0 */
634 iowrite16(tmp_addr, ioaddr + MTD_SA0);
635 /* Higher 16-bits to MTD_SA1 */
636 iowrite16((u16)(tmp_addr >> 16), ioaddr + MTD_SA1);
637 tmp_addr = cpu_to_le32((u32)lp->rx_insert_ptr);
638 tmp_addr = virt_to_bus((volatile void *)tmp_addr);
639 iowrite16(tmp_addr, ioaddr + MRD_SA0);
640 iowrite16((u16)(tmp_addr >> 16), ioaddr + MRD_SA1);
641
642 /* Buffer Size Register */
643 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
644 /* Read the PHY ID */
645 lp->switch_sig = phy_read(ioaddr, 0, 2);
646
647 if (lp->switch_sig == ICPLUS_PHY_ID) {
648 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
649 lp->phy_mode = 0x8000;
650 } else {
651 /* PHY Mode Check */
652 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
653 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
654
655 if (PHY_MODE == 0x3100)
656 lp->phy_mode = phy_mode_chk(dev);
657 else
658 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
659 }
660 /* MAC Bus Control Register */
661 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
662
663 /* MAC TX/RX Enable */
664 lp->mcr0 |= lp->phy_mode;
665 iowrite16(lp->mcr0, ioaddr);
666
667 /* set interrupt waiting time and packet numbers */
668 iowrite16(0x0F06, ioaddr + MT_ICR);
669 iowrite16(0x0F06, ioaddr + MR_ICR);
670
671 /* improve performance (by RDC guys) */
672 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
673 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
674 phy_write(ioaddr, 0, 19, 0x0000);
675 phy_write(ioaddr, 0, 30, 0x01F0);
676
677 /* Interrupt Mask Register */
678 iowrite16(INT_MASK, ioaddr + MIER);
679 }
680
681 /*
682 A periodic timer routine
683 Polling PHY Chip Link Status
684 */
685 static void r6040_timer(unsigned long data)
686 {
687 struct net_device *dev = (struct net_device *)data;
688 struct r6040_private *lp = netdev_priv(dev->priv);
689 void __iomem *ioaddr = lp->base;
690 u16 phy_mode;
691
692 /* Polling PHY Chip Status */
693 if (PHY_MODE == 0x3100)
694 phy_mode = phy_mode_chk(dev);
695 else
696 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
697
698 if (phy_mode != lp->phy_mode) {
699 lp->phy_mode = phy_mode;
700 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
701 iowrite16(lp->mcr0, ioaddr);
702 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
703 }
704
705 /* Timer active again */
706 lp->timer.expires = TIMER_WUT;
707 add_timer(&lp->timer);
708 }
709
710 /* Read/set MAC address routines */
711 static void r6040_mac_address(struct net_device *dev)
712 {
713 struct r6040_private *lp = netdev_priv(dev);
714 void __iomem *ioaddr = lp->base;
715 u16 *adrp;
716
717 /* MAC operation register */
718 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
719 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
720 iowrite16(0, ioaddr + MAC_SM);
721 udelay(5000);
722
723 /* Restore MAC Address */
724 adrp = (u16 *) dev->dev_addr;
725 iowrite16(adrp[0], ioaddr + MID_0L);
726 iowrite16(adrp[1], ioaddr + MID_0M);
727 iowrite16(adrp[2], ioaddr + MID_0H);
728 }
729
730 static int
731 r6040_open(struct net_device *dev)
732 {
733 struct r6040_private *lp = dev->priv;
734 int ret;
735
736 /* Request IRQ and Register interrupt handler */
737 ret = request_irq(dev->irq, &r6040_interrupt,
738 IRQF_SHARED, dev->name, dev);
739 if (ret)
740 return ret;
741
742 /* Set MAC address */
743 r6040_mac_address(dev);
744
745 /* Allocate Descriptor memory */
746 lp->desc_pool = pci_alloc_consistent(lp->pdev,
747 ALLOC_DESC_SIZE, &lp->desc_dma);
748 if (!lp->desc_pool)
749 return -ENOMEM;
750
751 r6040_up(dev);
752
753 napi_enable(&lp->napi);
754 netif_start_queue(dev);
755
756 if (lp->switch_sig != ICPLUS_PHY_ID) {
757 /* set and active a timer process */
758 init_timer(&lp->timer);
759 lp->timer.expires = TIMER_WUT;
760 lp->timer.data = (unsigned long)dev;
761 lp->timer.function = &r6040_timer;
762 add_timer(&lp->timer);
763 }
764 return 0;
765 }
766
767 static int
768 r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
769 {
770 struct r6040_private *lp = netdev_priv(dev);
771 struct r6040_descriptor *descptr;
772 void __iomem *ioaddr = lp->base;
773 unsigned long flags;
774 int ret = NETDEV_TX_OK;
775
776 /* Critical Section */
777 spin_lock_irqsave(&lp->lock, flags);
778
779 /* TX resource check */
780 if (!lp->tx_free_desc) {
781 spin_unlock_irqrestore(&lp->lock, flags);
782 netif_stop_queue(dev);
783 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
784 ret = NETDEV_TX_BUSY;
785 return ret;
786 }
787
788 /* Statistic Counter */
789 dev->stats.tx_packets++;
790 dev->stats.tx_bytes += skb->len;
791 /* Set TX descriptor & Transmit it */
792 lp->tx_free_desc--;
793 descptr = lp->tx_insert_ptr;
794 if (skb->len < MISR)
795 descptr->len = MISR;
796 else
797 descptr->len = skb->len;
798
799 descptr->skb_ptr = skb;
800 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
801 skb->data, skb->len, PCI_DMA_TODEVICE));
802 descptr->status = 0x8000;
803 /* Trigger the MAC to check the TX descriptor */
804 iowrite16(0x01, ioaddr + MTPR);
805 lp->tx_insert_ptr = descptr->vndescp;
806
807 /* If no tx resource, stop */
808 if (!lp->tx_free_desc)
809 netif_stop_queue(dev);
810
811 dev->trans_start = jiffies;
812 spin_unlock_irqrestore(&lp->lock, flags);
813 return ret;
814 }
815
816 static void
817 r6040_multicast_list(struct net_device *dev)
818 {
819 struct r6040_private *lp = netdev_priv(dev);
820 void __iomem *ioaddr = lp->base;
821 u16 *adrp;
822 u16 reg;
823 unsigned long flags;
824 struct dev_mc_list *dmi = dev->mc_list;
825 int i;
826
827 /* MAC Address */
828 adrp = (u16 *)dev->dev_addr;
829 iowrite16(adrp[0], ioaddr + MID_0L);
830 iowrite16(adrp[1], ioaddr + MID_0M);
831 iowrite16(adrp[2], ioaddr + MID_0H);
832
833 /* Promiscous Mode */
834 spin_lock_irqsave(&lp->lock, flags);
835
836 /* Clear AMCP & PROM bits */
837 reg = ioread16(ioaddr) & ~0x0120;
838 if (dev->flags & IFF_PROMISC) {
839 reg |= 0x0020;
840 lp->mcr0 |= 0x0020;
841 }
842 /* Too many multicast addresses
843 * accept all traffic */
844 else if ((dev->mc_count > MCAST_MAX)
845 || (dev->flags & IFF_ALLMULTI))
846 reg |= 0x0020;
847
848 iowrite16(reg, ioaddr);
849 spin_unlock_irqrestore(&lp->lock, flags);
850
851 /* Build the hash table */
852 if (dev->mc_count > MCAST_MAX) {
853 u16 hash_table[4];
854 u32 crc;
855
856 for (i = 0; i < 4; i++)
857 hash_table[i] = 0;
858
859 for (i = 0; i < dev->mc_count; i++) {
860 char *addrs = dmi->dmi_addr;
861
862 dmi = dmi->next;
863
864 if (!(*addrs & 1))
865 continue;
866
867 crc = ether_crc_le(6, addrs);
868 crc >>= 26;
869 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
870 }
871 /* Write the index of the hash table */
872 for (i = 0; i < 4; i++)
873 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
874 /* Fill the MAC hash tables with their values */
875 iowrite16(hash_table[0], ioaddr + MAR0);
876 iowrite16(hash_table[1], ioaddr + MAR1);
877 iowrite16(hash_table[2], ioaddr + MAR2);
878 iowrite16(hash_table[3], ioaddr + MAR3);
879 }
880 /* Multicast Address 1~4 case */
881 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
882 adrp = (u16 *)dmi->dmi_addr;
883 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
884 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
885 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
886 dmi = dmi->next;
887 }
888 for (i = dev->mc_count; i < MCAST_MAX; i++) {
889 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
890 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
891 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
892 }
893 }
894
895 static void netdev_get_drvinfo(struct net_device *dev,
896 struct ethtool_drvinfo *info)
897 {
898 struct r6040_private *rp = netdev_priv(dev);
899
900 strcpy(info->driver, DRV_NAME);
901 strcpy(info->version, DRV_VERSION);
902 strcpy(info->bus_info, pci_name(rp->pdev));
903 }
904
905 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
906 {
907 struct r6040_private *rp = netdev_priv(dev);
908 int rc;
909
910 spin_lock_irq(&rp->lock);
911 rc = mii_ethtool_gset(&rp->mii_if, cmd);
912 spin_unlock_irq(&rp->lock);
913
914 return rc;
915 }
916
917 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
918 {
919 struct r6040_private *rp = netdev_priv(dev);
920 int rc;
921
922 spin_lock_irq(&rp->lock);
923 rc = mii_ethtool_sset(&rp->mii_if, cmd);
924 spin_unlock_irq(&rp->lock);
925 r6040_set_carrier(&rp->mii_if);
926
927 return rc;
928 }
929
930 static u32 netdev_get_link(struct net_device *dev)
931 {
932 struct r6040_private *rp = netdev_priv(dev);
933
934 return mii_link_ok(&rp->mii_if);
935 }
936
937 static struct ethtool_ops netdev_ethtool_ops = {
938 .get_drvinfo = netdev_get_drvinfo,
939 .get_settings = netdev_get_settings,
940 .set_settings = netdev_set_settings,
941 .get_link = netdev_get_link,
942 };
943
944
945 static int __devinit r6040_init_one(struct pci_dev *pdev,
946 const struct pci_device_id *ent)
947 {
948 struct net_device *dev;
949 struct r6040_private *lp;
950 void __iomem *ioaddr;
951 int err, io_size = R6040_IO_SIZE;
952 static int card_idx = -1;
953 int bar = 0;
954 long pioaddr;
955 u16 *adrp;
956
957 printk(KERN_INFO "%s\n", version);
958
959 err = pci_enable_device(pdev);
960 if (err)
961 return err;
962
963 /* this should always be supported */
964 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
965 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
966 "not supported by the card\n");
967 return -ENODEV;
968 }
969 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
970 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
971 "not supported by the card\n");
972 return -ENODEV;
973 }
974
975 /* IO Size check */
976 if (pci_resource_len(pdev, 0) < io_size) {
977 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
978 return -EIO;
979 }
980
981 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
982 pci_set_master(pdev);
983
984 dev = alloc_etherdev(sizeof(struct r6040_private));
985 if (!dev) {
986 printk(KERN_ERR "Failed to allocate etherdev\n");
987 return -ENOMEM;
988 }
989 SET_NETDEV_DEV(dev, &pdev->dev);
990 lp = netdev_priv(dev);
991 lp->pdev = pdev;
992
993 if (pci_request_regions(pdev, DRV_NAME)) {
994 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
995 err = -ENODEV;
996 goto err_out_disable;
997 }
998
999 ioaddr = pci_iomap(pdev, bar, io_size);
1000 if (!ioaddr) {
1001 printk(KERN_ERR "ioremap failed for device %s\n",
1002 pci_name(pdev));
1003 return -EIO;
1004 }
1005
1006 /* Init system & device */
1007 lp->base = ioaddr;
1008 dev->irq = pdev->irq;
1009
1010 spin_lock_init(&lp->lock);
1011 pci_set_drvdata(pdev, dev);
1012
1013 /* Set MAC address */
1014 card_idx++;
1015
1016 adrp = (u16 *)dev->dev_addr;
1017 adrp[0] = ioread16(ioaddr + MID_0L);
1018 adrp[1] = ioread16(ioaddr + MID_0M);
1019 adrp[2] = ioread16(ioaddr + MID_0H);
1020
1021 /* Link new device into r6040_root_dev */
1022 lp->pdev = pdev;
1023
1024 /* Init RDC private data */
1025 lp->mcr0 = 0x1002;
1026 lp->phy_addr = phy_table[card_idx];
1027 lp->switch_sig = 0;
1028
1029 /* The RDC-specific entries in the device structure. */
1030 dev->open = &r6040_open;
1031 dev->hard_start_xmit = &r6040_start_xmit;
1032 dev->stop = &r6040_close;
1033 dev->get_stats = r6040_get_stats;
1034 dev->set_multicast_list = &r6040_multicast_list;
1035 dev->do_ioctl = &r6040_ioctl;
1036 dev->ethtool_ops = &netdev_ethtool_ops;
1037 dev->tx_timeout = &r6040_tx_timeout;
1038 dev->watchdog_timeo = TX_TIMEOUT;
1039 #ifdef CONFIG_NET_POLL_CONTROLLER
1040 dev->poll_controller = r6040_poll_controller;
1041 #endif
1042 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1043 lp->mii_if.dev = dev;
1044 lp->mii_if.mdio_read = mdio_read;
1045 lp->mii_if.mdio_write = mdio_write;
1046 lp->mii_if.phy_id = lp->phy_addr;
1047 lp->mii_if.phy_id_mask = 0x1f;
1048 lp->mii_if.reg_num_mask = 0x1f;
1049
1050 /* Register net device. After this dev->name assign */
1051 err = register_netdev(dev);
1052 if (err) {
1053 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1054 goto err_out_res;
1055 }
1056 return 0;
1057
1058 err_out_res:
1059 pci_release_regions(pdev);
1060 err_out_disable:
1061 pci_disable_device(pdev);
1062 pci_set_drvdata(pdev, NULL);
1063 free_netdev(dev);
1064
1065 return err;
1066 }
1067
1068 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1069 {
1070 struct net_device *dev = pci_get_drvdata(pdev);
1071
1072 unregister_netdev(dev);
1073 pci_release_regions(pdev);
1074 free_netdev(dev);
1075 pci_disable_device(pdev);
1076 pci_set_drvdata(pdev, NULL);
1077 }
1078
1079
1080 static struct pci_device_id r6040_pci_tbl[] = {
1081 { PCI_DEVICE(PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6040) },
1082 {0 }
1083 };
1084 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1085
1086 static struct pci_driver r6040_driver = {
1087 .name = "r6040",
1088 .id_table = r6040_pci_tbl,
1089 .probe = r6040_init_one,
1090 .remove = __devexit_p(r6040_remove_one),
1091 };
1092
1093
1094 static int __init r6040_init(void)
1095 {
1096 return pci_register_driver(&r6040_driver);
1097 }
1098
1099
1100 static void __exit r6040_cleanup(void)
1101 {
1102 pci_unregister_driver(&r6040_driver);
1103 }
1104
1105 module_init(r6040_init);
1106 module_exit(r6040_cleanup);
Linux kernel - Deliverables
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