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Merge branch 'drm-for-2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/airlie...
[deliverable/linux.git] / drivers / net / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/mii.h>
40 #include <linux/ethtool.h>
41 #include <linux/crc32.h>
42 #include <linux/spinlock.h>
43 #include <linux/bitops.h>
44 #include <linux/io.h>
45 #include <linux/irq.h>
46 #include <linux/uaccess.h>
47
48 #include <asm/processor.h>
49
50 #define DRV_NAME "r6040"
51 #define DRV_VERSION "0.25"
52 #define DRV_RELDATE "20Aug2009"
53
54 /* PHY CHIP Address */
55 #define PHY1_ADDR 1 /* For MAC1 */
56 #define PHY2_ADDR 3 /* For MAC2 */
57 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
58 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
59
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (6000 * HZ / 1000)
62
63 /* RDC MAC I/O Size */
64 #define R6040_IO_SIZE 256
65
66 /* MAX RDC MAC */
67 #define MAX_MAC 2
68
69 /* MAC registers */
70 #define MCR0 0x00 /* Control register 0 */
71 #define MCR1 0x04 /* Control register 1 */
72 #define MAC_RST 0x0001 /* Reset the MAC */
73 #define MBCR 0x08 /* Bus control */
74 #define MT_ICR 0x0C /* TX interrupt control */
75 #define MR_ICR 0x10 /* RX interrupt control */
76 #define MTPR 0x14 /* TX poll command register */
77 #define MR_BSR 0x18 /* RX buffer size */
78 #define MR_DCR 0x1A /* RX descriptor control */
79 #define MLSR 0x1C /* Last status */
80 #define MMDIO 0x20 /* MDIO control register */
81 #define MDIO_WRITE 0x4000 /* MDIO write */
82 #define MDIO_READ 0x2000 /* MDIO read */
83 #define MMRD 0x24 /* MDIO read data register */
84 #define MMWD 0x28 /* MDIO write data register */
85 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
86 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
87 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
88 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
89 #define MISR 0x3C /* Status register */
90 #define MIER 0x40 /* INT enable register */
91 #define MSK_INT 0x0000 /* Mask off interrupts */
92 #define RX_FINISH 0x0001 /* RX finished */
93 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
94 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
95 #define RX_EARLY 0x0008 /* RX early */
96 #define TX_FINISH 0x0010 /* TX finished */
97 #define TX_EARLY 0x0080 /* TX early */
98 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
99 #define LINK_CHANGED 0x0200 /* PHY link changed */
100 #define ME_CISR 0x44 /* Event counter INT status */
101 #define ME_CIER 0x48 /* Event counter INT enable */
102 #define MR_CNT 0x50 /* Successfully received packet counter */
103 #define ME_CNT0 0x52 /* Event counter 0 */
104 #define ME_CNT1 0x54 /* Event counter 1 */
105 #define ME_CNT2 0x56 /* Event counter 2 */
106 #define ME_CNT3 0x58 /* Event counter 3 */
107 #define MT_CNT 0x5A /* Successfully transmit packet counter */
108 #define ME_CNT4 0x5C /* Event counter 4 */
109 #define MP_CNT 0x5E /* Pause frame counter register */
110 #define MAR0 0x60 /* Hash table 0 */
111 #define MAR1 0x62 /* Hash table 1 */
112 #define MAR2 0x64 /* Hash table 2 */
113 #define MAR3 0x66 /* Hash table 3 */
114 #define MID_0L 0x68 /* Multicast address MID0 Low */
115 #define MID_0M 0x6A /* Multicast address MID0 Medium */
116 #define MID_0H 0x6C /* Multicast address MID0 High */
117 #define MID_1L 0x70 /* MID1 Low */
118 #define MID_1M 0x72 /* MID1 Medium */
119 #define MID_1H 0x74 /* MID1 High */
120 #define MID_2L 0x78 /* MID2 Low */
121 #define MID_2M 0x7A /* MID2 Medium */
122 #define MID_2H 0x7C /* MID2 High */
123 #define MID_3L 0x80 /* MID3 Low */
124 #define MID_3M 0x82 /* MID3 Medium */
125 #define MID_3H 0x84 /* MID3 High */
126 #define PHY_CC 0x88 /* PHY status change configuration register */
127 #define PHY_ST 0x8A /* PHY status register */
128 #define MAC_SM 0xAC /* MAC status machine */
129 #define MAC_ID 0xBE /* Identifier register */
130
131 #define TX_DCNT 0x80 /* TX descriptor count */
132 #define RX_DCNT 0x80 /* RX descriptor count */
133 #define MAX_BUF_SIZE 0x600
134 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
135 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
136 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
137 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
138
139 /* Descriptor status */
140 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
141 #define DSC_RX_OK 0x4000 /* RX was successful */
142 #define DSC_RX_ERR 0x0800 /* RX PHY error */
143 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
144 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
145 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
146 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
147 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
148 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
149 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
150 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
151 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
152 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
153
154 /* PHY settings */
155 #define ICPLUS_PHY_ID 0x0243
156
157 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
158 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
159 "Florian Fainelli <florian@openwrt.org>");
160 MODULE_LICENSE("GPL");
161 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
162 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
163
164 /* RX and TX interrupts that we handle */
165 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
166 #define TX_INTS (TX_FINISH)
167 #define INT_MASK (RX_INTS | TX_INTS)
168
169 struct r6040_descriptor {
170 u16 status, len; /* 0-3 */
171 __le32 buf; /* 4-7 */
172 __le32 ndesc; /* 8-B */
173 u32 rev1; /* C-F */
174 char *vbufp; /* 10-13 */
175 struct r6040_descriptor *vndescp; /* 14-17 */
176 struct sk_buff *skb_ptr; /* 18-1B */
177 u32 rev2; /* 1C-1F */
178 } __attribute__((aligned(32)));
179
180 struct r6040_private {
181 spinlock_t lock; /* driver lock */
182 struct timer_list timer;
183 struct pci_dev *pdev;
184 struct r6040_descriptor *rx_insert_ptr;
185 struct r6040_descriptor *rx_remove_ptr;
186 struct r6040_descriptor *tx_insert_ptr;
187 struct r6040_descriptor *tx_remove_ptr;
188 struct r6040_descriptor *rx_ring;
189 struct r6040_descriptor *tx_ring;
190 dma_addr_t rx_ring_dma;
191 dma_addr_t tx_ring_dma;
192 u16 tx_free_desc, phy_addr, phy_mode;
193 u16 mcr0, mcr1;
194 u16 switch_sig;
195 struct net_device *dev;
196 struct mii_if_info mii_if;
197 struct napi_struct napi;
198 void __iomem *base;
199 };
200
201 static char version[] __devinitdata = KERN_INFO DRV_NAME
202 ": RDC R6040 NAPI net driver,"
203 "version "DRV_VERSION " (" DRV_RELDATE ")";
204
205 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
206
207 /* Read a word data from PHY Chip */
208 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
209 {
210 int limit = 2048;
211 u16 cmd;
212
213 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
214 /* Wait for the read bit to be cleared */
215 while (limit--) {
216 cmd = ioread16(ioaddr + MMDIO);
217 if (!(cmd & MDIO_READ))
218 break;
219 }
220
221 return ioread16(ioaddr + MMRD);
222 }
223
224 /* Write a word data from PHY Chip */
225 static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
226 {
227 int limit = 2048;
228 u16 cmd;
229
230 iowrite16(val, ioaddr + MMWD);
231 /* Write the command to the MDIO bus */
232 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
233 /* Wait for the write bit to be cleared */
234 while (limit--) {
235 cmd = ioread16(ioaddr + MMDIO);
236 if (!(cmd & MDIO_WRITE))
237 break;
238 }
239 }
240
241 static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
242 {
243 struct r6040_private *lp = netdev_priv(dev);
244 void __iomem *ioaddr = lp->base;
245
246 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
247 }
248
249 static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
250 {
251 struct r6040_private *lp = netdev_priv(dev);
252 void __iomem *ioaddr = lp->base;
253
254 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
255 }
256
257 static void r6040_free_txbufs(struct net_device *dev)
258 {
259 struct r6040_private *lp = netdev_priv(dev);
260 int i;
261
262 for (i = 0; i < TX_DCNT; i++) {
263 if (lp->tx_insert_ptr->skb_ptr) {
264 pci_unmap_single(lp->pdev,
265 le32_to_cpu(lp->tx_insert_ptr->buf),
266 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
267 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
268 lp->tx_insert_ptr->skb_ptr = NULL;
269 }
270 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
271 }
272 }
273
274 static void r6040_free_rxbufs(struct net_device *dev)
275 {
276 struct r6040_private *lp = netdev_priv(dev);
277 int i;
278
279 for (i = 0; i < RX_DCNT; i++) {
280 if (lp->rx_insert_ptr->skb_ptr) {
281 pci_unmap_single(lp->pdev,
282 le32_to_cpu(lp->rx_insert_ptr->buf),
283 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
284 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
285 lp->rx_insert_ptr->skb_ptr = NULL;
286 }
287 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
288 }
289 }
290
291 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
292 dma_addr_t desc_dma, int size)
293 {
294 struct r6040_descriptor *desc = desc_ring;
295 dma_addr_t mapping = desc_dma;
296
297 while (size-- > 0) {
298 mapping += sizeof(*desc);
299 desc->ndesc = cpu_to_le32(mapping);
300 desc->vndescp = desc + 1;
301 desc++;
302 }
303 desc--;
304 desc->ndesc = cpu_to_le32(desc_dma);
305 desc->vndescp = desc_ring;
306 }
307
308 static void r6040_init_txbufs(struct net_device *dev)
309 {
310 struct r6040_private *lp = netdev_priv(dev);
311
312 lp->tx_free_desc = TX_DCNT;
313
314 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
315 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
316 }
317
318 static int r6040_alloc_rxbufs(struct net_device *dev)
319 {
320 struct r6040_private *lp = netdev_priv(dev);
321 struct r6040_descriptor *desc;
322 struct sk_buff *skb;
323 int rc;
324
325 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
326 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
327
328 /* Allocate skbs for the rx descriptors */
329 desc = lp->rx_ring;
330 do {
331 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
332 if (!skb) {
333 netdev_err(dev, "failed to alloc skb for rx\n");
334 rc = -ENOMEM;
335 goto err_exit;
336 }
337 desc->skb_ptr = skb;
338 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
339 desc->skb_ptr->data,
340 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
341 desc->status = DSC_OWNER_MAC;
342 desc = desc->vndescp;
343 } while (desc != lp->rx_ring);
344
345 return 0;
346
347 err_exit:
348 /* Deallocate all previously allocated skbs */
349 r6040_free_rxbufs(dev);
350 return rc;
351 }
352
353 static void r6040_init_mac_regs(struct net_device *dev)
354 {
355 struct r6040_private *lp = netdev_priv(dev);
356 void __iomem *ioaddr = lp->base;
357 int limit = 2048;
358 u16 cmd;
359
360 /* Mask Off Interrupt */
361 iowrite16(MSK_INT, ioaddr + MIER);
362
363 /* Reset RDC MAC */
364 iowrite16(MAC_RST, ioaddr + MCR1);
365 while (limit--) {
366 cmd = ioread16(ioaddr + MCR1);
367 if (cmd & 0x1)
368 break;
369 }
370 /* Reset internal state machine */
371 iowrite16(2, ioaddr + MAC_SM);
372 iowrite16(0, ioaddr + MAC_SM);
373 mdelay(5);
374
375 /* MAC Bus Control Register */
376 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
377
378 /* Buffer Size Register */
379 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
380
381 /* Write TX ring start address */
382 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
383 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
384
385 /* Write RX ring start address */
386 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
387 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
388
389 /* Set interrupt waiting time and packet numbers */
390 iowrite16(0, ioaddr + MT_ICR);
391 iowrite16(0, ioaddr + MR_ICR);
392
393 /* Enable interrupts */
394 iowrite16(INT_MASK, ioaddr + MIER);
395
396 /* Enable TX and RX */
397 iowrite16(lp->mcr0 | 0x0002, ioaddr);
398
399 /* Let TX poll the descriptors
400 * we may got called by r6040_tx_timeout which has left
401 * some unsent tx buffers */
402 iowrite16(0x01, ioaddr + MTPR);
403 }
404
405 static void r6040_tx_timeout(struct net_device *dev)
406 {
407 struct r6040_private *priv = netdev_priv(dev);
408 void __iomem *ioaddr = priv->base;
409
410 netdev_warn(dev, "transmit timed out, int enable %4.4x "
411 "status %4.4x, PHY status %4.4x\n",
412 ioread16(ioaddr + MIER),
413 ioread16(ioaddr + MISR),
414 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
415
416 dev->stats.tx_errors++;
417
418 /* Reset MAC and re-init all registers */
419 r6040_init_mac_regs(dev);
420 }
421
422 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
423 {
424 struct r6040_private *priv = netdev_priv(dev);
425 void __iomem *ioaddr = priv->base;
426 unsigned long flags;
427
428 spin_lock_irqsave(&priv->lock, flags);
429 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
430 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
431 spin_unlock_irqrestore(&priv->lock, flags);
432
433 return &dev->stats;
434 }
435
436 /* Stop RDC MAC and Free the allocated resource */
437 static void r6040_down(struct net_device *dev)
438 {
439 struct r6040_private *lp = netdev_priv(dev);
440 void __iomem *ioaddr = lp->base;
441 int limit = 2048;
442 u16 *adrp;
443 u16 cmd;
444
445 /* Stop MAC */
446 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
447 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
448 while (limit--) {
449 cmd = ioread16(ioaddr + MCR1);
450 if (cmd & 0x1)
451 break;
452 }
453
454 /* Restore MAC Address to MIDx */
455 adrp = (u16 *) dev->dev_addr;
456 iowrite16(adrp[0], ioaddr + MID_0L);
457 iowrite16(adrp[1], ioaddr + MID_0M);
458 iowrite16(adrp[2], ioaddr + MID_0H);
459 }
460
461 static int r6040_close(struct net_device *dev)
462 {
463 struct r6040_private *lp = netdev_priv(dev);
464 struct pci_dev *pdev = lp->pdev;
465
466 /* deleted timer */
467 del_timer_sync(&lp->timer);
468
469 spin_lock_irq(&lp->lock);
470 napi_disable(&lp->napi);
471 netif_stop_queue(dev);
472 r6040_down(dev);
473
474 free_irq(dev->irq, dev);
475
476 /* Free RX buffer */
477 r6040_free_rxbufs(dev);
478
479 /* Free TX buffer */
480 r6040_free_txbufs(dev);
481
482 spin_unlock_irq(&lp->lock);
483
484 /* Free Descriptor memory */
485 if (lp->rx_ring) {
486 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
487 lp->rx_ring = NULL;
488 }
489
490 if (lp->tx_ring) {
491 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
492 lp->tx_ring = NULL;
493 }
494
495 return 0;
496 }
497
498 /* Status of PHY CHIP */
499 static int r6040_phy_mode_chk(struct net_device *dev)
500 {
501 struct r6040_private *lp = netdev_priv(dev);
502 void __iomem *ioaddr = lp->base;
503 int phy_dat;
504
505 /* PHY Link Status Check */
506 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
507 if (!(phy_dat & 0x4))
508 phy_dat = 0x8000; /* Link Failed, full duplex */
509
510 /* PHY Chip Auto-Negotiation Status */
511 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
512 if (phy_dat & 0x0020) {
513 /* Auto Negotiation Mode */
514 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
515 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
516 if (phy_dat & 0x140)
517 /* Force full duplex */
518 phy_dat = 0x8000;
519 else
520 phy_dat = 0;
521 } else {
522 /* Force Mode */
523 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
524 if (phy_dat & 0x100)
525 phy_dat = 0x8000;
526 else
527 phy_dat = 0x0000;
528 }
529
530 return phy_dat;
531 };
532
533 static void r6040_set_carrier(struct mii_if_info *mii)
534 {
535 if (r6040_phy_mode_chk(mii->dev)) {
536 /* autoneg is off: Link is always assumed to be up */
537 if (!netif_carrier_ok(mii->dev))
538 netif_carrier_on(mii->dev);
539 } else
540 r6040_phy_mode_chk(mii->dev);
541 }
542
543 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
544 {
545 struct r6040_private *lp = netdev_priv(dev);
546 struct mii_ioctl_data *data = if_mii(rq);
547 int rc;
548
549 if (!netif_running(dev))
550 return -EINVAL;
551 spin_lock_irq(&lp->lock);
552 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
553 spin_unlock_irq(&lp->lock);
554 r6040_set_carrier(&lp->mii_if);
555 return rc;
556 }
557
558 static int r6040_rx(struct net_device *dev, int limit)
559 {
560 struct r6040_private *priv = netdev_priv(dev);
561 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
562 struct sk_buff *skb_ptr, *new_skb;
563 int count = 0;
564 u16 err;
565
566 /* Limit not reached and the descriptor belongs to the CPU */
567 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
568 /* Read the descriptor status */
569 err = descptr->status;
570 /* Global error status set */
571 if (err & DSC_RX_ERR) {
572 /* RX dribble */
573 if (err & DSC_RX_ERR_DRI)
574 dev->stats.rx_frame_errors++;
575 /* Buffer lenght exceeded */
576 if (err & DSC_RX_ERR_BUF)
577 dev->stats.rx_length_errors++;
578 /* Packet too long */
579 if (err & DSC_RX_ERR_LONG)
580 dev->stats.rx_length_errors++;
581 /* Packet < 64 bytes */
582 if (err & DSC_RX_ERR_RUNT)
583 dev->stats.rx_length_errors++;
584 /* CRC error */
585 if (err & DSC_RX_ERR_CRC) {
586 spin_lock(&priv->lock);
587 dev->stats.rx_crc_errors++;
588 spin_unlock(&priv->lock);
589 }
590 goto next_descr;
591 }
592
593 /* Packet successfully received */
594 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
595 if (!new_skb) {
596 dev->stats.rx_dropped++;
597 goto next_descr;
598 }
599 skb_ptr = descptr->skb_ptr;
600 skb_ptr->dev = priv->dev;
601
602 /* Do not count the CRC */
603 skb_put(skb_ptr, descptr->len - 4);
604 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
605 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
606 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
607
608 /* Send to upper layer */
609 netif_receive_skb(skb_ptr);
610 dev->stats.rx_packets++;
611 dev->stats.rx_bytes += descptr->len - 4;
612
613 /* put new skb into descriptor */
614 descptr->skb_ptr = new_skb;
615 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
616 descptr->skb_ptr->data,
617 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
618
619 next_descr:
620 /* put the descriptor back to the MAC */
621 descptr->status = DSC_OWNER_MAC;
622 descptr = descptr->vndescp;
623 count++;
624 }
625 priv->rx_remove_ptr = descptr;
626
627 return count;
628 }
629
630 static void r6040_tx(struct net_device *dev)
631 {
632 struct r6040_private *priv = netdev_priv(dev);
633 struct r6040_descriptor *descptr;
634 void __iomem *ioaddr = priv->base;
635 struct sk_buff *skb_ptr;
636 u16 err;
637
638 spin_lock(&priv->lock);
639 descptr = priv->tx_remove_ptr;
640 while (priv->tx_free_desc < TX_DCNT) {
641 /* Check for errors */
642 err = ioread16(ioaddr + MLSR);
643
644 if (err & 0x0200)
645 dev->stats.rx_fifo_errors++;
646 if (err & (0x2000 | 0x4000))
647 dev->stats.tx_carrier_errors++;
648
649 if (descptr->status & DSC_OWNER_MAC)
650 break; /* Not complete */
651 skb_ptr = descptr->skb_ptr;
652 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
653 skb_ptr->len, PCI_DMA_TODEVICE);
654 /* Free buffer */
655 dev_kfree_skb_irq(skb_ptr);
656 descptr->skb_ptr = NULL;
657 /* To next descriptor */
658 descptr = descptr->vndescp;
659 priv->tx_free_desc++;
660 }
661 priv->tx_remove_ptr = descptr;
662
663 if (priv->tx_free_desc)
664 netif_wake_queue(dev);
665 spin_unlock(&priv->lock);
666 }
667
668 static int r6040_poll(struct napi_struct *napi, int budget)
669 {
670 struct r6040_private *priv =
671 container_of(napi, struct r6040_private, napi);
672 struct net_device *dev = priv->dev;
673 void __iomem *ioaddr = priv->base;
674 int work_done;
675
676 work_done = r6040_rx(dev, budget);
677
678 if (work_done < budget) {
679 napi_complete(napi);
680 /* Enable RX interrupt */
681 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
682 }
683 return work_done;
684 }
685
686 /* The RDC interrupt handler. */
687 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
688 {
689 struct net_device *dev = dev_id;
690 struct r6040_private *lp = netdev_priv(dev);
691 void __iomem *ioaddr = lp->base;
692 u16 misr, status;
693
694 /* Save MIER */
695 misr = ioread16(ioaddr + MIER);
696 /* Mask off RDC MAC interrupt */
697 iowrite16(MSK_INT, ioaddr + MIER);
698 /* Read MISR status and clear */
699 status = ioread16(ioaddr + MISR);
700
701 if (status == 0x0000 || status == 0xffff) {
702 /* Restore RDC MAC interrupt */
703 iowrite16(misr, ioaddr + MIER);
704 return IRQ_NONE;
705 }
706
707 /* RX interrupt request */
708 if (status & RX_INTS) {
709 if (status & RX_NO_DESC) {
710 /* RX descriptor unavailable */
711 dev->stats.rx_dropped++;
712 dev->stats.rx_missed_errors++;
713 }
714 if (status & RX_FIFO_FULL)
715 dev->stats.rx_fifo_errors++;
716
717 /* Mask off RX interrupt */
718 misr &= ~RX_INTS;
719 napi_schedule(&lp->napi);
720 }
721
722 /* TX interrupt request */
723 if (status & TX_INTS)
724 r6040_tx(dev);
725
726 /* Restore RDC MAC interrupt */
727 iowrite16(misr, ioaddr + MIER);
728
729 return IRQ_HANDLED;
730 }
731
732 #ifdef CONFIG_NET_POLL_CONTROLLER
733 static void r6040_poll_controller(struct net_device *dev)
734 {
735 disable_irq(dev->irq);
736 r6040_interrupt(dev->irq, dev);
737 enable_irq(dev->irq);
738 }
739 #endif
740
741 /* Init RDC MAC */
742 static int r6040_up(struct net_device *dev)
743 {
744 struct r6040_private *lp = netdev_priv(dev);
745 void __iomem *ioaddr = lp->base;
746 int ret;
747
748 /* Initialise and alloc RX/TX buffers */
749 r6040_init_txbufs(dev);
750 ret = r6040_alloc_rxbufs(dev);
751 if (ret)
752 return ret;
753
754 /* Read the PHY ID */
755 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
756
757 if (lp->switch_sig == ICPLUS_PHY_ID) {
758 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
759 lp->phy_mode = 0x8000;
760 } else {
761 /* PHY Mode Check */
762 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
763 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
764
765 if (PHY_MODE == 0x3100)
766 lp->phy_mode = r6040_phy_mode_chk(dev);
767 else
768 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
769 }
770
771 /* Set duplex mode */
772 lp->mcr0 |= lp->phy_mode;
773
774 /* improve performance (by RDC guys) */
775 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
776 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
777 r6040_phy_write(ioaddr, 0, 19, 0x0000);
778 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
779
780 /* Initialize all MAC registers */
781 r6040_init_mac_regs(dev);
782
783 return 0;
784 }
785
786 /*
787 A periodic timer routine
788 Polling PHY Chip Link Status
789 */
790 static void r6040_timer(unsigned long data)
791 {
792 struct net_device *dev = (struct net_device *)data;
793 struct r6040_private *lp = netdev_priv(dev);
794 void __iomem *ioaddr = lp->base;
795 u16 phy_mode;
796
797 /* Polling PHY Chip Status */
798 if (PHY_MODE == 0x3100)
799 phy_mode = r6040_phy_mode_chk(dev);
800 else
801 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
802
803 if (phy_mode != lp->phy_mode) {
804 lp->phy_mode = phy_mode;
805 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
806 iowrite16(lp->mcr0, ioaddr);
807 }
808
809 /* Timer active again */
810 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
811
812 /* Check media */
813 mii_check_media(&lp->mii_if, 1, 1);
814 }
815
816 /* Read/set MAC address routines */
817 static void r6040_mac_address(struct net_device *dev)
818 {
819 struct r6040_private *lp = netdev_priv(dev);
820 void __iomem *ioaddr = lp->base;
821 u16 *adrp;
822
823 /* MAC operation register */
824 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
825 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
826 iowrite16(0, ioaddr + MAC_SM);
827 mdelay(5);
828
829 /* Restore MAC Address */
830 adrp = (u16 *) dev->dev_addr;
831 iowrite16(adrp[0], ioaddr + MID_0L);
832 iowrite16(adrp[1], ioaddr + MID_0M);
833 iowrite16(adrp[2], ioaddr + MID_0H);
834 }
835
836 static int r6040_open(struct net_device *dev)
837 {
838 struct r6040_private *lp = netdev_priv(dev);
839 int ret;
840
841 /* Request IRQ and Register interrupt handler */
842 ret = request_irq(dev->irq, r6040_interrupt,
843 IRQF_SHARED, dev->name, dev);
844 if (ret)
845 return ret;
846
847 /* Set MAC address */
848 r6040_mac_address(dev);
849
850 /* Allocate Descriptor memory */
851 lp->rx_ring =
852 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
853 if (!lp->rx_ring)
854 return -ENOMEM;
855
856 lp->tx_ring =
857 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
858 if (!lp->tx_ring) {
859 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
860 lp->rx_ring_dma);
861 return -ENOMEM;
862 }
863
864 ret = r6040_up(dev);
865 if (ret) {
866 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
867 lp->tx_ring_dma);
868 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
869 lp->rx_ring_dma);
870 return ret;
871 }
872
873 napi_enable(&lp->napi);
874 netif_start_queue(dev);
875
876 /* set and active a timer process */
877 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
878 if (lp->switch_sig != ICPLUS_PHY_ID)
879 mod_timer(&lp->timer, jiffies + HZ);
880 return 0;
881 }
882
883 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
884 struct net_device *dev)
885 {
886 struct r6040_private *lp = netdev_priv(dev);
887 struct r6040_descriptor *descptr;
888 void __iomem *ioaddr = lp->base;
889 unsigned long flags;
890
891 /* Critical Section */
892 spin_lock_irqsave(&lp->lock, flags);
893
894 /* TX resource check */
895 if (!lp->tx_free_desc) {
896 spin_unlock_irqrestore(&lp->lock, flags);
897 netif_stop_queue(dev);
898 netdev_err(dev, ": no tx descriptor\n");
899 return NETDEV_TX_BUSY;
900 }
901
902 /* Statistic Counter */
903 dev->stats.tx_packets++;
904 dev->stats.tx_bytes += skb->len;
905 /* Set TX descriptor & Transmit it */
906 lp->tx_free_desc--;
907 descptr = lp->tx_insert_ptr;
908 if (skb->len < MISR)
909 descptr->len = MISR;
910 else
911 descptr->len = skb->len;
912
913 descptr->skb_ptr = skb;
914 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
915 skb->data, skb->len, PCI_DMA_TODEVICE));
916 descptr->status = DSC_OWNER_MAC;
917 /* Trigger the MAC to check the TX descriptor */
918 iowrite16(0x01, ioaddr + MTPR);
919 lp->tx_insert_ptr = descptr->vndescp;
920
921 /* If no tx resource, stop */
922 if (!lp->tx_free_desc)
923 netif_stop_queue(dev);
924
925 spin_unlock_irqrestore(&lp->lock, flags);
926
927 return NETDEV_TX_OK;
928 }
929
930 static void r6040_multicast_list(struct net_device *dev)
931 {
932 struct r6040_private *lp = netdev_priv(dev);
933 void __iomem *ioaddr = lp->base;
934 u16 *adrp;
935 u16 reg;
936 unsigned long flags;
937 struct netdev_hw_addr *ha;
938 int i;
939
940 /* MAC Address */
941 adrp = (u16 *)dev->dev_addr;
942 iowrite16(adrp[0], ioaddr + MID_0L);
943 iowrite16(adrp[1], ioaddr + MID_0M);
944 iowrite16(adrp[2], ioaddr + MID_0H);
945
946 /* Promiscous Mode */
947 spin_lock_irqsave(&lp->lock, flags);
948
949 /* Clear AMCP & PROM bits */
950 reg = ioread16(ioaddr) & ~0x0120;
951 if (dev->flags & IFF_PROMISC) {
952 reg |= 0x0020;
953 lp->mcr0 |= 0x0020;
954 }
955 /* Too many multicast addresses
956 * accept all traffic */
957 else if ((netdev_mc_count(dev) > MCAST_MAX) ||
958 (dev->flags & IFF_ALLMULTI))
959 reg |= 0x0020;
960
961 iowrite16(reg, ioaddr);
962 spin_unlock_irqrestore(&lp->lock, flags);
963
964 /* Build the hash table */
965 if (netdev_mc_count(dev) > MCAST_MAX) {
966 u16 hash_table[4];
967 u32 crc;
968
969 for (i = 0; i < 4; i++)
970 hash_table[i] = 0;
971
972 netdev_for_each_mc_addr(ha, dev) {
973 char *addrs = ha->addr;
974
975 if (!(*addrs & 1))
976 continue;
977
978 crc = ether_crc_le(6, addrs);
979 crc >>= 26;
980 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
981 }
982 /* Fill the MAC hash tables with their values */
983 iowrite16(hash_table[0], ioaddr + MAR0);
984 iowrite16(hash_table[1], ioaddr + MAR1);
985 iowrite16(hash_table[2], ioaddr + MAR2);
986 iowrite16(hash_table[3], ioaddr + MAR3);
987 }
988 /* Multicast Address 1~4 case */
989 i = 0;
990 netdev_for_each_mc_addr(ha, dev) {
991 if (i < MCAST_MAX) {
992 adrp = (u16 *) ha->addr;
993 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
994 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
995 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
996 } else {
997 iowrite16(0xffff, ioaddr + MID_1L + 8 * i);
998 iowrite16(0xffff, ioaddr + MID_1M + 8 * i);
999 iowrite16(0xffff, ioaddr + MID_1H + 8 * i);
1000 }
1001 i++;
1002 }
1003 }
1004
1005 static void netdev_get_drvinfo(struct net_device *dev,
1006 struct ethtool_drvinfo *info)
1007 {
1008 struct r6040_private *rp = netdev_priv(dev);
1009
1010 strcpy(info->driver, DRV_NAME);
1011 strcpy(info->version, DRV_VERSION);
1012 strcpy(info->bus_info, pci_name(rp->pdev));
1013 }
1014
1015 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1016 {
1017 struct r6040_private *rp = netdev_priv(dev);
1018 int rc;
1019
1020 spin_lock_irq(&rp->lock);
1021 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1022 spin_unlock_irq(&rp->lock);
1023
1024 return rc;
1025 }
1026
1027 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1028 {
1029 struct r6040_private *rp = netdev_priv(dev);
1030 int rc;
1031
1032 spin_lock_irq(&rp->lock);
1033 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1034 spin_unlock_irq(&rp->lock);
1035 r6040_set_carrier(&rp->mii_if);
1036
1037 return rc;
1038 }
1039
1040 static u32 netdev_get_link(struct net_device *dev)
1041 {
1042 struct r6040_private *rp = netdev_priv(dev);
1043
1044 return mii_link_ok(&rp->mii_if);
1045 }
1046
1047 static const struct ethtool_ops netdev_ethtool_ops = {
1048 .get_drvinfo = netdev_get_drvinfo,
1049 .get_settings = netdev_get_settings,
1050 .set_settings = netdev_set_settings,
1051 .get_link = netdev_get_link,
1052 };
1053
1054 static const struct net_device_ops r6040_netdev_ops = {
1055 .ndo_open = r6040_open,
1056 .ndo_stop = r6040_close,
1057 .ndo_start_xmit = r6040_start_xmit,
1058 .ndo_get_stats = r6040_get_stats,
1059 .ndo_set_multicast_list = r6040_multicast_list,
1060 .ndo_change_mtu = eth_change_mtu,
1061 .ndo_validate_addr = eth_validate_addr,
1062 .ndo_set_mac_address = eth_mac_addr,
1063 .ndo_do_ioctl = r6040_ioctl,
1064 .ndo_tx_timeout = r6040_tx_timeout,
1065 #ifdef CONFIG_NET_POLL_CONTROLLER
1066 .ndo_poll_controller = r6040_poll_controller,
1067 #endif
1068 };
1069
1070 static int __devinit r6040_init_one(struct pci_dev *pdev,
1071 const struct pci_device_id *ent)
1072 {
1073 struct net_device *dev;
1074 struct r6040_private *lp;
1075 void __iomem *ioaddr;
1076 int err, io_size = R6040_IO_SIZE;
1077 static int card_idx = -1;
1078 int bar = 0;
1079 u16 *adrp;
1080
1081 printk("%s\n", version);
1082
1083 err = pci_enable_device(pdev);
1084 if (err)
1085 goto err_out;
1086
1087 /* this should always be supported */
1088 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1089 if (err) {
1090 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1091 "not supported by the card\n");
1092 goto err_out;
1093 }
1094 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1095 if (err) {
1096 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1097 "not supported by the card\n");
1098 goto err_out;
1099 }
1100
1101 /* IO Size check */
1102 if (pci_resource_len(pdev, bar) < io_size) {
1103 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1104 err = -EIO;
1105 goto err_out;
1106 }
1107
1108 pci_set_master(pdev);
1109
1110 dev = alloc_etherdev(sizeof(struct r6040_private));
1111 if (!dev) {
1112 dev_err(&pdev->dev, "Failed to allocate etherdev\n");
1113 err = -ENOMEM;
1114 goto err_out;
1115 }
1116 SET_NETDEV_DEV(dev, &pdev->dev);
1117 lp = netdev_priv(dev);
1118
1119 err = pci_request_regions(pdev, DRV_NAME);
1120
1121 if (err) {
1122 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1123 goto err_out_free_dev;
1124 }
1125
1126 ioaddr = pci_iomap(pdev, bar, io_size);
1127 if (!ioaddr) {
1128 dev_err(&pdev->dev, "ioremap failed for device\n");
1129 err = -EIO;
1130 goto err_out_free_res;
1131 }
1132 /* If PHY status change register is still set to zero it means the
1133 * bootloader didn't initialize it */
1134 if (ioread16(ioaddr + PHY_CC) == 0)
1135 iowrite16(0x9f07, ioaddr + PHY_CC);
1136
1137 /* Init system & device */
1138 lp->base = ioaddr;
1139 dev->irq = pdev->irq;
1140
1141 spin_lock_init(&lp->lock);
1142 pci_set_drvdata(pdev, dev);
1143
1144 /* Set MAC address */
1145 card_idx++;
1146
1147 adrp = (u16 *)dev->dev_addr;
1148 adrp[0] = ioread16(ioaddr + MID_0L);
1149 adrp[1] = ioread16(ioaddr + MID_0M);
1150 adrp[2] = ioread16(ioaddr + MID_0H);
1151
1152 /* Some bootloader/BIOSes do not initialize
1153 * MAC address, warn about that */
1154 if (!(adrp[0] || adrp[1] || adrp[2])) {
1155 netdev_warn(dev, "MAC address not initialized, generating random\n");
1156 random_ether_addr(dev->dev_addr);
1157 }
1158
1159 /* Link new device into r6040_root_dev */
1160 lp->pdev = pdev;
1161 lp->dev = dev;
1162
1163 /* Init RDC private data */
1164 lp->mcr0 = 0x1002;
1165 lp->phy_addr = phy_table[card_idx];
1166 lp->switch_sig = 0;
1167
1168 /* The RDC-specific entries in the device structure. */
1169 dev->netdev_ops = &r6040_netdev_ops;
1170 dev->ethtool_ops = &netdev_ethtool_ops;
1171 dev->watchdog_timeo = TX_TIMEOUT;
1172
1173 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1174 lp->mii_if.dev = dev;
1175 lp->mii_if.mdio_read = r6040_mdio_read;
1176 lp->mii_if.mdio_write = r6040_mdio_write;
1177 lp->mii_if.phy_id = lp->phy_addr;
1178 lp->mii_if.phy_id_mask = 0x1f;
1179 lp->mii_if.reg_num_mask = 0x1f;
1180
1181 /* Check the vendor ID on the PHY, if 0xffff assume none attached */
1182 if (r6040_phy_read(ioaddr, lp->phy_addr, 2) == 0xffff) {
1183 dev_err(&pdev->dev, "Failed to detect an attached PHY\n");
1184 err = -ENODEV;
1185 goto err_out_unmap;
1186 }
1187
1188 /* Register net device. After this dev->name assign */
1189 err = register_netdev(dev);
1190 if (err) {
1191 dev_err(&pdev->dev, "Failed to register net device\n");
1192 goto err_out_unmap;
1193 }
1194 return 0;
1195
1196 err_out_unmap:
1197 pci_iounmap(pdev, ioaddr);
1198 err_out_free_res:
1199 pci_release_regions(pdev);
1200 err_out_free_dev:
1201 free_netdev(dev);
1202 err_out:
1203 return err;
1204 }
1205
1206 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1207 {
1208 struct net_device *dev = pci_get_drvdata(pdev);
1209
1210 unregister_netdev(dev);
1211 pci_release_regions(pdev);
1212 free_netdev(dev);
1213 pci_disable_device(pdev);
1214 pci_set_drvdata(pdev, NULL);
1215 }
1216
1217
1218 static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1219 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1220 { 0 }
1221 };
1222 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1223
1224 static struct pci_driver r6040_driver = {
1225 .name = DRV_NAME,
1226 .id_table = r6040_pci_tbl,
1227 .probe = r6040_init_one,
1228 .remove = __devexit_p(r6040_remove_one),
1229 };
1230
1231
1232 static int __init r6040_init(void)
1233 {
1234 return pci_register_driver(&r6040_driver);
1235 }
1236
1237
1238 static void __exit r6040_cleanup(void)
1239 {
1240 pci_unregister_driver(&r6040_driver);
1241 }
1242
1243 module_init(r6040_init);
1244 module_exit(r6040_cleanup);
Linux kernel - Deliverables
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