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r6040: do not use a private stats structure to store statistics
[deliverable/linux.git] / drivers / net / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
49
50 #include <asm/processor.h>
51
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.16"
54 #define DRV_RELDATE "10Nov2007"
55
56 /* PHY CHIP Address */
57 #define PHY1_ADDR 1 /* For MAC1 */
58 #define PHY2_ADDR 2 /* For MAC2 */
59 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (6000 * HZ / 1000)
64 #define TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
65
66 /* RDC MAC I/O Size */
67 #define R6040_IO_SIZE 256
68
69 /* MAX RDC MAC */
70 #define MAX_MAC 2
71
72 /* MAC registers */
73 #define MCR0 0x00 /* Control register 0 */
74 #define MCR1 0x04 /* Control register 1 */
75 #define MAC_RST 0x0001 /* Reset the MAC */
76 #define MBCR 0x08 /* Bus control */
77 #define MT_ICR 0x0C /* TX interrupt control */
78 #define MR_ICR 0x10 /* RX interrupt control */
79 #define MTPR 0x14 /* TX poll command register */
80 #define MR_BSR 0x18 /* RX buffer size */
81 #define MR_DCR 0x1A /* RX descriptor control */
82 #define MLSR 0x1C /* Last status */
83 #define MMDIO 0x20 /* MDIO control register */
84 #define MDIO_WRITE 0x4000 /* MDIO write */
85 #define MDIO_READ 0x2000 /* MDIO read */
86 #define MMRD 0x24 /* MDIO read data register */
87 #define MMWD 0x28 /* MDIO write data register */
88 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
89 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
90 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
91 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
92 #define MISR 0x3C /* Status register */
93 #define MIER 0x40 /* INT enable register */
94 #define MSK_INT 0x0000 /* Mask off interrupts */
95 #define ME_CISR 0x44 /* Event counter INT status */
96 #define ME_CIER 0x48 /* Event counter INT enable */
97 #define MR_CNT 0x50 /* Successfully received packet counter */
98 #define ME_CNT0 0x52 /* Event counter 0 */
99 #define ME_CNT1 0x54 /* Event counter 1 */
100 #define ME_CNT2 0x56 /* Event counter 2 */
101 #define ME_CNT3 0x58 /* Event counter 3 */
102 #define MT_CNT 0x5A /* Successfully transmit packet counter */
103 #define ME_CNT4 0x5C /* Event counter 4 */
104 #define MP_CNT 0x5E /* Pause frame counter register */
105 #define MAR0 0x60 /* Hash table 0 */
106 #define MAR1 0x62 /* Hash table 1 */
107 #define MAR2 0x64 /* Hash table 2 */
108 #define MAR3 0x66 /* Hash table 3 */
109 #define MID_0L 0x68 /* Multicast address MID0 Low */
110 #define MID_0M 0x6A /* Multicast address MID0 Medium */
111 #define MID_0H 0x6C /* Multicast address MID0 High */
112 #define MID_1L 0x70 /* MID1 Low */
113 #define MID_1M 0x72 /* MID1 Medium */
114 #define MID_1H 0x74 /* MID1 High */
115 #define MID_2L 0x78 /* MID2 Low */
116 #define MID_2M 0x7A /* MID2 Medium */
117 #define MID_2H 0x7C /* MID2 High */
118 #define MID_3L 0x80 /* MID3 Low */
119 #define MID_3M 0x82 /* MID3 Medium */
120 #define MID_3H 0x84 /* MID3 High */
121 #define PHY_CC 0x88 /* PHY status change configuration register */
122 #define PHY_ST 0x8A /* PHY status register */
123 #define MAC_SM 0xAC /* MAC status machine */
124 #define MAC_ID 0xBE /* Identifier register */
125
126 #define TX_DCNT 0x80 /* TX descriptor count */
127 #define RX_DCNT 0x80 /* RX descriptor count */
128 #define MAX_BUF_SIZE 0x600
129 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
130 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
131 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
132 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
133
134 /* PHY settings */
135 #define ICPLUS_PHY_ID 0x0243
136
137 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
138 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
139 "Florian Fainelli <florian@openwrt.org>");
140 MODULE_LICENSE("GPL");
141 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
142
143 #define RX_INT 0x0001
144 #define TX_INT 0x0010
145 #define RX_NO_DESC_INT 0x0002
146 #define INT_MASK (RX_INT | TX_INT)
147
148 struct r6040_descriptor {
149 u16 status, len; /* 0-3 */
150 __le32 buf; /* 4-7 */
151 __le32 ndesc; /* 8-B */
152 u32 rev1; /* C-F */
153 char *vbufp; /* 10-13 */
154 struct r6040_descriptor *vndescp; /* 14-17 */
155 struct sk_buff *skb_ptr; /* 18-1B */
156 u32 rev2; /* 1C-1F */
157 } __attribute__((aligned(32)));
158
159 struct r6040_private {
160 spinlock_t lock; /* driver lock */
161 struct timer_list timer;
162 struct pci_dev *pdev;
163 struct r6040_descriptor *rx_insert_ptr;
164 struct r6040_descriptor *rx_remove_ptr;
165 struct r6040_descriptor *tx_insert_ptr;
166 struct r6040_descriptor *tx_remove_ptr;
167 struct r6040_descriptor *rx_ring;
168 struct r6040_descriptor *tx_ring;
169 dma_addr_t rx_ring_dma;
170 dma_addr_t tx_ring_dma;
171 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
172 u16 mcr0, mcr1;
173 u16 switch_sig;
174 struct net_device *dev;
175 struct mii_if_info mii_if;
176 struct napi_struct napi;
177 u16 napi_rx_running;
178 void __iomem *base;
179 };
180
181 static char version[] __devinitdata = KERN_INFO DRV_NAME
182 ": RDC R6040 NAPI net driver,"
183 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
184
185 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
186
187 /* Read a word data from PHY Chip */
188 static int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
189 {
190 int limit = 2048;
191 u16 cmd;
192
193 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
194 /* Wait for the read bit to be cleared */
195 while (limit--) {
196 cmd = ioread16(ioaddr + MMDIO);
197 if (cmd & MDIO_READ)
198 break;
199 }
200
201 return ioread16(ioaddr + MMRD);
202 }
203
204 /* Write a word data from PHY Chip */
205 static void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
206 {
207 int limit = 2048;
208 u16 cmd;
209
210 iowrite16(val, ioaddr + MMWD);
211 /* Write the command to the MDIO bus */
212 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
213 /* Wait for the write bit to be cleared */
214 while (limit--) {
215 cmd = ioread16(ioaddr + MMDIO);
216 if (cmd & MDIO_WRITE)
217 break;
218 }
219 }
220
221 static int mdio_read(struct net_device *dev, int mii_id, int reg)
222 {
223 struct r6040_private *lp = netdev_priv(dev);
224 void __iomem *ioaddr = lp->base;
225
226 return (phy_read(ioaddr, lp->phy_addr, reg));
227 }
228
229 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
230 {
231 struct r6040_private *lp = netdev_priv(dev);
232 void __iomem *ioaddr = lp->base;
233
234 phy_write(ioaddr, lp->phy_addr, reg, val);
235 }
236
237 static void r6040_tx_timeout(struct net_device *dev)
238 {
239 struct r6040_private *priv = netdev_priv(dev);
240
241 disable_irq(dev->irq);
242 napi_disable(&priv->napi);
243 spin_lock(&priv->lock);
244 dev->stats.tx_errors++;
245 spin_unlock(&priv->lock);
246
247 netif_stop_queue(dev);
248 }
249
250 /* Allocate skb buffer for rx descriptor */
251 static void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
252 {
253 struct r6040_descriptor *descptr;
254 void __iomem *ioaddr = lp->base;
255
256 descptr = lp->rx_insert_ptr;
257 while (lp->rx_free_desc < RX_DCNT) {
258 descptr->skb_ptr = dev_alloc_skb(MAX_BUF_SIZE);
259
260 if (!descptr->skb_ptr)
261 break;
262 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
263 descptr->skb_ptr->data,
264 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
265 descptr->status = 0x8000;
266 descptr = descptr->vndescp;
267 lp->rx_free_desc++;
268 /* Trigger RX DMA */
269 iowrite16(lp->mcr0 | 0x0002, ioaddr);
270 }
271 lp->rx_insert_ptr = descptr;
272 }
273
274
275 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
276 {
277 struct r6040_private *priv = netdev_priv(dev);
278 void __iomem *ioaddr = priv->base;
279 unsigned long flags;
280
281 spin_lock_irqsave(&priv->lock, flags);
282 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
283 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
284 spin_unlock_irqrestore(&priv->lock, flags);
285
286 return &dev->stats;
287 }
288
289 /* Stop RDC MAC and Free the allocated resource */
290 static void r6040_down(struct net_device *dev)
291 {
292 struct r6040_private *lp = netdev_priv(dev);
293 void __iomem *ioaddr = lp->base;
294 struct pci_dev *pdev = lp->pdev;
295 int i;
296 int limit = 2048;
297 u16 *adrp;
298 u16 cmd;
299
300 /* Stop MAC */
301 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
302 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
303 while (limit--) {
304 cmd = ioread16(ioaddr + MCR1);
305 if (cmd & 0x1)
306 break;
307 }
308
309 /* Restore MAC Address to MIDx */
310 adrp = (u16 *) dev->dev_addr;
311 iowrite16(adrp[0], ioaddr + MID_0L);
312 iowrite16(adrp[1], ioaddr + MID_0M);
313 iowrite16(adrp[2], ioaddr + MID_0H);
314 free_irq(dev->irq, dev);
315 /* Free RX buffer */
316 for (i = 0; i < RX_DCNT; i++) {
317 if (lp->rx_insert_ptr->skb_ptr) {
318 pci_unmap_single(lp->pdev, lp->rx_insert_ptr->buf,
319 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
320 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
321 lp->rx_insert_ptr->skb_ptr = NULL;
322 }
323 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
324 }
325
326 /* Free TX buffer */
327 for (i = 0; i < TX_DCNT; i++) {
328 if (lp->tx_insert_ptr->skb_ptr) {
329 pci_unmap_single(lp->pdev, lp->tx_insert_ptr->buf,
330 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
331 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
332 lp->rx_insert_ptr->skb_ptr = NULL;
333 }
334 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
335 }
336
337 /* Free Descriptor memory */
338 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
339 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
340 }
341
342 static int r6040_close(struct net_device *dev)
343 {
344 struct r6040_private *lp = netdev_priv(dev);
345
346 /* deleted timer */
347 del_timer_sync(&lp->timer);
348
349 spin_lock_irq(&lp->lock);
350 netif_stop_queue(dev);
351 r6040_down(dev);
352 spin_unlock_irq(&lp->lock);
353
354 return 0;
355 }
356
357 /* Status of PHY CHIP */
358 static int phy_mode_chk(struct net_device *dev)
359 {
360 struct r6040_private *lp = netdev_priv(dev);
361 void __iomem *ioaddr = lp->base;
362 int phy_dat;
363
364 /* PHY Link Status Check */
365 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
366 if (!(phy_dat & 0x4))
367 phy_dat = 0x8000; /* Link Failed, full duplex */
368
369 /* PHY Chip Auto-Negotiation Status */
370 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
371 if (phy_dat & 0x0020) {
372 /* Auto Negotiation Mode */
373 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
374 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
375 if (phy_dat & 0x140)
376 /* Force full duplex */
377 phy_dat = 0x8000;
378 else
379 phy_dat = 0;
380 } else {
381 /* Force Mode */
382 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
383 if (phy_dat & 0x100)
384 phy_dat = 0x8000;
385 else
386 phy_dat = 0x0000;
387 }
388
389 return phy_dat;
390 };
391
392 static void r6040_set_carrier(struct mii_if_info *mii)
393 {
394 if (phy_mode_chk(mii->dev)) {
395 /* autoneg is off: Link is always assumed to be up */
396 if (!netif_carrier_ok(mii->dev))
397 netif_carrier_on(mii->dev);
398 } else
399 phy_mode_chk(mii->dev);
400 }
401
402 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
403 {
404 struct r6040_private *lp = netdev_priv(dev);
405 struct mii_ioctl_data *data = if_mii(rq);
406 int rc;
407
408 if (!netif_running(dev))
409 return -EINVAL;
410 spin_lock_irq(&lp->lock);
411 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
412 spin_unlock_irq(&lp->lock);
413 r6040_set_carrier(&lp->mii_if);
414 return rc;
415 }
416
417 static int r6040_rx(struct net_device *dev, int limit)
418 {
419 struct r6040_private *priv = netdev_priv(dev);
420 int count;
421 void __iomem *ioaddr = priv->base;
422 u16 err;
423
424 for (count = 0; count < limit; ++count) {
425 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
426 struct sk_buff *skb_ptr;
427
428 /* Disable RX interrupt */
429 iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
430 descptr = priv->rx_remove_ptr;
431
432 /* Check for errors */
433 err = ioread16(ioaddr + MLSR);
434 if (err & 0x0400)
435 dev->stats.rx_errors++;
436 /* RX FIFO over-run */
437 if (err & 0x8000)
438 dev->stats.rx_fifo_errors++;
439 /* RX descriptor unavailable */
440 if (err & 0x0080)
441 dev->stats.rx_frame_errors++;
442 /* Received packet with length over buffer lenght */
443 if (err & 0x0020)
444 dev->stats.rx_over_errors++;
445 /* Received packet with too long or short */
446 if (err & (0x0010 | 0x0008))
447 dev->stats.rx_length_errors++;
448 /* Received packet with CRC errors */
449 if (err & 0x0004) {
450 spin_lock(&priv->lock);
451 dev->stats.rx_crc_errors++;
452 spin_unlock(&priv->lock);
453 }
454
455 while (priv->rx_free_desc) {
456 /* No RX packet */
457 if (descptr->status & 0x8000)
458 break;
459 skb_ptr = descptr->skb_ptr;
460 if (!skb_ptr) {
461 printk(KERN_ERR "%s: Inconsistent RX"
462 "descriptor chain\n",
463 dev->name);
464 break;
465 }
466 descptr->skb_ptr = NULL;
467 skb_ptr->dev = priv->dev;
468 /* Do not count the CRC */
469 skb_put(skb_ptr, descptr->len - 4);
470 pci_unmap_single(priv->pdev, descptr->buf,
471 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
472 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
473 /* Send to upper layer */
474 netif_receive_skb(skb_ptr);
475 dev->last_rx = jiffies;
476 dev->stats.rx_packets++;
477 dev->stats.rx_bytes += descptr->len;
478 /* To next descriptor */
479 descptr = descptr->vndescp;
480 priv->rx_free_desc--;
481 }
482 priv->rx_remove_ptr = descptr;
483 }
484 /* Allocate new RX buffer */
485 if (priv->rx_free_desc < RX_DCNT)
486 rx_buf_alloc(priv, priv->dev);
487
488 return count;
489 }
490
491 static void r6040_tx(struct net_device *dev)
492 {
493 struct r6040_private *priv = netdev_priv(dev);
494 struct r6040_descriptor *descptr;
495 void __iomem *ioaddr = priv->base;
496 struct sk_buff *skb_ptr;
497 u16 err;
498
499 spin_lock(&priv->lock);
500 descptr = priv->tx_remove_ptr;
501 while (priv->tx_free_desc < TX_DCNT) {
502 /* Check for errors */
503 err = ioread16(ioaddr + MLSR);
504
505 if (err & 0x0200)
506 dev->stats.rx_fifo_errors++;
507 if (err & (0x2000 | 0x4000))
508 dev->stats.tx_carrier_errors++;
509
510 if (descptr->status & 0x8000)
511 break; /* Not complte */
512 skb_ptr = descptr->skb_ptr;
513 pci_unmap_single(priv->pdev, descptr->buf,
514 skb_ptr->len, PCI_DMA_TODEVICE);
515 /* Free buffer */
516 dev_kfree_skb_irq(skb_ptr);
517 descptr->skb_ptr = NULL;
518 /* To next descriptor */
519 descptr = descptr->vndescp;
520 priv->tx_free_desc++;
521 }
522 priv->tx_remove_ptr = descptr;
523
524 if (priv->tx_free_desc)
525 netif_wake_queue(dev);
526 spin_unlock(&priv->lock);
527 }
528
529 static int r6040_poll(struct napi_struct *napi, int budget)
530 {
531 struct r6040_private *priv =
532 container_of(napi, struct r6040_private, napi);
533 struct net_device *dev = priv->dev;
534 void __iomem *ioaddr = priv->base;
535 int work_done;
536
537 work_done = r6040_rx(dev, budget);
538
539 if (work_done < budget) {
540 netif_rx_complete(dev, napi);
541 /* Enable RX interrupt */
542 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
543 }
544 return work_done;
545 }
546
547 /* The RDC interrupt handler. */
548 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
549 {
550 struct net_device *dev = dev_id;
551 struct r6040_private *lp = netdev_priv(dev);
552 void __iomem *ioaddr = lp->base;
553 u16 status;
554 int handled = 1;
555
556 /* Mask off RDC MAC interrupt */
557 iowrite16(MSK_INT, ioaddr + MIER);
558 /* Read MISR status and clear */
559 status = ioread16(ioaddr + MISR);
560
561 if (status == 0x0000 || status == 0xffff)
562 return IRQ_NONE;
563
564 /* RX interrupt request */
565 if (status & 0x01) {
566 netif_rx_schedule(dev, &lp->napi);
567 iowrite16(TX_INT, ioaddr + MIER);
568 }
569
570 /* TX interrupt request */
571 if (status & 0x10)
572 r6040_tx(dev);
573
574 return IRQ_RETVAL(handled);
575 }
576
577 #ifdef CONFIG_NET_POLL_CONTROLLER
578 static void r6040_poll_controller(struct net_device *dev)
579 {
580 disable_irq(dev->irq);
581 r6040_interrupt(dev->irq, dev);
582 enable_irq(dev->irq);
583 }
584 #endif
585
586 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
587 dma_addr_t desc_dma, int size)
588 {
589 struct r6040_descriptor *desc = desc_ring;
590 dma_addr_t mapping = desc_dma;
591
592 while (size-- > 0) {
593 mapping += sizeof(sizeof(*desc));
594 desc->ndesc = cpu_to_le32(mapping);
595 desc->vndescp = desc + 1;
596 desc++;
597 }
598 desc--;
599 desc->ndesc = cpu_to_le32(desc_dma);
600 desc->vndescp = desc_ring;
601 }
602
603 /* Init RDC MAC */
604 static void r6040_up(struct net_device *dev)
605 {
606 struct r6040_private *lp = netdev_priv(dev);
607 void __iomem *ioaddr = lp->base;
608
609 /* Initialize */
610 lp->tx_free_desc = TX_DCNT;
611 lp->rx_free_desc = 0;
612 /* Init descriptor */
613 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
614 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
615 /* Init TX descriptor */
616 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
617
618 /* Init RX descriptor */
619 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
620
621 /* Allocate buffer for RX descriptor */
622 rx_buf_alloc(lp, dev);
623
624 /*
625 * TX and RX descriptor start registers.
626 * Lower 16-bits to MxD_SA0. Higher 16-bits to MxD_SA1.
627 */
628 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
629 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
630
631 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
632 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
633
634 /* Buffer Size Register */
635 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
636 /* Read the PHY ID */
637 lp->switch_sig = phy_read(ioaddr, 0, 2);
638
639 if (lp->switch_sig == ICPLUS_PHY_ID) {
640 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
641 lp->phy_mode = 0x8000;
642 } else {
643 /* PHY Mode Check */
644 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
645 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
646
647 if (PHY_MODE == 0x3100)
648 lp->phy_mode = phy_mode_chk(dev);
649 else
650 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
651 }
652 /* MAC Bus Control Register */
653 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
654
655 /* MAC TX/RX Enable */
656 lp->mcr0 |= lp->phy_mode;
657 iowrite16(lp->mcr0, ioaddr);
658
659 /* set interrupt waiting time and packet numbers */
660 iowrite16(0x0F06, ioaddr + MT_ICR);
661 iowrite16(0x0F06, ioaddr + MR_ICR);
662
663 /* improve performance (by RDC guys) */
664 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
665 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
666 phy_write(ioaddr, 0, 19, 0x0000);
667 phy_write(ioaddr, 0, 30, 0x01F0);
668
669 /* Interrupt Mask Register */
670 iowrite16(INT_MASK, ioaddr + MIER);
671 }
672
673 /*
674 A periodic timer routine
675 Polling PHY Chip Link Status
676 */
677 static void r6040_timer(unsigned long data)
678 {
679 struct net_device *dev = (struct net_device *)data;
680 struct r6040_private *lp = netdev_priv(dev);
681 void __iomem *ioaddr = lp->base;
682 u16 phy_mode;
683
684 /* Polling PHY Chip Status */
685 if (PHY_MODE == 0x3100)
686 phy_mode = phy_mode_chk(dev);
687 else
688 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
689
690 if (phy_mode != lp->phy_mode) {
691 lp->phy_mode = phy_mode;
692 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
693 iowrite16(lp->mcr0, ioaddr);
694 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
695 }
696
697 /* Timer active again */
698 lp->timer.expires = TIMER_WUT;
699 add_timer(&lp->timer);
700 }
701
702 /* Read/set MAC address routines */
703 static void r6040_mac_address(struct net_device *dev)
704 {
705 struct r6040_private *lp = netdev_priv(dev);
706 void __iomem *ioaddr = lp->base;
707 u16 *adrp;
708
709 /* MAC operation register */
710 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
711 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
712 iowrite16(0, ioaddr + MAC_SM);
713 udelay(5000);
714
715 /* Restore MAC Address */
716 adrp = (u16 *) dev->dev_addr;
717 iowrite16(adrp[0], ioaddr + MID_0L);
718 iowrite16(adrp[1], ioaddr + MID_0M);
719 iowrite16(adrp[2], ioaddr + MID_0H);
720 }
721
722 static int r6040_open(struct net_device *dev)
723 {
724 struct r6040_private *lp = netdev_priv(dev);
725 int ret;
726
727 /* Request IRQ and Register interrupt handler */
728 ret = request_irq(dev->irq, &r6040_interrupt,
729 IRQF_SHARED, dev->name, dev);
730 if (ret)
731 return ret;
732
733 /* Set MAC address */
734 r6040_mac_address(dev);
735
736 /* Allocate Descriptor memory */
737 lp->rx_ring =
738 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
739 if (!lp->rx_ring)
740 return -ENOMEM;
741
742 lp->tx_ring =
743 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
744 if (!lp->tx_ring) {
745 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
746 lp->rx_ring_dma);
747 return -ENOMEM;
748 }
749
750 r6040_up(dev);
751
752 napi_enable(&lp->napi);
753 netif_start_queue(dev);
754
755 if (lp->switch_sig != ICPLUS_PHY_ID) {
756 /* set and active a timer process */
757 init_timer(&lp->timer);
758 lp->timer.expires = TIMER_WUT;
759 lp->timer.data = (unsigned long)dev;
760 lp->timer.function = &r6040_timer;
761 add_timer(&lp->timer);
762 }
763 return 0;
764 }
765
766 static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
767 {
768 struct r6040_private *lp = netdev_priv(dev);
769 struct r6040_descriptor *descptr;
770 void __iomem *ioaddr = lp->base;
771 unsigned long flags;
772 int ret = NETDEV_TX_OK;
773
774 /* Critical Section */
775 spin_lock_irqsave(&lp->lock, flags);
776
777 /* TX resource check */
778 if (!lp->tx_free_desc) {
779 spin_unlock_irqrestore(&lp->lock, flags);
780 netif_stop_queue(dev);
781 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
782 ret = NETDEV_TX_BUSY;
783 return ret;
784 }
785
786 /* Statistic Counter */
787 dev->stats.tx_packets++;
788 dev->stats.tx_bytes += skb->len;
789 /* Set TX descriptor & Transmit it */
790 lp->tx_free_desc--;
791 descptr = lp->tx_insert_ptr;
792 if (skb->len < MISR)
793 descptr->len = MISR;
794 else
795 descptr->len = skb->len;
796
797 descptr->skb_ptr = skb;
798 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
799 skb->data, skb->len, PCI_DMA_TODEVICE));
800 descptr->status = 0x8000;
801 /* Trigger the MAC to check the TX descriptor */
802 iowrite16(0x01, ioaddr + MTPR);
803 lp->tx_insert_ptr = descptr->vndescp;
804
805 /* If no tx resource, stop */
806 if (!lp->tx_free_desc)
807 netif_stop_queue(dev);
808
809 dev->trans_start = jiffies;
810 spin_unlock_irqrestore(&lp->lock, flags);
811 return ret;
812 }
813
814 static void r6040_multicast_list(struct net_device *dev)
815 {
816 struct r6040_private *lp = netdev_priv(dev);
817 void __iomem *ioaddr = lp->base;
818 u16 *adrp;
819 u16 reg;
820 unsigned long flags;
821 struct dev_mc_list *dmi = dev->mc_list;
822 int i;
823
824 /* MAC Address */
825 adrp = (u16 *)dev->dev_addr;
826 iowrite16(adrp[0], ioaddr + MID_0L);
827 iowrite16(adrp[1], ioaddr + MID_0M);
828 iowrite16(adrp[2], ioaddr + MID_0H);
829
830 /* Promiscous Mode */
831 spin_lock_irqsave(&lp->lock, flags);
832
833 /* Clear AMCP & PROM bits */
834 reg = ioread16(ioaddr) & ~0x0120;
835 if (dev->flags & IFF_PROMISC) {
836 reg |= 0x0020;
837 lp->mcr0 |= 0x0020;
838 }
839 /* Too many multicast addresses
840 * accept all traffic */
841 else if ((dev->mc_count > MCAST_MAX)
842 || (dev->flags & IFF_ALLMULTI))
843 reg |= 0x0020;
844
845 iowrite16(reg, ioaddr);
846 spin_unlock_irqrestore(&lp->lock, flags);
847
848 /* Build the hash table */
849 if (dev->mc_count > MCAST_MAX) {
850 u16 hash_table[4];
851 u32 crc;
852
853 for (i = 0; i < 4; i++)
854 hash_table[i] = 0;
855
856 for (i = 0; i < dev->mc_count; i++) {
857 char *addrs = dmi->dmi_addr;
858
859 dmi = dmi->next;
860
861 if (!(*addrs & 1))
862 continue;
863
864 crc = ether_crc_le(6, addrs);
865 crc >>= 26;
866 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
867 }
868 /* Write the index of the hash table */
869 for (i = 0; i < 4; i++)
870 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
871 /* Fill the MAC hash tables with their values */
872 iowrite16(hash_table[0], ioaddr + MAR0);
873 iowrite16(hash_table[1], ioaddr + MAR1);
874 iowrite16(hash_table[2], ioaddr + MAR2);
875 iowrite16(hash_table[3], ioaddr + MAR3);
876 }
877 /* Multicast Address 1~4 case */
878 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
879 adrp = (u16 *)dmi->dmi_addr;
880 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
881 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
882 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
883 dmi = dmi->next;
884 }
885 for (i = dev->mc_count; i < MCAST_MAX; i++) {
886 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
887 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
888 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
889 }
890 }
891
892 static void netdev_get_drvinfo(struct net_device *dev,
893 struct ethtool_drvinfo *info)
894 {
895 struct r6040_private *rp = netdev_priv(dev);
896
897 strcpy(info->driver, DRV_NAME);
898 strcpy(info->version, DRV_VERSION);
899 strcpy(info->bus_info, pci_name(rp->pdev));
900 }
901
902 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
903 {
904 struct r6040_private *rp = netdev_priv(dev);
905 int rc;
906
907 spin_lock_irq(&rp->lock);
908 rc = mii_ethtool_gset(&rp->mii_if, cmd);
909 spin_unlock_irq(&rp->lock);
910
911 return rc;
912 }
913
914 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
915 {
916 struct r6040_private *rp = netdev_priv(dev);
917 int rc;
918
919 spin_lock_irq(&rp->lock);
920 rc = mii_ethtool_sset(&rp->mii_if, cmd);
921 spin_unlock_irq(&rp->lock);
922 r6040_set_carrier(&rp->mii_if);
923
924 return rc;
925 }
926
927 static u32 netdev_get_link(struct net_device *dev)
928 {
929 struct r6040_private *rp = netdev_priv(dev);
930
931 return mii_link_ok(&rp->mii_if);
932 }
933
934 static struct ethtool_ops netdev_ethtool_ops = {
935 .get_drvinfo = netdev_get_drvinfo,
936 .get_settings = netdev_get_settings,
937 .set_settings = netdev_set_settings,
938 .get_link = netdev_get_link,
939 };
940
941 static int __devinit r6040_init_one(struct pci_dev *pdev,
942 const struct pci_device_id *ent)
943 {
944 struct net_device *dev;
945 struct r6040_private *lp;
946 void __iomem *ioaddr;
947 int err, io_size = R6040_IO_SIZE;
948 static int card_idx = -1;
949 int bar = 0;
950 long pioaddr;
951 u16 *adrp;
952
953 printk(KERN_INFO "%s\n", version);
954
955 err = pci_enable_device(pdev);
956 if (err)
957 return err;
958
959 /* this should always be supported */
960 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
961 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
962 "not supported by the card\n");
963 return -ENODEV;
964 }
965 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
966 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
967 "not supported by the card\n");
968 return -ENODEV;
969 }
970
971 /* IO Size check */
972 if (pci_resource_len(pdev, 0) < io_size) {
973 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
974 return -EIO;
975 }
976
977 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
978 pci_set_master(pdev);
979
980 dev = alloc_etherdev(sizeof(struct r6040_private));
981 if (!dev) {
982 printk(KERN_ERR "Failed to allocate etherdev\n");
983 return -ENOMEM;
984 }
985 SET_NETDEV_DEV(dev, &pdev->dev);
986 lp = netdev_priv(dev);
987 lp->pdev = pdev;
988
989 if (pci_request_regions(pdev, DRV_NAME)) {
990 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
991 err = -ENODEV;
992 goto err_out_disable;
993 }
994
995 ioaddr = pci_iomap(pdev, bar, io_size);
996 if (!ioaddr) {
997 printk(KERN_ERR "ioremap failed for device %s\n",
998 pci_name(pdev));
999 return -EIO;
1000 }
1001
1002 /* Init system & device */
1003 lp->base = ioaddr;
1004 dev->irq = pdev->irq;
1005
1006 spin_lock_init(&lp->lock);
1007 pci_set_drvdata(pdev, dev);
1008
1009 /* Set MAC address */
1010 card_idx++;
1011
1012 adrp = (u16 *)dev->dev_addr;
1013 adrp[0] = ioread16(ioaddr + MID_0L);
1014 adrp[1] = ioread16(ioaddr + MID_0M);
1015 adrp[2] = ioread16(ioaddr + MID_0H);
1016
1017 /* Link new device into r6040_root_dev */
1018 lp->pdev = pdev;
1019
1020 /* Init RDC private data */
1021 lp->mcr0 = 0x1002;
1022 lp->phy_addr = phy_table[card_idx];
1023 lp->switch_sig = 0;
1024
1025 /* The RDC-specific entries in the device structure. */
1026 dev->open = &r6040_open;
1027 dev->hard_start_xmit = &r6040_start_xmit;
1028 dev->stop = &r6040_close;
1029 dev->get_stats = r6040_get_stats;
1030 dev->set_multicast_list = &r6040_multicast_list;
1031 dev->do_ioctl = &r6040_ioctl;
1032 dev->ethtool_ops = &netdev_ethtool_ops;
1033 dev->tx_timeout = &r6040_tx_timeout;
1034 dev->watchdog_timeo = TX_TIMEOUT;
1035 #ifdef CONFIG_NET_POLL_CONTROLLER
1036 dev->poll_controller = r6040_poll_controller;
1037 #endif
1038 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1039 lp->mii_if.dev = dev;
1040 lp->mii_if.mdio_read = mdio_read;
1041 lp->mii_if.mdio_write = mdio_write;
1042 lp->mii_if.phy_id = lp->phy_addr;
1043 lp->mii_if.phy_id_mask = 0x1f;
1044 lp->mii_if.reg_num_mask = 0x1f;
1045
1046 /* Register net device. After this dev->name assign */
1047 err = register_netdev(dev);
1048 if (err) {
1049 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1050 goto err_out_res;
1051 }
1052 return 0;
1053
1054 err_out_res:
1055 pci_release_regions(pdev);
1056 err_out_disable:
1057 pci_disable_device(pdev);
1058 pci_set_drvdata(pdev, NULL);
1059 free_netdev(dev);
1060
1061 return err;
1062 }
1063
1064 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1065 {
1066 struct net_device *dev = pci_get_drvdata(pdev);
1067
1068 unregister_netdev(dev);
1069 pci_release_regions(pdev);
1070 free_netdev(dev);
1071 pci_disable_device(pdev);
1072 pci_set_drvdata(pdev, NULL);
1073 }
1074
1075
1076 static struct pci_device_id r6040_pci_tbl[] = {
1077 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1078 { 0 }
1079 };
1080 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1081
1082 static struct pci_driver r6040_driver = {
1083 .name = DRV_NAME,
1084 .id_table = r6040_pci_tbl,
1085 .probe = r6040_init_one,
1086 .remove = __devexit_p(r6040_remove_one),
1087 };
1088
1089
1090 static int __init r6040_init(void)
1091 {
1092 return pci_register_driver(&r6040_driver);
1093 }
1094
1095
1096 static void __exit r6040_cleanup(void)
1097 {
1098 pci_unregister_driver(&r6040_driver);
1099 }
1100
1101 module_init(r6040_init);
1102 module_exit(r6040_cleanup);
Linux kernel - Deliverables
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