2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work
= 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit
= 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
94 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
103 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
113 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
114 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
115 RTL_GIGA_MAC_VER_23
= 0x17 // 8168CP
118 #define _R(NAME,MAC,MASK) \
119 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
121 static const struct {
124 u32 RxConfigMask
; /* Clears the bits supported by this chip */
125 } rtl_chip_info
[] = {
126 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
127 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
128 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
129 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
130 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
131 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
132 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
133 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
134 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
136 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
137 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
138 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
139 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
140 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
143 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
144 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
145 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880) // PCI-E
158 static void rtl_hw_start_8169(struct net_device
*);
159 static void rtl_hw_start_8168(struct net_device
*);
160 static void rtl_hw_start_8101(struct net_device
*);
162 static struct pci_device_id rtl8169_pci_tbl
[] = {
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
168 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
169 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
170 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
171 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
172 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
174 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
178 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
180 static int rx_copybreak
= 200;
187 MAC0
= 0, /* Ethernet hardware address. */
189 MAR0
= 8, /* Multicast filter. */
190 CounterAddrLow
= 0x10,
191 CounterAddrHigh
= 0x14,
192 TxDescStartAddrLow
= 0x20,
193 TxDescStartAddrHigh
= 0x24,
194 TxHDescStartAddrLow
= 0x28,
195 TxHDescStartAddrHigh
= 0x2c,
218 RxDescAddrLow
= 0xe4,
219 RxDescAddrHigh
= 0xe8,
222 FuncEventMask
= 0xf4,
223 FuncPresetState
= 0xf8,
224 FuncForceEvent
= 0xfc,
227 enum rtl8110_registers
{
233 enum rtl8168_8101_registers
{
236 #define CSIAR_FLAG 0x80000000
237 #define CSIAR_WRITE_CMD 0x80000000
238 #define CSIAR_BYTE_ENABLE 0x0f
239 #define CSIAR_BYTE_ENABLE_SHIFT 12
240 #define CSIAR_ADDR_MASK 0x0fff
243 #define EPHYAR_FLAG 0x80000000
244 #define EPHYAR_WRITE_CMD 0x80000000
245 #define EPHYAR_REG_MASK 0x1f
246 #define EPHYAR_REG_SHIFT 16
247 #define EPHYAR_DATA_MASK 0xffff
249 #define FIX_NAK_1 (1 << 4)
250 #define FIX_NAK_2 (1 << 3)
253 enum rtl_register_content
{
254 /* InterruptStatusBits */
258 TxDescUnavail
= 0x0080,
280 /* TXPoll register p.5 */
281 HPQ
= 0x80, /* Poll cmd on the high prio queue */
282 NPQ
= 0x40, /* Poll cmd on the low prio queue */
283 FSWInt
= 0x01, /* Forced software interrupt */
287 Cfg9346_Unlock
= 0xc0,
292 AcceptBroadcast
= 0x08,
293 AcceptMulticast
= 0x04,
295 AcceptAllPhys
= 0x01,
302 TxInterFrameGapShift
= 24,
303 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
305 /* Config1 register p.24 */
308 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
309 Speed_down
= (1 << 4),
313 PMEnable
= (1 << 0), /* Power Management Enable */
315 /* Config2 register p. 25 */
316 PCI_Clock_66MHz
= 0x01,
317 PCI_Clock_33MHz
= 0x00,
319 /* Config3 register p.25 */
320 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
321 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
322 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
324 /* Config5 register p.27 */
325 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
326 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
327 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
328 LanWake
= (1 << 1), /* LanWake enable/disable */
329 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
332 TBIReset
= 0x80000000,
333 TBILoopback
= 0x40000000,
334 TBINwEnable
= 0x20000000,
335 TBINwRestart
= 0x10000000,
336 TBILinkOk
= 0x02000000,
337 TBINwComplete
= 0x01000000,
340 EnableBist
= (1 << 15), // 8168 8101
341 Mac_dbgo_oe
= (1 << 14), // 8168 8101
342 Normal_mode
= (1 << 13), // unused
343 Force_half_dup
= (1 << 12), // 8168 8101
344 Force_rxflow_en
= (1 << 11), // 8168 8101
345 Force_txflow_en
= (1 << 10), // 8168 8101
346 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
347 ASF
= (1 << 8), // 8168 8101
348 PktCntrDisable
= (1 << 7), // 8168 8101
349 Mac_dbgo_sel
= 0x001c, // 8168
354 INTT_0
= 0x0000, // 8168
355 INTT_1
= 0x0001, // 8168
356 INTT_2
= 0x0002, // 8168
357 INTT_3
= 0x0003, // 8168
359 /* rtl8169_PHYstatus */
370 TBILinkOK
= 0x02000000,
372 /* DumpCounterCommand */
376 enum desc_status_bit
{
377 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
378 RingEnd
= (1 << 30), /* End of descriptor ring */
379 FirstFrag
= (1 << 29), /* First segment of a packet */
380 LastFrag
= (1 << 28), /* Final segment of a packet */
383 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
384 MSSShift
= 16, /* MSS value position */
385 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
386 IPCS
= (1 << 18), /* Calculate IP checksum */
387 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
388 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
389 TxVlanTag
= (1 << 17), /* Add VLAN tag */
392 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
393 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
395 #define RxProtoUDP (PID1)
396 #define RxProtoTCP (PID0)
397 #define RxProtoIP (PID1 | PID0)
398 #define RxProtoMask RxProtoIP
400 IPFail
= (1 << 16), /* IP checksum failed */
401 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
402 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
403 RxVlanTag
= (1 << 16), /* VLAN tag available */
406 #define RsvdMask 0x3fffc000
423 u8 __pad
[sizeof(void *) - sizeof(u32
)];
427 RTL_FEATURE_WOL
= (1 << 0),
428 RTL_FEATURE_MSI
= (1 << 1),
429 RTL_FEATURE_GMII
= (1 << 2),
432 struct rtl8169_private
{
433 void __iomem
*mmio_addr
; /* memory map physical address */
434 struct pci_dev
*pci_dev
; /* Index of PCI device */
435 struct net_device
*dev
;
436 struct napi_struct napi
;
437 spinlock_t lock
; /* spin lock flag */
441 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
442 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
445 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
446 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
447 dma_addr_t TxPhyAddr
;
448 dma_addr_t RxPhyAddr
;
449 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
450 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
453 struct timer_list timer
;
458 int phy_auto_nego_reg
;
459 int phy_1000_ctrl_reg
;
460 #ifdef CONFIG_R8169_VLAN
461 struct vlan_group
*vlgrp
;
463 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
464 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
465 void (*phy_reset_enable
)(void __iomem
*);
466 void (*hw_start
)(struct net_device
*);
467 unsigned int (*phy_reset_pending
)(void __iomem
*);
468 unsigned int (*link_ok
)(void __iomem
*);
470 struct delayed_work task
;
473 struct mii_if_info mii
;
476 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
477 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
478 module_param(rx_copybreak
, int, 0);
479 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
480 module_param(use_dac
, int, 0);
481 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
482 module_param_named(debug
, debug
.msg_enable
, int, 0);
483 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
484 MODULE_LICENSE("GPL");
485 MODULE_VERSION(RTL8169_VERSION
);
487 static int rtl8169_open(struct net_device
*dev
);
488 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
489 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
490 static int rtl8169_init_ring(struct net_device
*dev
);
491 static void rtl_hw_start(struct net_device
*dev
);
492 static int rtl8169_close(struct net_device
*dev
);
493 static void rtl_set_rx_mode(struct net_device
*dev
);
494 static void rtl8169_tx_timeout(struct net_device
*dev
);
495 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
496 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
497 void __iomem
*, u32 budget
);
498 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
499 static void rtl8169_down(struct net_device
*dev
);
500 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
501 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
503 static const unsigned int rtl8169_rx_config
=
504 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
506 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
510 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
512 for (i
= 20; i
> 0; i
--) {
514 * Check if the RTL8169 has completed writing to the specified
517 if (!(RTL_R32(PHYAR
) & 0x80000000))
523 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
527 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
529 for (i
= 20; i
> 0; i
--) {
531 * Check if the RTL8169 has completed retrieving data from
532 * the specified MII register.
534 if (RTL_R32(PHYAR
) & 0x80000000) {
535 value
= RTL_R32(PHYAR
) & 0xffff;
543 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
545 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
548 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
551 struct rtl8169_private
*tp
= netdev_priv(dev
);
552 void __iomem
*ioaddr
= tp
->mmio_addr
;
554 mdio_write(ioaddr
, location
, val
);
557 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
559 struct rtl8169_private
*tp
= netdev_priv(dev
);
560 void __iomem
*ioaddr
= tp
->mmio_addr
;
562 return mdio_read(ioaddr
, location
);
565 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
569 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
570 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
572 for (i
= 0; i
< 100; i
++) {
573 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
579 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
584 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
586 for (i
= 0; i
< 100; i
++) {
587 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
588 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
597 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
601 RTL_W32(CSIDR
, value
);
602 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
603 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
605 for (i
= 0; i
< 100; i
++) {
606 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
612 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
617 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
618 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
620 for (i
= 0; i
< 100; i
++) {
621 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
622 value
= RTL_R32(CSIDR
);
631 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
633 RTL_W16(IntrMask
, 0x0000);
635 RTL_W16(IntrStatus
, 0xffff);
638 static void rtl8169_asic_down(void __iomem
*ioaddr
)
640 RTL_W8(ChipCmd
, 0x00);
641 rtl8169_irq_mask_and_ack(ioaddr
);
645 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
647 return RTL_R32(TBICSR
) & TBIReset
;
650 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
652 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
655 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
657 return RTL_R32(TBICSR
) & TBILinkOk
;
660 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
662 return RTL_R8(PHYstatus
) & LinkStatus
;
665 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
667 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
670 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
674 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
675 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
678 static void rtl8169_check_link_status(struct net_device
*dev
,
679 struct rtl8169_private
*tp
,
680 void __iomem
*ioaddr
)
684 spin_lock_irqsave(&tp
->lock
, flags
);
685 if (tp
->link_ok(ioaddr
)) {
686 netif_carrier_on(dev
);
687 if (netif_msg_ifup(tp
))
688 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
690 if (netif_msg_ifdown(tp
))
691 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
692 netif_carrier_off(dev
);
694 spin_unlock_irqrestore(&tp
->lock
, flags
);
697 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
699 struct rtl8169_private
*tp
= netdev_priv(dev
);
700 void __iomem
*ioaddr
= tp
->mmio_addr
;
705 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
706 wol
->supported
= WAKE_ANY
;
708 spin_lock_irq(&tp
->lock
);
710 options
= RTL_R8(Config1
);
711 if (!(options
& PMEnable
))
714 options
= RTL_R8(Config3
);
715 if (options
& LinkUp
)
716 wol
->wolopts
|= WAKE_PHY
;
717 if (options
& MagicPacket
)
718 wol
->wolopts
|= WAKE_MAGIC
;
720 options
= RTL_R8(Config5
);
722 wol
->wolopts
|= WAKE_UCAST
;
724 wol
->wolopts
|= WAKE_BCAST
;
726 wol
->wolopts
|= WAKE_MCAST
;
729 spin_unlock_irq(&tp
->lock
);
732 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
734 struct rtl8169_private
*tp
= netdev_priv(dev
);
735 void __iomem
*ioaddr
= tp
->mmio_addr
;
742 { WAKE_ANY
, Config1
, PMEnable
},
743 { WAKE_PHY
, Config3
, LinkUp
},
744 { WAKE_MAGIC
, Config3
, MagicPacket
},
745 { WAKE_UCAST
, Config5
, UWF
},
746 { WAKE_BCAST
, Config5
, BWF
},
747 { WAKE_MCAST
, Config5
, MWF
},
748 { WAKE_ANY
, Config5
, LanWake
}
751 spin_lock_irq(&tp
->lock
);
753 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
755 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
756 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
757 if (wol
->wolopts
& cfg
[i
].opt
)
758 options
|= cfg
[i
].mask
;
759 RTL_W8(cfg
[i
].reg
, options
);
762 RTL_W8(Cfg9346
, Cfg9346_Lock
);
765 tp
->features
|= RTL_FEATURE_WOL
;
767 tp
->features
&= ~RTL_FEATURE_WOL
;
768 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
770 spin_unlock_irq(&tp
->lock
);
775 static void rtl8169_get_drvinfo(struct net_device
*dev
,
776 struct ethtool_drvinfo
*info
)
778 struct rtl8169_private
*tp
= netdev_priv(dev
);
780 strcpy(info
->driver
, MODULENAME
);
781 strcpy(info
->version
, RTL8169_VERSION
);
782 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
785 static int rtl8169_get_regs_len(struct net_device
*dev
)
787 return R8169_REGS_SIZE
;
790 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
791 u8 autoneg
, u16 speed
, u8 duplex
)
793 struct rtl8169_private
*tp
= netdev_priv(dev
);
794 void __iomem
*ioaddr
= tp
->mmio_addr
;
798 reg
= RTL_R32(TBICSR
);
799 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
800 (duplex
== DUPLEX_FULL
)) {
801 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
802 } else if (autoneg
== AUTONEG_ENABLE
)
803 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
805 if (netif_msg_link(tp
)) {
806 printk(KERN_WARNING
"%s: "
807 "incorrect speed setting refused in TBI mode\n",
816 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
817 u8 autoneg
, u16 speed
, u8 duplex
)
819 struct rtl8169_private
*tp
= netdev_priv(dev
);
820 void __iomem
*ioaddr
= tp
->mmio_addr
;
821 int auto_nego
, giga_ctrl
;
823 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
824 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
825 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
826 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
827 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
829 if (autoneg
== AUTONEG_ENABLE
) {
830 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
831 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
832 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
834 if (speed
== SPEED_10
)
835 auto_nego
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
836 else if (speed
== SPEED_100
)
837 auto_nego
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
838 else if (speed
== SPEED_1000
)
839 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
841 if (duplex
== DUPLEX_HALF
)
842 auto_nego
&= ~(ADVERTISE_10FULL
| ADVERTISE_100FULL
);
844 if (duplex
== DUPLEX_FULL
)
845 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_100HALF
);
847 /* This tweak comes straight from Realtek's driver. */
848 if ((speed
== SPEED_100
) && (duplex
== DUPLEX_HALF
) &&
849 ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
850 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
))) {
851 auto_nego
= ADVERTISE_100HALF
| ADVERTISE_CSMA
;
855 /* The 8100e/8101e/8102e do Fast Ethernet only. */
856 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_07
) ||
857 (tp
->mac_version
== RTL_GIGA_MAC_VER_08
) ||
858 (tp
->mac_version
== RTL_GIGA_MAC_VER_09
) ||
859 (tp
->mac_version
== RTL_GIGA_MAC_VER_10
) ||
860 (tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
861 (tp
->mac_version
== RTL_GIGA_MAC_VER_14
) ||
862 (tp
->mac_version
== RTL_GIGA_MAC_VER_15
) ||
863 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
864 if ((giga_ctrl
& (ADVERTISE_1000FULL
| ADVERTISE_1000HALF
)) &&
865 netif_msg_link(tp
)) {
866 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
869 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
872 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
874 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
875 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
876 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
879 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
881 mdio_write(ioaddr
, 0x1f, 0x0000);
882 mdio_write(ioaddr
, 0x0e, 0x0000);
885 tp
->phy_auto_nego_reg
= auto_nego
;
886 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
888 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
889 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
890 mdio_write(ioaddr
, MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
);
894 static int rtl8169_set_speed(struct net_device
*dev
,
895 u8 autoneg
, u16 speed
, u8 duplex
)
897 struct rtl8169_private
*tp
= netdev_priv(dev
);
900 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
902 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
903 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
908 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
910 struct rtl8169_private
*tp
= netdev_priv(dev
);
914 spin_lock_irqsave(&tp
->lock
, flags
);
915 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
916 spin_unlock_irqrestore(&tp
->lock
, flags
);
921 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
923 struct rtl8169_private
*tp
= netdev_priv(dev
);
925 return tp
->cp_cmd
& RxChkSum
;
928 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
930 struct rtl8169_private
*tp
= netdev_priv(dev
);
931 void __iomem
*ioaddr
= tp
->mmio_addr
;
934 spin_lock_irqsave(&tp
->lock
, flags
);
937 tp
->cp_cmd
|= RxChkSum
;
939 tp
->cp_cmd
&= ~RxChkSum
;
941 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
944 spin_unlock_irqrestore(&tp
->lock
, flags
);
949 #ifdef CONFIG_R8169_VLAN
951 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
954 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
955 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
958 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
959 struct vlan_group
*grp
)
961 struct rtl8169_private
*tp
= netdev_priv(dev
);
962 void __iomem
*ioaddr
= tp
->mmio_addr
;
965 spin_lock_irqsave(&tp
->lock
, flags
);
968 tp
->cp_cmd
|= RxVlan
;
970 tp
->cp_cmd
&= ~RxVlan
;
971 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
973 spin_unlock_irqrestore(&tp
->lock
, flags
);
976 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
979 u32 opts2
= le32_to_cpu(desc
->opts2
);
980 struct vlan_group
*vlgrp
= tp
->vlgrp
;
983 if (vlgrp
&& (opts2
& RxVlanTag
)) {
984 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
992 #else /* !CONFIG_R8169_VLAN */
994 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1000 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1001 struct sk_buff
*skb
)
1008 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1010 struct rtl8169_private
*tp
= netdev_priv(dev
);
1011 void __iomem
*ioaddr
= tp
->mmio_addr
;
1015 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1016 cmd
->port
= PORT_FIBRE
;
1017 cmd
->transceiver
= XCVR_INTERNAL
;
1019 status
= RTL_R32(TBICSR
);
1020 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1021 cmd
->autoneg
= !!(status
& TBINwEnable
);
1023 cmd
->speed
= SPEED_1000
;
1024 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1029 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1031 struct rtl8169_private
*tp
= netdev_priv(dev
);
1033 return mii_ethtool_gset(&tp
->mii
, cmd
);
1036 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1038 struct rtl8169_private
*tp
= netdev_priv(dev
);
1039 unsigned long flags
;
1042 spin_lock_irqsave(&tp
->lock
, flags
);
1044 rc
= tp
->get_settings(dev
, cmd
);
1046 spin_unlock_irqrestore(&tp
->lock
, flags
);
1050 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1053 struct rtl8169_private
*tp
= netdev_priv(dev
);
1054 unsigned long flags
;
1056 if (regs
->len
> R8169_REGS_SIZE
)
1057 regs
->len
= R8169_REGS_SIZE
;
1059 spin_lock_irqsave(&tp
->lock
, flags
);
1060 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1061 spin_unlock_irqrestore(&tp
->lock
, flags
);
1064 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1066 struct rtl8169_private
*tp
= netdev_priv(dev
);
1068 return tp
->msg_enable
;
1071 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1073 struct rtl8169_private
*tp
= netdev_priv(dev
);
1075 tp
->msg_enable
= value
;
1078 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1085 "tx_single_collisions",
1086 "tx_multi_collisions",
1094 struct rtl8169_counters
{
1100 __le16 align_errors
;
1101 __le32 tx_one_collision
;
1102 __le32 tx_multi_collision
;
1104 __le64 rx_broadcast
;
1105 __le32 rx_multicast
;
1110 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1114 return ARRAY_SIZE(rtl8169_gstrings
);
1120 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1121 struct ethtool_stats
*stats
, u64
*data
)
1123 struct rtl8169_private
*tp
= netdev_priv(dev
);
1124 void __iomem
*ioaddr
= tp
->mmio_addr
;
1125 struct rtl8169_counters
*counters
;
1131 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1135 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1136 cmd
= (u64
)paddr
& DMA_32BIT_MASK
;
1137 RTL_W32(CounterAddrLow
, cmd
);
1138 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1140 while (RTL_R32(CounterAddrLow
) & CounterDump
) {
1141 if (msleep_interruptible(1))
1145 RTL_W32(CounterAddrLow
, 0);
1146 RTL_W32(CounterAddrHigh
, 0);
1148 data
[0] = le64_to_cpu(counters
->tx_packets
);
1149 data
[1] = le64_to_cpu(counters
->rx_packets
);
1150 data
[2] = le64_to_cpu(counters
->tx_errors
);
1151 data
[3] = le32_to_cpu(counters
->rx_errors
);
1152 data
[4] = le16_to_cpu(counters
->rx_missed
);
1153 data
[5] = le16_to_cpu(counters
->align_errors
);
1154 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1155 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1156 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1157 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1158 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1159 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1160 data
[12] = le16_to_cpu(counters
->tx_underun
);
1162 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1165 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1169 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1174 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1175 .get_drvinfo
= rtl8169_get_drvinfo
,
1176 .get_regs_len
= rtl8169_get_regs_len
,
1177 .get_link
= ethtool_op_get_link
,
1178 .get_settings
= rtl8169_get_settings
,
1179 .set_settings
= rtl8169_set_settings
,
1180 .get_msglevel
= rtl8169_get_msglevel
,
1181 .set_msglevel
= rtl8169_set_msglevel
,
1182 .get_rx_csum
= rtl8169_get_rx_csum
,
1183 .set_rx_csum
= rtl8169_set_rx_csum
,
1184 .set_tx_csum
= ethtool_op_set_tx_csum
,
1185 .set_sg
= ethtool_op_set_sg
,
1186 .set_tso
= ethtool_op_set_tso
,
1187 .get_regs
= rtl8169_get_regs
,
1188 .get_wol
= rtl8169_get_wol
,
1189 .set_wol
= rtl8169_set_wol
,
1190 .get_strings
= rtl8169_get_strings
,
1191 .get_sset_count
= rtl8169_get_sset_count
,
1192 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1195 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1196 int bitnum
, int bitval
)
1200 val
= mdio_read(ioaddr
, reg
);
1201 val
= (bitval
== 1) ?
1202 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1203 mdio_write(ioaddr
, reg
, val
& 0xffff);
1206 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1207 void __iomem
*ioaddr
)
1210 * The driver currently handles the 8168Bf and the 8168Be identically
1211 * but they can be identified more specifically through the test below
1214 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1216 * Same thing for the 8101Eb and the 8101Ec:
1218 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1226 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1227 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1228 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_23
},
1229 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1230 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1231 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1232 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1233 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1236 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1237 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1238 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1239 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1242 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1243 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1244 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1245 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1246 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1247 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1248 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1249 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1250 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1251 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1252 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1253 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1254 /* FIXME: where did these entries come from ? -- FR */
1255 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1256 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1259 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1260 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1261 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1262 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1263 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1264 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1266 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01
} /* Catch-all */
1270 reg
= RTL_R32(TxConfig
);
1271 while ((reg
& p
->mask
) != p
->val
)
1273 tp
->mac_version
= p
->mac_version
;
1275 if (p
->mask
== 0x00000000) {
1276 struct pci_dev
*pdev
= tp
->pci_dev
;
1278 dev_info(&pdev
->dev
, "unknown MAC (%08x)\n", reg
);
1282 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1284 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1292 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1295 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1300 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1303 u16 regs
[5]; /* Beware of bit-sign propagation */
1304 } phy_magic
[5] = { {
1305 { 0x0000, //w 4 15 12 0
1306 0x00a1, //w 3 15 0 00a1
1307 0x0008, //w 2 15 0 0008
1308 0x1020, //w 1 15 0 1020
1309 0x1000 } },{ //w 0 15 0 1000
1310 { 0x7000, //w 4 15 12 7
1311 0xff41, //w 3 15 0 ff41
1312 0xde60, //w 2 15 0 de60
1313 0x0140, //w 1 15 0 0140
1314 0x0077 } },{ //w 0 15 0 0077
1315 { 0xa000, //w 4 15 12 a
1316 0xdf01, //w 3 15 0 df01
1317 0xdf20, //w 2 15 0 df20
1318 0xff95, //w 1 15 0 ff95
1319 0xfa00 } },{ //w 0 15 0 fa00
1320 { 0xb000, //w 4 15 12 b
1321 0xff41, //w 3 15 0 ff41
1322 0xde20, //w 2 15 0 de20
1323 0x0140, //w 1 15 0 0140
1324 0x00bb } },{ //w 0 15 0 00bb
1325 { 0xf000, //w 4 15 12 f
1326 0xdf01, //w 3 15 0 df01
1327 0xdf20, //w 2 15 0 df20
1328 0xff95, //w 1 15 0 ff95
1329 0xbf00 } //w 0 15 0 bf00
1334 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1335 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1336 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1337 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1339 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1342 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1343 mdio_write(ioaddr
, pos
, val
);
1345 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1346 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1347 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1349 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1352 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1354 struct phy_reg phy_reg_init
[] = {
1360 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1363 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1365 struct phy_reg phy_reg_init
[] = {
1370 mdio_write(ioaddr
, 0x1f, 0x0001);
1371 mdio_patch(ioaddr
, 0x16, 1 << 0);
1373 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1376 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1378 struct phy_reg phy_reg_init
[] = {
1384 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1387 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1389 struct phy_reg phy_reg_init
[] = {
1397 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1400 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1402 struct phy_reg phy_reg_init
[] = {
1408 mdio_write(ioaddr
, 0x1f, 0x0000);
1409 mdio_patch(ioaddr
, 0x14, 1 << 5);
1410 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1412 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1415 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1417 struct phy_reg phy_reg_init
[] = {
1437 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1439 mdio_patch(ioaddr
, 0x14, 1 << 5);
1440 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1441 mdio_write(ioaddr
, 0x1f, 0x0000);
1444 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1446 struct phy_reg phy_reg_init
[] = {
1464 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1466 mdio_patch(ioaddr
, 0x16, 1 << 0);
1467 mdio_patch(ioaddr
, 0x14, 1 << 5);
1468 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1469 mdio_write(ioaddr
, 0x1f, 0x0000);
1472 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1474 struct phy_reg phy_reg_init
[] = {
1486 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1488 mdio_patch(ioaddr
, 0x16, 1 << 0);
1489 mdio_patch(ioaddr
, 0x14, 1 << 5);
1490 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1491 mdio_write(ioaddr
, 0x1f, 0x0000);
1494 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1496 rtl8168c_3_hw_phy_config(ioaddr
);
1499 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
1501 struct phy_reg phy_reg_init
[] = {
1508 mdio_write(ioaddr
, 0x1f, 0x0000);
1509 mdio_patch(ioaddr
, 0x11, 1 << 12);
1510 mdio_patch(ioaddr
, 0x19, 1 << 13);
1512 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1515 static void rtl_hw_phy_config(struct net_device
*dev
)
1517 struct rtl8169_private
*tp
= netdev_priv(dev
);
1518 void __iomem
*ioaddr
= tp
->mmio_addr
;
1520 rtl8169_print_mac_version(tp
);
1522 switch (tp
->mac_version
) {
1523 case RTL_GIGA_MAC_VER_01
:
1525 case RTL_GIGA_MAC_VER_02
:
1526 case RTL_GIGA_MAC_VER_03
:
1527 rtl8169s_hw_phy_config(ioaddr
);
1529 case RTL_GIGA_MAC_VER_04
:
1530 rtl8169sb_hw_phy_config(ioaddr
);
1532 case RTL_GIGA_MAC_VER_07
:
1533 case RTL_GIGA_MAC_VER_08
:
1534 case RTL_GIGA_MAC_VER_09
:
1535 rtl8102e_hw_phy_config(ioaddr
);
1537 case RTL_GIGA_MAC_VER_11
:
1538 rtl8168bb_hw_phy_config(ioaddr
);
1540 case RTL_GIGA_MAC_VER_12
:
1541 rtl8168bef_hw_phy_config(ioaddr
);
1543 case RTL_GIGA_MAC_VER_17
:
1544 rtl8168bef_hw_phy_config(ioaddr
);
1546 case RTL_GIGA_MAC_VER_18
:
1547 rtl8168cp_1_hw_phy_config(ioaddr
);
1549 case RTL_GIGA_MAC_VER_19
:
1550 rtl8168c_1_hw_phy_config(ioaddr
);
1552 case RTL_GIGA_MAC_VER_20
:
1553 rtl8168c_2_hw_phy_config(ioaddr
);
1555 case RTL_GIGA_MAC_VER_21
:
1556 rtl8168c_3_hw_phy_config(ioaddr
);
1558 case RTL_GIGA_MAC_VER_22
:
1559 rtl8168c_4_hw_phy_config(ioaddr
);
1561 case RTL_GIGA_MAC_VER_23
:
1562 rtl8168cp_2_hw_phy_config(ioaddr
);
1570 static void rtl8169_phy_timer(unsigned long __opaque
)
1572 struct net_device
*dev
= (struct net_device
*)__opaque
;
1573 struct rtl8169_private
*tp
= netdev_priv(dev
);
1574 struct timer_list
*timer
= &tp
->timer
;
1575 void __iomem
*ioaddr
= tp
->mmio_addr
;
1576 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1578 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1580 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1583 spin_lock_irq(&tp
->lock
);
1585 if (tp
->phy_reset_pending(ioaddr
)) {
1587 * A busy loop could burn quite a few cycles on nowadays CPU.
1588 * Let's delay the execution of the timer for a few ticks.
1594 if (tp
->link_ok(ioaddr
))
1597 if (netif_msg_link(tp
))
1598 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1600 tp
->phy_reset_enable(ioaddr
);
1603 mod_timer(timer
, jiffies
+ timeout
);
1605 spin_unlock_irq(&tp
->lock
);
1608 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1610 struct rtl8169_private
*tp
= netdev_priv(dev
);
1611 struct timer_list
*timer
= &tp
->timer
;
1613 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1616 del_timer_sync(timer
);
1619 static inline void rtl8169_request_timer(struct net_device
*dev
)
1621 struct rtl8169_private
*tp
= netdev_priv(dev
);
1622 struct timer_list
*timer
= &tp
->timer
;
1624 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1627 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1630 #ifdef CONFIG_NET_POLL_CONTROLLER
1632 * Polling 'interrupt' - used by things like netconsole to send skbs
1633 * without having to re-enable interrupts. It's not called while
1634 * the interrupt routine is executing.
1636 static void rtl8169_netpoll(struct net_device
*dev
)
1638 struct rtl8169_private
*tp
= netdev_priv(dev
);
1639 struct pci_dev
*pdev
= tp
->pci_dev
;
1641 disable_irq(pdev
->irq
);
1642 rtl8169_interrupt(pdev
->irq
, dev
);
1643 enable_irq(pdev
->irq
);
1647 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1648 void __iomem
*ioaddr
)
1651 pci_release_regions(pdev
);
1652 pci_disable_device(pdev
);
1656 static void rtl8169_phy_reset(struct net_device
*dev
,
1657 struct rtl8169_private
*tp
)
1659 void __iomem
*ioaddr
= tp
->mmio_addr
;
1662 tp
->phy_reset_enable(ioaddr
);
1663 for (i
= 0; i
< 100; i
++) {
1664 if (!tp
->phy_reset_pending(ioaddr
))
1668 if (netif_msg_link(tp
))
1669 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1672 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1674 void __iomem
*ioaddr
= tp
->mmio_addr
;
1676 rtl_hw_phy_config(dev
);
1678 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1679 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1683 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1685 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1686 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1688 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1689 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1691 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1692 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1695 rtl8169_phy_reset(dev
, tp
);
1698 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1699 * only 8101. Don't panic.
1701 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1703 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1704 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1707 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1709 void __iomem
*ioaddr
= tp
->mmio_addr
;
1713 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1714 high
= addr
[4] | (addr
[5] << 8);
1716 spin_lock_irq(&tp
->lock
);
1718 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1720 RTL_W32(MAC4
, high
);
1721 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1723 spin_unlock_irq(&tp
->lock
);
1726 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1728 struct rtl8169_private
*tp
= netdev_priv(dev
);
1729 struct sockaddr
*addr
= p
;
1731 if (!is_valid_ether_addr(addr
->sa_data
))
1732 return -EADDRNOTAVAIL
;
1734 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1736 rtl_rar_set(tp
, dev
->dev_addr
);
1741 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1743 struct rtl8169_private
*tp
= netdev_priv(dev
);
1744 struct mii_ioctl_data
*data
= if_mii(ifr
);
1746 if (!netif_running(dev
))
1751 data
->phy_id
= 32; /* Internal PHY */
1755 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1759 if (!capable(CAP_NET_ADMIN
))
1761 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1767 static const struct rtl_cfg_info
{
1768 void (*hw_start
)(struct net_device
*);
1769 unsigned int region
;
1774 } rtl_cfg_infos
[] = {
1776 .hw_start
= rtl_hw_start_8169
,
1779 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1780 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1781 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1782 .features
= RTL_FEATURE_GMII
1785 .hw_start
= rtl_hw_start_8168
,
1788 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1789 TxErr
| TxOK
| RxOK
| RxErr
,
1790 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1791 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
1794 .hw_start
= rtl_hw_start_8101
,
1797 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1798 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1799 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1800 .features
= RTL_FEATURE_MSI
1804 /* Cfg9346_Unlock assumed. */
1805 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1806 const struct rtl_cfg_info
*cfg
)
1811 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1812 if (cfg
->features
& RTL_FEATURE_MSI
) {
1813 if (pci_enable_msi(pdev
)) {
1814 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1817 msi
= RTL_FEATURE_MSI
;
1820 RTL_W8(Config2
, cfg2
);
1824 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
1826 if (tp
->features
& RTL_FEATURE_MSI
) {
1827 pci_disable_msi(pdev
);
1828 tp
->features
&= ~RTL_FEATURE_MSI
;
1832 static int rtl_eeprom_read(struct pci_dev
*pdev
, int cap
, int addr
, __le32
*val
)
1834 int ret
, count
= 100;
1838 ret
= pci_write_config_word(pdev
, cap
+ PCI_VPD_ADDR
, addr
);
1844 ret
= pci_read_config_word(pdev
, cap
+ PCI_VPD_ADDR
, &status
);
1847 } while (!(status
& PCI_VPD_ADDR_F
) && --count
);
1849 if (!(status
& PCI_VPD_ADDR_F
))
1852 ret
= pci_read_config_dword(pdev
, cap
+ PCI_VPD_DATA
, &value
);
1856 *val
= cpu_to_le32(value
);
1861 static void rtl_init_mac_address(struct rtl8169_private
*tp
,
1862 void __iomem
*ioaddr
)
1864 struct pci_dev
*pdev
= tp
->pci_dev
;
1868 DECLARE_MAC_BUF(buf
);
1870 cfg1
= RTL_R8(Config1
);
1871 if (!(cfg1
& VPD
)) {
1872 dprintk("VPD access not enabled, enabling\n");
1873 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1874 RTL_W8(Config1
, cfg1
| VPD
);
1875 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1878 vpd_cap
= pci_find_capability(pdev
, PCI_CAP_ID_VPD
);
1882 /* MAC address is stored in EEPROM at offset 0x0e
1883 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1884 * address as defined in the PCI 2.2 Specifications, but the VPD data
1885 * is always consecutive 4-byte data starting from the VPD address
1888 if (rtl_eeprom_read(pdev
, vpd_cap
, 0x000e, (__le32
*)&mac
[0]) < 0 ||
1889 rtl_eeprom_read(pdev
, vpd_cap
, 0x0012, (__le32
*)&mac
[4]) < 0) {
1890 dprintk("Reading MAC address from EEPROM failed\n");
1894 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf
, mac
));
1896 /* Write MAC address */
1897 rtl_rar_set(tp
, mac
);
1900 static int __devinit
1901 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1903 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1904 const unsigned int region
= cfg
->region
;
1905 struct rtl8169_private
*tp
;
1906 struct mii_if_info
*mii
;
1907 struct net_device
*dev
;
1908 void __iomem
*ioaddr
;
1912 if (netif_msg_drv(&debug
)) {
1913 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
1914 MODULENAME
, RTL8169_VERSION
);
1917 dev
= alloc_etherdev(sizeof (*tp
));
1919 if (netif_msg_drv(&debug
))
1920 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1925 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1926 tp
= netdev_priv(dev
);
1929 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
1933 mii
->mdio_read
= rtl_mdio_read
;
1934 mii
->mdio_write
= rtl_mdio_write
;
1935 mii
->phy_id_mask
= 0x1f;
1936 mii
->reg_num_mask
= 0x1f;
1937 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
1939 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1940 rc
= pci_enable_device(pdev
);
1942 if (netif_msg_probe(tp
))
1943 dev_err(&pdev
->dev
, "enable failure\n");
1944 goto err_out_free_dev_1
;
1947 rc
= pci_set_mwi(pdev
);
1949 goto err_out_disable_2
;
1951 /* make sure PCI base addr 1 is MMIO */
1952 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
1953 if (netif_msg_probe(tp
)) {
1955 "region #%d not an MMIO resource, aborting\n",
1962 /* check for weird/broken PCI region reporting */
1963 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
1964 if (netif_msg_probe(tp
)) {
1966 "Invalid PCI region size(s), aborting\n");
1972 rc
= pci_request_regions(pdev
, MODULENAME
);
1974 if (netif_msg_probe(tp
))
1975 dev_err(&pdev
->dev
, "could not request regions.\n");
1979 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
1981 if ((sizeof(dma_addr_t
) > 4) &&
1982 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) && use_dac
) {
1983 tp
->cp_cmd
|= PCIDAC
;
1984 dev
->features
|= NETIF_F_HIGHDMA
;
1986 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1988 if (netif_msg_probe(tp
)) {
1990 "DMA configuration failed.\n");
1992 goto err_out_free_res_4
;
1996 pci_set_master(pdev
);
1998 /* ioremap MMIO region */
1999 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
2001 if (netif_msg_probe(tp
))
2002 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
2004 goto err_out_free_res_4
;
2007 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2008 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
2009 dev_info(&pdev
->dev
, "no PCI Express capability\n");
2011 /* Unneeded ? Don't mess with Mrs. Murphy. */
2012 rtl8169_irq_mask_and_ack(ioaddr
);
2014 /* Soft reset the chip. */
2015 RTL_W8(ChipCmd
, CmdReset
);
2017 /* Check that the chip has finished the reset. */
2018 for (i
= 0; i
< 100; i
++) {
2019 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2021 msleep_interruptible(1);
2024 /* Identify chip attached to board */
2025 rtl8169_get_mac_version(tp
, ioaddr
);
2027 rtl8169_print_mac_version(tp
);
2029 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
2030 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
2033 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
2034 /* Unknown chip: assume array element #0, original RTL-8169 */
2035 if (netif_msg_probe(tp
)) {
2036 dev_printk(KERN_DEBUG
, &pdev
->dev
,
2037 "unknown chip version, assuming %s\n",
2038 rtl_chip_info
[0].name
);
2044 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2045 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
2046 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
2047 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
2048 tp
->features
|= RTL_FEATURE_WOL
;
2049 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
2050 tp
->features
|= RTL_FEATURE_WOL
;
2051 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
2052 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2054 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
2055 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
2056 tp
->set_speed
= rtl8169_set_speed_tbi
;
2057 tp
->get_settings
= rtl8169_gset_tbi
;
2058 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
2059 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
2060 tp
->link_ok
= rtl8169_tbi_link_ok
;
2062 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
2064 tp
->set_speed
= rtl8169_set_speed_xmii
;
2065 tp
->get_settings
= rtl8169_gset_xmii
;
2066 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
2067 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
2068 tp
->link_ok
= rtl8169_xmii_link_ok
;
2070 dev
->do_ioctl
= rtl8169_ioctl
;
2073 spin_lock_init(&tp
->lock
);
2075 rtl_init_mac_address(tp
, ioaddr
);
2077 /* Get MAC address */
2078 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
2079 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
2080 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
2082 dev
->open
= rtl8169_open
;
2083 dev
->hard_start_xmit
= rtl8169_start_xmit
;
2084 dev
->get_stats
= rtl8169_get_stats
;
2085 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
2086 dev
->stop
= rtl8169_close
;
2087 dev
->tx_timeout
= rtl8169_tx_timeout
;
2088 dev
->set_multicast_list
= rtl_set_rx_mode
;
2089 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
2090 dev
->irq
= pdev
->irq
;
2091 dev
->base_addr
= (unsigned long) ioaddr
;
2092 dev
->change_mtu
= rtl8169_change_mtu
;
2093 dev
->set_mac_address
= rtl_set_mac_address
;
2095 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
2097 #ifdef CONFIG_R8169_VLAN
2098 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2099 dev
->vlan_rx_register
= rtl8169_vlan_rx_register
;
2102 #ifdef CONFIG_NET_POLL_CONTROLLER
2103 dev
->poll_controller
= rtl8169_netpoll
;
2106 tp
->intr_mask
= 0xffff;
2107 tp
->mmio_addr
= ioaddr
;
2108 tp
->align
= cfg
->align
;
2109 tp
->hw_start
= cfg
->hw_start
;
2110 tp
->intr_event
= cfg
->intr_event
;
2111 tp
->napi_event
= cfg
->napi_event
;
2113 init_timer(&tp
->timer
);
2114 tp
->timer
.data
= (unsigned long) dev
;
2115 tp
->timer
.function
= rtl8169_phy_timer
;
2117 rc
= register_netdev(dev
);
2121 pci_set_drvdata(pdev
, dev
);
2123 if (netif_msg_probe(tp
)) {
2124 u32 xid
= RTL_R32(TxConfig
) & 0x7cf0f8ff;
2126 printk(KERN_INFO
"%s: %s at 0x%lx, "
2127 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2128 "XID %08x IRQ %d\n",
2130 rtl_chip_info
[tp
->chipset
].name
,
2132 dev
->dev_addr
[0], dev
->dev_addr
[1],
2133 dev
->dev_addr
[2], dev
->dev_addr
[3],
2134 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
2137 rtl8169_init_phy(dev
, tp
);
2138 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
2144 rtl_disable_msi(pdev
, tp
);
2147 pci_release_regions(pdev
);
2149 pci_clear_mwi(pdev
);
2151 pci_disable_device(pdev
);
2157 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
2159 struct net_device
*dev
= pci_get_drvdata(pdev
);
2160 struct rtl8169_private
*tp
= netdev_priv(dev
);
2162 flush_scheduled_work();
2164 unregister_netdev(dev
);
2165 rtl_disable_msi(pdev
, tp
);
2166 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
2167 pci_set_drvdata(pdev
, NULL
);
2170 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
2171 struct net_device
*dev
)
2173 unsigned int mtu
= dev
->mtu
;
2175 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
2178 static int rtl8169_open(struct net_device
*dev
)
2180 struct rtl8169_private
*tp
= netdev_priv(dev
);
2181 struct pci_dev
*pdev
= tp
->pci_dev
;
2182 int retval
= -ENOMEM
;
2185 rtl8169_set_rxbufsize(tp
, dev
);
2188 * Rx and Tx desscriptors needs 256 bytes alignment.
2189 * pci_alloc_consistent provides more.
2191 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
2193 if (!tp
->TxDescArray
)
2196 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
2198 if (!tp
->RxDescArray
)
2201 retval
= rtl8169_init_ring(dev
);
2205 INIT_DELAYED_WORK(&tp
->task
, NULL
);
2209 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
2210 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
2213 goto err_release_ring_2
;
2215 napi_enable(&tp
->napi
);
2219 rtl8169_request_timer(dev
);
2221 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2226 rtl8169_rx_clear(tp
);
2228 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2231 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2236 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
2238 /* Disable interrupts */
2239 rtl8169_irq_mask_and_ack(ioaddr
);
2241 /* Reset the chipset */
2242 RTL_W8(ChipCmd
, CmdReset
);
2248 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
2250 void __iomem
*ioaddr
= tp
->mmio_addr
;
2251 u32 cfg
= rtl8169_rx_config
;
2253 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
2254 RTL_W32(RxConfig
, cfg
);
2256 /* Set DMA burst size and Interframe Gap Time */
2257 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2258 (InterFrameGap
<< TxInterFrameGapShift
));
2261 static void rtl_hw_start(struct net_device
*dev
)
2263 struct rtl8169_private
*tp
= netdev_priv(dev
);
2264 void __iomem
*ioaddr
= tp
->mmio_addr
;
2267 /* Soft reset the chip. */
2268 RTL_W8(ChipCmd
, CmdReset
);
2270 /* Check that the chip has finished the reset. */
2271 for (i
= 0; i
< 100; i
++) {
2272 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2274 msleep_interruptible(1);
2279 netif_start_queue(dev
);
2283 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
2284 void __iomem
*ioaddr
)
2287 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2288 * register to be written before TxDescAddrLow to work.
2289 * Switching from MMIO to I/O access fixes the issue as well.
2291 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2292 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_32BIT_MASK
);
2293 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2294 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_32BIT_MASK
);
2297 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
2301 cmd
= RTL_R16(CPlusCmd
);
2302 RTL_W16(CPlusCmd
, cmd
);
2306 static void rtl_set_rx_max_size(void __iomem
*ioaddr
)
2308 /* Low hurts. Let's disable the filtering. */
2309 RTL_W16(RxMaxSize
, 16383);
2312 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
2319 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
2320 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
2321 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
2322 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
2327 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
2328 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
2329 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
2330 RTL_W32(0x7c, p
->val
);
2336 static void rtl_hw_start_8169(struct net_device
*dev
)
2338 struct rtl8169_private
*tp
= netdev_priv(dev
);
2339 void __iomem
*ioaddr
= tp
->mmio_addr
;
2340 struct pci_dev
*pdev
= tp
->pci_dev
;
2342 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
2343 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
2344 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2347 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2348 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2349 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2350 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2351 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2352 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2354 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2356 rtl_set_rx_max_size(ioaddr
);
2358 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2359 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2360 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2361 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2362 rtl_set_rx_tx_config_registers(tp
);
2364 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2366 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2367 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2368 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2369 "Bit-3 and bit-14 MUST be 1\n");
2370 tp
->cp_cmd
|= (1 << 14);
2373 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2375 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2378 * Undocumented corner. Supposedly:
2379 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2381 RTL_W16(IntrMitigate
, 0x0000);
2383 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2385 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2386 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2387 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2388 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2389 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2390 rtl_set_rx_tx_config_registers(tp
);
2393 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2395 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2398 RTL_W32(RxMissed
, 0);
2400 rtl_set_rx_mode(dev
);
2402 /* no early-rx interrupts */
2403 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2405 /* Enable all known interrupts by setting the interrupt mask. */
2406 RTL_W16(IntrMask
, tp
->intr_event
);
2409 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2411 struct net_device
*dev
= pci_get_drvdata(pdev
);
2412 struct rtl8169_private
*tp
= netdev_priv(dev
);
2413 int cap
= tp
->pcie_cap
;
2418 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2419 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2420 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2424 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
2428 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
2429 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
2433 unsigned int offset
;
2438 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
2443 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
2444 rtl_ephy_write(ioaddr
, e
->offset
, w
);
2449 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
2451 struct net_device
*dev
= pci_get_drvdata(pdev
);
2452 struct rtl8169_private
*tp
= netdev_priv(dev
);
2453 int cap
= tp
->pcie_cap
;
2458 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
2459 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
2460 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
2464 #define R8168_CPCMD_QUIRK_MASK (\
2475 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2477 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2479 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2481 rtl_tx_performance_tweak(pdev
,
2482 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
2485 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2487 rtl_hw_start_8168bb(ioaddr
, pdev
);
2489 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2491 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
2494 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2496 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
2498 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2500 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2502 rtl_disable_clock_request(pdev
);
2504 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2507 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2509 static struct ephy_info e_info_8168cp
[] = {
2510 { 0x01, 0, 0x0001 },
2511 { 0x02, 0x0800, 0x1000 },
2512 { 0x03, 0, 0x0042 },
2513 { 0x06, 0x0080, 0x0000 },
2517 rtl_csi_access_enable(ioaddr
);
2519 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
2521 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2524 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2526 rtl_csi_access_enable(ioaddr
);
2528 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2530 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2532 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2535 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2537 static struct ephy_info e_info_8168c_1
[] = {
2538 { 0x02, 0x0800, 0x1000 },
2539 { 0x03, 0, 0x0002 },
2540 { 0x06, 0x0080, 0x0000 }
2543 rtl_csi_access_enable(ioaddr
);
2545 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
2547 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
2549 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2552 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2554 static struct ephy_info e_info_8168c_2
[] = {
2555 { 0x01, 0, 0x0001 },
2556 { 0x03, 0x0400, 0x0220 }
2559 rtl_csi_access_enable(ioaddr
);
2561 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
2563 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2566 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2568 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2571 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2573 rtl_csi_access_enable(ioaddr
);
2575 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2578 static void rtl_hw_start_8168(struct net_device
*dev
)
2580 struct rtl8169_private
*tp
= netdev_priv(dev
);
2581 void __iomem
*ioaddr
= tp
->mmio_addr
;
2582 struct pci_dev
*pdev
= tp
->pci_dev
;
2584 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2586 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2588 rtl_set_rx_max_size(ioaddr
);
2590 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2592 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2594 RTL_W16(IntrMitigate
, 0x5151);
2596 /* Work around for RxFIFO overflow. */
2597 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2598 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2599 tp
->intr_event
&= ~RxOverflow
;
2602 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2604 rtl_set_rx_mode(dev
);
2606 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2607 (InterFrameGap
<< TxInterFrameGapShift
));
2611 switch (tp
->mac_version
) {
2612 case RTL_GIGA_MAC_VER_11
:
2613 rtl_hw_start_8168bb(ioaddr
, pdev
);
2616 case RTL_GIGA_MAC_VER_12
:
2617 case RTL_GIGA_MAC_VER_17
:
2618 rtl_hw_start_8168bef(ioaddr
, pdev
);
2621 case RTL_GIGA_MAC_VER_18
:
2622 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
2625 case RTL_GIGA_MAC_VER_19
:
2626 rtl_hw_start_8168c_1(ioaddr
, pdev
);
2629 case RTL_GIGA_MAC_VER_20
:
2630 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2633 case RTL_GIGA_MAC_VER_21
:
2634 rtl_hw_start_8168c_3(ioaddr
, pdev
);
2637 case RTL_GIGA_MAC_VER_22
:
2638 rtl_hw_start_8168c_4(ioaddr
, pdev
);
2641 case RTL_GIGA_MAC_VER_23
:
2642 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
2646 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
2647 dev
->name
, tp
->mac_version
);
2651 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2653 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2655 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2657 RTL_W16(IntrMask
, tp
->intr_event
);
2660 #define R810X_CPCMD_QUIRK_MASK (\
2672 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2674 static struct ephy_info e_info_8102e_1
[] = {
2675 { 0x01, 0, 0x6e65 },
2676 { 0x02, 0, 0x091f },
2677 { 0x03, 0, 0xc2f9 },
2678 { 0x06, 0, 0xafb5 },
2679 { 0x07, 0, 0x0e00 },
2680 { 0x19, 0, 0xec80 },
2681 { 0x01, 0, 0x2e65 },
2686 rtl_csi_access_enable(ioaddr
);
2688 RTL_W8(DBG_REG
, FIX_NAK_1
);
2690 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2693 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
2694 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2696 cfg1
= RTL_R8(Config1
);
2697 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
2698 RTL_W8(Config1
, cfg1
& ~LEDS0
);
2700 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2702 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
2705 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2707 rtl_csi_access_enable(ioaddr
);
2709 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2711 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
2712 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2714 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2717 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2719 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2721 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
2724 static void rtl_hw_start_8101(struct net_device
*dev
)
2726 struct rtl8169_private
*tp
= netdev_priv(dev
);
2727 void __iomem
*ioaddr
= tp
->mmio_addr
;
2728 struct pci_dev
*pdev
= tp
->pci_dev
;
2730 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2731 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2732 int cap
= tp
->pcie_cap
;
2735 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2736 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2740 switch (tp
->mac_version
) {
2741 case RTL_GIGA_MAC_VER_07
:
2742 rtl_hw_start_8102e_1(ioaddr
, pdev
);
2745 case RTL_GIGA_MAC_VER_08
:
2746 rtl_hw_start_8102e_3(ioaddr
, pdev
);
2749 case RTL_GIGA_MAC_VER_09
:
2750 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2754 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2756 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2758 rtl_set_rx_max_size(ioaddr
);
2760 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2762 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2764 RTL_W16(IntrMitigate
, 0x0000);
2766 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2768 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2769 rtl_set_rx_tx_config_registers(tp
);
2771 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2775 rtl_set_rx_mode(dev
);
2777 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2779 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2781 RTL_W16(IntrMask
, tp
->intr_event
);
2784 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2786 struct rtl8169_private
*tp
= netdev_priv(dev
);
2789 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2794 if (!netif_running(dev
))
2799 rtl8169_set_rxbufsize(tp
, dev
);
2801 ret
= rtl8169_init_ring(dev
);
2805 napi_enable(&tp
->napi
);
2809 rtl8169_request_timer(dev
);
2815 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2817 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2818 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2821 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2822 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2824 struct pci_dev
*pdev
= tp
->pci_dev
;
2826 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2827 PCI_DMA_FROMDEVICE
);
2828 dev_kfree_skb(*sk_buff
);
2830 rtl8169_make_unusable_by_asic(desc
);
2833 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2835 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2837 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2840 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2843 desc
->addr
= cpu_to_le64(mapping
);
2845 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2848 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2849 struct net_device
*dev
,
2850 struct RxDesc
*desc
, int rx_buf_sz
,
2853 struct sk_buff
*skb
;
2857 pad
= align
? align
: NET_IP_ALIGN
;
2859 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
2863 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
2865 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2866 PCI_DMA_FROMDEVICE
);
2868 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
2873 rtl8169_make_unusable_by_asic(desc
);
2877 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
2881 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2882 if (tp
->Rx_skbuff
[i
]) {
2883 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2884 tp
->RxDescArray
+ i
);
2889 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
2894 for (cur
= start
; end
- cur
!= 0; cur
++) {
2895 struct sk_buff
*skb
;
2896 unsigned int i
= cur
% NUM_RX_DESC
;
2898 WARN_ON((s32
)(end
- cur
) < 0);
2900 if (tp
->Rx_skbuff
[i
])
2903 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
2904 tp
->RxDescArray
+ i
,
2905 tp
->rx_buf_sz
, tp
->align
);
2909 tp
->Rx_skbuff
[i
] = skb
;
2914 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
2916 desc
->opts1
|= cpu_to_le32(RingEnd
);
2919 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
2921 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
2924 static int rtl8169_init_ring(struct net_device
*dev
)
2926 struct rtl8169_private
*tp
= netdev_priv(dev
);
2928 rtl8169_init_ring_indexes(tp
);
2930 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
2931 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
2933 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
2936 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
2941 rtl8169_rx_clear(tp
);
2945 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
2946 struct TxDesc
*desc
)
2948 unsigned int len
= tx_skb
->len
;
2950 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
2957 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
2961 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
2962 unsigned int entry
= i
% NUM_TX_DESC
;
2963 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2964 unsigned int len
= tx_skb
->len
;
2967 struct sk_buff
*skb
= tx_skb
->skb
;
2969 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
2970 tp
->TxDescArray
+ entry
);
2975 tp
->dev
->stats
.tx_dropped
++;
2978 tp
->cur_tx
= tp
->dirty_tx
= 0;
2981 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
2983 struct rtl8169_private
*tp
= netdev_priv(dev
);
2985 PREPARE_DELAYED_WORK(&tp
->task
, task
);
2986 schedule_delayed_work(&tp
->task
, 4);
2989 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
2991 struct rtl8169_private
*tp
= netdev_priv(dev
);
2992 void __iomem
*ioaddr
= tp
->mmio_addr
;
2994 synchronize_irq(dev
->irq
);
2996 /* Wait for any pending NAPI task to complete */
2997 napi_disable(&tp
->napi
);
2999 rtl8169_irq_mask_and_ack(ioaddr
);
3001 tp
->intr_mask
= 0xffff;
3002 RTL_W16(IntrMask
, tp
->intr_event
);
3003 napi_enable(&tp
->napi
);
3006 static void rtl8169_reinit_task(struct work_struct
*work
)
3008 struct rtl8169_private
*tp
=
3009 container_of(work
, struct rtl8169_private
, task
.work
);
3010 struct net_device
*dev
= tp
->dev
;
3015 if (!netif_running(dev
))
3018 rtl8169_wait_for_quiescence(dev
);
3021 ret
= rtl8169_open(dev
);
3022 if (unlikely(ret
< 0)) {
3023 if (net_ratelimit() && netif_msg_drv(tp
)) {
3024 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
3025 " Rescheduling.\n", dev
->name
, ret
);
3027 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3034 static void rtl8169_reset_task(struct work_struct
*work
)
3036 struct rtl8169_private
*tp
=
3037 container_of(work
, struct rtl8169_private
, task
.work
);
3038 struct net_device
*dev
= tp
->dev
;
3042 if (!netif_running(dev
))
3045 rtl8169_wait_for_quiescence(dev
);
3047 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
3048 rtl8169_tx_clear(tp
);
3050 if (tp
->dirty_rx
== tp
->cur_rx
) {
3051 rtl8169_init_ring_indexes(tp
);
3053 netif_wake_queue(dev
);
3054 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3056 if (net_ratelimit() && netif_msg_intr(tp
)) {
3057 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
3060 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3067 static void rtl8169_tx_timeout(struct net_device
*dev
)
3069 struct rtl8169_private
*tp
= netdev_priv(dev
);
3071 rtl8169_hw_reset(tp
->mmio_addr
);
3073 /* Let's wait a bit while any (async) irq lands on */
3074 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3077 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
3080 struct skb_shared_info
*info
= skb_shinfo(skb
);
3081 unsigned int cur_frag
, entry
;
3082 struct TxDesc
* uninitialized_var(txd
);
3085 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
3086 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
3091 entry
= (entry
+ 1) % NUM_TX_DESC
;
3093 txd
= tp
->TxDescArray
+ entry
;
3095 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
3096 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
3098 /* anti gcc 2.95.3 bugware (sic) */
3099 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3101 txd
->opts1
= cpu_to_le32(status
);
3102 txd
->addr
= cpu_to_le64(mapping
);
3104 tp
->tx_skb
[entry
].len
= len
;
3108 tp
->tx_skb
[entry
].skb
= skb
;
3109 txd
->opts1
|= cpu_to_le32(LastFrag
);
3115 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
3117 if (dev
->features
& NETIF_F_TSO
) {
3118 u32 mss
= skb_shinfo(skb
)->gso_size
;
3121 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
3123 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
3124 const struct iphdr
*ip
= ip_hdr(skb
);
3126 if (ip
->protocol
== IPPROTO_TCP
)
3127 return IPCS
| TCPCS
;
3128 else if (ip
->protocol
== IPPROTO_UDP
)
3129 return IPCS
| UDPCS
;
3130 WARN_ON(1); /* we need a WARN() */
3135 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3137 struct rtl8169_private
*tp
= netdev_priv(dev
);
3138 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
3139 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
3140 void __iomem
*ioaddr
= tp
->mmio_addr
;
3144 int ret
= NETDEV_TX_OK
;
3146 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
3147 if (netif_msg_drv(tp
)) {
3149 "%s: BUG! Tx Ring full when queue awake!\n",
3155 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
3158 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
3160 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
3162 len
= skb_headlen(skb
);
3167 if (unlikely(len
< ETH_ZLEN
)) {
3168 if (skb_padto(skb
, ETH_ZLEN
))
3169 goto err_update_stats
;
3173 opts1
|= FirstFrag
| LastFrag
;
3174 tp
->tx_skb
[entry
].skb
= skb
;
3177 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
3179 tp
->tx_skb
[entry
].len
= len
;
3180 txd
->addr
= cpu_to_le64(mapping
);
3181 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
3185 /* anti gcc 2.95.3 bugware (sic) */
3186 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3187 txd
->opts1
= cpu_to_le32(status
);
3189 dev
->trans_start
= jiffies
;
3191 tp
->cur_tx
+= frags
+ 1;
3195 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
3197 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
3198 netif_stop_queue(dev
);
3200 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
3201 netif_wake_queue(dev
);
3208 netif_stop_queue(dev
);
3209 ret
= NETDEV_TX_BUSY
;
3211 dev
->stats
.tx_dropped
++;
3215 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
3217 struct rtl8169_private
*tp
= netdev_priv(dev
);
3218 struct pci_dev
*pdev
= tp
->pci_dev
;
3219 void __iomem
*ioaddr
= tp
->mmio_addr
;
3220 u16 pci_status
, pci_cmd
;
3222 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3223 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3225 if (netif_msg_intr(tp
)) {
3227 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3228 dev
->name
, pci_cmd
, pci_status
);
3232 * The recovery sequence below admits a very elaborated explanation:
3233 * - it seems to work;
3234 * - I did not see what else could be done;
3235 * - it makes iop3xx happy.
3237 * Feel free to adjust to your needs.
3239 if (pdev
->broken_parity_status
)
3240 pci_cmd
&= ~PCI_COMMAND_PARITY
;
3242 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
3244 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
3246 pci_write_config_word(pdev
, PCI_STATUS
,
3247 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
3248 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
3249 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
3251 /* The infamous DAC f*ckup only happens at boot time */
3252 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
3253 if (netif_msg_intr(tp
))
3254 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
3255 tp
->cp_cmd
&= ~PCIDAC
;
3256 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3257 dev
->features
&= ~NETIF_F_HIGHDMA
;
3260 rtl8169_hw_reset(ioaddr
);
3262 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3265 static void rtl8169_tx_interrupt(struct net_device
*dev
,
3266 struct rtl8169_private
*tp
,
3267 void __iomem
*ioaddr
)
3269 unsigned int dirty_tx
, tx_left
;
3271 dirty_tx
= tp
->dirty_tx
;
3273 tx_left
= tp
->cur_tx
- dirty_tx
;
3275 while (tx_left
> 0) {
3276 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
3277 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3278 u32 len
= tx_skb
->len
;
3282 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
3283 if (status
& DescOwn
)
3286 dev
->stats
.tx_bytes
+= len
;
3287 dev
->stats
.tx_packets
++;
3289 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
3291 if (status
& LastFrag
) {
3292 dev_kfree_skb_irq(tx_skb
->skb
);
3299 if (tp
->dirty_tx
!= dirty_tx
) {
3300 tp
->dirty_tx
= dirty_tx
;
3302 if (netif_queue_stopped(dev
) &&
3303 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
3304 netif_wake_queue(dev
);
3307 * 8168 hack: TxPoll requests are lost when the Tx packets are
3308 * too close. Let's kick an extra TxPoll request when a burst
3309 * of start_xmit activity is detected (if it is not detected,
3310 * it is slow enough). -- FR
3313 if (tp
->cur_tx
!= dirty_tx
)
3314 RTL_W8(TxPoll
, NPQ
);
3318 static inline int rtl8169_fragmented_frame(u32 status
)
3320 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
3323 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
3325 u32 opts1
= le32_to_cpu(desc
->opts1
);
3326 u32 status
= opts1
& RxProtoMask
;
3328 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
3329 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
3330 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
3331 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3333 skb
->ip_summed
= CHECKSUM_NONE
;
3336 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
3337 struct rtl8169_private
*tp
, int pkt_size
,
3340 struct sk_buff
*skb
;
3343 if (pkt_size
>= rx_copybreak
)
3346 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
3350 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
3351 PCI_DMA_FROMDEVICE
);
3352 skb_reserve(skb
, NET_IP_ALIGN
);
3353 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
3360 static int rtl8169_rx_interrupt(struct net_device
*dev
,
3361 struct rtl8169_private
*tp
,
3362 void __iomem
*ioaddr
, u32 budget
)
3364 unsigned int cur_rx
, rx_left
;
3365 unsigned int delta
, count
;
3367 cur_rx
= tp
->cur_rx
;
3368 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
3369 rx_left
= min(rx_left
, budget
);
3371 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
3372 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
3373 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
3377 status
= le32_to_cpu(desc
->opts1
);
3379 if (status
& DescOwn
)
3381 if (unlikely(status
& RxRES
)) {
3382 if (netif_msg_rx_err(tp
)) {
3384 "%s: Rx ERROR. status = %08x\n",
3387 dev
->stats
.rx_errors
++;
3388 if (status
& (RxRWT
| RxRUNT
))
3389 dev
->stats
.rx_length_errors
++;
3391 dev
->stats
.rx_crc_errors
++;
3392 if (status
& RxFOVF
) {
3393 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3394 dev
->stats
.rx_fifo_errors
++;
3396 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3398 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
3399 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
3400 int pkt_size
= (status
& 0x00001FFF) - 4;
3401 struct pci_dev
*pdev
= tp
->pci_dev
;
3404 * The driver does not support incoming fragmented
3405 * frames. They are seen as a symptom of over-mtu
3408 if (unlikely(rtl8169_fragmented_frame(status
))) {
3409 dev
->stats
.rx_dropped
++;
3410 dev
->stats
.rx_length_errors
++;
3411 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3415 rtl8169_rx_csum(skb
, desc
);
3417 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
3418 pci_dma_sync_single_for_device(pdev
, addr
,
3419 pkt_size
, PCI_DMA_FROMDEVICE
);
3420 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3422 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
3423 PCI_DMA_FROMDEVICE
);
3424 tp
->Rx_skbuff
[entry
] = NULL
;
3427 skb_put(skb
, pkt_size
);
3428 skb
->protocol
= eth_type_trans(skb
, dev
);
3430 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
3431 netif_receive_skb(skb
);
3433 dev
->last_rx
= jiffies
;
3434 dev
->stats
.rx_bytes
+= pkt_size
;
3435 dev
->stats
.rx_packets
++;
3438 /* Work around for AMD plateform. */
3439 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
3440 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
3446 count
= cur_rx
- tp
->cur_rx
;
3447 tp
->cur_rx
= cur_rx
;
3449 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
3450 if (!delta
&& count
&& netif_msg_intr(tp
))
3451 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
3452 tp
->dirty_rx
+= delta
;
3455 * FIXME: until there is periodic timer to try and refill the ring,
3456 * a temporary shortage may definitely kill the Rx process.
3457 * - disable the asic to try and avoid an overflow and kick it again
3459 * - how do others driver handle this condition (Uh oh...).
3461 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
3462 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
3467 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
3469 struct net_device
*dev
= dev_instance
;
3470 struct rtl8169_private
*tp
= netdev_priv(dev
);
3471 void __iomem
*ioaddr
= tp
->mmio_addr
;
3475 status
= RTL_R16(IntrStatus
);
3477 /* hotplug/major error/no more work/shared irq */
3478 if ((status
== 0xffff) || !status
)
3483 if (unlikely(!netif_running(dev
))) {
3484 rtl8169_asic_down(ioaddr
);
3488 status
&= tp
->intr_mask
;
3490 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
3492 if (!(status
& tp
->intr_event
))
3495 /* Work around for rx fifo overflow */
3496 if (unlikely(status
& RxFIFOOver
) &&
3497 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
3498 netif_stop_queue(dev
);
3499 rtl8169_tx_timeout(dev
);
3503 if (unlikely(status
& SYSErr
)) {
3504 rtl8169_pcierr_interrupt(dev
);
3508 if (status
& LinkChg
)
3509 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3511 if (status
& tp
->napi_event
) {
3512 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
3513 tp
->intr_mask
= ~tp
->napi_event
;
3515 if (likely(netif_rx_schedule_prep(dev
, &tp
->napi
)))
3516 __netif_rx_schedule(dev
, &tp
->napi
);
3517 else if (netif_msg_intr(tp
)) {
3518 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
3523 return IRQ_RETVAL(handled
);
3526 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
3528 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
3529 struct net_device
*dev
= tp
->dev
;
3530 void __iomem
*ioaddr
= tp
->mmio_addr
;
3533 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
3534 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
3536 if (work_done
< budget
) {
3537 netif_rx_complete(dev
, napi
);
3538 tp
->intr_mask
= 0xffff;
3540 * 20040426: the barrier is not strictly required but the
3541 * behavior of the irq handler could be less predictable
3542 * without it. Btw, the lack of flush for the posted pci
3543 * write is safe - FR
3546 RTL_W16(IntrMask
, tp
->intr_event
);
3552 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
3554 struct rtl8169_private
*tp
= netdev_priv(dev
);
3556 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
3559 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
3560 RTL_W32(RxMissed
, 0);
3563 static void rtl8169_down(struct net_device
*dev
)
3565 struct rtl8169_private
*tp
= netdev_priv(dev
);
3566 void __iomem
*ioaddr
= tp
->mmio_addr
;
3567 unsigned int intrmask
;
3569 rtl8169_delete_timer(dev
);
3571 netif_stop_queue(dev
);
3573 napi_disable(&tp
->napi
);
3576 spin_lock_irq(&tp
->lock
);
3578 rtl8169_asic_down(ioaddr
);
3580 rtl8169_rx_missed(dev
, ioaddr
);
3582 spin_unlock_irq(&tp
->lock
);
3584 synchronize_irq(dev
->irq
);
3586 /* Give a racing hard_start_xmit a few cycles to complete. */
3587 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3590 * And now for the 50k$ question: are IRQ disabled or not ?
3592 * Two paths lead here:
3594 * -> netif_running() is available to sync the current code and the
3595 * IRQ handler. See rtl8169_interrupt for details.
3596 * 2) dev->change_mtu
3597 * -> rtl8169_poll can not be issued again and re-enable the
3598 * interruptions. Let's simply issue the IRQ down sequence again.
3600 * No loop if hotpluged or major error (0xffff).
3602 intrmask
= RTL_R16(IntrMask
);
3603 if (intrmask
&& (intrmask
!= 0xffff))
3606 rtl8169_tx_clear(tp
);
3608 rtl8169_rx_clear(tp
);
3611 static int rtl8169_close(struct net_device
*dev
)
3613 struct rtl8169_private
*tp
= netdev_priv(dev
);
3614 struct pci_dev
*pdev
= tp
->pci_dev
;
3618 free_irq(dev
->irq
, dev
);
3620 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3622 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3624 tp
->TxDescArray
= NULL
;
3625 tp
->RxDescArray
= NULL
;
3630 static void rtl_set_rx_mode(struct net_device
*dev
)
3632 struct rtl8169_private
*tp
= netdev_priv(dev
);
3633 void __iomem
*ioaddr
= tp
->mmio_addr
;
3634 unsigned long flags
;
3635 u32 mc_filter
[2]; /* Multicast hash filter */
3639 if (dev
->flags
& IFF_PROMISC
) {
3640 /* Unconditionally log net taps. */
3641 if (netif_msg_link(tp
)) {
3642 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3646 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3648 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3649 } else if ((dev
->mc_count
> multicast_filter_limit
)
3650 || (dev
->flags
& IFF_ALLMULTI
)) {
3651 /* Too many to filter perfectly -- accept all multicasts. */
3652 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3653 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3655 struct dev_mc_list
*mclist
;
3658 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3659 mc_filter
[1] = mc_filter
[0] = 0;
3660 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3661 i
++, mclist
= mclist
->next
) {
3662 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3663 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3664 rx_mode
|= AcceptMulticast
;
3668 spin_lock_irqsave(&tp
->lock
, flags
);
3670 tmp
= rtl8169_rx_config
| rx_mode
|
3671 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3673 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3674 u32 data
= mc_filter
[0];
3676 mc_filter
[0] = swab32(mc_filter
[1]);
3677 mc_filter
[1] = swab32(data
);
3680 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3681 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3683 RTL_W32(RxConfig
, tmp
);
3685 spin_unlock_irqrestore(&tp
->lock
, flags
);
3689 * rtl8169_get_stats - Get rtl8169 read/write statistics
3690 * @dev: The Ethernet Device to get statistics for
3692 * Get TX/RX statistics for rtl8169
3694 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3696 struct rtl8169_private
*tp
= netdev_priv(dev
);
3697 void __iomem
*ioaddr
= tp
->mmio_addr
;
3698 unsigned long flags
;
3700 if (netif_running(dev
)) {
3701 spin_lock_irqsave(&tp
->lock
, flags
);
3702 rtl8169_rx_missed(dev
, ioaddr
);
3703 spin_unlock_irqrestore(&tp
->lock
, flags
);
3711 static int rtl8169_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3713 struct net_device
*dev
= pci_get_drvdata(pdev
);
3714 struct rtl8169_private
*tp
= netdev_priv(dev
);
3715 void __iomem
*ioaddr
= tp
->mmio_addr
;
3717 if (!netif_running(dev
))
3718 goto out_pci_suspend
;
3720 netif_device_detach(dev
);
3721 netif_stop_queue(dev
);
3723 spin_lock_irq(&tp
->lock
);
3725 rtl8169_asic_down(ioaddr
);
3727 rtl8169_rx_missed(dev
, ioaddr
);
3729 spin_unlock_irq(&tp
->lock
);
3732 pci_save_state(pdev
);
3733 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
),
3734 (tp
->features
& RTL_FEATURE_WOL
) ? 1 : 0);
3735 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3740 static int rtl8169_resume(struct pci_dev
*pdev
)
3742 struct net_device
*dev
= pci_get_drvdata(pdev
);
3744 pci_set_power_state(pdev
, PCI_D0
);
3745 pci_restore_state(pdev
);
3746 pci_enable_wake(pdev
, PCI_D0
, 0);
3748 if (!netif_running(dev
))
3751 netif_device_attach(dev
);
3753 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3758 #endif /* CONFIG_PM */
3760 static struct pci_driver rtl8169_pci_driver
= {
3762 .id_table
= rtl8169_pci_tbl
,
3763 .probe
= rtl8169_init_one
,
3764 .remove
= __devexit_p(rtl8169_remove_one
),
3766 .suspend
= rtl8169_suspend
,
3767 .resume
= rtl8169_resume
,
3771 static int __init
rtl8169_init_module(void)
3773 return pci_register_driver(&rtl8169_pci_driver
);
3776 static void __exit
rtl8169_cleanup_module(void)
3778 pci_unregister_driver(&rtl8169_pci_driver
);
3781 module_init(rtl8169_init_module
);
3782 module_exit(rtl8169_cleanup_module
);