2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
30 #include <asm/system.h>
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define assert(expr) \
47 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
48 #expr,__FILE__,__func__,__LINE__); \
50 #define dprintk(fmt, args...) \
51 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
53 #define assert(expr) do {} while (0)
54 #define dprintk(fmt, args...) do {} while (0)
55 #endif /* RTL8169_DEBUG */
57 #define R8169_MSG_DEFAULT \
58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
60 #define TX_BUFFS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit
= 32;
67 /* MAC address length */
68 #define MAC_ADDR_LEN 6
70 #define MAX_READ_REQUEST_SHIFT 12
71 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77 #define R8169_REGS_SIZE 256
78 #define R8169_NAPI_WEIGHT 64
79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85 #define RTL8169_TX_TIMEOUT (6*HZ)
86 #define RTL8169_PHY_TIMEOUT (10*HZ)
88 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR 0x0000
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg) readb (ioaddr + (reg))
97 #define RTL_R16(reg) readw (ioaddr + (reg))
98 #define RTL_R32(reg) readl (ioaddr + (reg))
101 RTL_GIGA_MAC_NONE
= 0x00,
102 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
103 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
104 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
105 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
106 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
107 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
108 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
109 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
110 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
111 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
112 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
113 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
114 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
115 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
116 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
117 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
118 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
119 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
120 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
121 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
122 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
123 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
124 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
125 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
126 RTL_GIGA_MAC_VER_25
= 0x19, // 8168D
127 RTL_GIGA_MAC_VER_26
= 0x1a, // 8168D
128 RTL_GIGA_MAC_VER_27
= 0x1b, // 8168DP
129 RTL_GIGA_MAC_VER_28
= 0x1c, // 8168DP
130 RTL_GIGA_MAC_VER_29
= 0x1d, // 8105E
131 RTL_GIGA_MAC_VER_30
= 0x1e, // 8105E
132 RTL_GIGA_MAC_VER_31
= 0x1f, // 8168DP
133 RTL_GIGA_MAC_VER_32
= 0x20, // 8168E
134 RTL_GIGA_MAC_VER_33
= 0x21, // 8168E
137 enum rtl_tx_desc_version
{
142 #define _R(NAME,MAC,TD) \
143 { .name = NAME, .mac_version = MAC, .txd_version = TD }
145 static const struct {
148 enum rtl_tx_desc_version txd_version
;
149 } rtl_chip_info
[] = {
150 _R("RTL8169", RTL_GIGA_MAC_VER_01
, RTL_TD_0
), // 8169
151 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, RTL_TD_0
), // 8169S
152 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, RTL_TD_0
), // 8110S
153 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, RTL_TD_0
), // 8169SB
154 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, RTL_TD_0
), // 8110SCd
155 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, RTL_TD_0
), // 8110SCe
156 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, RTL_TD_1
), // PCI-E
157 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, RTL_TD_1
), // PCI-E
158 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, RTL_TD_1
), // PCI-E
159 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, RTL_TD_0
), // PCI-E
160 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, RTL_TD_0
), // PCI-E
161 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, RTL_TD_0
), // PCI-E
162 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, RTL_TD_0
), // PCI-E 8139
163 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, RTL_TD_0
), // PCI-E 8139
164 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, RTL_TD_0
), // PCI-E 8139
165 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, RTL_TD_0
), // PCI-E
166 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, RTL_TD_0
), // PCI-E
167 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, RTL_TD_1
), // PCI-E
168 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, RTL_TD_1
), // PCI-E
169 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, RTL_TD_1
), // PCI-E
170 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, RTL_TD_1
), // PCI-E
171 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, RTL_TD_1
), // PCI-E
172 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, RTL_TD_1
), // PCI-E
173 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, RTL_TD_1
), // PCI-E
174 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, RTL_TD_1
), // PCI-E
175 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26
, RTL_TD_1
), // PCI-E
176 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27
, RTL_TD_1
), // PCI-E
177 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28
, RTL_TD_1
), // PCI-E
178 _R("RTL8105e", RTL_GIGA_MAC_VER_29
, RTL_TD_1
), // PCI-E
179 _R("RTL8105e", RTL_GIGA_MAC_VER_30
, RTL_TD_1
), // PCI-E
180 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31
, RTL_TD_1
), // PCI-E
181 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32
, RTL_TD_1
), // PCI-E
182 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33
, RTL_TD_1
) // PCI-E
186 static const struct rtl_firmware_info
{
189 } rtl_firmware_infos
[] = {
190 { .mac_version
= RTL_GIGA_MAC_VER_25
, .fw_name
= FIRMWARE_8168D_1
},
191 { .mac_version
= RTL_GIGA_MAC_VER_26
, .fw_name
= FIRMWARE_8168D_2
},
192 { .mac_version
= RTL_GIGA_MAC_VER_29
, .fw_name
= FIRMWARE_8105E_1
},
193 { .mac_version
= RTL_GIGA_MAC_VER_30
, .fw_name
= FIRMWARE_8105E_1
},
194 { .mac_version
= RTL_GIGA_MAC_VER_32
, .fw_name
= FIRMWARE_8168E_1
},
195 { .mac_version
= RTL_GIGA_MAC_VER_33
, .fw_name
= FIRMWARE_8168E_2
}
204 static void rtl_hw_start_8169(struct net_device
*);
205 static void rtl_hw_start_8168(struct net_device
*);
206 static void rtl_hw_start_8101(struct net_device
*);
208 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
209 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
210 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
214 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
215 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
216 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
217 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
218 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
220 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
224 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
226 static int rx_buf_sz
= 16383;
233 MAC0
= 0, /* Ethernet hardware address. */
235 MAR0
= 8, /* Multicast filter. */
236 CounterAddrLow
= 0x10,
237 CounterAddrHigh
= 0x14,
238 TxDescStartAddrLow
= 0x20,
239 TxDescStartAddrHigh
= 0x24,
240 TxHDescStartAddrLow
= 0x28,
241 TxHDescStartAddrHigh
= 0x2c,
251 #define RTL_RX_CONFIG_MASK 0xff7e1880u
267 RxDescAddrLow
= 0xe4,
268 RxDescAddrHigh
= 0xe8,
269 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
271 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
273 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
275 #define TxPacketMax (8064 >> 7)
278 FuncEventMask
= 0xf4,
279 FuncPresetState
= 0xf8,
280 FuncForceEvent
= 0xfc,
283 enum rtl8110_registers
{
289 enum rtl8168_8101_registers
{
292 #define CSIAR_FLAG 0x80000000
293 #define CSIAR_WRITE_CMD 0x80000000
294 #define CSIAR_BYTE_ENABLE 0x0f
295 #define CSIAR_BYTE_ENABLE_SHIFT 12
296 #define CSIAR_ADDR_MASK 0x0fff
299 #define EPHYAR_FLAG 0x80000000
300 #define EPHYAR_WRITE_CMD 0x80000000
301 #define EPHYAR_REG_MASK 0x1f
302 #define EPHYAR_REG_SHIFT 16
303 #define EPHYAR_DATA_MASK 0xffff
305 #define PM_SWITCH (1 << 6)
307 #define FIX_NAK_1 (1 << 4)
308 #define FIX_NAK_2 (1 << 3)
311 #define EN_NDP (1 << 3)
312 #define EN_OOB_RESET (1 << 2)
314 #define EFUSEAR_FLAG 0x80000000
315 #define EFUSEAR_WRITE_CMD 0x80000000
316 #define EFUSEAR_READ_CMD 0x00000000
317 #define EFUSEAR_REG_MASK 0x03ff
318 #define EFUSEAR_REG_SHIFT 8
319 #define EFUSEAR_DATA_MASK 0xff
322 enum rtl8168_registers
{
325 #define ERIAR_FLAG 0x80000000
326 #define ERIAR_WRITE_CMD 0x80000000
327 #define ERIAR_READ_CMD 0x00000000
328 #define ERIAR_ADDR_BYTE_ALIGN 4
329 #define ERIAR_EXGMAC 0
332 #define ERIAR_TYPE_SHIFT 16
333 #define ERIAR_BYTEEN 0x0f
334 #define ERIAR_BYTEEN_SHIFT 12
335 EPHY_RXER_NUM
= 0x7c,
336 OCPDR
= 0xb0, /* OCP GPHY access */
337 #define OCPDR_WRITE_CMD 0x80000000
338 #define OCPDR_READ_CMD 0x00000000
339 #define OCPDR_REG_MASK 0x7f
340 #define OCPDR_GPHY_REG_SHIFT 16
341 #define OCPDR_DATA_MASK 0xffff
343 #define OCPAR_FLAG 0x80000000
344 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
345 #define OCPAR_GPHY_READ_CMD 0x0000f060
346 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
347 MISC
= 0xf0, /* 8168e only. */
348 txpla_rst
= (1 << 29)
351 enum rtl_register_content
{
352 /* InterruptStatusBits */
356 TxDescUnavail
= 0x0080,
378 /* TXPoll register p.5 */
379 HPQ
= 0x80, /* Poll cmd on the high prio queue */
380 NPQ
= 0x40, /* Poll cmd on the low prio queue */
381 FSWInt
= 0x01, /* Forced software interrupt */
385 Cfg9346_Unlock
= 0xc0,
390 AcceptBroadcast
= 0x08,
391 AcceptMulticast
= 0x04,
393 AcceptAllPhys
= 0x01,
400 TxInterFrameGapShift
= 24,
401 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
403 /* Config1 register p.24 */
406 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
407 Speed_down
= (1 << 4),
411 PMEnable
= (1 << 0), /* Power Management Enable */
413 /* Config2 register p. 25 */
414 PCI_Clock_66MHz
= 0x01,
415 PCI_Clock_33MHz
= 0x00,
417 /* Config3 register p.25 */
418 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
419 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
420 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
422 /* Config5 register p.27 */
423 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
424 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
425 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
427 LanWake
= (1 << 1), /* LanWake enable/disable */
428 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
431 TBIReset
= 0x80000000,
432 TBILoopback
= 0x40000000,
433 TBINwEnable
= 0x20000000,
434 TBINwRestart
= 0x10000000,
435 TBILinkOk
= 0x02000000,
436 TBINwComplete
= 0x01000000,
439 EnableBist
= (1 << 15), // 8168 8101
440 Mac_dbgo_oe
= (1 << 14), // 8168 8101
441 Normal_mode
= (1 << 13), // unused
442 Force_half_dup
= (1 << 12), // 8168 8101
443 Force_rxflow_en
= (1 << 11), // 8168 8101
444 Force_txflow_en
= (1 << 10), // 8168 8101
445 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
446 ASF
= (1 << 8), // 8168 8101
447 PktCntrDisable
= (1 << 7), // 8168 8101
448 Mac_dbgo_sel
= 0x001c, // 8168
453 INTT_0
= 0x0000, // 8168
454 INTT_1
= 0x0001, // 8168
455 INTT_2
= 0x0002, // 8168
456 INTT_3
= 0x0003, // 8168
458 /* rtl8169_PHYstatus */
469 TBILinkOK
= 0x02000000,
471 /* DumpCounterCommand */
476 /* First doubleword. */
477 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
478 RingEnd
= (1 << 30), /* End of descriptor ring */
479 FirstFrag
= (1 << 29), /* First segment of a packet */
480 LastFrag
= (1 << 28), /* Final segment of a packet */
484 enum rtl_tx_desc_bit
{
485 /* First doubleword. */
486 TD_LSO
= (1 << 27), /* Large Send Offload */
487 #define TD_MSS_MAX 0x07ffu /* MSS value */
489 /* Second doubleword. */
490 TxVlanTag
= (1 << 17), /* Add VLAN tag */
493 /* 8169, 8168b and 810x except 8102e. */
494 enum rtl_tx_desc_bit_0
{
495 /* First doubleword. */
496 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
497 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
498 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
499 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
502 /* 8102e, 8168c and beyond. */
503 enum rtl_tx_desc_bit_1
{
504 /* Second doubleword. */
505 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
506 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
507 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
508 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
511 static const struct rtl_tx_desc_info
{
518 } tx_desc_info
[] = {
521 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
522 .tcp
= TD0_IP_CS
| TD0_TCP_CS
524 .mss_shift
= TD0_MSS_SHIFT
,
529 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
530 .tcp
= TD1_IP_CS
| TD1_TCP_CS
532 .mss_shift
= TD1_MSS_SHIFT
,
537 enum rtl_rx_desc_bit
{
539 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
540 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
542 #define RxProtoUDP (PID1)
543 #define RxProtoTCP (PID0)
544 #define RxProtoIP (PID1 | PID0)
545 #define RxProtoMask RxProtoIP
547 IPFail
= (1 << 16), /* IP checksum failed */
548 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
549 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
550 RxVlanTag
= (1 << 16), /* VLAN tag available */
553 #define RsvdMask 0x3fffc000
570 u8 __pad
[sizeof(void *) - sizeof(u32
)];
574 RTL_FEATURE_WOL
= (1 << 0),
575 RTL_FEATURE_MSI
= (1 << 1),
576 RTL_FEATURE_GMII
= (1 << 2),
579 struct rtl8169_counters
{
586 __le32 tx_one_collision
;
587 __le32 tx_multi_collision
;
595 struct rtl8169_private
{
596 void __iomem
*mmio_addr
; /* memory map physical address */
597 struct pci_dev
*pci_dev
; /* Index of PCI device */
598 struct net_device
*dev
;
599 struct napi_struct napi
;
600 spinlock_t lock
; /* spin lock flag */
604 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
605 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
608 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
609 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
610 dma_addr_t TxPhyAddr
;
611 dma_addr_t RxPhyAddr
;
612 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
613 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
614 struct timer_list timer
;
619 int phy_1000_ctrl_reg
;
622 void (*write
)(void __iomem
*, int, int);
623 int (*read
)(void __iomem
*, int);
626 struct pll_power_ops
{
627 void (*down
)(struct rtl8169_private
*);
628 void (*up
)(struct rtl8169_private
*);
631 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
632 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
633 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
634 void (*hw_start
)(struct net_device
*);
635 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
636 unsigned int (*link_ok
)(void __iomem
*);
637 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
639 struct delayed_work task
;
642 struct mii_if_info mii
;
643 struct rtl8169_counters counters
;
646 const struct firmware
*fw
;
647 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
650 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
651 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
652 module_param(use_dac
, int, 0);
653 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
654 module_param_named(debug
, debug
.msg_enable
, int, 0);
655 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
656 MODULE_LICENSE("GPL");
657 MODULE_VERSION(RTL8169_VERSION
);
658 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
659 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
660 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
661 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
662 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
664 static int rtl8169_open(struct net_device
*dev
);
665 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
666 struct net_device
*dev
);
667 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
668 static int rtl8169_init_ring(struct net_device
*dev
);
669 static void rtl_hw_start(struct net_device
*dev
);
670 static int rtl8169_close(struct net_device
*dev
);
671 static void rtl_set_rx_mode(struct net_device
*dev
);
672 static void rtl8169_tx_timeout(struct net_device
*dev
);
673 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
674 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
675 void __iomem
*, u32 budget
);
676 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
677 static void rtl8169_down(struct net_device
*dev
);
678 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
679 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
681 static const unsigned int rtl8169_rx_config
=
682 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
684 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
686 void __iomem
*ioaddr
= tp
->mmio_addr
;
689 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
690 for (i
= 0; i
< 20; i
++) {
692 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
695 return RTL_R32(OCPDR
);
698 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
700 void __iomem
*ioaddr
= tp
->mmio_addr
;
703 RTL_W32(OCPDR
, data
);
704 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
705 for (i
= 0; i
< 20; i
++) {
707 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
712 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
714 void __iomem
*ioaddr
= tp
->mmio_addr
;
718 RTL_W32(ERIAR
, 0x800010e8);
720 for (i
= 0; i
< 5; i
++) {
722 if (!(RTL_R32(ERIDR
) & ERIAR_FLAG
))
726 ocp_write(tp
, 0x1, 0x30, 0x00000001);
729 #define OOB_CMD_RESET 0x00
730 #define OOB_CMD_DRIVER_START 0x05
731 #define OOB_CMD_DRIVER_STOP 0x06
733 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
738 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
740 if (tp
->mac_version
== RTL_GIGA_MAC_VER_31
)
745 for (i
= 0; i
< 10; i
++) {
747 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
752 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
757 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
759 if (tp
->mac_version
== RTL_GIGA_MAC_VER_31
)
764 for (i
= 0; i
< 10; i
++) {
766 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
771 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
775 if (tp
->mac_version
== RTL_GIGA_MAC_VER_31
)
780 if (ocp_read(tp
, 0xF, reg
) & 0x00008000)
786 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
790 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
792 for (i
= 20; i
> 0; i
--) {
794 * Check if the RTL8169 has completed writing to the specified
797 if (!(RTL_R32(PHYAR
) & 0x80000000))
802 * According to hardware specs a 20us delay is required after write
803 * complete indication, but before sending next command.
808 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
812 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
814 for (i
= 20; i
> 0; i
--) {
816 * Check if the RTL8169 has completed retrieving data from
817 * the specified MII register.
819 if (RTL_R32(PHYAR
) & 0x80000000) {
820 value
= RTL_R32(PHYAR
) & 0xffff;
826 * According to hardware specs a 20us delay is required after read
827 * complete indication, but before sending next command.
834 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
838 RTL_W32(OCPDR
, data
|
839 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
840 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
841 RTL_W32(EPHY_RXER_NUM
, 0);
843 for (i
= 0; i
< 100; i
++) {
845 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
850 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
852 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
853 (value
& OCPDR_DATA_MASK
));
856 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
860 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
863 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
864 RTL_W32(EPHY_RXER_NUM
, 0);
866 for (i
= 0; i
< 100; i
++) {
868 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
872 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
875 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
877 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
879 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
882 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
884 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
887 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
889 r8168dp_2_mdio_start(ioaddr
);
891 r8169_mdio_write(ioaddr
, reg_addr
, value
);
893 r8168dp_2_mdio_stop(ioaddr
);
896 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
900 r8168dp_2_mdio_start(ioaddr
);
902 value
= r8169_mdio_read(ioaddr
, reg_addr
);
904 r8168dp_2_mdio_stop(ioaddr
);
909 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
911 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
914 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
916 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
919 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
921 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
924 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
928 val
= rtl_readphy(tp
, reg_addr
);
929 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
932 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
935 struct rtl8169_private
*tp
= netdev_priv(dev
);
937 rtl_writephy(tp
, location
, val
);
940 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
942 struct rtl8169_private
*tp
= netdev_priv(dev
);
944 return rtl_readphy(tp
, location
);
947 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
951 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
952 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
954 for (i
= 0; i
< 100; i
++) {
955 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
961 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
966 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
968 for (i
= 0; i
< 100; i
++) {
969 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
970 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
979 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
983 RTL_W32(CSIDR
, value
);
984 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
985 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
987 for (i
= 0; i
< 100; i
++) {
988 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
994 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
999 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1000 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1002 for (i
= 0; i
< 100; i
++) {
1003 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1004 value
= RTL_R32(CSIDR
);
1013 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1018 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1020 for (i
= 0; i
< 300; i
++) {
1021 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1022 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1031 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
1033 RTL_W16(IntrMask
, 0x0000);
1035 RTL_W16(IntrStatus
, 0xffff);
1038 static void rtl8169_asic_down(void __iomem
*ioaddr
)
1040 RTL_W8(ChipCmd
, 0x00);
1041 rtl8169_irq_mask_and_ack(ioaddr
);
1045 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1047 void __iomem
*ioaddr
= tp
->mmio_addr
;
1049 return RTL_R32(TBICSR
) & TBIReset
;
1052 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1054 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1057 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1059 return RTL_R32(TBICSR
) & TBILinkOk
;
1062 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1064 return RTL_R8(PHYstatus
) & LinkStatus
;
1067 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1069 void __iomem
*ioaddr
= tp
->mmio_addr
;
1071 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1074 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1078 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1079 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1082 static void __rtl8169_check_link_status(struct net_device
*dev
,
1083 struct rtl8169_private
*tp
,
1084 void __iomem
*ioaddr
,
1087 unsigned long flags
;
1089 spin_lock_irqsave(&tp
->lock
, flags
);
1090 if (tp
->link_ok(ioaddr
)) {
1091 /* This is to cancel a scheduled suspend if there's one. */
1093 pm_request_resume(&tp
->pci_dev
->dev
);
1094 netif_carrier_on(dev
);
1095 if (net_ratelimit())
1096 netif_info(tp
, ifup
, dev
, "link up\n");
1098 netif_carrier_off(dev
);
1099 netif_info(tp
, ifdown
, dev
, "link down\n");
1101 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
1103 spin_unlock_irqrestore(&tp
->lock
, flags
);
1106 static void rtl8169_check_link_status(struct net_device
*dev
,
1107 struct rtl8169_private
*tp
,
1108 void __iomem
*ioaddr
)
1110 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1113 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1115 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1117 void __iomem
*ioaddr
= tp
->mmio_addr
;
1121 options
= RTL_R8(Config1
);
1122 if (!(options
& PMEnable
))
1125 options
= RTL_R8(Config3
);
1126 if (options
& LinkUp
)
1127 wolopts
|= WAKE_PHY
;
1128 if (options
& MagicPacket
)
1129 wolopts
|= WAKE_MAGIC
;
1131 options
= RTL_R8(Config5
);
1133 wolopts
|= WAKE_UCAST
;
1135 wolopts
|= WAKE_BCAST
;
1137 wolopts
|= WAKE_MCAST
;
1142 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1144 struct rtl8169_private
*tp
= netdev_priv(dev
);
1146 spin_lock_irq(&tp
->lock
);
1148 wol
->supported
= WAKE_ANY
;
1149 wol
->wolopts
= __rtl8169_get_wol(tp
);
1151 spin_unlock_irq(&tp
->lock
);
1154 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1156 void __iomem
*ioaddr
= tp
->mmio_addr
;
1158 static const struct {
1163 { WAKE_ANY
, Config1
, PMEnable
},
1164 { WAKE_PHY
, Config3
, LinkUp
},
1165 { WAKE_MAGIC
, Config3
, MagicPacket
},
1166 { WAKE_UCAST
, Config5
, UWF
},
1167 { WAKE_BCAST
, Config5
, BWF
},
1168 { WAKE_MCAST
, Config5
, MWF
},
1169 { WAKE_ANY
, Config5
, LanWake
}
1172 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1174 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1175 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1176 if (wolopts
& cfg
[i
].opt
)
1177 options
|= cfg
[i
].mask
;
1178 RTL_W8(cfg
[i
].reg
, options
);
1181 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1184 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1186 struct rtl8169_private
*tp
= netdev_priv(dev
);
1188 spin_lock_irq(&tp
->lock
);
1191 tp
->features
|= RTL_FEATURE_WOL
;
1193 tp
->features
&= ~RTL_FEATURE_WOL
;
1194 __rtl8169_set_wol(tp
, wol
->wolopts
);
1195 spin_unlock_irq(&tp
->lock
);
1197 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1202 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1203 struct ethtool_drvinfo
*info
)
1205 struct rtl8169_private
*tp
= netdev_priv(dev
);
1207 strcpy(info
->driver
, MODULENAME
);
1208 strcpy(info
->version
, RTL8169_VERSION
);
1209 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1212 static int rtl8169_get_regs_len(struct net_device
*dev
)
1214 return R8169_REGS_SIZE
;
1217 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1218 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1220 struct rtl8169_private
*tp
= netdev_priv(dev
);
1221 void __iomem
*ioaddr
= tp
->mmio_addr
;
1225 reg
= RTL_R32(TBICSR
);
1226 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1227 (duplex
== DUPLEX_FULL
)) {
1228 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1229 } else if (autoneg
== AUTONEG_ENABLE
)
1230 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1232 netif_warn(tp
, link
, dev
,
1233 "incorrect speed setting refused in TBI mode\n");
1240 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1241 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1243 struct rtl8169_private
*tp
= netdev_priv(dev
);
1244 int giga_ctrl
, bmcr
;
1247 rtl_writephy(tp
, 0x1f, 0x0000);
1249 if (autoneg
== AUTONEG_ENABLE
) {
1252 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1253 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1254 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1256 if (adv
& ADVERTISED_10baseT_Half
)
1257 auto_nego
|= ADVERTISE_10HALF
;
1258 if (adv
& ADVERTISED_10baseT_Full
)
1259 auto_nego
|= ADVERTISE_10FULL
;
1260 if (adv
& ADVERTISED_100baseT_Half
)
1261 auto_nego
|= ADVERTISE_100HALF
;
1262 if (adv
& ADVERTISED_100baseT_Full
)
1263 auto_nego
|= ADVERTISE_100FULL
;
1265 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1267 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1268 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1270 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1271 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
1272 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
1273 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
1274 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
1275 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
1276 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
1277 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
1278 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
) &&
1279 (tp
->mac_version
!= RTL_GIGA_MAC_VER_29
) &&
1280 (tp
->mac_version
!= RTL_GIGA_MAC_VER_30
)) {
1281 if (adv
& ADVERTISED_1000baseT_Half
)
1282 giga_ctrl
|= ADVERTISE_1000HALF
;
1283 if (adv
& ADVERTISED_1000baseT_Full
)
1284 giga_ctrl
|= ADVERTISE_1000FULL
;
1285 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1286 ADVERTISED_1000baseT_Full
)) {
1287 netif_info(tp
, link
, dev
,
1288 "PHY does not support 1000Mbps\n");
1292 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1294 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1295 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1299 if (speed
== SPEED_10
)
1301 else if (speed
== SPEED_100
)
1302 bmcr
= BMCR_SPEED100
;
1306 if (duplex
== DUPLEX_FULL
)
1307 bmcr
|= BMCR_FULLDPLX
;
1310 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
1312 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1314 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
1315 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
1316 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1317 rtl_writephy(tp
, 0x17, 0x2138);
1318 rtl_writephy(tp
, 0x0e, 0x0260);
1320 rtl_writephy(tp
, 0x17, 0x2108);
1321 rtl_writephy(tp
, 0x0e, 0x0000);
1330 static int rtl8169_set_speed(struct net_device
*dev
,
1331 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1333 struct rtl8169_private
*tp
= netdev_priv(dev
);
1336 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1338 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1339 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1344 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1346 struct rtl8169_private
*tp
= netdev_priv(dev
);
1347 unsigned long flags
;
1350 spin_lock_irqsave(&tp
->lock
, flags
);
1351 ret
= rtl8169_set_speed(dev
,
1352 cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1353 cmd
->duplex
, cmd
->advertising
);
1354 spin_unlock_irqrestore(&tp
->lock
, flags
);
1359 static u32
rtl8169_fix_features(struct net_device
*dev
, u32 features
)
1361 if (dev
->mtu
> TD_MSS_MAX
)
1362 features
&= ~NETIF_F_ALL_TSO
;
1367 static int rtl8169_set_features(struct net_device
*dev
, u32 features
)
1369 struct rtl8169_private
*tp
= netdev_priv(dev
);
1370 void __iomem
*ioaddr
= tp
->mmio_addr
;
1371 unsigned long flags
;
1373 spin_lock_irqsave(&tp
->lock
, flags
);
1375 if (features
& NETIF_F_RXCSUM
)
1376 tp
->cp_cmd
|= RxChkSum
;
1378 tp
->cp_cmd
&= ~RxChkSum
;
1380 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1381 tp
->cp_cmd
|= RxVlan
;
1383 tp
->cp_cmd
&= ~RxVlan
;
1385 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1388 spin_unlock_irqrestore(&tp
->lock
, flags
);
1393 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1394 struct sk_buff
*skb
)
1396 return (vlan_tx_tag_present(skb
)) ?
1397 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1400 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1402 u32 opts2
= le32_to_cpu(desc
->opts2
);
1404 if (opts2
& RxVlanTag
)
1405 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1410 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1412 struct rtl8169_private
*tp
= netdev_priv(dev
);
1413 void __iomem
*ioaddr
= tp
->mmio_addr
;
1417 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1418 cmd
->port
= PORT_FIBRE
;
1419 cmd
->transceiver
= XCVR_INTERNAL
;
1421 status
= RTL_R32(TBICSR
);
1422 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1423 cmd
->autoneg
= !!(status
& TBINwEnable
);
1425 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1426 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1431 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1433 struct rtl8169_private
*tp
= netdev_priv(dev
);
1435 return mii_ethtool_gset(&tp
->mii
, cmd
);
1438 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1440 struct rtl8169_private
*tp
= netdev_priv(dev
);
1441 unsigned long flags
;
1444 spin_lock_irqsave(&tp
->lock
, flags
);
1446 rc
= tp
->get_settings(dev
, cmd
);
1448 spin_unlock_irqrestore(&tp
->lock
, flags
);
1452 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1455 struct rtl8169_private
*tp
= netdev_priv(dev
);
1456 unsigned long flags
;
1458 if (regs
->len
> R8169_REGS_SIZE
)
1459 regs
->len
= R8169_REGS_SIZE
;
1461 spin_lock_irqsave(&tp
->lock
, flags
);
1462 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1463 spin_unlock_irqrestore(&tp
->lock
, flags
);
1466 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1468 struct rtl8169_private
*tp
= netdev_priv(dev
);
1470 return tp
->msg_enable
;
1473 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1475 struct rtl8169_private
*tp
= netdev_priv(dev
);
1477 tp
->msg_enable
= value
;
1480 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1487 "tx_single_collisions",
1488 "tx_multi_collisions",
1496 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1500 return ARRAY_SIZE(rtl8169_gstrings
);
1506 static void rtl8169_update_counters(struct net_device
*dev
)
1508 struct rtl8169_private
*tp
= netdev_priv(dev
);
1509 void __iomem
*ioaddr
= tp
->mmio_addr
;
1510 struct rtl8169_counters
*counters
;
1514 struct device
*d
= &tp
->pci_dev
->dev
;
1517 * Some chips are unable to dump tally counters when the receiver
1520 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1523 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1527 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1528 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1529 RTL_W32(CounterAddrLow
, cmd
);
1530 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1533 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1534 /* copy updated counters */
1535 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1541 RTL_W32(CounterAddrLow
, 0);
1542 RTL_W32(CounterAddrHigh
, 0);
1544 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1547 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1548 struct ethtool_stats
*stats
, u64
*data
)
1550 struct rtl8169_private
*tp
= netdev_priv(dev
);
1554 rtl8169_update_counters(dev
);
1556 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1557 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1558 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1559 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1560 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1561 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1562 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1563 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1564 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1565 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1566 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1567 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1568 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1571 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1575 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1580 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1581 .get_drvinfo
= rtl8169_get_drvinfo
,
1582 .get_regs_len
= rtl8169_get_regs_len
,
1583 .get_link
= ethtool_op_get_link
,
1584 .get_settings
= rtl8169_get_settings
,
1585 .set_settings
= rtl8169_set_settings
,
1586 .get_msglevel
= rtl8169_get_msglevel
,
1587 .set_msglevel
= rtl8169_set_msglevel
,
1588 .get_regs
= rtl8169_get_regs
,
1589 .get_wol
= rtl8169_get_wol
,
1590 .set_wol
= rtl8169_set_wol
,
1591 .get_strings
= rtl8169_get_strings
,
1592 .get_sset_count
= rtl8169_get_sset_count
,
1593 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1596 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1597 void __iomem
*ioaddr
)
1600 * The driver currently handles the 8168Bf and the 8168Be identically
1601 * but they can be identified more specifically through the test below
1604 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1606 * Same thing for the 8101Eb and the 8101Ec:
1608 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1610 static const struct {
1616 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1617 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1618 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1621 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1622 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1623 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1625 /* 8168DP family. */
1626 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1627 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1628 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1631 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1632 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1633 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1634 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1635 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1636 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1637 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1638 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1639 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1642 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1643 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1644 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1645 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1648 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1649 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1650 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1651 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1652 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1653 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1654 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1655 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1656 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1657 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1658 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1659 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1660 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1661 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1662 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1663 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1664 /* FIXME: where did these entries come from ? -- FR */
1665 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1666 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1669 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1670 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1671 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1672 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1673 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1674 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1677 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1681 reg
= RTL_R32(TxConfig
);
1682 while ((reg
& p
->mask
) != p
->val
)
1684 tp
->mac_version
= p
->mac_version
;
1687 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1689 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1697 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1698 const struct phy_reg
*regs
, int len
)
1701 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1706 #define PHY_READ 0x00000000
1707 #define PHY_DATA_OR 0x10000000
1708 #define PHY_DATA_AND 0x20000000
1709 #define PHY_BJMPN 0x30000000
1710 #define PHY_READ_EFUSE 0x40000000
1711 #define PHY_READ_MAC_BYTE 0x50000000
1712 #define PHY_WRITE_MAC_BYTE 0x60000000
1713 #define PHY_CLEAR_READCOUNT 0x70000000
1714 #define PHY_WRITE 0x80000000
1715 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1716 #define PHY_COMP_EQ_SKIPN 0xa0000000
1717 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1718 #define PHY_WRITE_PREVIOUS 0xc0000000
1719 #define PHY_SKIPN 0xd0000000
1720 #define PHY_DELAY_MS 0xe0000000
1721 #define PHY_WRITE_ERI_WORD 0xf0000000
1724 rtl_phy_write_fw(struct rtl8169_private
*tp
, const struct firmware
*fw
)
1726 __le32
*phytable
= (__le32
*)fw
->data
;
1727 struct net_device
*dev
= tp
->dev
;
1728 size_t index
, fw_size
= fw
->size
/ sizeof(*phytable
);
1731 if (fw
->size
% sizeof(*phytable
)) {
1732 netif_err(tp
, probe
, dev
, "odd sized firmware %zd\n", fw
->size
);
1736 for (index
= 0; index
< fw_size
; index
++) {
1737 u32 action
= le32_to_cpu(phytable
[index
]);
1738 u32 regno
= (action
& 0x0fff0000) >> 16;
1740 switch(action
& 0xf0000000) {
1744 case PHY_READ_EFUSE
:
1745 case PHY_CLEAR_READCOUNT
:
1747 case PHY_WRITE_PREVIOUS
:
1752 if (regno
> index
) {
1753 netif_err(tp
, probe
, tp
->dev
,
1754 "Out of range of firmware\n");
1758 case PHY_READCOUNT_EQ_SKIP
:
1759 if (index
+ 2 >= fw_size
) {
1760 netif_err(tp
, probe
, tp
->dev
,
1761 "Out of range of firmware\n");
1765 case PHY_COMP_EQ_SKIPN
:
1766 case PHY_COMP_NEQ_SKIPN
:
1768 if (index
+ 1 + regno
>= fw_size
) {
1769 netif_err(tp
, probe
, tp
->dev
,
1770 "Out of range of firmware\n");
1775 case PHY_READ_MAC_BYTE
:
1776 case PHY_WRITE_MAC_BYTE
:
1777 case PHY_WRITE_ERI_WORD
:
1779 netif_err(tp
, probe
, tp
->dev
,
1780 "Invalid action 0x%08x\n", action
);
1788 for (index
= 0; index
< fw_size
; ) {
1789 u32 action
= le32_to_cpu(phytable
[index
]);
1790 u32 data
= action
& 0x0000ffff;
1791 u32 regno
= (action
& 0x0fff0000) >> 16;
1796 switch(action
& 0xf0000000) {
1798 predata
= rtl_readphy(tp
, regno
);
1813 case PHY_READ_EFUSE
:
1814 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
1817 case PHY_CLEAR_READCOUNT
:
1822 rtl_writephy(tp
, regno
, data
);
1825 case PHY_READCOUNT_EQ_SKIP
:
1831 case PHY_COMP_EQ_SKIPN
:
1832 if (predata
== data
)
1836 case PHY_COMP_NEQ_SKIPN
:
1837 if (predata
!= data
)
1841 case PHY_WRITE_PREVIOUS
:
1842 rtl_writephy(tp
, regno
, predata
);
1853 case PHY_READ_MAC_BYTE
:
1854 case PHY_WRITE_MAC_BYTE
:
1855 case PHY_WRITE_ERI_WORD
:
1862 static void rtl_release_firmware(struct rtl8169_private
*tp
)
1864 if (!IS_ERR_OR_NULL(tp
->fw
))
1865 release_firmware(tp
->fw
);
1866 tp
->fw
= RTL_FIRMWARE_UNKNOWN
;
1869 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
1871 const struct firmware
*fw
= tp
->fw
;
1873 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1874 if (!IS_ERR_OR_NULL(fw
))
1875 rtl_phy_write_fw(tp
, fw
);
1878 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
1880 if (rtl_readphy(tp
, reg
) != val
)
1881 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
1883 rtl_apply_firmware(tp
);
1886 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
1888 static const struct phy_reg phy_reg_init
[] = {
1950 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1953 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
1955 static const struct phy_reg phy_reg_init
[] = {
1961 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1964 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
1966 struct pci_dev
*pdev
= tp
->pci_dev
;
1967 u16 vendor_id
, device_id
;
1969 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1970 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1972 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1975 rtl_writephy(tp
, 0x1f, 0x0001);
1976 rtl_writephy(tp
, 0x10, 0xf01b);
1977 rtl_writephy(tp
, 0x1f, 0x0000);
1980 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
1982 static const struct phy_reg phy_reg_init
[] = {
2022 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2024 rtl8169scd_hw_phy_config_quirk(tp
);
2027 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2029 static const struct phy_reg phy_reg_init
[] = {
2077 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2080 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2082 static const struct phy_reg phy_reg_init
[] = {
2087 rtl_writephy(tp
, 0x1f, 0x0001);
2088 rtl_patchphy(tp
, 0x16, 1 << 0);
2090 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2093 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2095 static const struct phy_reg phy_reg_init
[] = {
2101 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2104 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2106 static const struct phy_reg phy_reg_init
[] = {
2114 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2117 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2119 static const struct phy_reg phy_reg_init
[] = {
2125 rtl_writephy(tp
, 0x1f, 0x0000);
2126 rtl_patchphy(tp
, 0x14, 1 << 5);
2127 rtl_patchphy(tp
, 0x0d, 1 << 5);
2129 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2132 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2134 static const struct phy_reg phy_reg_init
[] = {
2154 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2156 rtl_patchphy(tp
, 0x14, 1 << 5);
2157 rtl_patchphy(tp
, 0x0d, 1 << 5);
2158 rtl_writephy(tp
, 0x1f, 0x0000);
2161 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2163 static const struct phy_reg phy_reg_init
[] = {
2181 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2183 rtl_patchphy(tp
, 0x16, 1 << 0);
2184 rtl_patchphy(tp
, 0x14, 1 << 5);
2185 rtl_patchphy(tp
, 0x0d, 1 << 5);
2186 rtl_writephy(tp
, 0x1f, 0x0000);
2189 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2191 static const struct phy_reg phy_reg_init
[] = {
2203 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2205 rtl_patchphy(tp
, 0x16, 1 << 0);
2206 rtl_patchphy(tp
, 0x14, 1 << 5);
2207 rtl_patchphy(tp
, 0x0d, 1 << 5);
2208 rtl_writephy(tp
, 0x1f, 0x0000);
2211 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2213 rtl8168c_3_hw_phy_config(tp
);
2216 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2218 static const struct phy_reg phy_reg_init_0
[] = {
2219 /* Channel Estimation */
2240 * enhance line driver power
2249 * Can not link to 1Gbps with bad cable
2250 * Decrease SNR threshold form 21.07dB to 19.04dB
2258 void __iomem
*ioaddr
= tp
->mmio_addr
;
2260 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2264 * Fine Tune Switching regulator parameter
2266 rtl_writephy(tp
, 0x1f, 0x0002);
2267 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2268 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2270 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2271 static const struct phy_reg phy_reg_init
[] = {
2281 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2283 val
= rtl_readphy(tp
, 0x0d);
2285 if ((val
& 0x00ff) != 0x006c) {
2286 static const u32 set
[] = {
2287 0x0065, 0x0066, 0x0067, 0x0068,
2288 0x0069, 0x006a, 0x006b, 0x006c
2292 rtl_writephy(tp
, 0x1f, 0x0002);
2295 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2296 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2299 static const struct phy_reg phy_reg_init
[] = {
2307 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2310 /* RSET couple improve */
2311 rtl_writephy(tp
, 0x1f, 0x0002);
2312 rtl_patchphy(tp
, 0x0d, 0x0300);
2313 rtl_patchphy(tp
, 0x0f, 0x0010);
2315 /* Fine tune PLL performance */
2316 rtl_writephy(tp
, 0x1f, 0x0002);
2317 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2318 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2320 rtl_writephy(tp
, 0x1f, 0x0005);
2321 rtl_writephy(tp
, 0x05, 0x001b);
2323 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2325 rtl_writephy(tp
, 0x1f, 0x0000);
2328 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2330 static const struct phy_reg phy_reg_init_0
[] = {
2331 /* Channel Estimation */
2352 * enhance line driver power
2361 * Can not link to 1Gbps with bad cable
2362 * Decrease SNR threshold form 21.07dB to 19.04dB
2370 void __iomem
*ioaddr
= tp
->mmio_addr
;
2372 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2374 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2375 static const struct phy_reg phy_reg_init
[] = {
2386 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2388 val
= rtl_readphy(tp
, 0x0d);
2389 if ((val
& 0x00ff) != 0x006c) {
2390 static const u32 set
[] = {
2391 0x0065, 0x0066, 0x0067, 0x0068,
2392 0x0069, 0x006a, 0x006b, 0x006c
2396 rtl_writephy(tp
, 0x1f, 0x0002);
2399 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2400 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2403 static const struct phy_reg phy_reg_init
[] = {
2411 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2414 /* Fine tune PLL performance */
2415 rtl_writephy(tp
, 0x1f, 0x0002);
2416 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2417 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2419 /* Switching regulator Slew rate */
2420 rtl_writephy(tp
, 0x1f, 0x0002);
2421 rtl_patchphy(tp
, 0x0f, 0x0017);
2423 rtl_writephy(tp
, 0x1f, 0x0005);
2424 rtl_writephy(tp
, 0x05, 0x001b);
2426 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2428 rtl_writephy(tp
, 0x1f, 0x0000);
2431 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2433 static const struct phy_reg phy_reg_init
[] = {
2489 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2492 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2494 static const struct phy_reg phy_reg_init
[] = {
2504 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2505 rtl_patchphy(tp
, 0x0d, 1 << 5);
2508 static void rtl8168e_hw_phy_config(struct rtl8169_private
*tp
)
2510 static const struct phy_reg phy_reg_init
[] = {
2511 /* Enable Delay cap */
2517 /* Channel estimation fine tune */
2526 /* Update PFM & 10M TX idle timer */
2538 rtl_apply_firmware(tp
);
2540 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2542 /* DCO enable for 10M IDLE Power */
2543 rtl_writephy(tp
, 0x1f, 0x0007);
2544 rtl_writephy(tp
, 0x1e, 0x0023);
2545 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2546 rtl_writephy(tp
, 0x1f, 0x0000);
2548 /* For impedance matching */
2549 rtl_writephy(tp
, 0x1f, 0x0002);
2550 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2551 rtl_writephy(tp
, 0x1F, 0x0000);
2553 /* PHY auto speed down */
2554 rtl_writephy(tp
, 0x1f, 0x0007);
2555 rtl_writephy(tp
, 0x1e, 0x002d);
2556 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2557 rtl_writephy(tp
, 0x1f, 0x0000);
2558 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2560 rtl_writephy(tp
, 0x1f, 0x0005);
2561 rtl_writephy(tp
, 0x05, 0x8b86);
2562 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2563 rtl_writephy(tp
, 0x1f, 0x0000);
2565 rtl_writephy(tp
, 0x1f, 0x0005);
2566 rtl_writephy(tp
, 0x05, 0x8b85);
2567 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2568 rtl_writephy(tp
, 0x1f, 0x0007);
2569 rtl_writephy(tp
, 0x1e, 0x0020);
2570 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2571 rtl_writephy(tp
, 0x1f, 0x0006);
2572 rtl_writephy(tp
, 0x00, 0x5a00);
2573 rtl_writephy(tp
, 0x1f, 0x0000);
2574 rtl_writephy(tp
, 0x0d, 0x0007);
2575 rtl_writephy(tp
, 0x0e, 0x003c);
2576 rtl_writephy(tp
, 0x0d, 0x4007);
2577 rtl_writephy(tp
, 0x0e, 0x0000);
2578 rtl_writephy(tp
, 0x0d, 0x0000);
2581 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
2583 static const struct phy_reg phy_reg_init
[] = {
2590 rtl_writephy(tp
, 0x1f, 0x0000);
2591 rtl_patchphy(tp
, 0x11, 1 << 12);
2592 rtl_patchphy(tp
, 0x19, 1 << 13);
2593 rtl_patchphy(tp
, 0x10, 1 << 15);
2595 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2598 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
2600 static const struct phy_reg phy_reg_init
[] = {
2614 /* Disable ALDPS before ram code */
2615 rtl_writephy(tp
, 0x1f, 0x0000);
2616 rtl_writephy(tp
, 0x18, 0x0310);
2619 rtl_apply_firmware(tp
);
2621 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2624 static void rtl_hw_phy_config(struct net_device
*dev
)
2626 struct rtl8169_private
*tp
= netdev_priv(dev
);
2628 rtl8169_print_mac_version(tp
);
2630 switch (tp
->mac_version
) {
2631 case RTL_GIGA_MAC_VER_01
:
2633 case RTL_GIGA_MAC_VER_02
:
2634 case RTL_GIGA_MAC_VER_03
:
2635 rtl8169s_hw_phy_config(tp
);
2637 case RTL_GIGA_MAC_VER_04
:
2638 rtl8169sb_hw_phy_config(tp
);
2640 case RTL_GIGA_MAC_VER_05
:
2641 rtl8169scd_hw_phy_config(tp
);
2643 case RTL_GIGA_MAC_VER_06
:
2644 rtl8169sce_hw_phy_config(tp
);
2646 case RTL_GIGA_MAC_VER_07
:
2647 case RTL_GIGA_MAC_VER_08
:
2648 case RTL_GIGA_MAC_VER_09
:
2649 rtl8102e_hw_phy_config(tp
);
2651 case RTL_GIGA_MAC_VER_11
:
2652 rtl8168bb_hw_phy_config(tp
);
2654 case RTL_GIGA_MAC_VER_12
:
2655 rtl8168bef_hw_phy_config(tp
);
2657 case RTL_GIGA_MAC_VER_17
:
2658 rtl8168bef_hw_phy_config(tp
);
2660 case RTL_GIGA_MAC_VER_18
:
2661 rtl8168cp_1_hw_phy_config(tp
);
2663 case RTL_GIGA_MAC_VER_19
:
2664 rtl8168c_1_hw_phy_config(tp
);
2666 case RTL_GIGA_MAC_VER_20
:
2667 rtl8168c_2_hw_phy_config(tp
);
2669 case RTL_GIGA_MAC_VER_21
:
2670 rtl8168c_3_hw_phy_config(tp
);
2672 case RTL_GIGA_MAC_VER_22
:
2673 rtl8168c_4_hw_phy_config(tp
);
2675 case RTL_GIGA_MAC_VER_23
:
2676 case RTL_GIGA_MAC_VER_24
:
2677 rtl8168cp_2_hw_phy_config(tp
);
2679 case RTL_GIGA_MAC_VER_25
:
2680 rtl8168d_1_hw_phy_config(tp
);
2682 case RTL_GIGA_MAC_VER_26
:
2683 rtl8168d_2_hw_phy_config(tp
);
2685 case RTL_GIGA_MAC_VER_27
:
2686 rtl8168d_3_hw_phy_config(tp
);
2688 case RTL_GIGA_MAC_VER_28
:
2689 rtl8168d_4_hw_phy_config(tp
);
2691 case RTL_GIGA_MAC_VER_29
:
2692 case RTL_GIGA_MAC_VER_30
:
2693 rtl8105e_hw_phy_config(tp
);
2695 case RTL_GIGA_MAC_VER_32
:
2696 case RTL_GIGA_MAC_VER_33
:
2697 rtl8168e_hw_phy_config(tp
);
2705 static void rtl8169_phy_timer(unsigned long __opaque
)
2707 struct net_device
*dev
= (struct net_device
*)__opaque
;
2708 struct rtl8169_private
*tp
= netdev_priv(dev
);
2709 struct timer_list
*timer
= &tp
->timer
;
2710 void __iomem
*ioaddr
= tp
->mmio_addr
;
2711 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2713 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2715 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
2718 spin_lock_irq(&tp
->lock
);
2720 if (tp
->phy_reset_pending(tp
)) {
2722 * A busy loop could burn quite a few cycles on nowadays CPU.
2723 * Let's delay the execution of the timer for a few ticks.
2729 if (tp
->link_ok(ioaddr
))
2732 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
2734 tp
->phy_reset_enable(tp
);
2737 mod_timer(timer
, jiffies
+ timeout
);
2739 spin_unlock_irq(&tp
->lock
);
2742 static inline void rtl8169_delete_timer(struct net_device
*dev
)
2744 struct rtl8169_private
*tp
= netdev_priv(dev
);
2745 struct timer_list
*timer
= &tp
->timer
;
2747 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2750 del_timer_sync(timer
);
2753 static inline void rtl8169_request_timer(struct net_device
*dev
)
2755 struct rtl8169_private
*tp
= netdev_priv(dev
);
2756 struct timer_list
*timer
= &tp
->timer
;
2758 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2761 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2764 #ifdef CONFIG_NET_POLL_CONTROLLER
2766 * Polling 'interrupt' - used by things like netconsole to send skbs
2767 * without having to re-enable interrupts. It's not called while
2768 * the interrupt routine is executing.
2770 static void rtl8169_netpoll(struct net_device
*dev
)
2772 struct rtl8169_private
*tp
= netdev_priv(dev
);
2773 struct pci_dev
*pdev
= tp
->pci_dev
;
2775 disable_irq(pdev
->irq
);
2776 rtl8169_interrupt(pdev
->irq
, dev
);
2777 enable_irq(pdev
->irq
);
2781 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2782 void __iomem
*ioaddr
)
2785 pci_release_regions(pdev
);
2786 pci_clear_mwi(pdev
);
2787 pci_disable_device(pdev
);
2791 static void rtl8169_phy_reset(struct net_device
*dev
,
2792 struct rtl8169_private
*tp
)
2796 tp
->phy_reset_enable(tp
);
2797 for (i
= 0; i
< 100; i
++) {
2798 if (!tp
->phy_reset_pending(tp
))
2802 netif_err(tp
, link
, dev
, "PHY reset failed\n");
2805 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2807 void __iomem
*ioaddr
= tp
->mmio_addr
;
2809 rtl_hw_phy_config(dev
);
2811 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2812 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2816 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2818 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2819 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2821 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2822 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2824 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2825 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
2828 rtl8169_phy_reset(dev
, tp
);
2830 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
2831 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
2832 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
2833 (tp
->mii
.supports_gmii
?
2834 ADVERTISED_1000baseT_Half
|
2835 ADVERTISED_1000baseT_Full
: 0));
2837 if (RTL_R8(PHYstatus
) & TBI_Enable
)
2838 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
2841 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2843 void __iomem
*ioaddr
= tp
->mmio_addr
;
2847 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2848 high
= addr
[4] | (addr
[5] << 8);
2850 spin_lock_irq(&tp
->lock
);
2852 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2854 RTL_W32(MAC4
, high
);
2860 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2862 spin_unlock_irq(&tp
->lock
);
2865 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2867 struct rtl8169_private
*tp
= netdev_priv(dev
);
2868 struct sockaddr
*addr
= p
;
2870 if (!is_valid_ether_addr(addr
->sa_data
))
2871 return -EADDRNOTAVAIL
;
2873 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2875 rtl_rar_set(tp
, dev
->dev_addr
);
2880 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2882 struct rtl8169_private
*tp
= netdev_priv(dev
);
2883 struct mii_ioctl_data
*data
= if_mii(ifr
);
2885 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2888 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2892 data
->phy_id
= 32; /* Internal PHY */
2896 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
2900 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
2906 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2911 static const struct rtl_cfg_info
{
2912 void (*hw_start
)(struct net_device
*);
2913 unsigned int region
;
2919 } rtl_cfg_infos
[] = {
2921 .hw_start
= rtl_hw_start_8169
,
2924 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2925 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2926 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2927 .features
= RTL_FEATURE_GMII
,
2928 .default_ver
= RTL_GIGA_MAC_VER_01
,
2931 .hw_start
= rtl_hw_start_8168
,
2934 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2935 TxErr
| TxOK
| RxOK
| RxErr
,
2936 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2937 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2938 .default_ver
= RTL_GIGA_MAC_VER_11
,
2941 .hw_start
= rtl_hw_start_8101
,
2944 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2945 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2946 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2947 .features
= RTL_FEATURE_MSI
,
2948 .default_ver
= RTL_GIGA_MAC_VER_13
,
2952 /* Cfg9346_Unlock assumed. */
2953 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2954 const struct rtl_cfg_info
*cfg
)
2959 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2960 if (cfg
->features
& RTL_FEATURE_MSI
) {
2961 if (pci_enable_msi(pdev
)) {
2962 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2965 msi
= RTL_FEATURE_MSI
;
2968 RTL_W8(Config2
, cfg2
);
2972 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2974 if (tp
->features
& RTL_FEATURE_MSI
) {
2975 pci_disable_msi(pdev
);
2976 tp
->features
&= ~RTL_FEATURE_MSI
;
2980 static const struct net_device_ops rtl8169_netdev_ops
= {
2981 .ndo_open
= rtl8169_open
,
2982 .ndo_stop
= rtl8169_close
,
2983 .ndo_get_stats
= rtl8169_get_stats
,
2984 .ndo_start_xmit
= rtl8169_start_xmit
,
2985 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2986 .ndo_validate_addr
= eth_validate_addr
,
2987 .ndo_change_mtu
= rtl8169_change_mtu
,
2988 .ndo_fix_features
= rtl8169_fix_features
,
2989 .ndo_set_features
= rtl8169_set_features
,
2990 .ndo_set_mac_address
= rtl_set_mac_address
,
2991 .ndo_do_ioctl
= rtl8169_ioctl
,
2992 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2993 #ifdef CONFIG_NET_POLL_CONTROLLER
2994 .ndo_poll_controller
= rtl8169_netpoll
,
2999 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3001 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3003 switch (tp
->mac_version
) {
3004 case RTL_GIGA_MAC_VER_27
:
3005 ops
->write
= r8168dp_1_mdio_write
;
3006 ops
->read
= r8168dp_1_mdio_read
;
3008 case RTL_GIGA_MAC_VER_28
:
3009 case RTL_GIGA_MAC_VER_31
:
3010 ops
->write
= r8168dp_2_mdio_write
;
3011 ops
->read
= r8168dp_2_mdio_read
;
3014 ops
->write
= r8169_mdio_write
;
3015 ops
->read
= r8169_mdio_read
;
3020 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3022 rtl_writephy(tp
, 0x1f, 0x0000);
3023 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3026 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3028 rtl_writephy(tp
, 0x1f, 0x0000);
3029 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3032 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3034 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3035 rtl_writephy(tp
, 0x1f, 0x0000);
3036 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3040 r810x_phy_power_down(tp
);
3043 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3045 r810x_phy_power_up(tp
);
3048 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3050 rtl_writephy(tp
, 0x1f, 0x0000);
3051 switch (tp
->mac_version
) {
3052 case RTL_GIGA_MAC_VER_11
:
3053 case RTL_GIGA_MAC_VER_12
:
3054 case RTL_GIGA_MAC_VER_17
:
3055 case RTL_GIGA_MAC_VER_18
:
3056 case RTL_GIGA_MAC_VER_19
:
3057 case RTL_GIGA_MAC_VER_20
:
3058 case RTL_GIGA_MAC_VER_21
:
3059 case RTL_GIGA_MAC_VER_22
:
3060 case RTL_GIGA_MAC_VER_23
:
3061 case RTL_GIGA_MAC_VER_24
:
3062 case RTL_GIGA_MAC_VER_25
:
3063 case RTL_GIGA_MAC_VER_26
:
3064 case RTL_GIGA_MAC_VER_27
:
3065 case RTL_GIGA_MAC_VER_28
:
3066 case RTL_GIGA_MAC_VER_31
:
3067 rtl_writephy(tp
, 0x0e, 0x0000);
3072 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3075 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3077 rtl_writephy(tp
, 0x1f, 0x0000);
3078 switch (tp
->mac_version
) {
3079 case RTL_GIGA_MAC_VER_32
:
3080 case RTL_GIGA_MAC_VER_33
:
3081 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3084 case RTL_GIGA_MAC_VER_11
:
3085 case RTL_GIGA_MAC_VER_12
:
3086 case RTL_GIGA_MAC_VER_17
:
3087 case RTL_GIGA_MAC_VER_18
:
3088 case RTL_GIGA_MAC_VER_19
:
3089 case RTL_GIGA_MAC_VER_20
:
3090 case RTL_GIGA_MAC_VER_21
:
3091 case RTL_GIGA_MAC_VER_22
:
3092 case RTL_GIGA_MAC_VER_23
:
3093 case RTL_GIGA_MAC_VER_24
:
3094 case RTL_GIGA_MAC_VER_25
:
3095 case RTL_GIGA_MAC_VER_26
:
3096 case RTL_GIGA_MAC_VER_27
:
3097 case RTL_GIGA_MAC_VER_28
:
3098 case RTL_GIGA_MAC_VER_31
:
3099 rtl_writephy(tp
, 0x0e, 0x0200);
3101 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3106 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3108 void __iomem
*ioaddr
= tp
->mmio_addr
;
3110 if (((tp
->mac_version
== RTL_GIGA_MAC_VER_27
) ||
3111 (tp
->mac_version
== RTL_GIGA_MAC_VER_28
) ||
3112 (tp
->mac_version
== RTL_GIGA_MAC_VER_31
)) &&
3113 r8168dp_check_dash(tp
)) {
3117 if (((tp
->mac_version
== RTL_GIGA_MAC_VER_23
) ||
3118 (tp
->mac_version
== RTL_GIGA_MAC_VER_24
)) &&
3119 (RTL_R16(CPlusCmd
) & ASF
)) {
3123 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3124 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3125 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3127 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3128 rtl_writephy(tp
, 0x1f, 0x0000);
3129 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3131 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
3132 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3136 r8168_phy_power_down(tp
);
3138 switch (tp
->mac_version
) {
3139 case RTL_GIGA_MAC_VER_25
:
3140 case RTL_GIGA_MAC_VER_26
:
3141 case RTL_GIGA_MAC_VER_27
:
3142 case RTL_GIGA_MAC_VER_28
:
3143 case RTL_GIGA_MAC_VER_31
:
3144 case RTL_GIGA_MAC_VER_32
:
3145 case RTL_GIGA_MAC_VER_33
:
3146 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3151 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3153 void __iomem
*ioaddr
= tp
->mmio_addr
;
3155 if (((tp
->mac_version
== RTL_GIGA_MAC_VER_27
) ||
3156 (tp
->mac_version
== RTL_GIGA_MAC_VER_28
) ||
3157 (tp
->mac_version
== RTL_GIGA_MAC_VER_31
)) &&
3158 r8168dp_check_dash(tp
)) {
3162 switch (tp
->mac_version
) {
3163 case RTL_GIGA_MAC_VER_25
:
3164 case RTL_GIGA_MAC_VER_26
:
3165 case RTL_GIGA_MAC_VER_27
:
3166 case RTL_GIGA_MAC_VER_28
:
3167 case RTL_GIGA_MAC_VER_31
:
3168 case RTL_GIGA_MAC_VER_32
:
3169 case RTL_GIGA_MAC_VER_33
:
3170 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3174 r8168_phy_power_up(tp
);
3177 static void rtl_pll_power_op(struct rtl8169_private
*tp
,
3178 void (*op
)(struct rtl8169_private
*))
3184 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3186 rtl_pll_power_op(tp
, tp
->pll_power_ops
.down
);
3189 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3191 rtl_pll_power_op(tp
, tp
->pll_power_ops
.up
);
3194 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3196 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3198 switch (tp
->mac_version
) {
3199 case RTL_GIGA_MAC_VER_07
:
3200 case RTL_GIGA_MAC_VER_08
:
3201 case RTL_GIGA_MAC_VER_09
:
3202 case RTL_GIGA_MAC_VER_10
:
3203 case RTL_GIGA_MAC_VER_16
:
3204 case RTL_GIGA_MAC_VER_29
:
3205 case RTL_GIGA_MAC_VER_30
:
3206 ops
->down
= r810x_pll_power_down
;
3207 ops
->up
= r810x_pll_power_up
;
3210 case RTL_GIGA_MAC_VER_11
:
3211 case RTL_GIGA_MAC_VER_12
:
3212 case RTL_GIGA_MAC_VER_17
:
3213 case RTL_GIGA_MAC_VER_18
:
3214 case RTL_GIGA_MAC_VER_19
:
3215 case RTL_GIGA_MAC_VER_20
:
3216 case RTL_GIGA_MAC_VER_21
:
3217 case RTL_GIGA_MAC_VER_22
:
3218 case RTL_GIGA_MAC_VER_23
:
3219 case RTL_GIGA_MAC_VER_24
:
3220 case RTL_GIGA_MAC_VER_25
:
3221 case RTL_GIGA_MAC_VER_26
:
3222 case RTL_GIGA_MAC_VER_27
:
3223 case RTL_GIGA_MAC_VER_28
:
3224 case RTL_GIGA_MAC_VER_31
:
3225 case RTL_GIGA_MAC_VER_32
:
3226 case RTL_GIGA_MAC_VER_33
:
3227 ops
->down
= r8168_pll_power_down
;
3228 ops
->up
= r8168_pll_power_up
;
3238 static int __devinit
3239 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3241 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3242 const unsigned int region
= cfg
->region
;
3243 struct rtl8169_private
*tp
;
3244 struct mii_if_info
*mii
;
3245 struct net_device
*dev
;
3246 void __iomem
*ioaddr
;
3250 if (netif_msg_drv(&debug
)) {
3251 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3252 MODULENAME
, RTL8169_VERSION
);
3255 dev
= alloc_etherdev(sizeof (*tp
));
3257 if (netif_msg_drv(&debug
))
3258 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3263 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3264 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3265 tp
= netdev_priv(dev
);
3268 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3272 mii
->mdio_read
= rtl_mdio_read
;
3273 mii
->mdio_write
= rtl_mdio_write
;
3274 mii
->phy_id_mask
= 0x1f;
3275 mii
->reg_num_mask
= 0x1f;
3276 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3278 /* disable ASPM completely as that cause random device stop working
3279 * problems as well as full system hangs for some PCIe devices users */
3280 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3281 PCIE_LINK_STATE_CLKPM
);
3283 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3284 rc
= pci_enable_device(pdev
);
3286 netif_err(tp
, probe
, dev
, "enable failure\n");
3287 goto err_out_free_dev_1
;
3290 if (pci_set_mwi(pdev
) < 0)
3291 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3293 /* make sure PCI base addr 1 is MMIO */
3294 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3295 netif_err(tp
, probe
, dev
,
3296 "region #%d not an MMIO resource, aborting\n",
3302 /* check for weird/broken PCI region reporting */
3303 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3304 netif_err(tp
, probe
, dev
,
3305 "Invalid PCI region size(s), aborting\n");
3310 rc
= pci_request_regions(pdev
, MODULENAME
);
3312 netif_err(tp
, probe
, dev
, "could not request regions\n");
3316 tp
->cp_cmd
= RxChkSum
;
3318 if ((sizeof(dma_addr_t
) > 4) &&
3319 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3320 tp
->cp_cmd
|= PCIDAC
;
3321 dev
->features
|= NETIF_F_HIGHDMA
;
3323 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3325 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3326 goto err_out_free_res_3
;
3330 /* ioremap MMIO region */
3331 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3333 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3335 goto err_out_free_res_3
;
3338 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3340 netif_info(tp
, probe
, dev
, "no PCI Express capability\n");
3342 RTL_W16(IntrMask
, 0x0000);
3344 /* Soft reset the chip. */
3345 RTL_W8(ChipCmd
, CmdReset
);
3347 /* Check that the chip has finished the reset. */
3348 for (i
= 0; i
< 100; i
++) {
3349 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3351 msleep_interruptible(1);
3354 RTL_W16(IntrStatus
, 0xffff);
3356 pci_set_master(pdev
);
3358 /* Identify chip attached to board */
3359 rtl8169_get_mac_version(tp
, ioaddr
);
3362 * Pretend we are using VLANs; This bypasses a nasty bug where
3363 * Interrupts stop flowing on high load on 8110SCd controllers.
3365 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3366 tp
->cp_cmd
|= RxVlan
;
3368 rtl_init_mdio_ops(tp
);
3369 rtl_init_pll_power_ops(tp
);
3371 /* Use appropriate default if unknown */
3372 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
3373 netif_notice(tp
, probe
, dev
,
3374 "unknown MAC, using family default\n");
3375 tp
->mac_version
= cfg
->default_ver
;
3378 rtl8169_print_mac_version(tp
);
3380 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
3381 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
3384 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
3386 "driver bug, MAC version not found in rtl_chip_info\n");
3390 tp
->txd_version
= rtl_chip_info
[chipset
].txd_version
;
3392 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3393 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3394 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3395 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3396 tp
->features
|= RTL_FEATURE_WOL
;
3397 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3398 tp
->features
|= RTL_FEATURE_WOL
;
3399 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3400 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3402 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3403 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3404 tp
->set_speed
= rtl8169_set_speed_tbi
;
3405 tp
->get_settings
= rtl8169_gset_tbi
;
3406 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3407 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3408 tp
->link_ok
= rtl8169_tbi_link_ok
;
3409 tp
->do_ioctl
= rtl_tbi_ioctl
;
3411 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
3413 tp
->set_speed
= rtl8169_set_speed_xmii
;
3414 tp
->get_settings
= rtl8169_gset_xmii
;
3415 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3416 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3417 tp
->link_ok
= rtl8169_xmii_link_ok
;
3418 tp
->do_ioctl
= rtl_xmii_ioctl
;
3421 spin_lock_init(&tp
->lock
);
3423 tp
->mmio_addr
= ioaddr
;
3425 /* Get MAC address */
3426 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3427 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3428 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3430 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3431 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3432 dev
->irq
= pdev
->irq
;
3433 dev
->base_addr
= (unsigned long) ioaddr
;
3435 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3437 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3438 * properly for all devices */
3439 dev
->features
|= NETIF_F_RXCSUM
|
3440 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3442 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3443 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3444 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3447 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3448 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3449 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
3451 tp
->intr_mask
= 0xffff;
3452 tp
->hw_start
= cfg
->hw_start
;
3453 tp
->intr_event
= cfg
->intr_event
;
3454 tp
->napi_event
= cfg
->napi_event
;
3456 init_timer(&tp
->timer
);
3457 tp
->timer
.data
= (unsigned long) dev
;
3458 tp
->timer
.function
= rtl8169_phy_timer
;
3460 tp
->fw
= RTL_FIRMWARE_UNKNOWN
;
3462 rc
= register_netdev(dev
);
3466 pci_set_drvdata(pdev
, dev
);
3468 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3469 rtl_chip_info
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
3470 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3472 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
) ||
3473 (tp
->mac_version
== RTL_GIGA_MAC_VER_28
) ||
3474 (tp
->mac_version
== RTL_GIGA_MAC_VER_31
)) {
3475 rtl8168_driver_start(tp
);
3478 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3480 if (pci_dev_run_wake(pdev
))
3481 pm_runtime_put_noidle(&pdev
->dev
);
3483 netif_carrier_off(dev
);
3489 rtl_disable_msi(pdev
, tp
);
3492 pci_release_regions(pdev
);
3494 pci_clear_mwi(pdev
);
3495 pci_disable_device(pdev
);
3501 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3503 struct net_device
*dev
= pci_get_drvdata(pdev
);
3504 struct rtl8169_private
*tp
= netdev_priv(dev
);
3506 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
) ||
3507 (tp
->mac_version
== RTL_GIGA_MAC_VER_28
) ||
3508 (tp
->mac_version
== RTL_GIGA_MAC_VER_31
)) {
3509 rtl8168_driver_stop(tp
);
3512 cancel_delayed_work_sync(&tp
->task
);
3514 unregister_netdev(dev
);
3516 rtl_release_firmware(tp
);
3518 if (pci_dev_run_wake(pdev
))
3519 pm_runtime_get_noresume(&pdev
->dev
);
3521 /* restore original MAC address */
3522 rtl_rar_set(tp
, dev
->perm_addr
);
3524 rtl_disable_msi(pdev
, tp
);
3525 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3526 pci_set_drvdata(pdev
, NULL
);
3529 static void rtl_request_firmware(struct rtl8169_private
*tp
)
3533 /* Return early if the firmware is already loaded / cached. */
3534 if (!IS_ERR(tp
->fw
))
3537 for (i
= 0; i
< ARRAY_SIZE(rtl_firmware_infos
); i
++) {
3538 const struct rtl_firmware_info
*info
= rtl_firmware_infos
+ i
;
3540 if (info
->mac_version
== tp
->mac_version
) {
3541 const char *name
= info
->fw_name
;
3544 rc
= request_firmware(&tp
->fw
, name
, &tp
->pci_dev
->dev
);
3546 netif_warn(tp
, ifup
, tp
->dev
, "unable to load "
3547 "firmware patch %s (%d)\n", name
, rc
);
3548 goto out_disable_request_firmware
;
3554 out_disable_request_firmware
:
3560 static int rtl8169_open(struct net_device
*dev
)
3562 struct rtl8169_private
*tp
= netdev_priv(dev
);
3563 void __iomem
*ioaddr
= tp
->mmio_addr
;
3564 struct pci_dev
*pdev
= tp
->pci_dev
;
3565 int retval
= -ENOMEM
;
3567 pm_runtime_get_sync(&pdev
->dev
);
3570 * Rx and Tx desscriptors needs 256 bytes alignment.
3571 * dma_alloc_coherent provides more.
3573 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3574 &tp
->TxPhyAddr
, GFP_KERNEL
);
3575 if (!tp
->TxDescArray
)
3576 goto err_pm_runtime_put
;
3578 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3579 &tp
->RxPhyAddr
, GFP_KERNEL
);
3580 if (!tp
->RxDescArray
)
3583 retval
= rtl8169_init_ring(dev
);
3587 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3591 rtl_request_firmware(tp
);
3593 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3594 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3597 goto err_release_fw_2
;
3599 napi_enable(&tp
->napi
);
3601 rtl8169_init_phy(dev
, tp
);
3603 rtl8169_set_features(dev
, dev
->features
);
3605 rtl_pll_power_up(tp
);
3609 rtl8169_request_timer(dev
);
3611 tp
->saved_wolopts
= 0;
3612 pm_runtime_put_noidle(&pdev
->dev
);
3614 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3619 rtl_release_firmware(tp
);
3620 rtl8169_rx_clear(tp
);
3622 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3624 tp
->RxDescArray
= NULL
;
3626 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3628 tp
->TxDescArray
= NULL
;
3630 pm_runtime_put_noidle(&pdev
->dev
);
3634 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3636 void __iomem
*ioaddr
= tp
->mmio_addr
;
3638 /* Disable interrupts */
3639 rtl8169_irq_mask_and_ack(ioaddr
);
3641 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3642 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3643 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3644 while (RTL_R8(TxPoll
) & NPQ
)
3649 /* Reset the chipset */
3650 RTL_W8(ChipCmd
, CmdReset
);
3656 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3658 void __iomem
*ioaddr
= tp
->mmio_addr
;
3659 u32 cfg
= rtl8169_rx_config
;
3661 cfg
|= (RTL_R32(RxConfig
) & RTL_RX_CONFIG_MASK
);
3662 RTL_W32(RxConfig
, cfg
);
3664 /* Set DMA burst size and Interframe Gap Time */
3665 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3666 (InterFrameGap
<< TxInterFrameGapShift
));
3669 static void rtl_hw_start(struct net_device
*dev
)
3671 struct rtl8169_private
*tp
= netdev_priv(dev
);
3672 void __iomem
*ioaddr
= tp
->mmio_addr
;
3675 /* Soft reset the chip. */
3676 RTL_W8(ChipCmd
, CmdReset
);
3678 /* Check that the chip has finished the reset. */
3679 for (i
= 0; i
< 100; i
++) {
3680 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3682 msleep_interruptible(1);
3687 netif_start_queue(dev
);
3691 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3692 void __iomem
*ioaddr
)
3695 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3696 * register to be written before TxDescAddrLow to work.
3697 * Switching from MMIO to I/O access fixes the issue as well.
3699 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3700 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3701 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3702 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3705 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3709 cmd
= RTL_R16(CPlusCmd
);
3710 RTL_W16(CPlusCmd
, cmd
);
3714 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3716 /* Low hurts. Let's disable the filtering. */
3717 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3720 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3722 static const struct {
3727 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3728 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3729 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3730 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3735 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3736 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3737 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3738 RTL_W32(0x7c, p
->val
);
3744 static void rtl_hw_start_8169(struct net_device
*dev
)
3746 struct rtl8169_private
*tp
= netdev_priv(dev
);
3747 void __iomem
*ioaddr
= tp
->mmio_addr
;
3748 struct pci_dev
*pdev
= tp
->pci_dev
;
3750 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3751 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3752 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3755 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3756 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3757 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3758 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3759 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3760 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3762 RTL_W8(EarlyTxThres
, NoEarlyTx
);
3764 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3766 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3767 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3768 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3769 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3770 rtl_set_rx_tx_config_registers(tp
);
3772 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3774 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3775 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
3776 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3777 "Bit-3 and bit-14 MUST be 1\n");
3778 tp
->cp_cmd
|= (1 << 14);
3781 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3783 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3786 * Undocumented corner. Supposedly:
3787 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3789 RTL_W16(IntrMitigate
, 0x0000);
3791 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3793 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
3794 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
3795 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
3796 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
3797 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3798 rtl_set_rx_tx_config_registers(tp
);
3801 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3803 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3806 RTL_W32(RxMissed
, 0);
3808 rtl_set_rx_mode(dev
);
3810 /* no early-rx interrupts */
3811 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3813 /* Enable all known interrupts by setting the interrupt mask. */
3814 RTL_W16(IntrMask
, tp
->intr_event
);
3817 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3819 struct net_device
*dev
= pci_get_drvdata(pdev
);
3820 struct rtl8169_private
*tp
= netdev_priv(dev
);
3821 int cap
= tp
->pcie_cap
;
3826 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3827 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3828 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3832 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
3836 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3837 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
3840 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
3842 rtl_csi_access_enable(ioaddr
, 0x17000000);
3845 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
3847 rtl_csi_access_enable(ioaddr
, 0x27000000);
3851 unsigned int offset
;
3856 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
3861 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3862 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3867 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3869 struct net_device
*dev
= pci_get_drvdata(pdev
);
3870 struct rtl8169_private
*tp
= netdev_priv(dev
);
3871 int cap
= tp
->pcie_cap
;
3876 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3877 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3878 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3882 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
3884 struct net_device
*dev
= pci_get_drvdata(pdev
);
3885 struct rtl8169_private
*tp
= netdev_priv(dev
);
3886 int cap
= tp
->pcie_cap
;
3891 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3892 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
3893 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3897 #define R8168_CPCMD_QUIRK_MASK (\
3908 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3910 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3912 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3914 rtl_tx_performance_tweak(pdev
,
3915 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3918 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3920 rtl_hw_start_8168bb(ioaddr
, pdev
);
3922 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3924 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3927 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3929 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3931 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3933 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3935 rtl_disable_clock_request(pdev
);
3937 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3940 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3942 static const struct ephy_info e_info_8168cp
[] = {
3943 { 0x01, 0, 0x0001 },
3944 { 0x02, 0x0800, 0x1000 },
3945 { 0x03, 0, 0x0042 },
3946 { 0x06, 0x0080, 0x0000 },
3950 rtl_csi_access_enable_2(ioaddr
);
3952 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3954 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3957 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3959 rtl_csi_access_enable_2(ioaddr
);
3961 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3963 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3965 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3968 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3970 rtl_csi_access_enable_2(ioaddr
);
3972 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3975 RTL_W8(DBG_REG
, 0x20);
3977 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3979 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3981 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3984 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3986 static const struct ephy_info e_info_8168c_1
[] = {
3987 { 0x02, 0x0800, 0x1000 },
3988 { 0x03, 0, 0x0002 },
3989 { 0x06, 0x0080, 0x0000 }
3992 rtl_csi_access_enable_2(ioaddr
);
3994 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3996 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3998 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4001 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4003 static const struct ephy_info e_info_8168c_2
[] = {
4004 { 0x01, 0, 0x0001 },
4005 { 0x03, 0x0400, 0x0220 }
4008 rtl_csi_access_enable_2(ioaddr
);
4010 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4012 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4015 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4017 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4020 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4022 rtl_csi_access_enable_2(ioaddr
);
4024 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4027 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4029 rtl_csi_access_enable_2(ioaddr
);
4031 rtl_disable_clock_request(pdev
);
4033 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4035 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4037 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4040 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4042 rtl_csi_access_enable_1(ioaddr
);
4044 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4046 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4048 rtl_disable_clock_request(pdev
);
4051 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4053 static const struct ephy_info e_info_8168d_4
[] = {
4055 { 0x19, 0x20, 0x50 },
4060 rtl_csi_access_enable_1(ioaddr
);
4062 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4064 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4066 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4067 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4070 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4071 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4074 rtl_enable_clock_request(pdev
);
4077 static void rtl_hw_start_8168e(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4079 static const struct ephy_info e_info_8168e
[] = {
4080 { 0x00, 0x0200, 0x0100 },
4081 { 0x00, 0x0000, 0x0004 },
4082 { 0x06, 0x0002, 0x0001 },
4083 { 0x06, 0x0000, 0x0030 },
4084 { 0x07, 0x0000, 0x2000 },
4085 { 0x00, 0x0000, 0x0020 },
4086 { 0x03, 0x5800, 0x2000 },
4087 { 0x03, 0x0000, 0x0001 },
4088 { 0x01, 0x0800, 0x1000 },
4089 { 0x07, 0x0000, 0x4000 },
4090 { 0x1e, 0x0000, 0x2000 },
4091 { 0x19, 0xffff, 0xfe6c },
4092 { 0x0a, 0x0000, 0x0040 }
4095 rtl_csi_access_enable_2(ioaddr
);
4097 rtl_ephy_init(ioaddr
, e_info_8168e
, ARRAY_SIZE(e_info_8168e
));
4099 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4101 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4103 rtl_disable_clock_request(pdev
);
4105 /* Reset tx FIFO pointer */
4106 RTL_W32(MISC
, RTL_R32(MISC
) | txpla_rst
);
4107 RTL_W32(MISC
, RTL_R32(MISC
) & ~txpla_rst
);
4109 RTL_W8(Config5
, RTL_R8(Config5
) & ~spi_en
);
4112 static void rtl_hw_start_8168(struct net_device
*dev
)
4114 struct rtl8169_private
*tp
= netdev_priv(dev
);
4115 void __iomem
*ioaddr
= tp
->mmio_addr
;
4116 struct pci_dev
*pdev
= tp
->pci_dev
;
4118 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4120 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4122 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4124 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4126 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4128 RTL_W16(IntrMitigate
, 0x5151);
4130 /* Work around for RxFIFO overflow. */
4131 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
4132 tp
->mac_version
== RTL_GIGA_MAC_VER_22
) {
4133 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4134 tp
->intr_event
&= ~RxOverflow
;
4137 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4139 rtl_set_rx_mode(dev
);
4141 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4142 (InterFrameGap
<< TxInterFrameGapShift
));
4146 switch (tp
->mac_version
) {
4147 case RTL_GIGA_MAC_VER_11
:
4148 rtl_hw_start_8168bb(ioaddr
, pdev
);
4151 case RTL_GIGA_MAC_VER_12
:
4152 case RTL_GIGA_MAC_VER_17
:
4153 rtl_hw_start_8168bef(ioaddr
, pdev
);
4156 case RTL_GIGA_MAC_VER_18
:
4157 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4160 case RTL_GIGA_MAC_VER_19
:
4161 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4164 case RTL_GIGA_MAC_VER_20
:
4165 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4168 case RTL_GIGA_MAC_VER_21
:
4169 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4172 case RTL_GIGA_MAC_VER_22
:
4173 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4176 case RTL_GIGA_MAC_VER_23
:
4177 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4180 case RTL_GIGA_MAC_VER_24
:
4181 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4184 case RTL_GIGA_MAC_VER_25
:
4185 case RTL_GIGA_MAC_VER_26
:
4186 case RTL_GIGA_MAC_VER_27
:
4187 rtl_hw_start_8168d(ioaddr
, pdev
);
4190 case RTL_GIGA_MAC_VER_28
:
4191 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4193 case RTL_GIGA_MAC_VER_31
:
4194 rtl_hw_start_8168dp(ioaddr
, pdev
);
4197 case RTL_GIGA_MAC_VER_32
:
4198 case RTL_GIGA_MAC_VER_33
:
4199 rtl_hw_start_8168e(ioaddr
, pdev
);
4203 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4204 dev
->name
, tp
->mac_version
);
4208 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4210 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4212 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4214 RTL_W16(IntrMask
, tp
->intr_event
);
4217 #define R810X_CPCMD_QUIRK_MASK (\
4228 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4230 static const struct ephy_info e_info_8102e_1
[] = {
4231 { 0x01, 0, 0x6e65 },
4232 { 0x02, 0, 0x091f },
4233 { 0x03, 0, 0xc2f9 },
4234 { 0x06, 0, 0xafb5 },
4235 { 0x07, 0, 0x0e00 },
4236 { 0x19, 0, 0xec80 },
4237 { 0x01, 0, 0x2e65 },
4242 rtl_csi_access_enable_2(ioaddr
);
4244 RTL_W8(DBG_REG
, FIX_NAK_1
);
4246 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4249 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4250 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4252 cfg1
= RTL_R8(Config1
);
4253 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4254 RTL_W8(Config1
, cfg1
& ~LEDS0
);
4256 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
4259 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4261 rtl_csi_access_enable_2(ioaddr
);
4263 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4265 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4266 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4269 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4271 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4273 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
4276 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4278 static const struct ephy_info e_info_8105e_1
[] = {
4279 { 0x07, 0, 0x4000 },
4280 { 0x19, 0, 0x0200 },
4281 { 0x19, 0, 0x0020 },
4282 { 0x1e, 0, 0x2000 },
4283 { 0x03, 0, 0x0001 },
4284 { 0x19, 0, 0x0100 },
4285 { 0x19, 0, 0x0004 },
4289 /* Force LAN exit from ASPM if Rx/Tx are not idel */
4290 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
4292 /* disable Early Tally Counter */
4293 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
4295 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
4296 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PM_SWITCH
);
4298 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
4301 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4303 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4304 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
4307 static void rtl_hw_start_8101(struct net_device
*dev
)
4309 struct rtl8169_private
*tp
= netdev_priv(dev
);
4310 void __iomem
*ioaddr
= tp
->mmio_addr
;
4311 struct pci_dev
*pdev
= tp
->pci_dev
;
4313 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
4314 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
4315 int cap
= tp
->pcie_cap
;
4318 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
4319 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4323 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4325 switch (tp
->mac_version
) {
4326 case RTL_GIGA_MAC_VER_07
:
4327 rtl_hw_start_8102e_1(ioaddr
, pdev
);
4330 case RTL_GIGA_MAC_VER_08
:
4331 rtl_hw_start_8102e_3(ioaddr
, pdev
);
4334 case RTL_GIGA_MAC_VER_09
:
4335 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4338 case RTL_GIGA_MAC_VER_29
:
4339 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4341 case RTL_GIGA_MAC_VER_30
:
4342 rtl_hw_start_8105e_2(ioaddr
, pdev
);
4346 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4348 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4350 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4352 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
4353 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4355 RTL_W16(IntrMitigate
, 0x0000);
4357 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4359 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4360 rtl_set_rx_tx_config_registers(tp
);
4364 rtl_set_rx_mode(dev
);
4366 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
4368 RTL_W16(IntrMask
, tp
->intr_event
);
4371 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
4373 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
4377 netdev_update_features(dev
);
4382 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
4384 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
4385 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
4388 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
4389 void **data_buff
, struct RxDesc
*desc
)
4391 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
4396 rtl8169_make_unusable_by_asic(desc
);
4399 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
4401 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
4403 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
4406 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4409 desc
->addr
= cpu_to_le64(mapping
);
4411 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4414 static inline void *rtl8169_align(void *data
)
4416 return (void *)ALIGN((long)data
, 16);
4419 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4420 struct RxDesc
*desc
)
4424 struct device
*d
= &tp
->pci_dev
->dev
;
4425 struct net_device
*dev
= tp
->dev
;
4426 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
4428 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
4432 if (rtl8169_align(data
) != data
) {
4434 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
4439 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
4441 if (unlikely(dma_mapping_error(d
, mapping
))) {
4442 if (net_ratelimit())
4443 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
4447 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4455 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4459 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4460 if (tp
->Rx_databuff
[i
]) {
4461 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4462 tp
->RxDescArray
+ i
);
4467 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4469 desc
->opts1
|= cpu_to_le32(RingEnd
);
4472 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
4476 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4479 if (tp
->Rx_databuff
[i
])
4482 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
4484 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4487 tp
->Rx_databuff
[i
] = data
;
4490 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4494 rtl8169_rx_clear(tp
);
4498 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4500 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4503 static int rtl8169_init_ring(struct net_device
*dev
)
4505 struct rtl8169_private
*tp
= netdev_priv(dev
);
4507 rtl8169_init_ring_indexes(tp
);
4509 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4510 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4512 return rtl8169_rx_fill(tp
);
4515 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
4516 struct TxDesc
*desc
)
4518 unsigned int len
= tx_skb
->len
;
4520 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
4528 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
4533 for (i
= 0; i
< n
; i
++) {
4534 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
4535 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4536 unsigned int len
= tx_skb
->len
;
4539 struct sk_buff
*skb
= tx_skb
->skb
;
4541 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4542 tp
->TxDescArray
+ entry
);
4544 tp
->dev
->stats
.tx_dropped
++;
4552 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4554 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
4555 tp
->cur_tx
= tp
->dirty_tx
= 0;
4558 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4560 struct rtl8169_private
*tp
= netdev_priv(dev
);
4562 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4563 schedule_delayed_work(&tp
->task
, 4);
4566 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4568 struct rtl8169_private
*tp
= netdev_priv(dev
);
4569 void __iomem
*ioaddr
= tp
->mmio_addr
;
4571 synchronize_irq(dev
->irq
);
4573 /* Wait for any pending NAPI task to complete */
4574 napi_disable(&tp
->napi
);
4576 rtl8169_irq_mask_and_ack(ioaddr
);
4578 tp
->intr_mask
= 0xffff;
4579 RTL_W16(IntrMask
, tp
->intr_event
);
4580 napi_enable(&tp
->napi
);
4583 static void rtl8169_reinit_task(struct work_struct
*work
)
4585 struct rtl8169_private
*tp
=
4586 container_of(work
, struct rtl8169_private
, task
.work
);
4587 struct net_device
*dev
= tp
->dev
;
4592 if (!netif_running(dev
))
4595 rtl8169_wait_for_quiescence(dev
);
4598 ret
= rtl8169_open(dev
);
4599 if (unlikely(ret
< 0)) {
4600 if (net_ratelimit())
4601 netif_err(tp
, drv
, dev
,
4602 "reinit failure (status = %d). Rescheduling\n",
4604 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4611 static void rtl8169_reset_task(struct work_struct
*work
)
4613 struct rtl8169_private
*tp
=
4614 container_of(work
, struct rtl8169_private
, task
.work
);
4615 struct net_device
*dev
= tp
->dev
;
4619 if (!netif_running(dev
))
4622 rtl8169_wait_for_quiescence(dev
);
4624 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
4625 rtl8169_tx_clear(tp
);
4627 if (tp
->dirty_rx
== tp
->cur_rx
) {
4628 rtl8169_init_ring_indexes(tp
);
4630 netif_wake_queue(dev
);
4631 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4633 if (net_ratelimit())
4634 netif_emerg(tp
, intr
, dev
, "Rx buffers shortage\n");
4635 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4642 static void rtl8169_tx_timeout(struct net_device
*dev
)
4644 struct rtl8169_private
*tp
= netdev_priv(dev
);
4646 rtl8169_hw_reset(tp
);
4648 /* Let's wait a bit while any (async) irq lands on */
4649 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4652 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4655 struct skb_shared_info
*info
= skb_shinfo(skb
);
4656 unsigned int cur_frag
, entry
;
4657 struct TxDesc
* uninitialized_var(txd
);
4658 struct device
*d
= &tp
->pci_dev
->dev
;
4661 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4662 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4667 entry
= (entry
+ 1) % NUM_TX_DESC
;
4669 txd
= tp
->TxDescArray
+ entry
;
4671 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4672 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
4673 if (unlikely(dma_mapping_error(d
, mapping
))) {
4674 if (net_ratelimit())
4675 netif_err(tp
, drv
, tp
->dev
,
4676 "Failed to map TX fragments DMA!\n");
4680 /* anti gcc 2.95.3 bugware (sic) */
4681 status
= opts
[0] | len
|
4682 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4684 txd
->opts1
= cpu_to_le32(status
);
4685 txd
->opts2
= cpu_to_le32(opts
[1]);
4686 txd
->addr
= cpu_to_le64(mapping
);
4688 tp
->tx_skb
[entry
].len
= len
;
4692 tp
->tx_skb
[entry
].skb
= skb
;
4693 txd
->opts1
|= cpu_to_le32(LastFrag
);
4699 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
4703 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
4704 struct sk_buff
*skb
, u32
*opts
)
4706 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
4707 u32 mss
= skb_shinfo(skb
)->gso_size
;
4708 int offset
= info
->opts_offset
;
4712 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
4713 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4714 const struct iphdr
*ip
= ip_hdr(skb
);
4716 if (ip
->protocol
== IPPROTO_TCP
)
4717 opts
[offset
] |= info
->checksum
.tcp
;
4718 else if (ip
->protocol
== IPPROTO_UDP
)
4719 opts
[offset
] |= info
->checksum
.udp
;
4725 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4726 struct net_device
*dev
)
4728 struct rtl8169_private
*tp
= netdev_priv(dev
);
4729 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
4730 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4731 void __iomem
*ioaddr
= tp
->mmio_addr
;
4732 struct device
*d
= &tp
->pci_dev
->dev
;
4738 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4739 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
4743 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4746 len
= skb_headlen(skb
);
4747 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
4748 if (unlikely(dma_mapping_error(d
, mapping
))) {
4749 if (net_ratelimit())
4750 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
4754 tp
->tx_skb
[entry
].len
= len
;
4755 txd
->addr
= cpu_to_le64(mapping
);
4757 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4760 rtl8169_tso_csum(tp
, skb
, opts
);
4762 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
4766 opts
[0] |= FirstFrag
;
4768 opts
[0] |= FirstFrag
| LastFrag
;
4769 tp
->tx_skb
[entry
].skb
= skb
;
4772 txd
->opts2
= cpu_to_le32(opts
[1]);
4776 /* anti gcc 2.95.3 bugware (sic) */
4777 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4778 txd
->opts1
= cpu_to_le32(status
);
4780 tp
->cur_tx
+= frags
+ 1;
4784 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
4786 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4787 netif_stop_queue(dev
);
4789 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4790 netif_wake_queue(dev
);
4793 return NETDEV_TX_OK
;
4796 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
4799 dev
->stats
.tx_dropped
++;
4800 return NETDEV_TX_OK
;
4803 netif_stop_queue(dev
);
4804 dev
->stats
.tx_dropped
++;
4805 return NETDEV_TX_BUSY
;
4808 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4810 struct rtl8169_private
*tp
= netdev_priv(dev
);
4811 struct pci_dev
*pdev
= tp
->pci_dev
;
4812 u16 pci_status
, pci_cmd
;
4814 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4815 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4817 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4818 pci_cmd
, pci_status
);
4821 * The recovery sequence below admits a very elaborated explanation:
4822 * - it seems to work;
4823 * - I did not see what else could be done;
4824 * - it makes iop3xx happy.
4826 * Feel free to adjust to your needs.
4828 if (pdev
->broken_parity_status
)
4829 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4831 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4833 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4835 pci_write_config_word(pdev
, PCI_STATUS
,
4836 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4837 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4838 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4840 /* The infamous DAC f*ckup only happens at boot time */
4841 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4842 void __iomem
*ioaddr
= tp
->mmio_addr
;
4844 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
4845 tp
->cp_cmd
&= ~PCIDAC
;
4846 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4847 dev
->features
&= ~NETIF_F_HIGHDMA
;
4850 rtl8169_hw_reset(tp
);
4852 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4855 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4856 struct rtl8169_private
*tp
,
4857 void __iomem
*ioaddr
)
4859 unsigned int dirty_tx
, tx_left
;
4861 dirty_tx
= tp
->dirty_tx
;
4863 tx_left
= tp
->cur_tx
- dirty_tx
;
4865 while (tx_left
> 0) {
4866 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4867 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4871 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4872 if (status
& DescOwn
)
4875 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4876 tp
->TxDescArray
+ entry
);
4877 if (status
& LastFrag
) {
4878 dev
->stats
.tx_packets
++;
4879 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
4880 dev_kfree_skb(tx_skb
->skb
);
4887 if (tp
->dirty_tx
!= dirty_tx
) {
4888 tp
->dirty_tx
= dirty_tx
;
4890 if (netif_queue_stopped(dev
) &&
4891 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4892 netif_wake_queue(dev
);
4895 * 8168 hack: TxPoll requests are lost when the Tx packets are
4896 * too close. Let's kick an extra TxPoll request when a burst
4897 * of start_xmit activity is detected (if it is not detected,
4898 * it is slow enough). -- FR
4901 if (tp
->cur_tx
!= dirty_tx
)
4902 RTL_W8(TxPoll
, NPQ
);
4906 static inline int rtl8169_fragmented_frame(u32 status
)
4908 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4911 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
4913 u32 status
= opts1
& RxProtoMask
;
4915 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4916 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
4917 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4919 skb_checksum_none_assert(skb
);
4922 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
4923 struct rtl8169_private
*tp
,
4927 struct sk_buff
*skb
;
4928 struct device
*d
= &tp
->pci_dev
->dev
;
4930 data
= rtl8169_align(data
);
4931 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4933 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
4935 memcpy(skb
->data
, data
, pkt_size
);
4936 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4942 * Warning : rtl8169_rx_interrupt() might be called :
4943 * 1) from NAPI (softirq) context
4944 * (polling = 1 : we should call netif_receive_skb())
4945 * 2) from process context (rtl8169_reset_task())
4946 * (polling = 0 : we must call netif_rx() instead)
4948 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4949 struct rtl8169_private
*tp
,
4950 void __iomem
*ioaddr
, u32 budget
)
4952 unsigned int cur_rx
, rx_left
;
4954 int polling
= (budget
!= ~(u32
)0) ? 1 : 0;
4956 cur_rx
= tp
->cur_rx
;
4957 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4958 rx_left
= min(rx_left
, budget
);
4960 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4961 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4962 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4966 status
= le32_to_cpu(desc
->opts1
);
4968 if (status
& DescOwn
)
4970 if (unlikely(status
& RxRES
)) {
4971 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
4973 dev
->stats
.rx_errors
++;
4974 if (status
& (RxRWT
| RxRUNT
))
4975 dev
->stats
.rx_length_errors
++;
4977 dev
->stats
.rx_crc_errors
++;
4978 if (status
& RxFOVF
) {
4979 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4980 dev
->stats
.rx_fifo_errors
++;
4982 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4984 struct sk_buff
*skb
;
4985 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4986 int pkt_size
= (status
& 0x00001FFF) - 4;
4989 * The driver does not support incoming fragmented
4990 * frames. They are seen as a symptom of over-mtu
4993 if (unlikely(rtl8169_fragmented_frame(status
))) {
4994 dev
->stats
.rx_dropped
++;
4995 dev
->stats
.rx_length_errors
++;
4996 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5000 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5001 tp
, pkt_size
, addr
);
5002 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5004 dev
->stats
.rx_dropped
++;
5008 rtl8169_rx_csum(skb
, status
);
5009 skb_put(skb
, pkt_size
);
5010 skb
->protocol
= eth_type_trans(skb
, dev
);
5012 rtl8169_rx_vlan_tag(desc
, skb
);
5014 if (likely(polling
))
5015 napi_gro_receive(&tp
->napi
, skb
);
5019 dev
->stats
.rx_bytes
+= pkt_size
;
5020 dev
->stats
.rx_packets
++;
5023 /* Work around for AMD plateform. */
5024 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5025 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5031 count
= cur_rx
- tp
->cur_rx
;
5032 tp
->cur_rx
= cur_rx
;
5034 tp
->dirty_rx
+= count
;
5039 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5041 struct net_device
*dev
= dev_instance
;
5042 struct rtl8169_private
*tp
= netdev_priv(dev
);
5043 void __iomem
*ioaddr
= tp
->mmio_addr
;
5047 /* loop handling interrupts until we have no new ones or
5048 * we hit a invalid/hotplug case.
5050 status
= RTL_R16(IntrStatus
);
5051 while (status
&& status
!= 0xffff) {
5054 /* Handle all of the error cases first. These will reset
5055 * the chip, so just exit the loop.
5057 if (unlikely(!netif_running(dev
))) {
5058 rtl8169_asic_down(ioaddr
);
5062 if (unlikely(status
& RxFIFOOver
)) {
5063 switch (tp
->mac_version
) {
5064 /* Work around for rx fifo overflow */
5065 case RTL_GIGA_MAC_VER_11
:
5066 case RTL_GIGA_MAC_VER_22
:
5067 case RTL_GIGA_MAC_VER_26
:
5068 netif_stop_queue(dev
);
5069 rtl8169_tx_timeout(dev
);
5071 /* Testers needed. */
5072 case RTL_GIGA_MAC_VER_17
:
5073 case RTL_GIGA_MAC_VER_19
:
5074 case RTL_GIGA_MAC_VER_20
:
5075 case RTL_GIGA_MAC_VER_21
:
5076 case RTL_GIGA_MAC_VER_23
:
5077 case RTL_GIGA_MAC_VER_24
:
5078 case RTL_GIGA_MAC_VER_27
:
5079 case RTL_GIGA_MAC_VER_28
:
5080 case RTL_GIGA_MAC_VER_31
:
5081 /* Experimental science. Pktgen proof. */
5082 case RTL_GIGA_MAC_VER_12
:
5083 case RTL_GIGA_MAC_VER_25
:
5084 if (status
== RxFIFOOver
)
5092 if (unlikely(status
& SYSErr
)) {
5093 rtl8169_pcierr_interrupt(dev
);
5097 if (status
& LinkChg
)
5098 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5100 /* We need to see the lastest version of tp->intr_mask to
5101 * avoid ignoring an MSI interrupt and having to wait for
5102 * another event which may never come.
5105 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5106 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5107 tp
->intr_mask
= ~tp
->napi_event
;
5109 if (likely(napi_schedule_prep(&tp
->napi
)))
5110 __napi_schedule(&tp
->napi
);
5112 netif_info(tp
, intr
, dev
,
5113 "interrupt %04x in poll\n", status
);
5116 /* We only get a new MSI interrupt when all active irq
5117 * sources on the chip have been acknowledged. So, ack
5118 * everything we've seen and check if new sources have become
5119 * active to avoid blocking all interrupts from the chip.
5122 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5123 status
= RTL_R16(IntrStatus
);
5126 return IRQ_RETVAL(handled
);
5129 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5131 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5132 struct net_device
*dev
= tp
->dev
;
5133 void __iomem
*ioaddr
= tp
->mmio_addr
;
5136 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5137 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5139 if (work_done
< budget
) {
5140 napi_complete(napi
);
5142 /* We need for force the visibility of tp->intr_mask
5143 * for other CPUs, as we can loose an MSI interrupt
5144 * and potentially wait for a retransmit timeout if we don't.
5145 * The posted write to IntrMask is safe, as it will
5146 * eventually make it to the chip and we won't loose anything
5149 tp
->intr_mask
= 0xffff;
5151 RTL_W16(IntrMask
, tp
->intr_event
);
5157 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5159 struct rtl8169_private
*tp
= netdev_priv(dev
);
5161 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5164 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5165 RTL_W32(RxMissed
, 0);
5168 static void rtl8169_down(struct net_device
*dev
)
5170 struct rtl8169_private
*tp
= netdev_priv(dev
);
5171 void __iomem
*ioaddr
= tp
->mmio_addr
;
5173 rtl8169_delete_timer(dev
);
5175 netif_stop_queue(dev
);
5177 napi_disable(&tp
->napi
);
5179 spin_lock_irq(&tp
->lock
);
5181 rtl8169_asic_down(ioaddr
);
5183 * At this point device interrupts can not be enabled in any function,
5184 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5185 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5187 rtl8169_rx_missed(dev
, ioaddr
);
5189 spin_unlock_irq(&tp
->lock
);
5191 synchronize_irq(dev
->irq
);
5193 /* Give a racing hard_start_xmit a few cycles to complete. */
5194 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5196 rtl8169_tx_clear(tp
);
5198 rtl8169_rx_clear(tp
);
5200 rtl_pll_power_down(tp
);
5203 static int rtl8169_close(struct net_device
*dev
)
5205 struct rtl8169_private
*tp
= netdev_priv(dev
);
5206 struct pci_dev
*pdev
= tp
->pci_dev
;
5208 pm_runtime_get_sync(&pdev
->dev
);
5210 /* update counters before going down */
5211 rtl8169_update_counters(dev
);
5215 free_irq(dev
->irq
, dev
);
5217 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5219 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5221 tp
->TxDescArray
= NULL
;
5222 tp
->RxDescArray
= NULL
;
5224 pm_runtime_put_sync(&pdev
->dev
);
5229 static void rtl_set_rx_mode(struct net_device
*dev
)
5231 struct rtl8169_private
*tp
= netdev_priv(dev
);
5232 void __iomem
*ioaddr
= tp
->mmio_addr
;
5233 unsigned long flags
;
5234 u32 mc_filter
[2]; /* Multicast hash filter */
5238 if (dev
->flags
& IFF_PROMISC
) {
5239 /* Unconditionally log net taps. */
5240 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5242 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5244 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5245 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5246 (dev
->flags
& IFF_ALLMULTI
)) {
5247 /* Too many to filter perfectly -- accept all multicasts. */
5248 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5249 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5251 struct netdev_hw_addr
*ha
;
5253 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5254 mc_filter
[1] = mc_filter
[0] = 0;
5255 netdev_for_each_mc_addr(ha
, dev
) {
5256 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5257 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5258 rx_mode
|= AcceptMulticast
;
5262 spin_lock_irqsave(&tp
->lock
, flags
);
5264 tmp
= rtl8169_rx_config
| rx_mode
|
5265 (RTL_R32(RxConfig
) & RTL_RX_CONFIG_MASK
);
5267 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5268 u32 data
= mc_filter
[0];
5270 mc_filter
[0] = swab32(mc_filter
[1]);
5271 mc_filter
[1] = swab32(data
);
5274 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5275 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5277 RTL_W32(RxConfig
, tmp
);
5279 spin_unlock_irqrestore(&tp
->lock
, flags
);
5283 * rtl8169_get_stats - Get rtl8169 read/write statistics
5284 * @dev: The Ethernet Device to get statistics for
5286 * Get TX/RX statistics for rtl8169
5288 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
5290 struct rtl8169_private
*tp
= netdev_priv(dev
);
5291 void __iomem
*ioaddr
= tp
->mmio_addr
;
5292 unsigned long flags
;
5294 if (netif_running(dev
)) {
5295 spin_lock_irqsave(&tp
->lock
, flags
);
5296 rtl8169_rx_missed(dev
, ioaddr
);
5297 spin_unlock_irqrestore(&tp
->lock
, flags
);
5303 static void rtl8169_net_suspend(struct net_device
*dev
)
5305 struct rtl8169_private
*tp
= netdev_priv(dev
);
5307 if (!netif_running(dev
))
5310 rtl_pll_power_down(tp
);
5312 netif_device_detach(dev
);
5313 netif_stop_queue(dev
);
5318 static int rtl8169_suspend(struct device
*device
)
5320 struct pci_dev
*pdev
= to_pci_dev(device
);
5321 struct net_device
*dev
= pci_get_drvdata(pdev
);
5323 rtl8169_net_suspend(dev
);
5328 static void __rtl8169_resume(struct net_device
*dev
)
5330 struct rtl8169_private
*tp
= netdev_priv(dev
);
5332 netif_device_attach(dev
);
5334 rtl_pll_power_up(tp
);
5336 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5339 static int rtl8169_resume(struct device
*device
)
5341 struct pci_dev
*pdev
= to_pci_dev(device
);
5342 struct net_device
*dev
= pci_get_drvdata(pdev
);
5343 struct rtl8169_private
*tp
= netdev_priv(dev
);
5345 rtl8169_init_phy(dev
, tp
);
5347 if (netif_running(dev
))
5348 __rtl8169_resume(dev
);
5353 static int rtl8169_runtime_suspend(struct device
*device
)
5355 struct pci_dev
*pdev
= to_pci_dev(device
);
5356 struct net_device
*dev
= pci_get_drvdata(pdev
);
5357 struct rtl8169_private
*tp
= netdev_priv(dev
);
5359 if (!tp
->TxDescArray
)
5362 spin_lock_irq(&tp
->lock
);
5363 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
5364 __rtl8169_set_wol(tp
, WAKE_ANY
);
5365 spin_unlock_irq(&tp
->lock
);
5367 rtl8169_net_suspend(dev
);
5372 static int rtl8169_runtime_resume(struct device
*device
)
5374 struct pci_dev
*pdev
= to_pci_dev(device
);
5375 struct net_device
*dev
= pci_get_drvdata(pdev
);
5376 struct rtl8169_private
*tp
= netdev_priv(dev
);
5378 if (!tp
->TxDescArray
)
5381 spin_lock_irq(&tp
->lock
);
5382 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
5383 tp
->saved_wolopts
= 0;
5384 spin_unlock_irq(&tp
->lock
);
5386 rtl8169_init_phy(dev
, tp
);
5388 __rtl8169_resume(dev
);
5393 static int rtl8169_runtime_idle(struct device
*device
)
5395 struct pci_dev
*pdev
= to_pci_dev(device
);
5396 struct net_device
*dev
= pci_get_drvdata(pdev
);
5397 struct rtl8169_private
*tp
= netdev_priv(dev
);
5399 return tp
->TxDescArray
? -EBUSY
: 0;
5402 static const struct dev_pm_ops rtl8169_pm_ops
= {
5403 .suspend
= rtl8169_suspend
,
5404 .resume
= rtl8169_resume
,
5405 .freeze
= rtl8169_suspend
,
5406 .thaw
= rtl8169_resume
,
5407 .poweroff
= rtl8169_suspend
,
5408 .restore
= rtl8169_resume
,
5409 .runtime_suspend
= rtl8169_runtime_suspend
,
5410 .runtime_resume
= rtl8169_runtime_resume
,
5411 .runtime_idle
= rtl8169_runtime_idle
,
5414 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5416 #else /* !CONFIG_PM */
5418 #define RTL8169_PM_OPS NULL
5420 #endif /* !CONFIG_PM */
5422 static void rtl_shutdown(struct pci_dev
*pdev
)
5424 struct net_device
*dev
= pci_get_drvdata(pdev
);
5425 struct rtl8169_private
*tp
= netdev_priv(dev
);
5426 void __iomem
*ioaddr
= tp
->mmio_addr
;
5428 rtl8169_net_suspend(dev
);
5430 /* restore original MAC address */
5431 rtl_rar_set(tp
, dev
->perm_addr
);
5433 spin_lock_irq(&tp
->lock
);
5435 rtl8169_asic_down(ioaddr
);
5437 spin_unlock_irq(&tp
->lock
);
5439 if (system_state
== SYSTEM_POWER_OFF
) {
5440 /* WoL fails with some 8168 when the receiver is disabled. */
5441 if (tp
->features
& RTL_FEATURE_WOL
) {
5442 pci_clear_master(pdev
);
5444 RTL_W8(ChipCmd
, CmdRxEnb
);
5449 pci_wake_from_d3(pdev
, true);
5450 pci_set_power_state(pdev
, PCI_D3hot
);
5454 static struct pci_driver rtl8169_pci_driver
= {
5456 .id_table
= rtl8169_pci_tbl
,
5457 .probe
= rtl8169_init_one
,
5458 .remove
= __devexit_p(rtl8169_remove_one
),
5459 .shutdown
= rtl_shutdown
,
5460 .driver
.pm
= RTL8169_PM_OPS
,
5463 static int __init
rtl8169_init_module(void)
5465 return pci_register_driver(&rtl8169_pci_driver
);
5468 static void __exit
rtl8169_cleanup_module(void)
5470 pci_unregister_driver(&rtl8169_pci_driver
);
5473 module_init(rtl8169_init_module
);
5474 module_exit(rtl8169_cleanup_module
);