2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
29 #include <asm/system.h>
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define assert(expr) \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44 #expr,__FILE__,__func__,__LINE__); \
46 #define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit
= 32;
63 /* MAC address length */
64 #define MAC_ADDR_LEN 6
66 #define MAX_READ_REQUEST_SHIFT 12
67 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) readl (ioaddr + (reg))
97 RTL_GIGA_MAC_NONE
= 0x00,
98 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
99 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25
= 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26
= 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27
= 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28
= 0x1c, // 8168DP
128 #define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131 static const struct {
134 u32 RxConfigMask
; /* Clears the bits supported by this chip */
135 } rtl_chip_info
[] = {
136 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
142 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
150 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26
, 0xff7e1880), // PCI-E
162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27
, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28
, 0xff7e1880) // PCI-E
173 static void rtl_hw_start_8169(struct net_device
*);
174 static void rtl_hw_start_8168(struct net_device
*);
175 static void rtl_hw_start_8101(struct net_device
*);
177 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
184 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
186 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
187 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
189 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
193 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
195 static int rx_buf_sz
= 16383;
202 MAC0
= 0, /* Ethernet hardware address. */
204 MAR0
= 8, /* Multicast filter. */
205 CounterAddrLow
= 0x10,
206 CounterAddrHigh
= 0x14,
207 TxDescStartAddrLow
= 0x20,
208 TxDescStartAddrHigh
= 0x24,
209 TxHDescStartAddrLow
= 0x28,
210 TxHDescStartAddrHigh
= 0x2c,
233 RxDescAddrLow
= 0xe4,
234 RxDescAddrHigh
= 0xe8,
235 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
237 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
239 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
241 #define TxPacketMax (8064 >> 7)
244 FuncEventMask
= 0xf4,
245 FuncPresetState
= 0xf8,
246 FuncForceEvent
= 0xfc,
249 enum rtl8110_registers
{
255 enum rtl8168_8101_registers
{
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0f
261 #define CSIAR_BYTE_ENABLE_SHIFT 12
262 #define CSIAR_ADDR_MASK 0x0fff
265 #define EPHYAR_FLAG 0x80000000
266 #define EPHYAR_WRITE_CMD 0x80000000
267 #define EPHYAR_REG_MASK 0x1f
268 #define EPHYAR_REG_SHIFT 16
269 #define EPHYAR_DATA_MASK 0xffff
271 #define FIX_NAK_1 (1 << 4)
272 #define FIX_NAK_2 (1 << 3)
274 #define EFUSEAR_FLAG 0x80000000
275 #define EFUSEAR_WRITE_CMD 0x80000000
276 #define EFUSEAR_READ_CMD 0x00000000
277 #define EFUSEAR_REG_MASK 0x03ff
278 #define EFUSEAR_REG_SHIFT 8
279 #define EFUSEAR_DATA_MASK 0xff
282 enum rtl8168_registers
{
285 #define ERIAR_FLAG 0x80000000
286 #define ERIAR_WRITE_CMD 0x80000000
287 #define ERIAR_READ_CMD 0x00000000
288 #define ERIAR_ADDR_BYTE_ALIGN 4
289 #define ERIAR_EXGMAC 0
292 #define ERIAR_TYPE_SHIFT 16
293 #define ERIAR_BYTEEN 0x0f
294 #define ERIAR_BYTEEN_SHIFT 12
295 EPHY_RXER_NUM
= 0x7c,
296 OCPDR
= 0xb0, /* OCP GPHY access */
297 #define OCPDR_WRITE_CMD 0x80000000
298 #define OCPDR_READ_CMD 0x00000000
299 #define OCPDR_REG_MASK 0x7f
300 #define OCPDR_GPHY_REG_SHIFT 16
301 #define OCPDR_DATA_MASK 0xffff
303 #define OCPAR_FLAG 0x80000000
304 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
305 #define OCPAR_GPHY_READ_CMD 0x0000f060
306 RDSAR1
= 0xd0 /* 8168c only. Undocumented on 8168dp */
309 enum rtl_register_content
{
310 /* InterruptStatusBits */
314 TxDescUnavail
= 0x0080,
336 /* TXPoll register p.5 */
337 HPQ
= 0x80, /* Poll cmd on the high prio queue */
338 NPQ
= 0x40, /* Poll cmd on the low prio queue */
339 FSWInt
= 0x01, /* Forced software interrupt */
343 Cfg9346_Unlock
= 0xc0,
348 AcceptBroadcast
= 0x08,
349 AcceptMulticast
= 0x04,
351 AcceptAllPhys
= 0x01,
358 TxInterFrameGapShift
= 24,
359 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
361 /* Config1 register p.24 */
364 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
365 Speed_down
= (1 << 4),
369 PMEnable
= (1 << 0), /* Power Management Enable */
371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz
= 0x01,
373 PCI_Clock_33MHz
= 0x00,
375 /* Config3 register p.25 */
376 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
378 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
380 /* Config5 register p.27 */
381 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
383 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake
= (1 << 1), /* LanWake enable/disable */
385 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
388 TBIReset
= 0x80000000,
389 TBILoopback
= 0x40000000,
390 TBINwEnable
= 0x20000000,
391 TBINwRestart
= 0x10000000,
392 TBILinkOk
= 0x02000000,
393 TBINwComplete
= 0x01000000,
396 EnableBist
= (1 << 15), // 8168 8101
397 Mac_dbgo_oe
= (1 << 14), // 8168 8101
398 Normal_mode
= (1 << 13), // unused
399 Force_half_dup
= (1 << 12), // 8168 8101
400 Force_rxflow_en
= (1 << 11), // 8168 8101
401 Force_txflow_en
= (1 << 10), // 8168 8101
402 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
403 ASF
= (1 << 8), // 8168 8101
404 PktCntrDisable
= (1 << 7), // 8168 8101
405 Mac_dbgo_sel
= 0x001c, // 8168
410 INTT_0
= 0x0000, // 8168
411 INTT_1
= 0x0001, // 8168
412 INTT_2
= 0x0002, // 8168
413 INTT_3
= 0x0003, // 8168
415 /* rtl8169_PHYstatus */
426 TBILinkOK
= 0x02000000,
428 /* DumpCounterCommand */
432 enum desc_status_bit
{
433 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd
= (1 << 30), /* End of descriptor ring */
435 FirstFrag
= (1 << 29), /* First segment of a packet */
436 LastFrag
= (1 << 28), /* Final segment of a packet */
439 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift
= 16, /* MSS value position */
441 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS
= (1 << 18), /* Calculate IP checksum */
443 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag
= (1 << 17), /* Add VLAN tag */
448 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
449 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
451 #define RxProtoUDP (PID1)
452 #define RxProtoTCP (PID0)
453 #define RxProtoIP (PID1 | PID0)
454 #define RxProtoMask RxProtoIP
456 IPFail
= (1 << 16), /* IP checksum failed */
457 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
458 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag
= (1 << 16), /* VLAN tag available */
462 #define RsvdMask 0x3fffc000
479 u8 __pad
[sizeof(void *) - sizeof(u32
)];
483 RTL_FEATURE_WOL
= (1 << 0),
484 RTL_FEATURE_MSI
= (1 << 1),
485 RTL_FEATURE_GMII
= (1 << 2),
488 struct rtl8169_counters
{
495 __le32 tx_one_collision
;
496 __le32 tx_multi_collision
;
504 struct rtl8169_private
{
505 void __iomem
*mmio_addr
; /* memory map physical address */
506 struct pci_dev
*pci_dev
; /* Index of PCI device */
507 struct net_device
*dev
;
508 struct napi_struct napi
;
509 spinlock_t lock
; /* spin lock flag */
513 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
517 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
518 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr
;
520 dma_addr_t RxPhyAddr
;
521 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
522 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
523 struct timer_list timer
;
528 int phy_1000_ctrl_reg
;
529 #ifdef CONFIG_R8169_VLAN
530 struct vlan_group
*vlgrp
;
534 void (*write
)(void __iomem
*, int, int);
535 int (*read
)(void __iomem
*, int);
538 struct pll_power_ops
{
539 void (*down
)(struct rtl8169_private
*);
540 void (*up
)(struct rtl8169_private
*);
543 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
544 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
545 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
546 void (*hw_start
)(struct net_device
*);
547 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
548 unsigned int (*link_ok
)(void __iomem
*);
549 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
551 struct delayed_work task
;
554 struct mii_if_info mii
;
555 struct rtl8169_counters counters
;
558 const struct firmware
*fw
;
561 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
562 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
563 module_param(use_dac
, int, 0);
564 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
565 module_param_named(debug
, debug
.msg_enable
, int, 0);
566 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
567 MODULE_LICENSE("GPL");
568 MODULE_VERSION(RTL8169_VERSION
);
569 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
570 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
572 static int rtl8169_open(struct net_device
*dev
);
573 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
574 struct net_device
*dev
);
575 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
576 static int rtl8169_init_ring(struct net_device
*dev
);
577 static void rtl_hw_start(struct net_device
*dev
);
578 static int rtl8169_close(struct net_device
*dev
);
579 static void rtl_set_rx_mode(struct net_device
*dev
);
580 static void rtl8169_tx_timeout(struct net_device
*dev
);
581 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
582 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
583 void __iomem
*, u32 budget
);
584 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
585 static void rtl8169_down(struct net_device
*dev
);
586 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
587 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
589 static const unsigned int rtl8169_rx_config
=
590 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
592 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
594 void __iomem
*ioaddr
= tp
->mmio_addr
;
597 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
598 for (i
= 0; i
< 20; i
++) {
600 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
603 return RTL_R32(OCPDR
);
606 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
608 void __iomem
*ioaddr
= tp
->mmio_addr
;
611 RTL_W32(OCPDR
, data
);
612 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
613 for (i
= 0; i
< 20; i
++) {
615 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
620 static void rtl8168_oob_notify(void __iomem
*ioaddr
, u8 cmd
)
625 RTL_W32(ERIAR
, 0x800010e8);
627 for (i
= 0; i
< 5; i
++) {
629 if (!(RTL_R32(ERIDR
) & ERIAR_FLAG
))
633 ocp_write(ioaddr
, 0x1, 0x30, 0x00000001);
636 #define OOB_CMD_RESET 0x00
637 #define OOB_CMD_DRIVER_START 0x05
638 #define OOB_CMD_DRIVER_STOP 0x06
640 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
644 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
646 for (i
= 0; i
< 10; i
++) {
648 if (ocp_read(tp
, 0x0f, 0x0010) & 0x00000800)
653 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
657 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
659 for (i
= 0; i
< 10; i
++) {
661 if ((ocp_read(tp
, 0x0f, 0x0010) & 0x00000800) == 0)
667 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
671 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
673 for (i
= 20; i
> 0; i
--) {
675 * Check if the RTL8169 has completed writing to the specified
678 if (!(RTL_R32(PHYAR
) & 0x80000000))
683 * According to hardware specs a 20us delay is required after write
684 * complete indication, but before sending next command.
689 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
693 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
695 for (i
= 20; i
> 0; i
--) {
697 * Check if the RTL8169 has completed retrieving data from
698 * the specified MII register.
700 if (RTL_R32(PHYAR
) & 0x80000000) {
701 value
= RTL_R32(PHYAR
) & 0xffff;
707 * According to hardware specs a 20us delay is required after read
708 * complete indication, but before sending next command.
715 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
719 RTL_W32(OCPDR
, data
|
720 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
721 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
722 RTL_W32(EPHY_RXER_NUM
, 0);
724 for (i
= 0; i
< 100; i
++) {
726 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
731 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
733 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
734 (value
& OCPDR_DATA_MASK
));
737 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
741 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
744 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
745 RTL_W32(EPHY_RXER_NUM
, 0);
747 for (i
= 0; i
< 100; i
++) {
749 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
753 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
756 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
758 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
760 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
763 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
765 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
768 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
770 r8168dp_2_mdio_start(ioaddr
);
772 r8169_mdio_write(ioaddr
, reg_addr
, value
);
774 r8168dp_2_mdio_stop(ioaddr
);
777 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
781 r8168dp_2_mdio_start(ioaddr
);
783 value
= r8169_mdio_read(ioaddr
, reg_addr
);
785 r8168dp_2_mdio_stop(ioaddr
);
790 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
792 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
795 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
797 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
800 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
802 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
805 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
809 val
= rtl_readphy(tp
, reg_addr
);
810 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
813 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
816 struct rtl8169_private
*tp
= netdev_priv(dev
);
818 rtl_writephy(tp
, location
, val
);
821 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
823 struct rtl8169_private
*tp
= netdev_priv(dev
);
825 return rtl_readphy(tp
, location
);
828 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
832 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
833 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
835 for (i
= 0; i
< 100; i
++) {
836 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
842 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
847 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
849 for (i
= 0; i
< 100; i
++) {
850 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
851 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
860 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
864 RTL_W32(CSIDR
, value
);
865 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
866 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
868 for (i
= 0; i
< 100; i
++) {
869 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
875 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
880 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
881 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
883 for (i
= 0; i
< 100; i
++) {
884 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
885 value
= RTL_R32(CSIDR
);
894 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
899 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
901 for (i
= 0; i
< 300; i
++) {
902 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
903 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
912 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
914 RTL_W16(IntrMask
, 0x0000);
916 RTL_W16(IntrStatus
, 0xffff);
919 static void rtl8169_asic_down(void __iomem
*ioaddr
)
921 RTL_W8(ChipCmd
, 0x00);
922 rtl8169_irq_mask_and_ack(ioaddr
);
926 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
928 void __iomem
*ioaddr
= tp
->mmio_addr
;
930 return RTL_R32(TBICSR
) & TBIReset
;
933 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
935 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
938 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
940 return RTL_R32(TBICSR
) & TBILinkOk
;
943 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
945 return RTL_R8(PHYstatus
) & LinkStatus
;
948 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
950 void __iomem
*ioaddr
= tp
->mmio_addr
;
952 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
955 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
959 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
960 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
963 static void __rtl8169_check_link_status(struct net_device
*dev
,
964 struct rtl8169_private
*tp
,
965 void __iomem
*ioaddr
,
970 spin_lock_irqsave(&tp
->lock
, flags
);
971 if (tp
->link_ok(ioaddr
)) {
972 /* This is to cancel a scheduled suspend if there's one. */
974 pm_request_resume(&tp
->pci_dev
->dev
);
975 netif_carrier_on(dev
);
976 netif_info(tp
, ifup
, dev
, "link up\n");
978 netif_carrier_off(dev
);
979 netif_info(tp
, ifdown
, dev
, "link down\n");
981 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
983 spin_unlock_irqrestore(&tp
->lock
, flags
);
986 static void rtl8169_check_link_status(struct net_device
*dev
,
987 struct rtl8169_private
*tp
,
988 void __iomem
*ioaddr
)
990 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
993 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
995 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
997 void __iomem
*ioaddr
= tp
->mmio_addr
;
1001 options
= RTL_R8(Config1
);
1002 if (!(options
& PMEnable
))
1005 options
= RTL_R8(Config3
);
1006 if (options
& LinkUp
)
1007 wolopts
|= WAKE_PHY
;
1008 if (options
& MagicPacket
)
1009 wolopts
|= WAKE_MAGIC
;
1011 options
= RTL_R8(Config5
);
1013 wolopts
|= WAKE_UCAST
;
1015 wolopts
|= WAKE_BCAST
;
1017 wolopts
|= WAKE_MCAST
;
1022 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1024 struct rtl8169_private
*tp
= netdev_priv(dev
);
1026 spin_lock_irq(&tp
->lock
);
1028 wol
->supported
= WAKE_ANY
;
1029 wol
->wolopts
= __rtl8169_get_wol(tp
);
1031 spin_unlock_irq(&tp
->lock
);
1034 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1036 void __iomem
*ioaddr
= tp
->mmio_addr
;
1038 static const struct {
1043 { WAKE_ANY
, Config1
, PMEnable
},
1044 { WAKE_PHY
, Config3
, LinkUp
},
1045 { WAKE_MAGIC
, Config3
, MagicPacket
},
1046 { WAKE_UCAST
, Config5
, UWF
},
1047 { WAKE_BCAST
, Config5
, BWF
},
1048 { WAKE_MCAST
, Config5
, MWF
},
1049 { WAKE_ANY
, Config5
, LanWake
}
1052 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1054 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1055 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1056 if (wolopts
& cfg
[i
].opt
)
1057 options
|= cfg
[i
].mask
;
1058 RTL_W8(cfg
[i
].reg
, options
);
1061 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1064 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1066 struct rtl8169_private
*tp
= netdev_priv(dev
);
1068 spin_lock_irq(&tp
->lock
);
1071 tp
->features
|= RTL_FEATURE_WOL
;
1073 tp
->features
&= ~RTL_FEATURE_WOL
;
1074 __rtl8169_set_wol(tp
, wol
->wolopts
);
1075 spin_unlock_irq(&tp
->lock
);
1077 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1082 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1083 struct ethtool_drvinfo
*info
)
1085 struct rtl8169_private
*tp
= netdev_priv(dev
);
1087 strcpy(info
->driver
, MODULENAME
);
1088 strcpy(info
->version
, RTL8169_VERSION
);
1089 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1092 static int rtl8169_get_regs_len(struct net_device
*dev
)
1094 return R8169_REGS_SIZE
;
1097 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1098 u8 autoneg
, u16 speed
, u8 duplex
)
1100 struct rtl8169_private
*tp
= netdev_priv(dev
);
1101 void __iomem
*ioaddr
= tp
->mmio_addr
;
1105 reg
= RTL_R32(TBICSR
);
1106 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1107 (duplex
== DUPLEX_FULL
)) {
1108 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1109 } else if (autoneg
== AUTONEG_ENABLE
)
1110 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1112 netif_warn(tp
, link
, dev
,
1113 "incorrect speed setting refused in TBI mode\n");
1120 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1121 u8 autoneg
, u16 speed
, u8 duplex
)
1123 struct rtl8169_private
*tp
= netdev_priv(dev
);
1124 int giga_ctrl
, bmcr
;
1126 if (autoneg
== AUTONEG_ENABLE
) {
1129 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1130 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1131 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1132 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1134 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1135 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1137 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1138 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
1139 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
1140 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
1141 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
1142 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
1143 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
1144 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
1145 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
1146 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
1148 netif_info(tp
, link
, dev
,
1149 "PHY does not support 1000Mbps\n");
1152 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1154 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
1155 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
1156 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
1159 * Vendor specific (0x1f) and reserved (0x0e) MII
1162 rtl_writephy(tp
, 0x1f, 0x0000);
1163 rtl_writephy(tp
, 0x0e, 0x0000);
1166 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1167 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1171 if (speed
== SPEED_10
)
1173 else if (speed
== SPEED_100
)
1174 bmcr
= BMCR_SPEED100
;
1178 if (duplex
== DUPLEX_FULL
)
1179 bmcr
|= BMCR_FULLDPLX
;
1181 rtl_writephy(tp
, 0x1f, 0x0000);
1184 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
1186 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1188 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
1189 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
1190 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1191 rtl_writephy(tp
, 0x17, 0x2138);
1192 rtl_writephy(tp
, 0x0e, 0x0260);
1194 rtl_writephy(tp
, 0x17, 0x2108);
1195 rtl_writephy(tp
, 0x0e, 0x0000);
1202 static int rtl8169_set_speed(struct net_device
*dev
,
1203 u8 autoneg
, u16 speed
, u8 duplex
)
1205 struct rtl8169_private
*tp
= netdev_priv(dev
);
1208 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
1210 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1211 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1216 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1218 struct rtl8169_private
*tp
= netdev_priv(dev
);
1219 unsigned long flags
;
1222 spin_lock_irqsave(&tp
->lock
, flags
);
1223 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
1224 spin_unlock_irqrestore(&tp
->lock
, flags
);
1229 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
1231 struct rtl8169_private
*tp
= netdev_priv(dev
);
1233 return tp
->cp_cmd
& RxChkSum
;
1236 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
1238 struct rtl8169_private
*tp
= netdev_priv(dev
);
1239 void __iomem
*ioaddr
= tp
->mmio_addr
;
1240 unsigned long flags
;
1242 spin_lock_irqsave(&tp
->lock
, flags
);
1245 tp
->cp_cmd
|= RxChkSum
;
1247 tp
->cp_cmd
&= ~RxChkSum
;
1249 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1252 spin_unlock_irqrestore(&tp
->lock
, flags
);
1257 #ifdef CONFIG_R8169_VLAN
1259 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1260 struct sk_buff
*skb
)
1262 return (vlan_tx_tag_present(skb
)) ?
1263 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1266 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
1267 struct vlan_group
*grp
)
1269 struct rtl8169_private
*tp
= netdev_priv(dev
);
1270 void __iomem
*ioaddr
= tp
->mmio_addr
;
1271 unsigned long flags
;
1273 spin_lock_irqsave(&tp
->lock
, flags
);
1276 * Do not disable RxVlan on 8110SCd.
1278 if (tp
->vlgrp
|| (tp
->mac_version
== RTL_GIGA_MAC_VER_05
))
1279 tp
->cp_cmd
|= RxVlan
;
1281 tp
->cp_cmd
&= ~RxVlan
;
1282 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1284 spin_unlock_irqrestore(&tp
->lock
, flags
);
1287 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1288 struct sk_buff
*skb
, int polling
)
1290 u32 opts2
= le32_to_cpu(desc
->opts2
);
1291 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1294 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1295 u16 vtag
= swab16(opts2
& 0xffff);
1297 if (likely(polling
))
1298 vlan_gro_receive(&tp
->napi
, vlgrp
, vtag
, skb
);
1300 __vlan_hwaccel_rx(skb
, vlgrp
, vtag
, polling
);
1308 #else /* !CONFIG_R8169_VLAN */
1310 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1311 struct sk_buff
*skb
)
1316 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1317 struct sk_buff
*skb
, int polling
)
1324 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1326 struct rtl8169_private
*tp
= netdev_priv(dev
);
1327 void __iomem
*ioaddr
= tp
->mmio_addr
;
1331 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1332 cmd
->port
= PORT_FIBRE
;
1333 cmd
->transceiver
= XCVR_INTERNAL
;
1335 status
= RTL_R32(TBICSR
);
1336 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1337 cmd
->autoneg
= !!(status
& TBINwEnable
);
1339 cmd
->speed
= SPEED_1000
;
1340 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1345 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1347 struct rtl8169_private
*tp
= netdev_priv(dev
);
1349 return mii_ethtool_gset(&tp
->mii
, cmd
);
1352 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1354 struct rtl8169_private
*tp
= netdev_priv(dev
);
1355 unsigned long flags
;
1358 spin_lock_irqsave(&tp
->lock
, flags
);
1360 rc
= tp
->get_settings(dev
, cmd
);
1362 spin_unlock_irqrestore(&tp
->lock
, flags
);
1366 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1369 struct rtl8169_private
*tp
= netdev_priv(dev
);
1370 unsigned long flags
;
1372 if (regs
->len
> R8169_REGS_SIZE
)
1373 regs
->len
= R8169_REGS_SIZE
;
1375 spin_lock_irqsave(&tp
->lock
, flags
);
1376 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1377 spin_unlock_irqrestore(&tp
->lock
, flags
);
1380 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1382 struct rtl8169_private
*tp
= netdev_priv(dev
);
1384 return tp
->msg_enable
;
1387 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1389 struct rtl8169_private
*tp
= netdev_priv(dev
);
1391 tp
->msg_enable
= value
;
1394 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1401 "tx_single_collisions",
1402 "tx_multi_collisions",
1410 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1414 return ARRAY_SIZE(rtl8169_gstrings
);
1420 static void rtl8169_update_counters(struct net_device
*dev
)
1422 struct rtl8169_private
*tp
= netdev_priv(dev
);
1423 void __iomem
*ioaddr
= tp
->mmio_addr
;
1424 struct rtl8169_counters
*counters
;
1428 struct device
*d
= &tp
->pci_dev
->dev
;
1431 * Some chips are unable to dump tally counters when the receiver
1434 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1437 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1441 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1442 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1443 RTL_W32(CounterAddrLow
, cmd
);
1444 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1447 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1448 /* copy updated counters */
1449 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1455 RTL_W32(CounterAddrLow
, 0);
1456 RTL_W32(CounterAddrHigh
, 0);
1458 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1461 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1462 struct ethtool_stats
*stats
, u64
*data
)
1464 struct rtl8169_private
*tp
= netdev_priv(dev
);
1468 rtl8169_update_counters(dev
);
1470 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1471 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1472 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1473 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1474 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1475 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1476 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1477 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1478 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1479 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1480 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1481 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1482 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1485 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1489 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1494 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1495 .get_drvinfo
= rtl8169_get_drvinfo
,
1496 .get_regs_len
= rtl8169_get_regs_len
,
1497 .get_link
= ethtool_op_get_link
,
1498 .get_settings
= rtl8169_get_settings
,
1499 .set_settings
= rtl8169_set_settings
,
1500 .get_msglevel
= rtl8169_get_msglevel
,
1501 .set_msglevel
= rtl8169_set_msglevel
,
1502 .get_rx_csum
= rtl8169_get_rx_csum
,
1503 .set_rx_csum
= rtl8169_set_rx_csum
,
1504 .set_tx_csum
= ethtool_op_set_tx_csum
,
1505 .set_sg
= ethtool_op_set_sg
,
1506 .set_tso
= ethtool_op_set_tso
,
1507 .get_regs
= rtl8169_get_regs
,
1508 .get_wol
= rtl8169_get_wol
,
1509 .set_wol
= rtl8169_set_wol
,
1510 .get_strings
= rtl8169_get_strings
,
1511 .get_sset_count
= rtl8169_get_sset_count
,
1512 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1515 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1516 void __iomem
*ioaddr
)
1519 * The driver currently handles the 8168Bf and the 8168Be identically
1520 * but they can be identified more specifically through the test below
1523 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1525 * Same thing for the 8101Eb and the 8101Ec:
1527 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1529 static const struct {
1535 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1536 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1537 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1539 /* 8168DP family. */
1540 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1541 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1544 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1545 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1546 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1547 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1548 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1549 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1550 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1551 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1552 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1555 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1556 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1557 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1558 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1561 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1562 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1563 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1564 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1565 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1566 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1567 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1568 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1569 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1570 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1571 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1572 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1573 /* FIXME: where did these entries come from ? -- FR */
1574 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1575 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1578 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1579 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1580 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1581 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1582 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1583 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1586 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1590 reg
= RTL_R32(TxConfig
);
1591 while ((reg
& p
->mask
) != p
->val
)
1593 tp
->mac_version
= p
->mac_version
;
1596 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1598 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1606 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1607 const struct phy_reg
*regs
, int len
)
1610 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1615 #define PHY_READ 0x00000000
1616 #define PHY_DATA_OR 0x10000000
1617 #define PHY_DATA_AND 0x20000000
1618 #define PHY_BJMPN 0x30000000
1619 #define PHY_READ_EFUSE 0x40000000
1620 #define PHY_READ_MAC_BYTE 0x50000000
1621 #define PHY_WRITE_MAC_BYTE 0x60000000
1622 #define PHY_CLEAR_READCOUNT 0x70000000
1623 #define PHY_WRITE 0x80000000
1624 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1625 #define PHY_COMP_EQ_SKIPN 0xa0000000
1626 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1627 #define PHY_WRITE_PREVIOUS 0xc0000000
1628 #define PHY_SKIPN 0xd0000000
1629 #define PHY_DELAY_MS 0xe0000000
1630 #define PHY_WRITE_ERI_WORD 0xf0000000
1633 rtl_phy_write_fw(struct rtl8169_private
*tp
, const struct firmware
*fw
)
1635 __le32
*phytable
= (__le32
*)fw
->data
;
1636 struct net_device
*dev
= tp
->dev
;
1637 size_t index
, fw_size
= fw
->size
/ sizeof(*phytable
);
1640 if (fw
->size
% sizeof(*phytable
)) {
1641 netif_err(tp
, probe
, dev
, "odd sized firmware %zd\n", fw
->size
);
1645 for (index
= 0; index
< fw_size
; index
++) {
1646 u32 action
= le32_to_cpu(phytable
[index
]);
1647 u32 regno
= (action
& 0x0fff0000) >> 16;
1649 switch(action
& 0xf0000000) {
1653 case PHY_READ_EFUSE
:
1654 case PHY_CLEAR_READCOUNT
:
1656 case PHY_WRITE_PREVIOUS
:
1661 if (regno
> index
) {
1662 netif_err(tp
, probe
, tp
->dev
,
1663 "Out of range of firmware\n");
1667 case PHY_READCOUNT_EQ_SKIP
:
1668 if (index
+ 2 >= fw_size
) {
1669 netif_err(tp
, probe
, tp
->dev
,
1670 "Out of range of firmware\n");
1674 case PHY_COMP_EQ_SKIPN
:
1675 case PHY_COMP_NEQ_SKIPN
:
1677 if (index
+ 1 + regno
>= fw_size
) {
1678 netif_err(tp
, probe
, tp
->dev
,
1679 "Out of range of firmware\n");
1684 case PHY_READ_MAC_BYTE
:
1685 case PHY_WRITE_MAC_BYTE
:
1686 case PHY_WRITE_ERI_WORD
:
1688 netif_err(tp
, probe
, tp
->dev
,
1689 "Invalid action 0x%08x\n", action
);
1697 for (index
= 0; index
< fw_size
; ) {
1698 u32 action
= le32_to_cpu(phytable
[index
]);
1699 u32 data
= action
& 0x0000ffff;
1700 u32 regno
= (action
& 0x0fff0000) >> 16;
1705 switch(action
& 0xf0000000) {
1707 predata
= rtl_readphy(tp
, regno
);
1722 case PHY_READ_EFUSE
:
1723 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
1726 case PHY_CLEAR_READCOUNT
:
1731 rtl_writephy(tp
, regno
, data
);
1734 case PHY_READCOUNT_EQ_SKIP
:
1740 case PHY_COMP_EQ_SKIPN
:
1741 if (predata
== data
)
1745 case PHY_COMP_NEQ_SKIPN
:
1746 if (predata
!= data
)
1750 case PHY_WRITE_PREVIOUS
:
1751 rtl_writephy(tp
, regno
, predata
);
1762 case PHY_READ_MAC_BYTE
:
1763 case PHY_WRITE_MAC_BYTE
:
1764 case PHY_WRITE_ERI_WORD
:
1771 static void rtl_release_firmware(struct rtl8169_private
*tp
)
1773 release_firmware(tp
->fw
);
1777 static int rtl_apply_firmware(struct rtl8169_private
*tp
, const char *fw_name
)
1779 const struct firmware
**fw
= &tp
->fw
;
1783 rc
= request_firmware(fw
, fw_name
, &tp
->pci_dev
->dev
);
1788 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1789 rtl_phy_write_fw(tp
, *fw
);
1794 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
1796 static const struct phy_reg phy_reg_init
[] = {
1858 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1861 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
1863 static const struct phy_reg phy_reg_init
[] = {
1869 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1872 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
1874 struct pci_dev
*pdev
= tp
->pci_dev
;
1875 u16 vendor_id
, device_id
;
1877 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1878 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1880 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1883 rtl_writephy(tp
, 0x1f, 0x0001);
1884 rtl_writephy(tp
, 0x10, 0xf01b);
1885 rtl_writephy(tp
, 0x1f, 0x0000);
1888 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
1890 static const struct phy_reg phy_reg_init
[] = {
1930 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1932 rtl8169scd_hw_phy_config_quirk(tp
);
1935 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
1937 static const struct phy_reg phy_reg_init
[] = {
1985 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1988 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
1990 static const struct phy_reg phy_reg_init
[] = {
1995 rtl_writephy(tp
, 0x1f, 0x0001);
1996 rtl_patchphy(tp
, 0x16, 1 << 0);
1998 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2001 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2003 static const struct phy_reg phy_reg_init
[] = {
2009 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2012 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2014 static const struct phy_reg phy_reg_init
[] = {
2022 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2025 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2027 static const struct phy_reg phy_reg_init
[] = {
2033 rtl_writephy(tp
, 0x1f, 0x0000);
2034 rtl_patchphy(tp
, 0x14, 1 << 5);
2035 rtl_patchphy(tp
, 0x0d, 1 << 5);
2037 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2040 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2042 static const struct phy_reg phy_reg_init
[] = {
2062 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2064 rtl_patchphy(tp
, 0x14, 1 << 5);
2065 rtl_patchphy(tp
, 0x0d, 1 << 5);
2066 rtl_writephy(tp
, 0x1f, 0x0000);
2069 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2071 static const struct phy_reg phy_reg_init
[] = {
2089 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2091 rtl_patchphy(tp
, 0x16, 1 << 0);
2092 rtl_patchphy(tp
, 0x14, 1 << 5);
2093 rtl_patchphy(tp
, 0x0d, 1 << 5);
2094 rtl_writephy(tp
, 0x1f, 0x0000);
2097 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2099 static const struct phy_reg phy_reg_init
[] = {
2111 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2113 rtl_patchphy(tp
, 0x16, 1 << 0);
2114 rtl_patchphy(tp
, 0x14, 1 << 5);
2115 rtl_patchphy(tp
, 0x0d, 1 << 5);
2116 rtl_writephy(tp
, 0x1f, 0x0000);
2119 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2121 rtl8168c_3_hw_phy_config(tp
);
2124 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2126 static const struct phy_reg phy_reg_init_0
[] = {
2127 /* Channel Estimation */
2148 * enhance line driver power
2157 * Can not link to 1Gbps with bad cable
2158 * Decrease SNR threshold form 21.07dB to 19.04dB
2166 void __iomem
*ioaddr
= tp
->mmio_addr
;
2168 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2172 * Fine Tune Switching regulator parameter
2174 rtl_writephy(tp
, 0x1f, 0x0002);
2175 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2176 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2178 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2179 static const struct phy_reg phy_reg_init
[] = {
2189 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2191 val
= rtl_readphy(tp
, 0x0d);
2193 if ((val
& 0x00ff) != 0x006c) {
2194 static const u32 set
[] = {
2195 0x0065, 0x0066, 0x0067, 0x0068,
2196 0x0069, 0x006a, 0x006b, 0x006c
2200 rtl_writephy(tp
, 0x1f, 0x0002);
2203 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2204 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2207 static const struct phy_reg phy_reg_init
[] = {
2215 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2218 /* RSET couple improve */
2219 rtl_writephy(tp
, 0x1f, 0x0002);
2220 rtl_patchphy(tp
, 0x0d, 0x0300);
2221 rtl_patchphy(tp
, 0x0f, 0x0010);
2223 /* Fine tune PLL performance */
2224 rtl_writephy(tp
, 0x1f, 0x0002);
2225 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2226 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2228 rtl_writephy(tp
, 0x1f, 0x0005);
2229 rtl_writephy(tp
, 0x05, 0x001b);
2230 if ((rtl_readphy(tp
, 0x06) != 0xbf00) ||
2231 (rtl_apply_firmware(tp
, FIRMWARE_8168D_1
) < 0)) {
2232 netif_warn(tp
, probe
, tp
->dev
, "unable to apply firmware patch\n");
2235 rtl_writephy(tp
, 0x1f, 0x0000);
2238 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2240 static const struct phy_reg phy_reg_init_0
[] = {
2241 /* Channel Estimation */
2262 * enhance line driver power
2271 * Can not link to 1Gbps with bad cable
2272 * Decrease SNR threshold form 21.07dB to 19.04dB
2280 void __iomem
*ioaddr
= tp
->mmio_addr
;
2282 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2284 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2285 static const struct phy_reg phy_reg_init
[] = {
2296 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2298 val
= rtl_readphy(tp
, 0x0d);
2299 if ((val
& 0x00ff) != 0x006c) {
2300 static const u32 set
[] = {
2301 0x0065, 0x0066, 0x0067, 0x0068,
2302 0x0069, 0x006a, 0x006b, 0x006c
2306 rtl_writephy(tp
, 0x1f, 0x0002);
2309 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2310 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2313 static const struct phy_reg phy_reg_init
[] = {
2321 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2324 /* Fine tune PLL performance */
2325 rtl_writephy(tp
, 0x1f, 0x0002);
2326 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2327 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2329 /* Switching regulator Slew rate */
2330 rtl_writephy(tp
, 0x1f, 0x0002);
2331 rtl_patchphy(tp
, 0x0f, 0x0017);
2333 rtl_writephy(tp
, 0x1f, 0x0005);
2334 rtl_writephy(tp
, 0x05, 0x001b);
2335 if ((rtl_readphy(tp
, 0x06) != 0xb300) ||
2336 (rtl_apply_firmware(tp
, FIRMWARE_8168D_2
) < 0)) {
2337 netif_warn(tp
, probe
, tp
->dev
, "unable to apply firmware patch\n");
2340 rtl_writephy(tp
, 0x1f, 0x0000);
2343 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2345 static const struct phy_reg phy_reg_init
[] = {
2401 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2404 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2406 static const struct phy_reg phy_reg_init
[] = {
2416 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2417 rtl_patchphy(tp
, 0x0d, 1 << 5);
2420 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
2422 static const struct phy_reg phy_reg_init
[] = {
2429 rtl_writephy(tp
, 0x1f, 0x0000);
2430 rtl_patchphy(tp
, 0x11, 1 << 12);
2431 rtl_patchphy(tp
, 0x19, 1 << 13);
2432 rtl_patchphy(tp
, 0x10, 1 << 15);
2434 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2437 static void rtl_hw_phy_config(struct net_device
*dev
)
2439 struct rtl8169_private
*tp
= netdev_priv(dev
);
2441 rtl8169_print_mac_version(tp
);
2443 switch (tp
->mac_version
) {
2444 case RTL_GIGA_MAC_VER_01
:
2446 case RTL_GIGA_MAC_VER_02
:
2447 case RTL_GIGA_MAC_VER_03
:
2448 rtl8169s_hw_phy_config(tp
);
2450 case RTL_GIGA_MAC_VER_04
:
2451 rtl8169sb_hw_phy_config(tp
);
2453 case RTL_GIGA_MAC_VER_05
:
2454 rtl8169scd_hw_phy_config(tp
);
2456 case RTL_GIGA_MAC_VER_06
:
2457 rtl8169sce_hw_phy_config(tp
);
2459 case RTL_GIGA_MAC_VER_07
:
2460 case RTL_GIGA_MAC_VER_08
:
2461 case RTL_GIGA_MAC_VER_09
:
2462 rtl8102e_hw_phy_config(tp
);
2464 case RTL_GIGA_MAC_VER_11
:
2465 rtl8168bb_hw_phy_config(tp
);
2467 case RTL_GIGA_MAC_VER_12
:
2468 rtl8168bef_hw_phy_config(tp
);
2470 case RTL_GIGA_MAC_VER_17
:
2471 rtl8168bef_hw_phy_config(tp
);
2473 case RTL_GIGA_MAC_VER_18
:
2474 rtl8168cp_1_hw_phy_config(tp
);
2476 case RTL_GIGA_MAC_VER_19
:
2477 rtl8168c_1_hw_phy_config(tp
);
2479 case RTL_GIGA_MAC_VER_20
:
2480 rtl8168c_2_hw_phy_config(tp
);
2482 case RTL_GIGA_MAC_VER_21
:
2483 rtl8168c_3_hw_phy_config(tp
);
2485 case RTL_GIGA_MAC_VER_22
:
2486 rtl8168c_4_hw_phy_config(tp
);
2488 case RTL_GIGA_MAC_VER_23
:
2489 case RTL_GIGA_MAC_VER_24
:
2490 rtl8168cp_2_hw_phy_config(tp
);
2492 case RTL_GIGA_MAC_VER_25
:
2493 rtl8168d_1_hw_phy_config(tp
);
2495 case RTL_GIGA_MAC_VER_26
:
2496 rtl8168d_2_hw_phy_config(tp
);
2498 case RTL_GIGA_MAC_VER_27
:
2499 rtl8168d_3_hw_phy_config(tp
);
2501 case RTL_GIGA_MAC_VER_28
:
2502 rtl8168d_4_hw_phy_config(tp
);
2510 static void rtl8169_phy_timer(unsigned long __opaque
)
2512 struct net_device
*dev
= (struct net_device
*)__opaque
;
2513 struct rtl8169_private
*tp
= netdev_priv(dev
);
2514 struct timer_list
*timer
= &tp
->timer
;
2515 void __iomem
*ioaddr
= tp
->mmio_addr
;
2516 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2518 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2520 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
2523 spin_lock_irq(&tp
->lock
);
2525 if (tp
->phy_reset_pending(tp
)) {
2527 * A busy loop could burn quite a few cycles on nowadays CPU.
2528 * Let's delay the execution of the timer for a few ticks.
2534 if (tp
->link_ok(ioaddr
))
2537 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
2539 tp
->phy_reset_enable(tp
);
2542 mod_timer(timer
, jiffies
+ timeout
);
2544 spin_unlock_irq(&tp
->lock
);
2547 static inline void rtl8169_delete_timer(struct net_device
*dev
)
2549 struct rtl8169_private
*tp
= netdev_priv(dev
);
2550 struct timer_list
*timer
= &tp
->timer
;
2552 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2555 del_timer_sync(timer
);
2558 static inline void rtl8169_request_timer(struct net_device
*dev
)
2560 struct rtl8169_private
*tp
= netdev_priv(dev
);
2561 struct timer_list
*timer
= &tp
->timer
;
2563 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2566 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2569 #ifdef CONFIG_NET_POLL_CONTROLLER
2571 * Polling 'interrupt' - used by things like netconsole to send skbs
2572 * without having to re-enable interrupts. It's not called while
2573 * the interrupt routine is executing.
2575 static void rtl8169_netpoll(struct net_device
*dev
)
2577 struct rtl8169_private
*tp
= netdev_priv(dev
);
2578 struct pci_dev
*pdev
= tp
->pci_dev
;
2580 disable_irq(pdev
->irq
);
2581 rtl8169_interrupt(pdev
->irq
, dev
);
2582 enable_irq(pdev
->irq
);
2586 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2587 void __iomem
*ioaddr
)
2590 pci_release_regions(pdev
);
2591 pci_clear_mwi(pdev
);
2592 pci_disable_device(pdev
);
2596 static void rtl8169_phy_reset(struct net_device
*dev
,
2597 struct rtl8169_private
*tp
)
2601 tp
->phy_reset_enable(tp
);
2602 for (i
= 0; i
< 100; i
++) {
2603 if (!tp
->phy_reset_pending(tp
))
2607 netif_err(tp
, link
, dev
, "PHY reset failed\n");
2610 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2612 void __iomem
*ioaddr
= tp
->mmio_addr
;
2614 rtl_hw_phy_config(dev
);
2616 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2617 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2621 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2623 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2624 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2626 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2627 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2629 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2630 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
2633 rtl8169_phy_reset(dev
, tp
);
2636 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2637 * only 8101. Don't panic.
2639 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
2641 if (RTL_R8(PHYstatus
) & TBI_Enable
)
2642 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
2645 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2647 void __iomem
*ioaddr
= tp
->mmio_addr
;
2651 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2652 high
= addr
[4] | (addr
[5] << 8);
2654 spin_lock_irq(&tp
->lock
);
2656 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2658 RTL_W32(MAC4
, high
);
2664 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2666 spin_unlock_irq(&tp
->lock
);
2669 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2671 struct rtl8169_private
*tp
= netdev_priv(dev
);
2672 struct sockaddr
*addr
= p
;
2674 if (!is_valid_ether_addr(addr
->sa_data
))
2675 return -EADDRNOTAVAIL
;
2677 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2679 rtl_rar_set(tp
, dev
->dev_addr
);
2684 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2686 struct rtl8169_private
*tp
= netdev_priv(dev
);
2687 struct mii_ioctl_data
*data
= if_mii(ifr
);
2689 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2692 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2696 data
->phy_id
= 32; /* Internal PHY */
2700 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
2704 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
2710 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2715 static const struct rtl_cfg_info
{
2716 void (*hw_start
)(struct net_device
*);
2717 unsigned int region
;
2723 } rtl_cfg_infos
[] = {
2725 .hw_start
= rtl_hw_start_8169
,
2728 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2729 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2730 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2731 .features
= RTL_FEATURE_GMII
,
2732 .default_ver
= RTL_GIGA_MAC_VER_01
,
2735 .hw_start
= rtl_hw_start_8168
,
2738 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2739 TxErr
| TxOK
| RxOK
| RxErr
,
2740 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2741 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2742 .default_ver
= RTL_GIGA_MAC_VER_11
,
2745 .hw_start
= rtl_hw_start_8101
,
2748 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2749 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2750 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2751 .features
= RTL_FEATURE_MSI
,
2752 .default_ver
= RTL_GIGA_MAC_VER_13
,
2756 /* Cfg9346_Unlock assumed. */
2757 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2758 const struct rtl_cfg_info
*cfg
)
2763 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2764 if (cfg
->features
& RTL_FEATURE_MSI
) {
2765 if (pci_enable_msi(pdev
)) {
2766 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2769 msi
= RTL_FEATURE_MSI
;
2772 RTL_W8(Config2
, cfg2
);
2776 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2778 if (tp
->features
& RTL_FEATURE_MSI
) {
2779 pci_disable_msi(pdev
);
2780 tp
->features
&= ~RTL_FEATURE_MSI
;
2784 static const struct net_device_ops rtl8169_netdev_ops
= {
2785 .ndo_open
= rtl8169_open
,
2786 .ndo_stop
= rtl8169_close
,
2787 .ndo_get_stats
= rtl8169_get_stats
,
2788 .ndo_start_xmit
= rtl8169_start_xmit
,
2789 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2790 .ndo_validate_addr
= eth_validate_addr
,
2791 .ndo_change_mtu
= rtl8169_change_mtu
,
2792 .ndo_set_mac_address
= rtl_set_mac_address
,
2793 .ndo_do_ioctl
= rtl8169_ioctl
,
2794 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2795 #ifdef CONFIG_R8169_VLAN
2796 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
2798 #ifdef CONFIG_NET_POLL_CONTROLLER
2799 .ndo_poll_controller
= rtl8169_netpoll
,
2804 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
2806 struct mdio_ops
*ops
= &tp
->mdio_ops
;
2808 switch (tp
->mac_version
) {
2809 case RTL_GIGA_MAC_VER_27
:
2810 ops
->write
= r8168dp_1_mdio_write
;
2811 ops
->read
= r8168dp_1_mdio_read
;
2813 case RTL_GIGA_MAC_VER_28
:
2814 ops
->write
= r8168dp_2_mdio_write
;
2815 ops
->read
= r8168dp_2_mdio_read
;
2818 ops
->write
= r8169_mdio_write
;
2819 ops
->read
= r8169_mdio_read
;
2824 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
2826 rtl_writephy(tp
, 0x1f, 0x0000);
2827 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2830 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
2832 rtl_writephy(tp
, 0x1f, 0x0000);
2833 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
2836 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
2838 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
2839 rtl_writephy(tp
, 0x1f, 0x0000);
2840 rtl_writephy(tp
, MII_BMCR
, 0x0000);
2844 r810x_phy_power_down(tp
);
2847 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
2849 r810x_phy_power_up(tp
);
2852 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
2854 rtl_writephy(tp
, 0x1f, 0x0000);
2855 rtl_writephy(tp
, 0x0e, 0x0000);
2856 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
2859 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
2861 rtl_writephy(tp
, 0x1f, 0x0000);
2862 rtl_writephy(tp
, 0x0e, 0x0200);
2863 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2866 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
2868 void __iomem
*ioaddr
= tp
->mmio_addr
;
2870 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
)
2873 if (((tp
->mac_version
== RTL_GIGA_MAC_VER_23
) ||
2874 (tp
->mac_version
== RTL_GIGA_MAC_VER_24
)) &&
2875 (RTL_R16(CPlusCmd
) & ASF
)) {
2879 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
2880 rtl_writephy(tp
, 0x1f, 0x0000);
2881 rtl_writephy(tp
, MII_BMCR
, 0x0000);
2883 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
2884 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
2888 r8168_phy_power_down(tp
);
2890 switch (tp
->mac_version
) {
2891 case RTL_GIGA_MAC_VER_25
:
2892 case RTL_GIGA_MAC_VER_26
:
2893 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
2898 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
2900 void __iomem
*ioaddr
= tp
->mmio_addr
;
2902 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
)
2905 switch (tp
->mac_version
) {
2906 case RTL_GIGA_MAC_VER_25
:
2907 case RTL_GIGA_MAC_VER_26
:
2908 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
2912 r8168_phy_power_up(tp
);
2915 static void rtl_pll_power_op(struct rtl8169_private
*tp
,
2916 void (*op
)(struct rtl8169_private
*))
2922 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
2924 rtl_pll_power_op(tp
, tp
->pll_power_ops
.down
);
2927 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
2929 rtl_pll_power_op(tp
, tp
->pll_power_ops
.up
);
2932 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
2934 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
2936 switch (tp
->mac_version
) {
2937 case RTL_GIGA_MAC_VER_07
:
2938 case RTL_GIGA_MAC_VER_08
:
2939 case RTL_GIGA_MAC_VER_09
:
2940 case RTL_GIGA_MAC_VER_10
:
2941 case RTL_GIGA_MAC_VER_16
:
2942 ops
->down
= r810x_pll_power_down
;
2943 ops
->up
= r810x_pll_power_up
;
2946 case RTL_GIGA_MAC_VER_11
:
2947 case RTL_GIGA_MAC_VER_12
:
2948 case RTL_GIGA_MAC_VER_17
:
2949 case RTL_GIGA_MAC_VER_18
:
2950 case RTL_GIGA_MAC_VER_19
:
2951 case RTL_GIGA_MAC_VER_20
:
2952 case RTL_GIGA_MAC_VER_21
:
2953 case RTL_GIGA_MAC_VER_22
:
2954 case RTL_GIGA_MAC_VER_23
:
2955 case RTL_GIGA_MAC_VER_24
:
2956 case RTL_GIGA_MAC_VER_25
:
2957 case RTL_GIGA_MAC_VER_26
:
2958 case RTL_GIGA_MAC_VER_27
:
2959 case RTL_GIGA_MAC_VER_28
:
2960 ops
->down
= r8168_pll_power_down
;
2961 ops
->up
= r8168_pll_power_up
;
2971 static int __devinit
2972 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2974 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
2975 const unsigned int region
= cfg
->region
;
2976 struct rtl8169_private
*tp
;
2977 struct mii_if_info
*mii
;
2978 struct net_device
*dev
;
2979 void __iomem
*ioaddr
;
2983 if (netif_msg_drv(&debug
)) {
2984 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
2985 MODULENAME
, RTL8169_VERSION
);
2988 dev
= alloc_etherdev(sizeof (*tp
));
2990 if (netif_msg_drv(&debug
))
2991 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
2996 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2997 dev
->netdev_ops
= &rtl8169_netdev_ops
;
2998 tp
= netdev_priv(dev
);
3001 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3005 mii
->mdio_read
= rtl_mdio_read
;
3006 mii
->mdio_write
= rtl_mdio_write
;
3007 mii
->phy_id_mask
= 0x1f;
3008 mii
->reg_num_mask
= 0x1f;
3009 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3011 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3012 rc
= pci_enable_device(pdev
);
3014 netif_err(tp
, probe
, dev
, "enable failure\n");
3015 goto err_out_free_dev_1
;
3018 if (pci_set_mwi(pdev
) < 0)
3019 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3021 /* make sure PCI base addr 1 is MMIO */
3022 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3023 netif_err(tp
, probe
, dev
,
3024 "region #%d not an MMIO resource, aborting\n",
3030 /* check for weird/broken PCI region reporting */
3031 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3032 netif_err(tp
, probe
, dev
,
3033 "Invalid PCI region size(s), aborting\n");
3038 rc
= pci_request_regions(pdev
, MODULENAME
);
3040 netif_err(tp
, probe
, dev
, "could not request regions\n");
3044 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
3046 if ((sizeof(dma_addr_t
) > 4) &&
3047 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3048 tp
->cp_cmd
|= PCIDAC
;
3049 dev
->features
|= NETIF_F_HIGHDMA
;
3051 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3053 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3054 goto err_out_free_res_3
;
3058 /* ioremap MMIO region */
3059 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3061 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3063 goto err_out_free_res_3
;
3066 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3068 netif_info(tp
, probe
, dev
, "no PCI Express capability\n");
3070 RTL_W16(IntrMask
, 0x0000);
3072 /* Soft reset the chip. */
3073 RTL_W8(ChipCmd
, CmdReset
);
3075 /* Check that the chip has finished the reset. */
3076 for (i
= 0; i
< 100; i
++) {
3077 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3079 msleep_interruptible(1);
3082 RTL_W16(IntrStatus
, 0xffff);
3084 pci_set_master(pdev
);
3086 /* Identify chip attached to board */
3087 rtl8169_get_mac_version(tp
, ioaddr
);
3089 rtl_init_mdio_ops(tp
);
3090 rtl_init_pll_power_ops(tp
);
3092 /* Use appropriate default if unknown */
3093 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
3094 netif_notice(tp
, probe
, dev
,
3095 "unknown MAC, using family default\n");
3096 tp
->mac_version
= cfg
->default_ver
;
3099 rtl8169_print_mac_version(tp
);
3101 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
3102 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
3105 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
3107 "driver bug, MAC version not found in rtl_chip_info\n");
3112 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3113 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3114 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3115 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3116 tp
->features
|= RTL_FEATURE_WOL
;
3117 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3118 tp
->features
|= RTL_FEATURE_WOL
;
3119 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3120 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3122 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3123 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3124 tp
->set_speed
= rtl8169_set_speed_tbi
;
3125 tp
->get_settings
= rtl8169_gset_tbi
;
3126 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3127 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3128 tp
->link_ok
= rtl8169_tbi_link_ok
;
3129 tp
->do_ioctl
= rtl_tbi_ioctl
;
3131 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
3133 tp
->set_speed
= rtl8169_set_speed_xmii
;
3134 tp
->get_settings
= rtl8169_gset_xmii
;
3135 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3136 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3137 tp
->link_ok
= rtl8169_xmii_link_ok
;
3138 tp
->do_ioctl
= rtl_xmii_ioctl
;
3141 spin_lock_init(&tp
->lock
);
3143 tp
->mmio_addr
= ioaddr
;
3145 /* Get MAC address */
3146 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3147 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3148 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3150 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3151 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3152 dev
->irq
= pdev
->irq
;
3153 dev
->base_addr
= (unsigned long) ioaddr
;
3155 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3157 #ifdef CONFIG_R8169_VLAN
3158 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3160 dev
->features
|= NETIF_F_GRO
;
3162 tp
->intr_mask
= 0xffff;
3163 tp
->hw_start
= cfg
->hw_start
;
3164 tp
->intr_event
= cfg
->intr_event
;
3165 tp
->napi_event
= cfg
->napi_event
;
3167 init_timer(&tp
->timer
);
3168 tp
->timer
.data
= (unsigned long) dev
;
3169 tp
->timer
.function
= rtl8169_phy_timer
;
3171 rc
= register_netdev(dev
);
3175 pci_set_drvdata(pdev
, dev
);
3177 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3178 rtl_chip_info
[tp
->chipset
].name
,
3179 dev
->base_addr
, dev
->dev_addr
,
3180 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3182 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
) ||
3183 (tp
->mac_version
== RTL_GIGA_MAC_VER_28
)) {
3184 rtl8168_driver_start(tp
);
3187 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3189 if (pci_dev_run_wake(pdev
))
3190 pm_runtime_put_noidle(&pdev
->dev
);
3196 rtl_disable_msi(pdev
, tp
);
3199 pci_release_regions(pdev
);
3201 pci_clear_mwi(pdev
);
3202 pci_disable_device(pdev
);
3208 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3210 struct net_device
*dev
= pci_get_drvdata(pdev
);
3211 struct rtl8169_private
*tp
= netdev_priv(dev
);
3213 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
) ||
3214 (tp
->mac_version
== RTL_GIGA_MAC_VER_28
)) {
3215 rtl8168_driver_stop(tp
);
3218 cancel_delayed_work_sync(&tp
->task
);
3220 rtl_release_firmware(tp
);
3222 unregister_netdev(dev
);
3224 if (pci_dev_run_wake(pdev
))
3225 pm_runtime_get_noresume(&pdev
->dev
);
3227 /* restore original MAC address */
3228 rtl_rar_set(tp
, dev
->perm_addr
);
3230 rtl_disable_msi(pdev
, tp
);
3231 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3232 pci_set_drvdata(pdev
, NULL
);
3235 static int rtl8169_open(struct net_device
*dev
)
3237 struct rtl8169_private
*tp
= netdev_priv(dev
);
3238 void __iomem
*ioaddr
= tp
->mmio_addr
;
3239 struct pci_dev
*pdev
= tp
->pci_dev
;
3240 int retval
= -ENOMEM
;
3242 pm_runtime_get_sync(&pdev
->dev
);
3245 * Rx and Tx desscriptors needs 256 bytes alignment.
3246 * dma_alloc_coherent provides more.
3248 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3249 &tp
->TxPhyAddr
, GFP_KERNEL
);
3250 if (!tp
->TxDescArray
)
3251 goto err_pm_runtime_put
;
3253 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3254 &tp
->RxPhyAddr
, GFP_KERNEL
);
3255 if (!tp
->RxDescArray
)
3258 retval
= rtl8169_init_ring(dev
);
3262 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3266 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3267 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3270 goto err_release_ring_2
;
3272 napi_enable(&tp
->napi
);
3274 rtl8169_init_phy(dev
, tp
);
3277 * Pretend we are using VLANs; This bypasses a nasty bug where
3278 * Interrupts stop flowing on high load on 8110SCd controllers.
3280 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3281 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | RxVlan
);
3283 rtl_pll_power_up(tp
);
3287 rtl8169_request_timer(dev
);
3289 tp
->saved_wolopts
= 0;
3290 pm_runtime_put_noidle(&pdev
->dev
);
3292 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3297 rtl8169_rx_clear(tp
);
3299 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3301 tp
->RxDescArray
= NULL
;
3303 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3305 tp
->TxDescArray
= NULL
;
3307 pm_runtime_put_noidle(&pdev
->dev
);
3311 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3313 void __iomem
*ioaddr
= tp
->mmio_addr
;
3315 /* Disable interrupts */
3316 rtl8169_irq_mask_and_ack(ioaddr
);
3318 if (tp
->mac_version
== RTL_GIGA_MAC_VER_28
) {
3319 while (RTL_R8(TxPoll
) & NPQ
)
3324 /* Reset the chipset */
3325 RTL_W8(ChipCmd
, CmdReset
);
3331 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3333 void __iomem
*ioaddr
= tp
->mmio_addr
;
3334 u32 cfg
= rtl8169_rx_config
;
3336 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3337 RTL_W32(RxConfig
, cfg
);
3339 /* Set DMA burst size and Interframe Gap Time */
3340 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3341 (InterFrameGap
<< TxInterFrameGapShift
));
3344 static void rtl_hw_start(struct net_device
*dev
)
3346 struct rtl8169_private
*tp
= netdev_priv(dev
);
3347 void __iomem
*ioaddr
= tp
->mmio_addr
;
3350 /* Soft reset the chip. */
3351 RTL_W8(ChipCmd
, CmdReset
);
3353 /* Check that the chip has finished the reset. */
3354 for (i
= 0; i
< 100; i
++) {
3355 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3357 msleep_interruptible(1);
3362 netif_start_queue(dev
);
3366 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3367 void __iomem
*ioaddr
)
3370 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3371 * register to be written before TxDescAddrLow to work.
3372 * Switching from MMIO to I/O access fixes the issue as well.
3374 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3375 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3376 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3377 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3380 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3384 cmd
= RTL_R16(CPlusCmd
);
3385 RTL_W16(CPlusCmd
, cmd
);
3389 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3391 /* Low hurts. Let's disable the filtering. */
3392 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3395 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3397 static const struct {
3402 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3403 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3404 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3405 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3410 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3411 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3412 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3413 RTL_W32(0x7c, p
->val
);
3419 static void rtl_hw_start_8169(struct net_device
*dev
)
3421 struct rtl8169_private
*tp
= netdev_priv(dev
);
3422 void __iomem
*ioaddr
= tp
->mmio_addr
;
3423 struct pci_dev
*pdev
= tp
->pci_dev
;
3425 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3426 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3427 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3430 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3431 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3432 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3433 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3434 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3435 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3437 RTL_W8(EarlyTxThres
, NoEarlyTx
);
3439 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3441 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3442 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3443 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3444 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3445 rtl_set_rx_tx_config_registers(tp
);
3447 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3449 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3450 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
3451 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3452 "Bit-3 and bit-14 MUST be 1\n");
3453 tp
->cp_cmd
|= (1 << 14);
3456 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3458 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3461 * Undocumented corner. Supposedly:
3462 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3464 RTL_W16(IntrMitigate
, 0x0000);
3466 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3468 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
3469 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
3470 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
3471 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
3472 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3473 rtl_set_rx_tx_config_registers(tp
);
3476 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3478 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3481 RTL_W32(RxMissed
, 0);
3483 rtl_set_rx_mode(dev
);
3485 /* no early-rx interrupts */
3486 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3488 /* Enable all known interrupts by setting the interrupt mask. */
3489 RTL_W16(IntrMask
, tp
->intr_event
);
3492 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3494 struct net_device
*dev
= pci_get_drvdata(pdev
);
3495 struct rtl8169_private
*tp
= netdev_priv(dev
);
3496 int cap
= tp
->pcie_cap
;
3501 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3502 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3503 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3507 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
3511 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3512 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
3515 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
3517 rtl_csi_access_enable(ioaddr
, 0x17000000);
3520 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
3522 rtl_csi_access_enable(ioaddr
, 0x27000000);
3526 unsigned int offset
;
3531 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
3536 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3537 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3542 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3544 struct net_device
*dev
= pci_get_drvdata(pdev
);
3545 struct rtl8169_private
*tp
= netdev_priv(dev
);
3546 int cap
= tp
->pcie_cap
;
3551 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3552 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3553 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3557 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
3559 struct net_device
*dev
= pci_get_drvdata(pdev
);
3560 struct rtl8169_private
*tp
= netdev_priv(dev
);
3561 int cap
= tp
->pcie_cap
;
3566 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3567 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
3568 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3572 #define R8168_CPCMD_QUIRK_MASK (\
3583 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3585 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3587 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3589 rtl_tx_performance_tweak(pdev
,
3590 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3593 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3595 rtl_hw_start_8168bb(ioaddr
, pdev
);
3597 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3599 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3602 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3604 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3606 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3608 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3610 rtl_disable_clock_request(pdev
);
3612 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3615 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3617 static const struct ephy_info e_info_8168cp
[] = {
3618 { 0x01, 0, 0x0001 },
3619 { 0x02, 0x0800, 0x1000 },
3620 { 0x03, 0, 0x0042 },
3621 { 0x06, 0x0080, 0x0000 },
3625 rtl_csi_access_enable_2(ioaddr
);
3627 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3629 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3632 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3634 rtl_csi_access_enable_2(ioaddr
);
3636 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3638 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3640 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3643 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3645 rtl_csi_access_enable_2(ioaddr
);
3647 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3650 RTL_W8(DBG_REG
, 0x20);
3652 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3654 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3656 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3659 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3661 static const struct ephy_info e_info_8168c_1
[] = {
3662 { 0x02, 0x0800, 0x1000 },
3663 { 0x03, 0, 0x0002 },
3664 { 0x06, 0x0080, 0x0000 }
3667 rtl_csi_access_enable_2(ioaddr
);
3669 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3671 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3673 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3676 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3678 static const struct ephy_info e_info_8168c_2
[] = {
3679 { 0x01, 0, 0x0001 },
3680 { 0x03, 0x0400, 0x0220 }
3683 rtl_csi_access_enable_2(ioaddr
);
3685 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
3687 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3690 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3692 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3695 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3697 rtl_csi_access_enable_2(ioaddr
);
3699 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3702 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3704 rtl_csi_access_enable_2(ioaddr
);
3706 rtl_disable_clock_request(pdev
);
3708 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3710 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3712 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3715 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3717 static const struct ephy_info e_info_8168d_4
[] = {
3719 { 0x19, 0x20, 0x50 },
3724 rtl_csi_access_enable_1(ioaddr
);
3726 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3728 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3730 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
3731 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
3734 w
= rtl_ephy_read(ioaddr
, e
->offset
);
3735 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
3738 rtl_enable_clock_request(pdev
);
3741 static void rtl_hw_start_8168(struct net_device
*dev
)
3743 struct rtl8169_private
*tp
= netdev_priv(dev
);
3744 void __iomem
*ioaddr
= tp
->mmio_addr
;
3745 struct pci_dev
*pdev
= tp
->pci_dev
;
3747 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3749 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3751 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3753 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
3755 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3757 RTL_W16(IntrMitigate
, 0x5151);
3759 /* Work around for RxFIFO overflow. */
3760 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
3761 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
3762 tp
->intr_event
&= ~RxOverflow
;
3765 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3767 rtl_set_rx_mode(dev
);
3769 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3770 (InterFrameGap
<< TxInterFrameGapShift
));
3774 switch (tp
->mac_version
) {
3775 case RTL_GIGA_MAC_VER_11
:
3776 rtl_hw_start_8168bb(ioaddr
, pdev
);
3779 case RTL_GIGA_MAC_VER_12
:
3780 case RTL_GIGA_MAC_VER_17
:
3781 rtl_hw_start_8168bef(ioaddr
, pdev
);
3784 case RTL_GIGA_MAC_VER_18
:
3785 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
3788 case RTL_GIGA_MAC_VER_19
:
3789 rtl_hw_start_8168c_1(ioaddr
, pdev
);
3792 case RTL_GIGA_MAC_VER_20
:
3793 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3796 case RTL_GIGA_MAC_VER_21
:
3797 rtl_hw_start_8168c_3(ioaddr
, pdev
);
3800 case RTL_GIGA_MAC_VER_22
:
3801 rtl_hw_start_8168c_4(ioaddr
, pdev
);
3804 case RTL_GIGA_MAC_VER_23
:
3805 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
3808 case RTL_GIGA_MAC_VER_24
:
3809 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
3812 case RTL_GIGA_MAC_VER_25
:
3813 case RTL_GIGA_MAC_VER_26
:
3814 case RTL_GIGA_MAC_VER_27
:
3815 rtl_hw_start_8168d(ioaddr
, pdev
);
3818 case RTL_GIGA_MAC_VER_28
:
3819 rtl_hw_start_8168d_4(ioaddr
, pdev
);
3823 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
3824 dev
->name
, tp
->mac_version
);
3828 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3830 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3832 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3834 RTL_W16(IntrMask
, tp
->intr_event
);
3837 #define R810X_CPCMD_QUIRK_MASK (\
3849 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3851 static const struct ephy_info e_info_8102e_1
[] = {
3852 { 0x01, 0, 0x6e65 },
3853 { 0x02, 0, 0x091f },
3854 { 0x03, 0, 0xc2f9 },
3855 { 0x06, 0, 0xafb5 },
3856 { 0x07, 0, 0x0e00 },
3857 { 0x19, 0, 0xec80 },
3858 { 0x01, 0, 0x2e65 },
3863 rtl_csi_access_enable_2(ioaddr
);
3865 RTL_W8(DBG_REG
, FIX_NAK_1
);
3867 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3870 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
3871 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3873 cfg1
= RTL_R8(Config1
);
3874 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
3875 RTL_W8(Config1
, cfg1
& ~LEDS0
);
3877 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3879 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
3882 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3884 rtl_csi_access_enable_2(ioaddr
);
3886 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3888 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
3889 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3891 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3894 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3896 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3898 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
3901 static void rtl_hw_start_8101(struct net_device
*dev
)
3903 struct rtl8169_private
*tp
= netdev_priv(dev
);
3904 void __iomem
*ioaddr
= tp
->mmio_addr
;
3905 struct pci_dev
*pdev
= tp
->pci_dev
;
3907 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
3908 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
3909 int cap
= tp
->pcie_cap
;
3912 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
3913 PCI_EXP_DEVCTL_NOSNOOP_EN
);
3917 switch (tp
->mac_version
) {
3918 case RTL_GIGA_MAC_VER_07
:
3919 rtl_hw_start_8102e_1(ioaddr
, pdev
);
3922 case RTL_GIGA_MAC_VER_08
:
3923 rtl_hw_start_8102e_3(ioaddr
, pdev
);
3926 case RTL_GIGA_MAC_VER_09
:
3927 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3931 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3933 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3935 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3937 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3939 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3941 RTL_W16(IntrMitigate
, 0x0000);
3943 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3945 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3946 rtl_set_rx_tx_config_registers(tp
);
3948 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3952 rtl_set_rx_mode(dev
);
3954 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3956 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
3958 RTL_W16(IntrMask
, tp
->intr_event
);
3961 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3963 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
3970 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
3972 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
3973 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
3976 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
3977 void **data_buff
, struct RxDesc
*desc
)
3979 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
3984 rtl8169_make_unusable_by_asic(desc
);
3987 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
3989 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3991 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
3994 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
3997 desc
->addr
= cpu_to_le64(mapping
);
3999 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4002 static inline void *rtl8169_align(void *data
)
4004 return (void *)ALIGN((long)data
, 16);
4007 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4008 struct RxDesc
*desc
)
4012 struct device
*d
= &tp
->pci_dev
->dev
;
4013 struct net_device
*dev
= tp
->dev
;
4014 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
4016 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
4020 if (rtl8169_align(data
) != data
) {
4022 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
4027 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
4029 if (unlikely(dma_mapping_error(d
, mapping
))) {
4030 if (net_ratelimit())
4031 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
4035 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4043 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4047 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4048 if (tp
->Rx_databuff
[i
]) {
4049 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4050 tp
->RxDescArray
+ i
);
4055 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4057 desc
->opts1
|= cpu_to_le32(RingEnd
);
4060 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
4064 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4067 if (tp
->Rx_databuff
[i
])
4070 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
4072 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4075 tp
->Rx_databuff
[i
] = data
;
4078 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4082 rtl8169_rx_clear(tp
);
4086 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4088 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4091 static int rtl8169_init_ring(struct net_device
*dev
)
4093 struct rtl8169_private
*tp
= netdev_priv(dev
);
4095 rtl8169_init_ring_indexes(tp
);
4097 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4098 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4100 return rtl8169_rx_fill(tp
);
4103 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
4104 struct TxDesc
*desc
)
4106 unsigned int len
= tx_skb
->len
;
4108 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
4116 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
4121 for (i
= 0; i
< n
; i
++) {
4122 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
4123 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4124 unsigned int len
= tx_skb
->len
;
4127 struct sk_buff
*skb
= tx_skb
->skb
;
4129 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4130 tp
->TxDescArray
+ entry
);
4132 tp
->dev
->stats
.tx_dropped
++;
4140 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4142 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
4143 tp
->cur_tx
= tp
->dirty_tx
= 0;
4146 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4148 struct rtl8169_private
*tp
= netdev_priv(dev
);
4150 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4151 schedule_delayed_work(&tp
->task
, 4);
4154 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4156 struct rtl8169_private
*tp
= netdev_priv(dev
);
4157 void __iomem
*ioaddr
= tp
->mmio_addr
;
4159 synchronize_irq(dev
->irq
);
4161 /* Wait for any pending NAPI task to complete */
4162 napi_disable(&tp
->napi
);
4164 rtl8169_irq_mask_and_ack(ioaddr
);
4166 tp
->intr_mask
= 0xffff;
4167 RTL_W16(IntrMask
, tp
->intr_event
);
4168 napi_enable(&tp
->napi
);
4171 static void rtl8169_reinit_task(struct work_struct
*work
)
4173 struct rtl8169_private
*tp
=
4174 container_of(work
, struct rtl8169_private
, task
.work
);
4175 struct net_device
*dev
= tp
->dev
;
4180 if (!netif_running(dev
))
4183 rtl8169_wait_for_quiescence(dev
);
4186 ret
= rtl8169_open(dev
);
4187 if (unlikely(ret
< 0)) {
4188 if (net_ratelimit())
4189 netif_err(tp
, drv
, dev
,
4190 "reinit failure (status = %d). Rescheduling\n",
4192 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4199 static void rtl8169_reset_task(struct work_struct
*work
)
4201 struct rtl8169_private
*tp
=
4202 container_of(work
, struct rtl8169_private
, task
.work
);
4203 struct net_device
*dev
= tp
->dev
;
4207 if (!netif_running(dev
))
4210 rtl8169_wait_for_quiescence(dev
);
4212 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
4213 rtl8169_tx_clear(tp
);
4215 if (tp
->dirty_rx
== tp
->cur_rx
) {
4216 rtl8169_init_ring_indexes(tp
);
4218 netif_wake_queue(dev
);
4219 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4221 if (net_ratelimit())
4222 netif_emerg(tp
, intr
, dev
, "Rx buffers shortage\n");
4223 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4230 static void rtl8169_tx_timeout(struct net_device
*dev
)
4232 struct rtl8169_private
*tp
= netdev_priv(dev
);
4234 rtl8169_hw_reset(tp
);
4236 /* Let's wait a bit while any (async) irq lands on */
4237 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4240 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4243 struct skb_shared_info
*info
= skb_shinfo(skb
);
4244 unsigned int cur_frag
, entry
;
4245 struct TxDesc
* uninitialized_var(txd
);
4246 struct device
*d
= &tp
->pci_dev
->dev
;
4249 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4250 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4255 entry
= (entry
+ 1) % NUM_TX_DESC
;
4257 txd
= tp
->TxDescArray
+ entry
;
4259 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4260 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
4261 if (unlikely(dma_mapping_error(d
, mapping
))) {
4262 if (net_ratelimit())
4263 netif_err(tp
, drv
, tp
->dev
,
4264 "Failed to map TX fragments DMA!\n");
4268 /* anti gcc 2.95.3 bugware (sic) */
4269 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4271 txd
->opts1
= cpu_to_le32(status
);
4272 txd
->addr
= cpu_to_le64(mapping
);
4274 tp
->tx_skb
[entry
].len
= len
;
4278 tp
->tx_skb
[entry
].skb
= skb
;
4279 txd
->opts1
|= cpu_to_le32(LastFrag
);
4285 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
4289 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
4291 if (dev
->features
& NETIF_F_TSO
) {
4292 u32 mss
= skb_shinfo(skb
)->gso_size
;
4295 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
4297 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4298 const struct iphdr
*ip
= ip_hdr(skb
);
4300 if (ip
->protocol
== IPPROTO_TCP
)
4301 return IPCS
| TCPCS
;
4302 else if (ip
->protocol
== IPPROTO_UDP
)
4303 return IPCS
| UDPCS
;
4304 WARN_ON(1); /* we need a WARN() */
4309 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4310 struct net_device
*dev
)
4312 struct rtl8169_private
*tp
= netdev_priv(dev
);
4313 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
4314 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4315 void __iomem
*ioaddr
= tp
->mmio_addr
;
4316 struct device
*d
= &tp
->pci_dev
->dev
;
4322 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4323 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
4327 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4330 len
= skb_headlen(skb
);
4331 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
4332 if (unlikely(dma_mapping_error(d
, mapping
))) {
4333 if (net_ratelimit())
4334 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
4338 tp
->tx_skb
[entry
].len
= len
;
4339 txd
->addr
= cpu_to_le64(mapping
);
4340 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4342 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
4344 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
4350 opts1
|= FirstFrag
| LastFrag
;
4351 tp
->tx_skb
[entry
].skb
= skb
;
4356 /* anti gcc 2.95.3 bugware (sic) */
4357 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4358 txd
->opts1
= cpu_to_le32(status
);
4360 tp
->cur_tx
+= frags
+ 1;
4364 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
4366 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4367 netif_stop_queue(dev
);
4369 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4370 netif_wake_queue(dev
);
4373 return NETDEV_TX_OK
;
4376 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
4379 dev
->stats
.tx_dropped
++;
4380 return NETDEV_TX_OK
;
4383 netif_stop_queue(dev
);
4384 dev
->stats
.tx_dropped
++;
4385 return NETDEV_TX_BUSY
;
4388 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4390 struct rtl8169_private
*tp
= netdev_priv(dev
);
4391 struct pci_dev
*pdev
= tp
->pci_dev
;
4392 u16 pci_status
, pci_cmd
;
4394 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4395 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4397 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4398 pci_cmd
, pci_status
);
4401 * The recovery sequence below admits a very elaborated explanation:
4402 * - it seems to work;
4403 * - I did not see what else could be done;
4404 * - it makes iop3xx happy.
4406 * Feel free to adjust to your needs.
4408 if (pdev
->broken_parity_status
)
4409 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4411 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4413 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4415 pci_write_config_word(pdev
, PCI_STATUS
,
4416 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4417 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4418 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4420 /* The infamous DAC f*ckup only happens at boot time */
4421 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4422 void __iomem
*ioaddr
= tp
->mmio_addr
;
4424 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
4425 tp
->cp_cmd
&= ~PCIDAC
;
4426 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4427 dev
->features
&= ~NETIF_F_HIGHDMA
;
4430 rtl8169_hw_reset(tp
);
4432 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4435 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4436 struct rtl8169_private
*tp
,
4437 void __iomem
*ioaddr
)
4439 unsigned int dirty_tx
, tx_left
;
4441 dirty_tx
= tp
->dirty_tx
;
4443 tx_left
= tp
->cur_tx
- dirty_tx
;
4445 while (tx_left
> 0) {
4446 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4447 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4451 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4452 if (status
& DescOwn
)
4455 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4456 tp
->TxDescArray
+ entry
);
4457 if (status
& LastFrag
) {
4458 dev
->stats
.tx_packets
++;
4459 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
4460 dev_kfree_skb(tx_skb
->skb
);
4467 if (tp
->dirty_tx
!= dirty_tx
) {
4468 tp
->dirty_tx
= dirty_tx
;
4470 if (netif_queue_stopped(dev
) &&
4471 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4472 netif_wake_queue(dev
);
4475 * 8168 hack: TxPoll requests are lost when the Tx packets are
4476 * too close. Let's kick an extra TxPoll request when a burst
4477 * of start_xmit activity is detected (if it is not detected,
4478 * it is slow enough). -- FR
4481 if (tp
->cur_tx
!= dirty_tx
)
4482 RTL_W8(TxPoll
, NPQ
);
4486 static inline int rtl8169_fragmented_frame(u32 status
)
4488 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4491 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
4493 u32 status
= opts1
& RxProtoMask
;
4495 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4496 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
4497 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4499 skb_checksum_none_assert(skb
);
4502 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
4503 struct rtl8169_private
*tp
,
4507 struct sk_buff
*skb
;
4508 struct device
*d
= &tp
->pci_dev
->dev
;
4510 data
= rtl8169_align(data
);
4511 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4513 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
4515 memcpy(skb
->data
, data
, pkt_size
);
4516 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4522 * Warning : rtl8169_rx_interrupt() might be called :
4523 * 1) from NAPI (softirq) context
4524 * (polling = 1 : we should call netif_receive_skb())
4525 * 2) from process context (rtl8169_reset_task())
4526 * (polling = 0 : we must call netif_rx() instead)
4528 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4529 struct rtl8169_private
*tp
,
4530 void __iomem
*ioaddr
, u32 budget
)
4532 unsigned int cur_rx
, rx_left
;
4534 int polling
= (budget
!= ~(u32
)0) ? 1 : 0;
4536 cur_rx
= tp
->cur_rx
;
4537 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4538 rx_left
= min(rx_left
, budget
);
4540 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4541 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4542 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4546 status
= le32_to_cpu(desc
->opts1
);
4548 if (status
& DescOwn
)
4550 if (unlikely(status
& RxRES
)) {
4551 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
4553 dev
->stats
.rx_errors
++;
4554 if (status
& (RxRWT
| RxRUNT
))
4555 dev
->stats
.rx_length_errors
++;
4557 dev
->stats
.rx_crc_errors
++;
4558 if (status
& RxFOVF
) {
4559 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4560 dev
->stats
.rx_fifo_errors
++;
4562 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4564 struct sk_buff
*skb
;
4565 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4566 int pkt_size
= (status
& 0x00001FFF) - 4;
4569 * The driver does not support incoming fragmented
4570 * frames. They are seen as a symptom of over-mtu
4573 if (unlikely(rtl8169_fragmented_frame(status
))) {
4574 dev
->stats
.rx_dropped
++;
4575 dev
->stats
.rx_length_errors
++;
4576 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4580 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
4581 tp
, pkt_size
, addr
);
4582 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4584 dev
->stats
.rx_dropped
++;
4588 rtl8169_rx_csum(skb
, status
);
4589 skb_put(skb
, pkt_size
);
4590 skb
->protocol
= eth_type_trans(skb
, dev
);
4592 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
, polling
) < 0) {
4593 if (likely(polling
))
4594 napi_gro_receive(&tp
->napi
, skb
);
4599 dev
->stats
.rx_bytes
+= pkt_size
;
4600 dev
->stats
.rx_packets
++;
4603 /* Work around for AMD plateform. */
4604 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
4605 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
4611 count
= cur_rx
- tp
->cur_rx
;
4612 tp
->cur_rx
= cur_rx
;
4614 tp
->dirty_rx
+= count
;
4619 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4621 struct net_device
*dev
= dev_instance
;
4622 struct rtl8169_private
*tp
= netdev_priv(dev
);
4623 void __iomem
*ioaddr
= tp
->mmio_addr
;
4627 /* loop handling interrupts until we have no new ones or
4628 * we hit a invalid/hotplug case.
4630 status
= RTL_R16(IntrStatus
);
4631 while (status
&& status
!= 0xffff) {
4634 /* Handle all of the error cases first. These will reset
4635 * the chip, so just exit the loop.
4637 if (unlikely(!netif_running(dev
))) {
4638 rtl8169_asic_down(ioaddr
);
4642 /* Work around for rx fifo overflow */
4643 if (unlikely(status
& RxFIFOOver
) &&
4644 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
4645 netif_stop_queue(dev
);
4646 rtl8169_tx_timeout(dev
);
4650 if (unlikely(status
& SYSErr
)) {
4651 rtl8169_pcierr_interrupt(dev
);
4655 if (status
& LinkChg
)
4656 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
4658 /* We need to see the lastest version of tp->intr_mask to
4659 * avoid ignoring an MSI interrupt and having to wait for
4660 * another event which may never come.
4663 if (status
& tp
->intr_mask
& tp
->napi_event
) {
4664 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
4665 tp
->intr_mask
= ~tp
->napi_event
;
4667 if (likely(napi_schedule_prep(&tp
->napi
)))
4668 __napi_schedule(&tp
->napi
);
4670 netif_info(tp
, intr
, dev
,
4671 "interrupt %04x in poll\n", status
);
4674 /* We only get a new MSI interrupt when all active irq
4675 * sources on the chip have been acknowledged. So, ack
4676 * everything we've seen and check if new sources have become
4677 * active to avoid blocking all interrupts from the chip.
4680 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
4681 status
= RTL_R16(IntrStatus
);
4684 return IRQ_RETVAL(handled
);
4687 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
4689 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
4690 struct net_device
*dev
= tp
->dev
;
4691 void __iomem
*ioaddr
= tp
->mmio_addr
;
4694 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
4695 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
4697 if (work_done
< budget
) {
4698 napi_complete(napi
);
4700 /* We need for force the visibility of tp->intr_mask
4701 * for other CPUs, as we can loose an MSI interrupt
4702 * and potentially wait for a retransmit timeout if we don't.
4703 * The posted write to IntrMask is safe, as it will
4704 * eventually make it to the chip and we won't loose anything
4707 tp
->intr_mask
= 0xffff;
4709 RTL_W16(IntrMask
, tp
->intr_event
);
4715 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
4717 struct rtl8169_private
*tp
= netdev_priv(dev
);
4719 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
4722 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
4723 RTL_W32(RxMissed
, 0);
4726 static void rtl8169_down(struct net_device
*dev
)
4728 struct rtl8169_private
*tp
= netdev_priv(dev
);
4729 void __iomem
*ioaddr
= tp
->mmio_addr
;
4731 rtl8169_delete_timer(dev
);
4733 netif_stop_queue(dev
);
4735 napi_disable(&tp
->napi
);
4737 spin_lock_irq(&tp
->lock
);
4739 rtl8169_asic_down(ioaddr
);
4741 * At this point device interrupts can not be enabled in any function,
4742 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4743 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4745 rtl8169_rx_missed(dev
, ioaddr
);
4747 spin_unlock_irq(&tp
->lock
);
4749 synchronize_irq(dev
->irq
);
4751 /* Give a racing hard_start_xmit a few cycles to complete. */
4752 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4754 rtl8169_tx_clear(tp
);
4756 rtl8169_rx_clear(tp
);
4758 rtl_pll_power_down(tp
);
4761 static int rtl8169_close(struct net_device
*dev
)
4763 struct rtl8169_private
*tp
= netdev_priv(dev
);
4764 struct pci_dev
*pdev
= tp
->pci_dev
;
4766 pm_runtime_get_sync(&pdev
->dev
);
4768 /* update counters before going down */
4769 rtl8169_update_counters(dev
);
4773 free_irq(dev
->irq
, dev
);
4775 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4777 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4779 tp
->TxDescArray
= NULL
;
4780 tp
->RxDescArray
= NULL
;
4782 pm_runtime_put_sync(&pdev
->dev
);
4787 static void rtl_set_rx_mode(struct net_device
*dev
)
4789 struct rtl8169_private
*tp
= netdev_priv(dev
);
4790 void __iomem
*ioaddr
= tp
->mmio_addr
;
4791 unsigned long flags
;
4792 u32 mc_filter
[2]; /* Multicast hash filter */
4796 if (dev
->flags
& IFF_PROMISC
) {
4797 /* Unconditionally log net taps. */
4798 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4800 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4802 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4803 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
4804 (dev
->flags
& IFF_ALLMULTI
)) {
4805 /* Too many to filter perfectly -- accept all multicasts. */
4806 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4807 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4809 struct netdev_hw_addr
*ha
;
4811 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4812 mc_filter
[1] = mc_filter
[0] = 0;
4813 netdev_for_each_mc_addr(ha
, dev
) {
4814 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4815 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4816 rx_mode
|= AcceptMulticast
;
4820 spin_lock_irqsave(&tp
->lock
, flags
);
4822 tmp
= rtl8169_rx_config
| rx_mode
|
4823 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
4825 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4826 u32 data
= mc_filter
[0];
4828 mc_filter
[0] = swab32(mc_filter
[1]);
4829 mc_filter
[1] = swab32(data
);
4832 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4833 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4835 RTL_W32(RxConfig
, tmp
);
4837 spin_unlock_irqrestore(&tp
->lock
, flags
);
4841 * rtl8169_get_stats - Get rtl8169 read/write statistics
4842 * @dev: The Ethernet Device to get statistics for
4844 * Get TX/RX statistics for rtl8169
4846 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
4848 struct rtl8169_private
*tp
= netdev_priv(dev
);
4849 void __iomem
*ioaddr
= tp
->mmio_addr
;
4850 unsigned long flags
;
4852 if (netif_running(dev
)) {
4853 spin_lock_irqsave(&tp
->lock
, flags
);
4854 rtl8169_rx_missed(dev
, ioaddr
);
4855 spin_unlock_irqrestore(&tp
->lock
, flags
);
4861 static void rtl8169_net_suspend(struct net_device
*dev
)
4863 struct rtl8169_private
*tp
= netdev_priv(dev
);
4865 if (!netif_running(dev
))
4868 rtl_pll_power_down(tp
);
4870 netif_device_detach(dev
);
4871 netif_stop_queue(dev
);
4876 static int rtl8169_suspend(struct device
*device
)
4878 struct pci_dev
*pdev
= to_pci_dev(device
);
4879 struct net_device
*dev
= pci_get_drvdata(pdev
);
4881 rtl8169_net_suspend(dev
);
4886 static void __rtl8169_resume(struct net_device
*dev
)
4888 struct rtl8169_private
*tp
= netdev_priv(dev
);
4890 netif_device_attach(dev
);
4892 rtl_pll_power_up(tp
);
4894 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4897 static int rtl8169_resume(struct device
*device
)
4899 struct pci_dev
*pdev
= to_pci_dev(device
);
4900 struct net_device
*dev
= pci_get_drvdata(pdev
);
4901 struct rtl8169_private
*tp
= netdev_priv(dev
);
4903 rtl8169_init_phy(dev
, tp
);
4905 if (netif_running(dev
))
4906 __rtl8169_resume(dev
);
4911 static int rtl8169_runtime_suspend(struct device
*device
)
4913 struct pci_dev
*pdev
= to_pci_dev(device
);
4914 struct net_device
*dev
= pci_get_drvdata(pdev
);
4915 struct rtl8169_private
*tp
= netdev_priv(dev
);
4917 if (!tp
->TxDescArray
)
4920 spin_lock_irq(&tp
->lock
);
4921 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
4922 __rtl8169_set_wol(tp
, WAKE_ANY
);
4923 spin_unlock_irq(&tp
->lock
);
4925 rtl8169_net_suspend(dev
);
4930 static int rtl8169_runtime_resume(struct device
*device
)
4932 struct pci_dev
*pdev
= to_pci_dev(device
);
4933 struct net_device
*dev
= pci_get_drvdata(pdev
);
4934 struct rtl8169_private
*tp
= netdev_priv(dev
);
4936 if (!tp
->TxDescArray
)
4939 spin_lock_irq(&tp
->lock
);
4940 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
4941 tp
->saved_wolopts
= 0;
4942 spin_unlock_irq(&tp
->lock
);
4944 rtl8169_init_phy(dev
, tp
);
4946 __rtl8169_resume(dev
);
4951 static int rtl8169_runtime_idle(struct device
*device
)
4953 struct pci_dev
*pdev
= to_pci_dev(device
);
4954 struct net_device
*dev
= pci_get_drvdata(pdev
);
4955 struct rtl8169_private
*tp
= netdev_priv(dev
);
4957 return tp
->TxDescArray
? -EBUSY
: 0;
4960 static const struct dev_pm_ops rtl8169_pm_ops
= {
4961 .suspend
= rtl8169_suspend
,
4962 .resume
= rtl8169_resume
,
4963 .freeze
= rtl8169_suspend
,
4964 .thaw
= rtl8169_resume
,
4965 .poweroff
= rtl8169_suspend
,
4966 .restore
= rtl8169_resume
,
4967 .runtime_suspend
= rtl8169_runtime_suspend
,
4968 .runtime_resume
= rtl8169_runtime_resume
,
4969 .runtime_idle
= rtl8169_runtime_idle
,
4972 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4974 #else /* !CONFIG_PM */
4976 #define RTL8169_PM_OPS NULL
4978 #endif /* !CONFIG_PM */
4980 static void rtl_shutdown(struct pci_dev
*pdev
)
4982 struct net_device
*dev
= pci_get_drvdata(pdev
);
4983 struct rtl8169_private
*tp
= netdev_priv(dev
);
4984 void __iomem
*ioaddr
= tp
->mmio_addr
;
4986 rtl8169_net_suspend(dev
);
4988 /* restore original MAC address */
4989 rtl_rar_set(tp
, dev
->perm_addr
);
4991 spin_lock_irq(&tp
->lock
);
4993 rtl8169_asic_down(ioaddr
);
4995 spin_unlock_irq(&tp
->lock
);
4997 if (system_state
== SYSTEM_POWER_OFF
) {
4998 /* WoL fails with some 8168 when the receiver is disabled. */
4999 if (tp
->features
& RTL_FEATURE_WOL
) {
5000 pci_clear_master(pdev
);
5002 RTL_W8(ChipCmd
, CmdRxEnb
);
5007 pci_wake_from_d3(pdev
, true);
5008 pci_set_power_state(pdev
, PCI_D3hot
);
5012 static struct pci_driver rtl8169_pci_driver
= {
5014 .id_table
= rtl8169_pci_tbl
,
5015 .probe
= rtl8169_init_one
,
5016 .remove
= __devexit_p(rtl8169_remove_one
),
5017 .shutdown
= rtl_shutdown
,
5018 .driver
.pm
= RTL8169_PM_OPS
,
5021 static int __init
rtl8169_init_module(void)
5023 return pci_register_driver(&rtl8169_pci_driver
);
5026 static void __exit
rtl8169_cleanup_module(void)
5028 pci_unregister_driver(&rtl8169_pci_driver
);
5031 module_init(rtl8169_init_module
);
5032 module_exit(rtl8169_cleanup_module
);