2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
28 #include <asm/system.h>
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
37 #define assert(expr) \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__func__,__LINE__); \
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
55 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
57 static const int multicast_filter_limit
= 32;
59 /* MAC address length */
60 #define MAC_ADDR_LEN 6
62 #define MAX_READ_REQUEST_SHIFT 12
63 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70 #define R8169_REGS_SIZE 256
71 #define R8169_NAPI_WEIGHT 64
72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78 #define RTL8169_TX_TIMEOUT (6*HZ)
79 #define RTL8169_PHY_TIMEOUT (10*HZ)
81 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
83 #define RTL_EEPROM_SIG_ADDR 0x0000
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) readl (ioaddr + (reg))
94 RTL_GIGA_MAC_NONE
= 0x00,
95 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
96 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
100 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
101 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
105 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
106 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
114 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
115 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
116 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
117 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
118 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
119 RTL_GIGA_MAC_VER_25
= 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26
= 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27
= 0x1b // 8168DP
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask
; /* Clears the bits supported by this chip */
131 } rtl_chip_info
[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26
, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27
, 0xff7e1880) // PCI-E
168 static void rtl_hw_start_8169(struct net_device
*);
169 static void rtl_hw_start_8168(struct net_device
*);
170 static void rtl_hw_start_8101(struct net_device
*);
172 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
179 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
181 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
182 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
184 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
188 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
190 static int rx_buf_sz
= 16383;
197 MAC0
= 0, /* Ethernet hardware address. */
199 MAR0
= 8, /* Multicast filter. */
200 CounterAddrLow
= 0x10,
201 CounterAddrHigh
= 0x14,
202 TxDescStartAddrLow
= 0x20,
203 TxDescStartAddrHigh
= 0x24,
204 TxHDescStartAddrLow
= 0x28,
205 TxHDescStartAddrHigh
= 0x2c,
228 RxDescAddrLow
= 0xe4,
229 RxDescAddrHigh
= 0xe8,
232 FuncEventMask
= 0xf4,
233 FuncPresetState
= 0xf8,
234 FuncForceEvent
= 0xfc,
237 enum rtl8110_registers
{
243 enum rtl8168_8101_registers
{
246 #define CSIAR_FLAG 0x80000000
247 #define CSIAR_WRITE_CMD 0x80000000
248 #define CSIAR_BYTE_ENABLE 0x0f
249 #define CSIAR_BYTE_ENABLE_SHIFT 12
250 #define CSIAR_ADDR_MASK 0x0fff
253 #define EPHYAR_FLAG 0x80000000
254 #define EPHYAR_WRITE_CMD 0x80000000
255 #define EPHYAR_REG_MASK 0x1f
256 #define EPHYAR_REG_SHIFT 16
257 #define EPHYAR_DATA_MASK 0xffff
259 #define FIX_NAK_1 (1 << 4)
260 #define FIX_NAK_2 (1 << 3)
262 #define EFUSEAR_FLAG 0x80000000
263 #define EFUSEAR_WRITE_CMD 0x80000000
264 #define EFUSEAR_READ_CMD 0x00000000
265 #define EFUSEAR_REG_MASK 0x03ff
266 #define EFUSEAR_REG_SHIFT 8
267 #define EFUSEAR_DATA_MASK 0xff
270 enum rtl_register_content
{
271 /* InterruptStatusBits */
275 TxDescUnavail
= 0x0080,
297 /* TXPoll register p.5 */
298 HPQ
= 0x80, /* Poll cmd on the high prio queue */
299 NPQ
= 0x40, /* Poll cmd on the low prio queue */
300 FSWInt
= 0x01, /* Forced software interrupt */
304 Cfg9346_Unlock
= 0xc0,
309 AcceptBroadcast
= 0x08,
310 AcceptMulticast
= 0x04,
312 AcceptAllPhys
= 0x01,
319 TxInterFrameGapShift
= 24,
320 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
322 /* Config1 register p.24 */
325 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
326 Speed_down
= (1 << 4),
330 PMEnable
= (1 << 0), /* Power Management Enable */
332 /* Config2 register p. 25 */
333 PCI_Clock_66MHz
= 0x01,
334 PCI_Clock_33MHz
= 0x00,
336 /* Config3 register p.25 */
337 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
338 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
339 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
341 /* Config5 register p.27 */
342 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
343 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
344 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
345 LanWake
= (1 << 1), /* LanWake enable/disable */
346 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
349 TBIReset
= 0x80000000,
350 TBILoopback
= 0x40000000,
351 TBINwEnable
= 0x20000000,
352 TBINwRestart
= 0x10000000,
353 TBILinkOk
= 0x02000000,
354 TBINwComplete
= 0x01000000,
357 EnableBist
= (1 << 15), // 8168 8101
358 Mac_dbgo_oe
= (1 << 14), // 8168 8101
359 Normal_mode
= (1 << 13), // unused
360 Force_half_dup
= (1 << 12), // 8168 8101
361 Force_rxflow_en
= (1 << 11), // 8168 8101
362 Force_txflow_en
= (1 << 10), // 8168 8101
363 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
364 ASF
= (1 << 8), // 8168 8101
365 PktCntrDisable
= (1 << 7), // 8168 8101
366 Mac_dbgo_sel
= 0x001c, // 8168
371 INTT_0
= 0x0000, // 8168
372 INTT_1
= 0x0001, // 8168
373 INTT_2
= 0x0002, // 8168
374 INTT_3
= 0x0003, // 8168
376 /* rtl8169_PHYstatus */
387 TBILinkOK
= 0x02000000,
389 /* DumpCounterCommand */
393 enum desc_status_bit
{
394 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
395 RingEnd
= (1 << 30), /* End of descriptor ring */
396 FirstFrag
= (1 << 29), /* First segment of a packet */
397 LastFrag
= (1 << 28), /* Final segment of a packet */
400 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
401 MSSShift
= 16, /* MSS value position */
402 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
403 IPCS
= (1 << 18), /* Calculate IP checksum */
404 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
405 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
406 TxVlanTag
= (1 << 17), /* Add VLAN tag */
409 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
410 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
412 #define RxProtoUDP (PID1)
413 #define RxProtoTCP (PID0)
414 #define RxProtoIP (PID1 | PID0)
415 #define RxProtoMask RxProtoIP
417 IPFail
= (1 << 16), /* IP checksum failed */
418 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
419 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
420 RxVlanTag
= (1 << 16), /* VLAN tag available */
423 #define RsvdMask 0x3fffc000
440 u8 __pad
[sizeof(void *) - sizeof(u32
)];
444 RTL_FEATURE_WOL
= (1 << 0),
445 RTL_FEATURE_MSI
= (1 << 1),
446 RTL_FEATURE_GMII
= (1 << 2),
449 struct rtl8169_counters
{
456 __le32 tx_one_collision
;
457 __le32 tx_multi_collision
;
465 struct rtl8169_private
{
466 void __iomem
*mmio_addr
; /* memory map physical address */
467 struct pci_dev
*pci_dev
; /* Index of PCI device */
468 struct net_device
*dev
;
469 struct napi_struct napi
;
470 spinlock_t lock
; /* spin lock flag */
474 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
475 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
478 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
479 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
480 dma_addr_t TxPhyAddr
;
481 dma_addr_t RxPhyAddr
;
482 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
483 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
484 struct timer_list timer
;
489 int phy_1000_ctrl_reg
;
490 #ifdef CONFIG_R8169_VLAN
491 struct vlan_group
*vlgrp
;
493 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
494 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
495 void (*phy_reset_enable
)(void __iomem
*);
496 void (*hw_start
)(struct net_device
*);
497 unsigned int (*phy_reset_pending
)(void __iomem
*);
498 unsigned int (*link_ok
)(void __iomem
*);
499 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
501 struct delayed_work task
;
504 struct mii_if_info mii
;
505 struct rtl8169_counters counters
;
509 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
510 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
511 module_param(use_dac
, int, 0);
512 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
513 module_param_named(debug
, debug
.msg_enable
, int, 0);
514 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
515 MODULE_LICENSE("GPL");
516 MODULE_VERSION(RTL8169_VERSION
);
518 static int rtl8169_open(struct net_device
*dev
);
519 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
520 struct net_device
*dev
);
521 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
522 static int rtl8169_init_ring(struct net_device
*dev
);
523 static void rtl_hw_start(struct net_device
*dev
);
524 static int rtl8169_close(struct net_device
*dev
);
525 static void rtl_set_rx_mode(struct net_device
*dev
);
526 static void rtl8169_tx_timeout(struct net_device
*dev
);
527 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
528 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
529 void __iomem
*, u32 budget
);
530 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
531 static void rtl8169_down(struct net_device
*dev
);
532 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
533 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
535 static const unsigned int rtl8169_rx_config
=
536 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
538 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
542 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
544 for (i
= 20; i
> 0; i
--) {
546 * Check if the RTL8169 has completed writing to the specified
549 if (!(RTL_R32(PHYAR
) & 0x80000000))
554 * According to hardware specs a 20us delay is required after write
555 * complete indication, but before sending next command.
560 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
564 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
566 for (i
= 20; i
> 0; i
--) {
568 * Check if the RTL8169 has completed retrieving data from
569 * the specified MII register.
571 if (RTL_R32(PHYAR
) & 0x80000000) {
572 value
= RTL_R32(PHYAR
) & 0xffff;
578 * According to hardware specs a 20us delay is required after read
579 * complete indication, but before sending next command.
586 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
588 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
591 static void mdio_plus_minus(void __iomem
*ioaddr
, int reg_addr
, int p
, int m
)
595 val
= mdio_read(ioaddr
, reg_addr
);
596 mdio_write(ioaddr
, reg_addr
, (val
| p
) & ~m
);
599 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
602 struct rtl8169_private
*tp
= netdev_priv(dev
);
603 void __iomem
*ioaddr
= tp
->mmio_addr
;
605 mdio_write(ioaddr
, location
, val
);
608 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
610 struct rtl8169_private
*tp
= netdev_priv(dev
);
611 void __iomem
*ioaddr
= tp
->mmio_addr
;
613 return mdio_read(ioaddr
, location
);
616 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
620 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
621 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
623 for (i
= 0; i
< 100; i
++) {
624 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
630 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
635 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
637 for (i
= 0; i
< 100; i
++) {
638 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
639 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
648 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
652 RTL_W32(CSIDR
, value
);
653 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
654 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
656 for (i
= 0; i
< 100; i
++) {
657 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
663 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
668 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
669 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
671 for (i
= 0; i
< 100; i
++) {
672 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
673 value
= RTL_R32(CSIDR
);
682 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
687 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
689 for (i
= 0; i
< 300; i
++) {
690 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
691 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
700 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
702 RTL_W16(IntrMask
, 0x0000);
704 RTL_W16(IntrStatus
, 0xffff);
707 static void rtl8169_asic_down(void __iomem
*ioaddr
)
709 RTL_W8(ChipCmd
, 0x00);
710 rtl8169_irq_mask_and_ack(ioaddr
);
714 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
716 return RTL_R32(TBICSR
) & TBIReset
;
719 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
721 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
724 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
726 return RTL_R32(TBICSR
) & TBILinkOk
;
729 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
731 return RTL_R8(PHYstatus
) & LinkStatus
;
734 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
736 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
739 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
743 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
744 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
747 static void __rtl8169_check_link_status(struct net_device
*dev
,
748 struct rtl8169_private
*tp
,
749 void __iomem
*ioaddr
,
754 spin_lock_irqsave(&tp
->lock
, flags
);
755 if (tp
->link_ok(ioaddr
)) {
756 /* This is to cancel a scheduled suspend if there's one. */
758 pm_request_resume(&tp
->pci_dev
->dev
);
759 netif_carrier_on(dev
);
760 netif_info(tp
, ifup
, dev
, "link up\n");
762 netif_carrier_off(dev
);
763 netif_info(tp
, ifdown
, dev
, "link down\n");
765 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
767 spin_unlock_irqrestore(&tp
->lock
, flags
);
770 static void rtl8169_check_link_status(struct net_device
*dev
,
771 struct rtl8169_private
*tp
,
772 void __iomem
*ioaddr
)
774 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
777 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
779 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
781 void __iomem
*ioaddr
= tp
->mmio_addr
;
785 options
= RTL_R8(Config1
);
786 if (!(options
& PMEnable
))
789 options
= RTL_R8(Config3
);
790 if (options
& LinkUp
)
792 if (options
& MagicPacket
)
793 wolopts
|= WAKE_MAGIC
;
795 options
= RTL_R8(Config5
);
797 wolopts
|= WAKE_UCAST
;
799 wolopts
|= WAKE_BCAST
;
801 wolopts
|= WAKE_MCAST
;
806 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
808 struct rtl8169_private
*tp
= netdev_priv(dev
);
810 spin_lock_irq(&tp
->lock
);
812 wol
->supported
= WAKE_ANY
;
813 wol
->wolopts
= __rtl8169_get_wol(tp
);
815 spin_unlock_irq(&tp
->lock
);
818 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
820 void __iomem
*ioaddr
= tp
->mmio_addr
;
822 static const struct {
827 { WAKE_ANY
, Config1
, PMEnable
},
828 { WAKE_PHY
, Config3
, LinkUp
},
829 { WAKE_MAGIC
, Config3
, MagicPacket
},
830 { WAKE_UCAST
, Config5
, UWF
},
831 { WAKE_BCAST
, Config5
, BWF
},
832 { WAKE_MCAST
, Config5
, MWF
},
833 { WAKE_ANY
, Config5
, LanWake
}
836 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
838 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
839 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
840 if (wolopts
& cfg
[i
].opt
)
841 options
|= cfg
[i
].mask
;
842 RTL_W8(cfg
[i
].reg
, options
);
845 RTL_W8(Cfg9346
, Cfg9346_Lock
);
848 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
850 struct rtl8169_private
*tp
= netdev_priv(dev
);
852 spin_lock_irq(&tp
->lock
);
855 tp
->features
|= RTL_FEATURE_WOL
;
857 tp
->features
&= ~RTL_FEATURE_WOL
;
858 __rtl8169_set_wol(tp
, wol
->wolopts
);
859 spin_unlock_irq(&tp
->lock
);
861 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
866 static void rtl8169_get_drvinfo(struct net_device
*dev
,
867 struct ethtool_drvinfo
*info
)
869 struct rtl8169_private
*tp
= netdev_priv(dev
);
871 strcpy(info
->driver
, MODULENAME
);
872 strcpy(info
->version
, RTL8169_VERSION
);
873 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
876 static int rtl8169_get_regs_len(struct net_device
*dev
)
878 return R8169_REGS_SIZE
;
881 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
882 u8 autoneg
, u16 speed
, u8 duplex
)
884 struct rtl8169_private
*tp
= netdev_priv(dev
);
885 void __iomem
*ioaddr
= tp
->mmio_addr
;
889 reg
= RTL_R32(TBICSR
);
890 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
891 (duplex
== DUPLEX_FULL
)) {
892 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
893 } else if (autoneg
== AUTONEG_ENABLE
)
894 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
896 netif_warn(tp
, link
, dev
,
897 "incorrect speed setting refused in TBI mode\n");
904 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
905 u8 autoneg
, u16 speed
, u8 duplex
)
907 struct rtl8169_private
*tp
= netdev_priv(dev
);
908 void __iomem
*ioaddr
= tp
->mmio_addr
;
911 if (autoneg
== AUTONEG_ENABLE
) {
914 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
915 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
916 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
917 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
919 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
920 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
922 /* The 8100e/8101e/8102e do Fast Ethernet only. */
923 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
924 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
925 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
926 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
927 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
928 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
929 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
930 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
931 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
933 netif_info(tp
, link
, dev
,
934 "PHY does not support 1000Mbps\n");
937 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
939 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
940 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
941 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
944 * Vendor specific (0x1f) and reserved (0x0e) MII
947 mdio_write(ioaddr
, 0x1f, 0x0000);
948 mdio_write(ioaddr
, 0x0e, 0x0000);
951 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
952 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
956 if (speed
== SPEED_10
)
958 else if (speed
== SPEED_100
)
959 bmcr
= BMCR_SPEED100
;
963 if (duplex
== DUPLEX_FULL
)
964 bmcr
|= BMCR_FULLDPLX
;
966 mdio_write(ioaddr
, 0x1f, 0x0000);
969 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
971 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
973 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
974 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
975 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
976 mdio_write(ioaddr
, 0x17, 0x2138);
977 mdio_write(ioaddr
, 0x0e, 0x0260);
979 mdio_write(ioaddr
, 0x17, 0x2108);
980 mdio_write(ioaddr
, 0x0e, 0x0000);
987 static int rtl8169_set_speed(struct net_device
*dev
,
988 u8 autoneg
, u16 speed
, u8 duplex
)
990 struct rtl8169_private
*tp
= netdev_priv(dev
);
993 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
995 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
996 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1001 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1003 struct rtl8169_private
*tp
= netdev_priv(dev
);
1004 unsigned long flags
;
1007 spin_lock_irqsave(&tp
->lock
, flags
);
1008 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
1009 spin_unlock_irqrestore(&tp
->lock
, flags
);
1014 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
1016 struct rtl8169_private
*tp
= netdev_priv(dev
);
1018 return tp
->cp_cmd
& RxChkSum
;
1021 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
1023 struct rtl8169_private
*tp
= netdev_priv(dev
);
1024 void __iomem
*ioaddr
= tp
->mmio_addr
;
1025 unsigned long flags
;
1027 spin_lock_irqsave(&tp
->lock
, flags
);
1030 tp
->cp_cmd
|= RxChkSum
;
1032 tp
->cp_cmd
&= ~RxChkSum
;
1034 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1037 spin_unlock_irqrestore(&tp
->lock
, flags
);
1042 #ifdef CONFIG_R8169_VLAN
1044 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1045 struct sk_buff
*skb
)
1047 return (vlan_tx_tag_present(skb
)) ?
1048 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1051 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
1052 struct vlan_group
*grp
)
1054 struct rtl8169_private
*tp
= netdev_priv(dev
);
1055 void __iomem
*ioaddr
= tp
->mmio_addr
;
1056 unsigned long flags
;
1058 spin_lock_irqsave(&tp
->lock
, flags
);
1061 * Do not disable RxVlan on 8110SCd.
1063 if (tp
->vlgrp
|| (tp
->mac_version
== RTL_GIGA_MAC_VER_05
))
1064 tp
->cp_cmd
|= RxVlan
;
1066 tp
->cp_cmd
&= ~RxVlan
;
1067 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1069 spin_unlock_irqrestore(&tp
->lock
, flags
);
1072 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1073 struct sk_buff
*skb
, int polling
)
1075 u32 opts2
= le32_to_cpu(desc
->opts2
);
1076 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1079 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1080 u16 vtag
= swab16(opts2
& 0xffff);
1082 if (likely(polling
))
1083 vlan_gro_receive(&tp
->napi
, vlgrp
, vtag
, skb
);
1085 __vlan_hwaccel_rx(skb
, vlgrp
, vtag
, polling
);
1093 #else /* !CONFIG_R8169_VLAN */
1095 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1096 struct sk_buff
*skb
)
1101 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1102 struct sk_buff
*skb
, int polling
)
1109 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1111 struct rtl8169_private
*tp
= netdev_priv(dev
);
1112 void __iomem
*ioaddr
= tp
->mmio_addr
;
1116 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1117 cmd
->port
= PORT_FIBRE
;
1118 cmd
->transceiver
= XCVR_INTERNAL
;
1120 status
= RTL_R32(TBICSR
);
1121 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1122 cmd
->autoneg
= !!(status
& TBINwEnable
);
1124 cmd
->speed
= SPEED_1000
;
1125 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1130 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1132 struct rtl8169_private
*tp
= netdev_priv(dev
);
1134 return mii_ethtool_gset(&tp
->mii
, cmd
);
1137 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1139 struct rtl8169_private
*tp
= netdev_priv(dev
);
1140 unsigned long flags
;
1143 spin_lock_irqsave(&tp
->lock
, flags
);
1145 rc
= tp
->get_settings(dev
, cmd
);
1147 spin_unlock_irqrestore(&tp
->lock
, flags
);
1151 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1154 struct rtl8169_private
*tp
= netdev_priv(dev
);
1155 unsigned long flags
;
1157 if (regs
->len
> R8169_REGS_SIZE
)
1158 regs
->len
= R8169_REGS_SIZE
;
1160 spin_lock_irqsave(&tp
->lock
, flags
);
1161 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1162 spin_unlock_irqrestore(&tp
->lock
, flags
);
1165 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1167 struct rtl8169_private
*tp
= netdev_priv(dev
);
1169 return tp
->msg_enable
;
1172 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1174 struct rtl8169_private
*tp
= netdev_priv(dev
);
1176 tp
->msg_enable
= value
;
1179 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1186 "tx_single_collisions",
1187 "tx_multi_collisions",
1195 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1199 return ARRAY_SIZE(rtl8169_gstrings
);
1205 static void rtl8169_update_counters(struct net_device
*dev
)
1207 struct rtl8169_private
*tp
= netdev_priv(dev
);
1208 void __iomem
*ioaddr
= tp
->mmio_addr
;
1209 struct rtl8169_counters
*counters
;
1213 struct device
*d
= &tp
->pci_dev
->dev
;
1216 * Some chips are unable to dump tally counters when the receiver
1219 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1222 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1226 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1227 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1228 RTL_W32(CounterAddrLow
, cmd
);
1229 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1232 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1233 /* copy updated counters */
1234 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1240 RTL_W32(CounterAddrLow
, 0);
1241 RTL_W32(CounterAddrHigh
, 0);
1243 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1246 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1247 struct ethtool_stats
*stats
, u64
*data
)
1249 struct rtl8169_private
*tp
= netdev_priv(dev
);
1253 rtl8169_update_counters(dev
);
1255 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1256 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1257 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1258 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1259 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1260 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1261 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1262 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1263 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1264 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1265 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1266 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1267 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1270 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1274 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1279 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1280 .get_drvinfo
= rtl8169_get_drvinfo
,
1281 .get_regs_len
= rtl8169_get_regs_len
,
1282 .get_link
= ethtool_op_get_link
,
1283 .get_settings
= rtl8169_get_settings
,
1284 .set_settings
= rtl8169_set_settings
,
1285 .get_msglevel
= rtl8169_get_msglevel
,
1286 .set_msglevel
= rtl8169_set_msglevel
,
1287 .get_rx_csum
= rtl8169_get_rx_csum
,
1288 .set_rx_csum
= rtl8169_set_rx_csum
,
1289 .set_tx_csum
= ethtool_op_set_tx_csum
,
1290 .set_sg
= ethtool_op_set_sg
,
1291 .set_tso
= ethtool_op_set_tso
,
1292 .get_regs
= rtl8169_get_regs
,
1293 .get_wol
= rtl8169_get_wol
,
1294 .set_wol
= rtl8169_set_wol
,
1295 .get_strings
= rtl8169_get_strings
,
1296 .get_sset_count
= rtl8169_get_sset_count
,
1297 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1300 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1301 void __iomem
*ioaddr
)
1304 * The driver currently handles the 8168Bf and the 8168Be identically
1305 * but they can be identified more specifically through the test below
1308 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1310 * Same thing for the 8101Eb and the 8101Ec:
1312 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1314 static const struct {
1320 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1321 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1322 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1323 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1326 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1327 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1328 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1329 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1330 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1331 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1332 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1333 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1334 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1337 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1338 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1339 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1340 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1343 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1344 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1345 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1346 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1347 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1348 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1349 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1350 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1351 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1352 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1353 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1354 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1355 /* FIXME: where did these entries come from ? -- FR */
1356 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1357 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1360 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1361 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1362 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1363 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1364 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1365 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1368 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1372 reg
= RTL_R32(TxConfig
);
1373 while ((reg
& p
->mask
) != p
->val
)
1375 tp
->mac_version
= p
->mac_version
;
1378 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1380 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1388 static void rtl_phy_write(void __iomem
*ioaddr
, const struct phy_reg
*regs
, int len
)
1391 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1396 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1398 static const struct phy_reg phy_reg_init
[] = {
1460 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1463 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1465 static const struct phy_reg phy_reg_init
[] = {
1471 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1474 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
,
1475 void __iomem
*ioaddr
)
1477 struct pci_dev
*pdev
= tp
->pci_dev
;
1478 u16 vendor_id
, device_id
;
1480 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1481 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1483 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1486 mdio_write(ioaddr
, 0x1f, 0x0001);
1487 mdio_write(ioaddr
, 0x10, 0xf01b);
1488 mdio_write(ioaddr
, 0x1f, 0x0000);
1491 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
,
1492 void __iomem
*ioaddr
)
1494 static const struct phy_reg phy_reg_init
[] = {
1534 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1536 rtl8169scd_hw_phy_config_quirk(tp
, ioaddr
);
1539 static void rtl8169sce_hw_phy_config(void __iomem
*ioaddr
)
1541 static const struct phy_reg phy_reg_init
[] = {
1589 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1592 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1594 static const struct phy_reg phy_reg_init
[] = {
1599 mdio_write(ioaddr
, 0x1f, 0x0001);
1600 mdio_patch(ioaddr
, 0x16, 1 << 0);
1602 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1605 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1607 static const struct phy_reg phy_reg_init
[] = {
1613 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1616 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1618 static const struct phy_reg phy_reg_init
[] = {
1626 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1629 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1631 static const struct phy_reg phy_reg_init
[] = {
1637 mdio_write(ioaddr
, 0x1f, 0x0000);
1638 mdio_patch(ioaddr
, 0x14, 1 << 5);
1639 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1641 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1644 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1646 static const struct phy_reg phy_reg_init
[] = {
1666 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1668 mdio_patch(ioaddr
, 0x14, 1 << 5);
1669 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1670 mdio_write(ioaddr
, 0x1f, 0x0000);
1673 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1675 static const struct phy_reg phy_reg_init
[] = {
1693 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1695 mdio_patch(ioaddr
, 0x16, 1 << 0);
1696 mdio_patch(ioaddr
, 0x14, 1 << 5);
1697 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1698 mdio_write(ioaddr
, 0x1f, 0x0000);
1701 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1703 static const struct phy_reg phy_reg_init
[] = {
1715 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1717 mdio_patch(ioaddr
, 0x16, 1 << 0);
1718 mdio_patch(ioaddr
, 0x14, 1 << 5);
1719 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1720 mdio_write(ioaddr
, 0x1f, 0x0000);
1723 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1725 rtl8168c_3_hw_phy_config(ioaddr
);
1728 static void rtl8168d_1_hw_phy_config(void __iomem
*ioaddr
)
1730 static const struct phy_reg phy_reg_init_0
[] = {
1749 static const struct phy_reg phy_reg_init_1
[] = {
1756 static const struct phy_reg phy_reg_init_2
[] = {
2112 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2114 mdio_write(ioaddr
, 0x1f, 0x0002);
2115 mdio_plus_minus(ioaddr
, 0x0b, 0x0010, 0x00ef);
2116 mdio_plus_minus(ioaddr
, 0x0c, 0xa200, 0x5d00);
2118 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2120 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2121 static const struct phy_reg phy_reg_init
[] = {
2131 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2133 val
= mdio_read(ioaddr
, 0x0d);
2135 if ((val
& 0x00ff) != 0x006c) {
2136 static const u32 set
[] = {
2137 0x0065, 0x0066, 0x0067, 0x0068,
2138 0x0069, 0x006a, 0x006b, 0x006c
2142 mdio_write(ioaddr
, 0x1f, 0x0002);
2145 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2146 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2149 static const struct phy_reg phy_reg_init
[] = {
2157 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2160 mdio_write(ioaddr
, 0x1f, 0x0002);
2161 mdio_patch(ioaddr
, 0x0d, 0x0300);
2162 mdio_patch(ioaddr
, 0x0f, 0x0010);
2164 mdio_write(ioaddr
, 0x1f, 0x0002);
2165 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2166 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2168 rtl_phy_write(ioaddr
, phy_reg_init_2
, ARRAY_SIZE(phy_reg_init_2
));
2171 static void rtl8168d_2_hw_phy_config(void __iomem
*ioaddr
)
2173 static const struct phy_reg phy_reg_init_0
[] = {
2198 static const struct phy_reg phy_reg_init_1
[] = {
2511 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2513 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2514 static const struct phy_reg phy_reg_init
[] = {
2525 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2527 val
= mdio_read(ioaddr
, 0x0d);
2528 if ((val
& 0x00ff) != 0x006c) {
2529 static const u32 set
[] = {
2530 0x0065, 0x0066, 0x0067, 0x0068,
2531 0x0069, 0x006a, 0x006b, 0x006c
2535 mdio_write(ioaddr
, 0x1f, 0x0002);
2538 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2539 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2542 static const struct phy_reg phy_reg_init
[] = {
2550 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2553 mdio_write(ioaddr
, 0x1f, 0x0002);
2554 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2555 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2557 mdio_write(ioaddr
, 0x1f, 0x0001);
2558 mdio_write(ioaddr
, 0x17, 0x0cc0);
2560 mdio_write(ioaddr
, 0x1f, 0x0002);
2561 mdio_patch(ioaddr
, 0x0f, 0x0017);
2563 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2566 static void rtl8168d_3_hw_phy_config(void __iomem
*ioaddr
)
2568 static const struct phy_reg phy_reg_init
[] = {
2624 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2627 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
2629 static const struct phy_reg phy_reg_init
[] = {
2636 mdio_write(ioaddr
, 0x1f, 0x0000);
2637 mdio_patch(ioaddr
, 0x11, 1 << 12);
2638 mdio_patch(ioaddr
, 0x19, 1 << 13);
2639 mdio_patch(ioaddr
, 0x10, 1 << 15);
2641 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2644 static void rtl_hw_phy_config(struct net_device
*dev
)
2646 struct rtl8169_private
*tp
= netdev_priv(dev
);
2647 void __iomem
*ioaddr
= tp
->mmio_addr
;
2649 rtl8169_print_mac_version(tp
);
2651 switch (tp
->mac_version
) {
2652 case RTL_GIGA_MAC_VER_01
:
2654 case RTL_GIGA_MAC_VER_02
:
2655 case RTL_GIGA_MAC_VER_03
:
2656 rtl8169s_hw_phy_config(ioaddr
);
2658 case RTL_GIGA_MAC_VER_04
:
2659 rtl8169sb_hw_phy_config(ioaddr
);
2661 case RTL_GIGA_MAC_VER_05
:
2662 rtl8169scd_hw_phy_config(tp
, ioaddr
);
2664 case RTL_GIGA_MAC_VER_06
:
2665 rtl8169sce_hw_phy_config(ioaddr
);
2667 case RTL_GIGA_MAC_VER_07
:
2668 case RTL_GIGA_MAC_VER_08
:
2669 case RTL_GIGA_MAC_VER_09
:
2670 rtl8102e_hw_phy_config(ioaddr
);
2672 case RTL_GIGA_MAC_VER_11
:
2673 rtl8168bb_hw_phy_config(ioaddr
);
2675 case RTL_GIGA_MAC_VER_12
:
2676 rtl8168bef_hw_phy_config(ioaddr
);
2678 case RTL_GIGA_MAC_VER_17
:
2679 rtl8168bef_hw_phy_config(ioaddr
);
2681 case RTL_GIGA_MAC_VER_18
:
2682 rtl8168cp_1_hw_phy_config(ioaddr
);
2684 case RTL_GIGA_MAC_VER_19
:
2685 rtl8168c_1_hw_phy_config(ioaddr
);
2687 case RTL_GIGA_MAC_VER_20
:
2688 rtl8168c_2_hw_phy_config(ioaddr
);
2690 case RTL_GIGA_MAC_VER_21
:
2691 rtl8168c_3_hw_phy_config(ioaddr
);
2693 case RTL_GIGA_MAC_VER_22
:
2694 rtl8168c_4_hw_phy_config(ioaddr
);
2696 case RTL_GIGA_MAC_VER_23
:
2697 case RTL_GIGA_MAC_VER_24
:
2698 rtl8168cp_2_hw_phy_config(ioaddr
);
2700 case RTL_GIGA_MAC_VER_25
:
2701 rtl8168d_1_hw_phy_config(ioaddr
);
2703 case RTL_GIGA_MAC_VER_26
:
2704 rtl8168d_2_hw_phy_config(ioaddr
);
2706 case RTL_GIGA_MAC_VER_27
:
2707 rtl8168d_3_hw_phy_config(ioaddr
);
2715 static void rtl8169_phy_timer(unsigned long __opaque
)
2717 struct net_device
*dev
= (struct net_device
*)__opaque
;
2718 struct rtl8169_private
*tp
= netdev_priv(dev
);
2719 struct timer_list
*timer
= &tp
->timer
;
2720 void __iomem
*ioaddr
= tp
->mmio_addr
;
2721 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2723 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2725 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
2728 spin_lock_irq(&tp
->lock
);
2730 if (tp
->phy_reset_pending(ioaddr
)) {
2732 * A busy loop could burn quite a few cycles on nowadays CPU.
2733 * Let's delay the execution of the timer for a few ticks.
2739 if (tp
->link_ok(ioaddr
))
2742 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
2744 tp
->phy_reset_enable(ioaddr
);
2747 mod_timer(timer
, jiffies
+ timeout
);
2749 spin_unlock_irq(&tp
->lock
);
2752 static inline void rtl8169_delete_timer(struct net_device
*dev
)
2754 struct rtl8169_private
*tp
= netdev_priv(dev
);
2755 struct timer_list
*timer
= &tp
->timer
;
2757 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2760 del_timer_sync(timer
);
2763 static inline void rtl8169_request_timer(struct net_device
*dev
)
2765 struct rtl8169_private
*tp
= netdev_priv(dev
);
2766 struct timer_list
*timer
= &tp
->timer
;
2768 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2771 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2774 #ifdef CONFIG_NET_POLL_CONTROLLER
2776 * Polling 'interrupt' - used by things like netconsole to send skbs
2777 * without having to re-enable interrupts. It's not called while
2778 * the interrupt routine is executing.
2780 static void rtl8169_netpoll(struct net_device
*dev
)
2782 struct rtl8169_private
*tp
= netdev_priv(dev
);
2783 struct pci_dev
*pdev
= tp
->pci_dev
;
2785 disable_irq(pdev
->irq
);
2786 rtl8169_interrupt(pdev
->irq
, dev
);
2787 enable_irq(pdev
->irq
);
2791 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2792 void __iomem
*ioaddr
)
2795 pci_release_regions(pdev
);
2796 pci_clear_mwi(pdev
);
2797 pci_disable_device(pdev
);
2801 static void rtl8169_phy_reset(struct net_device
*dev
,
2802 struct rtl8169_private
*tp
)
2804 void __iomem
*ioaddr
= tp
->mmio_addr
;
2807 tp
->phy_reset_enable(ioaddr
);
2808 for (i
= 0; i
< 100; i
++) {
2809 if (!tp
->phy_reset_pending(ioaddr
))
2813 netif_err(tp
, link
, dev
, "PHY reset failed\n");
2816 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2818 void __iomem
*ioaddr
= tp
->mmio_addr
;
2820 rtl_hw_phy_config(dev
);
2822 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2823 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2827 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2829 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2830 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2832 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2833 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2835 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2836 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
2839 rtl8169_phy_reset(dev
, tp
);
2842 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2843 * only 8101. Don't panic.
2845 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
2847 if (RTL_R8(PHYstatus
) & TBI_Enable
)
2848 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
2851 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2853 void __iomem
*ioaddr
= tp
->mmio_addr
;
2857 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2858 high
= addr
[4] | (addr
[5] << 8);
2860 spin_lock_irq(&tp
->lock
);
2862 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2864 RTL_W32(MAC4
, high
);
2870 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2872 spin_unlock_irq(&tp
->lock
);
2875 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2877 struct rtl8169_private
*tp
= netdev_priv(dev
);
2878 struct sockaddr
*addr
= p
;
2880 if (!is_valid_ether_addr(addr
->sa_data
))
2881 return -EADDRNOTAVAIL
;
2883 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2885 rtl_rar_set(tp
, dev
->dev_addr
);
2890 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2892 struct rtl8169_private
*tp
= netdev_priv(dev
);
2893 struct mii_ioctl_data
*data
= if_mii(ifr
);
2895 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2898 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2902 data
->phy_id
= 32; /* Internal PHY */
2906 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
2910 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
2916 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2921 static const struct rtl_cfg_info
{
2922 void (*hw_start
)(struct net_device
*);
2923 unsigned int region
;
2929 } rtl_cfg_infos
[] = {
2931 .hw_start
= rtl_hw_start_8169
,
2934 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2935 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2936 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2937 .features
= RTL_FEATURE_GMII
,
2938 .default_ver
= RTL_GIGA_MAC_VER_01
,
2941 .hw_start
= rtl_hw_start_8168
,
2944 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2945 TxErr
| TxOK
| RxOK
| RxErr
,
2946 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2947 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2948 .default_ver
= RTL_GIGA_MAC_VER_11
,
2951 .hw_start
= rtl_hw_start_8101
,
2954 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2955 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2956 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2957 .features
= RTL_FEATURE_MSI
,
2958 .default_ver
= RTL_GIGA_MAC_VER_13
,
2962 /* Cfg9346_Unlock assumed. */
2963 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2964 const struct rtl_cfg_info
*cfg
)
2969 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2970 if (cfg
->features
& RTL_FEATURE_MSI
) {
2971 if (pci_enable_msi(pdev
)) {
2972 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2975 msi
= RTL_FEATURE_MSI
;
2978 RTL_W8(Config2
, cfg2
);
2982 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2984 if (tp
->features
& RTL_FEATURE_MSI
) {
2985 pci_disable_msi(pdev
);
2986 tp
->features
&= ~RTL_FEATURE_MSI
;
2990 static const struct net_device_ops rtl8169_netdev_ops
= {
2991 .ndo_open
= rtl8169_open
,
2992 .ndo_stop
= rtl8169_close
,
2993 .ndo_get_stats
= rtl8169_get_stats
,
2994 .ndo_start_xmit
= rtl8169_start_xmit
,
2995 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2996 .ndo_validate_addr
= eth_validate_addr
,
2997 .ndo_change_mtu
= rtl8169_change_mtu
,
2998 .ndo_set_mac_address
= rtl_set_mac_address
,
2999 .ndo_do_ioctl
= rtl8169_ioctl
,
3000 .ndo_set_multicast_list
= rtl_set_rx_mode
,
3001 #ifdef CONFIG_R8169_VLAN
3002 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
3004 #ifdef CONFIG_NET_POLL_CONTROLLER
3005 .ndo_poll_controller
= rtl8169_netpoll
,
3010 static int __devinit
3011 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3013 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3014 const unsigned int region
= cfg
->region
;
3015 struct rtl8169_private
*tp
;
3016 struct mii_if_info
*mii
;
3017 struct net_device
*dev
;
3018 void __iomem
*ioaddr
;
3022 if (netif_msg_drv(&debug
)) {
3023 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3024 MODULENAME
, RTL8169_VERSION
);
3027 dev
= alloc_etherdev(sizeof (*tp
));
3029 if (netif_msg_drv(&debug
))
3030 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3035 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3036 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3037 tp
= netdev_priv(dev
);
3040 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3044 mii
->mdio_read
= rtl_mdio_read
;
3045 mii
->mdio_write
= rtl_mdio_write
;
3046 mii
->phy_id_mask
= 0x1f;
3047 mii
->reg_num_mask
= 0x1f;
3048 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3050 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3051 rc
= pci_enable_device(pdev
);
3053 netif_err(tp
, probe
, dev
, "enable failure\n");
3054 goto err_out_free_dev_1
;
3057 if (pci_set_mwi(pdev
) < 0)
3058 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3060 /* make sure PCI base addr 1 is MMIO */
3061 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3062 netif_err(tp
, probe
, dev
,
3063 "region #%d not an MMIO resource, aborting\n",
3069 /* check for weird/broken PCI region reporting */
3070 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3071 netif_err(tp
, probe
, dev
,
3072 "Invalid PCI region size(s), aborting\n");
3077 rc
= pci_request_regions(pdev
, MODULENAME
);
3079 netif_err(tp
, probe
, dev
, "could not request regions\n");
3083 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
3085 if ((sizeof(dma_addr_t
) > 4) &&
3086 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3087 tp
->cp_cmd
|= PCIDAC
;
3088 dev
->features
|= NETIF_F_HIGHDMA
;
3090 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3092 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3093 goto err_out_free_res_3
;
3097 /* ioremap MMIO region */
3098 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3100 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3102 goto err_out_free_res_3
;
3105 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3107 netif_info(tp
, probe
, dev
, "no PCI Express capability\n");
3109 RTL_W16(IntrMask
, 0x0000);
3111 /* Soft reset the chip. */
3112 RTL_W8(ChipCmd
, CmdReset
);
3114 /* Check that the chip has finished the reset. */
3115 for (i
= 0; i
< 100; i
++) {
3116 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3118 msleep_interruptible(1);
3121 RTL_W16(IntrStatus
, 0xffff);
3123 pci_set_master(pdev
);
3125 /* Identify chip attached to board */
3126 rtl8169_get_mac_version(tp
, ioaddr
);
3128 /* Use appropriate default if unknown */
3129 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
3130 netif_notice(tp
, probe
, dev
,
3131 "unknown MAC, using family default\n");
3132 tp
->mac_version
= cfg
->default_ver
;
3135 rtl8169_print_mac_version(tp
);
3137 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
3138 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
3141 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
3143 "driver bug, MAC version not found in rtl_chip_info\n");
3148 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3149 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3150 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3151 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3152 tp
->features
|= RTL_FEATURE_WOL
;
3153 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3154 tp
->features
|= RTL_FEATURE_WOL
;
3155 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3156 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3158 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3159 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3160 tp
->set_speed
= rtl8169_set_speed_tbi
;
3161 tp
->get_settings
= rtl8169_gset_tbi
;
3162 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3163 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3164 tp
->link_ok
= rtl8169_tbi_link_ok
;
3165 tp
->do_ioctl
= rtl_tbi_ioctl
;
3167 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
3169 tp
->set_speed
= rtl8169_set_speed_xmii
;
3170 tp
->get_settings
= rtl8169_gset_xmii
;
3171 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3172 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3173 tp
->link_ok
= rtl8169_xmii_link_ok
;
3174 tp
->do_ioctl
= rtl_xmii_ioctl
;
3177 spin_lock_init(&tp
->lock
);
3179 tp
->mmio_addr
= ioaddr
;
3181 /* Get MAC address */
3182 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3183 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3184 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3186 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3187 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3188 dev
->irq
= pdev
->irq
;
3189 dev
->base_addr
= (unsigned long) ioaddr
;
3191 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3193 #ifdef CONFIG_R8169_VLAN
3194 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3196 dev
->features
|= NETIF_F_GRO
;
3198 tp
->intr_mask
= 0xffff;
3199 tp
->hw_start
= cfg
->hw_start
;
3200 tp
->intr_event
= cfg
->intr_event
;
3201 tp
->napi_event
= cfg
->napi_event
;
3203 init_timer(&tp
->timer
);
3204 tp
->timer
.data
= (unsigned long) dev
;
3205 tp
->timer
.function
= rtl8169_phy_timer
;
3207 rc
= register_netdev(dev
);
3211 pci_set_drvdata(pdev
, dev
);
3213 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3214 rtl_chip_info
[tp
->chipset
].name
,
3215 dev
->base_addr
, dev
->dev_addr
,
3216 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3218 rtl8169_init_phy(dev
, tp
);
3221 * Pretend we are using VLANs; This bypasses a nasty bug where
3222 * Interrupts stop flowing on high load on 8110SCd controllers.
3224 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3225 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | RxVlan
);
3227 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3229 if (pci_dev_run_wake(pdev
))
3230 pm_runtime_put_noidle(&pdev
->dev
);
3236 rtl_disable_msi(pdev
, tp
);
3239 pci_release_regions(pdev
);
3241 pci_clear_mwi(pdev
);
3242 pci_disable_device(pdev
);
3248 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3250 struct net_device
*dev
= pci_get_drvdata(pdev
);
3251 struct rtl8169_private
*tp
= netdev_priv(dev
);
3253 cancel_delayed_work_sync(&tp
->task
);
3255 unregister_netdev(dev
);
3257 if (pci_dev_run_wake(pdev
))
3258 pm_runtime_get_noresume(&pdev
->dev
);
3260 /* restore original MAC address */
3261 rtl_rar_set(tp
, dev
->perm_addr
);
3263 rtl_disable_msi(pdev
, tp
);
3264 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3265 pci_set_drvdata(pdev
, NULL
);
3268 static int rtl8169_open(struct net_device
*dev
)
3270 struct rtl8169_private
*tp
= netdev_priv(dev
);
3271 struct pci_dev
*pdev
= tp
->pci_dev
;
3272 int retval
= -ENOMEM
;
3274 pm_runtime_get_sync(&pdev
->dev
);
3277 * Rx and Tx desscriptors needs 256 bytes alignment.
3278 * dma_alloc_coherent provides more.
3280 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3281 &tp
->TxPhyAddr
, GFP_KERNEL
);
3282 if (!tp
->TxDescArray
)
3283 goto err_pm_runtime_put
;
3285 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3286 &tp
->RxPhyAddr
, GFP_KERNEL
);
3287 if (!tp
->RxDescArray
)
3290 retval
= rtl8169_init_ring(dev
);
3294 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3298 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3299 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3302 goto err_release_ring_2
;
3304 napi_enable(&tp
->napi
);
3308 rtl8169_request_timer(dev
);
3310 tp
->saved_wolopts
= 0;
3311 pm_runtime_put_noidle(&pdev
->dev
);
3313 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3318 rtl8169_rx_clear(tp
);
3320 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3322 tp
->RxDescArray
= NULL
;
3324 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3326 tp
->TxDescArray
= NULL
;
3328 pm_runtime_put_noidle(&pdev
->dev
);
3332 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
3334 /* Disable interrupts */
3335 rtl8169_irq_mask_and_ack(ioaddr
);
3337 /* Reset the chipset */
3338 RTL_W8(ChipCmd
, CmdReset
);
3344 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3346 void __iomem
*ioaddr
= tp
->mmio_addr
;
3347 u32 cfg
= rtl8169_rx_config
;
3349 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3350 RTL_W32(RxConfig
, cfg
);
3352 /* Set DMA burst size and Interframe Gap Time */
3353 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3354 (InterFrameGap
<< TxInterFrameGapShift
));
3357 static void rtl_hw_start(struct net_device
*dev
)
3359 struct rtl8169_private
*tp
= netdev_priv(dev
);
3360 void __iomem
*ioaddr
= tp
->mmio_addr
;
3363 /* Soft reset the chip. */
3364 RTL_W8(ChipCmd
, CmdReset
);
3366 /* Check that the chip has finished the reset. */
3367 for (i
= 0; i
< 100; i
++) {
3368 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3370 msleep_interruptible(1);
3375 netif_start_queue(dev
);
3379 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3380 void __iomem
*ioaddr
)
3383 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3384 * register to be written before TxDescAddrLow to work.
3385 * Switching from MMIO to I/O access fixes the issue as well.
3387 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3388 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3389 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3390 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3393 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3397 cmd
= RTL_R16(CPlusCmd
);
3398 RTL_W16(CPlusCmd
, cmd
);
3402 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3404 /* Low hurts. Let's disable the filtering. */
3405 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3408 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3410 static const struct {
3415 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3416 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3417 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3418 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3423 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3424 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3425 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3426 RTL_W32(0x7c, p
->val
);
3432 static void rtl_hw_start_8169(struct net_device
*dev
)
3434 struct rtl8169_private
*tp
= netdev_priv(dev
);
3435 void __iomem
*ioaddr
= tp
->mmio_addr
;
3436 struct pci_dev
*pdev
= tp
->pci_dev
;
3438 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3439 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3440 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3443 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3444 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3445 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3446 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3447 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3448 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3450 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3452 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3454 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3455 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3456 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3457 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3458 rtl_set_rx_tx_config_registers(tp
);
3460 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3462 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3463 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
3464 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3465 "Bit-3 and bit-14 MUST be 1\n");
3466 tp
->cp_cmd
|= (1 << 14);
3469 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3471 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3474 * Undocumented corner. Supposedly:
3475 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3477 RTL_W16(IntrMitigate
, 0x0000);
3479 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3481 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
3482 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
3483 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
3484 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
3485 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3486 rtl_set_rx_tx_config_registers(tp
);
3489 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3491 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3494 RTL_W32(RxMissed
, 0);
3496 rtl_set_rx_mode(dev
);
3498 /* no early-rx interrupts */
3499 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3501 /* Enable all known interrupts by setting the interrupt mask. */
3502 RTL_W16(IntrMask
, tp
->intr_event
);
3505 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3507 struct net_device
*dev
= pci_get_drvdata(pdev
);
3508 struct rtl8169_private
*tp
= netdev_priv(dev
);
3509 int cap
= tp
->pcie_cap
;
3514 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3515 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3516 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3520 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
3524 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3525 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
3529 unsigned int offset
;
3534 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
3539 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3540 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3545 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3547 struct net_device
*dev
= pci_get_drvdata(pdev
);
3548 struct rtl8169_private
*tp
= netdev_priv(dev
);
3549 int cap
= tp
->pcie_cap
;
3554 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3555 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3556 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3560 #define R8168_CPCMD_QUIRK_MASK (\
3571 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3573 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3575 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3577 rtl_tx_performance_tweak(pdev
,
3578 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3581 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3583 rtl_hw_start_8168bb(ioaddr
, pdev
);
3585 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3587 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3590 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3592 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3594 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3596 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3598 rtl_disable_clock_request(pdev
);
3600 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3603 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3605 static const struct ephy_info e_info_8168cp
[] = {
3606 { 0x01, 0, 0x0001 },
3607 { 0x02, 0x0800, 0x1000 },
3608 { 0x03, 0, 0x0042 },
3609 { 0x06, 0x0080, 0x0000 },
3613 rtl_csi_access_enable(ioaddr
);
3615 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3617 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3620 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3622 rtl_csi_access_enable(ioaddr
);
3624 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3626 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3628 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3631 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3633 rtl_csi_access_enable(ioaddr
);
3635 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3638 RTL_W8(DBG_REG
, 0x20);
3640 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3642 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3644 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3647 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3649 static const struct ephy_info e_info_8168c_1
[] = {
3650 { 0x02, 0x0800, 0x1000 },
3651 { 0x03, 0, 0x0002 },
3652 { 0x06, 0x0080, 0x0000 }
3655 rtl_csi_access_enable(ioaddr
);
3657 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3659 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3661 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3664 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3666 static const struct ephy_info e_info_8168c_2
[] = {
3667 { 0x01, 0, 0x0001 },
3668 { 0x03, 0x0400, 0x0220 }
3671 rtl_csi_access_enable(ioaddr
);
3673 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
3675 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3678 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3680 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3683 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3685 rtl_csi_access_enable(ioaddr
);
3687 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3690 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3692 rtl_csi_access_enable(ioaddr
);
3694 rtl_disable_clock_request(pdev
);
3696 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3698 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3700 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3703 static void rtl_hw_start_8168(struct net_device
*dev
)
3705 struct rtl8169_private
*tp
= netdev_priv(dev
);
3706 void __iomem
*ioaddr
= tp
->mmio_addr
;
3707 struct pci_dev
*pdev
= tp
->pci_dev
;
3709 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3711 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3713 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3715 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
3717 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3719 RTL_W16(IntrMitigate
, 0x5151);
3721 /* Work around for RxFIFO overflow. */
3722 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
3723 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
3724 tp
->intr_event
&= ~RxOverflow
;
3727 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3729 rtl_set_rx_mode(dev
);
3731 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3732 (InterFrameGap
<< TxInterFrameGapShift
));
3736 switch (tp
->mac_version
) {
3737 case RTL_GIGA_MAC_VER_11
:
3738 rtl_hw_start_8168bb(ioaddr
, pdev
);
3741 case RTL_GIGA_MAC_VER_12
:
3742 case RTL_GIGA_MAC_VER_17
:
3743 rtl_hw_start_8168bef(ioaddr
, pdev
);
3746 case RTL_GIGA_MAC_VER_18
:
3747 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
3750 case RTL_GIGA_MAC_VER_19
:
3751 rtl_hw_start_8168c_1(ioaddr
, pdev
);
3754 case RTL_GIGA_MAC_VER_20
:
3755 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3758 case RTL_GIGA_MAC_VER_21
:
3759 rtl_hw_start_8168c_3(ioaddr
, pdev
);
3762 case RTL_GIGA_MAC_VER_22
:
3763 rtl_hw_start_8168c_4(ioaddr
, pdev
);
3766 case RTL_GIGA_MAC_VER_23
:
3767 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
3770 case RTL_GIGA_MAC_VER_24
:
3771 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
3774 case RTL_GIGA_MAC_VER_25
:
3775 case RTL_GIGA_MAC_VER_26
:
3776 case RTL_GIGA_MAC_VER_27
:
3777 rtl_hw_start_8168d(ioaddr
, pdev
);
3781 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
3782 dev
->name
, tp
->mac_version
);
3786 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3788 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3790 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3792 RTL_W16(IntrMask
, tp
->intr_event
);
3795 #define R810X_CPCMD_QUIRK_MASK (\
3807 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3809 static const struct ephy_info e_info_8102e_1
[] = {
3810 { 0x01, 0, 0x6e65 },
3811 { 0x02, 0, 0x091f },
3812 { 0x03, 0, 0xc2f9 },
3813 { 0x06, 0, 0xafb5 },
3814 { 0x07, 0, 0x0e00 },
3815 { 0x19, 0, 0xec80 },
3816 { 0x01, 0, 0x2e65 },
3821 rtl_csi_access_enable(ioaddr
);
3823 RTL_W8(DBG_REG
, FIX_NAK_1
);
3825 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3828 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
3829 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3831 cfg1
= RTL_R8(Config1
);
3832 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
3833 RTL_W8(Config1
, cfg1
& ~LEDS0
);
3835 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3837 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
3840 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3842 rtl_csi_access_enable(ioaddr
);
3844 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3846 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
3847 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3849 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3852 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3854 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3856 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
3859 static void rtl_hw_start_8101(struct net_device
*dev
)
3861 struct rtl8169_private
*tp
= netdev_priv(dev
);
3862 void __iomem
*ioaddr
= tp
->mmio_addr
;
3863 struct pci_dev
*pdev
= tp
->pci_dev
;
3865 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
3866 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
3867 int cap
= tp
->pcie_cap
;
3870 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
3871 PCI_EXP_DEVCTL_NOSNOOP_EN
);
3875 switch (tp
->mac_version
) {
3876 case RTL_GIGA_MAC_VER_07
:
3877 rtl_hw_start_8102e_1(ioaddr
, pdev
);
3880 case RTL_GIGA_MAC_VER_08
:
3881 rtl_hw_start_8102e_3(ioaddr
, pdev
);
3884 case RTL_GIGA_MAC_VER_09
:
3885 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3889 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3891 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3893 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3895 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3897 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3899 RTL_W16(IntrMitigate
, 0x0000);
3901 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3903 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3904 rtl_set_rx_tx_config_registers(tp
);
3906 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3910 rtl_set_rx_mode(dev
);
3912 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3914 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
3916 RTL_W16(IntrMask
, tp
->intr_event
);
3919 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3921 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
3928 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
3930 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
3931 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
3934 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
3935 void **data_buff
, struct RxDesc
*desc
)
3937 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
3942 rtl8169_make_unusable_by_asic(desc
);
3945 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
3947 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3949 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
3952 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
3955 desc
->addr
= cpu_to_le64(mapping
);
3957 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
3960 static inline void *rtl8169_align(void *data
)
3962 return (void *)ALIGN((long)data
, 16);
3965 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
3966 struct RxDesc
*desc
)
3970 struct device
*d
= &tp
->pci_dev
->dev
;
3971 struct net_device
*dev
= tp
->dev
;
3972 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
3974 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
3978 if (rtl8169_align(data
) != data
) {
3980 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
3985 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
3987 if (unlikely(dma_mapping_error(d
, mapping
))) {
3988 if (net_ratelimit())
3989 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
3993 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4001 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4005 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4006 if (tp
->Rx_databuff
[i
]) {
4007 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4008 tp
->RxDescArray
+ i
);
4013 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4015 desc
->opts1
|= cpu_to_le32(RingEnd
);
4018 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
4022 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4025 if (tp
->Rx_databuff
[i
])
4028 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
4030 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4033 tp
->Rx_databuff
[i
] = data
;
4036 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4040 rtl8169_rx_clear(tp
);
4044 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4046 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4049 static int rtl8169_init_ring(struct net_device
*dev
)
4051 struct rtl8169_private
*tp
= netdev_priv(dev
);
4053 rtl8169_init_ring_indexes(tp
);
4055 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4056 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4058 return rtl8169_rx_fill(tp
);
4061 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
4062 struct TxDesc
*desc
)
4064 unsigned int len
= tx_skb
->len
;
4066 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
4074 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
4079 for (i
= 0; i
< n
; i
++) {
4080 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
4081 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4082 unsigned int len
= tx_skb
->len
;
4085 struct sk_buff
*skb
= tx_skb
->skb
;
4087 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4088 tp
->TxDescArray
+ entry
);
4090 tp
->dev
->stats
.tx_dropped
++;
4098 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4100 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
4101 tp
->cur_tx
= tp
->dirty_tx
= 0;
4104 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4106 struct rtl8169_private
*tp
= netdev_priv(dev
);
4108 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4109 schedule_delayed_work(&tp
->task
, 4);
4112 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4114 struct rtl8169_private
*tp
= netdev_priv(dev
);
4115 void __iomem
*ioaddr
= tp
->mmio_addr
;
4117 synchronize_irq(dev
->irq
);
4119 /* Wait for any pending NAPI task to complete */
4120 napi_disable(&tp
->napi
);
4122 rtl8169_irq_mask_and_ack(ioaddr
);
4124 tp
->intr_mask
= 0xffff;
4125 RTL_W16(IntrMask
, tp
->intr_event
);
4126 napi_enable(&tp
->napi
);
4129 static void rtl8169_reinit_task(struct work_struct
*work
)
4131 struct rtl8169_private
*tp
=
4132 container_of(work
, struct rtl8169_private
, task
.work
);
4133 struct net_device
*dev
= tp
->dev
;
4138 if (!netif_running(dev
))
4141 rtl8169_wait_for_quiescence(dev
);
4144 ret
= rtl8169_open(dev
);
4145 if (unlikely(ret
< 0)) {
4146 if (net_ratelimit())
4147 netif_err(tp
, drv
, dev
,
4148 "reinit failure (status = %d). Rescheduling\n",
4150 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4157 static void rtl8169_reset_task(struct work_struct
*work
)
4159 struct rtl8169_private
*tp
=
4160 container_of(work
, struct rtl8169_private
, task
.work
);
4161 struct net_device
*dev
= tp
->dev
;
4165 if (!netif_running(dev
))
4168 rtl8169_wait_for_quiescence(dev
);
4170 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
4171 rtl8169_tx_clear(tp
);
4173 if (tp
->dirty_rx
== tp
->cur_rx
) {
4174 rtl8169_init_ring_indexes(tp
);
4176 netif_wake_queue(dev
);
4177 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4179 if (net_ratelimit())
4180 netif_emerg(tp
, intr
, dev
, "Rx buffers shortage\n");
4181 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4188 static void rtl8169_tx_timeout(struct net_device
*dev
)
4190 struct rtl8169_private
*tp
= netdev_priv(dev
);
4192 rtl8169_hw_reset(tp
->mmio_addr
);
4194 /* Let's wait a bit while any (async) irq lands on */
4195 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4198 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4201 struct skb_shared_info
*info
= skb_shinfo(skb
);
4202 unsigned int cur_frag
, entry
;
4203 struct TxDesc
* uninitialized_var(txd
);
4204 struct device
*d
= &tp
->pci_dev
->dev
;
4207 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4208 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4213 entry
= (entry
+ 1) % NUM_TX_DESC
;
4215 txd
= tp
->TxDescArray
+ entry
;
4217 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4218 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
4219 if (unlikely(dma_mapping_error(d
, mapping
))) {
4220 if (net_ratelimit())
4221 netif_err(tp
, drv
, tp
->dev
,
4222 "Failed to map TX fragments DMA!\n");
4226 /* anti gcc 2.95.3 bugware (sic) */
4227 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4229 txd
->opts1
= cpu_to_le32(status
);
4230 txd
->addr
= cpu_to_le64(mapping
);
4232 tp
->tx_skb
[entry
].len
= len
;
4236 tp
->tx_skb
[entry
].skb
= skb
;
4237 txd
->opts1
|= cpu_to_le32(LastFrag
);
4243 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
4247 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
4249 if (dev
->features
& NETIF_F_TSO
) {
4250 u32 mss
= skb_shinfo(skb
)->gso_size
;
4253 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
4255 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4256 const struct iphdr
*ip
= ip_hdr(skb
);
4258 if (ip
->protocol
== IPPROTO_TCP
)
4259 return IPCS
| TCPCS
;
4260 else if (ip
->protocol
== IPPROTO_UDP
)
4261 return IPCS
| UDPCS
;
4262 WARN_ON(1); /* we need a WARN() */
4267 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4268 struct net_device
*dev
)
4270 struct rtl8169_private
*tp
= netdev_priv(dev
);
4271 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
4272 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4273 void __iomem
*ioaddr
= tp
->mmio_addr
;
4274 struct device
*d
= &tp
->pci_dev
->dev
;
4280 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4281 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
4285 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4288 len
= skb_headlen(skb
);
4289 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
4290 if (unlikely(dma_mapping_error(d
, mapping
))) {
4291 if (net_ratelimit())
4292 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
4296 tp
->tx_skb
[entry
].len
= len
;
4297 txd
->addr
= cpu_to_le64(mapping
);
4298 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4300 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
4302 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
4308 opts1
|= FirstFrag
| LastFrag
;
4309 tp
->tx_skb
[entry
].skb
= skb
;
4314 /* anti gcc 2.95.3 bugware (sic) */
4315 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4316 txd
->opts1
= cpu_to_le32(status
);
4318 tp
->cur_tx
+= frags
+ 1;
4322 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
4324 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4325 netif_stop_queue(dev
);
4327 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4328 netif_wake_queue(dev
);
4331 return NETDEV_TX_OK
;
4334 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
4337 dev
->stats
.tx_dropped
++;
4338 return NETDEV_TX_OK
;
4341 netif_stop_queue(dev
);
4342 dev
->stats
.tx_dropped
++;
4343 return NETDEV_TX_BUSY
;
4346 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4348 struct rtl8169_private
*tp
= netdev_priv(dev
);
4349 struct pci_dev
*pdev
= tp
->pci_dev
;
4350 void __iomem
*ioaddr
= tp
->mmio_addr
;
4351 u16 pci_status
, pci_cmd
;
4353 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4354 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4356 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4357 pci_cmd
, pci_status
);
4360 * The recovery sequence below admits a very elaborated explanation:
4361 * - it seems to work;
4362 * - I did not see what else could be done;
4363 * - it makes iop3xx happy.
4365 * Feel free to adjust to your needs.
4367 if (pdev
->broken_parity_status
)
4368 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4370 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4372 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4374 pci_write_config_word(pdev
, PCI_STATUS
,
4375 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4376 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4377 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4379 /* The infamous DAC f*ckup only happens at boot time */
4380 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4381 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
4382 tp
->cp_cmd
&= ~PCIDAC
;
4383 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4384 dev
->features
&= ~NETIF_F_HIGHDMA
;
4387 rtl8169_hw_reset(ioaddr
);
4389 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4392 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4393 struct rtl8169_private
*tp
,
4394 void __iomem
*ioaddr
)
4396 unsigned int dirty_tx
, tx_left
;
4398 dirty_tx
= tp
->dirty_tx
;
4400 tx_left
= tp
->cur_tx
- dirty_tx
;
4402 while (tx_left
> 0) {
4403 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4404 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4408 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4409 if (status
& DescOwn
)
4412 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4413 tp
->TxDescArray
+ entry
);
4414 if (status
& LastFrag
) {
4415 dev
->stats
.tx_packets
++;
4416 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
4417 dev_kfree_skb(tx_skb
->skb
);
4424 if (tp
->dirty_tx
!= dirty_tx
) {
4425 tp
->dirty_tx
= dirty_tx
;
4427 if (netif_queue_stopped(dev
) &&
4428 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4429 netif_wake_queue(dev
);
4432 * 8168 hack: TxPoll requests are lost when the Tx packets are
4433 * too close. Let's kick an extra TxPoll request when a burst
4434 * of start_xmit activity is detected (if it is not detected,
4435 * it is slow enough). -- FR
4438 if (tp
->cur_tx
!= dirty_tx
)
4439 RTL_W8(TxPoll
, NPQ
);
4443 static inline int rtl8169_fragmented_frame(u32 status
)
4445 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4448 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
4450 u32 status
= opts1
& RxProtoMask
;
4452 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4453 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
4454 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4456 skb_checksum_none_assert(skb
);
4459 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
4460 struct rtl8169_private
*tp
,
4464 struct sk_buff
*skb
;
4465 struct device
*d
= &tp
->pci_dev
->dev
;
4467 data
= rtl8169_align(data
);
4468 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4470 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
4472 memcpy(skb
->data
, data
, pkt_size
);
4473 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4479 * Warning : rtl8169_rx_interrupt() might be called :
4480 * 1) from NAPI (softirq) context
4481 * (polling = 1 : we should call netif_receive_skb())
4482 * 2) from process context (rtl8169_reset_task())
4483 * (polling = 0 : we must call netif_rx() instead)
4485 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4486 struct rtl8169_private
*tp
,
4487 void __iomem
*ioaddr
, u32 budget
)
4489 unsigned int cur_rx
, rx_left
;
4491 int polling
= (budget
!= ~(u32
)0) ? 1 : 0;
4493 cur_rx
= tp
->cur_rx
;
4494 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4495 rx_left
= min(rx_left
, budget
);
4497 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4498 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4499 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4503 status
= le32_to_cpu(desc
->opts1
);
4505 if (status
& DescOwn
)
4507 if (unlikely(status
& RxRES
)) {
4508 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
4510 dev
->stats
.rx_errors
++;
4511 if (status
& (RxRWT
| RxRUNT
))
4512 dev
->stats
.rx_length_errors
++;
4514 dev
->stats
.rx_crc_errors
++;
4515 if (status
& RxFOVF
) {
4516 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4517 dev
->stats
.rx_fifo_errors
++;
4519 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4521 struct sk_buff
*skb
;
4522 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4523 int pkt_size
= (status
& 0x00001FFF) - 4;
4526 * The driver does not support incoming fragmented
4527 * frames. They are seen as a symptom of over-mtu
4530 if (unlikely(rtl8169_fragmented_frame(status
))) {
4531 dev
->stats
.rx_dropped
++;
4532 dev
->stats
.rx_length_errors
++;
4533 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4537 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
4538 tp
, pkt_size
, addr
);
4539 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4541 dev
->stats
.rx_dropped
++;
4545 rtl8169_rx_csum(skb
, status
);
4546 skb_put(skb
, pkt_size
);
4547 skb
->protocol
= eth_type_trans(skb
, dev
);
4549 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
, polling
) < 0) {
4550 if (likely(polling
))
4551 napi_gro_receive(&tp
->napi
, skb
);
4556 dev
->stats
.rx_bytes
+= pkt_size
;
4557 dev
->stats
.rx_packets
++;
4560 /* Work around for AMD plateform. */
4561 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
4562 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
4568 count
= cur_rx
- tp
->cur_rx
;
4569 tp
->cur_rx
= cur_rx
;
4571 tp
->dirty_rx
+= count
;
4576 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4578 struct net_device
*dev
= dev_instance
;
4579 struct rtl8169_private
*tp
= netdev_priv(dev
);
4580 void __iomem
*ioaddr
= tp
->mmio_addr
;
4584 /* loop handling interrupts until we have no new ones or
4585 * we hit a invalid/hotplug case.
4587 status
= RTL_R16(IntrStatus
);
4588 while (status
&& status
!= 0xffff) {
4591 /* Handle all of the error cases first. These will reset
4592 * the chip, so just exit the loop.
4594 if (unlikely(!netif_running(dev
))) {
4595 rtl8169_asic_down(ioaddr
);
4599 /* Work around for rx fifo overflow */
4600 if (unlikely(status
& RxFIFOOver
) &&
4601 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
4602 netif_stop_queue(dev
);
4603 rtl8169_tx_timeout(dev
);
4607 if (unlikely(status
& SYSErr
)) {
4608 rtl8169_pcierr_interrupt(dev
);
4612 if (status
& LinkChg
)
4613 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
4615 /* We need to see the lastest version of tp->intr_mask to
4616 * avoid ignoring an MSI interrupt and having to wait for
4617 * another event which may never come.
4620 if (status
& tp
->intr_mask
& tp
->napi_event
) {
4621 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
4622 tp
->intr_mask
= ~tp
->napi_event
;
4624 if (likely(napi_schedule_prep(&tp
->napi
)))
4625 __napi_schedule(&tp
->napi
);
4627 netif_info(tp
, intr
, dev
,
4628 "interrupt %04x in poll\n", status
);
4631 /* We only get a new MSI interrupt when all active irq
4632 * sources on the chip have been acknowledged. So, ack
4633 * everything we've seen and check if new sources have become
4634 * active to avoid blocking all interrupts from the chip.
4637 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
4638 status
= RTL_R16(IntrStatus
);
4641 return IRQ_RETVAL(handled
);
4644 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
4646 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
4647 struct net_device
*dev
= tp
->dev
;
4648 void __iomem
*ioaddr
= tp
->mmio_addr
;
4651 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
4652 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
4654 if (work_done
< budget
) {
4655 napi_complete(napi
);
4657 /* We need for force the visibility of tp->intr_mask
4658 * for other CPUs, as we can loose an MSI interrupt
4659 * and potentially wait for a retransmit timeout if we don't.
4660 * The posted write to IntrMask is safe, as it will
4661 * eventually make it to the chip and we won't loose anything
4664 tp
->intr_mask
= 0xffff;
4666 RTL_W16(IntrMask
, tp
->intr_event
);
4672 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
4674 struct rtl8169_private
*tp
= netdev_priv(dev
);
4676 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
4679 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
4680 RTL_W32(RxMissed
, 0);
4683 static void rtl8169_down(struct net_device
*dev
)
4685 struct rtl8169_private
*tp
= netdev_priv(dev
);
4686 void __iomem
*ioaddr
= tp
->mmio_addr
;
4688 rtl8169_delete_timer(dev
);
4690 netif_stop_queue(dev
);
4692 napi_disable(&tp
->napi
);
4694 spin_lock_irq(&tp
->lock
);
4696 rtl8169_asic_down(ioaddr
);
4698 * At this point device interrupts can not be enabled in any function,
4699 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4700 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4702 rtl8169_rx_missed(dev
, ioaddr
);
4704 spin_unlock_irq(&tp
->lock
);
4706 synchronize_irq(dev
->irq
);
4708 /* Give a racing hard_start_xmit a few cycles to complete. */
4709 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4711 rtl8169_tx_clear(tp
);
4713 rtl8169_rx_clear(tp
);
4716 static int rtl8169_close(struct net_device
*dev
)
4718 struct rtl8169_private
*tp
= netdev_priv(dev
);
4719 struct pci_dev
*pdev
= tp
->pci_dev
;
4721 pm_runtime_get_sync(&pdev
->dev
);
4723 /* update counters before going down */
4724 rtl8169_update_counters(dev
);
4728 free_irq(dev
->irq
, dev
);
4730 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4732 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4734 tp
->TxDescArray
= NULL
;
4735 tp
->RxDescArray
= NULL
;
4737 pm_runtime_put_sync(&pdev
->dev
);
4742 static void rtl_set_rx_mode(struct net_device
*dev
)
4744 struct rtl8169_private
*tp
= netdev_priv(dev
);
4745 void __iomem
*ioaddr
= tp
->mmio_addr
;
4746 unsigned long flags
;
4747 u32 mc_filter
[2]; /* Multicast hash filter */
4751 if (dev
->flags
& IFF_PROMISC
) {
4752 /* Unconditionally log net taps. */
4753 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4755 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4757 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4758 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
4759 (dev
->flags
& IFF_ALLMULTI
)) {
4760 /* Too many to filter perfectly -- accept all multicasts. */
4761 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4762 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4764 struct netdev_hw_addr
*ha
;
4766 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4767 mc_filter
[1] = mc_filter
[0] = 0;
4768 netdev_for_each_mc_addr(ha
, dev
) {
4769 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4770 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4771 rx_mode
|= AcceptMulticast
;
4775 spin_lock_irqsave(&tp
->lock
, flags
);
4777 tmp
= rtl8169_rx_config
| rx_mode
|
4778 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
4780 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4781 u32 data
= mc_filter
[0];
4783 mc_filter
[0] = swab32(mc_filter
[1]);
4784 mc_filter
[1] = swab32(data
);
4787 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4788 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4790 RTL_W32(RxConfig
, tmp
);
4792 spin_unlock_irqrestore(&tp
->lock
, flags
);
4796 * rtl8169_get_stats - Get rtl8169 read/write statistics
4797 * @dev: The Ethernet Device to get statistics for
4799 * Get TX/RX statistics for rtl8169
4801 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
4803 struct rtl8169_private
*tp
= netdev_priv(dev
);
4804 void __iomem
*ioaddr
= tp
->mmio_addr
;
4805 unsigned long flags
;
4807 if (netif_running(dev
)) {
4808 spin_lock_irqsave(&tp
->lock
, flags
);
4809 rtl8169_rx_missed(dev
, ioaddr
);
4810 spin_unlock_irqrestore(&tp
->lock
, flags
);
4816 static void rtl8169_net_suspend(struct net_device
*dev
)
4818 if (!netif_running(dev
))
4821 netif_device_detach(dev
);
4822 netif_stop_queue(dev
);
4827 static int rtl8169_suspend(struct device
*device
)
4829 struct pci_dev
*pdev
= to_pci_dev(device
);
4830 struct net_device
*dev
= pci_get_drvdata(pdev
);
4832 rtl8169_net_suspend(dev
);
4837 static void __rtl8169_resume(struct net_device
*dev
)
4839 netif_device_attach(dev
);
4840 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4843 static int rtl8169_resume(struct device
*device
)
4845 struct pci_dev
*pdev
= to_pci_dev(device
);
4846 struct net_device
*dev
= pci_get_drvdata(pdev
);
4847 struct rtl8169_private
*tp
= netdev_priv(dev
);
4849 rtl8169_init_phy(dev
, tp
);
4851 if (netif_running(dev
))
4852 __rtl8169_resume(dev
);
4857 static int rtl8169_runtime_suspend(struct device
*device
)
4859 struct pci_dev
*pdev
= to_pci_dev(device
);
4860 struct net_device
*dev
= pci_get_drvdata(pdev
);
4861 struct rtl8169_private
*tp
= netdev_priv(dev
);
4863 if (!tp
->TxDescArray
)
4866 spin_lock_irq(&tp
->lock
);
4867 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
4868 __rtl8169_set_wol(tp
, WAKE_ANY
);
4869 spin_unlock_irq(&tp
->lock
);
4871 rtl8169_net_suspend(dev
);
4876 static int rtl8169_runtime_resume(struct device
*device
)
4878 struct pci_dev
*pdev
= to_pci_dev(device
);
4879 struct net_device
*dev
= pci_get_drvdata(pdev
);
4880 struct rtl8169_private
*tp
= netdev_priv(dev
);
4882 if (!tp
->TxDescArray
)
4885 spin_lock_irq(&tp
->lock
);
4886 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
4887 tp
->saved_wolopts
= 0;
4888 spin_unlock_irq(&tp
->lock
);
4890 rtl8169_init_phy(dev
, tp
);
4892 __rtl8169_resume(dev
);
4897 static int rtl8169_runtime_idle(struct device
*device
)
4899 struct pci_dev
*pdev
= to_pci_dev(device
);
4900 struct net_device
*dev
= pci_get_drvdata(pdev
);
4901 struct rtl8169_private
*tp
= netdev_priv(dev
);
4903 return tp
->TxDescArray
? -EBUSY
: 0;
4906 static const struct dev_pm_ops rtl8169_pm_ops
= {
4907 .suspend
= rtl8169_suspend
,
4908 .resume
= rtl8169_resume
,
4909 .freeze
= rtl8169_suspend
,
4910 .thaw
= rtl8169_resume
,
4911 .poweroff
= rtl8169_suspend
,
4912 .restore
= rtl8169_resume
,
4913 .runtime_suspend
= rtl8169_runtime_suspend
,
4914 .runtime_resume
= rtl8169_runtime_resume
,
4915 .runtime_idle
= rtl8169_runtime_idle
,
4918 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4920 #else /* !CONFIG_PM */
4922 #define RTL8169_PM_OPS NULL
4924 #endif /* !CONFIG_PM */
4926 static void rtl_shutdown(struct pci_dev
*pdev
)
4928 struct net_device
*dev
= pci_get_drvdata(pdev
);
4929 struct rtl8169_private
*tp
= netdev_priv(dev
);
4930 void __iomem
*ioaddr
= tp
->mmio_addr
;
4932 rtl8169_net_suspend(dev
);
4934 /* restore original MAC address */
4935 rtl_rar_set(tp
, dev
->perm_addr
);
4937 spin_lock_irq(&tp
->lock
);
4939 rtl8169_asic_down(ioaddr
);
4941 spin_unlock_irq(&tp
->lock
);
4943 if (system_state
== SYSTEM_POWER_OFF
) {
4944 /* WoL fails with some 8168 when the receiver is disabled. */
4945 if (tp
->features
& RTL_FEATURE_WOL
) {
4946 pci_clear_master(pdev
);
4948 RTL_W8(ChipCmd
, CmdRxEnb
);
4953 pci_wake_from_d3(pdev
, true);
4954 pci_set_power_state(pdev
, PCI_D3hot
);
4958 static struct pci_driver rtl8169_pci_driver
= {
4960 .id_table
= rtl8169_pci_tbl
,
4961 .probe
= rtl8169_init_one
,
4962 .remove
= __devexit_p(rtl8169_remove_one
),
4963 .shutdown
= rtl_shutdown
,
4964 .driver
.pm
= RTL8169_PM_OPS
,
4967 static int __init
rtl8169_init_module(void)
4969 return pci_register_driver(&rtl8169_pci_driver
);
4972 static void __exit
rtl8169_cleanup_module(void)
4974 pci_unregister_driver(&rtl8169_pci_driver
);
4977 module_init(rtl8169_init_module
);
4978 module_exit(rtl8169_cleanup_module
);