2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define assert(expr) \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
51 #expr,__FILE__,__func__,__LINE__); \
53 #define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
56 #define assert(expr) do {} while (0)
57 #define dprintk(fmt, args...) do {} while (0)
58 #endif /* RTL8169_DEBUG */
60 #define R8169_MSG_DEFAULT \
61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
63 #define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit
= 32;
70 /* MAC address length */
71 #define MAC_ADDR_LEN 6
73 #define MAX_READ_REQUEST_SHIFT 12
74 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
78 #define R8169_REGS_SIZE 256
79 #define R8169_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
86 #define RTL8169_TX_TIMEOUT (6*HZ)
87 #define RTL8169_PHY_TIMEOUT (10*HZ)
89 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
91 #define RTL_EEPROM_SIG_ADDR 0x0000
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) readl (ioaddr + (reg))
102 RTL_GIGA_MAC_VER_01
= 0,
136 RTL_GIGA_MAC_NONE
= 0xff,
139 enum rtl_tx_desc_version
{
144 #define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
147 static const struct {
149 enum rtl_tx_desc_version txd_version
;
151 } rtl_chip_infos
[] = {
153 [RTL_GIGA_MAC_VER_01
] =
154 _R("RTL8169", RTL_TD_0
, NULL
),
155 [RTL_GIGA_MAC_VER_02
] =
156 _R("RTL8169s", RTL_TD_0
, NULL
),
157 [RTL_GIGA_MAC_VER_03
] =
158 _R("RTL8110s", RTL_TD_0
, NULL
),
159 [RTL_GIGA_MAC_VER_04
] =
160 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
),
161 [RTL_GIGA_MAC_VER_05
] =
162 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
163 [RTL_GIGA_MAC_VER_06
] =
164 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
166 [RTL_GIGA_MAC_VER_07
] =
167 _R("RTL8102e", RTL_TD_1
, NULL
),
168 [RTL_GIGA_MAC_VER_08
] =
169 _R("RTL8102e", RTL_TD_1
, NULL
),
170 [RTL_GIGA_MAC_VER_09
] =
171 _R("RTL8102e", RTL_TD_1
, NULL
),
172 [RTL_GIGA_MAC_VER_10
] =
173 _R("RTL8101e", RTL_TD_0
, NULL
),
174 [RTL_GIGA_MAC_VER_11
] =
175 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
176 [RTL_GIGA_MAC_VER_12
] =
177 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
178 [RTL_GIGA_MAC_VER_13
] =
179 _R("RTL8101e", RTL_TD_0
, NULL
),
180 [RTL_GIGA_MAC_VER_14
] =
181 _R("RTL8100e", RTL_TD_0
, NULL
),
182 [RTL_GIGA_MAC_VER_15
] =
183 _R("RTL8100e", RTL_TD_0
, NULL
),
184 [RTL_GIGA_MAC_VER_16
] =
185 _R("RTL8101e", RTL_TD_0
, NULL
),
186 [RTL_GIGA_MAC_VER_17
] =
187 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
188 [RTL_GIGA_MAC_VER_18
] =
189 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
190 [RTL_GIGA_MAC_VER_19
] =
191 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
192 [RTL_GIGA_MAC_VER_20
] =
193 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
194 [RTL_GIGA_MAC_VER_21
] =
195 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
196 [RTL_GIGA_MAC_VER_22
] =
197 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
198 [RTL_GIGA_MAC_VER_23
] =
199 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
200 [RTL_GIGA_MAC_VER_24
] =
201 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
202 [RTL_GIGA_MAC_VER_25
] =
203 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
),
204 [RTL_GIGA_MAC_VER_26
] =
205 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
),
206 [RTL_GIGA_MAC_VER_27
] =
207 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
208 [RTL_GIGA_MAC_VER_28
] =
209 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
210 [RTL_GIGA_MAC_VER_29
] =
211 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
212 [RTL_GIGA_MAC_VER_30
] =
213 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
214 [RTL_GIGA_MAC_VER_31
] =
215 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
216 [RTL_GIGA_MAC_VER_32
] =
217 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
),
218 [RTL_GIGA_MAC_VER_33
] =
219 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
),
220 [RTL_GIGA_MAC_VER_34
] =
221 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
)
231 static void rtl_hw_start_8169(struct net_device
*);
232 static void rtl_hw_start_8168(struct net_device
*);
233 static void rtl_hw_start_8101(struct net_device
*);
235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
242 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
243 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
244 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
245 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
247 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
251 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
253 static int rx_buf_sz
= 16383;
260 MAC0
= 0, /* Ethernet hardware address. */
262 MAR0
= 8, /* Multicast filter. */
263 CounterAddrLow
= 0x10,
264 CounterAddrHigh
= 0x14,
265 TxDescStartAddrLow
= 0x20,
266 TxDescStartAddrHigh
= 0x24,
267 TxHDescStartAddrLow
= 0x28,
268 TxHDescStartAddrHigh
= 0x2c,
277 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
278 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
281 #define RX128_INT_EN (1 << 15) /* 8111c and later */
282 #define RX_MULTI_EN (1 << 14) /* 8111c only */
283 #define RXCFG_FIFO_SHIFT 13
284 /* No threshold before first PCI xfer */
285 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
286 #define RXCFG_DMA_SHIFT 8
287 /* Unlimited maximum PCI burst. */
288 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
304 RxDescAddrLow
= 0xe4,
305 RxDescAddrHigh
= 0xe8,
306 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
308 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
310 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
312 #define TxPacketMax (8064 >> 7)
315 FuncEventMask
= 0xf4,
316 FuncPresetState
= 0xf8,
317 FuncForceEvent
= 0xfc,
320 enum rtl8110_registers
{
326 enum rtl8168_8101_registers
{
329 #define CSIAR_FLAG 0x80000000
330 #define CSIAR_WRITE_CMD 0x80000000
331 #define CSIAR_BYTE_ENABLE 0x0f
332 #define CSIAR_BYTE_ENABLE_SHIFT 12
333 #define CSIAR_ADDR_MASK 0x0fff
336 #define EPHYAR_FLAG 0x80000000
337 #define EPHYAR_WRITE_CMD 0x80000000
338 #define EPHYAR_REG_MASK 0x1f
339 #define EPHYAR_REG_SHIFT 16
340 #define EPHYAR_DATA_MASK 0xffff
342 #define PFM_EN (1 << 6)
344 #define FIX_NAK_1 (1 << 4)
345 #define FIX_NAK_2 (1 << 3)
348 #define NOW_IS_OOB (1 << 7)
349 #define EN_NDP (1 << 3)
350 #define EN_OOB_RESET (1 << 2)
352 #define EFUSEAR_FLAG 0x80000000
353 #define EFUSEAR_WRITE_CMD 0x80000000
354 #define EFUSEAR_READ_CMD 0x00000000
355 #define EFUSEAR_REG_MASK 0x03ff
356 #define EFUSEAR_REG_SHIFT 8
357 #define EFUSEAR_DATA_MASK 0xff
360 enum rtl8168_registers
{
365 #define ERIAR_FLAG 0x80000000
366 #define ERIAR_WRITE_CMD 0x80000000
367 #define ERIAR_READ_CMD 0x00000000
368 #define ERIAR_ADDR_BYTE_ALIGN 4
369 #define ERIAR_TYPE_SHIFT 16
370 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
371 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_MASK_SHIFT 12
374 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
375 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
377 EPHY_RXER_NUM
= 0x7c,
378 OCPDR
= 0xb0, /* OCP GPHY access */
379 #define OCPDR_WRITE_CMD 0x80000000
380 #define OCPDR_READ_CMD 0x00000000
381 #define OCPDR_REG_MASK 0x7f
382 #define OCPDR_GPHY_REG_SHIFT 16
383 #define OCPDR_DATA_MASK 0xffff
385 #define OCPAR_FLAG 0x80000000
386 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
387 #define OCPAR_GPHY_READ_CMD 0x0000f060
388 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
389 MISC
= 0xf0, /* 8168e only. */
390 #define TXPLA_RST (1 << 29)
391 #define PWM_EN (1 << 22)
394 enum rtl_register_content
{
395 /* InterruptStatusBits */
399 TxDescUnavail
= 0x0080,
422 /* TXPoll register p.5 */
423 HPQ
= 0x80, /* Poll cmd on the high prio queue */
424 NPQ
= 0x40, /* Poll cmd on the low prio queue */
425 FSWInt
= 0x01, /* Forced software interrupt */
429 Cfg9346_Unlock
= 0xc0,
434 AcceptBroadcast
= 0x08,
435 AcceptMulticast
= 0x04,
437 AcceptAllPhys
= 0x01,
438 #define RX_CONFIG_ACCEPT_MASK 0x3f
441 TxInterFrameGapShift
= 24,
442 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
444 /* Config1 register p.24 */
447 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
448 Speed_down
= (1 << 4),
452 PMEnable
= (1 << 0), /* Power Management Enable */
454 /* Config2 register p. 25 */
455 PCI_Clock_66MHz
= 0x01,
456 PCI_Clock_33MHz
= 0x00,
458 /* Config3 register p.25 */
459 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
460 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
461 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
463 /* Config5 register p.27 */
464 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
465 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
466 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
468 LanWake
= (1 << 1), /* LanWake enable/disable */
469 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
472 TBIReset
= 0x80000000,
473 TBILoopback
= 0x40000000,
474 TBINwEnable
= 0x20000000,
475 TBINwRestart
= 0x10000000,
476 TBILinkOk
= 0x02000000,
477 TBINwComplete
= 0x01000000,
480 EnableBist
= (1 << 15), // 8168 8101
481 Mac_dbgo_oe
= (1 << 14), // 8168 8101
482 Normal_mode
= (1 << 13), // unused
483 Force_half_dup
= (1 << 12), // 8168 8101
484 Force_rxflow_en
= (1 << 11), // 8168 8101
485 Force_txflow_en
= (1 << 10), // 8168 8101
486 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
487 ASF
= (1 << 8), // 8168 8101
488 PktCntrDisable
= (1 << 7), // 8168 8101
489 Mac_dbgo_sel
= 0x001c, // 8168
494 INTT_0
= 0x0000, // 8168
495 INTT_1
= 0x0001, // 8168
496 INTT_2
= 0x0002, // 8168
497 INTT_3
= 0x0003, // 8168
499 /* rtl8169_PHYstatus */
510 TBILinkOK
= 0x02000000,
512 /* DumpCounterCommand */
517 /* First doubleword. */
518 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
519 RingEnd
= (1 << 30), /* End of descriptor ring */
520 FirstFrag
= (1 << 29), /* First segment of a packet */
521 LastFrag
= (1 << 28), /* Final segment of a packet */
525 enum rtl_tx_desc_bit
{
526 /* First doubleword. */
527 TD_LSO
= (1 << 27), /* Large Send Offload */
528 #define TD_MSS_MAX 0x07ffu /* MSS value */
530 /* Second doubleword. */
531 TxVlanTag
= (1 << 17), /* Add VLAN tag */
534 /* 8169, 8168b and 810x except 8102e. */
535 enum rtl_tx_desc_bit_0
{
536 /* First doubleword. */
537 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
538 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
539 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
540 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
543 /* 8102e, 8168c and beyond. */
544 enum rtl_tx_desc_bit_1
{
545 /* Second doubleword. */
546 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
547 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
548 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
549 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
552 static const struct rtl_tx_desc_info
{
559 } tx_desc_info
[] = {
562 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
563 .tcp
= TD0_IP_CS
| TD0_TCP_CS
565 .mss_shift
= TD0_MSS_SHIFT
,
570 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
571 .tcp
= TD1_IP_CS
| TD1_TCP_CS
573 .mss_shift
= TD1_MSS_SHIFT
,
578 enum rtl_rx_desc_bit
{
580 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
581 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
583 #define RxProtoUDP (PID1)
584 #define RxProtoTCP (PID0)
585 #define RxProtoIP (PID1 | PID0)
586 #define RxProtoMask RxProtoIP
588 IPFail
= (1 << 16), /* IP checksum failed */
589 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
590 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
591 RxVlanTag
= (1 << 16), /* VLAN tag available */
594 #define RsvdMask 0x3fffc000
611 u8 __pad
[sizeof(void *) - sizeof(u32
)];
615 RTL_FEATURE_WOL
= (1 << 0),
616 RTL_FEATURE_MSI
= (1 << 1),
617 RTL_FEATURE_GMII
= (1 << 2),
620 struct rtl8169_counters
{
627 __le32 tx_one_collision
;
628 __le32 tx_multi_collision
;
636 struct rtl8169_private
{
637 void __iomem
*mmio_addr
; /* memory map physical address */
638 struct pci_dev
*pci_dev
;
639 struct net_device
*dev
;
640 struct napi_struct napi
;
645 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
646 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
649 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
650 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
651 dma_addr_t TxPhyAddr
;
652 dma_addr_t RxPhyAddr
;
653 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
654 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
655 struct timer_list timer
;
662 void (*write
)(void __iomem
*, int, int);
663 int (*read
)(void __iomem
*, int);
666 struct pll_power_ops
{
667 void (*down
)(struct rtl8169_private
*);
668 void (*up
)(struct rtl8169_private
*);
671 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
672 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
673 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
674 void (*hw_start
)(struct net_device
*);
675 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
676 unsigned int (*link_ok
)(void __iomem
*);
677 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
678 struct delayed_work task
;
681 struct mii_if_info mii
;
682 struct rtl8169_counters counters
;
686 const struct firmware
*fw
;
688 #define RTL_VER_SIZE 32
690 char version
[RTL_VER_SIZE
];
692 struct rtl_fw_phy_action
{
697 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
700 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
701 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
702 module_param(use_dac
, int, 0);
703 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
704 module_param_named(debug
, debug
.msg_enable
, int, 0);
705 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
706 MODULE_LICENSE("GPL");
707 MODULE_VERSION(RTL8169_VERSION
);
708 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
709 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
710 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
711 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
712 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
714 static int rtl8169_open(struct net_device
*dev
);
715 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
716 struct net_device
*dev
);
717 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
718 static int rtl8169_init_ring(struct net_device
*dev
);
719 static void rtl_hw_start(struct net_device
*dev
);
720 static int rtl8169_close(struct net_device
*dev
);
721 static void rtl_set_rx_mode(struct net_device
*dev
);
722 static void rtl8169_tx_timeout(struct net_device
*dev
);
723 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
724 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
725 void __iomem
*, u32 budget
);
726 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
727 static void rtl8169_down(struct net_device
*dev
);
728 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
729 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
731 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
733 void __iomem
*ioaddr
= tp
->mmio_addr
;
736 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
737 for (i
= 0; i
< 20; i
++) {
739 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
742 return RTL_R32(OCPDR
);
745 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
747 void __iomem
*ioaddr
= tp
->mmio_addr
;
750 RTL_W32(OCPDR
, data
);
751 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
752 for (i
= 0; i
< 20; i
++) {
754 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
759 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
761 void __iomem
*ioaddr
= tp
->mmio_addr
;
765 RTL_W32(ERIAR
, 0x800010e8);
767 for (i
= 0; i
< 5; i
++) {
769 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
773 ocp_write(tp
, 0x1, 0x30, 0x00000001);
776 #define OOB_CMD_RESET 0x00
777 #define OOB_CMD_DRIVER_START 0x05
778 #define OOB_CMD_DRIVER_STOP 0x06
780 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
782 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
785 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
790 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
792 reg
= rtl8168_get_ocp_reg(tp
);
794 for (i
= 0; i
< 10; i
++) {
796 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
801 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
806 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
808 reg
= rtl8168_get_ocp_reg(tp
);
810 for (i
= 0; i
< 10; i
++) {
812 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
817 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
819 u16 reg
= rtl8168_get_ocp_reg(tp
);
821 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
824 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
828 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
830 for (i
= 20; i
> 0; i
--) {
832 * Check if the RTL8169 has completed writing to the specified
835 if (!(RTL_R32(PHYAR
) & 0x80000000))
840 * According to hardware specs a 20us delay is required after write
841 * complete indication, but before sending next command.
846 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
850 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
852 for (i
= 20; i
> 0; i
--) {
854 * Check if the RTL8169 has completed retrieving data from
855 * the specified MII register.
857 if (RTL_R32(PHYAR
) & 0x80000000) {
858 value
= RTL_R32(PHYAR
) & 0xffff;
864 * According to hardware specs a 20us delay is required after read
865 * complete indication, but before sending next command.
872 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
876 RTL_W32(OCPDR
, data
|
877 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
878 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
879 RTL_W32(EPHY_RXER_NUM
, 0);
881 for (i
= 0; i
< 100; i
++) {
883 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
888 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
890 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
891 (value
& OCPDR_DATA_MASK
));
894 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
898 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
901 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
902 RTL_W32(EPHY_RXER_NUM
, 0);
904 for (i
= 0; i
< 100; i
++) {
906 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
910 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
913 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
915 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
917 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
920 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
922 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
925 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
927 r8168dp_2_mdio_start(ioaddr
);
929 r8169_mdio_write(ioaddr
, reg_addr
, value
);
931 r8168dp_2_mdio_stop(ioaddr
);
934 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
938 r8168dp_2_mdio_start(ioaddr
);
940 value
= r8169_mdio_read(ioaddr
, reg_addr
);
942 r8168dp_2_mdio_stop(ioaddr
);
947 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
949 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
952 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
954 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
957 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
959 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
962 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
966 val
= rtl_readphy(tp
, reg_addr
);
967 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
970 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
973 struct rtl8169_private
*tp
= netdev_priv(dev
);
975 rtl_writephy(tp
, location
, val
);
978 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
980 struct rtl8169_private
*tp
= netdev_priv(dev
);
982 return rtl_readphy(tp
, location
);
985 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
989 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
990 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
992 for (i
= 0; i
< 100; i
++) {
993 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
999 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
1004 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1006 for (i
= 0; i
< 100; i
++) {
1007 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
1008 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1017 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
1021 RTL_W32(CSIDR
, value
);
1022 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
1023 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1025 for (i
= 0; i
< 100; i
++) {
1026 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1032 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1037 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1038 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1040 for (i
= 0; i
< 100; i
++) {
1041 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1042 value
= RTL_R32(CSIDR
);
1052 void rtl_eri_write(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 val
, int type
)
1056 BUG_ON((addr
& 3) || (mask
== 0));
1057 RTL_W32(ERIDR
, val
);
1058 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1060 for (i
= 0; i
< 100; i
++) {
1061 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
1067 static u32
rtl_eri_read(void __iomem
*ioaddr
, int addr
, int type
)
1072 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1074 for (i
= 0; i
< 100; i
++) {
1075 if (RTL_R32(ERIAR
) & ERIAR_FLAG
) {
1076 value
= RTL_R32(ERIDR
);
1086 rtl_w1w0_eri(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 p
, u32 m
, int type
)
1090 val
= rtl_eri_read(ioaddr
, addr
, type
);
1091 rtl_eri_write(ioaddr
, addr
, mask
, (val
& ~m
) | p
, type
);
1094 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1099 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1101 for (i
= 0; i
< 300; i
++) {
1102 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1103 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1112 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
1114 RTL_W16(IntrMask
, 0x0000);
1116 RTL_W16(IntrStatus
, 0xffff);
1119 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1121 void __iomem
*ioaddr
= tp
->mmio_addr
;
1123 return RTL_R32(TBICSR
) & TBIReset
;
1126 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1128 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1131 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1133 return RTL_R32(TBICSR
) & TBILinkOk
;
1136 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1138 return RTL_R8(PHYstatus
) & LinkStatus
;
1141 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1143 void __iomem
*ioaddr
= tp
->mmio_addr
;
1145 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1148 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1152 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1153 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1156 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1158 void __iomem
*ioaddr
= tp
->mmio_addr
;
1159 struct net_device
*dev
= tp
->dev
;
1161 if (!netif_running(dev
))
1164 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
1165 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1166 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1167 0x00000011, ERIAR_EXGMAC
);
1168 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1169 0x00000005, ERIAR_EXGMAC
);
1170 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1171 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1172 0x0000001f, ERIAR_EXGMAC
);
1173 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1174 0x00000005, ERIAR_EXGMAC
);
1176 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1177 0x0000001f, ERIAR_EXGMAC
);
1178 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1179 0x0000003f, ERIAR_EXGMAC
);
1181 /* Reset packet filter */
1182 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1184 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1189 static void __rtl8169_check_link_status(struct net_device
*dev
,
1190 struct rtl8169_private
*tp
,
1191 void __iomem
*ioaddr
, bool pm
)
1193 unsigned long flags
;
1195 spin_lock_irqsave(&tp
->lock
, flags
);
1196 if (tp
->link_ok(ioaddr
)) {
1197 rtl_link_chg_patch(tp
);
1198 /* This is to cancel a scheduled suspend if there's one. */
1200 pm_request_resume(&tp
->pci_dev
->dev
);
1201 netif_carrier_on(dev
);
1202 if (net_ratelimit())
1203 netif_info(tp
, ifup
, dev
, "link up\n");
1205 netif_carrier_off(dev
);
1206 netif_info(tp
, ifdown
, dev
, "link down\n");
1208 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
1210 spin_unlock_irqrestore(&tp
->lock
, flags
);
1213 static void rtl8169_check_link_status(struct net_device
*dev
,
1214 struct rtl8169_private
*tp
,
1215 void __iomem
*ioaddr
)
1217 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1220 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1222 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1224 void __iomem
*ioaddr
= tp
->mmio_addr
;
1228 options
= RTL_R8(Config1
);
1229 if (!(options
& PMEnable
))
1232 options
= RTL_R8(Config3
);
1233 if (options
& LinkUp
)
1234 wolopts
|= WAKE_PHY
;
1235 if (options
& MagicPacket
)
1236 wolopts
|= WAKE_MAGIC
;
1238 options
= RTL_R8(Config5
);
1240 wolopts
|= WAKE_UCAST
;
1242 wolopts
|= WAKE_BCAST
;
1244 wolopts
|= WAKE_MCAST
;
1249 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1251 struct rtl8169_private
*tp
= netdev_priv(dev
);
1253 spin_lock_irq(&tp
->lock
);
1255 wol
->supported
= WAKE_ANY
;
1256 wol
->wolopts
= __rtl8169_get_wol(tp
);
1258 spin_unlock_irq(&tp
->lock
);
1261 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1263 void __iomem
*ioaddr
= tp
->mmio_addr
;
1265 static const struct {
1270 { WAKE_ANY
, Config1
, PMEnable
},
1271 { WAKE_PHY
, Config3
, LinkUp
},
1272 { WAKE_MAGIC
, Config3
, MagicPacket
},
1273 { WAKE_UCAST
, Config5
, UWF
},
1274 { WAKE_BCAST
, Config5
, BWF
},
1275 { WAKE_MCAST
, Config5
, MWF
},
1276 { WAKE_ANY
, Config5
, LanWake
}
1279 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1281 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1282 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1283 if (wolopts
& cfg
[i
].opt
)
1284 options
|= cfg
[i
].mask
;
1285 RTL_W8(cfg
[i
].reg
, options
);
1288 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1291 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1293 struct rtl8169_private
*tp
= netdev_priv(dev
);
1295 spin_lock_irq(&tp
->lock
);
1298 tp
->features
|= RTL_FEATURE_WOL
;
1300 tp
->features
&= ~RTL_FEATURE_WOL
;
1301 __rtl8169_set_wol(tp
, wol
->wolopts
);
1302 spin_unlock_irq(&tp
->lock
);
1304 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1309 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1311 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1314 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1315 struct ethtool_drvinfo
*info
)
1317 struct rtl8169_private
*tp
= netdev_priv(dev
);
1318 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1320 strcpy(info
->driver
, MODULENAME
);
1321 strcpy(info
->version
, RTL8169_VERSION
);
1322 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1323 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1324 strcpy(info
->fw_version
, IS_ERR_OR_NULL(rtl_fw
) ? "N/A" :
1328 static int rtl8169_get_regs_len(struct net_device
*dev
)
1330 return R8169_REGS_SIZE
;
1333 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1334 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1336 struct rtl8169_private
*tp
= netdev_priv(dev
);
1337 void __iomem
*ioaddr
= tp
->mmio_addr
;
1341 reg
= RTL_R32(TBICSR
);
1342 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1343 (duplex
== DUPLEX_FULL
)) {
1344 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1345 } else if (autoneg
== AUTONEG_ENABLE
)
1346 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1348 netif_warn(tp
, link
, dev
,
1349 "incorrect speed setting refused in TBI mode\n");
1356 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1357 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1359 struct rtl8169_private
*tp
= netdev_priv(dev
);
1360 int giga_ctrl
, bmcr
;
1363 rtl_writephy(tp
, 0x1f, 0x0000);
1365 if (autoneg
== AUTONEG_ENABLE
) {
1368 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1369 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1370 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1372 if (adv
& ADVERTISED_10baseT_Half
)
1373 auto_nego
|= ADVERTISE_10HALF
;
1374 if (adv
& ADVERTISED_10baseT_Full
)
1375 auto_nego
|= ADVERTISE_10FULL
;
1376 if (adv
& ADVERTISED_100baseT_Half
)
1377 auto_nego
|= ADVERTISE_100HALF
;
1378 if (adv
& ADVERTISED_100baseT_Full
)
1379 auto_nego
|= ADVERTISE_100FULL
;
1381 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1383 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1384 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1386 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1387 if (tp
->mii
.supports_gmii
) {
1388 if (adv
& ADVERTISED_1000baseT_Half
)
1389 giga_ctrl
|= ADVERTISE_1000HALF
;
1390 if (adv
& ADVERTISED_1000baseT_Full
)
1391 giga_ctrl
|= ADVERTISE_1000FULL
;
1392 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1393 ADVERTISED_1000baseT_Full
)) {
1394 netif_info(tp
, link
, dev
,
1395 "PHY does not support 1000Mbps\n");
1399 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1401 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1402 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1406 if (speed
== SPEED_10
)
1408 else if (speed
== SPEED_100
)
1409 bmcr
= BMCR_SPEED100
;
1413 if (duplex
== DUPLEX_FULL
)
1414 bmcr
|= BMCR_FULLDPLX
;
1417 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1419 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1420 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1421 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1422 rtl_writephy(tp
, 0x17, 0x2138);
1423 rtl_writephy(tp
, 0x0e, 0x0260);
1425 rtl_writephy(tp
, 0x17, 0x2108);
1426 rtl_writephy(tp
, 0x0e, 0x0000);
1435 static int rtl8169_set_speed(struct net_device
*dev
,
1436 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1438 struct rtl8169_private
*tp
= netdev_priv(dev
);
1441 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1445 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1446 (advertising
& ADVERTISED_1000baseT_Full
)) {
1447 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1453 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1455 struct rtl8169_private
*tp
= netdev_priv(dev
);
1456 unsigned long flags
;
1459 del_timer_sync(&tp
->timer
);
1461 spin_lock_irqsave(&tp
->lock
, flags
);
1462 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1463 cmd
->duplex
, cmd
->advertising
);
1464 spin_unlock_irqrestore(&tp
->lock
, flags
);
1469 static u32
rtl8169_fix_features(struct net_device
*dev
, u32 features
)
1471 if (dev
->mtu
> TD_MSS_MAX
)
1472 features
&= ~NETIF_F_ALL_TSO
;
1477 static int rtl8169_set_features(struct net_device
*dev
, u32 features
)
1479 struct rtl8169_private
*tp
= netdev_priv(dev
);
1480 void __iomem
*ioaddr
= tp
->mmio_addr
;
1481 unsigned long flags
;
1483 spin_lock_irqsave(&tp
->lock
, flags
);
1485 if (features
& NETIF_F_RXCSUM
)
1486 tp
->cp_cmd
|= RxChkSum
;
1488 tp
->cp_cmd
&= ~RxChkSum
;
1490 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1491 tp
->cp_cmd
|= RxVlan
;
1493 tp
->cp_cmd
&= ~RxVlan
;
1495 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1498 spin_unlock_irqrestore(&tp
->lock
, flags
);
1503 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1504 struct sk_buff
*skb
)
1506 return (vlan_tx_tag_present(skb
)) ?
1507 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1510 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1512 u32 opts2
= le32_to_cpu(desc
->opts2
);
1514 if (opts2
& RxVlanTag
)
1515 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1520 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1522 struct rtl8169_private
*tp
= netdev_priv(dev
);
1523 void __iomem
*ioaddr
= tp
->mmio_addr
;
1527 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1528 cmd
->port
= PORT_FIBRE
;
1529 cmd
->transceiver
= XCVR_INTERNAL
;
1531 status
= RTL_R32(TBICSR
);
1532 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1533 cmd
->autoneg
= !!(status
& TBINwEnable
);
1535 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1536 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1541 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1543 struct rtl8169_private
*tp
= netdev_priv(dev
);
1545 return mii_ethtool_gset(&tp
->mii
, cmd
);
1548 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1550 struct rtl8169_private
*tp
= netdev_priv(dev
);
1551 unsigned long flags
;
1554 spin_lock_irqsave(&tp
->lock
, flags
);
1556 rc
= tp
->get_settings(dev
, cmd
);
1558 spin_unlock_irqrestore(&tp
->lock
, flags
);
1562 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1565 struct rtl8169_private
*tp
= netdev_priv(dev
);
1566 unsigned long flags
;
1568 if (regs
->len
> R8169_REGS_SIZE
)
1569 regs
->len
= R8169_REGS_SIZE
;
1571 spin_lock_irqsave(&tp
->lock
, flags
);
1572 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1573 spin_unlock_irqrestore(&tp
->lock
, flags
);
1576 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1578 struct rtl8169_private
*tp
= netdev_priv(dev
);
1580 return tp
->msg_enable
;
1583 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1585 struct rtl8169_private
*tp
= netdev_priv(dev
);
1587 tp
->msg_enable
= value
;
1590 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1597 "tx_single_collisions",
1598 "tx_multi_collisions",
1606 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1610 return ARRAY_SIZE(rtl8169_gstrings
);
1616 static void rtl8169_update_counters(struct net_device
*dev
)
1618 struct rtl8169_private
*tp
= netdev_priv(dev
);
1619 void __iomem
*ioaddr
= tp
->mmio_addr
;
1620 struct device
*d
= &tp
->pci_dev
->dev
;
1621 struct rtl8169_counters
*counters
;
1627 * Some chips are unable to dump tally counters when the receiver
1630 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1633 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1637 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1638 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1639 RTL_W32(CounterAddrLow
, cmd
);
1640 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1643 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1644 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1650 RTL_W32(CounterAddrLow
, 0);
1651 RTL_W32(CounterAddrHigh
, 0);
1653 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1656 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1657 struct ethtool_stats
*stats
, u64
*data
)
1659 struct rtl8169_private
*tp
= netdev_priv(dev
);
1663 rtl8169_update_counters(dev
);
1665 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1666 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1667 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1668 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1669 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1670 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1671 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1672 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1673 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1674 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1675 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1676 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1677 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1680 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1684 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1689 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1690 .get_drvinfo
= rtl8169_get_drvinfo
,
1691 .get_regs_len
= rtl8169_get_regs_len
,
1692 .get_link
= ethtool_op_get_link
,
1693 .get_settings
= rtl8169_get_settings
,
1694 .set_settings
= rtl8169_set_settings
,
1695 .get_msglevel
= rtl8169_get_msglevel
,
1696 .set_msglevel
= rtl8169_set_msglevel
,
1697 .get_regs
= rtl8169_get_regs
,
1698 .get_wol
= rtl8169_get_wol
,
1699 .set_wol
= rtl8169_set_wol
,
1700 .get_strings
= rtl8169_get_strings
,
1701 .get_sset_count
= rtl8169_get_sset_count
,
1702 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1705 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1706 struct net_device
*dev
, u8 default_version
)
1708 void __iomem
*ioaddr
= tp
->mmio_addr
;
1710 * The driver currently handles the 8168Bf and the 8168Be identically
1711 * but they can be identified more specifically through the test below
1714 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1716 * Same thing for the 8101Eb and the 8101Ec:
1718 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1720 static const struct rtl_mac_info
{
1726 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
1727 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1728 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1729 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1732 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1733 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1734 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1736 /* 8168DP family. */
1737 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1738 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1739 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1742 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1743 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1744 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1745 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1746 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1747 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1748 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1749 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1750 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1753 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1754 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1755 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1756 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1759 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1760 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1761 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1762 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1763 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1764 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1765 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1766 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1767 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1768 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1769 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1770 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1771 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1772 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1773 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1774 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1775 /* FIXME: where did these entries come from ? -- FR */
1776 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1777 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1780 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1781 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1782 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1783 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1784 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1785 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1788 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1790 const struct rtl_mac_info
*p
= mac_info
;
1793 reg
= RTL_R32(TxConfig
);
1794 while ((reg
& p
->mask
) != p
->val
)
1796 tp
->mac_version
= p
->mac_version
;
1798 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1799 netif_notice(tp
, probe
, dev
,
1800 "unknown MAC, using family default\n");
1801 tp
->mac_version
= default_version
;
1805 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1807 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1815 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1816 const struct phy_reg
*regs
, int len
)
1819 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1824 #define PHY_READ 0x00000000
1825 #define PHY_DATA_OR 0x10000000
1826 #define PHY_DATA_AND 0x20000000
1827 #define PHY_BJMPN 0x30000000
1828 #define PHY_READ_EFUSE 0x40000000
1829 #define PHY_READ_MAC_BYTE 0x50000000
1830 #define PHY_WRITE_MAC_BYTE 0x60000000
1831 #define PHY_CLEAR_READCOUNT 0x70000000
1832 #define PHY_WRITE 0x80000000
1833 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1834 #define PHY_COMP_EQ_SKIPN 0xa0000000
1835 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1836 #define PHY_WRITE_PREVIOUS 0xc0000000
1837 #define PHY_SKIPN 0xd0000000
1838 #define PHY_DELAY_MS 0xe0000000
1839 #define PHY_WRITE_ERI_WORD 0xf0000000
1843 char version
[RTL_VER_SIZE
];
1849 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1851 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1853 const struct firmware
*fw
= rtl_fw
->fw
;
1854 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
1855 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1856 char *version
= rtl_fw
->version
;
1859 if (fw
->size
< FW_OPCODE_SIZE
)
1862 if (!fw_info
->magic
) {
1863 size_t i
, size
, start
;
1866 if (fw
->size
< sizeof(*fw_info
))
1869 for (i
= 0; i
< fw
->size
; i
++)
1870 checksum
+= fw
->data
[i
];
1874 start
= le32_to_cpu(fw_info
->fw_start
);
1875 if (start
> fw
->size
)
1878 size
= le32_to_cpu(fw_info
->fw_len
);
1879 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
1882 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
1884 pa
->code
= (__le32
*)(fw
->data
+ start
);
1887 if (fw
->size
% FW_OPCODE_SIZE
)
1890 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
1892 pa
->code
= (__le32
*)fw
->data
;
1893 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
1895 version
[RTL_VER_SIZE
- 1] = 0;
1902 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
1903 struct rtl_fw_phy_action
*pa
)
1908 for (index
= 0; index
< pa
->size
; index
++) {
1909 u32 action
= le32_to_cpu(pa
->code
[index
]);
1910 u32 regno
= (action
& 0x0fff0000) >> 16;
1912 switch(action
& 0xf0000000) {
1916 case PHY_READ_EFUSE
:
1917 case PHY_CLEAR_READCOUNT
:
1919 case PHY_WRITE_PREVIOUS
:
1924 if (regno
> index
) {
1925 netif_err(tp
, ifup
, tp
->dev
,
1926 "Out of range of firmware\n");
1930 case PHY_READCOUNT_EQ_SKIP
:
1931 if (index
+ 2 >= pa
->size
) {
1932 netif_err(tp
, ifup
, tp
->dev
,
1933 "Out of range of firmware\n");
1937 case PHY_COMP_EQ_SKIPN
:
1938 case PHY_COMP_NEQ_SKIPN
:
1940 if (index
+ 1 + regno
>= pa
->size
) {
1941 netif_err(tp
, ifup
, tp
->dev
,
1942 "Out of range of firmware\n");
1947 case PHY_READ_MAC_BYTE
:
1948 case PHY_WRITE_MAC_BYTE
:
1949 case PHY_WRITE_ERI_WORD
:
1951 netif_err(tp
, ifup
, tp
->dev
,
1952 "Invalid action 0x%08x\n", action
);
1961 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1963 struct net_device
*dev
= tp
->dev
;
1966 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
1967 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
1971 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
1977 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1979 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1983 predata
= count
= 0;
1985 for (index
= 0; index
< pa
->size
; ) {
1986 u32 action
= le32_to_cpu(pa
->code
[index
]);
1987 u32 data
= action
& 0x0000ffff;
1988 u32 regno
= (action
& 0x0fff0000) >> 16;
1993 switch(action
& 0xf0000000) {
1995 predata
= rtl_readphy(tp
, regno
);
2010 case PHY_READ_EFUSE
:
2011 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
2014 case PHY_CLEAR_READCOUNT
:
2019 rtl_writephy(tp
, regno
, data
);
2022 case PHY_READCOUNT_EQ_SKIP
:
2023 index
+= (count
== data
) ? 2 : 1;
2025 case PHY_COMP_EQ_SKIPN
:
2026 if (predata
== data
)
2030 case PHY_COMP_NEQ_SKIPN
:
2031 if (predata
!= data
)
2035 case PHY_WRITE_PREVIOUS
:
2036 rtl_writephy(tp
, regno
, predata
);
2047 case PHY_READ_MAC_BYTE
:
2048 case PHY_WRITE_MAC_BYTE
:
2049 case PHY_WRITE_ERI_WORD
:
2056 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2058 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2059 release_firmware(tp
->rtl_fw
->fw
);
2062 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2065 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2067 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2069 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2070 if (!IS_ERR_OR_NULL(rtl_fw
))
2071 rtl_phy_write_fw(tp
, rtl_fw
);
2074 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2076 if (rtl_readphy(tp
, reg
) != val
)
2077 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2079 rtl_apply_firmware(tp
);
2082 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2084 static const struct phy_reg phy_reg_init
[] = {
2146 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2149 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2151 static const struct phy_reg phy_reg_init
[] = {
2157 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2160 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2162 struct pci_dev
*pdev
= tp
->pci_dev
;
2164 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2165 (pdev
->subsystem_device
!= 0xe000))
2168 rtl_writephy(tp
, 0x1f, 0x0001);
2169 rtl_writephy(tp
, 0x10, 0xf01b);
2170 rtl_writephy(tp
, 0x1f, 0x0000);
2173 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2175 static const struct phy_reg phy_reg_init
[] = {
2215 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2217 rtl8169scd_hw_phy_config_quirk(tp
);
2220 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2222 static const struct phy_reg phy_reg_init
[] = {
2270 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2273 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2275 static const struct phy_reg phy_reg_init
[] = {
2280 rtl_writephy(tp
, 0x1f, 0x0001);
2281 rtl_patchphy(tp
, 0x16, 1 << 0);
2283 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2286 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2288 static const struct phy_reg phy_reg_init
[] = {
2294 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2297 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2299 static const struct phy_reg phy_reg_init
[] = {
2307 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2310 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2312 static const struct phy_reg phy_reg_init
[] = {
2318 rtl_writephy(tp
, 0x1f, 0x0000);
2319 rtl_patchphy(tp
, 0x14, 1 << 5);
2320 rtl_patchphy(tp
, 0x0d, 1 << 5);
2322 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2325 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2327 static const struct phy_reg phy_reg_init
[] = {
2347 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2349 rtl_patchphy(tp
, 0x14, 1 << 5);
2350 rtl_patchphy(tp
, 0x0d, 1 << 5);
2351 rtl_writephy(tp
, 0x1f, 0x0000);
2354 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2356 static const struct phy_reg phy_reg_init
[] = {
2374 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2376 rtl_patchphy(tp
, 0x16, 1 << 0);
2377 rtl_patchphy(tp
, 0x14, 1 << 5);
2378 rtl_patchphy(tp
, 0x0d, 1 << 5);
2379 rtl_writephy(tp
, 0x1f, 0x0000);
2382 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2384 static const struct phy_reg phy_reg_init
[] = {
2396 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2398 rtl_patchphy(tp
, 0x16, 1 << 0);
2399 rtl_patchphy(tp
, 0x14, 1 << 5);
2400 rtl_patchphy(tp
, 0x0d, 1 << 5);
2401 rtl_writephy(tp
, 0x1f, 0x0000);
2404 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2406 rtl8168c_3_hw_phy_config(tp
);
2409 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2411 static const struct phy_reg phy_reg_init_0
[] = {
2412 /* Channel Estimation */
2433 * Enhance line driver power
2442 * Can not link to 1Gbps with bad cable
2443 * Decrease SNR threshold form 21.07dB to 19.04dB
2451 void __iomem
*ioaddr
= tp
->mmio_addr
;
2453 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2457 * Fine Tune Switching regulator parameter
2459 rtl_writephy(tp
, 0x1f, 0x0002);
2460 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2461 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2463 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2464 static const struct phy_reg phy_reg_init
[] = {
2474 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2476 val
= rtl_readphy(tp
, 0x0d);
2478 if ((val
& 0x00ff) != 0x006c) {
2479 static const u32 set
[] = {
2480 0x0065, 0x0066, 0x0067, 0x0068,
2481 0x0069, 0x006a, 0x006b, 0x006c
2485 rtl_writephy(tp
, 0x1f, 0x0002);
2488 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2489 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2492 static const struct phy_reg phy_reg_init
[] = {
2500 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2503 /* RSET couple improve */
2504 rtl_writephy(tp
, 0x1f, 0x0002);
2505 rtl_patchphy(tp
, 0x0d, 0x0300);
2506 rtl_patchphy(tp
, 0x0f, 0x0010);
2508 /* Fine tune PLL performance */
2509 rtl_writephy(tp
, 0x1f, 0x0002);
2510 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2511 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2513 rtl_writephy(tp
, 0x1f, 0x0005);
2514 rtl_writephy(tp
, 0x05, 0x001b);
2516 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2518 rtl_writephy(tp
, 0x1f, 0x0000);
2521 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2523 static const struct phy_reg phy_reg_init_0
[] = {
2524 /* Channel Estimation */
2545 * Enhance line driver power
2554 * Can not link to 1Gbps with bad cable
2555 * Decrease SNR threshold form 21.07dB to 19.04dB
2563 void __iomem
*ioaddr
= tp
->mmio_addr
;
2565 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2567 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2568 static const struct phy_reg phy_reg_init
[] = {
2579 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2581 val
= rtl_readphy(tp
, 0x0d);
2582 if ((val
& 0x00ff) != 0x006c) {
2583 static const u32 set
[] = {
2584 0x0065, 0x0066, 0x0067, 0x0068,
2585 0x0069, 0x006a, 0x006b, 0x006c
2589 rtl_writephy(tp
, 0x1f, 0x0002);
2592 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2593 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2596 static const struct phy_reg phy_reg_init
[] = {
2604 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2607 /* Fine tune PLL performance */
2608 rtl_writephy(tp
, 0x1f, 0x0002);
2609 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2610 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2612 /* Switching regulator Slew rate */
2613 rtl_writephy(tp
, 0x1f, 0x0002);
2614 rtl_patchphy(tp
, 0x0f, 0x0017);
2616 rtl_writephy(tp
, 0x1f, 0x0005);
2617 rtl_writephy(tp
, 0x05, 0x001b);
2619 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2621 rtl_writephy(tp
, 0x1f, 0x0000);
2624 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2626 static const struct phy_reg phy_reg_init
[] = {
2682 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2685 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2687 static const struct phy_reg phy_reg_init
[] = {
2697 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2698 rtl_patchphy(tp
, 0x0d, 1 << 5);
2701 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2703 static const struct phy_reg phy_reg_init
[] = {
2704 /* Enable Delay cap */
2710 /* Channel estimation fine tune */
2719 /* Update PFM & 10M TX idle timer */
2731 rtl_apply_firmware(tp
);
2733 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2735 /* DCO enable for 10M IDLE Power */
2736 rtl_writephy(tp
, 0x1f, 0x0007);
2737 rtl_writephy(tp
, 0x1e, 0x0023);
2738 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2739 rtl_writephy(tp
, 0x1f, 0x0000);
2741 /* For impedance matching */
2742 rtl_writephy(tp
, 0x1f, 0x0002);
2743 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2744 rtl_writephy(tp
, 0x1f, 0x0000);
2746 /* PHY auto speed down */
2747 rtl_writephy(tp
, 0x1f, 0x0007);
2748 rtl_writephy(tp
, 0x1e, 0x002d);
2749 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2750 rtl_writephy(tp
, 0x1f, 0x0000);
2751 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2753 rtl_writephy(tp
, 0x1f, 0x0005);
2754 rtl_writephy(tp
, 0x05, 0x8b86);
2755 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2756 rtl_writephy(tp
, 0x1f, 0x0000);
2758 rtl_writephy(tp
, 0x1f, 0x0005);
2759 rtl_writephy(tp
, 0x05, 0x8b85);
2760 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2761 rtl_writephy(tp
, 0x1f, 0x0007);
2762 rtl_writephy(tp
, 0x1e, 0x0020);
2763 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2764 rtl_writephy(tp
, 0x1f, 0x0006);
2765 rtl_writephy(tp
, 0x00, 0x5a00);
2766 rtl_writephy(tp
, 0x1f, 0x0000);
2767 rtl_writephy(tp
, 0x0d, 0x0007);
2768 rtl_writephy(tp
, 0x0e, 0x003c);
2769 rtl_writephy(tp
, 0x0d, 0x4007);
2770 rtl_writephy(tp
, 0x0e, 0x0000);
2771 rtl_writephy(tp
, 0x0d, 0x0000);
2774 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2776 static const struct phy_reg phy_reg_init
[] = {
2777 /* Enable Delay cap */
2786 /* Channel estimation fine tune */
2803 rtl_apply_firmware(tp
);
2805 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2807 /* For 4-corner performance improve */
2808 rtl_writephy(tp
, 0x1f, 0x0005);
2809 rtl_writephy(tp
, 0x05, 0x8b80);
2810 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2811 rtl_writephy(tp
, 0x1f, 0x0000);
2813 /* PHY auto speed down */
2814 rtl_writephy(tp
, 0x1f, 0x0004);
2815 rtl_writephy(tp
, 0x1f, 0x0007);
2816 rtl_writephy(tp
, 0x1e, 0x002d);
2817 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2818 rtl_writephy(tp
, 0x1f, 0x0002);
2819 rtl_writephy(tp
, 0x1f, 0x0000);
2820 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2822 /* improve 10M EEE waveform */
2823 rtl_writephy(tp
, 0x1f, 0x0005);
2824 rtl_writephy(tp
, 0x05, 0x8b86);
2825 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2826 rtl_writephy(tp
, 0x1f, 0x0000);
2828 /* Improve 2-pair detection performance */
2829 rtl_writephy(tp
, 0x1f, 0x0005);
2830 rtl_writephy(tp
, 0x05, 0x8b85);
2831 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2832 rtl_writephy(tp
, 0x1f, 0x0000);
2835 rtl_w1w0_eri(tp
->mmio_addr
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003,
2837 rtl_writephy(tp
, 0x1f, 0x0005);
2838 rtl_writephy(tp
, 0x05, 0x8b85);
2839 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2840 rtl_writephy(tp
, 0x1f, 0x0004);
2841 rtl_writephy(tp
, 0x1f, 0x0007);
2842 rtl_writephy(tp
, 0x1e, 0x0020);
2843 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0100);
2844 rtl_writephy(tp
, 0x1f, 0x0002);
2845 rtl_writephy(tp
, 0x1f, 0x0000);
2846 rtl_writephy(tp
, 0x0d, 0x0007);
2847 rtl_writephy(tp
, 0x0e, 0x003c);
2848 rtl_writephy(tp
, 0x0d, 0x4007);
2849 rtl_writephy(tp
, 0x0e, 0x0000);
2850 rtl_writephy(tp
, 0x0d, 0x0000);
2853 rtl_writephy(tp
, 0x1f, 0x0003);
2854 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
2855 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
2856 rtl_writephy(tp
, 0x1f, 0x0000);
2859 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
2861 static const struct phy_reg phy_reg_init
[] = {
2868 rtl_writephy(tp
, 0x1f, 0x0000);
2869 rtl_patchphy(tp
, 0x11, 1 << 12);
2870 rtl_patchphy(tp
, 0x19, 1 << 13);
2871 rtl_patchphy(tp
, 0x10, 1 << 15);
2873 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2876 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
2878 static const struct phy_reg phy_reg_init
[] = {
2892 /* Disable ALDPS before ram code */
2893 rtl_writephy(tp
, 0x1f, 0x0000);
2894 rtl_writephy(tp
, 0x18, 0x0310);
2897 rtl_apply_firmware(tp
);
2899 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2902 static void rtl_hw_phy_config(struct net_device
*dev
)
2904 struct rtl8169_private
*tp
= netdev_priv(dev
);
2906 rtl8169_print_mac_version(tp
);
2908 switch (tp
->mac_version
) {
2909 case RTL_GIGA_MAC_VER_01
:
2911 case RTL_GIGA_MAC_VER_02
:
2912 case RTL_GIGA_MAC_VER_03
:
2913 rtl8169s_hw_phy_config(tp
);
2915 case RTL_GIGA_MAC_VER_04
:
2916 rtl8169sb_hw_phy_config(tp
);
2918 case RTL_GIGA_MAC_VER_05
:
2919 rtl8169scd_hw_phy_config(tp
);
2921 case RTL_GIGA_MAC_VER_06
:
2922 rtl8169sce_hw_phy_config(tp
);
2924 case RTL_GIGA_MAC_VER_07
:
2925 case RTL_GIGA_MAC_VER_08
:
2926 case RTL_GIGA_MAC_VER_09
:
2927 rtl8102e_hw_phy_config(tp
);
2929 case RTL_GIGA_MAC_VER_11
:
2930 rtl8168bb_hw_phy_config(tp
);
2932 case RTL_GIGA_MAC_VER_12
:
2933 rtl8168bef_hw_phy_config(tp
);
2935 case RTL_GIGA_MAC_VER_17
:
2936 rtl8168bef_hw_phy_config(tp
);
2938 case RTL_GIGA_MAC_VER_18
:
2939 rtl8168cp_1_hw_phy_config(tp
);
2941 case RTL_GIGA_MAC_VER_19
:
2942 rtl8168c_1_hw_phy_config(tp
);
2944 case RTL_GIGA_MAC_VER_20
:
2945 rtl8168c_2_hw_phy_config(tp
);
2947 case RTL_GIGA_MAC_VER_21
:
2948 rtl8168c_3_hw_phy_config(tp
);
2950 case RTL_GIGA_MAC_VER_22
:
2951 rtl8168c_4_hw_phy_config(tp
);
2953 case RTL_GIGA_MAC_VER_23
:
2954 case RTL_GIGA_MAC_VER_24
:
2955 rtl8168cp_2_hw_phy_config(tp
);
2957 case RTL_GIGA_MAC_VER_25
:
2958 rtl8168d_1_hw_phy_config(tp
);
2960 case RTL_GIGA_MAC_VER_26
:
2961 rtl8168d_2_hw_phy_config(tp
);
2963 case RTL_GIGA_MAC_VER_27
:
2964 rtl8168d_3_hw_phy_config(tp
);
2966 case RTL_GIGA_MAC_VER_28
:
2967 rtl8168d_4_hw_phy_config(tp
);
2969 case RTL_GIGA_MAC_VER_29
:
2970 case RTL_GIGA_MAC_VER_30
:
2971 rtl8105e_hw_phy_config(tp
);
2973 case RTL_GIGA_MAC_VER_31
:
2976 case RTL_GIGA_MAC_VER_32
:
2977 case RTL_GIGA_MAC_VER_33
:
2978 rtl8168e_1_hw_phy_config(tp
);
2980 case RTL_GIGA_MAC_VER_34
:
2981 rtl8168e_2_hw_phy_config(tp
);
2989 static void rtl8169_phy_timer(unsigned long __opaque
)
2991 struct net_device
*dev
= (struct net_device
*)__opaque
;
2992 struct rtl8169_private
*tp
= netdev_priv(dev
);
2993 struct timer_list
*timer
= &tp
->timer
;
2994 void __iomem
*ioaddr
= tp
->mmio_addr
;
2995 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2997 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2999 spin_lock_irq(&tp
->lock
);
3001 if (tp
->phy_reset_pending(tp
)) {
3003 * A busy loop could burn quite a few cycles on nowadays CPU.
3004 * Let's delay the execution of the timer for a few ticks.
3010 if (tp
->link_ok(ioaddr
))
3013 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
3015 tp
->phy_reset_enable(tp
);
3018 mod_timer(timer
, jiffies
+ timeout
);
3020 spin_unlock_irq(&tp
->lock
);
3023 #ifdef CONFIG_NET_POLL_CONTROLLER
3025 * Polling 'interrupt' - used by things like netconsole to send skbs
3026 * without having to re-enable interrupts. It's not called while
3027 * the interrupt routine is executing.
3029 static void rtl8169_netpoll(struct net_device
*dev
)
3031 struct rtl8169_private
*tp
= netdev_priv(dev
);
3032 struct pci_dev
*pdev
= tp
->pci_dev
;
3034 disable_irq(pdev
->irq
);
3035 rtl8169_interrupt(pdev
->irq
, dev
);
3036 enable_irq(pdev
->irq
);
3040 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3041 void __iomem
*ioaddr
)
3044 pci_release_regions(pdev
);
3045 pci_clear_mwi(pdev
);
3046 pci_disable_device(pdev
);
3050 static void rtl8169_phy_reset(struct net_device
*dev
,
3051 struct rtl8169_private
*tp
)
3055 tp
->phy_reset_enable(tp
);
3056 for (i
= 0; i
< 100; i
++) {
3057 if (!tp
->phy_reset_pending(tp
))
3061 netif_err(tp
, link
, dev
, "PHY reset failed\n");
3064 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3066 void __iomem
*ioaddr
= tp
->mmio_addr
;
3068 rtl_hw_phy_config(dev
);
3070 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3071 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3075 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3077 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3078 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3080 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3081 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3083 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3084 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3087 rtl8169_phy_reset(dev
, tp
);
3089 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3090 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3091 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3092 (tp
->mii
.supports_gmii
?
3093 ADVERTISED_1000baseT_Half
|
3094 ADVERTISED_1000baseT_Full
: 0));
3096 if (RTL_R8(PHYstatus
) & TBI_Enable
)
3097 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3100 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3102 void __iomem
*ioaddr
= tp
->mmio_addr
;
3106 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
3107 high
= addr
[4] | (addr
[5] << 8);
3109 spin_lock_irq(&tp
->lock
);
3111 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3113 RTL_W32(MAC4
, high
);
3119 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3121 spin_unlock_irq(&tp
->lock
);
3124 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3126 struct rtl8169_private
*tp
= netdev_priv(dev
);
3127 struct sockaddr
*addr
= p
;
3129 if (!is_valid_ether_addr(addr
->sa_data
))
3130 return -EADDRNOTAVAIL
;
3132 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3134 rtl_rar_set(tp
, dev
->dev_addr
);
3139 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3141 struct rtl8169_private
*tp
= netdev_priv(dev
);
3142 struct mii_ioctl_data
*data
= if_mii(ifr
);
3144 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3147 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3148 struct mii_ioctl_data
*data
, int cmd
)
3152 data
->phy_id
= 32; /* Internal PHY */
3156 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3160 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3166 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3171 static const struct rtl_cfg_info
{
3172 void (*hw_start
)(struct net_device
*);
3173 unsigned int region
;
3179 } rtl_cfg_infos
[] = {
3181 .hw_start
= rtl_hw_start_8169
,
3184 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3185 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3186 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3187 .features
= RTL_FEATURE_GMII
,
3188 .default_ver
= RTL_GIGA_MAC_VER_01
,
3191 .hw_start
= rtl_hw_start_8168
,
3194 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3195 TxErr
| TxOK
| RxOK
| RxErr
,
3196 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
3197 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
3198 .default_ver
= RTL_GIGA_MAC_VER_11
,
3201 .hw_start
= rtl_hw_start_8101
,
3204 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
3205 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3206 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3207 .features
= RTL_FEATURE_MSI
,
3208 .default_ver
= RTL_GIGA_MAC_VER_13
,
3212 /* Cfg9346_Unlock assumed. */
3213 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
3214 const struct rtl_cfg_info
*cfg
)
3219 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
3220 if (cfg
->features
& RTL_FEATURE_MSI
) {
3221 if (pci_enable_msi(pdev
)) {
3222 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
3225 msi
= RTL_FEATURE_MSI
;
3228 RTL_W8(Config2
, cfg2
);
3232 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3234 if (tp
->features
& RTL_FEATURE_MSI
) {
3235 pci_disable_msi(pdev
);
3236 tp
->features
&= ~RTL_FEATURE_MSI
;
3240 static const struct net_device_ops rtl8169_netdev_ops
= {
3241 .ndo_open
= rtl8169_open
,
3242 .ndo_stop
= rtl8169_close
,
3243 .ndo_get_stats
= rtl8169_get_stats
,
3244 .ndo_start_xmit
= rtl8169_start_xmit
,
3245 .ndo_tx_timeout
= rtl8169_tx_timeout
,
3246 .ndo_validate_addr
= eth_validate_addr
,
3247 .ndo_change_mtu
= rtl8169_change_mtu
,
3248 .ndo_fix_features
= rtl8169_fix_features
,
3249 .ndo_set_features
= rtl8169_set_features
,
3250 .ndo_set_mac_address
= rtl_set_mac_address
,
3251 .ndo_do_ioctl
= rtl8169_ioctl
,
3252 .ndo_set_multicast_list
= rtl_set_rx_mode
,
3253 #ifdef CONFIG_NET_POLL_CONTROLLER
3254 .ndo_poll_controller
= rtl8169_netpoll
,
3259 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3261 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3263 switch (tp
->mac_version
) {
3264 case RTL_GIGA_MAC_VER_27
:
3265 ops
->write
= r8168dp_1_mdio_write
;
3266 ops
->read
= r8168dp_1_mdio_read
;
3268 case RTL_GIGA_MAC_VER_28
:
3269 case RTL_GIGA_MAC_VER_31
:
3270 ops
->write
= r8168dp_2_mdio_write
;
3271 ops
->read
= r8168dp_2_mdio_read
;
3274 ops
->write
= r8169_mdio_write
;
3275 ops
->read
= r8169_mdio_read
;
3280 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3282 rtl_writephy(tp
, 0x1f, 0x0000);
3283 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3286 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3288 rtl_writephy(tp
, 0x1f, 0x0000);
3289 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3292 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3294 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3295 rtl_writephy(tp
, 0x1f, 0x0000);
3296 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3300 r810x_phy_power_down(tp
);
3303 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3305 r810x_phy_power_up(tp
);
3308 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3310 rtl_writephy(tp
, 0x1f, 0x0000);
3311 switch (tp
->mac_version
) {
3312 case RTL_GIGA_MAC_VER_11
:
3313 case RTL_GIGA_MAC_VER_12
:
3314 case RTL_GIGA_MAC_VER_17
:
3315 case RTL_GIGA_MAC_VER_18
:
3316 case RTL_GIGA_MAC_VER_19
:
3317 case RTL_GIGA_MAC_VER_20
:
3318 case RTL_GIGA_MAC_VER_21
:
3319 case RTL_GIGA_MAC_VER_22
:
3320 case RTL_GIGA_MAC_VER_23
:
3321 case RTL_GIGA_MAC_VER_24
:
3322 case RTL_GIGA_MAC_VER_25
:
3323 case RTL_GIGA_MAC_VER_26
:
3324 case RTL_GIGA_MAC_VER_27
:
3325 case RTL_GIGA_MAC_VER_28
:
3326 case RTL_GIGA_MAC_VER_31
:
3327 rtl_writephy(tp
, 0x0e, 0x0000);
3332 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3335 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3337 rtl_writephy(tp
, 0x1f, 0x0000);
3338 switch (tp
->mac_version
) {
3339 case RTL_GIGA_MAC_VER_32
:
3340 case RTL_GIGA_MAC_VER_33
:
3341 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3344 case RTL_GIGA_MAC_VER_11
:
3345 case RTL_GIGA_MAC_VER_12
:
3346 case RTL_GIGA_MAC_VER_17
:
3347 case RTL_GIGA_MAC_VER_18
:
3348 case RTL_GIGA_MAC_VER_19
:
3349 case RTL_GIGA_MAC_VER_20
:
3350 case RTL_GIGA_MAC_VER_21
:
3351 case RTL_GIGA_MAC_VER_22
:
3352 case RTL_GIGA_MAC_VER_23
:
3353 case RTL_GIGA_MAC_VER_24
:
3354 case RTL_GIGA_MAC_VER_25
:
3355 case RTL_GIGA_MAC_VER_26
:
3356 case RTL_GIGA_MAC_VER_27
:
3357 case RTL_GIGA_MAC_VER_28
:
3358 case RTL_GIGA_MAC_VER_31
:
3359 rtl_writephy(tp
, 0x0e, 0x0200);
3361 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3366 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3368 void __iomem
*ioaddr
= tp
->mmio_addr
;
3370 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3371 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3372 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3373 r8168dp_check_dash(tp
)) {
3377 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3378 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3379 (RTL_R16(CPlusCmd
) & ASF
)) {
3383 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3384 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3385 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3387 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3388 rtl_writephy(tp
, 0x1f, 0x0000);
3389 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3391 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3392 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3393 RTL_W32(RxConfig
, RTL_R32(RxConfig
) | AcceptBroadcast
|
3394 AcceptMulticast
| AcceptMyPhys
);
3398 r8168_phy_power_down(tp
);
3400 switch (tp
->mac_version
) {
3401 case RTL_GIGA_MAC_VER_25
:
3402 case RTL_GIGA_MAC_VER_26
:
3403 case RTL_GIGA_MAC_VER_27
:
3404 case RTL_GIGA_MAC_VER_28
:
3405 case RTL_GIGA_MAC_VER_31
:
3406 case RTL_GIGA_MAC_VER_32
:
3407 case RTL_GIGA_MAC_VER_33
:
3408 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3413 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3415 void __iomem
*ioaddr
= tp
->mmio_addr
;
3417 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3418 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3419 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3420 r8168dp_check_dash(tp
)) {
3424 switch (tp
->mac_version
) {
3425 case RTL_GIGA_MAC_VER_25
:
3426 case RTL_GIGA_MAC_VER_26
:
3427 case RTL_GIGA_MAC_VER_27
:
3428 case RTL_GIGA_MAC_VER_28
:
3429 case RTL_GIGA_MAC_VER_31
:
3430 case RTL_GIGA_MAC_VER_32
:
3431 case RTL_GIGA_MAC_VER_33
:
3432 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3436 r8168_phy_power_up(tp
);
3439 static void rtl_pll_power_op(struct rtl8169_private
*tp
,
3440 void (*op
)(struct rtl8169_private
*))
3446 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3448 rtl_pll_power_op(tp
, tp
->pll_power_ops
.down
);
3451 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3453 rtl_pll_power_op(tp
, tp
->pll_power_ops
.up
);
3456 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3458 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3460 switch (tp
->mac_version
) {
3461 case RTL_GIGA_MAC_VER_07
:
3462 case RTL_GIGA_MAC_VER_08
:
3463 case RTL_GIGA_MAC_VER_09
:
3464 case RTL_GIGA_MAC_VER_10
:
3465 case RTL_GIGA_MAC_VER_16
:
3466 case RTL_GIGA_MAC_VER_29
:
3467 case RTL_GIGA_MAC_VER_30
:
3468 ops
->down
= r810x_pll_power_down
;
3469 ops
->up
= r810x_pll_power_up
;
3472 case RTL_GIGA_MAC_VER_11
:
3473 case RTL_GIGA_MAC_VER_12
:
3474 case RTL_GIGA_MAC_VER_17
:
3475 case RTL_GIGA_MAC_VER_18
:
3476 case RTL_GIGA_MAC_VER_19
:
3477 case RTL_GIGA_MAC_VER_20
:
3478 case RTL_GIGA_MAC_VER_21
:
3479 case RTL_GIGA_MAC_VER_22
:
3480 case RTL_GIGA_MAC_VER_23
:
3481 case RTL_GIGA_MAC_VER_24
:
3482 case RTL_GIGA_MAC_VER_25
:
3483 case RTL_GIGA_MAC_VER_26
:
3484 case RTL_GIGA_MAC_VER_27
:
3485 case RTL_GIGA_MAC_VER_28
:
3486 case RTL_GIGA_MAC_VER_31
:
3487 case RTL_GIGA_MAC_VER_32
:
3488 case RTL_GIGA_MAC_VER_33
:
3489 case RTL_GIGA_MAC_VER_34
:
3490 ops
->down
= r8168_pll_power_down
;
3491 ops
->up
= r8168_pll_power_up
;
3501 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3503 void __iomem
*ioaddr
= tp
->mmio_addr
;
3505 switch (tp
->mac_version
) {
3506 case RTL_GIGA_MAC_VER_01
:
3507 case RTL_GIGA_MAC_VER_02
:
3508 case RTL_GIGA_MAC_VER_03
:
3509 case RTL_GIGA_MAC_VER_04
:
3510 case RTL_GIGA_MAC_VER_05
:
3511 case RTL_GIGA_MAC_VER_06
:
3512 case RTL_GIGA_MAC_VER_10
:
3513 case RTL_GIGA_MAC_VER_11
:
3514 case RTL_GIGA_MAC_VER_12
:
3515 case RTL_GIGA_MAC_VER_13
:
3516 case RTL_GIGA_MAC_VER_14
:
3517 case RTL_GIGA_MAC_VER_15
:
3518 case RTL_GIGA_MAC_VER_16
:
3519 case RTL_GIGA_MAC_VER_17
:
3520 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3522 case RTL_GIGA_MAC_VER_18
:
3523 case RTL_GIGA_MAC_VER_19
:
3524 case RTL_GIGA_MAC_VER_20
:
3525 case RTL_GIGA_MAC_VER_21
:
3526 case RTL_GIGA_MAC_VER_22
:
3527 case RTL_GIGA_MAC_VER_23
:
3528 case RTL_GIGA_MAC_VER_24
:
3529 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3532 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3537 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3539 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3542 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3544 void __iomem
*ioaddr
= tp
->mmio_addr
;
3547 /* Soft reset the chip. */
3548 RTL_W8(ChipCmd
, CmdReset
);
3550 /* Check that the chip has finished the reset. */
3551 for (i
= 0; i
< 100; i
++) {
3552 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3557 rtl8169_init_ring_indexes(tp
);
3560 static int __devinit
3561 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3563 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3564 const unsigned int region
= cfg
->region
;
3565 struct rtl8169_private
*tp
;
3566 struct mii_if_info
*mii
;
3567 struct net_device
*dev
;
3568 void __iomem
*ioaddr
;
3572 if (netif_msg_drv(&debug
)) {
3573 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3574 MODULENAME
, RTL8169_VERSION
);
3577 dev
= alloc_etherdev(sizeof (*tp
));
3579 if (netif_msg_drv(&debug
))
3580 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3585 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3586 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3587 tp
= netdev_priv(dev
);
3590 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3594 mii
->mdio_read
= rtl_mdio_read
;
3595 mii
->mdio_write
= rtl_mdio_write
;
3596 mii
->phy_id_mask
= 0x1f;
3597 mii
->reg_num_mask
= 0x1f;
3598 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3600 /* disable ASPM completely as that cause random device stop working
3601 * problems as well as full system hangs for some PCIe devices users */
3602 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3603 PCIE_LINK_STATE_CLKPM
);
3605 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3606 rc
= pci_enable_device(pdev
);
3608 netif_err(tp
, probe
, dev
, "enable failure\n");
3609 goto err_out_free_dev_1
;
3612 if (pci_set_mwi(pdev
) < 0)
3613 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3615 /* make sure PCI base addr 1 is MMIO */
3616 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3617 netif_err(tp
, probe
, dev
,
3618 "region #%d not an MMIO resource, aborting\n",
3624 /* check for weird/broken PCI region reporting */
3625 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3626 netif_err(tp
, probe
, dev
,
3627 "Invalid PCI region size(s), aborting\n");
3632 rc
= pci_request_regions(pdev
, MODULENAME
);
3634 netif_err(tp
, probe
, dev
, "could not request regions\n");
3638 tp
->cp_cmd
= RxChkSum
;
3640 if ((sizeof(dma_addr_t
) > 4) &&
3641 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3642 tp
->cp_cmd
|= PCIDAC
;
3643 dev
->features
|= NETIF_F_HIGHDMA
;
3645 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3647 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3648 goto err_out_free_res_3
;
3652 /* ioremap MMIO region */
3653 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3655 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3657 goto err_out_free_res_3
;
3659 tp
->mmio_addr
= ioaddr
;
3661 if (!pci_is_pcie(pdev
))
3662 netif_info(tp
, probe
, dev
, "not PCI Express\n");
3664 /* Identify chip attached to board */
3665 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
3669 RTL_W16(IntrMask
, 0x0000);
3673 RTL_W16(IntrStatus
, 0xffff);
3675 pci_set_master(pdev
);
3678 * Pretend we are using VLANs; This bypasses a nasty bug where
3679 * Interrupts stop flowing on high load on 8110SCd controllers.
3681 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3682 tp
->cp_cmd
|= RxVlan
;
3684 rtl_init_mdio_ops(tp
);
3685 rtl_init_pll_power_ops(tp
);
3687 rtl8169_print_mac_version(tp
);
3689 chipset
= tp
->mac_version
;
3690 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
3692 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3693 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3694 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3695 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3696 tp
->features
|= RTL_FEATURE_WOL
;
3697 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3698 tp
->features
|= RTL_FEATURE_WOL
;
3699 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3700 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3702 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3703 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3704 tp
->set_speed
= rtl8169_set_speed_tbi
;
3705 tp
->get_settings
= rtl8169_gset_tbi
;
3706 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3707 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3708 tp
->link_ok
= rtl8169_tbi_link_ok
;
3709 tp
->do_ioctl
= rtl_tbi_ioctl
;
3711 tp
->set_speed
= rtl8169_set_speed_xmii
;
3712 tp
->get_settings
= rtl8169_gset_xmii
;
3713 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3714 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3715 tp
->link_ok
= rtl8169_xmii_link_ok
;
3716 tp
->do_ioctl
= rtl_xmii_ioctl
;
3719 spin_lock_init(&tp
->lock
);
3721 /* Get MAC address */
3722 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3723 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3724 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3726 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3727 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3728 dev
->irq
= pdev
->irq
;
3729 dev
->base_addr
= (unsigned long) ioaddr
;
3731 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3733 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3734 * properly for all devices */
3735 dev
->features
|= NETIF_F_RXCSUM
|
3736 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3738 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3739 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3740 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3743 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3744 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3745 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
3747 tp
->intr_mask
= 0xffff;
3748 tp
->hw_start
= cfg
->hw_start
;
3749 tp
->intr_event
= cfg
->intr_event
;
3750 tp
->napi_event
= cfg
->napi_event
;
3752 init_timer(&tp
->timer
);
3753 tp
->timer
.data
= (unsigned long) dev
;
3754 tp
->timer
.function
= rtl8169_phy_timer
;
3756 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
3758 rc
= register_netdev(dev
);
3762 pci_set_drvdata(pdev
, dev
);
3764 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3765 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
3766 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3768 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3769 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3770 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3771 rtl8168_driver_start(tp
);
3774 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3776 if (pci_dev_run_wake(pdev
))
3777 pm_runtime_put_noidle(&pdev
->dev
);
3779 netif_carrier_off(dev
);
3785 rtl_disable_msi(pdev
, tp
);
3788 pci_release_regions(pdev
);
3790 pci_clear_mwi(pdev
);
3791 pci_disable_device(pdev
);
3797 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3799 struct net_device
*dev
= pci_get_drvdata(pdev
);
3800 struct rtl8169_private
*tp
= netdev_priv(dev
);
3802 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3803 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3804 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3805 rtl8168_driver_stop(tp
);
3808 cancel_delayed_work_sync(&tp
->task
);
3810 unregister_netdev(dev
);
3812 rtl_release_firmware(tp
);
3814 if (pci_dev_run_wake(pdev
))
3815 pm_runtime_get_noresume(&pdev
->dev
);
3817 /* restore original MAC address */
3818 rtl_rar_set(tp
, dev
->perm_addr
);
3820 rtl_disable_msi(pdev
, tp
);
3821 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3822 pci_set_drvdata(pdev
, NULL
);
3825 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
3827 struct rtl_fw
*rtl_fw
;
3831 name
= rtl_lookup_firmware_name(tp
);
3833 goto out_no_firmware
;
3835 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
3839 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
3843 rc
= rtl_check_firmware(tp
, rtl_fw
);
3845 goto err_release_firmware
;
3847 tp
->rtl_fw
= rtl_fw
;
3851 err_release_firmware
:
3852 release_firmware(rtl_fw
->fw
);
3856 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
3863 static void rtl_request_firmware(struct rtl8169_private
*tp
)
3865 if (IS_ERR(tp
->rtl_fw
))
3866 rtl_request_uncached_firmware(tp
);
3869 static int rtl8169_open(struct net_device
*dev
)
3871 struct rtl8169_private
*tp
= netdev_priv(dev
);
3872 void __iomem
*ioaddr
= tp
->mmio_addr
;
3873 struct pci_dev
*pdev
= tp
->pci_dev
;
3874 int retval
= -ENOMEM
;
3876 pm_runtime_get_sync(&pdev
->dev
);
3879 * Rx and Tx desscriptors needs 256 bytes alignment.
3880 * dma_alloc_coherent provides more.
3882 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3883 &tp
->TxPhyAddr
, GFP_KERNEL
);
3884 if (!tp
->TxDescArray
)
3885 goto err_pm_runtime_put
;
3887 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3888 &tp
->RxPhyAddr
, GFP_KERNEL
);
3889 if (!tp
->RxDescArray
)
3892 retval
= rtl8169_init_ring(dev
);
3896 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3900 rtl_request_firmware(tp
);
3902 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3903 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3906 goto err_release_fw_2
;
3908 napi_enable(&tp
->napi
);
3910 rtl8169_init_phy(dev
, tp
);
3912 rtl8169_set_features(dev
, dev
->features
);
3914 rtl_pll_power_up(tp
);
3918 tp
->saved_wolopts
= 0;
3919 pm_runtime_put_noidle(&pdev
->dev
);
3921 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3926 rtl_release_firmware(tp
);
3927 rtl8169_rx_clear(tp
);
3929 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3931 tp
->RxDescArray
= NULL
;
3933 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3935 tp
->TxDescArray
= NULL
;
3937 pm_runtime_put_noidle(&pdev
->dev
);
3941 static void rtl_rx_close(struct rtl8169_private
*tp
)
3943 void __iomem
*ioaddr
= tp
->mmio_addr
;
3945 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
3948 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3950 void __iomem
*ioaddr
= tp
->mmio_addr
;
3952 /* Disable interrupts */
3953 rtl8169_irq_mask_and_ack(ioaddr
);
3957 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3958 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3959 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3960 while (RTL_R8(TxPoll
) & NPQ
)
3962 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
3963 while (!(RTL_R32(TxConfig
) & TXCFG_EMPTY
))
3966 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
3973 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3975 void __iomem
*ioaddr
= tp
->mmio_addr
;
3977 /* Set DMA burst size and Interframe Gap Time */
3978 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3979 (InterFrameGap
<< TxInterFrameGapShift
));
3982 static void rtl_hw_start(struct net_device
*dev
)
3984 struct rtl8169_private
*tp
= netdev_priv(dev
);
3988 netif_start_queue(dev
);
3991 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3992 void __iomem
*ioaddr
)
3995 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3996 * register to be written before TxDescAddrLow to work.
3997 * Switching from MMIO to I/O access fixes the issue as well.
3999 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4000 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4001 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4002 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4005 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4009 cmd
= RTL_R16(CPlusCmd
);
4010 RTL_W16(CPlusCmd
, cmd
);
4014 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4016 /* Low hurts. Let's disable the filtering. */
4017 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4020 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4022 static const struct rtl_cfg2_info
{
4027 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4028 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4029 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4030 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4032 const struct rtl_cfg2_info
*p
= cfg2_info
;
4036 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4037 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4038 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4039 RTL_W32(0x7c, p
->val
);
4045 static void rtl_hw_start_8169(struct net_device
*dev
)
4047 struct rtl8169_private
*tp
= netdev_priv(dev
);
4048 void __iomem
*ioaddr
= tp
->mmio_addr
;
4049 struct pci_dev
*pdev
= tp
->pci_dev
;
4051 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4052 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4053 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4056 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4057 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4058 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4059 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4060 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4061 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4065 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4067 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4069 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4070 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4071 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4072 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4073 rtl_set_rx_tx_config_registers(tp
);
4075 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4077 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4078 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4079 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4080 "Bit-3 and bit-14 MUST be 1\n");
4081 tp
->cp_cmd
|= (1 << 14);
4084 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4086 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4089 * Undocumented corner. Supposedly:
4090 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4092 RTL_W16(IntrMitigate
, 0x0000);
4094 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4096 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4097 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4098 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4099 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4100 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4101 rtl_set_rx_tx_config_registers(tp
);
4104 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4106 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4109 RTL_W32(RxMissed
, 0);
4111 rtl_set_rx_mode(dev
);
4113 /* no early-rx interrupts */
4114 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4116 /* Enable all known interrupts by setting the interrupt mask. */
4117 RTL_W16(IntrMask
, tp
->intr_event
);
4120 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
4122 int cap
= pci_pcie_cap(pdev
);
4127 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
4128 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
4129 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
4133 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
4137 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
4138 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
4141 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
4143 rtl_csi_access_enable(ioaddr
, 0x17000000);
4146 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
4148 rtl_csi_access_enable(ioaddr
, 0x27000000);
4152 unsigned int offset
;
4157 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
4162 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
4163 rtl_ephy_write(ioaddr
, e
->offset
, w
);
4168 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4170 int cap
= pci_pcie_cap(pdev
);
4175 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4176 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
4177 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4181 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4183 int cap
= pci_pcie_cap(pdev
);
4188 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4189 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
4190 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4194 #define R8168_CPCMD_QUIRK_MASK (\
4205 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4207 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4209 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4211 rtl_tx_performance_tweak(pdev
,
4212 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4215 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4217 rtl_hw_start_8168bb(ioaddr
, pdev
);
4219 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4221 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4224 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4226 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4228 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4230 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4232 rtl_disable_clock_request(pdev
);
4234 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4237 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4239 static const struct ephy_info e_info_8168cp
[] = {
4240 { 0x01, 0, 0x0001 },
4241 { 0x02, 0x0800, 0x1000 },
4242 { 0x03, 0, 0x0042 },
4243 { 0x06, 0x0080, 0x0000 },
4247 rtl_csi_access_enable_2(ioaddr
);
4249 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4251 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4254 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4256 rtl_csi_access_enable_2(ioaddr
);
4258 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4260 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4262 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4265 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4267 rtl_csi_access_enable_2(ioaddr
);
4269 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4272 RTL_W8(DBG_REG
, 0x20);
4274 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4276 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4278 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4281 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4283 static const struct ephy_info e_info_8168c_1
[] = {
4284 { 0x02, 0x0800, 0x1000 },
4285 { 0x03, 0, 0x0002 },
4286 { 0x06, 0x0080, 0x0000 }
4289 rtl_csi_access_enable_2(ioaddr
);
4291 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4293 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4295 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4298 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4300 static const struct ephy_info e_info_8168c_2
[] = {
4301 { 0x01, 0, 0x0001 },
4302 { 0x03, 0x0400, 0x0220 }
4305 rtl_csi_access_enable_2(ioaddr
);
4307 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4309 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4312 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4314 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4317 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4319 rtl_csi_access_enable_2(ioaddr
);
4321 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4324 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4326 rtl_csi_access_enable_2(ioaddr
);
4328 rtl_disable_clock_request(pdev
);
4330 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4332 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4334 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4337 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4339 rtl_csi_access_enable_1(ioaddr
);
4341 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4343 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4345 rtl_disable_clock_request(pdev
);
4348 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4350 static const struct ephy_info e_info_8168d_4
[] = {
4352 { 0x19, 0x20, 0x50 },
4357 rtl_csi_access_enable_1(ioaddr
);
4359 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4361 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4363 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4364 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4367 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4368 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4371 rtl_enable_clock_request(pdev
);
4374 static void rtl_hw_start_8168e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4376 static const struct ephy_info e_info_8168e_1
[] = {
4377 { 0x00, 0x0200, 0x0100 },
4378 { 0x00, 0x0000, 0x0004 },
4379 { 0x06, 0x0002, 0x0001 },
4380 { 0x06, 0x0000, 0x0030 },
4381 { 0x07, 0x0000, 0x2000 },
4382 { 0x00, 0x0000, 0x0020 },
4383 { 0x03, 0x5800, 0x2000 },
4384 { 0x03, 0x0000, 0x0001 },
4385 { 0x01, 0x0800, 0x1000 },
4386 { 0x07, 0x0000, 0x4000 },
4387 { 0x1e, 0x0000, 0x2000 },
4388 { 0x19, 0xffff, 0xfe6c },
4389 { 0x0a, 0x0000, 0x0040 }
4392 rtl_csi_access_enable_2(ioaddr
);
4394 rtl_ephy_init(ioaddr
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
4396 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4398 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4400 rtl_disable_clock_request(pdev
);
4402 /* Reset tx FIFO pointer */
4403 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4404 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4406 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4409 static void rtl_hw_start_8168e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4411 static const struct ephy_info e_info_8168e_2
[] = {
4412 { 0x09, 0x0000, 0x0080 },
4413 { 0x19, 0x0000, 0x0224 }
4416 rtl_csi_access_enable_1(ioaddr
);
4418 rtl_ephy_init(ioaddr
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
4420 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4422 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4423 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4424 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4425 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4426 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4427 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
4428 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4429 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4432 RTL_W8(MaxTxPacketSize
, 0x27);
4434 rtl_disable_clock_request(pdev
);
4436 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4437 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4439 /* Adjust EEE LED frequency */
4440 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4442 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4443 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4444 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4447 static void rtl_hw_start_8168(struct net_device
*dev
)
4449 struct rtl8169_private
*tp
= netdev_priv(dev
);
4450 void __iomem
*ioaddr
= tp
->mmio_addr
;
4451 struct pci_dev
*pdev
= tp
->pci_dev
;
4453 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4455 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4457 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4459 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4461 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4463 RTL_W16(IntrMitigate
, 0x5151);
4465 /* Work around for RxFIFO overflow. */
4466 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
4467 tp
->mac_version
== RTL_GIGA_MAC_VER_22
) {
4468 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4469 tp
->intr_event
&= ~RxOverflow
;
4472 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4474 rtl_set_rx_mode(dev
);
4476 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4477 (InterFrameGap
<< TxInterFrameGapShift
));
4481 switch (tp
->mac_version
) {
4482 case RTL_GIGA_MAC_VER_11
:
4483 rtl_hw_start_8168bb(ioaddr
, pdev
);
4486 case RTL_GIGA_MAC_VER_12
:
4487 case RTL_GIGA_MAC_VER_17
:
4488 rtl_hw_start_8168bef(ioaddr
, pdev
);
4491 case RTL_GIGA_MAC_VER_18
:
4492 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4495 case RTL_GIGA_MAC_VER_19
:
4496 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4499 case RTL_GIGA_MAC_VER_20
:
4500 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4503 case RTL_GIGA_MAC_VER_21
:
4504 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4507 case RTL_GIGA_MAC_VER_22
:
4508 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4511 case RTL_GIGA_MAC_VER_23
:
4512 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4515 case RTL_GIGA_MAC_VER_24
:
4516 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4519 case RTL_GIGA_MAC_VER_25
:
4520 case RTL_GIGA_MAC_VER_26
:
4521 case RTL_GIGA_MAC_VER_27
:
4522 rtl_hw_start_8168d(ioaddr
, pdev
);
4525 case RTL_GIGA_MAC_VER_28
:
4526 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4529 case RTL_GIGA_MAC_VER_31
:
4530 rtl_hw_start_8168dp(ioaddr
, pdev
);
4533 case RTL_GIGA_MAC_VER_32
:
4534 case RTL_GIGA_MAC_VER_33
:
4535 rtl_hw_start_8168e_1(ioaddr
, pdev
);
4537 case RTL_GIGA_MAC_VER_34
:
4538 rtl_hw_start_8168e_2(ioaddr
, pdev
);
4542 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4543 dev
->name
, tp
->mac_version
);
4547 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4549 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4551 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4553 RTL_W16(IntrMask
, tp
->intr_event
);
4556 #define R810X_CPCMD_QUIRK_MASK (\
4567 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4569 static const struct ephy_info e_info_8102e_1
[] = {
4570 { 0x01, 0, 0x6e65 },
4571 { 0x02, 0, 0x091f },
4572 { 0x03, 0, 0xc2f9 },
4573 { 0x06, 0, 0xafb5 },
4574 { 0x07, 0, 0x0e00 },
4575 { 0x19, 0, 0xec80 },
4576 { 0x01, 0, 0x2e65 },
4581 rtl_csi_access_enable_2(ioaddr
);
4583 RTL_W8(DBG_REG
, FIX_NAK_1
);
4585 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4588 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4589 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4591 cfg1
= RTL_R8(Config1
);
4592 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4593 RTL_W8(Config1
, cfg1
& ~LEDS0
);
4595 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
4598 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4600 rtl_csi_access_enable_2(ioaddr
);
4602 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4604 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4605 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4608 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4610 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4612 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
4615 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4617 static const struct ephy_info e_info_8105e_1
[] = {
4618 { 0x07, 0, 0x4000 },
4619 { 0x19, 0, 0x0200 },
4620 { 0x19, 0, 0x0020 },
4621 { 0x1e, 0, 0x2000 },
4622 { 0x03, 0, 0x0001 },
4623 { 0x19, 0, 0x0100 },
4624 { 0x19, 0, 0x0004 },
4628 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4629 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
4631 /* Disable Early Tally Counter */
4632 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
4634 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
4635 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4637 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
4640 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4642 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4643 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
4646 static void rtl_hw_start_8101(struct net_device
*dev
)
4648 struct rtl8169_private
*tp
= netdev_priv(dev
);
4649 void __iomem
*ioaddr
= tp
->mmio_addr
;
4650 struct pci_dev
*pdev
= tp
->pci_dev
;
4652 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
4653 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
4654 int cap
= pci_pcie_cap(pdev
);
4657 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
4658 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4662 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4664 switch (tp
->mac_version
) {
4665 case RTL_GIGA_MAC_VER_07
:
4666 rtl_hw_start_8102e_1(ioaddr
, pdev
);
4669 case RTL_GIGA_MAC_VER_08
:
4670 rtl_hw_start_8102e_3(ioaddr
, pdev
);
4673 case RTL_GIGA_MAC_VER_09
:
4674 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4677 case RTL_GIGA_MAC_VER_29
:
4678 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4680 case RTL_GIGA_MAC_VER_30
:
4681 rtl_hw_start_8105e_2(ioaddr
, pdev
);
4685 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4687 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4689 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4691 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
4692 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4694 RTL_W16(IntrMitigate
, 0x0000);
4696 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4698 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4699 rtl_set_rx_tx_config_registers(tp
);
4703 rtl_set_rx_mode(dev
);
4705 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
4707 RTL_W16(IntrMask
, tp
->intr_event
);
4710 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
4712 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
4716 netdev_update_features(dev
);
4721 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
4723 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
4724 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
4727 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
4728 void **data_buff
, struct RxDesc
*desc
)
4730 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
4735 rtl8169_make_unusable_by_asic(desc
);
4738 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
4740 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
4742 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
4745 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4748 desc
->addr
= cpu_to_le64(mapping
);
4750 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4753 static inline void *rtl8169_align(void *data
)
4755 return (void *)ALIGN((long)data
, 16);
4758 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4759 struct RxDesc
*desc
)
4763 struct device
*d
= &tp
->pci_dev
->dev
;
4764 struct net_device
*dev
= tp
->dev
;
4765 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
4767 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
4771 if (rtl8169_align(data
) != data
) {
4773 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
4778 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
4780 if (unlikely(dma_mapping_error(d
, mapping
))) {
4781 if (net_ratelimit())
4782 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
4786 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4794 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4798 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4799 if (tp
->Rx_databuff
[i
]) {
4800 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4801 tp
->RxDescArray
+ i
);
4806 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4808 desc
->opts1
|= cpu_to_le32(RingEnd
);
4811 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
4815 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4818 if (tp
->Rx_databuff
[i
])
4821 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
4823 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4826 tp
->Rx_databuff
[i
] = data
;
4829 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4833 rtl8169_rx_clear(tp
);
4837 static int rtl8169_init_ring(struct net_device
*dev
)
4839 struct rtl8169_private
*tp
= netdev_priv(dev
);
4841 rtl8169_init_ring_indexes(tp
);
4843 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4844 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4846 return rtl8169_rx_fill(tp
);
4849 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
4850 struct TxDesc
*desc
)
4852 unsigned int len
= tx_skb
->len
;
4854 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
4862 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
4867 for (i
= 0; i
< n
; i
++) {
4868 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
4869 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4870 unsigned int len
= tx_skb
->len
;
4873 struct sk_buff
*skb
= tx_skb
->skb
;
4875 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4876 tp
->TxDescArray
+ entry
);
4878 tp
->dev
->stats
.tx_dropped
++;
4886 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4888 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
4889 tp
->cur_tx
= tp
->dirty_tx
= 0;
4892 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4894 struct rtl8169_private
*tp
= netdev_priv(dev
);
4896 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4897 schedule_delayed_work(&tp
->task
, 4);
4900 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4902 struct rtl8169_private
*tp
= netdev_priv(dev
);
4903 void __iomem
*ioaddr
= tp
->mmio_addr
;
4905 synchronize_irq(dev
->irq
);
4907 /* Wait for any pending NAPI task to complete */
4908 napi_disable(&tp
->napi
);
4910 rtl8169_irq_mask_and_ack(ioaddr
);
4912 tp
->intr_mask
= 0xffff;
4913 RTL_W16(IntrMask
, tp
->intr_event
);
4914 napi_enable(&tp
->napi
);
4917 static void rtl8169_reinit_task(struct work_struct
*work
)
4919 struct rtl8169_private
*tp
=
4920 container_of(work
, struct rtl8169_private
, task
.work
);
4921 struct net_device
*dev
= tp
->dev
;
4926 if (!netif_running(dev
))
4929 rtl8169_wait_for_quiescence(dev
);
4932 ret
= rtl8169_open(dev
);
4933 if (unlikely(ret
< 0)) {
4934 if (net_ratelimit())
4935 netif_err(tp
, drv
, dev
,
4936 "reinit failure (status = %d). Rescheduling\n",
4938 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4945 static void rtl8169_reset_task(struct work_struct
*work
)
4947 struct rtl8169_private
*tp
=
4948 container_of(work
, struct rtl8169_private
, task
.work
);
4949 struct net_device
*dev
= tp
->dev
;
4954 if (!netif_running(dev
))
4957 rtl8169_wait_for_quiescence(dev
);
4959 for (i
= 0; i
< NUM_RX_DESC
; i
++)
4960 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
4962 rtl8169_tx_clear(tp
);
4964 rtl8169_hw_reset(tp
);
4966 netif_wake_queue(dev
);
4967 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4973 static void rtl8169_tx_timeout(struct net_device
*dev
)
4975 struct rtl8169_private
*tp
= netdev_priv(dev
);
4977 rtl8169_hw_reset(tp
);
4979 /* Let's wait a bit while any (async) irq lands on */
4980 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4983 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4986 struct skb_shared_info
*info
= skb_shinfo(skb
);
4987 unsigned int cur_frag
, entry
;
4988 struct TxDesc
* uninitialized_var(txd
);
4989 struct device
*d
= &tp
->pci_dev
->dev
;
4992 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4993 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4998 entry
= (entry
+ 1) % NUM_TX_DESC
;
5000 txd
= tp
->TxDescArray
+ entry
;
5002 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
5003 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5004 if (unlikely(dma_mapping_error(d
, mapping
))) {
5005 if (net_ratelimit())
5006 netif_err(tp
, drv
, tp
->dev
,
5007 "Failed to map TX fragments DMA!\n");
5011 /* Anti gcc 2.95.3 bugware (sic) */
5012 status
= opts
[0] | len
|
5013 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5015 txd
->opts1
= cpu_to_le32(status
);
5016 txd
->opts2
= cpu_to_le32(opts
[1]);
5017 txd
->addr
= cpu_to_le64(mapping
);
5019 tp
->tx_skb
[entry
].len
= len
;
5023 tp
->tx_skb
[entry
].skb
= skb
;
5024 txd
->opts1
|= cpu_to_le32(LastFrag
);
5030 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5034 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
5035 struct sk_buff
*skb
, u32
*opts
)
5037 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
5038 u32 mss
= skb_shinfo(skb
)->gso_size
;
5039 int offset
= info
->opts_offset
;
5043 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
5044 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5045 const struct iphdr
*ip
= ip_hdr(skb
);
5047 if (ip
->protocol
== IPPROTO_TCP
)
5048 opts
[offset
] |= info
->checksum
.tcp
;
5049 else if (ip
->protocol
== IPPROTO_UDP
)
5050 opts
[offset
] |= info
->checksum
.udp
;
5056 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5057 struct net_device
*dev
)
5059 struct rtl8169_private
*tp
= netdev_priv(dev
);
5060 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5061 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5062 void __iomem
*ioaddr
= tp
->mmio_addr
;
5063 struct device
*d
= &tp
->pci_dev
->dev
;
5069 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
5070 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5074 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5077 len
= skb_headlen(skb
);
5078 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5079 if (unlikely(dma_mapping_error(d
, mapping
))) {
5080 if (net_ratelimit())
5081 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5085 tp
->tx_skb
[entry
].len
= len
;
5086 txd
->addr
= cpu_to_le64(mapping
);
5088 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
5091 rtl8169_tso_csum(tp
, skb
, opts
);
5093 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5097 opts
[0] |= FirstFrag
;
5099 opts
[0] |= FirstFrag
| LastFrag
;
5100 tp
->tx_skb
[entry
].skb
= skb
;
5103 txd
->opts2
= cpu_to_le32(opts
[1]);
5107 /* Anti gcc 2.95.3 bugware (sic) */
5108 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5109 txd
->opts1
= cpu_to_le32(status
);
5111 tp
->cur_tx
+= frags
+ 1;
5115 RTL_W8(TxPoll
, NPQ
);
5117 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
5118 netif_stop_queue(dev
);
5120 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
5121 netif_wake_queue(dev
);
5124 return NETDEV_TX_OK
;
5127 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5130 dev
->stats
.tx_dropped
++;
5131 return NETDEV_TX_OK
;
5134 netif_stop_queue(dev
);
5135 dev
->stats
.tx_dropped
++;
5136 return NETDEV_TX_BUSY
;
5139 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5141 struct rtl8169_private
*tp
= netdev_priv(dev
);
5142 struct pci_dev
*pdev
= tp
->pci_dev
;
5143 u16 pci_status
, pci_cmd
;
5145 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5146 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5148 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5149 pci_cmd
, pci_status
);
5152 * The recovery sequence below admits a very elaborated explanation:
5153 * - it seems to work;
5154 * - I did not see what else could be done;
5155 * - it makes iop3xx happy.
5157 * Feel free to adjust to your needs.
5159 if (pdev
->broken_parity_status
)
5160 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5162 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5164 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5166 pci_write_config_word(pdev
, PCI_STATUS
,
5167 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5168 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5169 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5171 /* The infamous DAC f*ckup only happens at boot time */
5172 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
5173 void __iomem
*ioaddr
= tp
->mmio_addr
;
5175 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
5176 tp
->cp_cmd
&= ~PCIDAC
;
5177 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5178 dev
->features
&= ~NETIF_F_HIGHDMA
;
5181 rtl8169_hw_reset(tp
);
5183 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5186 static void rtl8169_tx_interrupt(struct net_device
*dev
,
5187 struct rtl8169_private
*tp
,
5188 void __iomem
*ioaddr
)
5190 unsigned int dirty_tx
, tx_left
;
5192 dirty_tx
= tp
->dirty_tx
;
5194 tx_left
= tp
->cur_tx
- dirty_tx
;
5196 while (tx_left
> 0) {
5197 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5198 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5202 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5203 if (status
& DescOwn
)
5206 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5207 tp
->TxDescArray
+ entry
);
5208 if (status
& LastFrag
) {
5209 dev
->stats
.tx_packets
++;
5210 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
5211 dev_kfree_skb(tx_skb
->skb
);
5218 if (tp
->dirty_tx
!= dirty_tx
) {
5219 tp
->dirty_tx
= dirty_tx
;
5221 if (netif_queue_stopped(dev
) &&
5222 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
5223 netif_wake_queue(dev
);
5226 * 8168 hack: TxPoll requests are lost when the Tx packets are
5227 * too close. Let's kick an extra TxPoll request when a burst
5228 * of start_xmit activity is detected (if it is not detected,
5229 * it is slow enough). -- FR
5232 if (tp
->cur_tx
!= dirty_tx
)
5233 RTL_W8(TxPoll
, NPQ
);
5237 static inline int rtl8169_fragmented_frame(u32 status
)
5239 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5242 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5244 u32 status
= opts1
& RxProtoMask
;
5246 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5247 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5248 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5250 skb_checksum_none_assert(skb
);
5253 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
5254 struct rtl8169_private
*tp
,
5258 struct sk_buff
*skb
;
5259 struct device
*d
= &tp
->pci_dev
->dev
;
5261 data
= rtl8169_align(data
);
5262 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5264 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5266 memcpy(skb
->data
, data
, pkt_size
);
5267 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5272 static int rtl8169_rx_interrupt(struct net_device
*dev
,
5273 struct rtl8169_private
*tp
,
5274 void __iomem
*ioaddr
, u32 budget
)
5276 unsigned int cur_rx
, rx_left
;
5279 cur_rx
= tp
->cur_rx
;
5280 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5281 rx_left
= min(rx_left
, budget
);
5283 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5284 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5285 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5289 status
= le32_to_cpu(desc
->opts1
);
5291 if (status
& DescOwn
)
5293 if (unlikely(status
& RxRES
)) {
5294 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5296 dev
->stats
.rx_errors
++;
5297 if (status
& (RxRWT
| RxRUNT
))
5298 dev
->stats
.rx_length_errors
++;
5300 dev
->stats
.rx_crc_errors
++;
5301 if (status
& RxFOVF
) {
5302 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5303 dev
->stats
.rx_fifo_errors
++;
5305 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5307 struct sk_buff
*skb
;
5308 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
5309 int pkt_size
= (status
& 0x00001FFF) - 4;
5312 * The driver does not support incoming fragmented
5313 * frames. They are seen as a symptom of over-mtu
5316 if (unlikely(rtl8169_fragmented_frame(status
))) {
5317 dev
->stats
.rx_dropped
++;
5318 dev
->stats
.rx_length_errors
++;
5319 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5323 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5324 tp
, pkt_size
, addr
);
5325 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5327 dev
->stats
.rx_dropped
++;
5331 rtl8169_rx_csum(skb
, status
);
5332 skb_put(skb
, pkt_size
);
5333 skb
->protocol
= eth_type_trans(skb
, dev
);
5335 rtl8169_rx_vlan_tag(desc
, skb
);
5337 napi_gro_receive(&tp
->napi
, skb
);
5339 dev
->stats
.rx_bytes
+= pkt_size
;
5340 dev
->stats
.rx_packets
++;
5343 /* Work around for AMD plateform. */
5344 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5345 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5351 count
= cur_rx
- tp
->cur_rx
;
5352 tp
->cur_rx
= cur_rx
;
5354 tp
->dirty_rx
+= count
;
5359 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5361 struct net_device
*dev
= dev_instance
;
5362 struct rtl8169_private
*tp
= netdev_priv(dev
);
5363 void __iomem
*ioaddr
= tp
->mmio_addr
;
5367 /* loop handling interrupts until we have no new ones or
5368 * we hit a invalid/hotplug case.
5370 status
= RTL_R16(IntrStatus
);
5371 while (status
&& status
!= 0xffff) {
5374 /* Handle all of the error cases first. These will reset
5375 * the chip, so just exit the loop.
5377 if (unlikely(!netif_running(dev
))) {
5378 rtl8169_hw_reset(tp
);
5382 if (unlikely(status
& RxFIFOOver
)) {
5383 switch (tp
->mac_version
) {
5384 /* Work around for rx fifo overflow */
5385 case RTL_GIGA_MAC_VER_11
:
5386 case RTL_GIGA_MAC_VER_22
:
5387 case RTL_GIGA_MAC_VER_26
:
5388 netif_stop_queue(dev
);
5389 rtl8169_tx_timeout(dev
);
5391 /* Testers needed. */
5392 case RTL_GIGA_MAC_VER_17
:
5393 case RTL_GIGA_MAC_VER_19
:
5394 case RTL_GIGA_MAC_VER_20
:
5395 case RTL_GIGA_MAC_VER_21
:
5396 case RTL_GIGA_MAC_VER_23
:
5397 case RTL_GIGA_MAC_VER_24
:
5398 case RTL_GIGA_MAC_VER_27
:
5399 case RTL_GIGA_MAC_VER_28
:
5400 case RTL_GIGA_MAC_VER_31
:
5401 /* Experimental science. Pktgen proof. */
5402 case RTL_GIGA_MAC_VER_12
:
5403 case RTL_GIGA_MAC_VER_25
:
5404 if (status
== RxFIFOOver
)
5412 if (unlikely(status
& SYSErr
)) {
5413 rtl8169_pcierr_interrupt(dev
);
5417 if (status
& LinkChg
)
5418 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5420 /* We need to see the lastest version of tp->intr_mask to
5421 * avoid ignoring an MSI interrupt and having to wait for
5422 * another event which may never come.
5425 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5426 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5427 tp
->intr_mask
= ~tp
->napi_event
;
5429 if (likely(napi_schedule_prep(&tp
->napi
)))
5430 __napi_schedule(&tp
->napi
);
5432 netif_info(tp
, intr
, dev
,
5433 "interrupt %04x in poll\n", status
);
5436 /* We only get a new MSI interrupt when all active irq
5437 * sources on the chip have been acknowledged. So, ack
5438 * everything we've seen and check if new sources have become
5439 * active to avoid blocking all interrupts from the chip.
5442 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5443 status
= RTL_R16(IntrStatus
);
5446 return IRQ_RETVAL(handled
);
5449 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5451 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5452 struct net_device
*dev
= tp
->dev
;
5453 void __iomem
*ioaddr
= tp
->mmio_addr
;
5456 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5457 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5459 if (work_done
< budget
) {
5460 napi_complete(napi
);
5462 /* We need for force the visibility of tp->intr_mask
5463 * for other CPUs, as we can loose an MSI interrupt
5464 * and potentially wait for a retransmit timeout if we don't.
5465 * The posted write to IntrMask is safe, as it will
5466 * eventually make it to the chip and we won't loose anything
5469 tp
->intr_mask
= 0xffff;
5471 RTL_W16(IntrMask
, tp
->intr_event
);
5477 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5479 struct rtl8169_private
*tp
= netdev_priv(dev
);
5481 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5484 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5485 RTL_W32(RxMissed
, 0);
5488 static void rtl8169_down(struct net_device
*dev
)
5490 struct rtl8169_private
*tp
= netdev_priv(dev
);
5491 void __iomem
*ioaddr
= tp
->mmio_addr
;
5493 del_timer_sync(&tp
->timer
);
5495 netif_stop_queue(dev
);
5497 napi_disable(&tp
->napi
);
5499 spin_lock_irq(&tp
->lock
);
5501 rtl8169_hw_reset(tp
);
5503 * At this point device interrupts can not be enabled in any function,
5504 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5505 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5507 rtl8169_rx_missed(dev
, ioaddr
);
5509 spin_unlock_irq(&tp
->lock
);
5511 synchronize_irq(dev
->irq
);
5513 /* Give a racing hard_start_xmit a few cycles to complete. */
5514 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5516 rtl8169_tx_clear(tp
);
5518 rtl8169_rx_clear(tp
);
5520 rtl_pll_power_down(tp
);
5523 static int rtl8169_close(struct net_device
*dev
)
5525 struct rtl8169_private
*tp
= netdev_priv(dev
);
5526 struct pci_dev
*pdev
= tp
->pci_dev
;
5528 pm_runtime_get_sync(&pdev
->dev
);
5530 /* Update counters before going down */
5531 rtl8169_update_counters(dev
);
5535 free_irq(dev
->irq
, dev
);
5537 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5539 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5541 tp
->TxDescArray
= NULL
;
5542 tp
->RxDescArray
= NULL
;
5544 pm_runtime_put_sync(&pdev
->dev
);
5549 static void rtl_set_rx_mode(struct net_device
*dev
)
5551 struct rtl8169_private
*tp
= netdev_priv(dev
);
5552 void __iomem
*ioaddr
= tp
->mmio_addr
;
5553 unsigned long flags
;
5554 u32 mc_filter
[2]; /* Multicast hash filter */
5558 if (dev
->flags
& IFF_PROMISC
) {
5559 /* Unconditionally log net taps. */
5560 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5562 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5564 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5565 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5566 (dev
->flags
& IFF_ALLMULTI
)) {
5567 /* Too many to filter perfectly -- accept all multicasts. */
5568 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5569 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5571 struct netdev_hw_addr
*ha
;
5573 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5574 mc_filter
[1] = mc_filter
[0] = 0;
5575 netdev_for_each_mc_addr(ha
, dev
) {
5576 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5577 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5578 rx_mode
|= AcceptMulticast
;
5582 spin_lock_irqsave(&tp
->lock
, flags
);
5584 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
5586 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5587 u32 data
= mc_filter
[0];
5589 mc_filter
[0] = swab32(mc_filter
[1]);
5590 mc_filter
[1] = swab32(data
);
5593 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5594 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5596 RTL_W32(RxConfig
, tmp
);
5598 spin_unlock_irqrestore(&tp
->lock
, flags
);
5602 * rtl8169_get_stats - Get rtl8169 read/write statistics
5603 * @dev: The Ethernet Device to get statistics for
5605 * Get TX/RX statistics for rtl8169
5607 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
5609 struct rtl8169_private
*tp
= netdev_priv(dev
);
5610 void __iomem
*ioaddr
= tp
->mmio_addr
;
5611 unsigned long flags
;
5613 if (netif_running(dev
)) {
5614 spin_lock_irqsave(&tp
->lock
, flags
);
5615 rtl8169_rx_missed(dev
, ioaddr
);
5616 spin_unlock_irqrestore(&tp
->lock
, flags
);
5622 static void rtl8169_net_suspend(struct net_device
*dev
)
5624 struct rtl8169_private
*tp
= netdev_priv(dev
);
5626 if (!netif_running(dev
))
5629 rtl_pll_power_down(tp
);
5631 netif_device_detach(dev
);
5632 netif_stop_queue(dev
);
5637 static int rtl8169_suspend(struct device
*device
)
5639 struct pci_dev
*pdev
= to_pci_dev(device
);
5640 struct net_device
*dev
= pci_get_drvdata(pdev
);
5642 rtl8169_net_suspend(dev
);
5647 static void __rtl8169_resume(struct net_device
*dev
)
5649 struct rtl8169_private
*tp
= netdev_priv(dev
);
5651 netif_device_attach(dev
);
5653 rtl_pll_power_up(tp
);
5655 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5658 static int rtl8169_resume(struct device
*device
)
5660 struct pci_dev
*pdev
= to_pci_dev(device
);
5661 struct net_device
*dev
= pci_get_drvdata(pdev
);
5662 struct rtl8169_private
*tp
= netdev_priv(dev
);
5664 rtl8169_init_phy(dev
, tp
);
5666 if (netif_running(dev
))
5667 __rtl8169_resume(dev
);
5672 static int rtl8169_runtime_suspend(struct device
*device
)
5674 struct pci_dev
*pdev
= to_pci_dev(device
);
5675 struct net_device
*dev
= pci_get_drvdata(pdev
);
5676 struct rtl8169_private
*tp
= netdev_priv(dev
);
5678 if (!tp
->TxDescArray
)
5681 spin_lock_irq(&tp
->lock
);
5682 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
5683 __rtl8169_set_wol(tp
, WAKE_ANY
);
5684 spin_unlock_irq(&tp
->lock
);
5686 rtl8169_net_suspend(dev
);
5691 static int rtl8169_runtime_resume(struct device
*device
)
5693 struct pci_dev
*pdev
= to_pci_dev(device
);
5694 struct net_device
*dev
= pci_get_drvdata(pdev
);
5695 struct rtl8169_private
*tp
= netdev_priv(dev
);
5697 if (!tp
->TxDescArray
)
5700 spin_lock_irq(&tp
->lock
);
5701 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
5702 tp
->saved_wolopts
= 0;
5703 spin_unlock_irq(&tp
->lock
);
5705 rtl8169_init_phy(dev
, tp
);
5707 __rtl8169_resume(dev
);
5712 static int rtl8169_runtime_idle(struct device
*device
)
5714 struct pci_dev
*pdev
= to_pci_dev(device
);
5715 struct net_device
*dev
= pci_get_drvdata(pdev
);
5716 struct rtl8169_private
*tp
= netdev_priv(dev
);
5718 return tp
->TxDescArray
? -EBUSY
: 0;
5721 static const struct dev_pm_ops rtl8169_pm_ops
= {
5722 .suspend
= rtl8169_suspend
,
5723 .resume
= rtl8169_resume
,
5724 .freeze
= rtl8169_suspend
,
5725 .thaw
= rtl8169_resume
,
5726 .poweroff
= rtl8169_suspend
,
5727 .restore
= rtl8169_resume
,
5728 .runtime_suspend
= rtl8169_runtime_suspend
,
5729 .runtime_resume
= rtl8169_runtime_resume
,
5730 .runtime_idle
= rtl8169_runtime_idle
,
5733 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5735 #else /* !CONFIG_PM */
5737 #define RTL8169_PM_OPS NULL
5739 #endif /* !CONFIG_PM */
5741 static void rtl_shutdown(struct pci_dev
*pdev
)
5743 struct net_device
*dev
= pci_get_drvdata(pdev
);
5744 struct rtl8169_private
*tp
= netdev_priv(dev
);
5745 void __iomem
*ioaddr
= tp
->mmio_addr
;
5747 rtl8169_net_suspend(dev
);
5749 /* Restore original MAC address */
5750 rtl_rar_set(tp
, dev
->perm_addr
);
5752 spin_lock_irq(&tp
->lock
);
5754 rtl8169_hw_reset(tp
);
5756 spin_unlock_irq(&tp
->lock
);
5758 if (system_state
== SYSTEM_POWER_OFF
) {
5759 /* WoL fails with 8168b when the receiver is disabled. */
5760 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
5761 tp
->mac_version
== RTL_GIGA_MAC_VER_12
||
5762 tp
->mac_version
== RTL_GIGA_MAC_VER_17
) &&
5763 (tp
->features
& RTL_FEATURE_WOL
)) {
5764 pci_clear_master(pdev
);
5766 RTL_W8(ChipCmd
, CmdRxEnb
);
5771 pci_wake_from_d3(pdev
, true);
5772 pci_set_power_state(pdev
, PCI_D3hot
);
5776 static struct pci_driver rtl8169_pci_driver
= {
5778 .id_table
= rtl8169_pci_tbl
,
5779 .probe
= rtl8169_init_one
,
5780 .remove
= __devexit_p(rtl8169_remove_one
),
5781 .shutdown
= rtl_shutdown
,
5782 .driver
.pm
= RTL8169_PM_OPS
,
5785 static int __init
rtl8169_init_module(void)
5787 return pci_register_driver(&rtl8169_pci_driver
);
5790 static void __exit
rtl8169_cleanup_module(void)
5792 pci_unregister_driver(&rtl8169_pci_driver
);
5795 module_init(rtl8169_init_module
);
5796 module_exit(rtl8169_cleanup_module
);