1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 ************************************************************************/
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/skbuff.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/stddef.h>
68 #include <linux/ioctl.h>
69 #include <linux/timex.h>
70 #include <linux/ethtool.h>
71 #include <linux/workqueue.h>
72 #include <linux/if_vlan.h>
74 #include <linux/tcp.h>
77 #include <asm/system.h>
78 #include <asm/uaccess.h>
80 #include <asm/div64.h>
85 #include "s2io-regs.h"
87 #define DRV_VERSION "2.0.26.6"
89 /* S2io Driver name & version. */
90 static char s2io_driver_name
[] = "Neterion";
91 static char s2io_driver_version
[] = DRV_VERSION
;
93 static int rxd_size
[2] = {32,48};
94 static int rxd_count
[2] = {127,85};
96 static inline int RXD_IS_UP2DT(struct RxD_t
*rxdp
)
100 ret
= ((!(rxdp
->Control_1
& RXD_OWN_XENA
)) &&
101 (GET_RXD_MARKER(rxdp
->Control_2
) != THE_RXD_MARK
));
107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
121 static inline int rx_buffer_level(struct s2io_nic
* sp
, int rxb_size
, int ring
)
123 struct mac_info
*mac_control
;
125 mac_control
= &sp
->mac_control
;
126 if (rxb_size
<= rxd_count
[sp
->rxd_mode
])
128 else if ((mac_control
->rings
[ring
].pkt_cnt
- rxb_size
) > 16)
133 static inline int is_s2io_card_up(const struct s2io_nic
* sp
)
135 return test_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
138 /* Ethtool related variables and Macros. */
139 static char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
140 "Register test\t(offline)",
141 "Eeprom test\t(offline)",
142 "Link test\t(online)",
143 "RLDRAM test\t(offline)",
144 "BIST Test\t(offline)"
147 static char ethtool_xena_stats_keys
[][ETH_GSTRING_LEN
] = {
149 {"tmac_data_octets"},
153 {"tmac_pause_ctrl_frms"},
157 {"tmac_any_err_frms"},
158 {"tmac_ttl_less_fb_octets"},
159 {"tmac_vld_ip_octets"},
167 {"rmac_data_octets"},
168 {"rmac_fcs_err_frms"},
170 {"rmac_vld_mcst_frms"},
171 {"rmac_vld_bcst_frms"},
172 {"rmac_in_rng_len_err_frms"},
173 {"rmac_out_rng_len_err_frms"},
175 {"rmac_pause_ctrl_frms"},
176 {"rmac_unsup_ctrl_frms"},
178 {"rmac_accepted_ucst_frms"},
179 {"rmac_accepted_nucst_frms"},
180 {"rmac_discarded_frms"},
181 {"rmac_drop_events"},
182 {"rmac_ttl_less_fb_octets"},
184 {"rmac_usized_frms"},
185 {"rmac_osized_frms"},
187 {"rmac_jabber_frms"},
188 {"rmac_ttl_64_frms"},
189 {"rmac_ttl_65_127_frms"},
190 {"rmac_ttl_128_255_frms"},
191 {"rmac_ttl_256_511_frms"},
192 {"rmac_ttl_512_1023_frms"},
193 {"rmac_ttl_1024_1518_frms"},
201 {"rmac_err_drp_udp"},
202 {"rmac_xgmii_err_sym"},
220 {"rmac_xgmii_data_err_cnt"},
221 {"rmac_xgmii_ctrl_err_cnt"},
222 {"rmac_accepted_ip"},
226 {"new_rd_req_rtry_cnt"},
228 {"wr_rtry_rd_ack_cnt"},
231 {"new_wr_req_rtry_cnt"},
234 {"rd_rtry_wr_ack_cnt"},
244 static char ethtool_enhanced_stats_keys
[][ETH_GSTRING_LEN
] = {
245 {"rmac_ttl_1519_4095_frms"},
246 {"rmac_ttl_4096_8191_frms"},
247 {"rmac_ttl_8192_max_frms"},
248 {"rmac_ttl_gt_max_frms"},
249 {"rmac_osized_alt_frms"},
250 {"rmac_jabber_alt_frms"},
251 {"rmac_gt_max_alt_frms"},
253 {"rmac_len_discard"},
254 {"rmac_fcs_discard"},
257 {"rmac_red_discard"},
258 {"rmac_rts_discard"},
259 {"rmac_ingm_full_discard"},
263 static char ethtool_driver_stats_keys
[][ETH_GSTRING_LEN
] = {
264 {"\n DRIVER STATISTICS"},
265 {"single_bit_ecc_errs"},
266 {"double_bit_ecc_errs"},
279 {"alarm_transceiver_temp_high"},
280 {"alarm_transceiver_temp_low"},
281 {"alarm_laser_bias_current_high"},
282 {"alarm_laser_bias_current_low"},
283 {"alarm_laser_output_power_high"},
284 {"alarm_laser_output_power_low"},
285 {"warn_transceiver_temp_high"},
286 {"warn_transceiver_temp_low"},
287 {"warn_laser_bias_current_high"},
288 {"warn_laser_bias_current_low"},
289 {"warn_laser_output_power_high"},
290 {"warn_laser_output_power_low"},
291 {"lro_aggregated_pkts"},
292 {"lro_flush_both_count"},
293 {"lro_out_of_sequence_pkts"},
294 {"lro_flush_due_to_max_pkts"},
295 {"lro_avg_aggr_pkts"},
296 {"mem_alloc_fail_cnt"},
297 {"pci_map_fail_cnt"},
298 {"watchdog_timer_cnt"},
305 {"tx_tcode_buf_abort_cnt"},
306 {"tx_tcode_desc_abort_cnt"},
307 {"tx_tcode_parity_err_cnt"},
308 {"tx_tcode_link_loss_cnt"},
309 {"tx_tcode_list_proc_err_cnt"},
310 {"rx_tcode_parity_err_cnt"},
311 {"rx_tcode_abort_cnt"},
312 {"rx_tcode_parity_abort_cnt"},
313 {"rx_tcode_rda_fail_cnt"},
314 {"rx_tcode_unkn_prot_cnt"},
315 {"rx_tcode_fcs_err_cnt"},
316 {"rx_tcode_buf_size_err_cnt"},
317 {"rx_tcode_rxd_corrupt_cnt"},
318 {"rx_tcode_unkn_err_cnt"},
326 {"mac_tmac_err_cnt"},
327 {"mac_rmac_err_cnt"},
328 {"xgxs_txgxs_err_cnt"},
329 {"xgxs_rxgxs_err_cnt"},
331 {"prc_pcix_err_cnt"},
338 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
339 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
341 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
343 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
344 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
346 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
347 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
349 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
350 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
352 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
353 init_timer(&timer); \
354 timer.function = handle; \
355 timer.data = (unsigned long) arg; \
356 mod_timer(&timer, (jiffies + exp)) \
358 /* copy mac addr to def_mac_addr array */
359 static void do_s2io_copy_mac_addr(struct s2io_nic
*sp
, int offset
, u64 mac_addr
)
361 sp
->def_mac_addr
[offset
].mac_addr
[5] = (u8
) (mac_addr
);
362 sp
->def_mac_addr
[offset
].mac_addr
[4] = (u8
) (mac_addr
>> 8);
363 sp
->def_mac_addr
[offset
].mac_addr
[3] = (u8
) (mac_addr
>> 16);
364 sp
->def_mac_addr
[offset
].mac_addr
[2] = (u8
) (mac_addr
>> 24);
365 sp
->def_mac_addr
[offset
].mac_addr
[1] = (u8
) (mac_addr
>> 32);
366 sp
->def_mac_addr
[offset
].mac_addr
[0] = (u8
) (mac_addr
>> 40);
369 static void s2io_vlan_rx_register(struct net_device
*dev
,
370 struct vlan_group
*grp
)
372 struct s2io_nic
*nic
= dev
->priv
;
375 spin_lock_irqsave(&nic
->tx_lock
, flags
);
377 spin_unlock_irqrestore(&nic
->tx_lock
, flags
);
380 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
381 static int vlan_strip_flag
;
384 * Constants to be programmed into the Xena's registers, to configure
389 static const u64 herc_act_dtx_cfg
[] = {
391 0x8000051536750000ULL
, 0x80000515367500E0ULL
,
393 0x8000051536750004ULL
, 0x80000515367500E4ULL
,
395 0x80010515003F0000ULL
, 0x80010515003F00E0ULL
,
397 0x80010515003F0004ULL
, 0x80010515003F00E4ULL
,
399 0x801205150D440000ULL
, 0x801205150D4400E0ULL
,
401 0x801205150D440004ULL
, 0x801205150D4400E4ULL
,
403 0x80020515F2100000ULL
, 0x80020515F21000E0ULL
,
405 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
410 static const u64 xena_dtx_cfg
[] = {
412 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
414 0x80000515D9350004ULL
, 0x80000515D93500E4ULL
,
416 0x8001051500000000ULL
, 0x80010515000000E0ULL
,
418 0x80010515001E0004ULL
, 0x80010515001E00E4ULL
,
420 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
422 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
427 * Constants for Fixing the MacAddress problem seen mostly on
430 static const u64 fix_mac
[] = {
431 0x0060000000000000ULL
, 0x0060600000000000ULL
,
432 0x0040600000000000ULL
, 0x0000600000000000ULL
,
433 0x0020600000000000ULL
, 0x0060600000000000ULL
,
434 0x0020600000000000ULL
, 0x0060600000000000ULL
,
435 0x0020600000000000ULL
, 0x0060600000000000ULL
,
436 0x0020600000000000ULL
, 0x0060600000000000ULL
,
437 0x0020600000000000ULL
, 0x0060600000000000ULL
,
438 0x0020600000000000ULL
, 0x0060600000000000ULL
,
439 0x0020600000000000ULL
, 0x0060600000000000ULL
,
440 0x0020600000000000ULL
, 0x0060600000000000ULL
,
441 0x0020600000000000ULL
, 0x0060600000000000ULL
,
442 0x0020600000000000ULL
, 0x0060600000000000ULL
,
443 0x0020600000000000ULL
, 0x0000600000000000ULL
,
444 0x0040600000000000ULL
, 0x0060600000000000ULL
,
448 MODULE_LICENSE("GPL");
449 MODULE_VERSION(DRV_VERSION
);
452 /* Module Loadable parameters. */
453 S2IO_PARM_INT(tx_fifo_num
, 1);
454 S2IO_PARM_INT(rx_ring_num
, 1);
457 S2IO_PARM_INT(rx_ring_mode
, 1);
458 S2IO_PARM_INT(use_continuous_tx_intrs
, 1);
459 S2IO_PARM_INT(rmac_pause_time
, 0x100);
460 S2IO_PARM_INT(mc_pause_threshold_q0q3
, 187);
461 S2IO_PARM_INT(mc_pause_threshold_q4q7
, 187);
462 S2IO_PARM_INT(shared_splits
, 0);
463 S2IO_PARM_INT(tmac_util_period
, 5);
464 S2IO_PARM_INT(rmac_util_period
, 5);
465 S2IO_PARM_INT(l3l4hdr_size
, 128);
466 /* Frequency of Rx desc syncs expressed as power of 2 */
467 S2IO_PARM_INT(rxsync_frequency
, 3);
468 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
469 S2IO_PARM_INT(intr_type
, 2);
470 /* Large receive offload feature */
471 static unsigned int lro_enable
;
472 module_param_named(lro
, lro_enable
, uint
, 0);
474 /* Max pkts to be aggregated by LRO at one time. If not specified,
475 * aggregation happens until we hit max IP pkt size(64K)
477 S2IO_PARM_INT(lro_max_pkts
, 0xFFFF);
478 S2IO_PARM_INT(indicate_max_pkts
, 0);
480 S2IO_PARM_INT(napi
, 1);
481 S2IO_PARM_INT(ufo
, 0);
482 S2IO_PARM_INT(vlan_tag_strip
, NO_STRIP_IN_PROMISC
);
484 static unsigned int tx_fifo_len
[MAX_TX_FIFOS
] =
485 {DEFAULT_FIFO_0_LEN
, [1 ...(MAX_TX_FIFOS
- 1)] = DEFAULT_FIFO_1_7_LEN
};
486 static unsigned int rx_ring_sz
[MAX_RX_RINGS
] =
487 {[0 ...(MAX_RX_RINGS
- 1)] = SMALL_BLK_CNT
};
488 static unsigned int rts_frm_len
[MAX_RX_RINGS
] =
489 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
491 module_param_array(tx_fifo_len
, uint
, NULL
, 0);
492 module_param_array(rx_ring_sz
, uint
, NULL
, 0);
493 module_param_array(rts_frm_len
, uint
, NULL
, 0);
497 * This table lists all the devices that this driver supports.
499 static struct pci_device_id s2io_tbl
[] __devinitdata
= {
500 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
501 PCI_ANY_ID
, PCI_ANY_ID
},
502 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
503 PCI_ANY_ID
, PCI_ANY_ID
},
504 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_WIN
,
505 PCI_ANY_ID
, PCI_ANY_ID
},
506 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_UNI
,
507 PCI_ANY_ID
, PCI_ANY_ID
},
511 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
513 static struct pci_error_handlers s2io_err_handler
= {
514 .error_detected
= s2io_io_error_detected
,
515 .slot_reset
= s2io_io_slot_reset
,
516 .resume
= s2io_io_resume
,
519 static struct pci_driver s2io_driver
= {
521 .id_table
= s2io_tbl
,
522 .probe
= s2io_init_nic
,
523 .remove
= __devexit_p(s2io_rem_nic
),
524 .err_handler
= &s2io_err_handler
,
527 /* A simplifier macro used both by init and free shared_mem Fns(). */
528 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
531 * init_shared_mem - Allocation and Initialization of Memory
532 * @nic: Device private variable.
533 * Description: The function allocates all the memory areas shared
534 * between the NIC and the driver. This includes Tx descriptors,
535 * Rx descriptors and the statistics block.
538 static int init_shared_mem(struct s2io_nic
*nic
)
541 void *tmp_v_addr
, *tmp_v_addr_next
;
542 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
543 struct RxD_block
*pre_rxd_blk
= NULL
;
545 int lst_size
, lst_per_page
;
546 struct net_device
*dev
= nic
->dev
;
550 struct mac_info
*mac_control
;
551 struct config_param
*config
;
552 unsigned long long mem_allocated
= 0;
554 mac_control
= &nic
->mac_control
;
555 config
= &nic
->config
;
558 /* Allocation and initialization of TXDLs in FIOFs */
560 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
561 size
+= config
->tx_cfg
[i
].fifo_len
;
563 if (size
> MAX_AVAILABLE_TXDS
) {
564 DBG_PRINT(ERR_DBG
, "s2io: Requested TxDs too high, ");
565 DBG_PRINT(ERR_DBG
, "Requested: %d, max supported: 8192\n", size
);
569 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
570 lst_per_page
= PAGE_SIZE
/ lst_size
;
572 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
573 int fifo_len
= config
->tx_cfg
[i
].fifo_len
;
574 int list_holder_size
= fifo_len
* sizeof(struct list_info_hold
);
575 mac_control
->fifos
[i
].list_info
= kzalloc(list_holder_size
,
577 if (!mac_control
->fifos
[i
].list_info
) {
579 "Malloc failed for list_info\n");
582 mem_allocated
+= list_holder_size
;
584 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
585 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
587 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
588 mac_control
->fifos
[i
].tx_curr_put_info
.fifo_len
=
589 config
->tx_cfg
[i
].fifo_len
- 1;
590 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
591 mac_control
->fifos
[i
].tx_curr_get_info
.fifo_len
=
592 config
->tx_cfg
[i
].fifo_len
- 1;
593 mac_control
->fifos
[i
].fifo_no
= i
;
594 mac_control
->fifos
[i
].nic
= nic
;
595 mac_control
->fifos
[i
].max_txds
= MAX_SKB_FRAGS
+ 2;
597 for (j
= 0; j
< page_num
; j
++) {
601 tmp_v
= pci_alloc_consistent(nic
->pdev
,
605 "pci_alloc_consistent ");
606 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
609 /* If we got a zero DMA address(can happen on
610 * certain platforms like PPC), reallocate.
611 * Store virtual address of page we don't want,
615 mac_control
->zerodma_virt_addr
= tmp_v
;
617 "%s: Zero DMA address for TxDL. ", dev
->name
);
619 "Virtual address %p\n", tmp_v
);
620 tmp_v
= pci_alloc_consistent(nic
->pdev
,
624 "pci_alloc_consistent ");
625 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
628 mem_allocated
+= PAGE_SIZE
;
630 while (k
< lst_per_page
) {
631 int l
= (j
* lst_per_page
) + k
;
632 if (l
== config
->tx_cfg
[i
].fifo_len
)
634 mac_control
->fifos
[i
].list_info
[l
].list_virt_addr
=
635 tmp_v
+ (k
* lst_size
);
636 mac_control
->fifos
[i
].list_info
[l
].list_phy_addr
=
637 tmp_p
+ (k
* lst_size
);
643 nic
->ufo_in_band_v
= kcalloc(size
, sizeof(u64
), GFP_KERNEL
);
644 if (!nic
->ufo_in_band_v
)
646 mem_allocated
+= (size
* sizeof(u64
));
648 /* Allocation and initialization of RXDs in Rings */
650 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
651 if (config
->rx_cfg
[i
].num_rxd
%
652 (rxd_count
[nic
->rxd_mode
] + 1)) {
653 DBG_PRINT(ERR_DBG
, "%s: RxD count of ", dev
->name
);
654 DBG_PRINT(ERR_DBG
, "Ring%d is not a multiple of ",
656 DBG_PRINT(ERR_DBG
, "RxDs per Block");
659 size
+= config
->rx_cfg
[i
].num_rxd
;
660 mac_control
->rings
[i
].block_count
=
661 config
->rx_cfg
[i
].num_rxd
/
662 (rxd_count
[nic
->rxd_mode
] + 1 );
663 mac_control
->rings
[i
].pkt_cnt
= config
->rx_cfg
[i
].num_rxd
-
664 mac_control
->rings
[i
].block_count
;
666 if (nic
->rxd_mode
== RXD_MODE_1
)
667 size
= (size
* (sizeof(struct RxD1
)));
669 size
= (size
* (sizeof(struct RxD3
)));
671 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
672 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
673 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
674 mac_control
->rings
[i
].rx_curr_get_info
.ring_len
=
675 config
->rx_cfg
[i
].num_rxd
- 1;
676 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
677 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
678 mac_control
->rings
[i
].rx_curr_put_info
.ring_len
=
679 config
->rx_cfg
[i
].num_rxd
- 1;
680 mac_control
->rings
[i
].nic
= nic
;
681 mac_control
->rings
[i
].ring_no
= i
;
683 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
684 (rxd_count
[nic
->rxd_mode
] + 1);
685 /* Allocating all the Rx blocks */
686 for (j
= 0; j
< blk_cnt
; j
++) {
687 struct rx_block_info
*rx_blocks
;
690 rx_blocks
= &mac_control
->rings
[i
].rx_blocks
[j
];
691 size
= SIZE_OF_BLOCK
; //size is always page size
692 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
694 if (tmp_v_addr
== NULL
) {
696 * In case of failure, free_shared_mem()
697 * is called, which should free any
698 * memory that was alloced till the
701 rx_blocks
->block_virt_addr
= tmp_v_addr
;
704 mem_allocated
+= size
;
705 memset(tmp_v_addr
, 0, size
);
706 rx_blocks
->block_virt_addr
= tmp_v_addr
;
707 rx_blocks
->block_dma_addr
= tmp_p_addr
;
708 rx_blocks
->rxds
= kmalloc(sizeof(struct rxd_info
)*
709 rxd_count
[nic
->rxd_mode
],
711 if (!rx_blocks
->rxds
)
714 (sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
715 for (l
=0; l
<rxd_count
[nic
->rxd_mode
];l
++) {
716 rx_blocks
->rxds
[l
].virt_addr
=
717 rx_blocks
->block_virt_addr
+
718 (rxd_size
[nic
->rxd_mode
] * l
);
719 rx_blocks
->rxds
[l
].dma_addr
=
720 rx_blocks
->block_dma_addr
+
721 (rxd_size
[nic
->rxd_mode
] * l
);
724 /* Interlinking all Rx Blocks */
725 for (j
= 0; j
< blk_cnt
; j
++) {
727 mac_control
->rings
[i
].rx_blocks
[j
].block_virt_addr
;
729 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
730 blk_cnt
].block_virt_addr
;
732 mac_control
->rings
[i
].rx_blocks
[j
].block_dma_addr
;
734 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
735 blk_cnt
].block_dma_addr
;
737 pre_rxd_blk
= (struct RxD_block
*) tmp_v_addr
;
738 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
739 (unsigned long) tmp_v_addr_next
;
740 pre_rxd_blk
->pNext_RxD_Blk_physical
=
741 (u64
) tmp_p_addr_next
;
744 if (nic
->rxd_mode
== RXD_MODE_3B
) {
746 * Allocation of Storages for buffer addresses in 2BUFF mode
747 * and the buffers as well.
749 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
750 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
751 (rxd_count
[nic
->rxd_mode
]+ 1);
752 mac_control
->rings
[i
].ba
=
753 kmalloc((sizeof(struct buffAdd
*) * blk_cnt
),
755 if (!mac_control
->rings
[i
].ba
)
757 mem_allocated
+=(sizeof(struct buffAdd
*) * blk_cnt
);
758 for (j
= 0; j
< blk_cnt
; j
++) {
760 mac_control
->rings
[i
].ba
[j
] =
761 kmalloc((sizeof(struct buffAdd
) *
762 (rxd_count
[nic
->rxd_mode
] + 1)),
764 if (!mac_control
->rings
[i
].ba
[j
])
766 mem_allocated
+= (sizeof(struct buffAdd
) * \
767 (rxd_count
[nic
->rxd_mode
] + 1));
768 while (k
!= rxd_count
[nic
->rxd_mode
]) {
769 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
771 ba
->ba_0_org
= (void *) kmalloc
772 (BUF0_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
776 (BUF0_LEN
+ ALIGN_SIZE
);
777 tmp
= (unsigned long)ba
->ba_0_org
;
779 tmp
&= ~((unsigned long) ALIGN_SIZE
);
780 ba
->ba_0
= (void *) tmp
;
782 ba
->ba_1_org
= (void *) kmalloc
783 (BUF1_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
787 += (BUF1_LEN
+ ALIGN_SIZE
);
788 tmp
= (unsigned long) ba
->ba_1_org
;
790 tmp
&= ~((unsigned long) ALIGN_SIZE
);
791 ba
->ba_1
= (void *) tmp
;
798 /* Allocation and initialization of Statistics block */
799 size
= sizeof(struct stat_block
);
800 mac_control
->stats_mem
= pci_alloc_consistent
801 (nic
->pdev
, size
, &mac_control
->stats_mem_phy
);
803 if (!mac_control
->stats_mem
) {
805 * In case of failure, free_shared_mem() is called, which
806 * should free any memory that was alloced till the
811 mem_allocated
+= size
;
812 mac_control
->stats_mem_sz
= size
;
814 tmp_v_addr
= mac_control
->stats_mem
;
815 mac_control
->stats_info
= (struct stat_block
*) tmp_v_addr
;
816 memset(tmp_v_addr
, 0, size
);
817 DBG_PRINT(INIT_DBG
, "%s:Ring Mem PHY: 0x%llx\n", dev
->name
,
818 (unsigned long long) tmp_p_addr
);
819 mac_control
->stats_info
->sw_stat
.mem_allocated
+= mem_allocated
;
824 * free_shared_mem - Free the allocated Memory
825 * @nic: Device private variable.
826 * Description: This function is to free all memory locations allocated by
827 * the init_shared_mem() function and return it to the kernel.
830 static void free_shared_mem(struct s2io_nic
*nic
)
832 int i
, j
, blk_cnt
, size
;
835 dma_addr_t tmp_p_addr
;
836 struct mac_info
*mac_control
;
837 struct config_param
*config
;
838 int lst_size
, lst_per_page
;
839 struct net_device
*dev
;
847 mac_control
= &nic
->mac_control
;
848 config
= &nic
->config
;
850 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
851 lst_per_page
= PAGE_SIZE
/ lst_size
;
853 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
854 ufo_size
+= config
->tx_cfg
[i
].fifo_len
;
855 page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
857 for (j
= 0; j
< page_num
; j
++) {
858 int mem_blks
= (j
* lst_per_page
);
859 if (!mac_control
->fifos
[i
].list_info
)
861 if (!mac_control
->fifos
[i
].list_info
[mem_blks
].
864 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
865 mac_control
->fifos
[i
].
868 mac_control
->fifos
[i
].
871 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
874 /* If we got a zero DMA address during allocation,
877 if (mac_control
->zerodma_virt_addr
) {
878 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
879 mac_control
->zerodma_virt_addr
,
882 "%s: Freeing TxDL with zero DMA addr. ",
884 DBG_PRINT(INIT_DBG
, "Virtual address %p\n",
885 mac_control
->zerodma_virt_addr
);
886 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
889 kfree(mac_control
->fifos
[i
].list_info
);
890 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
891 (nic
->config
.tx_cfg
[i
].fifo_len
*sizeof(struct list_info_hold
));
894 size
= SIZE_OF_BLOCK
;
895 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
896 blk_cnt
= mac_control
->rings
[i
].block_count
;
897 for (j
= 0; j
< blk_cnt
; j
++) {
898 tmp_v_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
900 tmp_p_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
902 if (tmp_v_addr
== NULL
)
904 pci_free_consistent(nic
->pdev
, size
,
905 tmp_v_addr
, tmp_p_addr
);
906 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= size
;
907 kfree(mac_control
->rings
[i
].rx_blocks
[j
].rxds
);
908 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
909 ( sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
913 if (nic
->rxd_mode
== RXD_MODE_3B
) {
914 /* Freeing buffer storage addresses in 2BUFF mode. */
915 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
916 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
917 (rxd_count
[nic
->rxd_mode
] + 1);
918 for (j
= 0; j
< blk_cnt
; j
++) {
920 if (!mac_control
->rings
[i
].ba
[j
])
922 while (k
!= rxd_count
[nic
->rxd_mode
]) {
924 &mac_control
->rings
[i
].ba
[j
][k
];
926 nic
->mac_control
.stats_info
->sw_stat
.\
927 mem_freed
+= (BUF0_LEN
+ ALIGN_SIZE
);
929 nic
->mac_control
.stats_info
->sw_stat
.\
930 mem_freed
+= (BUF1_LEN
+ ALIGN_SIZE
);
933 kfree(mac_control
->rings
[i
].ba
[j
]);
934 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
935 (sizeof(struct buffAdd
) *
936 (rxd_count
[nic
->rxd_mode
] + 1));
938 kfree(mac_control
->rings
[i
].ba
);
939 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
940 (sizeof(struct buffAdd
*) * blk_cnt
);
944 if (mac_control
->stats_mem
) {
945 pci_free_consistent(nic
->pdev
,
946 mac_control
->stats_mem_sz
,
947 mac_control
->stats_mem
,
948 mac_control
->stats_mem_phy
);
949 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
950 mac_control
->stats_mem_sz
;
952 if (nic
->ufo_in_band_v
) {
953 kfree(nic
->ufo_in_band_v
);
954 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
955 += (ufo_size
* sizeof(u64
));
960 * s2io_verify_pci_mode -
963 static int s2io_verify_pci_mode(struct s2io_nic
*nic
)
965 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
966 register u64 val64
= 0;
969 val64
= readq(&bar0
->pci_mode
);
970 mode
= (u8
)GET_PCI_MODE(val64
);
972 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
973 return -1; /* Unknown PCI mode */
977 #define NEC_VENID 0x1033
978 #define NEC_DEVID 0x0125
979 static int s2io_on_nec_bridge(struct pci_dev
*s2io_pdev
)
981 struct pci_dev
*tdev
= NULL
;
982 while ((tdev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, tdev
)) != NULL
) {
983 if (tdev
->vendor
== NEC_VENID
&& tdev
->device
== NEC_DEVID
) {
984 if (tdev
->bus
== s2io_pdev
->bus
->parent
)
992 static int bus_speed
[8] = {33, 133, 133, 200, 266, 133, 200, 266};
994 * s2io_print_pci_mode -
996 static int s2io_print_pci_mode(struct s2io_nic
*nic
)
998 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
999 register u64 val64
= 0;
1001 struct config_param
*config
= &nic
->config
;
1003 val64
= readq(&bar0
->pci_mode
);
1004 mode
= (u8
)GET_PCI_MODE(val64
);
1006 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
1007 return -1; /* Unknown PCI mode */
1009 config
->bus_speed
= bus_speed
[mode
];
1011 if (s2io_on_nec_bridge(nic
->pdev
)) {
1012 DBG_PRINT(ERR_DBG
, "%s: Device is on PCI-E bus\n",
1017 if (val64
& PCI_MODE_32_BITS
) {
1018 DBG_PRINT(ERR_DBG
, "%s: Device is on 32 bit ", nic
->dev
->name
);
1020 DBG_PRINT(ERR_DBG
, "%s: Device is on 64 bit ", nic
->dev
->name
);
1024 case PCI_MODE_PCI_33
:
1025 DBG_PRINT(ERR_DBG
, "33MHz PCI bus\n");
1027 case PCI_MODE_PCI_66
:
1028 DBG_PRINT(ERR_DBG
, "66MHz PCI bus\n");
1030 case PCI_MODE_PCIX_M1_66
:
1031 DBG_PRINT(ERR_DBG
, "66MHz PCIX(M1) bus\n");
1033 case PCI_MODE_PCIX_M1_100
:
1034 DBG_PRINT(ERR_DBG
, "100MHz PCIX(M1) bus\n");
1036 case PCI_MODE_PCIX_M1_133
:
1037 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M1) bus\n");
1039 case PCI_MODE_PCIX_M2_66
:
1040 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M2) bus\n");
1042 case PCI_MODE_PCIX_M2_100
:
1043 DBG_PRINT(ERR_DBG
, "200MHz PCIX(M2) bus\n");
1045 case PCI_MODE_PCIX_M2_133
:
1046 DBG_PRINT(ERR_DBG
, "266MHz PCIX(M2) bus\n");
1049 return -1; /* Unsupported bus speed */
1056 * init_nic - Initialization of hardware
1057 * @nic: device peivate variable
1058 * Description: The function sequentially configures every block
1059 * of the H/W from their reset values.
1060 * Return Value: SUCCESS on success and
1061 * '-1' on failure (endian settings incorrect).
1064 static int init_nic(struct s2io_nic
*nic
)
1066 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1067 struct net_device
*dev
= nic
->dev
;
1068 register u64 val64
= 0;
1072 struct mac_info
*mac_control
;
1073 struct config_param
*config
;
1075 unsigned long long mem_share
;
1078 mac_control
= &nic
->mac_control
;
1079 config
= &nic
->config
;
1081 /* to set the swapper controle on the card */
1082 if(s2io_set_swapper(nic
)) {
1083 DBG_PRINT(ERR_DBG
,"ERROR: Setting Swapper failed\n");
1088 * Herc requires EOI to be removed from reset before XGXS, so..
1090 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1091 val64
= 0xA500000000ULL
;
1092 writeq(val64
, &bar0
->sw_reset
);
1094 val64
= readq(&bar0
->sw_reset
);
1097 /* Remove XGXS from reset state */
1099 writeq(val64
, &bar0
->sw_reset
);
1101 val64
= readq(&bar0
->sw_reset
);
1103 /* Enable Receiving broadcasts */
1104 add
= &bar0
->mac_cfg
;
1105 val64
= readq(&bar0
->mac_cfg
);
1106 val64
|= MAC_RMAC_BCAST_ENABLE
;
1107 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1108 writel((u32
) val64
, add
);
1109 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1110 writel((u32
) (val64
>> 32), (add
+ 4));
1112 /* Read registers in all blocks */
1113 val64
= readq(&bar0
->mac_int_mask
);
1114 val64
= readq(&bar0
->mc_int_mask
);
1115 val64
= readq(&bar0
->xgxs_int_mask
);
1119 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
1121 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1122 while (herc_act_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1123 SPECIAL_REG_WRITE(herc_act_dtx_cfg
[dtx_cnt
],
1124 &bar0
->dtx_control
, UF
);
1126 msleep(1); /* Necessary!! */
1130 while (xena_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1131 SPECIAL_REG_WRITE(xena_dtx_cfg
[dtx_cnt
],
1132 &bar0
->dtx_control
, UF
);
1133 val64
= readq(&bar0
->dtx_control
);
1138 /* Tx DMA Initialization */
1140 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1141 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1142 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1143 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1146 for (i
= 0, j
= 0; i
< config
->tx_fifo_num
; i
++) {
1148 vBIT(config
->tx_cfg
[i
].fifo_len
- 1, ((i
* 32) + 19),
1149 13) | vBIT(config
->tx_cfg
[i
].fifo_priority
,
1152 if (i
== (config
->tx_fifo_num
- 1)) {
1159 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1163 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1167 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1171 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1177 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1178 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1180 if ((nic
->device_type
== XFRAME_I_DEVICE
) &&
1181 (nic
->pdev
->revision
< 4))
1182 writeq(PCC_ENABLE_FOUR
, &bar0
->pcc_enable
);
1184 val64
= readq(&bar0
->tx_fifo_partition_0
);
1185 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
1186 &bar0
->tx_fifo_partition_0
, (unsigned long long) val64
);
1189 * Initialization of Tx_PA_CONFIG register to ignore packet
1190 * integrity checking.
1192 val64
= readq(&bar0
->tx_pa_cfg
);
1193 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
| TX_PA_CFG_IGNORE_SNAP_OUI
|
1194 TX_PA_CFG_IGNORE_LLC_CTRL
| TX_PA_CFG_IGNORE_L2_ERR
;
1195 writeq(val64
, &bar0
->tx_pa_cfg
);
1197 /* Rx DMA intialization. */
1199 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1201 vBIT(config
->rx_cfg
[i
].ring_priority
, (5 + (i
* 8)),
1204 writeq(val64
, &bar0
->rx_queue_priority
);
1207 * Allocating equal share of memory to all the
1211 if (nic
->device_type
& XFRAME_II_DEVICE
)
1216 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1219 mem_share
= (mem_size
/ config
->rx_ring_num
+
1220 mem_size
% config
->rx_ring_num
);
1221 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
1224 mem_share
= (mem_size
/ config
->rx_ring_num
);
1225 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
1228 mem_share
= (mem_size
/ config
->rx_ring_num
);
1229 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
1232 mem_share
= (mem_size
/ config
->rx_ring_num
);
1233 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
1236 mem_share
= (mem_size
/ config
->rx_ring_num
);
1237 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
1240 mem_share
= (mem_size
/ config
->rx_ring_num
);
1241 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
1244 mem_share
= (mem_size
/ config
->rx_ring_num
);
1245 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
1248 mem_share
= (mem_size
/ config
->rx_ring_num
);
1249 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
1253 writeq(val64
, &bar0
->rx_queue_cfg
);
1256 * Filling Tx round robin registers
1257 * as per the number of FIFOs
1259 switch (config
->tx_fifo_num
) {
1261 val64
= 0x0000000000000000ULL
;
1262 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1263 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1264 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1265 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1266 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1269 val64
= 0x0000010000010000ULL
;
1270 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1271 val64
= 0x0100000100000100ULL
;
1272 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1273 val64
= 0x0001000001000001ULL
;
1274 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1275 val64
= 0x0000010000010000ULL
;
1276 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1277 val64
= 0x0100000000000000ULL
;
1278 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1281 val64
= 0x0001000102000001ULL
;
1282 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1283 val64
= 0x0001020000010001ULL
;
1284 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1285 val64
= 0x0200000100010200ULL
;
1286 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1287 val64
= 0x0001000102000001ULL
;
1288 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1289 val64
= 0x0001020000000000ULL
;
1290 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1293 val64
= 0x0001020300010200ULL
;
1294 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1295 val64
= 0x0100000102030001ULL
;
1296 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1297 val64
= 0x0200010000010203ULL
;
1298 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1299 val64
= 0x0001020001000001ULL
;
1300 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1301 val64
= 0x0203000100000000ULL
;
1302 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1305 val64
= 0x0001000203000102ULL
;
1306 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1307 val64
= 0x0001020001030004ULL
;
1308 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1309 val64
= 0x0001000203000102ULL
;
1310 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1311 val64
= 0x0001020001030004ULL
;
1312 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1313 val64
= 0x0001000000000000ULL
;
1314 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1317 val64
= 0x0001020304000102ULL
;
1318 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1319 val64
= 0x0304050001020001ULL
;
1320 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1321 val64
= 0x0203000100000102ULL
;
1322 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1323 val64
= 0x0304000102030405ULL
;
1324 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1325 val64
= 0x0001000200000000ULL
;
1326 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1329 val64
= 0x0001020001020300ULL
;
1330 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1331 val64
= 0x0102030400010203ULL
;
1332 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1333 val64
= 0x0405060001020001ULL
;
1334 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1335 val64
= 0x0304050000010200ULL
;
1336 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1337 val64
= 0x0102030000000000ULL
;
1338 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1341 val64
= 0x0001020300040105ULL
;
1342 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1343 val64
= 0x0200030106000204ULL
;
1344 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1345 val64
= 0x0103000502010007ULL
;
1346 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1347 val64
= 0x0304010002060500ULL
;
1348 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1349 val64
= 0x0103020400000000ULL
;
1350 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1354 /* Enable all configured Tx FIFO partitions */
1355 val64
= readq(&bar0
->tx_fifo_partition_0
);
1356 val64
|= (TX_FIFO_PARTITION_EN
);
1357 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1359 /* Filling the Rx round robin registers as per the
1360 * number of Rings and steering based on QoS.
1362 switch (config
->rx_ring_num
) {
1364 val64
= 0x8080808080808080ULL
;
1365 writeq(val64
, &bar0
->rts_qos_steering
);
1368 val64
= 0x0000010000010000ULL
;
1369 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1370 val64
= 0x0100000100000100ULL
;
1371 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1372 val64
= 0x0001000001000001ULL
;
1373 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1374 val64
= 0x0000010000010000ULL
;
1375 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1376 val64
= 0x0100000000000000ULL
;
1377 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1379 val64
= 0x8080808040404040ULL
;
1380 writeq(val64
, &bar0
->rts_qos_steering
);
1383 val64
= 0x0001000102000001ULL
;
1384 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1385 val64
= 0x0001020000010001ULL
;
1386 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1387 val64
= 0x0200000100010200ULL
;
1388 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1389 val64
= 0x0001000102000001ULL
;
1390 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1391 val64
= 0x0001020000000000ULL
;
1392 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1394 val64
= 0x8080804040402020ULL
;
1395 writeq(val64
, &bar0
->rts_qos_steering
);
1398 val64
= 0x0001020300010200ULL
;
1399 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1400 val64
= 0x0100000102030001ULL
;
1401 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1402 val64
= 0x0200010000010203ULL
;
1403 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1404 val64
= 0x0001020001000001ULL
;
1405 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1406 val64
= 0x0203000100000000ULL
;
1407 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1409 val64
= 0x8080404020201010ULL
;
1410 writeq(val64
, &bar0
->rts_qos_steering
);
1413 val64
= 0x0001000203000102ULL
;
1414 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1415 val64
= 0x0001020001030004ULL
;
1416 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1417 val64
= 0x0001000203000102ULL
;
1418 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1419 val64
= 0x0001020001030004ULL
;
1420 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1421 val64
= 0x0001000000000000ULL
;
1422 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1424 val64
= 0x8080404020201008ULL
;
1425 writeq(val64
, &bar0
->rts_qos_steering
);
1428 val64
= 0x0001020304000102ULL
;
1429 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1430 val64
= 0x0304050001020001ULL
;
1431 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1432 val64
= 0x0203000100000102ULL
;
1433 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1434 val64
= 0x0304000102030405ULL
;
1435 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1436 val64
= 0x0001000200000000ULL
;
1437 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1439 val64
= 0x8080404020100804ULL
;
1440 writeq(val64
, &bar0
->rts_qos_steering
);
1443 val64
= 0x0001020001020300ULL
;
1444 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1445 val64
= 0x0102030400010203ULL
;
1446 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1447 val64
= 0x0405060001020001ULL
;
1448 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1449 val64
= 0x0304050000010200ULL
;
1450 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1451 val64
= 0x0102030000000000ULL
;
1452 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1454 val64
= 0x8080402010080402ULL
;
1455 writeq(val64
, &bar0
->rts_qos_steering
);
1458 val64
= 0x0001020300040105ULL
;
1459 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1460 val64
= 0x0200030106000204ULL
;
1461 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1462 val64
= 0x0103000502010007ULL
;
1463 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1464 val64
= 0x0304010002060500ULL
;
1465 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1466 val64
= 0x0103020400000000ULL
;
1467 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1469 val64
= 0x8040201008040201ULL
;
1470 writeq(val64
, &bar0
->rts_qos_steering
);
1476 for (i
= 0; i
< 8; i
++)
1477 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1479 /* Set the default rts frame length for the rings configured */
1480 val64
= MAC_RTS_FRM_LEN_SET(dev
->mtu
+22);
1481 for (i
= 0 ; i
< config
->rx_ring_num
; i
++)
1482 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1484 /* Set the frame length for the configured rings
1485 * desired by the user
1487 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1488 /* If rts_frm_len[i] == 0 then it is assumed that user not
1489 * specified frame length steering.
1490 * If the user provides the frame length then program
1491 * the rts_frm_len register for those values or else
1492 * leave it as it is.
1494 if (rts_frm_len
[i
] != 0) {
1495 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len
[i
]),
1496 &bar0
->rts_frm_len_n
[i
]);
1500 /* Disable differentiated services steering logic */
1501 for (i
= 0; i
< 64; i
++) {
1502 if (rts_ds_steer(nic
, i
, 0) == FAILURE
) {
1503 DBG_PRINT(ERR_DBG
, "%s: failed rts ds steering",
1505 DBG_PRINT(ERR_DBG
, "set on codepoint %d\n", i
);
1510 /* Program statistics memory */
1511 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
1513 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1514 val64
= STAT_BC(0x320);
1515 writeq(val64
, &bar0
->stat_byte_cnt
);
1519 * Initializing the sampling rate for the device to calculate the
1520 * bandwidth utilization.
1522 val64
= MAC_TX_LINK_UTIL_VAL(tmac_util_period
) |
1523 MAC_RX_LINK_UTIL_VAL(rmac_util_period
);
1524 writeq(val64
, &bar0
->mac_link_util
);
1528 * Initializing the Transmit and Receive Traffic Interrupt
1532 * TTI Initialization. Default Tx timer gets us about
1533 * 250 interrupts per sec. Continuous interrupts are enabled
1536 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1537 int count
= (nic
->config
.bus_speed
* 125)/2;
1538 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(count
);
1541 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1543 val64
|= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1544 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1545 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN
;
1546 if (use_continuous_tx_intrs
)
1547 val64
|= TTI_DATA1_MEM_TX_TIMER_CI_EN
;
1548 writeq(val64
, &bar0
->tti_data1_mem
);
1550 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1551 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1552 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1553 writeq(val64
, &bar0
->tti_data2_mem
);
1555 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1556 writeq(val64
, &bar0
->tti_command_mem
);
1559 * Once the operation completes, the Strobe bit of the command
1560 * register will be reset. We poll for this particular condition
1561 * We wait for a maximum of 500ms for the operation to complete,
1562 * if it's not complete by then we return error.
1566 val64
= readq(&bar0
->tti_command_mem
);
1567 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1571 DBG_PRINT(ERR_DBG
, "%s: TTI init Failed\n",
1579 /* RTI Initialization */
1580 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1582 * Programmed to generate Apprx 500 Intrs per
1585 int count
= (nic
->config
.bus_speed
* 125)/4;
1586 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(count
);
1588 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1589 val64
|= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1590 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1591 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN
;
1593 writeq(val64
, &bar0
->rti_data1_mem
);
1595 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) |
1596 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1597 if (nic
->config
.intr_type
== MSI_X
)
1598 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1599 RTI_DATA2_MEM_RX_UFC_D(0x40));
1601 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1602 RTI_DATA2_MEM_RX_UFC_D(0x80));
1603 writeq(val64
, &bar0
->rti_data2_mem
);
1605 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1606 val64
= RTI_CMD_MEM_WE
| RTI_CMD_MEM_STROBE_NEW_CMD
1607 | RTI_CMD_MEM_OFFSET(i
);
1608 writeq(val64
, &bar0
->rti_command_mem
);
1611 * Once the operation completes, the Strobe bit of the
1612 * command register will be reset. We poll for this
1613 * particular condition. We wait for a maximum of 500ms
1614 * for the operation to complete, if it's not complete
1615 * by then we return error.
1619 val64
= readq(&bar0
->rti_command_mem
);
1620 if (!(val64
& RTI_CMD_MEM_STROBE_NEW_CMD
))
1624 DBG_PRINT(ERR_DBG
, "%s: RTI init Failed\n",
1634 * Initializing proper values as Pause threshold into all
1635 * the 8 Queues on Rx side.
1637 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
1638 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
1640 /* Disable RMAC PAD STRIPPING */
1641 add
= &bar0
->mac_cfg
;
1642 val64
= readq(&bar0
->mac_cfg
);
1643 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
1644 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1645 writel((u32
) (val64
), add
);
1646 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1647 writel((u32
) (val64
>> 32), (add
+ 4));
1648 val64
= readq(&bar0
->mac_cfg
);
1650 /* Enable FCS stripping by adapter */
1651 add
= &bar0
->mac_cfg
;
1652 val64
= readq(&bar0
->mac_cfg
);
1653 val64
|= MAC_CFG_RMAC_STRIP_FCS
;
1654 if (nic
->device_type
== XFRAME_II_DEVICE
)
1655 writeq(val64
, &bar0
->mac_cfg
);
1657 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1658 writel((u32
) (val64
), add
);
1659 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1660 writel((u32
) (val64
>> 32), (add
+ 4));
1664 * Set the time value to be inserted in the pause frame
1665 * generated by xena.
1667 val64
= readq(&bar0
->rmac_pause_cfg
);
1668 val64
&= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1669 val64
|= RMAC_PAUSE_HG_PTIME(nic
->mac_control
.rmac_pause_time
);
1670 writeq(val64
, &bar0
->rmac_pause_cfg
);
1673 * Set the Threshold Limit for Generating the pause frame
1674 * If the amount of data in any Queue exceeds ratio of
1675 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1676 * pause frame is generated
1679 for (i
= 0; i
< 4; i
++) {
1681 (((u64
) 0xFF00 | nic
->mac_control
.
1682 mc_pause_threshold_q0q3
)
1685 writeq(val64
, &bar0
->mc_pause_thresh_q0q3
);
1688 for (i
= 0; i
< 4; i
++) {
1690 (((u64
) 0xFF00 | nic
->mac_control
.
1691 mc_pause_threshold_q4q7
)
1694 writeq(val64
, &bar0
->mc_pause_thresh_q4q7
);
1697 * TxDMA will stop Read request if the number of read split has
1698 * exceeded the limit pointed by shared_splits
1700 val64
= readq(&bar0
->pic_control
);
1701 val64
|= PIC_CNTL_SHARED_SPLITS(shared_splits
);
1702 writeq(val64
, &bar0
->pic_control
);
1704 if (nic
->config
.bus_speed
== 266) {
1705 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN
, &bar0
->txreqtimeout
);
1706 writeq(0x0, &bar0
->read_retry_delay
);
1707 writeq(0x0, &bar0
->write_retry_delay
);
1711 * Programming the Herc to split every write transaction
1712 * that does not start on an ADB to reduce disconnects.
1714 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1715 val64
= FAULT_BEHAVIOUR
| EXT_REQ_EN
|
1716 MISC_LINK_STABILITY_PRD(3);
1717 writeq(val64
, &bar0
->misc_control
);
1718 val64
= readq(&bar0
->pic_control2
);
1719 val64
&= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1720 writeq(val64
, &bar0
->pic_control2
);
1722 if (strstr(nic
->product_name
, "CX4")) {
1723 val64
= TMAC_AVG_IPG(0x17);
1724 writeq(val64
, &bar0
->tmac_avg_ipg
);
1729 #define LINK_UP_DOWN_INTERRUPT 1
1730 #define MAC_RMAC_ERR_TIMER 2
1732 static int s2io_link_fault_indication(struct s2io_nic
*nic
)
1734 if (nic
->config
.intr_type
!= INTA
)
1735 return MAC_RMAC_ERR_TIMER
;
1736 if (nic
->device_type
== XFRAME_II_DEVICE
)
1737 return LINK_UP_DOWN_INTERRUPT
;
1739 return MAC_RMAC_ERR_TIMER
;
1743 * do_s2io_write_bits - update alarm bits in alarm register
1744 * @value: alarm bits
1745 * @flag: interrupt status
1746 * @addr: address value
1747 * Description: update alarm bits in alarm register
1751 static void do_s2io_write_bits(u64 value
, int flag
, void __iomem
*addr
)
1755 temp64
= readq(addr
);
1757 if(flag
== ENABLE_INTRS
)
1758 temp64
&= ~((u64
) value
);
1760 temp64
|= ((u64
) value
);
1761 writeq(temp64
, addr
);
1764 static void en_dis_err_alarms(struct s2io_nic
*nic
, u16 mask
, int flag
)
1766 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1767 register u64 gen_int_mask
= 0;
1769 if (mask
& TX_DMA_INTR
) {
1771 gen_int_mask
|= TXDMA_INT_M
;
1773 do_s2io_write_bits(TXDMA_TDA_INT
| TXDMA_PFC_INT
|
1774 TXDMA_PCC_INT
| TXDMA_TTI_INT
|
1775 TXDMA_LSO_INT
| TXDMA_TPA_INT
|
1776 TXDMA_SM_INT
, flag
, &bar0
->txdma_int_mask
);
1778 do_s2io_write_bits(PFC_ECC_DB_ERR
| PFC_SM_ERR_ALARM
|
1779 PFC_MISC_0_ERR
| PFC_MISC_1_ERR
|
1780 PFC_PCIX_ERR
| PFC_ECC_SG_ERR
, flag
,
1781 &bar0
->pfc_err_mask
);
1783 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR
| TDA_SM0_ERR_ALARM
|
1784 TDA_SM1_ERR_ALARM
| TDA_Fn_ECC_SG_ERR
|
1785 TDA_PCIX_ERR
, flag
, &bar0
->tda_err_mask
);
1787 do_s2io_write_bits(PCC_FB_ECC_DB_ERR
| PCC_TXB_ECC_DB_ERR
|
1788 PCC_SM_ERR_ALARM
| PCC_WR_ERR_ALARM
|
1789 PCC_N_SERR
| PCC_6_COF_OV_ERR
|
1790 PCC_7_COF_OV_ERR
| PCC_6_LSO_OV_ERR
|
1791 PCC_7_LSO_OV_ERR
| PCC_FB_ECC_SG_ERR
|
1792 PCC_TXB_ECC_SG_ERR
, flag
, &bar0
->pcc_err_mask
);
1794 do_s2io_write_bits(TTI_SM_ERR_ALARM
| TTI_ECC_SG_ERR
|
1795 TTI_ECC_DB_ERR
, flag
, &bar0
->tti_err_mask
);
1797 do_s2io_write_bits(LSO6_ABORT
| LSO7_ABORT
|
1798 LSO6_SM_ERR_ALARM
| LSO7_SM_ERR_ALARM
|
1799 LSO6_SEND_OFLOW
| LSO7_SEND_OFLOW
,
1800 flag
, &bar0
->lso_err_mask
);
1802 do_s2io_write_bits(TPA_SM_ERR_ALARM
| TPA_TX_FRM_DROP
,
1803 flag
, &bar0
->tpa_err_mask
);
1805 do_s2io_write_bits(SM_SM_ERR_ALARM
, flag
, &bar0
->sm_err_mask
);
1809 if (mask
& TX_MAC_INTR
) {
1810 gen_int_mask
|= TXMAC_INT_M
;
1811 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT
, flag
,
1812 &bar0
->mac_int_mask
);
1813 do_s2io_write_bits(TMAC_TX_BUF_OVRN
| TMAC_TX_SM_ERR
|
1814 TMAC_ECC_SG_ERR
| TMAC_ECC_DB_ERR
|
1815 TMAC_DESC_ECC_SG_ERR
| TMAC_DESC_ECC_DB_ERR
,
1816 flag
, &bar0
->mac_tmac_err_mask
);
1819 if (mask
& TX_XGXS_INTR
) {
1820 gen_int_mask
|= TXXGXS_INT_M
;
1821 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS
, flag
,
1822 &bar0
->xgxs_int_mask
);
1823 do_s2io_write_bits(TXGXS_ESTORE_UFLOW
| TXGXS_TX_SM_ERR
|
1824 TXGXS_ECC_SG_ERR
| TXGXS_ECC_DB_ERR
,
1825 flag
, &bar0
->xgxs_txgxs_err_mask
);
1828 if (mask
& RX_DMA_INTR
) {
1829 gen_int_mask
|= RXDMA_INT_M
;
1830 do_s2io_write_bits(RXDMA_INT_RC_INT_M
| RXDMA_INT_RPA_INT_M
|
1831 RXDMA_INT_RDA_INT_M
| RXDMA_INT_RTI_INT_M
,
1832 flag
, &bar0
->rxdma_int_mask
);
1833 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR
| RC_FTC_ECC_DB_ERR
|
1834 RC_PRCn_SM_ERR_ALARM
| RC_FTC_SM_ERR_ALARM
|
1835 RC_PRCn_ECC_SG_ERR
| RC_FTC_ECC_SG_ERR
|
1836 RC_RDA_FAIL_WR_Rn
, flag
, &bar0
->rc_err_mask
);
1837 do_s2io_write_bits(PRC_PCI_AB_RD_Rn
| PRC_PCI_AB_WR_Rn
|
1838 PRC_PCI_AB_F_WR_Rn
| PRC_PCI_DP_RD_Rn
|
1839 PRC_PCI_DP_WR_Rn
| PRC_PCI_DP_F_WR_Rn
, flag
,
1840 &bar0
->prc_pcix_err_mask
);
1841 do_s2io_write_bits(RPA_SM_ERR_ALARM
| RPA_CREDIT_ERR
|
1842 RPA_ECC_SG_ERR
| RPA_ECC_DB_ERR
, flag
,
1843 &bar0
->rpa_err_mask
);
1844 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR
| RDA_FRM_ECC_DB_N_AERR
|
1845 RDA_SM1_ERR_ALARM
| RDA_SM0_ERR_ALARM
|
1846 RDA_RXD_ECC_DB_SERR
| RDA_RXDn_ECC_SG_ERR
|
1847 RDA_FRM_ECC_SG_ERR
| RDA_MISC_ERR
|RDA_PCIX_ERR
,
1848 flag
, &bar0
->rda_err_mask
);
1849 do_s2io_write_bits(RTI_SM_ERR_ALARM
|
1850 RTI_ECC_SG_ERR
| RTI_ECC_DB_ERR
,
1851 flag
, &bar0
->rti_err_mask
);
1854 if (mask
& RX_MAC_INTR
) {
1855 gen_int_mask
|= RXMAC_INT_M
;
1856 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT
, flag
,
1857 &bar0
->mac_int_mask
);
1858 do_s2io_write_bits(RMAC_RX_BUFF_OVRN
| RMAC_RX_SM_ERR
|
1859 RMAC_UNUSED_INT
| RMAC_SINGLE_ECC_ERR
|
1860 RMAC_DOUBLE_ECC_ERR
|
1861 RMAC_LINK_STATE_CHANGE_INT
,
1862 flag
, &bar0
->mac_rmac_err_mask
);
1865 if (mask
& RX_XGXS_INTR
)
1867 gen_int_mask
|= RXXGXS_INT_M
;
1868 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS
, flag
,
1869 &bar0
->xgxs_int_mask
);
1870 do_s2io_write_bits(RXGXS_ESTORE_OFLOW
| RXGXS_RX_SM_ERR
, flag
,
1871 &bar0
->xgxs_rxgxs_err_mask
);
1874 if (mask
& MC_INTR
) {
1875 gen_int_mask
|= MC_INT_M
;
1876 do_s2io_write_bits(MC_INT_MASK_MC_INT
, flag
, &bar0
->mc_int_mask
);
1877 do_s2io_write_bits(MC_ERR_REG_SM_ERR
| MC_ERR_REG_ECC_ALL_SNG
|
1878 MC_ERR_REG_ECC_ALL_DBL
| PLL_LOCK_N
, flag
,
1879 &bar0
->mc_err_mask
);
1881 nic
->general_int_mask
= gen_int_mask
;
1883 /* Remove this line when alarm interrupts are enabled */
1884 nic
->general_int_mask
= 0;
1887 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1888 * @nic: device private variable,
1889 * @mask: A mask indicating which Intr block must be modified and,
1890 * @flag: A flag indicating whether to enable or disable the Intrs.
1891 * Description: This function will either disable or enable the interrupts
1892 * depending on the flag argument. The mask argument can be used to
1893 * enable/disable any Intr block.
1894 * Return Value: NONE.
1897 static void en_dis_able_nic_intrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
1899 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1900 register u64 temp64
= 0, intr_mask
= 0;
1902 intr_mask
= nic
->general_int_mask
;
1904 /* Top level interrupt classification */
1905 /* PIC Interrupts */
1906 if (mask
& TX_PIC_INTR
) {
1907 /* Enable PIC Intrs in the general intr mask register */
1908 intr_mask
|= TXPIC_INT_M
;
1909 if (flag
== ENABLE_INTRS
) {
1911 * If Hercules adapter enable GPIO otherwise
1912 * disable all PCIX, Flash, MDIO, IIC and GPIO
1913 * interrupts for now.
1916 if (s2io_link_fault_indication(nic
) ==
1917 LINK_UP_DOWN_INTERRUPT
) {
1918 do_s2io_write_bits(PIC_INT_GPIO
, flag
,
1919 &bar0
->pic_int_mask
);
1920 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP
, flag
,
1921 &bar0
->gpio_int_mask
);
1923 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1924 } else if (flag
== DISABLE_INTRS
) {
1926 * Disable PIC Intrs in the general
1927 * intr mask register
1929 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1933 /* Tx traffic interrupts */
1934 if (mask
& TX_TRAFFIC_INTR
) {
1935 intr_mask
|= TXTRAFFIC_INT_M
;
1936 if (flag
== ENABLE_INTRS
) {
1938 * Enable all the Tx side interrupts
1939 * writing 0 Enables all 64 TX interrupt levels
1941 writeq(0x0, &bar0
->tx_traffic_mask
);
1942 } else if (flag
== DISABLE_INTRS
) {
1944 * Disable Tx Traffic Intrs in the general intr mask
1947 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
1951 /* Rx traffic interrupts */
1952 if (mask
& RX_TRAFFIC_INTR
) {
1953 intr_mask
|= RXTRAFFIC_INT_M
;
1954 if (flag
== ENABLE_INTRS
) {
1955 /* writing 0 Enables all 8 RX interrupt levels */
1956 writeq(0x0, &bar0
->rx_traffic_mask
);
1957 } else if (flag
== DISABLE_INTRS
) {
1959 * Disable Rx Traffic Intrs in the general intr mask
1962 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
1966 temp64
= readq(&bar0
->general_int_mask
);
1967 if (flag
== ENABLE_INTRS
)
1968 temp64
&= ~((u64
) intr_mask
);
1970 temp64
= DISABLE_ALL_INTRS
;
1971 writeq(temp64
, &bar0
->general_int_mask
);
1973 nic
->general_int_mask
= readq(&bar0
->general_int_mask
);
1977 * verify_pcc_quiescent- Checks for PCC quiescent state
1978 * Return: 1 If PCC is quiescence
1979 * 0 If PCC is not quiescence
1981 static int verify_pcc_quiescent(struct s2io_nic
*sp
, int flag
)
1984 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1985 u64 val64
= readq(&bar0
->adapter_status
);
1987 herc
= (sp
->device_type
== XFRAME_II_DEVICE
);
1989 if (flag
== FALSE
) {
1990 if ((!herc
&& (sp
->pdev
->revision
>= 4)) || herc
) {
1991 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
))
1994 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
1998 if ((!herc
&& (sp
->pdev
->revision
>= 4)) || herc
) {
1999 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
2000 ADAPTER_STATUS_RMAC_PCC_IDLE
))
2003 if (((val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) ==
2004 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
2012 * verify_xena_quiescence - Checks whether the H/W is ready
2013 * Description: Returns whether the H/W is ready to go or not. Depending
2014 * on whether adapter enable bit was written or not the comparison
2015 * differs and the calling function passes the input argument flag to
2017 * Return: 1 If xena is quiescence
2018 * 0 If Xena is not quiescence
2021 static int verify_xena_quiescence(struct s2io_nic
*sp
)
2024 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2025 u64 val64
= readq(&bar0
->adapter_status
);
2026 mode
= s2io_verify_pci_mode(sp
);
2028 if (!(val64
& ADAPTER_STATUS_TDMA_READY
)) {
2029 DBG_PRINT(ERR_DBG
, "%s", "TDMA is not ready!");
2032 if (!(val64
& ADAPTER_STATUS_RDMA_READY
)) {
2033 DBG_PRINT(ERR_DBG
, "%s", "RDMA is not ready!");
2036 if (!(val64
& ADAPTER_STATUS_PFC_READY
)) {
2037 DBG_PRINT(ERR_DBG
, "%s", "PFC is not ready!");
2040 if (!(val64
& ADAPTER_STATUS_TMAC_BUF_EMPTY
)) {
2041 DBG_PRINT(ERR_DBG
, "%s", "TMAC BUF is not empty!");
2044 if (!(val64
& ADAPTER_STATUS_PIC_QUIESCENT
)) {
2045 DBG_PRINT(ERR_DBG
, "%s", "PIC is not QUIESCENT!");
2048 if (!(val64
& ADAPTER_STATUS_MC_DRAM_READY
)) {
2049 DBG_PRINT(ERR_DBG
, "%s", "MC_DRAM is not ready!");
2052 if (!(val64
& ADAPTER_STATUS_MC_QUEUES_READY
)) {
2053 DBG_PRINT(ERR_DBG
, "%s", "MC_QUEUES is not ready!");
2056 if (!(val64
& ADAPTER_STATUS_M_PLL_LOCK
)) {
2057 DBG_PRINT(ERR_DBG
, "%s", "M_PLL is not locked!");
2062 * In PCI 33 mode, the P_PLL is not used, and therefore,
2063 * the the P_PLL_LOCK bit in the adapter_status register will
2066 if (!(val64
& ADAPTER_STATUS_P_PLL_LOCK
) &&
2067 sp
->device_type
== XFRAME_II_DEVICE
&& mode
!=
2069 DBG_PRINT(ERR_DBG
, "%s", "P_PLL is not locked!");
2072 if (!((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
2073 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
2074 DBG_PRINT(ERR_DBG
, "%s", "RC_PRC is not QUIESCENT!");
2081 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2082 * @sp: Pointer to device specifc structure
2084 * New procedure to clear mac address reading problems on Alpha platforms
2088 static void fix_mac_address(struct s2io_nic
* sp
)
2090 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2094 while (fix_mac
[i
] != END_SIGN
) {
2095 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
2097 val64
= readq(&bar0
->gpio_control
);
2102 * start_nic - Turns the device on
2103 * @nic : device private variable.
2105 * This function actually turns the device on. Before this function is
2106 * called,all Registers are configured from their reset states
2107 * and shared memory is allocated but the NIC is still quiescent. On
2108 * calling this function, the device interrupts are cleared and the NIC is
2109 * literally switched on by writing into the adapter control register.
2111 * SUCCESS on success and -1 on failure.
2114 static int start_nic(struct s2io_nic
*nic
)
2116 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2117 struct net_device
*dev
= nic
->dev
;
2118 register u64 val64
= 0;
2120 struct mac_info
*mac_control
;
2121 struct config_param
*config
;
2123 mac_control
= &nic
->mac_control
;
2124 config
= &nic
->config
;
2126 /* PRC Initialization and configuration */
2127 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2128 writeq((u64
) mac_control
->rings
[i
].rx_blocks
[0].block_dma_addr
,
2129 &bar0
->prc_rxd0_n
[i
]);
2131 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
2132 if (nic
->rxd_mode
== RXD_MODE_1
)
2133 val64
|= PRC_CTRL_RC_ENABLED
;
2135 val64
|= PRC_CTRL_RC_ENABLED
| PRC_CTRL_RING_MODE_3
;
2136 if (nic
->device_type
== XFRAME_II_DEVICE
)
2137 val64
|= PRC_CTRL_GROUP_READS
;
2138 val64
&= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2139 val64
|= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2140 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
2143 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2144 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2145 val64
= readq(&bar0
->rx_pa_cfg
);
2146 val64
|= RX_PA_CFG_IGNORE_L2_ERR
;
2147 writeq(val64
, &bar0
->rx_pa_cfg
);
2150 if (vlan_tag_strip
== 0) {
2151 val64
= readq(&bar0
->rx_pa_cfg
);
2152 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
2153 writeq(val64
, &bar0
->rx_pa_cfg
);
2154 vlan_strip_flag
= 0;
2158 * Enabling MC-RLDRAM. After enabling the device, we timeout
2159 * for around 100ms, which is approximately the time required
2160 * for the device to be ready for operation.
2162 val64
= readq(&bar0
->mc_rldram_mrs
);
2163 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
2164 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
2165 val64
= readq(&bar0
->mc_rldram_mrs
);
2167 msleep(100); /* Delay by around 100 ms. */
2169 /* Enabling ECC Protection. */
2170 val64
= readq(&bar0
->adapter_control
);
2171 val64
&= ~ADAPTER_ECC_EN
;
2172 writeq(val64
, &bar0
->adapter_control
);
2175 * Verify if the device is ready to be enabled, if so enable
2178 val64
= readq(&bar0
->adapter_status
);
2179 if (!verify_xena_quiescence(nic
)) {
2180 DBG_PRINT(ERR_DBG
, "%s: device is not ready, ", dev
->name
);
2181 DBG_PRINT(ERR_DBG
, "Adapter status reads: 0x%llx\n",
2182 (unsigned long long) val64
);
2187 * With some switches, link might be already up at this point.
2188 * Because of this weird behavior, when we enable laser,
2189 * we may not get link. We need to handle this. We cannot
2190 * figure out which switch is misbehaving. So we are forced to
2191 * make a global change.
2194 /* Enabling Laser. */
2195 val64
= readq(&bar0
->adapter_control
);
2196 val64
|= ADAPTER_EOI_TX_ON
;
2197 writeq(val64
, &bar0
->adapter_control
);
2199 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
2201 * Dont see link state interrupts initally on some switches,
2202 * so directly scheduling the link state task here.
2204 schedule_work(&nic
->set_link_task
);
2206 /* SXE-002: Initialize link and activity LED */
2207 subid
= nic
->pdev
->subsystem_device
;
2208 if (((subid
& 0xFF) >= 0x07) &&
2209 (nic
->device_type
== XFRAME_I_DEVICE
)) {
2210 val64
= readq(&bar0
->gpio_control
);
2211 val64
|= 0x0000800000000000ULL
;
2212 writeq(val64
, &bar0
->gpio_control
);
2213 val64
= 0x0411040400000000ULL
;
2214 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
2220 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2222 static struct sk_buff
*s2io_txdl_getskb(struct fifo_info
*fifo_data
, struct \
2223 TxD
*txdlp
, int get_off
)
2225 struct s2io_nic
*nic
= fifo_data
->nic
;
2226 struct sk_buff
*skb
;
2231 if (txds
->Host_Control
== (u64
)(long)nic
->ufo_in_band_v
) {
2232 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2233 txds
->Buffer_Pointer
, sizeof(u64
),
2238 skb
= (struct sk_buff
*) ((unsigned long)
2239 txds
->Host_Control
);
2241 memset(txdlp
, 0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2244 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2245 txds
->Buffer_Pointer
,
2246 skb
->len
- skb
->data_len
,
2248 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2251 for (j
= 0; j
< frg_cnt
; j
++, txds
++) {
2252 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
2253 if (!txds
->Buffer_Pointer
)
2255 pci_unmap_page(nic
->pdev
, (dma_addr_t
)
2256 txds
->Buffer_Pointer
,
2257 frag
->size
, PCI_DMA_TODEVICE
);
2260 memset(txdlp
,0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2265 * free_tx_buffers - Free all queued Tx buffers
2266 * @nic : device private variable.
2268 * Free all queued Tx buffers.
2269 * Return Value: void
2272 static void free_tx_buffers(struct s2io_nic
*nic
)
2274 struct net_device
*dev
= nic
->dev
;
2275 struct sk_buff
*skb
;
2278 struct mac_info
*mac_control
;
2279 struct config_param
*config
;
2282 mac_control
= &nic
->mac_control
;
2283 config
= &nic
->config
;
2285 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
2286 for (j
= 0; j
< config
->tx_cfg
[i
].fifo_len
- 1; j
++) {
2287 txdp
= (struct TxD
*) \
2288 mac_control
->fifos
[i
].list_info
[j
].list_virt_addr
;
2289 skb
= s2io_txdl_getskb(&mac_control
->fifos
[i
], txdp
, j
);
2291 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
2298 "%s:forcibly freeing %d skbs on FIFO%d\n",
2300 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
2301 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
2306 * stop_nic - To stop the nic
2307 * @nic ; device private variable.
2309 * This function does exactly the opposite of what the start_nic()
2310 * function does. This function is called to stop the device.
2315 static void stop_nic(struct s2io_nic
*nic
)
2317 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2318 register u64 val64
= 0;
2320 struct mac_info
*mac_control
;
2321 struct config_param
*config
;
2323 mac_control
= &nic
->mac_control
;
2324 config
= &nic
->config
;
2326 /* Disable all interrupts */
2327 en_dis_err_alarms(nic
, ENA_ALL_INTRS
, DISABLE_INTRS
);
2328 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
2329 interruptible
|= TX_PIC_INTR
;
2330 en_dis_able_nic_intrs(nic
, interruptible
, DISABLE_INTRS
);
2332 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2333 val64
= readq(&bar0
->adapter_control
);
2334 val64
&= ~(ADAPTER_CNTL_EN
);
2335 writeq(val64
, &bar0
->adapter_control
);
2339 * fill_rx_buffers - Allocates the Rx side skbs
2340 * @nic: device private variable
2341 * @ring_no: ring number
2343 * The function allocates Rx side skbs and puts the physical
2344 * address of these buffers into the RxD buffer pointers, so that the NIC
2345 * can DMA the received frame into these locations.
2346 * The NIC supports 3 receive modes, viz
2348 * 2. three buffer and
2349 * 3. Five buffer modes.
2350 * Each mode defines how many fragments the received frame will be split
2351 * up into by the NIC. The frame is split into L3 header, L4 Header,
2352 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2353 * is split into 3 fragments. As of now only single buffer mode is
2356 * SUCCESS on success or an appropriate -ve value on failure.
2359 static int fill_rx_buffers(struct s2io_nic
*nic
, int ring_no
)
2361 struct net_device
*dev
= nic
->dev
;
2362 struct sk_buff
*skb
;
2364 int off
, off1
, size
, block_no
, block_no1
;
2367 struct mac_info
*mac_control
;
2368 struct config_param
*config
;
2371 unsigned long flags
;
2372 struct RxD_t
*first_rxdp
= NULL
;
2373 u64 Buffer0_ptr
= 0, Buffer1_ptr
= 0;
2376 struct swStat
*stats
= &nic
->mac_control
.stats_info
->sw_stat
;
2378 mac_control
= &nic
->mac_control
;
2379 config
= &nic
->config
;
2380 alloc_cnt
= mac_control
->rings
[ring_no
].pkt_cnt
-
2381 atomic_read(&nic
->rx_bufs_left
[ring_no
]);
2383 block_no1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.block_index
;
2384 off1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.offset
;
2385 while (alloc_tab
< alloc_cnt
) {
2386 block_no
= mac_control
->rings
[ring_no
].rx_curr_put_info
.
2388 off
= mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
;
2390 rxdp
= mac_control
->rings
[ring_no
].
2391 rx_blocks
[block_no
].rxds
[off
].virt_addr
;
2393 if ((block_no
== block_no1
) && (off
== off1
) &&
2394 (rxdp
->Host_Control
)) {
2395 DBG_PRINT(INTR_DBG
, "%s: Get and Put",
2397 DBG_PRINT(INTR_DBG
, " info equated\n");
2400 if (off
&& (off
== rxd_count
[nic
->rxd_mode
])) {
2401 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2403 if (mac_control
->rings
[ring_no
].rx_curr_put_info
.
2404 block_index
== mac_control
->rings
[ring_no
].
2406 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2408 block_no
= mac_control
->rings
[ring_no
].
2409 rx_curr_put_info
.block_index
;
2410 if (off
== rxd_count
[nic
->rxd_mode
])
2412 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2414 rxdp
= mac_control
->rings
[ring_no
].
2415 rx_blocks
[block_no
].block_virt_addr
;
2416 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
2420 spin_lock_irqsave(&nic
->put_lock
, flags
);
2421 mac_control
->rings
[ring_no
].put_pos
=
2422 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2423 spin_unlock_irqrestore(&nic
->put_lock
, flags
);
2425 mac_control
->rings
[ring_no
].put_pos
=
2426 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2428 if ((rxdp
->Control_1
& RXD_OWN_XENA
) &&
2429 ((nic
->rxd_mode
== RXD_MODE_3B
) &&
2430 (rxdp
->Control_2
& s2BIT(0)))) {
2431 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2435 /* calculate size of skb based on ring mode */
2436 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
2437 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
2438 if (nic
->rxd_mode
== RXD_MODE_1
)
2439 size
+= NET_IP_ALIGN
;
2441 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2444 skb
= dev_alloc_skb(size
);
2446 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
2447 DBG_PRINT(INFO_DBG
, "memory to allocate SKBs\n");
2450 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2452 nic
->mac_control
.stats_info
->sw_stat
. \
2453 mem_alloc_fail_cnt
++;
2456 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
2458 if (nic
->rxd_mode
== RXD_MODE_1
) {
2459 /* 1 buffer mode - normal operation mode */
2460 rxdp1
= (struct RxD1
*)rxdp
;
2461 memset(rxdp
, 0, sizeof(struct RxD1
));
2462 skb_reserve(skb
, NET_IP_ALIGN
);
2463 rxdp1
->Buffer0_ptr
= pci_map_single
2464 (nic
->pdev
, skb
->data
, size
- NET_IP_ALIGN
,
2465 PCI_DMA_FROMDEVICE
);
2466 if( (rxdp1
->Buffer0_ptr
== 0) ||
2467 (rxdp1
->Buffer0_ptr
==
2469 goto pci_map_failed
;
2472 SET_BUFFER0_SIZE_1(size
- NET_IP_ALIGN
);
2474 } else if (nic
->rxd_mode
== RXD_MODE_3B
) {
2477 * 2 buffer mode provides 128
2478 * byte aligned receive buffers.
2481 rxdp3
= (struct RxD3
*)rxdp
;
2482 /* save buffer pointers to avoid frequent dma mapping */
2483 Buffer0_ptr
= rxdp3
->Buffer0_ptr
;
2484 Buffer1_ptr
= rxdp3
->Buffer1_ptr
;
2485 memset(rxdp
, 0, sizeof(struct RxD3
));
2486 /* restore the buffer pointers for dma sync*/
2487 rxdp3
->Buffer0_ptr
= Buffer0_ptr
;
2488 rxdp3
->Buffer1_ptr
= Buffer1_ptr
;
2490 ba
= &mac_control
->rings
[ring_no
].ba
[block_no
][off
];
2491 skb_reserve(skb
, BUF0_LEN
);
2492 tmp
= (u64
)(unsigned long) skb
->data
;
2495 skb
->data
= (void *) (unsigned long)tmp
;
2496 skb_reset_tail_pointer(skb
);
2498 if (!(rxdp3
->Buffer0_ptr
))
2499 rxdp3
->Buffer0_ptr
=
2500 pci_map_single(nic
->pdev
, ba
->ba_0
, BUF0_LEN
,
2501 PCI_DMA_FROMDEVICE
);
2503 pci_dma_sync_single_for_device(nic
->pdev
,
2504 (dma_addr_t
) rxdp3
->Buffer0_ptr
,
2505 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2506 if( (rxdp3
->Buffer0_ptr
== 0) ||
2507 (rxdp3
->Buffer0_ptr
== DMA_ERROR_CODE
))
2508 goto pci_map_failed
;
2510 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
2511 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2512 /* Two buffer mode */
2515 * Buffer2 will have L3/L4 header plus
2518 rxdp3
->Buffer2_ptr
= pci_map_single
2519 (nic
->pdev
, skb
->data
, dev
->mtu
+ 4,
2520 PCI_DMA_FROMDEVICE
);
2522 if( (rxdp3
->Buffer2_ptr
== 0) ||
2523 (rxdp3
->Buffer2_ptr
== DMA_ERROR_CODE
))
2524 goto pci_map_failed
;
2526 rxdp3
->Buffer1_ptr
=
2527 pci_map_single(nic
->pdev
,
2529 PCI_DMA_FROMDEVICE
);
2530 if( (rxdp3
->Buffer1_ptr
== 0) ||
2531 (rxdp3
->Buffer1_ptr
== DMA_ERROR_CODE
)) {
2534 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
2536 PCI_DMA_FROMDEVICE
);
2537 goto pci_map_failed
;
2539 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
2540 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3
2543 rxdp
->Control_2
|= s2BIT(0);
2545 rxdp
->Host_Control
= (unsigned long) (skb
);
2546 if (alloc_tab
& ((1 << rxsync_frequency
) - 1))
2547 rxdp
->Control_1
|= RXD_OWN_XENA
;
2549 if (off
== (rxd_count
[nic
->rxd_mode
] + 1))
2551 mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
= off
;
2553 rxdp
->Control_2
|= SET_RXD_MARKER
;
2554 if (!(alloc_tab
& ((1 << rxsync_frequency
) - 1))) {
2557 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2561 atomic_inc(&nic
->rx_bufs_left
[ring_no
]);
2566 /* Transfer ownership of first descriptor to adapter just before
2567 * exiting. Before that, use memory barrier so that ownership
2568 * and other fields are seen by adapter correctly.
2572 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2577 stats
->pci_map_fail_cnt
++;
2578 stats
->mem_freed
+= skb
->truesize
;
2579 dev_kfree_skb_irq(skb
);
2583 static void free_rxd_blk(struct s2io_nic
*sp
, int ring_no
, int blk
)
2585 struct net_device
*dev
= sp
->dev
;
2587 struct sk_buff
*skb
;
2589 struct mac_info
*mac_control
;
2594 mac_control
= &sp
->mac_control
;
2595 for (j
= 0 ; j
< rxd_count
[sp
->rxd_mode
]; j
++) {
2596 rxdp
= mac_control
->rings
[ring_no
].
2597 rx_blocks
[blk
].rxds
[j
].virt_addr
;
2598 skb
= (struct sk_buff
*)
2599 ((unsigned long) rxdp
->Host_Control
);
2603 if (sp
->rxd_mode
== RXD_MODE_1
) {
2604 rxdp1
= (struct RxD1
*)rxdp
;
2605 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2608 HEADER_ETHERNET_II_802_3_SIZE
2609 + HEADER_802_2_SIZE
+
2611 PCI_DMA_FROMDEVICE
);
2612 memset(rxdp
, 0, sizeof(struct RxD1
));
2613 } else if(sp
->rxd_mode
== RXD_MODE_3B
) {
2614 rxdp3
= (struct RxD3
*)rxdp
;
2615 ba
= &mac_control
->rings
[ring_no
].
2617 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2620 PCI_DMA_FROMDEVICE
);
2621 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2624 PCI_DMA_FROMDEVICE
);
2625 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2628 PCI_DMA_FROMDEVICE
);
2629 memset(rxdp
, 0, sizeof(struct RxD3
));
2631 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
2633 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
2638 * free_rx_buffers - Frees all Rx buffers
2639 * @sp: device private variable.
2641 * This function will free all Rx buffers allocated by host.
2646 static void free_rx_buffers(struct s2io_nic
*sp
)
2648 struct net_device
*dev
= sp
->dev
;
2649 int i
, blk
= 0, buf_cnt
= 0;
2650 struct mac_info
*mac_control
;
2651 struct config_param
*config
;
2653 mac_control
= &sp
->mac_control
;
2654 config
= &sp
->config
;
2656 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2657 for (blk
= 0; blk
< rx_ring_sz
[i
]; blk
++)
2658 free_rxd_blk(sp
,i
,blk
);
2660 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
2661 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
2662 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
2663 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
2664 atomic_set(&sp
->rx_bufs_left
[i
], 0);
2665 DBG_PRINT(INIT_DBG
, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2666 dev
->name
, buf_cnt
, i
);
2671 * s2io_poll - Rx interrupt handler for NAPI support
2672 * @napi : pointer to the napi structure.
2673 * @budget : The number of packets that were budgeted to be processed
2674 * during one pass through the 'Poll" function.
2676 * Comes into picture only if NAPI support has been incorporated. It does
2677 * the same thing that rx_intr_handler does, but not in a interrupt context
2678 * also It will process only a given number of packets.
2680 * 0 on success and 1 if there are No Rx packets to be processed.
2683 static int s2io_poll(struct napi_struct
*napi
, int budget
)
2685 struct s2io_nic
*nic
= container_of(napi
, struct s2io_nic
, napi
);
2686 struct net_device
*dev
= nic
->dev
;
2687 int pkt_cnt
= 0, org_pkts_to_process
;
2688 struct mac_info
*mac_control
;
2689 struct config_param
*config
;
2690 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2693 if (!is_s2io_card_up(nic
))
2696 mac_control
= &nic
->mac_control
;
2697 config
= &nic
->config
;
2699 nic
->pkts_to_process
= budget
;
2700 org_pkts_to_process
= nic
->pkts_to_process
;
2702 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
2703 readl(&bar0
->rx_traffic_int
);
2705 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2706 rx_intr_handler(&mac_control
->rings
[i
]);
2707 pkt_cnt
= org_pkts_to_process
- nic
->pkts_to_process
;
2708 if (!nic
->pkts_to_process
) {
2709 /* Quota for the current iteration has been met */
2714 netif_rx_complete(dev
, napi
);
2716 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2717 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2718 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2719 DBG_PRINT(INFO_DBG
, " in Rx Poll!!\n");
2723 /* Re enable the Rx interrupts. */
2724 writeq(0x0, &bar0
->rx_traffic_mask
);
2725 readl(&bar0
->rx_traffic_mask
);
2729 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2730 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2731 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2732 DBG_PRINT(INFO_DBG
, " in Rx Poll!!\n");
2739 #ifdef CONFIG_NET_POLL_CONTROLLER
2741 * s2io_netpoll - netpoll event handler entry point
2742 * @dev : pointer to the device structure.
2744 * This function will be called by upper layer to check for events on the
2745 * interface in situations where interrupts are disabled. It is used for
2746 * specific in-kernel networking tasks, such as remote consoles and kernel
2747 * debugging over the network (example netdump in RedHat).
2749 static void s2io_netpoll(struct net_device
*dev
)
2751 struct s2io_nic
*nic
= dev
->priv
;
2752 struct mac_info
*mac_control
;
2753 struct config_param
*config
;
2754 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2755 u64 val64
= 0xFFFFFFFFFFFFFFFFULL
;
2758 if (pci_channel_offline(nic
->pdev
))
2761 disable_irq(dev
->irq
);
2763 mac_control
= &nic
->mac_control
;
2764 config
= &nic
->config
;
2766 writeq(val64
, &bar0
->rx_traffic_int
);
2767 writeq(val64
, &bar0
->tx_traffic_int
);
2769 /* we need to free up the transmitted skbufs or else netpoll will
2770 * run out of skbs and will fail and eventually netpoll application such
2771 * as netdump will fail.
2773 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
2774 tx_intr_handler(&mac_control
->fifos
[i
]);
2776 /* check for received packet and indicate up to network */
2777 for (i
= 0; i
< config
->rx_ring_num
; i
++)
2778 rx_intr_handler(&mac_control
->rings
[i
]);
2780 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2781 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2782 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2783 DBG_PRINT(INFO_DBG
, " in Rx Netpoll!!\n");
2787 enable_irq(dev
->irq
);
2793 * rx_intr_handler - Rx interrupt handler
2794 * @nic: device private variable.
2796 * If the interrupt is because of a received frame or if the
2797 * receive ring contains fresh as yet un-processed frames,this function is
2798 * called. It picks out the RxD at which place the last Rx processing had
2799 * stopped and sends the skb to the OSM's Rx handler and then increments
2804 static void rx_intr_handler(struct ring_info
*ring_data
)
2806 struct s2io_nic
*nic
= ring_data
->nic
;
2807 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2808 int get_block
, put_block
, put_offset
;
2809 struct rx_curr_get_info get_info
, put_info
;
2811 struct sk_buff
*skb
;
2817 spin_lock(&nic
->rx_lock
);
2819 get_info
= ring_data
->rx_curr_get_info
;
2820 get_block
= get_info
.block_index
;
2821 memcpy(&put_info
, &ring_data
->rx_curr_put_info
, sizeof(put_info
));
2822 put_block
= put_info
.block_index
;
2823 rxdp
= ring_data
->rx_blocks
[get_block
].rxds
[get_info
.offset
].virt_addr
;
2825 spin_lock(&nic
->put_lock
);
2826 put_offset
= ring_data
->put_pos
;
2827 spin_unlock(&nic
->put_lock
);
2829 put_offset
= ring_data
->put_pos
;
2831 while (RXD_IS_UP2DT(rxdp
)) {
2833 * If your are next to put index then it's
2834 * FIFO full condition
2836 if ((get_block
== put_block
) &&
2837 (get_info
.offset
+ 1) == put_info
.offset
) {
2838 DBG_PRINT(INTR_DBG
, "%s: Ring Full\n",dev
->name
);
2841 skb
= (struct sk_buff
*) ((unsigned long)rxdp
->Host_Control
);
2843 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
2845 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
2846 spin_unlock(&nic
->rx_lock
);
2849 if (nic
->rxd_mode
== RXD_MODE_1
) {
2850 rxdp1
= (struct RxD1
*)rxdp
;
2851 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2854 HEADER_ETHERNET_II_802_3_SIZE
+
2857 PCI_DMA_FROMDEVICE
);
2858 } else if (nic
->rxd_mode
== RXD_MODE_3B
) {
2859 rxdp3
= (struct RxD3
*)rxdp
;
2860 pci_dma_sync_single_for_cpu(nic
->pdev
, (dma_addr_t
)
2862 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2863 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2866 PCI_DMA_FROMDEVICE
);
2868 prefetch(skb
->data
);
2869 rx_osm_handler(ring_data
, rxdp
);
2871 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2872 rxdp
= ring_data
->rx_blocks
[get_block
].
2873 rxds
[get_info
.offset
].virt_addr
;
2874 if (get_info
.offset
== rxd_count
[nic
->rxd_mode
]) {
2875 get_info
.offset
= 0;
2876 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2878 if (get_block
== ring_data
->block_count
)
2880 ring_data
->rx_curr_get_info
.block_index
= get_block
;
2881 rxdp
= ring_data
->rx_blocks
[get_block
].block_virt_addr
;
2884 nic
->pkts_to_process
-= 1;
2885 if ((napi
) && (!nic
->pkts_to_process
))
2888 if ((indicate_max_pkts
) && (pkt_cnt
> indicate_max_pkts
))
2892 /* Clear all LRO sessions before exiting */
2893 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
2894 struct lro
*lro
= &nic
->lro0_n
[i
];
2896 update_L3L4_header(nic
, lro
);
2897 queue_rx_frame(lro
->parent
);
2898 clear_lro_session(lro
);
2903 spin_unlock(&nic
->rx_lock
);
2907 * tx_intr_handler - Transmit interrupt handler
2908 * @nic : device private variable
2910 * If an interrupt was raised to indicate DMA complete of the
2911 * Tx packet, this function is called. It identifies the last TxD
2912 * whose buffer was freed and frees all skbs whose data have already
2913 * DMA'ed into the NICs internal memory.
2918 static void tx_intr_handler(struct fifo_info
*fifo_data
)
2920 struct s2io_nic
*nic
= fifo_data
->nic
;
2921 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2922 struct tx_curr_get_info get_info
, put_info
;
2923 struct sk_buff
*skb
;
2927 get_info
= fifo_data
->tx_curr_get_info
;
2928 memcpy(&put_info
, &fifo_data
->tx_curr_put_info
, sizeof(put_info
));
2929 txdlp
= (struct TxD
*) fifo_data
->list_info
[get_info
.offset
].
2931 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
2932 (get_info
.offset
!= put_info
.offset
) &&
2933 (txdlp
->Host_Control
)) {
2934 /* Check for TxD errors */
2935 if (txdlp
->Control_1
& TXD_T_CODE
) {
2936 unsigned long long err
;
2937 err
= txdlp
->Control_1
& TXD_T_CODE
;
2939 nic
->mac_control
.stats_info
->sw_stat
.
2943 /* update t_code statistics */
2944 err_mask
= err
>> 48;
2947 nic
->mac_control
.stats_info
->sw_stat
.
2952 nic
->mac_control
.stats_info
->sw_stat
.
2953 tx_desc_abort_cnt
++;
2957 nic
->mac_control
.stats_info
->sw_stat
.
2958 tx_parity_err_cnt
++;
2962 nic
->mac_control
.stats_info
->sw_stat
.
2967 nic
->mac_control
.stats_info
->sw_stat
.
2968 tx_list_proc_err_cnt
++;
2973 skb
= s2io_txdl_getskb(fifo_data
, txdlp
, get_info
.offset
);
2975 DBG_PRINT(ERR_DBG
, "%s: Null skb ",
2977 DBG_PRINT(ERR_DBG
, "in Tx Free Intr\n");
2981 /* Updating the statistics block */
2982 nic
->stats
.tx_bytes
+= skb
->len
;
2983 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
2984 dev_kfree_skb_irq(skb
);
2987 if (get_info
.offset
== get_info
.fifo_len
+ 1)
2988 get_info
.offset
= 0;
2989 txdlp
= (struct TxD
*) fifo_data
->list_info
2990 [get_info
.offset
].list_virt_addr
;
2991 fifo_data
->tx_curr_get_info
.offset
=
2995 spin_lock(&nic
->tx_lock
);
2996 if (netif_queue_stopped(dev
))
2997 netif_wake_queue(dev
);
2998 spin_unlock(&nic
->tx_lock
);
3002 * s2io_mdio_write - Function to write in to MDIO registers
3003 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3004 * @addr : address value
3005 * @value : data value
3006 * @dev : pointer to net_device structure
3008 * This function is used to write values to the MDIO registers
3011 static void s2io_mdio_write(u32 mmd_type
, u64 addr
, u16 value
, struct net_device
*dev
)
3014 struct s2io_nic
*sp
= dev
->priv
;
3015 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3017 //address transaction
3018 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3019 | MDIO_MMD_DEV_ADDR(mmd_type
)
3020 | MDIO_MMS_PRT_ADDR(0x0);
3021 writeq(val64
, &bar0
->mdio_control
);
3022 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3023 writeq(val64
, &bar0
->mdio_control
);
3028 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3029 | MDIO_MMD_DEV_ADDR(mmd_type
)
3030 | MDIO_MMS_PRT_ADDR(0x0)
3031 | MDIO_MDIO_DATA(value
)
3032 | MDIO_OP(MDIO_OP_WRITE_TRANS
);
3033 writeq(val64
, &bar0
->mdio_control
);
3034 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3035 writeq(val64
, &bar0
->mdio_control
);
3039 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3040 | MDIO_MMD_DEV_ADDR(mmd_type
)
3041 | MDIO_MMS_PRT_ADDR(0x0)
3042 | MDIO_OP(MDIO_OP_READ_TRANS
);
3043 writeq(val64
, &bar0
->mdio_control
);
3044 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3045 writeq(val64
, &bar0
->mdio_control
);
3051 * s2io_mdio_read - Function to write in to MDIO registers
3052 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3053 * @addr : address value
3054 * @dev : pointer to net_device structure
3056 * This function is used to read values to the MDIO registers
3059 static u64
s2io_mdio_read(u32 mmd_type
, u64 addr
, struct net_device
*dev
)
3063 struct s2io_nic
*sp
= dev
->priv
;
3064 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3066 /* address transaction */
3067 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3068 | MDIO_MMD_DEV_ADDR(mmd_type
)
3069 | MDIO_MMS_PRT_ADDR(0x0);
3070 writeq(val64
, &bar0
->mdio_control
);
3071 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3072 writeq(val64
, &bar0
->mdio_control
);
3075 /* Data transaction */
3077 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3078 | MDIO_MMD_DEV_ADDR(mmd_type
)
3079 | MDIO_MMS_PRT_ADDR(0x0)
3080 | MDIO_OP(MDIO_OP_READ_TRANS
);
3081 writeq(val64
, &bar0
->mdio_control
);
3082 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3083 writeq(val64
, &bar0
->mdio_control
);
3086 /* Read the value from regs */
3087 rval64
= readq(&bar0
->mdio_control
);
3088 rval64
= rval64
& 0xFFFF0000;
3089 rval64
= rval64
>> 16;
3093 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3094 * @counter : couter value to be updated
3095 * @flag : flag to indicate the status
3096 * @type : counter type
3098 * This function is to check the status of the xpak counters value
3102 static void s2io_chk_xpak_counter(u64
*counter
, u64
* regs_stat
, u32 index
, u16 flag
, u16 type
)
3107 for(i
= 0; i
<index
; i
++)
3112 *counter
= *counter
+ 1;
3113 val64
= *regs_stat
& mask
;
3114 val64
= val64
>> (index
* 0x2);
3121 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3122 "service. Excessive temperatures may "
3123 "result in premature transceiver "
3127 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3128 "service Excessive bias currents may "
3129 "indicate imminent laser diode "
3133 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3134 "service Excessive laser output "
3135 "power may saturate far-end "
3139 DBG_PRINT(ERR_DBG
, "Incorrect XPAK Alarm "
3144 val64
= val64
<< (index
* 0x2);
3145 *regs_stat
= (*regs_stat
& (~mask
)) | (val64
);
3148 *regs_stat
= *regs_stat
& (~mask
);
3153 * s2io_updt_xpak_counter - Function to update the xpak counters
3154 * @dev : pointer to net_device struct
3156 * This function is to upate the status of the xpak counters value
3159 static void s2io_updt_xpak_counter(struct net_device
*dev
)
3167 struct s2io_nic
*sp
= dev
->priv
;
3168 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
3170 /* Check the communication with the MDIO slave */
3173 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3174 if((val64
== 0xFFFF) || (val64
== 0x0000))
3176 DBG_PRINT(ERR_DBG
, "ERR: MDIO slave access failed - "
3177 "Returned %llx\n", (unsigned long long)val64
);
3181 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3184 DBG_PRINT(ERR_DBG
, "Incorrect value at PMA address 0x0000 - ");
3185 DBG_PRINT(ERR_DBG
, "Returned: %llx- Expected: 0x2040\n",
3186 (unsigned long long)val64
);
3190 /* Loading the DOM register to MDIO register */
3192 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR
, addr
, val16
, dev
);
3193 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3195 /* Reading the Alarm flags */
3198 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3200 flag
= CHECKBIT(val64
, 0x7);
3202 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_transceiver_temp_high
,
3203 &stat_info
->xpak_stat
.xpak_regs_stat
,
3206 if(CHECKBIT(val64
, 0x6))
3207 stat_info
->xpak_stat
.alarm_transceiver_temp_low
++;
3209 flag
= CHECKBIT(val64
, 0x3);
3211 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_bias_current_high
,
3212 &stat_info
->xpak_stat
.xpak_regs_stat
,
3215 if(CHECKBIT(val64
, 0x2))
3216 stat_info
->xpak_stat
.alarm_laser_bias_current_low
++;
3218 flag
= CHECKBIT(val64
, 0x1);
3220 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_output_power_high
,
3221 &stat_info
->xpak_stat
.xpak_regs_stat
,
3224 if(CHECKBIT(val64
, 0x0))
3225 stat_info
->xpak_stat
.alarm_laser_output_power_low
++;
3227 /* Reading the Warning flags */
3230 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3232 if(CHECKBIT(val64
, 0x7))
3233 stat_info
->xpak_stat
.warn_transceiver_temp_high
++;
3235 if(CHECKBIT(val64
, 0x6))
3236 stat_info
->xpak_stat
.warn_transceiver_temp_low
++;
3238 if(CHECKBIT(val64
, 0x3))
3239 stat_info
->xpak_stat
.warn_laser_bias_current_high
++;
3241 if(CHECKBIT(val64
, 0x2))
3242 stat_info
->xpak_stat
.warn_laser_bias_current_low
++;
3244 if(CHECKBIT(val64
, 0x1))
3245 stat_info
->xpak_stat
.warn_laser_output_power_high
++;
3247 if(CHECKBIT(val64
, 0x0))
3248 stat_info
->xpak_stat
.warn_laser_output_power_low
++;
3252 * wait_for_cmd_complete - waits for a command to complete.
3253 * @sp : private member of the device structure, which is a pointer to the
3254 * s2io_nic structure.
3255 * Description: Function that waits for a command to Write into RMAC
3256 * ADDR DATA registers to be completed and returns either success or
3257 * error depending on whether the command was complete or not.
3259 * SUCCESS on success and FAILURE on failure.
3262 static int wait_for_cmd_complete(void __iomem
*addr
, u64 busy_bit
,
3265 int ret
= FAILURE
, cnt
= 0, delay
= 1;
3268 if ((bit_state
!= S2IO_BIT_RESET
) && (bit_state
!= S2IO_BIT_SET
))
3272 val64
= readq(addr
);
3273 if (bit_state
== S2IO_BIT_RESET
) {
3274 if (!(val64
& busy_bit
)) {
3279 if (!(val64
& busy_bit
)) {
3296 * check_pci_device_id - Checks if the device id is supported
3298 * Description: Function to check if the pci device id is supported by driver.
3299 * Return value: Actual device id if supported else PCI_ANY_ID
3301 static u16
check_pci_device_id(u16 id
)
3304 case PCI_DEVICE_ID_HERC_WIN
:
3305 case PCI_DEVICE_ID_HERC_UNI
:
3306 return XFRAME_II_DEVICE
;
3307 case PCI_DEVICE_ID_S2IO_UNI
:
3308 case PCI_DEVICE_ID_S2IO_WIN
:
3309 return XFRAME_I_DEVICE
;
3316 * s2io_reset - Resets the card.
3317 * @sp : private member of the device structure.
3318 * Description: Function to Reset the card. This function then also
3319 * restores the previously saved PCI configuration space registers as
3320 * the card reset also resets the configuration space.
3325 static void s2io_reset(struct s2io_nic
* sp
)
3327 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3332 unsigned long long up_cnt
, down_cnt
, up_time
, down_time
, reset_cnt
;
3333 unsigned long long mem_alloc_cnt
, mem_free_cnt
, watchdog_cnt
;
3335 DBG_PRINT(INIT_DBG
,"%s - Resetting XFrame card %s\n",
3336 __FUNCTION__
, sp
->dev
->name
);
3338 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3339 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, &(pci_cmd
));
3341 val64
= SW_RESET_ALL
;
3342 writeq(val64
, &bar0
->sw_reset
);
3343 if (strstr(sp
->product_name
, "CX4")) {
3347 for (i
= 0; i
< S2IO_MAX_PCI_CONFIG_SPACE_REINIT
; i
++) {
3349 /* Restore the PCI state saved during initialization. */
3350 pci_restore_state(sp
->pdev
);
3351 pci_read_config_word(sp
->pdev
, 0x2, &val16
);
3352 if (check_pci_device_id(val16
) != (u16
)PCI_ANY_ID
)
3357 if (check_pci_device_id(val16
) == (u16
)PCI_ANY_ID
) {
3358 DBG_PRINT(ERR_DBG
,"%s SW_Reset failed!\n", __FUNCTION__
);
3361 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, pci_cmd
);
3365 /* Set swapper to enable I/O register access */
3366 s2io_set_swapper(sp
);
3368 /* Restore the MSIX table entries from local variables */
3369 restore_xmsi_data(sp
);
3371 /* Clear certain PCI/PCI-X fields after reset */
3372 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3373 /* Clear "detected parity error" bit */
3374 pci_write_config_word(sp
->pdev
, PCI_STATUS
, 0x8000);
3376 /* Clearing PCIX Ecc status register */
3377 pci_write_config_dword(sp
->pdev
, 0x68, 0x7C);
3379 /* Clearing PCI_STATUS error reflected here */
3380 writeq(s2BIT(62), &bar0
->txpic_int_reg
);
3383 /* Reset device statistics maintained by OS */
3384 memset(&sp
->stats
, 0, sizeof (struct net_device_stats
));
3386 up_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
;
3387 down_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
;
3388 up_time
= sp
->mac_control
.stats_info
->sw_stat
.link_up_time
;
3389 down_time
= sp
->mac_control
.stats_info
->sw_stat
.link_down_time
;
3390 reset_cnt
= sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
;
3391 mem_alloc_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
;
3392 mem_free_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_freed
;
3393 watchdog_cnt
= sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
;
3394 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3395 memset(sp
->mac_control
.stats_info
, 0, sizeof(struct stat_block
));
3396 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3397 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
= up_cnt
;
3398 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
= down_cnt
;
3399 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
= up_time
;
3400 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
= down_time
;
3401 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
= reset_cnt
;
3402 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
= mem_alloc_cnt
;
3403 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
= mem_free_cnt
;
3404 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
= watchdog_cnt
;
3406 /* SXE-002: Configure link and activity LED to turn it off */
3407 subid
= sp
->pdev
->subsystem_device
;
3408 if (((subid
& 0xFF) >= 0x07) &&
3409 (sp
->device_type
== XFRAME_I_DEVICE
)) {
3410 val64
= readq(&bar0
->gpio_control
);
3411 val64
|= 0x0000800000000000ULL
;
3412 writeq(val64
, &bar0
->gpio_control
);
3413 val64
= 0x0411040400000000ULL
;
3414 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
3418 * Clear spurious ECC interrupts that would have occured on
3419 * XFRAME II cards after reset.
3421 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3422 val64
= readq(&bar0
->pcc_err_reg
);
3423 writeq(val64
, &bar0
->pcc_err_reg
);
3426 /* restore the previously assigned mac address */
3427 do_s2io_prog_unicast(sp
->dev
, (u8
*)&sp
->def_mac_addr
[0].mac_addr
);
3429 sp
->device_enabled_once
= FALSE
;
3433 * s2io_set_swapper - to set the swapper controle on the card
3434 * @sp : private member of the device structure,
3435 * pointer to the s2io_nic structure.
3436 * Description: Function to set the swapper control on the card
3437 * correctly depending on the 'endianness' of the system.
3439 * SUCCESS on success and FAILURE on failure.
3442 static int s2io_set_swapper(struct s2io_nic
* sp
)
3444 struct net_device
*dev
= sp
->dev
;
3445 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3446 u64 val64
, valt
, valr
;
3449 * Set proper endian settings and verify the same by reading
3450 * the PIF Feed-back register.
3453 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3454 if (val64
!= 0x0123456789ABCDEFULL
) {
3456 u64 value
[] = { 0xC30000C3C30000C3ULL
, /* FE=1, SE=1 */
3457 0x8100008181000081ULL
, /* FE=1, SE=0 */
3458 0x4200004242000042ULL
, /* FE=0, SE=1 */
3459 0}; /* FE=0, SE=0 */
3462 writeq(value
[i
], &bar0
->swapper_ctrl
);
3463 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3464 if (val64
== 0x0123456789ABCDEFULL
)
3469 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3471 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3472 (unsigned long long) val64
);
3477 valr
= readq(&bar0
->swapper_ctrl
);
3480 valt
= 0x0123456789ABCDEFULL
;
3481 writeq(valt
, &bar0
->xmsi_address
);
3482 val64
= readq(&bar0
->xmsi_address
);
3486 u64 value
[] = { 0x00C3C30000C3C300ULL
, /* FE=1, SE=1 */
3487 0x0081810000818100ULL
, /* FE=1, SE=0 */
3488 0x0042420000424200ULL
, /* FE=0, SE=1 */
3489 0}; /* FE=0, SE=0 */
3492 writeq((value
[i
] | valr
), &bar0
->swapper_ctrl
);
3493 writeq(valt
, &bar0
->xmsi_address
);
3494 val64
= readq(&bar0
->xmsi_address
);
3500 unsigned long long x
= val64
;
3501 DBG_PRINT(ERR_DBG
, "Write failed, Xmsi_addr ");
3502 DBG_PRINT(ERR_DBG
, "reads:0x%llx\n", x
);
3506 val64
= readq(&bar0
->swapper_ctrl
);
3507 val64
&= 0xFFFF000000000000ULL
;
3511 * The device by default set to a big endian format, so a
3512 * big endian driver need not set anything.
3514 val64
|= (SWAPPER_CTRL_TXP_FE
|
3515 SWAPPER_CTRL_TXP_SE
|
3516 SWAPPER_CTRL_TXD_R_FE
|
3517 SWAPPER_CTRL_TXD_W_FE
|
3518 SWAPPER_CTRL_TXF_R_FE
|
3519 SWAPPER_CTRL_RXD_R_FE
|
3520 SWAPPER_CTRL_RXD_W_FE
|
3521 SWAPPER_CTRL_RXF_W_FE
|
3522 SWAPPER_CTRL_XMSI_FE
|
3523 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3524 if (sp
->config
.intr_type
== INTA
)
3525 val64
|= SWAPPER_CTRL_XMSI_SE
;
3526 writeq(val64
, &bar0
->swapper_ctrl
);
3529 * Initially we enable all bits to make it accessible by the
3530 * driver, then we selectively enable only those bits that
3533 val64
|= (SWAPPER_CTRL_TXP_FE
|
3534 SWAPPER_CTRL_TXP_SE
|
3535 SWAPPER_CTRL_TXD_R_FE
|
3536 SWAPPER_CTRL_TXD_R_SE
|
3537 SWAPPER_CTRL_TXD_W_FE
|
3538 SWAPPER_CTRL_TXD_W_SE
|
3539 SWAPPER_CTRL_TXF_R_FE
|
3540 SWAPPER_CTRL_RXD_R_FE
|
3541 SWAPPER_CTRL_RXD_R_SE
|
3542 SWAPPER_CTRL_RXD_W_FE
|
3543 SWAPPER_CTRL_RXD_W_SE
|
3544 SWAPPER_CTRL_RXF_W_FE
|
3545 SWAPPER_CTRL_XMSI_FE
|
3546 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3547 if (sp
->config
.intr_type
== INTA
)
3548 val64
|= SWAPPER_CTRL_XMSI_SE
;
3549 writeq(val64
, &bar0
->swapper_ctrl
);
3551 val64
= readq(&bar0
->swapper_ctrl
);
3554 * Verifying if endian settings are accurate by reading a
3555 * feedback register.
3557 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3558 if (val64
!= 0x0123456789ABCDEFULL
) {
3559 /* Endian settings are incorrect, calls for another dekko. */
3560 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3562 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3563 (unsigned long long) val64
);
3570 static int wait_for_msix_trans(struct s2io_nic
*nic
, int i
)
3572 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3574 int ret
= 0, cnt
= 0;
3577 val64
= readq(&bar0
->xmsi_access
);
3578 if (!(val64
& s2BIT(15)))
3584 DBG_PRINT(ERR_DBG
, "XMSI # %d Access failed\n", i
);
3591 static void restore_xmsi_data(struct s2io_nic
*nic
)
3593 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3597 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3598 writeq(nic
->msix_info
[i
].addr
, &bar0
->xmsi_address
);
3599 writeq(nic
->msix_info
[i
].data
, &bar0
->xmsi_data
);
3600 val64
= (s2BIT(7) | s2BIT(15) | vBIT(i
, 26, 6));
3601 writeq(val64
, &bar0
->xmsi_access
);
3602 if (wait_for_msix_trans(nic
, i
)) {
3603 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3609 static void store_xmsi_data(struct s2io_nic
*nic
)
3611 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3612 u64 val64
, addr
, data
;
3615 /* Store and display */
3616 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3617 val64
= (s2BIT(15) | vBIT(i
, 26, 6));
3618 writeq(val64
, &bar0
->xmsi_access
);
3619 if (wait_for_msix_trans(nic
, i
)) {
3620 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3623 addr
= readq(&bar0
->xmsi_address
);
3624 data
= readq(&bar0
->xmsi_data
);
3626 nic
->msix_info
[i
].addr
= addr
;
3627 nic
->msix_info
[i
].data
= data
;
3632 static int s2io_enable_msi_x(struct s2io_nic
*nic
)
3634 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3636 u16 msi_control
; /* Temp variable */
3637 int ret
, i
, j
, msix_indx
= 1;
3639 nic
->entries
= kcalloc(MAX_REQUESTED_MSI_X
, sizeof(struct msix_entry
),
3641 if (!nic
->entries
) {
3642 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n", \
3644 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3647 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3648 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3651 kcalloc(MAX_REQUESTED_MSI_X
, sizeof(struct s2io_msix_entry
),
3653 if (!nic
->s2io_entries
) {
3654 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n",
3656 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3657 kfree(nic
->entries
);
3658 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3659 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3662 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3663 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3665 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3666 nic
->entries
[i
].entry
= i
;
3667 nic
->s2io_entries
[i
].entry
= i
;
3668 nic
->s2io_entries
[i
].arg
= NULL
;
3669 nic
->s2io_entries
[i
].in_use
= 0;
3672 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3673 for (i
=0; i
<nic
->config
.tx_fifo_num
; i
++, msix_indx
++) {
3674 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3675 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.fifos
[i
];
3676 nic
->s2io_entries
[msix_indx
].type
= MSIX_FIFO_TYPE
;
3677 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3679 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3681 rx_mat
= readq(&bar0
->rx_mat
);
3682 for (j
= 0; j
< nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3683 rx_mat
|= RX_MAT_SET(j
, msix_indx
);
3684 nic
->s2io_entries
[msix_indx
].arg
3685 = &nic
->mac_control
.rings
[j
];
3686 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3687 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3689 writeq(rx_mat
, &bar0
->rx_mat
);
3691 nic
->avail_msix_vectors
= 0;
3692 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, MAX_REQUESTED_MSI_X
);
3693 /* We fail init if error or we get less vectors than min required */
3694 if (ret
>= (nic
->config
.tx_fifo_num
+ nic
->config
.rx_ring_num
+ 1)) {
3695 nic
->avail_msix_vectors
= ret
;
3696 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, ret
);
3699 DBG_PRINT(ERR_DBG
, "%s: Enabling MSIX failed\n", nic
->dev
->name
);
3700 kfree(nic
->entries
);
3701 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3702 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3703 kfree(nic
->s2io_entries
);
3704 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3705 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3706 nic
->entries
= NULL
;
3707 nic
->s2io_entries
= NULL
;
3708 nic
->avail_msix_vectors
= 0;
3711 if (!nic
->avail_msix_vectors
)
3712 nic
->avail_msix_vectors
= MAX_REQUESTED_MSI_X
;
3715 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3716 * in the herc NIC. (Temp change, needs to be removed later)
3718 pci_read_config_word(nic
->pdev
, 0x42, &msi_control
);
3719 msi_control
|= 0x1; /* Enable MSI */
3720 pci_write_config_word(nic
->pdev
, 0x42, msi_control
);
3725 /* Handle software interrupt used during MSI(X) test */
3726 static irqreturn_t __devinit
s2io_test_intr(int irq
, void *dev_id
)
3728 struct s2io_nic
*sp
= dev_id
;
3730 sp
->msi_detected
= 1;
3731 wake_up(&sp
->msi_wait
);
3736 /* Test interrupt path by forcing a a software IRQ */
3737 static int __devinit
s2io_test_msi(struct s2io_nic
*sp
)
3739 struct pci_dev
*pdev
= sp
->pdev
;
3740 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3744 err
= request_irq(sp
->entries
[1].vector
, s2io_test_intr
, 0,
3747 DBG_PRINT(ERR_DBG
, "%s: PCI %s: cannot assign irq %d\n",
3748 sp
->dev
->name
, pci_name(pdev
), pdev
->irq
);
3752 init_waitqueue_head (&sp
->msi_wait
);
3753 sp
->msi_detected
= 0;
3755 saved64
= val64
= readq(&bar0
->scheduled_int_ctrl
);
3756 val64
|= SCHED_INT_CTRL_ONE_SHOT
;
3757 val64
|= SCHED_INT_CTRL_TIMER_EN
;
3758 val64
|= SCHED_INT_CTRL_INT2MSI(1);
3759 writeq(val64
, &bar0
->scheduled_int_ctrl
);
3761 wait_event_timeout(sp
->msi_wait
, sp
->msi_detected
, HZ
/10);
3763 if (!sp
->msi_detected
) {
3764 /* MSI(X) test failed, go back to INTx mode */
3765 DBG_PRINT(ERR_DBG
, "%s: PCI %s: No interrupt was generated"
3766 "using MSI(X) during test\n", sp
->dev
->name
,
3772 free_irq(sp
->entries
[1].vector
, sp
);
3774 writeq(saved64
, &bar0
->scheduled_int_ctrl
);
3779 static void remove_msix_isr(struct s2io_nic
*sp
)
3784 for (i
= 0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3785 if (sp
->s2io_entries
[i
].in_use
==
3786 MSIX_REGISTERED_SUCCESS
) {
3787 int vector
= sp
->entries
[i
].vector
;
3788 void *arg
= sp
->s2io_entries
[i
].arg
;
3789 free_irq(vector
, arg
);
3794 kfree(sp
->s2io_entries
);
3796 sp
->s2io_entries
= NULL
;
3798 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
3799 msi_control
&= 0xFFFE; /* Disable MSI */
3800 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
3802 pci_disable_msix(sp
->pdev
);
3805 static void remove_inta_isr(struct s2io_nic
*sp
)
3807 struct net_device
*dev
= sp
->dev
;
3809 free_irq(sp
->pdev
->irq
, dev
);
3812 /* ********************************************************* *
3813 * Functions defined below concern the OS part of the driver *
3814 * ********************************************************* */
3817 * s2io_open - open entry point of the driver
3818 * @dev : pointer to the device structure.
3820 * This function is the open entry point of the driver. It mainly calls a
3821 * function to allocate Rx buffers and inserts them into the buffer
3822 * descriptors and then enables the Rx part of the NIC.
3824 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3828 static int s2io_open(struct net_device
*dev
)
3830 struct s2io_nic
*sp
= dev
->priv
;
3834 * Make sure you have link off by default every time
3835 * Nic is initialized
3837 netif_carrier_off(dev
);
3838 sp
->last_link_state
= 0;
3840 napi_enable(&sp
->napi
);
3842 if (sp
->config
.intr_type
== MSI_X
) {
3843 int ret
= s2io_enable_msi_x(sp
);
3846 ret
= s2io_test_msi(sp
);
3847 /* rollback MSI-X, will re-enable during add_isr() */
3848 remove_msix_isr(sp
);
3853 "%s: MSI-X requested but failed to enable\n",
3855 sp
->config
.intr_type
= INTA
;
3859 /* NAPI doesn't work well with MSI(X) */
3860 if (sp
->config
.intr_type
!= INTA
) {
3862 sp
->config
.napi
= 0;
3865 /* Initialize H/W and enable interrupts */
3866 err
= s2io_card_up(sp
);
3868 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
3870 goto hw_init_failed
;
3873 if (do_s2io_prog_unicast(dev
, dev
->dev_addr
) == FAILURE
) {
3874 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
3877 goto hw_init_failed
;
3880 netif_start_queue(dev
);
3884 napi_disable(&sp
->napi
);
3885 if (sp
->config
.intr_type
== MSI_X
) {
3888 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
3889 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3891 if (sp
->s2io_entries
) {
3892 kfree(sp
->s2io_entries
);
3893 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
3894 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3901 * s2io_close -close entry point of the driver
3902 * @dev : device pointer.
3904 * This is the stop entry point of the driver. It needs to undo exactly
3905 * whatever was done by the open entry point,thus it's usually referred to
3906 * as the close function.Among other things this function mainly stops the
3907 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3909 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3913 static int s2io_close(struct net_device
*dev
)
3915 struct s2io_nic
*sp
= dev
->priv
;
3917 netif_stop_queue(dev
);
3918 napi_disable(&sp
->napi
);
3919 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3926 * s2io_xmit - Tx entry point of te driver
3927 * @skb : the socket buffer containing the Tx data.
3928 * @dev : device pointer.
3930 * This function is the Tx entry point of the driver. S2IO NIC supports
3931 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3932 * NOTE: when device cant queue the pkt,just the trans_start variable will
3935 * 0 on success & 1 on failure.
3938 static int s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3940 struct s2io_nic
*sp
= dev
->priv
;
3941 u16 frg_cnt
, frg_len
, i
, queue
, queue_len
, put_off
, get_off
;
3944 struct TxFIFO_element __iomem
*tx_fifo
;
3945 unsigned long flags
;
3947 int vlan_priority
= 0;
3948 struct mac_info
*mac_control
;
3949 struct config_param
*config
;
3951 struct swStat
*stats
= &sp
->mac_control
.stats_info
->sw_stat
;
3953 mac_control
= &sp
->mac_control
;
3954 config
= &sp
->config
;
3956 DBG_PRINT(TX_DBG
, "%s: In Neterion Tx routine\n", dev
->name
);
3958 if (unlikely(skb
->len
<= 0)) {
3959 DBG_PRINT(TX_DBG
, "%s:Buffer has no data..\n", dev
->name
);
3960 dev_kfree_skb_any(skb
);
3964 spin_lock_irqsave(&sp
->tx_lock
, flags
);
3965 if (!is_s2io_card_up(sp
)) {
3966 DBG_PRINT(TX_DBG
, "%s: Card going down for reset\n",
3968 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3974 /* Get Fifo number to Transmit based on vlan priority */
3975 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
3976 vlan_tag
= vlan_tx_tag_get(skb
);
3977 vlan_priority
= vlan_tag
>> 13;
3978 queue
= config
->fifo_mapping
[vlan_priority
];
3981 put_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_put_info
.offset
;
3982 get_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_get_info
.offset
;
3983 txdp
= (struct TxD
*) mac_control
->fifos
[queue
].list_info
[put_off
].
3986 queue_len
= mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1;
3987 /* Avoid "put" pointer going beyond "get" pointer */
3988 if (txdp
->Host_Control
||
3989 ((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
3990 DBG_PRINT(TX_DBG
, "Error in xmit, No free TXDs.\n");
3991 netif_stop_queue(dev
);
3993 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3997 offload_type
= s2io_offload_type(skb
);
3998 if (offload_type
& (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
3999 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
4000 txdp
->Control_1
|= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb
));
4002 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4004 (TXD_TX_CKO_IPV4_EN
| TXD_TX_CKO_TCP_EN
|
4007 txdp
->Control_1
|= TXD_GATHER_CODE_FIRST
;
4008 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
4009 txdp
->Control_2
|= config
->tx_intr_type
;
4011 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
4012 txdp
->Control_2
|= TXD_VLAN_ENABLE
;
4013 txdp
->Control_2
|= TXD_VLAN_TAG(vlan_tag
);
4016 frg_len
= skb
->len
- skb
->data_len
;
4017 if (offload_type
== SKB_GSO_UDP
) {
4020 ufo_size
= s2io_udp_mss(skb
);
4022 txdp
->Control_1
|= TXD_UFO_EN
;
4023 txdp
->Control_1
|= TXD_UFO_MSS(ufo_size
);
4024 txdp
->Control_1
|= TXD_BUFFER0_SIZE(8);
4026 sp
->ufo_in_band_v
[put_off
] =
4027 (u64
)skb_shinfo(skb
)->ip6_frag_id
;
4029 sp
->ufo_in_band_v
[put_off
] =
4030 (u64
)skb_shinfo(skb
)->ip6_frag_id
<< 32;
4032 txdp
->Host_Control
= (unsigned long)sp
->ufo_in_band_v
;
4033 txdp
->Buffer_Pointer
= pci_map_single(sp
->pdev
,
4035 sizeof(u64
), PCI_DMA_TODEVICE
);
4036 if((txdp
->Buffer_Pointer
== 0) ||
4037 (txdp
->Buffer_Pointer
== DMA_ERROR_CODE
))
4038 goto pci_map_failed
;
4042 txdp
->Buffer_Pointer
= pci_map_single
4043 (sp
->pdev
, skb
->data
, frg_len
, PCI_DMA_TODEVICE
);
4044 if((txdp
->Buffer_Pointer
== 0) ||
4045 (txdp
->Buffer_Pointer
== DMA_ERROR_CODE
))
4046 goto pci_map_failed
;
4048 txdp
->Host_Control
= (unsigned long) skb
;
4049 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frg_len
);
4050 if (offload_type
== SKB_GSO_UDP
)
4051 txdp
->Control_1
|= TXD_UFO_EN
;
4053 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
4054 /* For fragmented SKB. */
4055 for (i
= 0; i
< frg_cnt
; i
++) {
4056 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
4057 /* A '0' length fragment will be ignored */
4061 txdp
->Buffer_Pointer
= (u64
) pci_map_page
4062 (sp
->pdev
, frag
->page
, frag
->page_offset
,
4063 frag
->size
, PCI_DMA_TODEVICE
);
4064 txdp
->Control_1
= TXD_BUFFER0_SIZE(frag
->size
);
4065 if (offload_type
== SKB_GSO_UDP
)
4066 txdp
->Control_1
|= TXD_UFO_EN
;
4068 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
4070 if (offload_type
== SKB_GSO_UDP
)
4071 frg_cnt
++; /* as Txd0 was used for inband header */
4073 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
4074 val64
= mac_control
->fifos
[queue
].list_info
[put_off
].list_phy_addr
;
4075 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
4077 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
4080 val64
|= TX_FIFO_SPECIAL_FUNC
;
4082 writeq(val64
, &tx_fifo
->List_Control
);
4087 if (put_off
== mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1)
4089 mac_control
->fifos
[queue
].tx_curr_put_info
.offset
= put_off
;
4091 /* Avoid "put" pointer going beyond "get" pointer */
4092 if (((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4093 sp
->mac_control
.stats_info
->sw_stat
.fifo_full_cnt
++;
4095 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4097 netif_stop_queue(dev
);
4099 mac_control
->stats_info
->sw_stat
.mem_allocated
+= skb
->truesize
;
4100 dev
->trans_start
= jiffies
;
4101 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
4105 stats
->pci_map_fail_cnt
++;
4106 netif_stop_queue(dev
);
4107 stats
->mem_freed
+= skb
->truesize
;
4109 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
4114 s2io_alarm_handle(unsigned long data
)
4116 struct s2io_nic
*sp
= (struct s2io_nic
*)data
;
4117 struct net_device
*dev
= sp
->dev
;
4119 s2io_handle_errors(dev
);
4120 mod_timer(&sp
->alarm_timer
, jiffies
+ HZ
/ 2);
4123 static int s2io_chk_rx_buffers(struct s2io_nic
*sp
, int rng_n
)
4125 int rxb_size
, level
;
4128 rxb_size
= atomic_read(&sp
->rx_bufs_left
[rng_n
]);
4129 level
= rx_buffer_level(sp
, rxb_size
, rng_n
);
4131 if ((level
== PANIC
) && (!TASKLET_IN_USE
)) {
4133 DBG_PRINT(INTR_DBG
, "%s: Rx BD hit ", __FUNCTION__
);
4134 DBG_PRINT(INTR_DBG
, "PANIC levels\n");
4135 if ((ret
= fill_rx_buffers(sp
, rng_n
)) == -ENOMEM
) {
4136 DBG_PRINT(INFO_DBG
, "Out of memory in %s",
4138 clear_bit(0, (&sp
->tasklet_status
));
4141 clear_bit(0, (&sp
->tasklet_status
));
4142 } else if (level
== LOW
)
4143 tasklet_schedule(&sp
->task
);
4145 } else if (fill_rx_buffers(sp
, rng_n
) == -ENOMEM
) {
4146 DBG_PRINT(INFO_DBG
, "%s:Out of memory", sp
->dev
->name
);
4147 DBG_PRINT(INFO_DBG
, " in Rx Intr!!\n");
4152 static irqreturn_t
s2io_msix_ring_handle(int irq
, void *dev_id
)
4154 struct ring_info
*ring
= (struct ring_info
*)dev_id
;
4155 struct s2io_nic
*sp
= ring
->nic
;
4157 if (!is_s2io_card_up(sp
))
4160 rx_intr_handler(ring
);
4161 s2io_chk_rx_buffers(sp
, ring
->ring_no
);
4166 static irqreturn_t
s2io_msix_fifo_handle(int irq
, void *dev_id
)
4168 struct fifo_info
*fifo
= (struct fifo_info
*)dev_id
;
4169 struct s2io_nic
*sp
= fifo
->nic
;
4171 if (!is_s2io_card_up(sp
))
4174 tx_intr_handler(fifo
);
4177 static void s2io_txpic_intr_handle(struct s2io_nic
*sp
)
4179 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4182 val64
= readq(&bar0
->pic_int_status
);
4183 if (val64
& PIC_INT_GPIO
) {
4184 val64
= readq(&bar0
->gpio_int_reg
);
4185 if ((val64
& GPIO_INT_REG_LINK_DOWN
) &&
4186 (val64
& GPIO_INT_REG_LINK_UP
)) {
4188 * This is unstable state so clear both up/down
4189 * interrupt and adapter to re-evaluate the link state.
4191 val64
|= GPIO_INT_REG_LINK_DOWN
;
4192 val64
|= GPIO_INT_REG_LINK_UP
;
4193 writeq(val64
, &bar0
->gpio_int_reg
);
4194 val64
= readq(&bar0
->gpio_int_mask
);
4195 val64
&= ~(GPIO_INT_MASK_LINK_UP
|
4196 GPIO_INT_MASK_LINK_DOWN
);
4197 writeq(val64
, &bar0
->gpio_int_mask
);
4199 else if (val64
& GPIO_INT_REG_LINK_UP
) {
4200 val64
= readq(&bar0
->adapter_status
);
4201 /* Enable Adapter */
4202 val64
= readq(&bar0
->adapter_control
);
4203 val64
|= ADAPTER_CNTL_EN
;
4204 writeq(val64
, &bar0
->adapter_control
);
4205 val64
|= ADAPTER_LED_ON
;
4206 writeq(val64
, &bar0
->adapter_control
);
4207 if (!sp
->device_enabled_once
)
4208 sp
->device_enabled_once
= 1;
4210 s2io_link(sp
, LINK_UP
);
4212 * unmask link down interrupt and mask link-up
4215 val64
= readq(&bar0
->gpio_int_mask
);
4216 val64
&= ~GPIO_INT_MASK_LINK_DOWN
;
4217 val64
|= GPIO_INT_MASK_LINK_UP
;
4218 writeq(val64
, &bar0
->gpio_int_mask
);
4220 }else if (val64
& GPIO_INT_REG_LINK_DOWN
) {
4221 val64
= readq(&bar0
->adapter_status
);
4222 s2io_link(sp
, LINK_DOWN
);
4223 /* Link is down so unmaks link up interrupt */
4224 val64
= readq(&bar0
->gpio_int_mask
);
4225 val64
&= ~GPIO_INT_MASK_LINK_UP
;
4226 val64
|= GPIO_INT_MASK_LINK_DOWN
;
4227 writeq(val64
, &bar0
->gpio_int_mask
);
4230 val64
= readq(&bar0
->adapter_control
);
4231 val64
= val64
&(~ADAPTER_LED_ON
);
4232 writeq(val64
, &bar0
->adapter_control
);
4235 val64
= readq(&bar0
->gpio_int_mask
);
4239 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4240 * @value: alarm bits
4241 * @addr: address value
4242 * @cnt: counter variable
4243 * Description: Check for alarm and increment the counter
4245 * 1 - if alarm bit set
4246 * 0 - if alarm bit is not set
4248 static int do_s2io_chk_alarm_bit(u64 value
, void __iomem
* addr
,
4249 unsigned long long *cnt
)
4252 val64
= readq(addr
);
4253 if ( val64
& value
) {
4254 writeq(val64
, addr
);
4263 * s2io_handle_errors - Xframe error indication handler
4264 * @nic: device private variable
4265 * Description: Handle alarms such as loss of link, single or
4266 * double ECC errors, critical and serious errors.
4270 static void s2io_handle_errors(void * dev_id
)
4272 struct net_device
*dev
= (struct net_device
*) dev_id
;
4273 struct s2io_nic
*sp
= dev
->priv
;
4274 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4275 u64 temp64
= 0,val64
=0;
4278 struct swStat
*sw_stat
= &sp
->mac_control
.stats_info
->sw_stat
;
4279 struct xpakStat
*stats
= &sp
->mac_control
.stats_info
->xpak_stat
;
4281 if (!is_s2io_card_up(sp
))
4284 if (pci_channel_offline(sp
->pdev
))
4287 memset(&sw_stat
->ring_full_cnt
, 0,
4288 sizeof(sw_stat
->ring_full_cnt
));
4290 /* Handling the XPAK counters update */
4291 if(stats
->xpak_timer_count
< 72000) {
4292 /* waiting for an hour */
4293 stats
->xpak_timer_count
++;
4295 s2io_updt_xpak_counter(dev
);
4296 /* reset the count to zero */
4297 stats
->xpak_timer_count
= 0;
4300 /* Handling link status change error Intr */
4301 if (s2io_link_fault_indication(sp
) == MAC_RMAC_ERR_TIMER
) {
4302 val64
= readq(&bar0
->mac_rmac_err_reg
);
4303 writeq(val64
, &bar0
->mac_rmac_err_reg
);
4304 if (val64
& RMAC_LINK_STATE_CHANGE_INT
)
4305 schedule_work(&sp
->set_link_task
);
4308 /* In case of a serious error, the device will be Reset. */
4309 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY
, &bar0
->serr_source
,
4310 &sw_stat
->serious_err_cnt
))
4313 /* Check for data parity error */
4314 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT
, &bar0
->gpio_int_reg
,
4315 &sw_stat
->parity_err_cnt
))
4318 /* Check for ring full counter */
4319 if (sp
->device_type
== XFRAME_II_DEVICE
) {
4320 val64
= readq(&bar0
->ring_bump_counter1
);
4321 for (i
=0; i
<4; i
++) {
4322 temp64
= ( val64
& vBIT(0xFFFF,(i
*16),16));
4323 temp64
>>= 64 - ((i
+1)*16);
4324 sw_stat
->ring_full_cnt
[i
] += temp64
;
4327 val64
= readq(&bar0
->ring_bump_counter2
);
4328 for (i
=0; i
<4; i
++) {
4329 temp64
= ( val64
& vBIT(0xFFFF,(i
*16),16));
4330 temp64
>>= 64 - ((i
+1)*16);
4331 sw_stat
->ring_full_cnt
[i
+4] += temp64
;
4335 val64
= readq(&bar0
->txdma_int_status
);
4336 /*check for pfc_err*/
4337 if (val64
& TXDMA_PFC_INT
) {
4338 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR
| PFC_SM_ERR_ALARM
|
4339 PFC_MISC_0_ERR
| PFC_MISC_1_ERR
|
4340 PFC_PCIX_ERR
, &bar0
->pfc_err_reg
,
4341 &sw_stat
->pfc_err_cnt
))
4343 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR
, &bar0
->pfc_err_reg
,
4344 &sw_stat
->pfc_err_cnt
);
4347 /*check for tda_err*/
4348 if (val64
& TXDMA_TDA_INT
) {
4349 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR
| TDA_SM0_ERR_ALARM
|
4350 TDA_SM1_ERR_ALARM
, &bar0
->tda_err_reg
,
4351 &sw_stat
->tda_err_cnt
))
4353 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR
| TDA_PCIX_ERR
,
4354 &bar0
->tda_err_reg
, &sw_stat
->tda_err_cnt
);
4356 /*check for pcc_err*/
4357 if (val64
& TXDMA_PCC_INT
) {
4358 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM
| PCC_WR_ERR_ALARM
4359 | PCC_N_SERR
| PCC_6_COF_OV_ERR
4360 | PCC_7_COF_OV_ERR
| PCC_6_LSO_OV_ERR
4361 | PCC_7_LSO_OV_ERR
| PCC_FB_ECC_DB_ERR
4362 | PCC_TXB_ECC_DB_ERR
, &bar0
->pcc_err_reg
,
4363 &sw_stat
->pcc_err_cnt
))
4365 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR
| PCC_TXB_ECC_SG_ERR
,
4366 &bar0
->pcc_err_reg
, &sw_stat
->pcc_err_cnt
);
4369 /*check for tti_err*/
4370 if (val64
& TXDMA_TTI_INT
) {
4371 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM
, &bar0
->tti_err_reg
,
4372 &sw_stat
->tti_err_cnt
))
4374 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR
| TTI_ECC_DB_ERR
,
4375 &bar0
->tti_err_reg
, &sw_stat
->tti_err_cnt
);
4378 /*check for lso_err*/
4379 if (val64
& TXDMA_LSO_INT
) {
4380 if (do_s2io_chk_alarm_bit(LSO6_ABORT
| LSO7_ABORT
4381 | LSO6_SM_ERR_ALARM
| LSO7_SM_ERR_ALARM
,
4382 &bar0
->lso_err_reg
, &sw_stat
->lso_err_cnt
))
4384 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW
| LSO7_SEND_OFLOW
,
4385 &bar0
->lso_err_reg
, &sw_stat
->lso_err_cnt
);
4388 /*check for tpa_err*/
4389 if (val64
& TXDMA_TPA_INT
) {
4390 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM
, &bar0
->tpa_err_reg
,
4391 &sw_stat
->tpa_err_cnt
))
4393 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP
, &bar0
->tpa_err_reg
,
4394 &sw_stat
->tpa_err_cnt
);
4397 /*check for sm_err*/
4398 if (val64
& TXDMA_SM_INT
) {
4399 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM
, &bar0
->sm_err_reg
,
4400 &sw_stat
->sm_err_cnt
))
4404 val64
= readq(&bar0
->mac_int_status
);
4405 if (val64
& MAC_INT_STATUS_TMAC_INT
) {
4406 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN
| TMAC_TX_SM_ERR
,
4407 &bar0
->mac_tmac_err_reg
,
4408 &sw_stat
->mac_tmac_err_cnt
))
4410 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR
| TMAC_ECC_DB_ERR
4411 | TMAC_DESC_ECC_SG_ERR
| TMAC_DESC_ECC_DB_ERR
,
4412 &bar0
->mac_tmac_err_reg
,
4413 &sw_stat
->mac_tmac_err_cnt
);
4416 val64
= readq(&bar0
->xgxs_int_status
);
4417 if (val64
& XGXS_INT_STATUS_TXGXS
) {
4418 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW
| TXGXS_TX_SM_ERR
,
4419 &bar0
->xgxs_txgxs_err_reg
,
4420 &sw_stat
->xgxs_txgxs_err_cnt
))
4422 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR
| TXGXS_ECC_DB_ERR
,
4423 &bar0
->xgxs_txgxs_err_reg
,
4424 &sw_stat
->xgxs_txgxs_err_cnt
);
4427 val64
= readq(&bar0
->rxdma_int_status
);
4428 if (val64
& RXDMA_INT_RC_INT_M
) {
4429 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR
| RC_FTC_ECC_DB_ERR
4430 | RC_PRCn_SM_ERR_ALARM
|RC_FTC_SM_ERR_ALARM
,
4431 &bar0
->rc_err_reg
, &sw_stat
->rc_err_cnt
))
4433 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR
| RC_FTC_ECC_SG_ERR
4434 | RC_RDA_FAIL_WR_Rn
, &bar0
->rc_err_reg
,
4435 &sw_stat
->rc_err_cnt
);
4436 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn
| PRC_PCI_AB_WR_Rn
4437 | PRC_PCI_AB_F_WR_Rn
, &bar0
->prc_pcix_err_reg
,
4438 &sw_stat
->prc_pcix_err_cnt
))
4440 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn
| PRC_PCI_DP_WR_Rn
4441 | PRC_PCI_DP_F_WR_Rn
, &bar0
->prc_pcix_err_reg
,
4442 &sw_stat
->prc_pcix_err_cnt
);
4445 if (val64
& RXDMA_INT_RPA_INT_M
) {
4446 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM
| RPA_CREDIT_ERR
,
4447 &bar0
->rpa_err_reg
, &sw_stat
->rpa_err_cnt
))
4449 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR
| RPA_ECC_DB_ERR
,
4450 &bar0
->rpa_err_reg
, &sw_stat
->rpa_err_cnt
);
4453 if (val64
& RXDMA_INT_RDA_INT_M
) {
4454 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4455 | RDA_FRM_ECC_DB_N_AERR
| RDA_SM1_ERR_ALARM
4456 | RDA_SM0_ERR_ALARM
| RDA_RXD_ECC_DB_SERR
,
4457 &bar0
->rda_err_reg
, &sw_stat
->rda_err_cnt
))
4459 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR
| RDA_FRM_ECC_SG_ERR
4460 | RDA_MISC_ERR
| RDA_PCIX_ERR
,
4461 &bar0
->rda_err_reg
, &sw_stat
->rda_err_cnt
);
4464 if (val64
& RXDMA_INT_RTI_INT_M
) {
4465 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM
, &bar0
->rti_err_reg
,
4466 &sw_stat
->rti_err_cnt
))
4468 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR
| RTI_ECC_DB_ERR
,
4469 &bar0
->rti_err_reg
, &sw_stat
->rti_err_cnt
);
4472 val64
= readq(&bar0
->mac_int_status
);
4473 if (val64
& MAC_INT_STATUS_RMAC_INT
) {
4474 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN
| RMAC_RX_SM_ERR
,
4475 &bar0
->mac_rmac_err_reg
,
4476 &sw_stat
->mac_rmac_err_cnt
))
4478 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT
|RMAC_SINGLE_ECC_ERR
|
4479 RMAC_DOUBLE_ECC_ERR
, &bar0
->mac_rmac_err_reg
,
4480 &sw_stat
->mac_rmac_err_cnt
);
4483 val64
= readq(&bar0
->xgxs_int_status
);
4484 if (val64
& XGXS_INT_STATUS_RXGXS
) {
4485 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW
| RXGXS_RX_SM_ERR
,
4486 &bar0
->xgxs_rxgxs_err_reg
,
4487 &sw_stat
->xgxs_rxgxs_err_cnt
))
4491 val64
= readq(&bar0
->mc_int_status
);
4492 if(val64
& MC_INT_STATUS_MC_INT
) {
4493 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR
, &bar0
->mc_err_reg
,
4494 &sw_stat
->mc_err_cnt
))
4497 /* Handling Ecc errors */
4498 if (val64
& (MC_ERR_REG_ECC_ALL_SNG
| MC_ERR_REG_ECC_ALL_DBL
)) {
4499 writeq(val64
, &bar0
->mc_err_reg
);
4500 if (val64
& MC_ERR_REG_ECC_ALL_DBL
) {
4501 sw_stat
->double_ecc_errs
++;
4502 if (sp
->device_type
!= XFRAME_II_DEVICE
) {
4504 * Reset XframeI only if critical error
4507 (MC_ERR_REG_MIRI_ECC_DB_ERR_0
|
4508 MC_ERR_REG_MIRI_ECC_DB_ERR_1
))
4512 sw_stat
->single_ecc_errs
++;
4518 netif_stop_queue(dev
);
4519 schedule_work(&sp
->rst_timer_task
);
4520 sw_stat
->soft_reset_cnt
++;
4525 * s2io_isr - ISR handler of the device .
4526 * @irq: the irq of the device.
4527 * @dev_id: a void pointer to the dev structure of the NIC.
4528 * Description: This function is the ISR handler of the device. It
4529 * identifies the reason for the interrupt and calls the relevant
4530 * service routines. As a contongency measure, this ISR allocates the
4531 * recv buffers, if their numbers are below the panic value which is
4532 * presently set to 25% of the original number of rcv buffers allocated.
4534 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4535 * IRQ_NONE: will be returned if interrupt is not from our device
4537 static irqreturn_t
s2io_isr(int irq
, void *dev_id
)
4539 struct net_device
*dev
= (struct net_device
*) dev_id
;
4540 struct s2io_nic
*sp
= dev
->priv
;
4541 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4544 struct mac_info
*mac_control
;
4545 struct config_param
*config
;
4547 /* Pretend we handled any irq's from a disconnected card */
4548 if (pci_channel_offline(sp
->pdev
))
4551 if (!is_s2io_card_up(sp
))
4554 mac_control
= &sp
->mac_control
;
4555 config
= &sp
->config
;
4558 * Identify the cause for interrupt and call the appropriate
4559 * interrupt handler. Causes for the interrupt could be;
4564 reason
= readq(&bar0
->general_int_status
);
4566 if (unlikely(reason
== S2IO_MINUS_ONE
) ) {
4567 /* Nothing much can be done. Get out */
4571 if (reason
& (GEN_INTR_RXTRAFFIC
|
4572 GEN_INTR_TXTRAFFIC
| GEN_INTR_TXPIC
))
4574 writeq(S2IO_MINUS_ONE
, &bar0
->general_int_mask
);
4577 if (reason
& GEN_INTR_RXTRAFFIC
) {
4578 if (likely(netif_rx_schedule_prep(dev
,
4580 __netif_rx_schedule(dev
, &sp
->napi
);
4581 writeq(S2IO_MINUS_ONE
,
4582 &bar0
->rx_traffic_mask
);
4584 writeq(S2IO_MINUS_ONE
,
4585 &bar0
->rx_traffic_int
);
4589 * rx_traffic_int reg is an R1 register, writing all 1's
4590 * will ensure that the actual interrupt causing bit
4591 * get's cleared and hence a read can be avoided.
4593 if (reason
& GEN_INTR_RXTRAFFIC
)
4594 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4596 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4597 rx_intr_handler(&mac_control
->rings
[i
]);
4601 * tx_traffic_int reg is an R1 register, writing all 1's
4602 * will ensure that the actual interrupt causing bit get's
4603 * cleared and hence a read can be avoided.
4605 if (reason
& GEN_INTR_TXTRAFFIC
)
4606 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4608 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4609 tx_intr_handler(&mac_control
->fifos
[i
]);
4611 if (reason
& GEN_INTR_TXPIC
)
4612 s2io_txpic_intr_handle(sp
);
4615 * Reallocate the buffers from the interrupt handler itself.
4617 if (!config
->napi
) {
4618 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4619 s2io_chk_rx_buffers(sp
, i
);
4621 writeq(sp
->general_int_mask
, &bar0
->general_int_mask
);
4622 readl(&bar0
->general_int_status
);
4628 /* The interrupt was not raised by us */
4638 static void s2io_updt_stats(struct s2io_nic
*sp
)
4640 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4644 if (is_s2io_card_up(sp
)) {
4645 /* Apprx 30us on a 133 MHz bus */
4646 val64
= SET_UPDT_CLICKS(10) |
4647 STAT_CFG_ONE_SHOT_EN
| STAT_CFG_STAT_EN
;
4648 writeq(val64
, &bar0
->stat_cfg
);
4651 val64
= readq(&bar0
->stat_cfg
);
4652 if (!(val64
& s2BIT(0)))
4656 break; /* Updt failed */
4662 * s2io_get_stats - Updates the device statistics structure.
4663 * @dev : pointer to the device structure.
4665 * This function updates the device statistics structure in the s2io_nic
4666 * structure and returns a pointer to the same.
4668 * pointer to the updated net_device_stats structure.
4671 static struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
4673 struct s2io_nic
*sp
= dev
->priv
;
4674 struct mac_info
*mac_control
;
4675 struct config_param
*config
;
4678 mac_control
= &sp
->mac_control
;
4679 config
= &sp
->config
;
4681 /* Configure Stats for immediate updt */
4682 s2io_updt_stats(sp
);
4684 sp
->stats
.tx_packets
=
4685 le32_to_cpu(mac_control
->stats_info
->tmac_frms
);
4686 sp
->stats
.tx_errors
=
4687 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
);
4688 sp
->stats
.rx_errors
=
4689 le64_to_cpu(mac_control
->stats_info
->rmac_drop_frms
);
4690 sp
->stats
.multicast
=
4691 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
);
4692 sp
->stats
.rx_length_errors
=
4693 le64_to_cpu(mac_control
->stats_info
->rmac_long_frms
);
4695 return (&sp
->stats
);
4699 * s2io_set_multicast - entry point for multicast address enable/disable.
4700 * @dev : pointer to the device structure
4702 * This function is a driver entry point which gets called by the kernel
4703 * whenever multicast addresses must be enabled/disabled. This also gets
4704 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4705 * determine, if multicast address must be enabled or if promiscuous mode
4706 * is to be disabled etc.
4711 static void s2io_set_multicast(struct net_device
*dev
)
4714 struct dev_mc_list
*mclist
;
4715 struct s2io_nic
*sp
= dev
->priv
;
4716 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4717 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
4719 u64 dis_addr
= 0xffffffffffffULL
, mac_addr
= 0;
4722 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
4723 /* Enable all Multicast addresses */
4724 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
4725 &bar0
->rmac_addr_data0_mem
);
4726 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
4727 &bar0
->rmac_addr_data1_mem
);
4728 val64
= RMAC_ADDR_CMD_MEM_WE
|
4729 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4730 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET
);
4731 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4732 /* Wait till command completes */
4733 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4734 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4738 sp
->all_multi_pos
= MAC_MC_ALL_MC_ADDR_OFFSET
;
4739 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
4740 /* Disable all Multicast addresses */
4741 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4742 &bar0
->rmac_addr_data0_mem
);
4743 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4744 &bar0
->rmac_addr_data1_mem
);
4745 val64
= RMAC_ADDR_CMD_MEM_WE
|
4746 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4747 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
4748 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4749 /* Wait till command completes */
4750 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4751 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4755 sp
->all_multi_pos
= 0;
4758 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
4759 /* Put the NIC into promiscuous mode */
4760 add
= &bar0
->mac_cfg
;
4761 val64
= readq(&bar0
->mac_cfg
);
4762 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
4764 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4765 writel((u32
) val64
, add
);
4766 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4767 writel((u32
) (val64
>> 32), (add
+ 4));
4769 if (vlan_tag_strip
!= 1) {
4770 val64
= readq(&bar0
->rx_pa_cfg
);
4771 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
4772 writeq(val64
, &bar0
->rx_pa_cfg
);
4773 vlan_strip_flag
= 0;
4776 val64
= readq(&bar0
->mac_cfg
);
4777 sp
->promisc_flg
= 1;
4778 DBG_PRINT(INFO_DBG
, "%s: entered promiscuous mode\n",
4780 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
4781 /* Remove the NIC from promiscuous mode */
4782 add
= &bar0
->mac_cfg
;
4783 val64
= readq(&bar0
->mac_cfg
);
4784 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
4786 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4787 writel((u32
) val64
, add
);
4788 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4789 writel((u32
) (val64
>> 32), (add
+ 4));
4791 if (vlan_tag_strip
!= 0) {
4792 val64
= readq(&bar0
->rx_pa_cfg
);
4793 val64
|= RX_PA_CFG_STRIP_VLAN_TAG
;
4794 writeq(val64
, &bar0
->rx_pa_cfg
);
4795 vlan_strip_flag
= 1;
4798 val64
= readq(&bar0
->mac_cfg
);
4799 sp
->promisc_flg
= 0;
4800 DBG_PRINT(INFO_DBG
, "%s: left promiscuous mode\n",
4804 /* Update individual M_CAST address list */
4805 if ((!sp
->m_cast_flg
) && dev
->mc_count
) {
4807 (MAX_ADDRS_SUPPORTED
- MAC_MC_ADDR_START_OFFSET
- 1)) {
4808 DBG_PRINT(ERR_DBG
, "%s: No more Rx filters ",
4810 DBG_PRINT(ERR_DBG
, "can be added, please enable ");
4811 DBG_PRINT(ERR_DBG
, "ALL_MULTI instead\n");
4815 prev_cnt
= sp
->mc_addr_count
;
4816 sp
->mc_addr_count
= dev
->mc_count
;
4818 /* Clear out the previous list of Mc in the H/W. */
4819 for (i
= 0; i
< prev_cnt
; i
++) {
4820 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4821 &bar0
->rmac_addr_data0_mem
);
4822 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4823 &bar0
->rmac_addr_data1_mem
);
4824 val64
= RMAC_ADDR_CMD_MEM_WE
|
4825 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4826 RMAC_ADDR_CMD_MEM_OFFSET
4827 (MAC_MC_ADDR_START_OFFSET
+ i
);
4828 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4830 /* Wait for command completes */
4831 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4832 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4834 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4836 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4841 /* Create the new Rx filter list and update the same in H/W. */
4842 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
4843 i
++, mclist
= mclist
->next
) {
4844 memcpy(sp
->usr_addrs
[i
].addr
, mclist
->dmi_addr
,
4847 for (j
= 0; j
< ETH_ALEN
; j
++) {
4848 mac_addr
|= mclist
->dmi_addr
[j
];
4852 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4853 &bar0
->rmac_addr_data0_mem
);
4854 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4855 &bar0
->rmac_addr_data1_mem
);
4856 val64
= RMAC_ADDR_CMD_MEM_WE
|
4857 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4858 RMAC_ADDR_CMD_MEM_OFFSET
4859 (i
+ MAC_MC_ADDR_START_OFFSET
);
4860 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4862 /* Wait for command completes */
4863 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4864 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4866 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4868 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4875 /* add unicast MAC address to CAM */
4876 static int do_s2io_add_unicast(struct s2io_nic
*sp
, u64 addr
, int off
)
4879 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4881 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr
),
4882 &bar0
->rmac_addr_data0_mem
);
4885 RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4886 RMAC_ADDR_CMD_MEM_OFFSET(off
);
4887 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4889 /* Wait till command completes */
4890 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4891 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4893 DBG_PRINT(INFO_DBG
, "add_mac_addr failed\n");
4900 * s2io_set_mac_addr driver entry point
4902 static int s2io_set_mac_addr(struct net_device
*dev
, void *p
)
4904 struct sockaddr
*addr
= p
;
4906 if (!is_valid_ether_addr(addr
->sa_data
))
4909 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
4911 /* store the MAC address in CAM */
4912 return (do_s2io_prog_unicast(dev
, dev
->dev_addr
));
4916 * do_s2io_prog_unicast - Programs the Xframe mac address
4917 * @dev : pointer to the device structure.
4918 * @addr: a uchar pointer to the new mac address which is to be set.
4919 * Description : This procedure will program the Xframe to receive
4920 * frames with new Mac Address
4921 * Return value: SUCCESS on success and an appropriate (-)ve integer
4922 * as defined in errno.h file on failure.
4924 static int do_s2io_prog_unicast(struct net_device
*dev
, u8
*addr
)
4926 struct s2io_nic
*sp
= dev
->priv
;
4927 register u64 mac_addr
= 0, perm_addr
= 0;
4931 * Set the new MAC address as the new unicast filter and reflect this
4932 * change on the device address registered with the OS. It will be
4935 for (i
= 0; i
< ETH_ALEN
; i
++) {
4937 mac_addr
|= addr
[i
];
4939 perm_addr
|= sp
->def_mac_addr
[0].mac_addr
[i
];
4942 /* check if the dev_addr is different than perm_addr */
4943 if (mac_addr
== perm_addr
)
4946 /* Update the internal structure with this new mac address */
4947 do_s2io_copy_mac_addr(sp
, 0, mac_addr
);
4948 return (do_s2io_add_unicast(sp
, mac_addr
, 0));
4952 * s2io_ethtool_sset - Sets different link parameters.
4953 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4954 * @info: pointer to the structure with parameters given by ethtool to set
4957 * The function sets different link parameters provided by the user onto
4963 static int s2io_ethtool_sset(struct net_device
*dev
,
4964 struct ethtool_cmd
*info
)
4966 struct s2io_nic
*sp
= dev
->priv
;
4967 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
4968 (info
->speed
!= SPEED_10000
) || (info
->duplex
!= DUPLEX_FULL
))
4971 s2io_close(sp
->dev
);
4979 * s2io_ethtol_gset - Return link specific information.
4980 * @sp : private member of the device structure, pointer to the
4981 * s2io_nic structure.
4982 * @info : pointer to the structure with parameters given by ethtool
4983 * to return link information.
4985 * Returns link specific information like speed, duplex etc.. to ethtool.
4987 * return 0 on success.
4990 static int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
4992 struct s2io_nic
*sp
= dev
->priv
;
4993 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4994 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4995 info
->port
= PORT_FIBRE
;
4997 /* info->transceiver */
4998 info
->transceiver
= XCVR_EXTERNAL
;
5000 if (netif_carrier_ok(sp
->dev
)) {
5001 info
->speed
= 10000;
5002 info
->duplex
= DUPLEX_FULL
;
5008 info
->autoneg
= AUTONEG_DISABLE
;
5013 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5014 * @sp : private member of the device structure, which is a pointer to the
5015 * s2io_nic structure.
5016 * @info : pointer to the structure with parameters given by ethtool to
5017 * return driver information.
5019 * Returns driver specefic information like name, version etc.. to ethtool.
5024 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
5025 struct ethtool_drvinfo
*info
)
5027 struct s2io_nic
*sp
= dev
->priv
;
5029 strncpy(info
->driver
, s2io_driver_name
, sizeof(info
->driver
));
5030 strncpy(info
->version
, s2io_driver_version
, sizeof(info
->version
));
5031 strncpy(info
->fw_version
, "", sizeof(info
->fw_version
));
5032 strncpy(info
->bus_info
, pci_name(sp
->pdev
), sizeof(info
->bus_info
));
5033 info
->regdump_len
= XENA_REG_SPACE
;
5034 info
->eedump_len
= XENA_EEPROM_SPACE
;
5038 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5039 * @sp: private member of the device structure, which is a pointer to the
5040 * s2io_nic structure.
5041 * @regs : pointer to the structure with parameters given by ethtool for
5042 * dumping the registers.
5043 * @reg_space: The input argumnet into which all the registers are dumped.
5045 * Dumps the entire register space of xFrame NIC into the user given
5051 static void s2io_ethtool_gregs(struct net_device
*dev
,
5052 struct ethtool_regs
*regs
, void *space
)
5056 u8
*reg_space
= (u8
*) space
;
5057 struct s2io_nic
*sp
= dev
->priv
;
5059 regs
->len
= XENA_REG_SPACE
;
5060 regs
->version
= sp
->pdev
->subsystem_device
;
5062 for (i
= 0; i
< regs
->len
; i
+= 8) {
5063 reg
= readq(sp
->bar0
+ i
);
5064 memcpy((reg_space
+ i
), ®
, 8);
5069 * s2io_phy_id - timer function that alternates adapter LED.
5070 * @data : address of the private member of the device structure, which
5071 * is a pointer to the s2io_nic structure, provided as an u32.
5072 * Description: This is actually the timer function that alternates the
5073 * adapter LED bit of the adapter control bit to set/reset every time on
5074 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5075 * once every second.
5077 static void s2io_phy_id(unsigned long data
)
5079 struct s2io_nic
*sp
= (struct s2io_nic
*) data
;
5080 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5084 subid
= sp
->pdev
->subsystem_device
;
5085 if ((sp
->device_type
== XFRAME_II_DEVICE
) ||
5086 ((subid
& 0xFF) >= 0x07)) {
5087 val64
= readq(&bar0
->gpio_control
);
5088 val64
^= GPIO_CTRL_GPIO_0
;
5089 writeq(val64
, &bar0
->gpio_control
);
5091 val64
= readq(&bar0
->adapter_control
);
5092 val64
^= ADAPTER_LED_ON
;
5093 writeq(val64
, &bar0
->adapter_control
);
5096 mod_timer(&sp
->id_timer
, jiffies
+ HZ
/ 2);
5100 * s2io_ethtool_idnic - To physically identify the nic on the system.
5101 * @sp : private member of the device structure, which is a pointer to the
5102 * s2io_nic structure.
5103 * @id : pointer to the structure with identification parameters given by
5105 * Description: Used to physically identify the NIC on the system.
5106 * The Link LED will blink for a time specified by the user for
5108 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5109 * identification is possible only if it's link is up.
5111 * int , returns 0 on success
5114 static int s2io_ethtool_idnic(struct net_device
*dev
, u32 data
)
5116 u64 val64
= 0, last_gpio_ctrl_val
;
5117 struct s2io_nic
*sp
= dev
->priv
;
5118 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5121 subid
= sp
->pdev
->subsystem_device
;
5122 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
5123 if ((sp
->device_type
== XFRAME_I_DEVICE
) &&
5124 ((subid
& 0xFF) < 0x07)) {
5125 val64
= readq(&bar0
->adapter_control
);
5126 if (!(val64
& ADAPTER_CNTL_EN
)) {
5128 "Adapter Link down, cannot blink LED\n");
5132 if (sp
->id_timer
.function
== NULL
) {
5133 init_timer(&sp
->id_timer
);
5134 sp
->id_timer
.function
= s2io_phy_id
;
5135 sp
->id_timer
.data
= (unsigned long) sp
;
5137 mod_timer(&sp
->id_timer
, jiffies
);
5139 msleep_interruptible(data
* HZ
);
5141 msleep_interruptible(MAX_FLICKER_TIME
);
5142 del_timer_sync(&sp
->id_timer
);
5144 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp
->device_type
, subid
)) {
5145 writeq(last_gpio_ctrl_val
, &bar0
->gpio_control
);
5146 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
5152 static void s2io_ethtool_gringparam(struct net_device
*dev
,
5153 struct ethtool_ringparam
*ering
)
5155 struct s2io_nic
*sp
= dev
->priv
;
5156 int i
,tx_desc_count
=0,rx_desc_count
=0;
5158 if (sp
->rxd_mode
== RXD_MODE_1
)
5159 ering
->rx_max_pending
= MAX_RX_DESC_1
;
5160 else if (sp
->rxd_mode
== RXD_MODE_3B
)
5161 ering
->rx_max_pending
= MAX_RX_DESC_2
;
5163 ering
->tx_max_pending
= MAX_TX_DESC
;
5164 for (i
= 0 ; i
< sp
->config
.tx_fifo_num
; i
++)
5165 tx_desc_count
+= sp
->config
.tx_cfg
[i
].fifo_len
;
5167 DBG_PRINT(INFO_DBG
,"\nmax txds : %d\n",sp
->config
.max_txds
);
5168 ering
->tx_pending
= tx_desc_count
;
5170 for (i
= 0 ; i
< sp
->config
.rx_ring_num
; i
++)
5171 rx_desc_count
+= sp
->config
.rx_cfg
[i
].num_rxd
;
5173 ering
->rx_pending
= rx_desc_count
;
5175 ering
->rx_mini_max_pending
= 0;
5176 ering
->rx_mini_pending
= 0;
5177 if(sp
->rxd_mode
== RXD_MODE_1
)
5178 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_1
;
5179 else if (sp
->rxd_mode
== RXD_MODE_3B
)
5180 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_2
;
5181 ering
->rx_jumbo_pending
= rx_desc_count
;
5185 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5186 * @sp : private member of the device structure, which is a pointer to the
5187 * s2io_nic structure.
5188 * @ep : pointer to the structure with pause parameters given by ethtool.
5190 * Returns the Pause frame generation and reception capability of the NIC.
5194 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
5195 struct ethtool_pauseparam
*ep
)
5198 struct s2io_nic
*sp
= dev
->priv
;
5199 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5201 val64
= readq(&bar0
->rmac_pause_cfg
);
5202 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
5203 ep
->tx_pause
= TRUE
;
5204 if (val64
& RMAC_PAUSE_RX_ENABLE
)
5205 ep
->rx_pause
= TRUE
;
5206 ep
->autoneg
= FALSE
;
5210 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5211 * @sp : private member of the device structure, which is a pointer to the
5212 * s2io_nic structure.
5213 * @ep : pointer to the structure with pause parameters given by ethtool.
5215 * It can be used to set or reset Pause frame generation or reception
5216 * support of the NIC.
5218 * int, returns 0 on Success
5221 static int s2io_ethtool_setpause_data(struct net_device
*dev
,
5222 struct ethtool_pauseparam
*ep
)
5225 struct s2io_nic
*sp
= dev
->priv
;
5226 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5228 val64
= readq(&bar0
->rmac_pause_cfg
);
5230 val64
|= RMAC_PAUSE_GEN_ENABLE
;
5232 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
5234 val64
|= RMAC_PAUSE_RX_ENABLE
;
5236 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
5237 writeq(val64
, &bar0
->rmac_pause_cfg
);
5242 * read_eeprom - reads 4 bytes of data from user given offset.
5243 * @sp : private member of the device structure, which is a pointer to the
5244 * s2io_nic structure.
5245 * @off : offset at which the data must be written
5246 * @data : Its an output parameter where the data read at the given
5249 * Will read 4 bytes of data from the user given offset and return the
5251 * NOTE: Will allow to read only part of the EEPROM visible through the
5254 * -1 on failure and 0 on success.
5257 #define S2IO_DEV_ID 5
5258 static int read_eeprom(struct s2io_nic
* sp
, int off
, u64
* data
)
5263 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5265 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5266 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5267 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ
|
5268 I2C_CONTROL_CNTL_START
;
5269 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5271 while (exit_cnt
< 5) {
5272 val64
= readq(&bar0
->i2c_control
);
5273 if (I2C_CONTROL_CNTL_END(val64
)) {
5274 *data
= I2C_CONTROL_GET_DATA(val64
);
5283 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5284 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5285 SPI_CONTROL_BYTECNT(0x3) |
5286 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off
);
5287 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5288 val64
|= SPI_CONTROL_REQ
;
5289 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5290 while (exit_cnt
< 5) {
5291 val64
= readq(&bar0
->spi_control
);
5292 if (val64
& SPI_CONTROL_NACK
) {
5295 } else if (val64
& SPI_CONTROL_DONE
) {
5296 *data
= readq(&bar0
->spi_data
);
5309 * write_eeprom - actually writes the relevant part of the data value.
5310 * @sp : private member of the device structure, which is a pointer to the
5311 * s2io_nic structure.
5312 * @off : offset at which the data must be written
5313 * @data : The data that is to be written
5314 * @cnt : Number of bytes of the data that are actually to be written into
5315 * the Eeprom. (max of 3)
5317 * Actually writes the relevant part of the data value into the Eeprom
5318 * through the I2C bus.
5320 * 0 on success, -1 on failure.
5323 static int write_eeprom(struct s2io_nic
* sp
, int off
, u64 data
, int cnt
)
5325 int exit_cnt
= 0, ret
= -1;
5327 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5329 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5330 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5331 I2C_CONTROL_BYTE_CNT(cnt
) | I2C_CONTROL_SET_DATA((u32
)data
) |
5332 I2C_CONTROL_CNTL_START
;
5333 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5335 while (exit_cnt
< 5) {
5336 val64
= readq(&bar0
->i2c_control
);
5337 if (I2C_CONTROL_CNTL_END(val64
)) {
5338 if (!(val64
& I2C_CONTROL_NACK
))
5347 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5348 int write_cnt
= (cnt
== 8) ? 0 : cnt
;
5349 writeq(SPI_DATA_WRITE(data
,(cnt
<<3)), &bar0
->spi_data
);
5351 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5352 SPI_CONTROL_BYTECNT(write_cnt
) |
5353 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off
);
5354 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5355 val64
|= SPI_CONTROL_REQ
;
5356 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5357 while (exit_cnt
< 5) {
5358 val64
= readq(&bar0
->spi_control
);
5359 if (val64
& SPI_CONTROL_NACK
) {
5362 } else if (val64
& SPI_CONTROL_DONE
) {
5372 static void s2io_vpd_read(struct s2io_nic
*nic
)
5376 int i
=0, cnt
, fail
= 0;
5377 int vpd_addr
= 0x80;
5379 if (nic
->device_type
== XFRAME_II_DEVICE
) {
5380 strcpy(nic
->product_name
, "Xframe II 10GbE network adapter");
5384 strcpy(nic
->product_name
, "Xframe I 10GbE network adapter");
5387 strcpy(nic
->serial_num
, "NOT AVAILABLE");
5389 vpd_data
= kmalloc(256, GFP_KERNEL
);
5391 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
5394 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
+= 256;
5396 for (i
= 0; i
< 256; i
+=4 ) {
5397 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 2), i
);
5398 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 2), &data
);
5399 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 3), 0);
5400 for (cnt
= 0; cnt
<5; cnt
++) {
5402 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 3), &data
);
5407 DBG_PRINT(ERR_DBG
, "Read of VPD data failed\n");
5411 pci_read_config_dword(nic
->pdev
, (vpd_addr
+ 4),
5412 (u32
*)&vpd_data
[i
]);
5416 /* read serial number of adapter */
5417 for (cnt
= 0; cnt
< 256; cnt
++) {
5418 if ((vpd_data
[cnt
] == 'S') &&
5419 (vpd_data
[cnt
+1] == 'N') &&
5420 (vpd_data
[cnt
+2] < VPD_STRING_LEN
)) {
5421 memset(nic
->serial_num
, 0, VPD_STRING_LEN
);
5422 memcpy(nic
->serial_num
, &vpd_data
[cnt
+ 3],
5429 if ((!fail
) && (vpd_data
[1] < VPD_STRING_LEN
)) {
5430 memset(nic
->product_name
, 0, vpd_data
[1]);
5431 memcpy(nic
->product_name
, &vpd_data
[3], vpd_data
[1]);
5434 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= 256;
5438 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5439 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5440 * @eeprom : pointer to the user level structure provided by ethtool,
5441 * containing all relevant information.
5442 * @data_buf : user defined value to be written into Eeprom.
5443 * Description: Reads the values stored in the Eeprom at given offset
5444 * for a given length. Stores these values int the input argument data
5445 * buffer 'data_buf' and returns these to the caller (ethtool.)
5450 static int s2io_ethtool_geeprom(struct net_device
*dev
,
5451 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
5455 struct s2io_nic
*sp
= dev
->priv
;
5457 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
5459 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
5460 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
5462 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
5463 if (read_eeprom(sp
, (eeprom
->offset
+ i
), &data
)) {
5464 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
5468 memcpy((data_buf
+ i
), &valid
, 4);
5474 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5475 * @sp : private member of the device structure, which is a pointer to the
5476 * s2io_nic structure.
5477 * @eeprom : pointer to the user level structure provided by ethtool,
5478 * containing all relevant information.
5479 * @data_buf ; user defined value to be written into Eeprom.
5481 * Tries to write the user provided value in the Eeprom, at the offset
5482 * given by the user.
5484 * 0 on success, -EFAULT on failure.
5487 static int s2io_ethtool_seeprom(struct net_device
*dev
,
5488 struct ethtool_eeprom
*eeprom
,
5491 int len
= eeprom
->len
, cnt
= 0;
5492 u64 valid
= 0, data
;
5493 struct s2io_nic
*sp
= dev
->priv
;
5495 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
5497 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5498 DBG_PRINT(ERR_DBG
, "is wrong, Its not 0x%x\n",
5504 data
= (u32
) data_buf
[cnt
] & 0x000000FF;
5506 valid
= (u32
) (data
<< 24);
5510 if (write_eeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
5512 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5514 "write into the specified offset\n");
5525 * s2io_register_test - reads and writes into all clock domains.
5526 * @sp : private member of the device structure, which is a pointer to the
5527 * s2io_nic structure.
5528 * @data : variable that returns the result of each of the test conducted b
5531 * Read and write into all clock domains. The NIC has 3 clock domains,
5532 * see that registers in all the three regions are accessible.
5537 static int s2io_register_test(struct s2io_nic
* sp
, uint64_t * data
)
5539 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5540 u64 val64
= 0, exp_val
;
5543 val64
= readq(&bar0
->pif_rd_swapper_fb
);
5544 if (val64
!= 0x123456789abcdefULL
) {
5546 DBG_PRINT(INFO_DBG
, "Read Test level 1 fails\n");
5549 val64
= readq(&bar0
->rmac_pause_cfg
);
5550 if (val64
!= 0xc000ffff00000000ULL
) {
5552 DBG_PRINT(INFO_DBG
, "Read Test level 2 fails\n");
5555 val64
= readq(&bar0
->rx_queue_cfg
);
5556 if (sp
->device_type
== XFRAME_II_DEVICE
)
5557 exp_val
= 0x0404040404040404ULL
;
5559 exp_val
= 0x0808080808080808ULL
;
5560 if (val64
!= exp_val
) {
5562 DBG_PRINT(INFO_DBG
, "Read Test level 3 fails\n");
5565 val64
= readq(&bar0
->xgxs_efifo_cfg
);
5566 if (val64
!= 0x000000001923141EULL
) {
5568 DBG_PRINT(INFO_DBG
, "Read Test level 4 fails\n");
5571 val64
= 0x5A5A5A5A5A5A5A5AULL
;
5572 writeq(val64
, &bar0
->xmsi_data
);
5573 val64
= readq(&bar0
->xmsi_data
);
5574 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
5576 DBG_PRINT(ERR_DBG
, "Write Test level 1 fails\n");
5579 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
5580 writeq(val64
, &bar0
->xmsi_data
);
5581 val64
= readq(&bar0
->xmsi_data
);
5582 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
5584 DBG_PRINT(ERR_DBG
, "Write Test level 2 fails\n");
5592 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5593 * @sp : private member of the device structure, which is a pointer to the
5594 * s2io_nic structure.
5595 * @data:variable that returns the result of each of the test conducted by
5598 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5604 static int s2io_eeprom_test(struct s2io_nic
* sp
, uint64_t * data
)
5607 u64 ret_data
, org_4F0
, org_7F0
;
5608 u8 saved_4F0
= 0, saved_7F0
= 0;
5609 struct net_device
*dev
= sp
->dev
;
5611 /* Test Write Error at offset 0 */
5612 /* Note that SPI interface allows write access to all areas
5613 * of EEPROM. Hence doing all negative testing only for Xframe I.
5615 if (sp
->device_type
== XFRAME_I_DEVICE
)
5616 if (!write_eeprom(sp
, 0, 0, 3))
5619 /* Save current values at offsets 0x4F0 and 0x7F0 */
5620 if (!read_eeprom(sp
, 0x4F0, &org_4F0
))
5622 if (!read_eeprom(sp
, 0x7F0, &org_7F0
))
5625 /* Test Write at offset 4f0 */
5626 if (write_eeprom(sp
, 0x4F0, 0x012345, 3))
5628 if (read_eeprom(sp
, 0x4F0, &ret_data
))
5631 if (ret_data
!= 0x012345) {
5632 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x4F0. "
5633 "Data written %llx Data read %llx\n",
5634 dev
->name
, (unsigned long long)0x12345,
5635 (unsigned long long)ret_data
);
5639 /* Reset the EEPROM data go FFFF */
5640 write_eeprom(sp
, 0x4F0, 0xFFFFFF, 3);
5642 /* Test Write Request Error at offset 0x7c */
5643 if (sp
->device_type
== XFRAME_I_DEVICE
)
5644 if (!write_eeprom(sp
, 0x07C, 0, 3))
5647 /* Test Write Request at offset 0x7f0 */
5648 if (write_eeprom(sp
, 0x7F0, 0x012345, 3))
5650 if (read_eeprom(sp
, 0x7F0, &ret_data
))
5653 if (ret_data
!= 0x012345) {
5654 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x7F0. "
5655 "Data written %llx Data read %llx\n",
5656 dev
->name
, (unsigned long long)0x12345,
5657 (unsigned long long)ret_data
);
5661 /* Reset the EEPROM data go FFFF */
5662 write_eeprom(sp
, 0x7F0, 0xFFFFFF, 3);
5664 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5665 /* Test Write Error at offset 0x80 */
5666 if (!write_eeprom(sp
, 0x080, 0, 3))
5669 /* Test Write Error at offset 0xfc */
5670 if (!write_eeprom(sp
, 0x0FC, 0, 3))
5673 /* Test Write Error at offset 0x100 */
5674 if (!write_eeprom(sp
, 0x100, 0, 3))
5677 /* Test Write Error at offset 4ec */
5678 if (!write_eeprom(sp
, 0x4EC, 0, 3))
5682 /* Restore values at offsets 0x4F0 and 0x7F0 */
5684 write_eeprom(sp
, 0x4F0, org_4F0
, 3);
5686 write_eeprom(sp
, 0x7F0, org_7F0
, 3);
5693 * s2io_bist_test - invokes the MemBist test of the card .
5694 * @sp : private member of the device structure, which is a pointer to the
5695 * s2io_nic structure.
5696 * @data:variable that returns the result of each of the test conducted by
5699 * This invokes the MemBist test of the card. We give around
5700 * 2 secs time for the Test to complete. If it's still not complete
5701 * within this peiod, we consider that the test failed.
5703 * 0 on success and -1 on failure.
5706 static int s2io_bist_test(struct s2io_nic
* sp
, uint64_t * data
)
5709 int cnt
= 0, ret
= -1;
5711 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
5712 bist
|= PCI_BIST_START
;
5713 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
5716 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
5717 if (!(bist
& PCI_BIST_START
)) {
5718 *data
= (bist
& PCI_BIST_CODE_MASK
);
5730 * s2io-link_test - verifies the link state of the nic
5731 * @sp ; private member of the device structure, which is a pointer to the
5732 * s2io_nic structure.
5733 * @data: variable that returns the result of each of the test conducted by
5736 * The function verifies the link state of the NIC and updates the input
5737 * argument 'data' appropriately.
5742 static int s2io_link_test(struct s2io_nic
* sp
, uint64_t * data
)
5744 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5747 val64
= readq(&bar0
->adapter_status
);
5748 if(!(LINK_IS_UP(val64
)))
5757 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5758 * @sp - private member of the device structure, which is a pointer to the
5759 * s2io_nic structure.
5760 * @data - variable that returns the result of each of the test
5761 * conducted by the driver.
5763 * This is one of the offline test that tests the read and write
5764 * access to the RldRam chip on the NIC.
5769 static int s2io_rldram_test(struct s2io_nic
* sp
, uint64_t * data
)
5771 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5773 int cnt
, iteration
= 0, test_fail
= 0;
5775 val64
= readq(&bar0
->adapter_control
);
5776 val64
&= ~ADAPTER_ECC_EN
;
5777 writeq(val64
, &bar0
->adapter_control
);
5779 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5780 val64
|= MC_RLDRAM_TEST_MODE
;
5781 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5783 val64
= readq(&bar0
->mc_rldram_mrs
);
5784 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
5785 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
5787 val64
|= MC_RLDRAM_MRS_ENABLE
;
5788 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
5790 while (iteration
< 2) {
5791 val64
= 0x55555555aaaa0000ULL
;
5792 if (iteration
== 1) {
5793 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5795 writeq(val64
, &bar0
->mc_rldram_test_d0
);
5797 val64
= 0xaaaa5a5555550000ULL
;
5798 if (iteration
== 1) {
5799 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5801 writeq(val64
, &bar0
->mc_rldram_test_d1
);
5803 val64
= 0x55aaaaaaaa5a0000ULL
;
5804 if (iteration
== 1) {
5805 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5807 writeq(val64
, &bar0
->mc_rldram_test_d2
);
5809 val64
= (u64
) (0x0000003ffffe0100ULL
);
5810 writeq(val64
, &bar0
->mc_rldram_test_add
);
5812 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_WRITE
|
5814 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5816 for (cnt
= 0; cnt
< 5; cnt
++) {
5817 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5818 if (val64
& MC_RLDRAM_TEST_DONE
)
5826 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
5827 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5829 for (cnt
= 0; cnt
< 5; cnt
++) {
5830 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5831 if (val64
& MC_RLDRAM_TEST_DONE
)
5839 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5840 if (!(val64
& MC_RLDRAM_TEST_PASS
))
5848 /* Bring the adapter out of test mode */
5849 SPECIAL_REG_WRITE(0, &bar0
->mc_rldram_test_ctrl
, LF
);
5855 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5856 * @sp : private member of the device structure, which is a pointer to the
5857 * s2io_nic structure.
5858 * @ethtest : pointer to a ethtool command specific structure that will be
5859 * returned to the user.
5860 * @data : variable that returns the result of each of the test
5861 * conducted by the driver.
5863 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5864 * the health of the card.
5869 static void s2io_ethtool_test(struct net_device
*dev
,
5870 struct ethtool_test
*ethtest
,
5873 struct s2io_nic
*sp
= dev
->priv
;
5874 int orig_state
= netif_running(sp
->dev
);
5876 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
5877 /* Offline Tests. */
5879 s2io_close(sp
->dev
);
5881 if (s2io_register_test(sp
, &data
[0]))
5882 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5886 if (s2io_rldram_test(sp
, &data
[3]))
5887 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5891 if (s2io_eeprom_test(sp
, &data
[1]))
5892 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5894 if (s2io_bist_test(sp
, &data
[4]))
5895 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5905 "%s: is not up, cannot run test\n",
5914 if (s2io_link_test(sp
, &data
[2]))
5915 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5924 static void s2io_get_ethtool_stats(struct net_device
*dev
,
5925 struct ethtool_stats
*estats
,
5929 struct s2io_nic
*sp
= dev
->priv
;
5930 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
5932 s2io_updt_stats(sp
);
5934 (u64
)le32_to_cpu(stat_info
->tmac_frms_oflow
) << 32 |
5935 le32_to_cpu(stat_info
->tmac_frms
);
5937 (u64
)le32_to_cpu(stat_info
->tmac_data_octets_oflow
) << 32 |
5938 le32_to_cpu(stat_info
->tmac_data_octets
);
5939 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_drop_frms
);
5941 (u64
)le32_to_cpu(stat_info
->tmac_mcst_frms_oflow
) << 32 |
5942 le32_to_cpu(stat_info
->tmac_mcst_frms
);
5944 (u64
)le32_to_cpu(stat_info
->tmac_bcst_frms_oflow
) << 32 |
5945 le32_to_cpu(stat_info
->tmac_bcst_frms
);
5946 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_pause_ctrl_frms
);
5948 (u64
)le32_to_cpu(stat_info
->tmac_ttl_octets_oflow
) << 32 |
5949 le32_to_cpu(stat_info
->tmac_ttl_octets
);
5951 (u64
)le32_to_cpu(stat_info
->tmac_ucst_frms_oflow
) << 32 |
5952 le32_to_cpu(stat_info
->tmac_ucst_frms
);
5954 (u64
)le32_to_cpu(stat_info
->tmac_nucst_frms_oflow
) << 32 |
5955 le32_to_cpu(stat_info
->tmac_nucst_frms
);
5957 (u64
)le32_to_cpu(stat_info
->tmac_any_err_frms_oflow
) << 32 |
5958 le32_to_cpu(stat_info
->tmac_any_err_frms
);
5959 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_ttl_less_fb_octets
);
5960 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_vld_ip_octets
);
5962 (u64
)le32_to_cpu(stat_info
->tmac_vld_ip_oflow
) << 32 |
5963 le32_to_cpu(stat_info
->tmac_vld_ip
);
5965 (u64
)le32_to_cpu(stat_info
->tmac_drop_ip_oflow
) << 32 |
5966 le32_to_cpu(stat_info
->tmac_drop_ip
);
5968 (u64
)le32_to_cpu(stat_info
->tmac_icmp_oflow
) << 32 |
5969 le32_to_cpu(stat_info
->tmac_icmp
);
5971 (u64
)le32_to_cpu(stat_info
->tmac_rst_tcp_oflow
) << 32 |
5972 le32_to_cpu(stat_info
->tmac_rst_tcp
);
5973 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_tcp
);
5974 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->tmac_udp_oflow
) << 32 |
5975 le32_to_cpu(stat_info
->tmac_udp
);
5977 (u64
)le32_to_cpu(stat_info
->rmac_vld_frms_oflow
) << 32 |
5978 le32_to_cpu(stat_info
->rmac_vld_frms
);
5980 (u64
)le32_to_cpu(stat_info
->rmac_data_octets_oflow
) << 32 |
5981 le32_to_cpu(stat_info
->rmac_data_octets
);
5982 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_fcs_err_frms
);
5983 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_drop_frms
);
5985 (u64
)le32_to_cpu(stat_info
->rmac_vld_mcst_frms_oflow
) << 32 |
5986 le32_to_cpu(stat_info
->rmac_vld_mcst_frms
);
5988 (u64
)le32_to_cpu(stat_info
->rmac_vld_bcst_frms_oflow
) << 32 |
5989 le32_to_cpu(stat_info
->rmac_vld_bcst_frms
);
5990 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_in_rng_len_err_frms
);
5991 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_out_rng_len_err_frms
);
5992 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_long_frms
);
5993 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_pause_ctrl_frms
);
5994 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_unsup_ctrl_frms
);
5996 (u64
)le32_to_cpu(stat_info
->rmac_ttl_octets_oflow
) << 32 |
5997 le32_to_cpu(stat_info
->rmac_ttl_octets
);
5999 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ucst_frms_oflow
)
6000 << 32 | le32_to_cpu(stat_info
->rmac_accepted_ucst_frms
);
6002 (u64
)le32_to_cpu(stat_info
->rmac_accepted_nucst_frms_oflow
)
6003 << 32 | le32_to_cpu(stat_info
->rmac_accepted_nucst_frms
);
6005 (u64
)le32_to_cpu(stat_info
->rmac_discarded_frms_oflow
) << 32 |
6006 le32_to_cpu(stat_info
->rmac_discarded_frms
);
6008 (u64
)le32_to_cpu(stat_info
->rmac_drop_events_oflow
)
6009 << 32 | le32_to_cpu(stat_info
->rmac_drop_events
);
6010 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_less_fb_octets
);
6011 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_frms
);
6013 (u64
)le32_to_cpu(stat_info
->rmac_usized_frms_oflow
) << 32 |
6014 le32_to_cpu(stat_info
->rmac_usized_frms
);
6016 (u64
)le32_to_cpu(stat_info
->rmac_osized_frms_oflow
) << 32 |
6017 le32_to_cpu(stat_info
->rmac_osized_frms
);
6019 (u64
)le32_to_cpu(stat_info
->rmac_frag_frms_oflow
) << 32 |
6020 le32_to_cpu(stat_info
->rmac_frag_frms
);
6022 (u64
)le32_to_cpu(stat_info
->rmac_jabber_frms_oflow
) << 32 |
6023 le32_to_cpu(stat_info
->rmac_jabber_frms
);
6024 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_64_frms
);
6025 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_65_127_frms
);
6026 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_128_255_frms
);
6027 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_256_511_frms
);
6028 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_512_1023_frms
);
6029 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_1024_1518_frms
);
6031 (u64
)le32_to_cpu(stat_info
->rmac_ip_oflow
) << 32 |
6032 le32_to_cpu(stat_info
->rmac_ip
);
6033 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ip_octets
);
6034 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_hdr_err_ip
);
6036 (u64
)le32_to_cpu(stat_info
->rmac_drop_ip_oflow
) << 32 |
6037 le32_to_cpu(stat_info
->rmac_drop_ip
);
6039 (u64
)le32_to_cpu(stat_info
->rmac_icmp_oflow
) << 32 |
6040 le32_to_cpu(stat_info
->rmac_icmp
);
6041 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_tcp
);
6043 (u64
)le32_to_cpu(stat_info
->rmac_udp_oflow
) << 32 |
6044 le32_to_cpu(stat_info
->rmac_udp
);
6046 (u64
)le32_to_cpu(stat_info
->rmac_err_drp_udp_oflow
) << 32 |
6047 le32_to_cpu(stat_info
->rmac_err_drp_udp
);
6048 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_err_sym
);
6049 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q0
);
6050 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q1
);
6051 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q2
);
6052 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q3
);
6053 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q4
);
6054 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q5
);
6055 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q6
);
6056 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q7
);
6057 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q0
);
6058 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q1
);
6059 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q2
);
6060 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q3
);
6061 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q4
);
6062 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q5
);
6063 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q6
);
6064 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q7
);
6066 (u64
)le32_to_cpu(stat_info
->rmac_pause_cnt_oflow
) << 32 |
6067 le32_to_cpu(stat_info
->rmac_pause_cnt
);
6068 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_data_err_cnt
);
6069 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_ctrl_err_cnt
);
6071 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ip_oflow
) << 32 |
6072 le32_to_cpu(stat_info
->rmac_accepted_ip
);
6073 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_err_tcp
);
6074 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_req_cnt
);
6075 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_cnt
);
6076 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_rtry_cnt
);
6077 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_cnt
);
6078 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_rd_ack_cnt
);
6079 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_req_cnt
);
6080 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_cnt
);
6081 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_rtry_cnt
);
6082 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_cnt
);
6083 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_disc_cnt
);
6084 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_wr_ack_cnt
);
6085 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txp_wr_cnt
);
6086 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_rd_cnt
);
6087 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_wr_cnt
);
6088 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_rd_cnt
);
6089 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_wr_cnt
);
6090 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txf_rd_cnt
);
6091 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxf_wr_cnt
);
6093 /* Enhanced statistics exist only for Hercules */
6094 if(sp
->device_type
== XFRAME_II_DEVICE
) {
6096 le64_to_cpu(stat_info
->rmac_ttl_1519_4095_frms
);
6098 le64_to_cpu(stat_info
->rmac_ttl_4096_8191_frms
);
6100 le64_to_cpu(stat_info
->rmac_ttl_8192_max_frms
);
6101 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_gt_max_frms
);
6102 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_osized_alt_frms
);
6103 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_jabber_alt_frms
);
6104 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_gt_max_alt_frms
);
6105 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_vlan_frms
);
6106 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_len_discard
);
6107 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_fcs_discard
);
6108 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_pf_discard
);
6109 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_da_discard
);
6110 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_red_discard
);
6111 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_rts_discard
);
6112 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_ingm_full_discard
);
6113 tmp_stats
[i
++] = le32_to_cpu(stat_info
->link_fault_cnt
);
6117 tmp_stats
[i
++] = stat_info
->sw_stat
.single_ecc_errs
;
6118 tmp_stats
[i
++] = stat_info
->sw_stat
.double_ecc_errs
;
6119 tmp_stats
[i
++] = stat_info
->sw_stat
.parity_err_cnt
;
6120 tmp_stats
[i
++] = stat_info
->sw_stat
.serious_err_cnt
;
6121 tmp_stats
[i
++] = stat_info
->sw_stat
.soft_reset_cnt
;
6122 tmp_stats
[i
++] = stat_info
->sw_stat
.fifo_full_cnt
;
6123 for (k
= 0; k
< MAX_RX_RINGS
; k
++)
6124 tmp_stats
[i
++] = stat_info
->sw_stat
.ring_full_cnt
[k
];
6125 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_high
;
6126 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_low
;
6127 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_high
;
6128 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_low
;
6129 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_high
;
6130 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_low
;
6131 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_high
;
6132 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_low
;
6133 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_high
;
6134 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_low
;
6135 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_high
;
6136 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_low
;
6137 tmp_stats
[i
++] = stat_info
->sw_stat
.clubbed_frms_cnt
;
6138 tmp_stats
[i
++] = stat_info
->sw_stat
.sending_both
;
6139 tmp_stats
[i
++] = stat_info
->sw_stat
.outof_sequence_pkts
;
6140 tmp_stats
[i
++] = stat_info
->sw_stat
.flush_max_pkts
;
6141 if (stat_info
->sw_stat
.num_aggregations
) {
6142 u64 tmp
= stat_info
->sw_stat
.sum_avg_pkts_aggregated
;
6145 * Since 64-bit divide does not work on all platforms,
6146 * do repeated subtraction.
6148 while (tmp
>= stat_info
->sw_stat
.num_aggregations
) {
6149 tmp
-= stat_info
->sw_stat
.num_aggregations
;
6152 tmp_stats
[i
++] = count
;
6156 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_alloc_fail_cnt
;
6157 tmp_stats
[i
++] = stat_info
->sw_stat
.pci_map_fail_cnt
;
6158 tmp_stats
[i
++] = stat_info
->sw_stat
.watchdog_timer_cnt
;
6159 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_allocated
;
6160 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_freed
;
6161 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_cnt
;
6162 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_cnt
;
6163 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_time
;
6164 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_time
;
6166 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_buf_abort_cnt
;
6167 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_desc_abort_cnt
;
6168 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_parity_err_cnt
;
6169 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_link_loss_cnt
;
6170 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_list_proc_err_cnt
;
6172 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_err_cnt
;
6173 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_abort_cnt
;
6174 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_abort_cnt
;
6175 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rda_fail_cnt
;
6176 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_prot_cnt
;
6177 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_fcs_err_cnt
;
6178 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_buf_size_err_cnt
;
6179 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rxd_corrupt_cnt
;
6180 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_err_cnt
;
6181 tmp_stats
[i
++] = stat_info
->sw_stat
.tda_err_cnt
;
6182 tmp_stats
[i
++] = stat_info
->sw_stat
.pfc_err_cnt
;
6183 tmp_stats
[i
++] = stat_info
->sw_stat
.pcc_err_cnt
;
6184 tmp_stats
[i
++] = stat_info
->sw_stat
.tti_err_cnt
;
6185 tmp_stats
[i
++] = stat_info
->sw_stat
.tpa_err_cnt
;
6186 tmp_stats
[i
++] = stat_info
->sw_stat
.sm_err_cnt
;
6187 tmp_stats
[i
++] = stat_info
->sw_stat
.lso_err_cnt
;
6188 tmp_stats
[i
++] = stat_info
->sw_stat
.mac_tmac_err_cnt
;
6189 tmp_stats
[i
++] = stat_info
->sw_stat
.mac_rmac_err_cnt
;
6190 tmp_stats
[i
++] = stat_info
->sw_stat
.xgxs_txgxs_err_cnt
;
6191 tmp_stats
[i
++] = stat_info
->sw_stat
.xgxs_rxgxs_err_cnt
;
6192 tmp_stats
[i
++] = stat_info
->sw_stat
.rc_err_cnt
;
6193 tmp_stats
[i
++] = stat_info
->sw_stat
.prc_pcix_err_cnt
;
6194 tmp_stats
[i
++] = stat_info
->sw_stat
.rpa_err_cnt
;
6195 tmp_stats
[i
++] = stat_info
->sw_stat
.rda_err_cnt
;
6196 tmp_stats
[i
++] = stat_info
->sw_stat
.rti_err_cnt
;
6197 tmp_stats
[i
++] = stat_info
->sw_stat
.mc_err_cnt
;
6200 static int s2io_ethtool_get_regs_len(struct net_device
*dev
)
6202 return (XENA_REG_SPACE
);
6206 static u32
s2io_ethtool_get_rx_csum(struct net_device
* dev
)
6208 struct s2io_nic
*sp
= dev
->priv
;
6210 return (sp
->rx_csum
);
6213 static int s2io_ethtool_set_rx_csum(struct net_device
*dev
, u32 data
)
6215 struct s2io_nic
*sp
= dev
->priv
;
6225 static int s2io_get_eeprom_len(struct net_device
*dev
)
6227 return (XENA_EEPROM_SPACE
);
6230 static int s2io_get_sset_count(struct net_device
*dev
, int sset
)
6232 struct s2io_nic
*sp
= dev
->priv
;
6236 return S2IO_TEST_LEN
;
6238 switch(sp
->device_type
) {
6239 case XFRAME_I_DEVICE
:
6240 return XFRAME_I_STAT_LEN
;
6241 case XFRAME_II_DEVICE
:
6242 return XFRAME_II_STAT_LEN
;
6251 static void s2io_ethtool_get_strings(struct net_device
*dev
,
6252 u32 stringset
, u8
* data
)
6255 struct s2io_nic
*sp
= dev
->priv
;
6257 switch (stringset
) {
6259 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
6262 stat_size
= sizeof(ethtool_xena_stats_keys
);
6263 memcpy(data
, ðtool_xena_stats_keys
,stat_size
);
6264 if(sp
->device_type
== XFRAME_II_DEVICE
) {
6265 memcpy(data
+ stat_size
,
6266 ðtool_enhanced_stats_keys
,
6267 sizeof(ethtool_enhanced_stats_keys
));
6268 stat_size
+= sizeof(ethtool_enhanced_stats_keys
);
6271 memcpy(data
+ stat_size
, ðtool_driver_stats_keys
,
6272 sizeof(ethtool_driver_stats_keys
));
6276 static int s2io_ethtool_op_set_tx_csum(struct net_device
*dev
, u32 data
)
6279 dev
->features
|= NETIF_F_IP_CSUM
;
6281 dev
->features
&= ~NETIF_F_IP_CSUM
;
6286 static u32
s2io_ethtool_op_get_tso(struct net_device
*dev
)
6288 return (dev
->features
& NETIF_F_TSO
) != 0;
6290 static int s2io_ethtool_op_set_tso(struct net_device
*dev
, u32 data
)
6293 dev
->features
|= (NETIF_F_TSO
| NETIF_F_TSO6
);
6295 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
6300 static const struct ethtool_ops netdev_ethtool_ops
= {
6301 .get_settings
= s2io_ethtool_gset
,
6302 .set_settings
= s2io_ethtool_sset
,
6303 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
6304 .get_regs_len
= s2io_ethtool_get_regs_len
,
6305 .get_regs
= s2io_ethtool_gregs
,
6306 .get_link
= ethtool_op_get_link
,
6307 .get_eeprom_len
= s2io_get_eeprom_len
,
6308 .get_eeprom
= s2io_ethtool_geeprom
,
6309 .set_eeprom
= s2io_ethtool_seeprom
,
6310 .get_ringparam
= s2io_ethtool_gringparam
,
6311 .get_pauseparam
= s2io_ethtool_getpause_data
,
6312 .set_pauseparam
= s2io_ethtool_setpause_data
,
6313 .get_rx_csum
= s2io_ethtool_get_rx_csum
,
6314 .set_rx_csum
= s2io_ethtool_set_rx_csum
,
6315 .set_tx_csum
= s2io_ethtool_op_set_tx_csum
,
6316 .set_sg
= ethtool_op_set_sg
,
6317 .get_tso
= s2io_ethtool_op_get_tso
,
6318 .set_tso
= s2io_ethtool_op_set_tso
,
6319 .set_ufo
= ethtool_op_set_ufo
,
6320 .self_test
= s2io_ethtool_test
,
6321 .get_strings
= s2io_ethtool_get_strings
,
6322 .phys_id
= s2io_ethtool_idnic
,
6323 .get_ethtool_stats
= s2io_get_ethtool_stats
,
6324 .get_sset_count
= s2io_get_sset_count
,
6328 * s2io_ioctl - Entry point for the Ioctl
6329 * @dev : Device pointer.
6330 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6331 * a proprietary structure used to pass information to the driver.
6332 * @cmd : This is used to distinguish between the different commands that
6333 * can be passed to the IOCTL functions.
6335 * Currently there are no special functionality supported in IOCTL, hence
6336 * function always return EOPNOTSUPPORTED
6339 static int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
6345 * s2io_change_mtu - entry point to change MTU size for the device.
6346 * @dev : device pointer.
6347 * @new_mtu : the new MTU size for the device.
6348 * Description: A driver entry point to change MTU size for the device.
6349 * Before changing the MTU the device must be stopped.
6351 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6355 static int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
6357 struct s2io_nic
*sp
= dev
->priv
;
6359 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
6360 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n",
6366 if (netif_running(dev
)) {
6368 netif_stop_queue(dev
);
6369 if (s2io_card_up(sp
)) {
6370 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6373 if (netif_queue_stopped(dev
))
6374 netif_wake_queue(dev
);
6375 } else { /* Device is down */
6376 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6377 u64 val64
= new_mtu
;
6379 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
6386 * s2io_tasklet - Bottom half of the ISR.
6387 * @dev_adr : address of the device structure in dma_addr_t format.
6389 * This is the tasklet or the bottom half of the ISR. This is
6390 * an extension of the ISR which is scheduled by the scheduler to be run
6391 * when the load on the CPU is low. All low priority tasks of the ISR can
6392 * be pushed into the tasklet. For now the tasklet is used only to
6393 * replenish the Rx buffers in the Rx buffer descriptors.
6398 static void s2io_tasklet(unsigned long dev_addr
)
6400 struct net_device
*dev
= (struct net_device
*) dev_addr
;
6401 struct s2io_nic
*sp
= dev
->priv
;
6403 struct mac_info
*mac_control
;
6404 struct config_param
*config
;
6406 mac_control
= &sp
->mac_control
;
6407 config
= &sp
->config
;
6409 if (!TASKLET_IN_USE
) {
6410 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6411 ret
= fill_rx_buffers(sp
, i
);
6412 if (ret
== -ENOMEM
) {
6413 DBG_PRINT(INFO_DBG
, "%s: Out of ",
6415 DBG_PRINT(INFO_DBG
, "memory in tasklet\n");
6417 } else if (ret
== -EFILL
) {
6419 "%s: Rx Ring %d is full\n",
6424 clear_bit(0, (&sp
->tasklet_status
));
6429 * s2io_set_link - Set the LInk status
6430 * @data: long pointer to device private structue
6431 * Description: Sets the link status for the adapter
6434 static void s2io_set_link(struct work_struct
*work
)
6436 struct s2io_nic
*nic
= container_of(work
, struct s2io_nic
, set_link_task
);
6437 struct net_device
*dev
= nic
->dev
;
6438 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
6444 if (!netif_running(dev
))
6447 if (test_and_set_bit(__S2IO_STATE_LINK_TASK
, &(nic
->state
))) {
6448 /* The card is being reset, no point doing anything */
6452 subid
= nic
->pdev
->subsystem_device
;
6453 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
6455 * Allow a small delay for the NICs self initiated
6456 * cleanup to complete.
6461 val64
= readq(&bar0
->adapter_status
);
6462 if (LINK_IS_UP(val64
)) {
6463 if (!(readq(&bar0
->adapter_control
) & ADAPTER_CNTL_EN
)) {
6464 if (verify_xena_quiescence(nic
)) {
6465 val64
= readq(&bar0
->adapter_control
);
6466 val64
|= ADAPTER_CNTL_EN
;
6467 writeq(val64
, &bar0
->adapter_control
);
6468 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6469 nic
->device_type
, subid
)) {
6470 val64
= readq(&bar0
->gpio_control
);
6471 val64
|= GPIO_CTRL_GPIO_0
;
6472 writeq(val64
, &bar0
->gpio_control
);
6473 val64
= readq(&bar0
->gpio_control
);
6475 val64
|= ADAPTER_LED_ON
;
6476 writeq(val64
, &bar0
->adapter_control
);
6478 nic
->device_enabled_once
= TRUE
;
6480 DBG_PRINT(ERR_DBG
, "%s: Error: ", dev
->name
);
6481 DBG_PRINT(ERR_DBG
, "device is not Quiescent\n");
6482 netif_stop_queue(dev
);
6485 val64
= readq(&bar0
->adapter_control
);
6486 val64
|= ADAPTER_LED_ON
;
6487 writeq(val64
, &bar0
->adapter_control
);
6488 s2io_link(nic
, LINK_UP
);
6490 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
6492 val64
= readq(&bar0
->gpio_control
);
6493 val64
&= ~GPIO_CTRL_GPIO_0
;
6494 writeq(val64
, &bar0
->gpio_control
);
6495 val64
= readq(&bar0
->gpio_control
);
6498 val64
= readq(&bar0
->adapter_control
);
6499 val64
= val64
&(~ADAPTER_LED_ON
);
6500 writeq(val64
, &bar0
->adapter_control
);
6501 s2io_link(nic
, LINK_DOWN
);
6503 clear_bit(__S2IO_STATE_LINK_TASK
, &(nic
->state
));
6509 static int set_rxd_buffer_pointer(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6511 struct sk_buff
**skb
, u64
*temp0
, u64
*temp1
,
6512 u64
*temp2
, int size
)
6514 struct net_device
*dev
= sp
->dev
;
6515 struct swStat
*stats
= &sp
->mac_control
.stats_info
->sw_stat
;
6517 if ((sp
->rxd_mode
== RXD_MODE_1
) && (rxdp
->Host_Control
== 0)) {
6518 struct RxD1
*rxdp1
= (struct RxD1
*)rxdp
;
6521 DBG_PRINT(INFO_DBG
, "SKB is not NULL\n");
6523 * As Rx frame are not going to be processed,
6524 * using same mapped address for the Rxd
6527 rxdp1
->Buffer0_ptr
= *temp0
;
6529 *skb
= dev_alloc_skb(size
);
6531 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6532 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6533 DBG_PRINT(INFO_DBG
, "1 buf mode SKBs\n");
6534 sp
->mac_control
.stats_info
->sw_stat
. \
6535 mem_alloc_fail_cnt
++;
6538 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6539 += (*skb
)->truesize
;
6540 /* storing the mapped addr in a temp variable
6541 * such it will be used for next rxd whose
6542 * Host Control is NULL
6544 rxdp1
->Buffer0_ptr
= *temp0
=
6545 pci_map_single( sp
->pdev
, (*skb
)->data
,
6546 size
- NET_IP_ALIGN
,
6547 PCI_DMA_FROMDEVICE
);
6548 if( (rxdp1
->Buffer0_ptr
== 0) ||
6549 (rxdp1
->Buffer0_ptr
== DMA_ERROR_CODE
)) {
6550 goto memalloc_failed
;
6552 rxdp
->Host_Control
= (unsigned long) (*skb
);
6554 } else if ((sp
->rxd_mode
== RXD_MODE_3B
) && (rxdp
->Host_Control
== 0)) {
6555 struct RxD3
*rxdp3
= (struct RxD3
*)rxdp
;
6556 /* Two buffer Mode */
6558 rxdp3
->Buffer2_ptr
= *temp2
;
6559 rxdp3
->Buffer0_ptr
= *temp0
;
6560 rxdp3
->Buffer1_ptr
= *temp1
;
6562 *skb
= dev_alloc_skb(size
);
6564 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6565 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6566 DBG_PRINT(INFO_DBG
, "2 buf mode SKBs\n");
6567 sp
->mac_control
.stats_info
->sw_stat
. \
6568 mem_alloc_fail_cnt
++;
6571 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6572 += (*skb
)->truesize
;
6573 rxdp3
->Buffer2_ptr
= *temp2
=
6574 pci_map_single(sp
->pdev
, (*skb
)->data
,
6576 PCI_DMA_FROMDEVICE
);
6577 if( (rxdp3
->Buffer2_ptr
== 0) ||
6578 (rxdp3
->Buffer2_ptr
== DMA_ERROR_CODE
)) {
6579 goto memalloc_failed
;
6581 rxdp3
->Buffer0_ptr
= *temp0
=
6582 pci_map_single( sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
6583 PCI_DMA_FROMDEVICE
);
6584 if( (rxdp3
->Buffer0_ptr
== 0) ||
6585 (rxdp3
->Buffer0_ptr
== DMA_ERROR_CODE
)) {
6586 pci_unmap_single (sp
->pdev
,
6587 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
6588 dev
->mtu
+ 4, PCI_DMA_FROMDEVICE
);
6589 goto memalloc_failed
;
6591 rxdp
->Host_Control
= (unsigned long) (*skb
);
6593 /* Buffer-1 will be dummy buffer not used */
6594 rxdp3
->Buffer1_ptr
= *temp1
=
6595 pci_map_single(sp
->pdev
, ba
->ba_1
, BUF1_LEN
,
6596 PCI_DMA_FROMDEVICE
);
6597 if( (rxdp3
->Buffer1_ptr
== 0) ||
6598 (rxdp3
->Buffer1_ptr
== DMA_ERROR_CODE
)) {
6599 pci_unmap_single (sp
->pdev
,
6600 (dma_addr_t
)rxdp3
->Buffer0_ptr
,
6601 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
6602 pci_unmap_single (sp
->pdev
,
6603 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
6604 dev
->mtu
+ 4, PCI_DMA_FROMDEVICE
);
6605 goto memalloc_failed
;
6611 stats
->pci_map_fail_cnt
++;
6612 stats
->mem_freed
+= (*skb
)->truesize
;
6613 dev_kfree_skb(*skb
);
6617 static void set_rxd_buffer_size(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6620 struct net_device
*dev
= sp
->dev
;
6621 if (sp
->rxd_mode
== RXD_MODE_1
) {
6622 rxdp
->Control_2
= SET_BUFFER0_SIZE_1( size
- NET_IP_ALIGN
);
6623 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
6624 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6625 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
6626 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3( dev
->mtu
+ 4);
6630 static int rxd_owner_bit_reset(struct s2io_nic
*sp
)
6632 int i
, j
, k
, blk_cnt
= 0, size
;
6633 struct mac_info
* mac_control
= &sp
->mac_control
;
6634 struct config_param
*config
= &sp
->config
;
6635 struct net_device
*dev
= sp
->dev
;
6636 struct RxD_t
*rxdp
= NULL
;
6637 struct sk_buff
*skb
= NULL
;
6638 struct buffAdd
*ba
= NULL
;
6639 u64 temp0_64
= 0, temp1_64
= 0, temp2_64
= 0;
6641 /* Calculate the size based on ring mode */
6642 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
6643 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
6644 if (sp
->rxd_mode
== RXD_MODE_1
)
6645 size
+= NET_IP_ALIGN
;
6646 else if (sp
->rxd_mode
== RXD_MODE_3B
)
6647 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6649 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6650 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
6651 (rxd_count
[sp
->rxd_mode
] +1);
6653 for (j
= 0; j
< blk_cnt
; j
++) {
6654 for (k
= 0; k
< rxd_count
[sp
->rxd_mode
]; k
++) {
6655 rxdp
= mac_control
->rings
[i
].
6656 rx_blocks
[j
].rxds
[k
].virt_addr
;
6657 if(sp
->rxd_mode
== RXD_MODE_3B
)
6658 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
6659 if (set_rxd_buffer_pointer(sp
, rxdp
, ba
,
6660 &skb
,(u64
*)&temp0_64
,
6667 set_rxd_buffer_size(sp
, rxdp
, size
);
6669 /* flip the Ownership bit to Hardware */
6670 rxdp
->Control_1
|= RXD_OWN_XENA
;
6678 static int s2io_add_isr(struct s2io_nic
* sp
)
6681 struct net_device
*dev
= sp
->dev
;
6684 if (sp
->config
.intr_type
== MSI_X
)
6685 ret
= s2io_enable_msi_x(sp
);
6687 DBG_PRINT(ERR_DBG
, "%s: Defaulting to INTA\n", dev
->name
);
6688 sp
->config
.intr_type
= INTA
;
6691 /* Store the values of the MSIX table in the struct s2io_nic structure */
6692 store_xmsi_data(sp
);
6694 /* After proper initialization of H/W, register ISR */
6695 if (sp
->config
.intr_type
== MSI_X
) {
6696 int i
, msix_tx_cnt
=0,msix_rx_cnt
=0;
6698 for (i
=1; (sp
->s2io_entries
[i
].in_use
== MSIX_FLG
); i
++) {
6699 if (sp
->s2io_entries
[i
].type
== MSIX_FIFO_TYPE
) {
6700 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-TX",
6702 err
= request_irq(sp
->entries
[i
].vector
,
6703 s2io_msix_fifo_handle
, 0, sp
->desc
[i
],
6704 sp
->s2io_entries
[i
].arg
);
6705 /* If either data or addr is zero print it */
6706 if(!(sp
->msix_info
[i
].addr
&&
6707 sp
->msix_info
[i
].data
)) {
6708 DBG_PRINT(ERR_DBG
, "%s @ Addr:0x%llx"
6709 "Data:0x%lx\n",sp
->desc
[i
],
6710 (unsigned long long)
6711 sp
->msix_info
[i
].addr
,
6713 ntohl(sp
->msix_info
[i
].data
));
6718 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-RX",
6720 err
= request_irq(sp
->entries
[i
].vector
,
6721 s2io_msix_ring_handle
, 0, sp
->desc
[i
],
6722 sp
->s2io_entries
[i
].arg
);
6723 /* If either data or addr is zero print it */
6724 if(!(sp
->msix_info
[i
].addr
&&
6725 sp
->msix_info
[i
].data
)) {
6726 DBG_PRINT(ERR_DBG
, "%s @ Addr:0x%llx"
6727 "Data:0x%lx\n",sp
->desc
[i
],
6728 (unsigned long long)
6729 sp
->msix_info
[i
].addr
,
6731 ntohl(sp
->msix_info
[i
].data
));
6737 remove_msix_isr(sp
);
6738 DBG_PRINT(ERR_DBG
,"%s:MSI-X-%d registration "
6739 "failed\n", dev
->name
, i
);
6740 DBG_PRINT(ERR_DBG
, "%s: defaulting to INTA\n",
6742 sp
->config
.intr_type
= INTA
;
6745 sp
->s2io_entries
[i
].in_use
= MSIX_REGISTERED_SUCCESS
;
6748 printk(KERN_INFO
"MSI-X-TX %d entries enabled\n",
6750 printk(KERN_INFO
"MSI-X-RX %d entries enabled\n",
6754 if (sp
->config
.intr_type
== INTA
) {
6755 err
= request_irq((int) sp
->pdev
->irq
, s2io_isr
, IRQF_SHARED
,
6758 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
6765 static void s2io_rem_isr(struct s2io_nic
* sp
)
6767 if (sp
->config
.intr_type
== MSI_X
)
6768 remove_msix_isr(sp
);
6770 remove_inta_isr(sp
);
6773 static void do_s2io_card_down(struct s2io_nic
* sp
, int do_io
)
6776 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6777 unsigned long flags
;
6778 register u64 val64
= 0;
6780 del_timer_sync(&sp
->alarm_timer
);
6781 /* If s2io_set_link task is executing, wait till it completes. */
6782 while (test_and_set_bit(__S2IO_STATE_LINK_TASK
, &(sp
->state
))) {
6785 clear_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
6787 /* disable Tx and Rx traffic on the NIC */
6794 tasklet_kill(&sp
->task
);
6796 /* Check if the device is Quiescent and then Reset the NIC */
6798 /* As per the HW requirement we need to replenish the
6799 * receive buffer to avoid the ring bump. Since there is
6800 * no intention of processing the Rx frame at this pointwe are
6801 * just settting the ownership bit of rxd in Each Rx
6802 * ring to HW and set the appropriate buffer size
6803 * based on the ring mode
6805 rxd_owner_bit_reset(sp
);
6807 val64
= readq(&bar0
->adapter_status
);
6808 if (verify_xena_quiescence(sp
)) {
6809 if(verify_pcc_quiescent(sp
, sp
->device_enabled_once
))
6817 "s2io_close:Device not Quiescent ");
6818 DBG_PRINT(ERR_DBG
, "adaper status reads 0x%llx\n",
6819 (unsigned long long) val64
);
6826 spin_lock_irqsave(&sp
->tx_lock
, flags
);
6827 /* Free all Tx buffers */
6828 free_tx_buffers(sp
);
6829 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
6831 /* Free all Rx buffers */
6832 spin_lock_irqsave(&sp
->rx_lock
, flags
);
6833 free_rx_buffers(sp
);
6834 spin_unlock_irqrestore(&sp
->rx_lock
, flags
);
6836 clear_bit(__S2IO_STATE_LINK_TASK
, &(sp
->state
));
6839 static void s2io_card_down(struct s2io_nic
* sp
)
6841 do_s2io_card_down(sp
, 1);
6844 static int s2io_card_up(struct s2io_nic
* sp
)
6847 struct mac_info
*mac_control
;
6848 struct config_param
*config
;
6849 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
6852 /* Initialize the H/W I/O registers */
6853 if (init_nic(sp
) != 0) {
6854 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
6861 * Initializing the Rx buffers. For now we are considering only 1
6862 * Rx ring and initializing buffers into 30 Rx blocks
6864 mac_control
= &sp
->mac_control
;
6865 config
= &sp
->config
;
6867 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6868 if ((ret
= fill_rx_buffers(sp
, i
))) {
6869 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
6872 free_rx_buffers(sp
);
6875 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
6876 atomic_read(&sp
->rx_bufs_left
[i
]));
6878 /* Maintain the state prior to the open */
6879 if (sp
->promisc_flg
)
6880 sp
->promisc_flg
= 0;
6881 if (sp
->m_cast_flg
) {
6883 sp
->all_multi_pos
= 0;
6886 /* Setting its receive mode */
6887 s2io_set_multicast(dev
);
6890 /* Initialize max aggregatable pkts per session based on MTU */
6891 sp
->lro_max_aggr_per_sess
= ((1<<16) - 1) / dev
->mtu
;
6892 /* Check if we can use(if specified) user provided value */
6893 if (lro_max_pkts
< sp
->lro_max_aggr_per_sess
)
6894 sp
->lro_max_aggr_per_sess
= lro_max_pkts
;
6897 /* Enable Rx Traffic and interrupts on the NIC */
6898 if (start_nic(sp
)) {
6899 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
6901 free_rx_buffers(sp
);
6905 /* Add interrupt service routine */
6906 if (s2io_add_isr(sp
) != 0) {
6907 if (sp
->config
.intr_type
== MSI_X
)
6910 free_rx_buffers(sp
);
6914 S2IO_TIMER_CONF(sp
->alarm_timer
, s2io_alarm_handle
, sp
, (HZ
/2));
6916 /* Enable tasklet for the device */
6917 tasklet_init(&sp
->task
, s2io_tasklet
, (unsigned long) dev
);
6919 /* Enable select interrupts */
6920 en_dis_err_alarms(sp
, ENA_ALL_INTRS
, ENABLE_INTRS
);
6921 if (sp
->config
.intr_type
!= INTA
)
6922 en_dis_able_nic_intrs(sp
, ENA_ALL_INTRS
, DISABLE_INTRS
);
6924 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
6925 interruptible
|= TX_PIC_INTR
;
6926 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
6929 set_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
6934 * s2io_restart_nic - Resets the NIC.
6935 * @data : long pointer to the device private structure
6937 * This function is scheduled to be run by the s2io_tx_watchdog
6938 * function after 0.5 secs to reset the NIC. The idea is to reduce
6939 * the run time of the watch dog routine which is run holding a
6943 static void s2io_restart_nic(struct work_struct
*work
)
6945 struct s2io_nic
*sp
= container_of(work
, struct s2io_nic
, rst_timer_task
);
6946 struct net_device
*dev
= sp
->dev
;
6950 if (!netif_running(dev
))
6954 if (s2io_card_up(sp
)) {
6955 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6958 netif_wake_queue(dev
);
6959 DBG_PRINT(ERR_DBG
, "%s: was reset by Tx watchdog timer\n",
6966 * s2io_tx_watchdog - Watchdog for transmit side.
6967 * @dev : Pointer to net device structure
6969 * This function is triggered if the Tx Queue is stopped
6970 * for a pre-defined amount of time when the Interface is still up.
6971 * If the Interface is jammed in such a situation, the hardware is
6972 * reset (by s2io_close) and restarted again (by s2io_open) to
6973 * overcome any problem that might have been caused in the hardware.
6978 static void s2io_tx_watchdog(struct net_device
*dev
)
6980 struct s2io_nic
*sp
= dev
->priv
;
6982 if (netif_carrier_ok(dev
)) {
6983 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
++;
6984 schedule_work(&sp
->rst_timer_task
);
6985 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
6990 * rx_osm_handler - To perform some OS related operations on SKB.
6991 * @sp: private member of the device structure,pointer to s2io_nic structure.
6992 * @skb : the socket buffer pointer.
6993 * @len : length of the packet
6994 * @cksum : FCS checksum of the frame.
6995 * @ring_no : the ring from which this RxD was extracted.
6997 * This function is called by the Rx interrupt serivce routine to perform
6998 * some OS related operations on the SKB before passing it to the upper
6999 * layers. It mainly checks if the checksum is OK, if so adds it to the
7000 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7001 * to the upper layer. If the checksum is wrong, it increments the Rx
7002 * packet error count, frees the SKB and returns error.
7004 * SUCCESS on success and -1 on failure.
7006 static int rx_osm_handler(struct ring_info
*ring_data
, struct RxD_t
* rxdp
)
7008 struct s2io_nic
*sp
= ring_data
->nic
;
7009 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
7010 struct sk_buff
*skb
= (struct sk_buff
*)
7011 ((unsigned long) rxdp
->Host_Control
);
7012 int ring_no
= ring_data
->ring_no
;
7013 u16 l3_csum
, l4_csum
;
7014 unsigned long long err
= rxdp
->Control_1
& RXD_T_CODE
;
7021 /* Check for parity error */
7023 sp
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
7025 err_mask
= err
>> 48;
7028 sp
->mac_control
.stats_info
->sw_stat
.
7029 rx_parity_err_cnt
++;
7033 sp
->mac_control
.stats_info
->sw_stat
.
7038 sp
->mac_control
.stats_info
->sw_stat
.
7039 rx_parity_abort_cnt
++;
7043 sp
->mac_control
.stats_info
->sw_stat
.
7048 sp
->mac_control
.stats_info
->sw_stat
.
7053 sp
->mac_control
.stats_info
->sw_stat
.
7058 sp
->mac_control
.stats_info
->sw_stat
.
7059 rx_buf_size_err_cnt
++;
7063 sp
->mac_control
.stats_info
->sw_stat
.
7064 rx_rxd_corrupt_cnt
++;
7068 sp
->mac_control
.stats_info
->sw_stat
.
7073 * Drop the packet if bad transfer code. Exception being
7074 * 0x5, which could be due to unsupported IPv6 extension header.
7075 * In this case, we let stack handle the packet.
7076 * Note that in this case, since checksum will be incorrect,
7077 * stack will validate the same.
7079 if (err_mask
!= 0x5) {
7080 DBG_PRINT(ERR_DBG
, "%s: Rx error Value: 0x%x\n",
7081 dev
->name
, err_mask
);
7082 sp
->stats
.rx_crc_errors
++;
7083 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
7086 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
7087 rxdp
->Host_Control
= 0;
7092 /* Updating statistics */
7093 sp
->stats
.rx_packets
++;
7094 rxdp
->Host_Control
= 0;
7095 if (sp
->rxd_mode
== RXD_MODE_1
) {
7096 int len
= RXD_GET_BUFFER0_SIZE_1(rxdp
->Control_2
);
7098 sp
->stats
.rx_bytes
+= len
;
7101 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
7102 int get_block
= ring_data
->rx_curr_get_info
.block_index
;
7103 int get_off
= ring_data
->rx_curr_get_info
.offset
;
7104 int buf0_len
= RXD_GET_BUFFER0_SIZE_3(rxdp
->Control_2
);
7105 int buf2_len
= RXD_GET_BUFFER2_SIZE_3(rxdp
->Control_2
);
7106 unsigned char *buff
= skb_push(skb
, buf0_len
);
7108 struct buffAdd
*ba
= &ring_data
->ba
[get_block
][get_off
];
7109 sp
->stats
.rx_bytes
+= buf0_len
+ buf2_len
;
7110 memcpy(buff
, ba
->ba_0
, buf0_len
);
7111 skb_put(skb
, buf2_len
);
7114 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) && ((!sp
->lro
) ||
7115 (sp
->lro
&& (!(rxdp
->Control_1
& RXD_FRAME_IP_FRAG
)))) &&
7117 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
7118 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
7119 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
7121 * NIC verifies if the Checksum of the received
7122 * frame is Ok or not and accordingly returns
7123 * a flag in the RxD.
7125 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
7131 ret
= s2io_club_tcp_session(skb
->data
, &tcp
,
7135 case 3: /* Begin anew */
7138 case 1: /* Aggregate */
7140 lro_append_pkt(sp
, lro
,
7144 case 4: /* Flush session */
7146 lro_append_pkt(sp
, lro
,
7148 queue_rx_frame(lro
->parent
);
7149 clear_lro_session(lro
);
7150 sp
->mac_control
.stats_info
->
7151 sw_stat
.flush_max_pkts
++;
7154 case 2: /* Flush both */
7155 lro
->parent
->data_len
=
7157 sp
->mac_control
.stats_info
->
7158 sw_stat
.sending_both
++;
7159 queue_rx_frame(lro
->parent
);
7160 clear_lro_session(lro
);
7162 case 0: /* sessions exceeded */
7163 case -1: /* non-TCP or not
7167 * First pkt in session not
7168 * L3/L4 aggregatable
7173 "%s: Samadhana!!\n",
7180 * Packet with erroneous checksum, let the
7181 * upper layers deal with it.
7183 skb
->ip_summed
= CHECKSUM_NONE
;
7186 skb
->ip_summed
= CHECKSUM_NONE
;
7188 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
7190 skb
->protocol
= eth_type_trans(skb
, dev
);
7191 if ((sp
->vlgrp
&& RXD_GET_VLAN_TAG(rxdp
->Control_2
) &&
7193 /* Queueing the vlan frame to the upper layer */
7195 vlan_hwaccel_receive_skb(skb
, sp
->vlgrp
,
7196 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7198 vlan_hwaccel_rx(skb
, sp
->vlgrp
,
7199 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7202 netif_receive_skb(skb
);
7208 queue_rx_frame(skb
);
7210 dev
->last_rx
= jiffies
;
7212 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
7217 * s2io_link - stops/starts the Tx queue.
7218 * @sp : private member of the device structure, which is a pointer to the
7219 * s2io_nic structure.
7220 * @link : inidicates whether link is UP/DOWN.
7222 * This function stops/starts the Tx queue depending on whether the link
7223 * status of the NIC is is down or up. This is called by the Alarm
7224 * interrupt handler whenever a link change interrupt comes up.
7229 static void s2io_link(struct s2io_nic
* sp
, int link
)
7231 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
7233 if (link
!= sp
->last_link_state
) {
7234 if (link
== LINK_DOWN
) {
7235 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
7236 netif_carrier_off(dev
);
7237 if(sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
)
7238 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
=
7239 jiffies
- sp
->start_time
;
7240 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
++;
7242 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
7243 if (sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
)
7244 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
=
7245 jiffies
- sp
->start_time
;
7246 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
++;
7247 netif_carrier_on(dev
);
7250 sp
->last_link_state
= link
;
7251 sp
->start_time
= jiffies
;
7255 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7256 * @sp : private member of the device structure, which is a pointer to the
7257 * s2io_nic structure.
7259 * This function initializes a few of the PCI and PCI-X configuration registers
7260 * with recommended values.
7265 static void s2io_init_pci(struct s2io_nic
* sp
)
7267 u16 pci_cmd
= 0, pcix_cmd
= 0;
7269 /* Enable Data Parity Error Recovery in PCI-X command register. */
7270 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7272 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7274 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7277 /* Set the PErr Response bit in PCI command register. */
7278 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7279 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
7280 (pci_cmd
| PCI_COMMAND_PARITY
));
7281 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7284 static int s2io_verify_parm(struct pci_dev
*pdev
, u8
*dev_intr_type
)
7286 if ( tx_fifo_num
> 8) {
7287 DBG_PRINT(ERR_DBG
, "s2io: Requested number of Tx fifos not "
7289 DBG_PRINT(ERR_DBG
, "s2io: Default to 8 Tx fifos\n");
7292 if ( rx_ring_num
> 8) {
7293 DBG_PRINT(ERR_DBG
, "s2io: Requested number of Rx rings not "
7295 DBG_PRINT(ERR_DBG
, "s2io: Default to 8 Rx rings\n");
7298 if (*dev_intr_type
!= INTA
)
7301 if ((*dev_intr_type
!= INTA
) && (*dev_intr_type
!= MSI_X
)) {
7302 DBG_PRINT(ERR_DBG
, "s2io: Wrong intr_type requested. "
7303 "Defaulting to INTA\n");
7304 *dev_intr_type
= INTA
;
7307 if ((*dev_intr_type
== MSI_X
) &&
7308 ((pdev
->device
!= PCI_DEVICE_ID_HERC_WIN
) &&
7309 (pdev
->device
!= PCI_DEVICE_ID_HERC_UNI
))) {
7310 DBG_PRINT(ERR_DBG
, "s2io: Xframe I does not support MSI_X. "
7311 "Defaulting to INTA\n");
7312 *dev_intr_type
= INTA
;
7315 if ((rx_ring_mode
!= 1) && (rx_ring_mode
!= 2)) {
7316 DBG_PRINT(ERR_DBG
, "s2io: Requested ring mode not supported\n");
7317 DBG_PRINT(ERR_DBG
, "s2io: Defaulting to 1-buffer mode\n");
7324 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7325 * or Traffic class respectively.
7326 * @nic: device peivate variable
7327 * Description: The function configures the receive steering to
7328 * desired receive ring.
7329 * Return Value: SUCCESS on success and
7330 * '-1' on failure (endian settings incorrect).
7332 static int rts_ds_steer(struct s2io_nic
*nic
, u8 ds_codepoint
, u8 ring
)
7334 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
7335 register u64 val64
= 0;
7337 if (ds_codepoint
> 63)
7340 val64
= RTS_DS_MEM_DATA(ring
);
7341 writeq(val64
, &bar0
->rts_ds_mem_data
);
7343 val64
= RTS_DS_MEM_CTRL_WE
|
7344 RTS_DS_MEM_CTRL_STROBE_NEW_CMD
|
7345 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint
);
7347 writeq(val64
, &bar0
->rts_ds_mem_ctrl
);
7349 return wait_for_cmd_complete(&bar0
->rts_ds_mem_ctrl
,
7350 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED
,
7355 * s2io_init_nic - Initialization of the adapter .
7356 * @pdev : structure containing the PCI related information of the device.
7357 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7359 * The function initializes an adapter identified by the pci_dec structure.
7360 * All OS related initialization including memory and device structure and
7361 * initlaization of the device private variable is done. Also the swapper
7362 * control register is initialized to enable read and write into the I/O
7363 * registers of the device.
7365 * returns 0 on success and negative on failure.
7368 static int __devinit
7369 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
7371 struct s2io_nic
*sp
;
7372 struct net_device
*dev
;
7374 int dma_flag
= FALSE
;
7375 u32 mac_up
, mac_down
;
7376 u64 val64
= 0, tmp64
= 0;
7377 struct XENA_dev_config __iomem
*bar0
= NULL
;
7379 struct mac_info
*mac_control
;
7380 struct config_param
*config
;
7382 u8 dev_intr_type
= intr_type
;
7383 DECLARE_MAC_BUF(mac
);
7385 if ((ret
= s2io_verify_parm(pdev
, &dev_intr_type
)))
7388 if ((ret
= pci_enable_device(pdev
))) {
7390 "s2io_init_nic: pci_enable_device failed\n");
7394 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
7395 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 64bit DMA\n");
7397 if (pci_set_consistent_dma_mask
7398 (pdev
, DMA_64BIT_MASK
)) {
7400 "Unable to obtain 64bit DMA for \
7401 consistent allocations\n");
7402 pci_disable_device(pdev
);
7405 } else if (!pci_set_dma_mask(pdev
, DMA_32BIT_MASK
)) {
7406 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 32bit DMA\n");
7408 pci_disable_device(pdev
);
7411 if ((ret
= pci_request_regions(pdev
, s2io_driver_name
))) {
7412 DBG_PRINT(ERR_DBG
, "%s: Request Regions failed - %x \n", __FUNCTION__
, ret
);
7413 pci_disable_device(pdev
);
7417 dev
= alloc_etherdev(sizeof(struct s2io_nic
));
7419 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
7420 pci_disable_device(pdev
);
7421 pci_release_regions(pdev
);
7425 pci_set_master(pdev
);
7426 pci_set_drvdata(pdev
, dev
);
7427 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7429 /* Private member variable initialized to s2io NIC structure */
7431 memset(sp
, 0, sizeof(struct s2io_nic
));
7434 sp
->high_dma_flag
= dma_flag
;
7435 sp
->device_enabled_once
= FALSE
;
7436 if (rx_ring_mode
== 1)
7437 sp
->rxd_mode
= RXD_MODE_1
;
7438 if (rx_ring_mode
== 2)
7439 sp
->rxd_mode
= RXD_MODE_3B
;
7441 sp
->config
.intr_type
= dev_intr_type
;
7443 if ((pdev
->device
== PCI_DEVICE_ID_HERC_WIN
) ||
7444 (pdev
->device
== PCI_DEVICE_ID_HERC_UNI
))
7445 sp
->device_type
= XFRAME_II_DEVICE
;
7447 sp
->device_type
= XFRAME_I_DEVICE
;
7449 sp
->lro
= lro_enable
;
7451 /* Initialize some PCI/PCI-X fields of the NIC. */
7455 * Setting the device configuration parameters.
7456 * Most of these parameters can be specified by the user during
7457 * module insertion as they are module loadable parameters. If
7458 * these parameters are not not specified during load time, they
7459 * are initialized with default values.
7461 mac_control
= &sp
->mac_control
;
7462 config
= &sp
->config
;
7464 config
->napi
= napi
;
7466 /* Tx side parameters. */
7467 config
->tx_fifo_num
= tx_fifo_num
;
7468 for (i
= 0; i
< MAX_TX_FIFOS
; i
++) {
7469 config
->tx_cfg
[i
].fifo_len
= tx_fifo_len
[i
];
7470 config
->tx_cfg
[i
].fifo_priority
= i
;
7473 /* mapping the QoS priority to the configured fifos */
7474 for (i
= 0; i
< MAX_TX_FIFOS
; i
++)
7475 config
->fifo_mapping
[i
] = fifo_map
[config
->tx_fifo_num
][i
];
7477 config
->tx_intr_type
= TXD_INT_TYPE_UTILZ
;
7478 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7479 config
->tx_cfg
[i
].f_no_snoop
=
7480 (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
7481 if (config
->tx_cfg
[i
].fifo_len
< 65) {
7482 config
->tx_intr_type
= TXD_INT_TYPE_PER_LIST
;
7486 /* + 2 because one Txd for skb->data and one Txd for UFO */
7487 config
->max_txds
= MAX_SKB_FRAGS
+ 2;
7489 /* Rx side parameters. */
7490 config
->rx_ring_num
= rx_ring_num
;
7491 for (i
= 0; i
< MAX_RX_RINGS
; i
++) {
7492 config
->rx_cfg
[i
].num_rxd
= rx_ring_sz
[i
] *
7493 (rxd_count
[sp
->rxd_mode
] + 1);
7494 config
->rx_cfg
[i
].ring_priority
= i
;
7497 for (i
= 0; i
< rx_ring_num
; i
++) {
7498 config
->rx_cfg
[i
].ring_org
= RING_ORG_BUFF1
;
7499 config
->rx_cfg
[i
].f_no_snoop
=
7500 (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
7503 /* Setting Mac Control parameters */
7504 mac_control
->rmac_pause_time
= rmac_pause_time
;
7505 mac_control
->mc_pause_threshold_q0q3
= mc_pause_threshold_q0q3
;
7506 mac_control
->mc_pause_threshold_q4q7
= mc_pause_threshold_q4q7
;
7509 /* Initialize Ring buffer parameters. */
7510 for (i
= 0; i
< config
->rx_ring_num
; i
++)
7511 atomic_set(&sp
->rx_bufs_left
[i
], 0);
7513 /* initialize the shared memory used by the NIC and the host */
7514 if (init_shared_mem(sp
)) {
7515 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n",
7518 goto mem_alloc_failed
;
7521 sp
->bar0
= ioremap(pci_resource_start(pdev
, 0),
7522 pci_resource_len(pdev
, 0));
7524 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem1\n",
7527 goto bar0_remap_failed
;
7530 sp
->bar1
= ioremap(pci_resource_start(pdev
, 2),
7531 pci_resource_len(pdev
, 2));
7533 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem2\n",
7536 goto bar1_remap_failed
;
7539 dev
->irq
= pdev
->irq
;
7540 dev
->base_addr
= (unsigned long) sp
->bar0
;
7542 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7543 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
7544 mac_control
->tx_FIFO_start
[j
] = (struct TxFIFO_element __iomem
*)
7545 (sp
->bar1
+ (j
* 0x00020000));
7548 /* Driver entry points */
7549 dev
->open
= &s2io_open
;
7550 dev
->stop
= &s2io_close
;
7551 dev
->hard_start_xmit
= &s2io_xmit
;
7552 dev
->get_stats
= &s2io_get_stats
;
7553 dev
->set_multicast_list
= &s2io_set_multicast
;
7554 dev
->do_ioctl
= &s2io_ioctl
;
7555 dev
->set_mac_address
= &s2io_set_mac_addr
;
7556 dev
->change_mtu
= &s2io_change_mtu
;
7557 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
7558 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
7559 dev
->vlan_rx_register
= s2io_vlan_rx_register
;
7562 * will use eth_mac_addr() for dev->set_mac_address
7563 * mac address will be set every time dev->open() is called
7565 netif_napi_add(dev
, &sp
->napi
, s2io_poll
, 32);
7567 #ifdef CONFIG_NET_POLL_CONTROLLER
7568 dev
->poll_controller
= s2io_netpoll
;
7571 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
7572 if (sp
->high_dma_flag
== TRUE
)
7573 dev
->features
|= NETIF_F_HIGHDMA
;
7574 dev
->features
|= NETIF_F_TSO
;
7575 dev
->features
|= NETIF_F_TSO6
;
7576 if ((sp
->device_type
& XFRAME_II_DEVICE
) && (ufo
)) {
7577 dev
->features
|= NETIF_F_UFO
;
7578 dev
->features
|= NETIF_F_HW_CSUM
;
7581 dev
->tx_timeout
= &s2io_tx_watchdog
;
7582 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
7583 INIT_WORK(&sp
->rst_timer_task
, s2io_restart_nic
);
7584 INIT_WORK(&sp
->set_link_task
, s2io_set_link
);
7586 pci_save_state(sp
->pdev
);
7588 /* Setting swapper control on the NIC, for proper reset operation */
7589 if (s2io_set_swapper(sp
)) {
7590 DBG_PRINT(ERR_DBG
, "%s:swapper settings are wrong\n",
7593 goto set_swap_failed
;
7596 /* Verify if the Herc works on the slot its placed into */
7597 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7598 mode
= s2io_verify_pci_mode(sp
);
7600 DBG_PRINT(ERR_DBG
, "%s: ", __FUNCTION__
);
7601 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
7603 goto set_swap_failed
;
7607 /* Not needed for Herc */
7608 if (sp
->device_type
& XFRAME_I_DEVICE
) {
7610 * Fix for all "FFs" MAC address problems observed on
7613 fix_mac_address(sp
);
7618 * MAC address initialization.
7619 * For now only one mac address will be read and used.
7622 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
7623 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET
);
7624 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
7625 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
7626 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
, S2IO_BIT_RESET
);
7627 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
7628 mac_down
= (u32
) tmp64
;
7629 mac_up
= (u32
) (tmp64
>> 32);
7631 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_up
);
7632 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
7633 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
7634 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
7635 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
7636 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
7638 /* Set the factory defined MAC address initially */
7639 dev
->addr_len
= ETH_ALEN
;
7640 memcpy(dev
->dev_addr
, sp
->def_mac_addr
, ETH_ALEN
);
7641 memcpy(dev
->perm_addr
, dev
->dev_addr
, ETH_ALEN
);
7643 /* Store the values of the MSIX table in the s2io_nic structure */
7644 store_xmsi_data(sp
);
7645 /* reset Nic and bring it to known state */
7649 * Initialize the tasklet status and link state flags
7650 * and the card state parameter
7652 sp
->tasklet_status
= 0;
7655 /* Initialize spinlocks */
7656 spin_lock_init(&sp
->tx_lock
);
7659 spin_lock_init(&sp
->put_lock
);
7660 spin_lock_init(&sp
->rx_lock
);
7663 * SXE-002: Configure link and activity LED to init state
7666 subid
= sp
->pdev
->subsystem_device
;
7667 if ((subid
& 0xFF) >= 0x07) {
7668 val64
= readq(&bar0
->gpio_control
);
7669 val64
|= 0x0000800000000000ULL
;
7670 writeq(val64
, &bar0
->gpio_control
);
7671 val64
= 0x0411040400000000ULL
;
7672 writeq(val64
, (void __iomem
*) bar0
+ 0x2700);
7673 val64
= readq(&bar0
->gpio_control
);
7676 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
7678 if (register_netdev(dev
)) {
7679 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
7681 goto register_failed
;
7684 DBG_PRINT(ERR_DBG
, "Copyright(c) 2002-2007 Neterion Inc.\n");
7685 DBG_PRINT(ERR_DBG
, "%s: Neterion %s (rev %d)\n",dev
->name
,
7686 sp
->product_name
, pdev
->revision
);
7687 DBG_PRINT(ERR_DBG
, "%s: Driver version %s\n", dev
->name
,
7688 s2io_driver_version
);
7689 DBG_PRINT(ERR_DBG
, "%s: MAC ADDR: %s\n",
7690 dev
->name
, print_mac(mac
, dev
->dev_addr
));
7691 DBG_PRINT(ERR_DBG
, "SERIAL NUMBER: %s\n", sp
->serial_num
);
7692 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7693 mode
= s2io_print_pci_mode(sp
);
7695 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
7697 unregister_netdev(dev
);
7698 goto set_swap_failed
;
7701 switch(sp
->rxd_mode
) {
7703 DBG_PRINT(ERR_DBG
, "%s: 1-Buffer receive mode enabled\n",
7707 DBG_PRINT(ERR_DBG
, "%s: 2-Buffer receive mode enabled\n",
7713 DBG_PRINT(ERR_DBG
, "%s: NAPI enabled\n", dev
->name
);
7714 switch(sp
->config
.intr_type
) {
7716 DBG_PRINT(ERR_DBG
, "%s: Interrupt type INTA\n", dev
->name
);
7719 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI-X\n", dev
->name
);
7723 DBG_PRINT(ERR_DBG
, "%s: Large receive offload enabled\n",
7726 DBG_PRINT(ERR_DBG
, "%s: UDP Fragmentation Offload(UFO)"
7727 " enabled\n", dev
->name
);
7728 /* Initialize device name */
7729 sprintf(sp
->name
, "%s Neterion %s", dev
->name
, sp
->product_name
);
7732 * Make Link state as off at this point, when the Link change
7733 * interrupt comes the state will be automatically changed to
7736 netif_carrier_off(dev
);
7747 free_shared_mem(sp
);
7748 pci_disable_device(pdev
);
7749 pci_release_regions(pdev
);
7750 pci_set_drvdata(pdev
, NULL
);
7757 * s2io_rem_nic - Free the PCI device
7758 * @pdev: structure containing the PCI related information of the device.
7759 * Description: This function is called by the Pci subsystem to release a
7760 * PCI device and free up all resource held up by the device. This could
7761 * be in response to a Hot plug event or when the driver is to be removed
7765 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
7767 struct net_device
*dev
=
7768 (struct net_device
*) pci_get_drvdata(pdev
);
7769 struct s2io_nic
*sp
;
7772 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
7776 flush_scheduled_work();
7779 unregister_netdev(dev
);
7781 free_shared_mem(sp
);
7784 pci_release_regions(pdev
);
7785 pci_set_drvdata(pdev
, NULL
);
7787 pci_disable_device(pdev
);
7791 * s2io_starter - Entry point for the driver
7792 * Description: This function is the entry point for the driver. It verifies
7793 * the module loadable parameters and initializes PCI configuration space.
7796 static int __init
s2io_starter(void)
7798 return pci_register_driver(&s2io_driver
);
7802 * s2io_closer - Cleanup routine for the driver
7803 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7806 static __exit
void s2io_closer(void)
7808 pci_unregister_driver(&s2io_driver
);
7809 DBG_PRINT(INIT_DBG
, "cleanup done\n");
7812 module_init(s2io_starter
);
7813 module_exit(s2io_closer
);
7815 static int check_L2_lro_capable(u8
*buffer
, struct iphdr
**ip
,
7816 struct tcphdr
**tcp
, struct RxD_t
*rxdp
)
7819 u8 l2_type
= (u8
)((rxdp
->Control_1
>> 37) & 0x7), ip_len
;
7821 if (!(rxdp
->Control_1
& RXD_FRAME_PROTO_TCP
)) {
7822 DBG_PRINT(INIT_DBG
,"%s: Non-TCP frames not supported for LRO\n",
7828 * By default the VLAN field in the MAC is stripped by the card, if this
7829 * feature is turned off in rx_pa_cfg register, then the ip_off field
7830 * has to be shifted by a further 2 bytes
7833 case 0: /* DIX type */
7834 case 4: /* DIX type with VLAN */
7835 ip_off
= HEADER_ETHERNET_II_802_3_SIZE
;
7837 /* LLC, SNAP etc are considered non-mergeable */
7842 *ip
= (struct iphdr
*)((u8
*)buffer
+ ip_off
);
7843 ip_len
= (u8
)((*ip
)->ihl
);
7845 *tcp
= (struct tcphdr
*)((unsigned long)*ip
+ ip_len
);
7850 static int check_for_socket_match(struct lro
*lro
, struct iphdr
*ip
,
7853 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7854 if ((lro
->iph
->saddr
!= ip
->saddr
) || (lro
->iph
->daddr
!= ip
->daddr
) ||
7855 (lro
->tcph
->source
!= tcp
->source
) || (lro
->tcph
->dest
!= tcp
->dest
))
7860 static inline int get_l4_pyld_length(struct iphdr
*ip
, struct tcphdr
*tcp
)
7862 return(ntohs(ip
->tot_len
) - (ip
->ihl
<< 2) - (tcp
->doff
<< 2));
7865 static void initiate_new_session(struct lro
*lro
, u8
*l2h
,
7866 struct iphdr
*ip
, struct tcphdr
*tcp
, u32 tcp_pyld_len
)
7868 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7872 lro
->tcp_next_seq
= tcp_pyld_len
+ ntohl(tcp
->seq
);
7873 lro
->tcp_ack
= ntohl(tcp
->ack_seq
);
7875 lro
->total_len
= ntohs(ip
->tot_len
);
7878 * check if we saw TCP timestamp. Other consistency checks have
7879 * already been done.
7881 if (tcp
->doff
== 8) {
7883 ptr
= (u32
*)(tcp
+1);
7885 lro
->cur_tsval
= *(ptr
+1);
7886 lro
->cur_tsecr
= *(ptr
+2);
7891 static void update_L3L4_header(struct s2io_nic
*sp
, struct lro
*lro
)
7893 struct iphdr
*ip
= lro
->iph
;
7894 struct tcphdr
*tcp
= lro
->tcph
;
7896 struct stat_block
*statinfo
= sp
->mac_control
.stats_info
;
7897 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7899 /* Update L3 header */
7900 ip
->tot_len
= htons(lro
->total_len
);
7902 nchk
= ip_fast_csum((u8
*)lro
->iph
, ip
->ihl
);
7905 /* Update L4 header */
7906 tcp
->ack_seq
= lro
->tcp_ack
;
7907 tcp
->window
= lro
->window
;
7909 /* Update tsecr field if this session has timestamps enabled */
7911 u32
*ptr
= (u32
*)(tcp
+ 1);
7912 *(ptr
+2) = lro
->cur_tsecr
;
7915 /* Update counters required for calculation of
7916 * average no. of packets aggregated.
7918 statinfo
->sw_stat
.sum_avg_pkts_aggregated
+= lro
->sg_num
;
7919 statinfo
->sw_stat
.num_aggregations
++;
7922 static void aggregate_new_rx(struct lro
*lro
, struct iphdr
*ip
,
7923 struct tcphdr
*tcp
, u32 l4_pyld
)
7925 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7926 lro
->total_len
+= l4_pyld
;
7927 lro
->frags_len
+= l4_pyld
;
7928 lro
->tcp_next_seq
+= l4_pyld
;
7931 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7932 lro
->tcp_ack
= tcp
->ack_seq
;
7933 lro
->window
= tcp
->window
;
7937 /* Update tsecr and tsval from this packet */
7938 ptr
= (u32
*) (tcp
+ 1);
7939 lro
->cur_tsval
= *(ptr
+ 1);
7940 lro
->cur_tsecr
= *(ptr
+ 2);
7944 static int verify_l3_l4_lro_capable(struct lro
*l_lro
, struct iphdr
*ip
,
7945 struct tcphdr
*tcp
, u32 tcp_pyld_len
)
7949 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7951 if (!tcp_pyld_len
) {
7952 /* Runt frame or a pure ack */
7956 if (ip
->ihl
!= 5) /* IP has options */
7959 /* If we see CE codepoint in IP header, packet is not mergeable */
7960 if (INET_ECN_is_ce(ipv4_get_dsfield(ip
)))
7963 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7964 if (tcp
->urg
|| tcp
->psh
|| tcp
->rst
|| tcp
->syn
|| tcp
->fin
||
7965 tcp
->ece
|| tcp
->cwr
|| !tcp
->ack
) {
7967 * Currently recognize only the ack control word and
7968 * any other control field being set would result in
7969 * flushing the LRO session
7975 * Allow only one TCP timestamp option. Don't aggregate if
7976 * any other options are detected.
7978 if (tcp
->doff
!= 5 && tcp
->doff
!= 8)
7981 if (tcp
->doff
== 8) {
7982 ptr
= (u8
*)(tcp
+ 1);
7983 while (*ptr
== TCPOPT_NOP
)
7985 if (*ptr
!= TCPOPT_TIMESTAMP
|| *(ptr
+1) != TCPOLEN_TIMESTAMP
)
7988 /* Ensure timestamp value increases monotonically */
7990 if (l_lro
->cur_tsval
> *((u32
*)(ptr
+2)))
7993 /* timestamp echo reply should be non-zero */
7994 if (*((u32
*)(ptr
+6)) == 0)
8002 s2io_club_tcp_session(u8
*buffer
, u8
**tcp
, u32
*tcp_len
, struct lro
**lro
,
8003 struct RxD_t
*rxdp
, struct s2io_nic
*sp
)
8006 struct tcphdr
*tcph
;
8009 if (!(ret
= check_L2_lro_capable(buffer
, &ip
, (struct tcphdr
**)tcp
,
8011 DBG_PRINT(INFO_DBG
,"IP Saddr: %x Daddr: %x\n",
8012 ip
->saddr
, ip
->daddr
);
8017 tcph
= (struct tcphdr
*)*tcp
;
8018 *tcp_len
= get_l4_pyld_length(ip
, tcph
);
8019 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
8020 struct lro
*l_lro
= &sp
->lro0_n
[i
];
8021 if (l_lro
->in_use
) {
8022 if (check_for_socket_match(l_lro
, ip
, tcph
))
8024 /* Sock pair matched */
8027 if ((*lro
)->tcp_next_seq
!= ntohl(tcph
->seq
)) {
8028 DBG_PRINT(INFO_DBG
, "%s:Out of order. expected "
8029 "0x%x, actual 0x%x\n", __FUNCTION__
,
8030 (*lro
)->tcp_next_seq
,
8033 sp
->mac_control
.stats_info
->
8034 sw_stat
.outof_sequence_pkts
++;
8039 if (!verify_l3_l4_lro_capable(l_lro
, ip
, tcph
,*tcp_len
))
8040 ret
= 1; /* Aggregate */
8042 ret
= 2; /* Flush both */
8048 /* Before searching for available LRO objects,
8049 * check if the pkt is L3/L4 aggregatable. If not
8050 * don't create new LRO session. Just send this
8053 if (verify_l3_l4_lro_capable(NULL
, ip
, tcph
, *tcp_len
)) {
8057 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
8058 struct lro
*l_lro
= &sp
->lro0_n
[i
];
8059 if (!(l_lro
->in_use
)) {
8061 ret
= 3; /* Begin anew */
8067 if (ret
== 0) { /* sessions exceeded */
8068 DBG_PRINT(INFO_DBG
,"%s:All LRO sessions already in use\n",
8076 initiate_new_session(*lro
, buffer
, ip
, tcph
, *tcp_len
);
8079 update_L3L4_header(sp
, *lro
);
8082 aggregate_new_rx(*lro
, ip
, tcph
, *tcp_len
);
8083 if ((*lro
)->sg_num
== sp
->lro_max_aggr_per_sess
) {
8084 update_L3L4_header(sp
, *lro
);
8085 ret
= 4; /* Flush the LRO */
8089 DBG_PRINT(ERR_DBG
,"%s:Dont know, can't say!!\n",
8097 static void clear_lro_session(struct lro
*lro
)
8099 static u16 lro_struct_size
= sizeof(struct lro
);
8101 memset(lro
, 0, lro_struct_size
);
8104 static void queue_rx_frame(struct sk_buff
*skb
)
8106 struct net_device
*dev
= skb
->dev
;
8108 skb
->protocol
= eth_type_trans(skb
, dev
);
8110 netif_receive_skb(skb
);
8115 static void lro_append_pkt(struct s2io_nic
*sp
, struct lro
*lro
,
8116 struct sk_buff
*skb
,
8119 struct sk_buff
*first
= lro
->parent
;
8121 first
->len
+= tcp_len
;
8122 first
->data_len
= lro
->frags_len
;
8123 skb_pull(skb
, (skb
->len
- tcp_len
));
8124 if (skb_shinfo(first
)->frag_list
)
8125 lro
->last_frag
->next
= skb
;
8127 skb_shinfo(first
)->frag_list
= skb
;
8128 first
->truesize
+= skb
->truesize
;
8129 lro
->last_frag
= skb
;
8130 sp
->mac_control
.stats_info
->sw_stat
.clubbed_frms_cnt
++;
8135 * s2io_io_error_detected - called when PCI error is detected
8136 * @pdev: Pointer to PCI device
8137 * @state: The current pci connection state
8139 * This function is called after a PCI bus error affecting
8140 * this device has been detected.
8142 static pci_ers_result_t
s2io_io_error_detected(struct pci_dev
*pdev
,
8143 pci_channel_state_t state
)
8145 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8146 struct s2io_nic
*sp
= netdev
->priv
;
8148 netif_device_detach(netdev
);
8150 if (netif_running(netdev
)) {
8151 /* Bring down the card, while avoiding PCI I/O */
8152 do_s2io_card_down(sp
, 0);
8154 pci_disable_device(pdev
);
8156 return PCI_ERS_RESULT_NEED_RESET
;
8160 * s2io_io_slot_reset - called after the pci bus has been reset.
8161 * @pdev: Pointer to PCI device
8163 * Restart the card from scratch, as if from a cold-boot.
8164 * At this point, the card has exprienced a hard reset,
8165 * followed by fixups by BIOS, and has its config space
8166 * set up identically to what it was at cold boot.
8168 static pci_ers_result_t
s2io_io_slot_reset(struct pci_dev
*pdev
)
8170 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8171 struct s2io_nic
*sp
= netdev
->priv
;
8173 if (pci_enable_device(pdev
)) {
8174 printk(KERN_ERR
"s2io: "
8175 "Cannot re-enable PCI device after reset.\n");
8176 return PCI_ERS_RESULT_DISCONNECT
;
8179 pci_set_master(pdev
);
8182 return PCI_ERS_RESULT_RECOVERED
;
8186 * s2io_io_resume - called when traffic can start flowing again.
8187 * @pdev: Pointer to PCI device
8189 * This callback is called when the error recovery driver tells
8190 * us that its OK to resume normal operation.
8192 static void s2io_io_resume(struct pci_dev
*pdev
)
8194 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8195 struct s2io_nic
*sp
= netdev
->priv
;
8197 if (netif_running(netdev
)) {
8198 if (s2io_card_up(sp
)) {
8199 printk(KERN_ERR
"s2io: "
8200 "Can't bring device back up after reset.\n");
8204 if (s2io_set_mac_addr(netdev
, netdev
->dev_addr
) == FAILURE
) {
8206 printk(KERN_ERR
"s2io: "
8207 "Can't resetore mac addr after reset.\n");
8212 netif_device_attach(netdev
);
8213 netif_wake_queue(netdev
);