1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 ************************************************************************/
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/skbuff.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/stddef.h>
68 #include <linux/ioctl.h>
69 #include <linux/timex.h>
70 #include <linux/ethtool.h>
71 #include <linux/workqueue.h>
72 #include <linux/if_vlan.h>
74 #include <linux/tcp.h>
77 #include <asm/system.h>
78 #include <asm/uaccess.h>
80 #include <asm/div64.h>
85 #include "s2io-regs.h"
87 #define DRV_VERSION "2.0.23.1"
89 /* S2io Driver name & version. */
90 static char s2io_driver_name
[] = "Neterion";
91 static char s2io_driver_version
[] = DRV_VERSION
;
93 static int rxd_size
[4] = {32,48,48,64};
94 static int rxd_count
[4] = {127,85,85,63};
96 static inline int RXD_IS_UP2DT(struct RxD_t
*rxdp
)
100 ret
= ((!(rxdp
->Control_1
& RXD_OWN_XENA
)) &&
101 (GET_RXD_MARKER(rxdp
->Control_2
) != THE_RXD_MARK
));
107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
121 static inline int rx_buffer_level(struct s2io_nic
* sp
, int rxb_size
, int ring
)
123 struct mac_info
*mac_control
;
125 mac_control
= &sp
->mac_control
;
126 if (rxb_size
<= rxd_count
[sp
->rxd_mode
])
128 else if ((mac_control
->rings
[ring
].pkt_cnt
- rxb_size
) > 16)
133 /* Ethtool related variables and Macros. */
134 static char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
135 "Register test\t(offline)",
136 "Eeprom test\t(offline)",
137 "Link test\t(online)",
138 "RLDRAM test\t(offline)",
139 "BIST Test\t(offline)"
142 static char ethtool_xena_stats_keys
[][ETH_GSTRING_LEN
] = {
144 {"tmac_data_octets"},
148 {"tmac_pause_ctrl_frms"},
152 {"tmac_any_err_frms"},
153 {"tmac_ttl_less_fb_octets"},
154 {"tmac_vld_ip_octets"},
162 {"rmac_data_octets"},
163 {"rmac_fcs_err_frms"},
165 {"rmac_vld_mcst_frms"},
166 {"rmac_vld_bcst_frms"},
167 {"rmac_in_rng_len_err_frms"},
168 {"rmac_out_rng_len_err_frms"},
170 {"rmac_pause_ctrl_frms"},
171 {"rmac_unsup_ctrl_frms"},
173 {"rmac_accepted_ucst_frms"},
174 {"rmac_accepted_nucst_frms"},
175 {"rmac_discarded_frms"},
176 {"rmac_drop_events"},
177 {"rmac_ttl_less_fb_octets"},
179 {"rmac_usized_frms"},
180 {"rmac_osized_frms"},
182 {"rmac_jabber_frms"},
183 {"rmac_ttl_64_frms"},
184 {"rmac_ttl_65_127_frms"},
185 {"rmac_ttl_128_255_frms"},
186 {"rmac_ttl_256_511_frms"},
187 {"rmac_ttl_512_1023_frms"},
188 {"rmac_ttl_1024_1518_frms"},
196 {"rmac_err_drp_udp"},
197 {"rmac_xgmii_err_sym"},
215 {"rmac_xgmii_data_err_cnt"},
216 {"rmac_xgmii_ctrl_err_cnt"},
217 {"rmac_accepted_ip"},
221 {"new_rd_req_rtry_cnt"},
223 {"wr_rtry_rd_ack_cnt"},
226 {"new_wr_req_rtry_cnt"},
229 {"rd_rtry_wr_ack_cnt"},
239 static char ethtool_enhanced_stats_keys
[][ETH_GSTRING_LEN
] = {
240 {"rmac_ttl_1519_4095_frms"},
241 {"rmac_ttl_4096_8191_frms"},
242 {"rmac_ttl_8192_max_frms"},
243 {"rmac_ttl_gt_max_frms"},
244 {"rmac_osized_alt_frms"},
245 {"rmac_jabber_alt_frms"},
246 {"rmac_gt_max_alt_frms"},
248 {"rmac_len_discard"},
249 {"rmac_fcs_discard"},
252 {"rmac_red_discard"},
253 {"rmac_rts_discard"},
254 {"rmac_ingm_full_discard"},
258 static char ethtool_driver_stats_keys
[][ETH_GSTRING_LEN
] = {
259 {"\n DRIVER STATISTICS"},
260 {"single_bit_ecc_errs"},
261 {"double_bit_ecc_errs"},
267 ("alarm_transceiver_temp_high"),
268 ("alarm_transceiver_temp_low"),
269 ("alarm_laser_bias_current_high"),
270 ("alarm_laser_bias_current_low"),
271 ("alarm_laser_output_power_high"),
272 ("alarm_laser_output_power_low"),
273 ("warn_transceiver_temp_high"),
274 ("warn_transceiver_temp_low"),
275 ("warn_laser_bias_current_high"),
276 ("warn_laser_bias_current_low"),
277 ("warn_laser_output_power_high"),
278 ("warn_laser_output_power_low"),
279 ("lro_aggregated_pkts"),
280 ("lro_flush_both_count"),
281 ("lro_out_of_sequence_pkts"),
282 ("lro_flush_due_to_max_pkts"),
283 ("lro_avg_aggr_pkts"),
284 ("mem_alloc_fail_cnt"),
285 ("watchdog_timer_cnt"),
292 ("tx_tcode_buf_abort_cnt"),
293 ("tx_tcode_desc_abort_cnt"),
294 ("tx_tcode_parity_err_cnt"),
295 ("tx_tcode_link_loss_cnt"),
296 ("tx_tcode_list_proc_err_cnt"),
297 ("rx_tcode_parity_err_cnt"),
298 ("rx_tcode_abort_cnt"),
299 ("rx_tcode_parity_abort_cnt"),
300 ("rx_tcode_rda_fail_cnt"),
301 ("rx_tcode_unkn_prot_cnt"),
302 ("rx_tcode_fcs_err_cnt"),
303 ("rx_tcode_buf_size_err_cnt"),
304 ("rx_tcode_rxd_corrupt_cnt"),
305 ("rx_tcode_unkn_err_cnt")
308 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
309 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
311 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
313 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
314 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
316 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
317 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
319 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
320 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
322 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
323 init_timer(&timer); \
324 timer.function = handle; \
325 timer.data = (unsigned long) arg; \
326 mod_timer(&timer, (jiffies + exp)) \
329 static void s2io_vlan_rx_register(struct net_device
*dev
,
330 struct vlan_group
*grp
)
332 struct s2io_nic
*nic
= dev
->priv
;
335 spin_lock_irqsave(&nic
->tx_lock
, flags
);
337 spin_unlock_irqrestore(&nic
->tx_lock
, flags
);
340 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
341 static int vlan_strip_flag
;
344 * Constants to be programmed into the Xena's registers, to configure
349 static const u64 herc_act_dtx_cfg
[] = {
351 0x8000051536750000ULL
, 0x80000515367500E0ULL
,
353 0x8000051536750004ULL
, 0x80000515367500E4ULL
,
355 0x80010515003F0000ULL
, 0x80010515003F00E0ULL
,
357 0x80010515003F0004ULL
, 0x80010515003F00E4ULL
,
359 0x801205150D440000ULL
, 0x801205150D4400E0ULL
,
361 0x801205150D440004ULL
, 0x801205150D4400E4ULL
,
363 0x80020515F2100000ULL
, 0x80020515F21000E0ULL
,
365 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
370 static const u64 xena_dtx_cfg
[] = {
372 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
374 0x80000515D9350004ULL
, 0x80000515D93500E4ULL
,
376 0x8001051500000000ULL
, 0x80010515000000E0ULL
,
378 0x80010515001E0004ULL
, 0x80010515001E00E4ULL
,
380 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
382 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
387 * Constants for Fixing the MacAddress problem seen mostly on
390 static const u64 fix_mac
[] = {
391 0x0060000000000000ULL
, 0x0060600000000000ULL
,
392 0x0040600000000000ULL
, 0x0000600000000000ULL
,
393 0x0020600000000000ULL
, 0x0060600000000000ULL
,
394 0x0020600000000000ULL
, 0x0060600000000000ULL
,
395 0x0020600000000000ULL
, 0x0060600000000000ULL
,
396 0x0020600000000000ULL
, 0x0060600000000000ULL
,
397 0x0020600000000000ULL
, 0x0060600000000000ULL
,
398 0x0020600000000000ULL
, 0x0060600000000000ULL
,
399 0x0020600000000000ULL
, 0x0060600000000000ULL
,
400 0x0020600000000000ULL
, 0x0060600000000000ULL
,
401 0x0020600000000000ULL
, 0x0060600000000000ULL
,
402 0x0020600000000000ULL
, 0x0060600000000000ULL
,
403 0x0020600000000000ULL
, 0x0000600000000000ULL
,
404 0x0040600000000000ULL
, 0x0060600000000000ULL
,
408 MODULE_LICENSE("GPL");
409 MODULE_VERSION(DRV_VERSION
);
412 /* Module Loadable parameters. */
413 S2IO_PARM_INT(tx_fifo_num
, 1);
414 S2IO_PARM_INT(rx_ring_num
, 1);
417 S2IO_PARM_INT(rx_ring_mode
, 1);
418 S2IO_PARM_INT(use_continuous_tx_intrs
, 1);
419 S2IO_PARM_INT(rmac_pause_time
, 0x100);
420 S2IO_PARM_INT(mc_pause_threshold_q0q3
, 187);
421 S2IO_PARM_INT(mc_pause_threshold_q4q7
, 187);
422 S2IO_PARM_INT(shared_splits
, 0);
423 S2IO_PARM_INT(tmac_util_period
, 5);
424 S2IO_PARM_INT(rmac_util_period
, 5);
425 S2IO_PARM_INT(bimodal
, 0);
426 S2IO_PARM_INT(l3l4hdr_size
, 128);
427 /* Frequency of Rx desc syncs expressed as power of 2 */
428 S2IO_PARM_INT(rxsync_frequency
, 3);
429 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
430 S2IO_PARM_INT(intr_type
, 0);
431 /* Large receive offload feature */
432 S2IO_PARM_INT(lro
, 0);
433 /* Max pkts to be aggregated by LRO at one time. If not specified,
434 * aggregation happens until we hit max IP pkt size(64K)
436 S2IO_PARM_INT(lro_max_pkts
, 0xFFFF);
437 S2IO_PARM_INT(indicate_max_pkts
, 0);
439 S2IO_PARM_INT(napi
, 1);
440 S2IO_PARM_INT(ufo
, 0);
441 S2IO_PARM_INT(vlan_tag_strip
, NO_STRIP_IN_PROMISC
);
443 static unsigned int tx_fifo_len
[MAX_TX_FIFOS
] =
444 {DEFAULT_FIFO_0_LEN
, [1 ...(MAX_TX_FIFOS
- 1)] = DEFAULT_FIFO_1_7_LEN
};
445 static unsigned int rx_ring_sz
[MAX_RX_RINGS
] =
446 {[0 ...(MAX_RX_RINGS
- 1)] = SMALL_BLK_CNT
};
447 static unsigned int rts_frm_len
[MAX_RX_RINGS
] =
448 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
450 module_param_array(tx_fifo_len
, uint
, NULL
, 0);
451 module_param_array(rx_ring_sz
, uint
, NULL
, 0);
452 module_param_array(rts_frm_len
, uint
, NULL
, 0);
456 * This table lists all the devices that this driver supports.
458 static struct pci_device_id s2io_tbl
[] __devinitdata
= {
459 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
460 PCI_ANY_ID
, PCI_ANY_ID
},
461 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
462 PCI_ANY_ID
, PCI_ANY_ID
},
463 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_WIN
,
464 PCI_ANY_ID
, PCI_ANY_ID
},
465 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_UNI
,
466 PCI_ANY_ID
, PCI_ANY_ID
},
470 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
472 static struct pci_driver s2io_driver
= {
474 .id_table
= s2io_tbl
,
475 .probe
= s2io_init_nic
,
476 .remove
= __devexit_p(s2io_rem_nic
),
479 /* A simplifier macro used both by init and free shared_mem Fns(). */
480 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
483 * init_shared_mem - Allocation and Initialization of Memory
484 * @nic: Device private variable.
485 * Description: The function allocates all the memory areas shared
486 * between the NIC and the driver. This includes Tx descriptors,
487 * Rx descriptors and the statistics block.
490 static int init_shared_mem(struct s2io_nic
*nic
)
493 void *tmp_v_addr
, *tmp_v_addr_next
;
494 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
495 struct RxD_block
*pre_rxd_blk
= NULL
;
497 int lst_size
, lst_per_page
;
498 struct net_device
*dev
= nic
->dev
;
502 struct mac_info
*mac_control
;
503 struct config_param
*config
;
504 unsigned long long mem_allocated
= 0;
506 mac_control
= &nic
->mac_control
;
507 config
= &nic
->config
;
510 /* Allocation and initialization of TXDLs in FIOFs */
512 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
513 size
+= config
->tx_cfg
[i
].fifo_len
;
515 if (size
> MAX_AVAILABLE_TXDS
) {
516 DBG_PRINT(ERR_DBG
, "s2io: Requested TxDs too high, ");
517 DBG_PRINT(ERR_DBG
, "Requested: %d, max supported: 8192\n", size
);
521 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
522 lst_per_page
= PAGE_SIZE
/ lst_size
;
524 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
525 int fifo_len
= config
->tx_cfg
[i
].fifo_len
;
526 int list_holder_size
= fifo_len
* sizeof(struct list_info_hold
);
527 mac_control
->fifos
[i
].list_info
= kmalloc(list_holder_size
,
529 if (!mac_control
->fifos
[i
].list_info
) {
531 "Malloc failed for list_info\n");
534 mem_allocated
+= list_holder_size
;
535 memset(mac_control
->fifos
[i
].list_info
, 0, list_holder_size
);
537 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
538 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
540 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
541 mac_control
->fifos
[i
].tx_curr_put_info
.fifo_len
=
542 config
->tx_cfg
[i
].fifo_len
- 1;
543 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
544 mac_control
->fifos
[i
].tx_curr_get_info
.fifo_len
=
545 config
->tx_cfg
[i
].fifo_len
- 1;
546 mac_control
->fifos
[i
].fifo_no
= i
;
547 mac_control
->fifos
[i
].nic
= nic
;
548 mac_control
->fifos
[i
].max_txds
= MAX_SKB_FRAGS
+ 2;
550 for (j
= 0; j
< page_num
; j
++) {
554 tmp_v
= pci_alloc_consistent(nic
->pdev
,
558 "pci_alloc_consistent ");
559 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
562 /* If we got a zero DMA address(can happen on
563 * certain platforms like PPC), reallocate.
564 * Store virtual address of page we don't want,
568 mac_control
->zerodma_virt_addr
= tmp_v
;
570 "%s: Zero DMA address for TxDL. ", dev
->name
);
572 "Virtual address %p\n", tmp_v
);
573 tmp_v
= pci_alloc_consistent(nic
->pdev
,
577 "pci_alloc_consistent ");
578 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
581 mem_allocated
+= PAGE_SIZE
;
583 while (k
< lst_per_page
) {
584 int l
= (j
* lst_per_page
) + k
;
585 if (l
== config
->tx_cfg
[i
].fifo_len
)
587 mac_control
->fifos
[i
].list_info
[l
].list_virt_addr
=
588 tmp_v
+ (k
* lst_size
);
589 mac_control
->fifos
[i
].list_info
[l
].list_phy_addr
=
590 tmp_p
+ (k
* lst_size
);
596 nic
->ufo_in_band_v
= kcalloc(size
, sizeof(u64
), GFP_KERNEL
);
597 if (!nic
->ufo_in_band_v
)
599 mem_allocated
+= (size
* sizeof(u64
));
601 /* Allocation and initialization of RXDs in Rings */
603 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
604 if (config
->rx_cfg
[i
].num_rxd
%
605 (rxd_count
[nic
->rxd_mode
] + 1)) {
606 DBG_PRINT(ERR_DBG
, "%s: RxD count of ", dev
->name
);
607 DBG_PRINT(ERR_DBG
, "Ring%d is not a multiple of ",
609 DBG_PRINT(ERR_DBG
, "RxDs per Block");
612 size
+= config
->rx_cfg
[i
].num_rxd
;
613 mac_control
->rings
[i
].block_count
=
614 config
->rx_cfg
[i
].num_rxd
/
615 (rxd_count
[nic
->rxd_mode
] + 1 );
616 mac_control
->rings
[i
].pkt_cnt
= config
->rx_cfg
[i
].num_rxd
-
617 mac_control
->rings
[i
].block_count
;
619 if (nic
->rxd_mode
== RXD_MODE_1
)
620 size
= (size
* (sizeof(struct RxD1
)));
622 size
= (size
* (sizeof(struct RxD3
)));
624 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
625 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
626 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
627 mac_control
->rings
[i
].rx_curr_get_info
.ring_len
=
628 config
->rx_cfg
[i
].num_rxd
- 1;
629 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
630 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
631 mac_control
->rings
[i
].rx_curr_put_info
.ring_len
=
632 config
->rx_cfg
[i
].num_rxd
- 1;
633 mac_control
->rings
[i
].nic
= nic
;
634 mac_control
->rings
[i
].ring_no
= i
;
636 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
637 (rxd_count
[nic
->rxd_mode
] + 1);
638 /* Allocating all the Rx blocks */
639 for (j
= 0; j
< blk_cnt
; j
++) {
640 struct rx_block_info
*rx_blocks
;
643 rx_blocks
= &mac_control
->rings
[i
].rx_blocks
[j
];
644 size
= SIZE_OF_BLOCK
; //size is always page size
645 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
647 if (tmp_v_addr
== NULL
) {
649 * In case of failure, free_shared_mem()
650 * is called, which should free any
651 * memory that was alloced till the
654 rx_blocks
->block_virt_addr
= tmp_v_addr
;
657 mem_allocated
+= size
;
658 memset(tmp_v_addr
, 0, size
);
659 rx_blocks
->block_virt_addr
= tmp_v_addr
;
660 rx_blocks
->block_dma_addr
= tmp_p_addr
;
661 rx_blocks
->rxds
= kmalloc(sizeof(struct rxd_info
)*
662 rxd_count
[nic
->rxd_mode
],
664 if (!rx_blocks
->rxds
)
667 (sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
668 for (l
=0; l
<rxd_count
[nic
->rxd_mode
];l
++) {
669 rx_blocks
->rxds
[l
].virt_addr
=
670 rx_blocks
->block_virt_addr
+
671 (rxd_size
[nic
->rxd_mode
] * l
);
672 rx_blocks
->rxds
[l
].dma_addr
=
673 rx_blocks
->block_dma_addr
+
674 (rxd_size
[nic
->rxd_mode
] * l
);
677 /* Interlinking all Rx Blocks */
678 for (j
= 0; j
< blk_cnt
; j
++) {
680 mac_control
->rings
[i
].rx_blocks
[j
].block_virt_addr
;
682 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
683 blk_cnt
].block_virt_addr
;
685 mac_control
->rings
[i
].rx_blocks
[j
].block_dma_addr
;
687 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
688 blk_cnt
].block_dma_addr
;
690 pre_rxd_blk
= (struct RxD_block
*) tmp_v_addr
;
691 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
692 (unsigned long) tmp_v_addr_next
;
693 pre_rxd_blk
->pNext_RxD_Blk_physical
=
694 (u64
) tmp_p_addr_next
;
697 if (nic
->rxd_mode
>= RXD_MODE_3A
) {
699 * Allocation of Storages for buffer addresses in 2BUFF mode
700 * and the buffers as well.
702 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
703 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
704 (rxd_count
[nic
->rxd_mode
]+ 1);
705 mac_control
->rings
[i
].ba
=
706 kmalloc((sizeof(struct buffAdd
*) * blk_cnt
),
708 if (!mac_control
->rings
[i
].ba
)
710 mem_allocated
+=(sizeof(struct buffAdd
*) * blk_cnt
);
711 for (j
= 0; j
< blk_cnt
; j
++) {
713 mac_control
->rings
[i
].ba
[j
] =
714 kmalloc((sizeof(struct buffAdd
) *
715 (rxd_count
[nic
->rxd_mode
] + 1)),
717 if (!mac_control
->rings
[i
].ba
[j
])
719 mem_allocated
+= (sizeof(struct buffAdd
) * \
720 (rxd_count
[nic
->rxd_mode
] + 1));
721 while (k
!= rxd_count
[nic
->rxd_mode
]) {
722 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
724 ba
->ba_0_org
= (void *) kmalloc
725 (BUF0_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
729 (BUF0_LEN
+ ALIGN_SIZE
);
730 tmp
= (unsigned long)ba
->ba_0_org
;
732 tmp
&= ~((unsigned long) ALIGN_SIZE
);
733 ba
->ba_0
= (void *) tmp
;
735 ba
->ba_1_org
= (void *) kmalloc
736 (BUF1_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
740 += (BUF1_LEN
+ ALIGN_SIZE
);
741 tmp
= (unsigned long) ba
->ba_1_org
;
743 tmp
&= ~((unsigned long) ALIGN_SIZE
);
744 ba
->ba_1
= (void *) tmp
;
751 /* Allocation and initialization of Statistics block */
752 size
= sizeof(struct stat_block
);
753 mac_control
->stats_mem
= pci_alloc_consistent
754 (nic
->pdev
, size
, &mac_control
->stats_mem_phy
);
756 if (!mac_control
->stats_mem
) {
758 * In case of failure, free_shared_mem() is called, which
759 * should free any memory that was alloced till the
764 mem_allocated
+= size
;
765 mac_control
->stats_mem_sz
= size
;
767 tmp_v_addr
= mac_control
->stats_mem
;
768 mac_control
->stats_info
= (struct stat_block
*) tmp_v_addr
;
769 memset(tmp_v_addr
, 0, size
);
770 DBG_PRINT(INIT_DBG
, "%s:Ring Mem PHY: 0x%llx\n", dev
->name
,
771 (unsigned long long) tmp_p_addr
);
772 mac_control
->stats_info
->sw_stat
.mem_allocated
+= mem_allocated
;
777 * free_shared_mem - Free the allocated Memory
778 * @nic: Device private variable.
779 * Description: This function is to free all memory locations allocated by
780 * the init_shared_mem() function and return it to the kernel.
783 static void free_shared_mem(struct s2io_nic
*nic
)
785 int i
, j
, blk_cnt
, size
;
788 dma_addr_t tmp_p_addr
;
789 struct mac_info
*mac_control
;
790 struct config_param
*config
;
791 int lst_size
, lst_per_page
;
792 struct net_device
*dev
= nic
->dev
;
798 mac_control
= &nic
->mac_control
;
799 config
= &nic
->config
;
801 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
802 lst_per_page
= PAGE_SIZE
/ lst_size
;
804 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
805 ufo_size
+= config
->tx_cfg
[i
].fifo_len
;
806 page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
808 for (j
= 0; j
< page_num
; j
++) {
809 int mem_blks
= (j
* lst_per_page
);
810 if (!mac_control
->fifos
[i
].list_info
)
812 if (!mac_control
->fifos
[i
].list_info
[mem_blks
].
815 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
816 mac_control
->fifos
[i
].
819 mac_control
->fifos
[i
].
822 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
825 /* If we got a zero DMA address during allocation,
828 if (mac_control
->zerodma_virt_addr
) {
829 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
830 mac_control
->zerodma_virt_addr
,
833 "%s: Freeing TxDL with zero DMA addr. ",
835 DBG_PRINT(INIT_DBG
, "Virtual address %p\n",
836 mac_control
->zerodma_virt_addr
);
837 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
840 kfree(mac_control
->fifos
[i
].list_info
);
841 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
842 (nic
->config
.tx_cfg
[i
].fifo_len
*sizeof(struct list_info_hold
));
845 size
= SIZE_OF_BLOCK
;
846 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
847 blk_cnt
= mac_control
->rings
[i
].block_count
;
848 for (j
= 0; j
< blk_cnt
; j
++) {
849 tmp_v_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
851 tmp_p_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
853 if (tmp_v_addr
== NULL
)
855 pci_free_consistent(nic
->pdev
, size
,
856 tmp_v_addr
, tmp_p_addr
);
857 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= size
;
858 kfree(mac_control
->rings
[i
].rx_blocks
[j
].rxds
);
859 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
860 ( sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
864 if (nic
->rxd_mode
>= RXD_MODE_3A
) {
865 /* Freeing buffer storage addresses in 2BUFF mode. */
866 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
867 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
868 (rxd_count
[nic
->rxd_mode
] + 1);
869 for (j
= 0; j
< blk_cnt
; j
++) {
871 if (!mac_control
->rings
[i
].ba
[j
])
873 while (k
!= rxd_count
[nic
->rxd_mode
]) {
875 &mac_control
->rings
[i
].ba
[j
][k
];
877 nic
->mac_control
.stats_info
->sw_stat
.\
878 mem_freed
+= (BUF0_LEN
+ ALIGN_SIZE
);
880 nic
->mac_control
.stats_info
->sw_stat
.\
881 mem_freed
+= (BUF1_LEN
+ ALIGN_SIZE
);
884 kfree(mac_control
->rings
[i
].ba
[j
]);
885 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= (sizeof(struct buffAdd
) *
886 (rxd_count
[nic
->rxd_mode
] + 1));
888 kfree(mac_control
->rings
[i
].ba
);
889 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
890 (sizeof(struct buffAdd
*) * blk_cnt
);
894 if (mac_control
->stats_mem
) {
895 pci_free_consistent(nic
->pdev
,
896 mac_control
->stats_mem_sz
,
897 mac_control
->stats_mem
,
898 mac_control
->stats_mem_phy
);
899 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
900 mac_control
->stats_mem_sz
;
902 if (nic
->ufo_in_band_v
) {
903 kfree(nic
->ufo_in_band_v
);
904 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
905 += (ufo_size
* sizeof(u64
));
910 * s2io_verify_pci_mode -
913 static int s2io_verify_pci_mode(struct s2io_nic
*nic
)
915 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
916 register u64 val64
= 0;
919 val64
= readq(&bar0
->pci_mode
);
920 mode
= (u8
)GET_PCI_MODE(val64
);
922 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
923 return -1; /* Unknown PCI mode */
927 #define NEC_VENID 0x1033
928 #define NEC_DEVID 0x0125
929 static int s2io_on_nec_bridge(struct pci_dev
*s2io_pdev
)
931 struct pci_dev
*tdev
= NULL
;
932 while ((tdev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, tdev
)) != NULL
) {
933 if (tdev
->vendor
== NEC_VENID
&& tdev
->device
== NEC_DEVID
) {
934 if (tdev
->bus
== s2io_pdev
->bus
->parent
)
942 static int bus_speed
[8] = {33, 133, 133, 200, 266, 133, 200, 266};
944 * s2io_print_pci_mode -
946 static int s2io_print_pci_mode(struct s2io_nic
*nic
)
948 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
949 register u64 val64
= 0;
951 struct config_param
*config
= &nic
->config
;
953 val64
= readq(&bar0
->pci_mode
);
954 mode
= (u8
)GET_PCI_MODE(val64
);
956 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
957 return -1; /* Unknown PCI mode */
959 config
->bus_speed
= bus_speed
[mode
];
961 if (s2io_on_nec_bridge(nic
->pdev
)) {
962 DBG_PRINT(ERR_DBG
, "%s: Device is on PCI-E bus\n",
967 if (val64
& PCI_MODE_32_BITS
) {
968 DBG_PRINT(ERR_DBG
, "%s: Device is on 32 bit ", nic
->dev
->name
);
970 DBG_PRINT(ERR_DBG
, "%s: Device is on 64 bit ", nic
->dev
->name
);
974 case PCI_MODE_PCI_33
:
975 DBG_PRINT(ERR_DBG
, "33MHz PCI bus\n");
977 case PCI_MODE_PCI_66
:
978 DBG_PRINT(ERR_DBG
, "66MHz PCI bus\n");
980 case PCI_MODE_PCIX_M1_66
:
981 DBG_PRINT(ERR_DBG
, "66MHz PCIX(M1) bus\n");
983 case PCI_MODE_PCIX_M1_100
:
984 DBG_PRINT(ERR_DBG
, "100MHz PCIX(M1) bus\n");
986 case PCI_MODE_PCIX_M1_133
:
987 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M1) bus\n");
989 case PCI_MODE_PCIX_M2_66
:
990 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M2) bus\n");
992 case PCI_MODE_PCIX_M2_100
:
993 DBG_PRINT(ERR_DBG
, "200MHz PCIX(M2) bus\n");
995 case PCI_MODE_PCIX_M2_133
:
996 DBG_PRINT(ERR_DBG
, "266MHz PCIX(M2) bus\n");
999 return -1; /* Unsupported bus speed */
1006 * init_nic - Initialization of hardware
1007 * @nic: device peivate variable
1008 * Description: The function sequentially configures every block
1009 * of the H/W from their reset values.
1010 * Return Value: SUCCESS on success and
1011 * '-1' on failure (endian settings incorrect).
1014 static int init_nic(struct s2io_nic
*nic
)
1016 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1017 struct net_device
*dev
= nic
->dev
;
1018 register u64 val64
= 0;
1022 struct mac_info
*mac_control
;
1023 struct config_param
*config
;
1025 unsigned long long mem_share
;
1028 mac_control
= &nic
->mac_control
;
1029 config
= &nic
->config
;
1031 /* to set the swapper controle on the card */
1032 if(s2io_set_swapper(nic
)) {
1033 DBG_PRINT(ERR_DBG
,"ERROR: Setting Swapper failed\n");
1038 * Herc requires EOI to be removed from reset before XGXS, so..
1040 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1041 val64
= 0xA500000000ULL
;
1042 writeq(val64
, &bar0
->sw_reset
);
1044 val64
= readq(&bar0
->sw_reset
);
1047 /* Remove XGXS from reset state */
1049 writeq(val64
, &bar0
->sw_reset
);
1051 val64
= readq(&bar0
->sw_reset
);
1053 /* Enable Receiving broadcasts */
1054 add
= &bar0
->mac_cfg
;
1055 val64
= readq(&bar0
->mac_cfg
);
1056 val64
|= MAC_RMAC_BCAST_ENABLE
;
1057 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1058 writel((u32
) val64
, add
);
1059 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1060 writel((u32
) (val64
>> 32), (add
+ 4));
1062 /* Read registers in all blocks */
1063 val64
= readq(&bar0
->mac_int_mask
);
1064 val64
= readq(&bar0
->mc_int_mask
);
1065 val64
= readq(&bar0
->xgxs_int_mask
);
1069 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
1071 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1072 while (herc_act_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1073 SPECIAL_REG_WRITE(herc_act_dtx_cfg
[dtx_cnt
],
1074 &bar0
->dtx_control
, UF
);
1076 msleep(1); /* Necessary!! */
1080 while (xena_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1081 SPECIAL_REG_WRITE(xena_dtx_cfg
[dtx_cnt
],
1082 &bar0
->dtx_control
, UF
);
1083 val64
= readq(&bar0
->dtx_control
);
1088 /* Tx DMA Initialization */
1090 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1091 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1092 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1093 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1096 for (i
= 0, j
= 0; i
< config
->tx_fifo_num
; i
++) {
1098 vBIT(config
->tx_cfg
[i
].fifo_len
- 1, ((i
* 32) + 19),
1099 13) | vBIT(config
->tx_cfg
[i
].fifo_priority
,
1102 if (i
== (config
->tx_fifo_num
- 1)) {
1109 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1113 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1117 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1121 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1127 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1128 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1130 if ((nic
->device_type
== XFRAME_I_DEVICE
) &&
1131 (get_xena_rev_id(nic
->pdev
) < 4))
1132 writeq(PCC_ENABLE_FOUR
, &bar0
->pcc_enable
);
1134 val64
= readq(&bar0
->tx_fifo_partition_0
);
1135 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
1136 &bar0
->tx_fifo_partition_0
, (unsigned long long) val64
);
1139 * Initialization of Tx_PA_CONFIG register to ignore packet
1140 * integrity checking.
1142 val64
= readq(&bar0
->tx_pa_cfg
);
1143 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
| TX_PA_CFG_IGNORE_SNAP_OUI
|
1144 TX_PA_CFG_IGNORE_LLC_CTRL
| TX_PA_CFG_IGNORE_L2_ERR
;
1145 writeq(val64
, &bar0
->tx_pa_cfg
);
1147 /* Rx DMA intialization. */
1149 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1151 vBIT(config
->rx_cfg
[i
].ring_priority
, (5 + (i
* 8)),
1154 writeq(val64
, &bar0
->rx_queue_priority
);
1157 * Allocating equal share of memory to all the
1161 if (nic
->device_type
& XFRAME_II_DEVICE
)
1166 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1169 mem_share
= (mem_size
/ config
->rx_ring_num
+
1170 mem_size
% config
->rx_ring_num
);
1171 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
1174 mem_share
= (mem_size
/ config
->rx_ring_num
);
1175 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
1178 mem_share
= (mem_size
/ config
->rx_ring_num
);
1179 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
1182 mem_share
= (mem_size
/ config
->rx_ring_num
);
1183 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
1186 mem_share
= (mem_size
/ config
->rx_ring_num
);
1187 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
1190 mem_share
= (mem_size
/ config
->rx_ring_num
);
1191 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
1194 mem_share
= (mem_size
/ config
->rx_ring_num
);
1195 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
1198 mem_share
= (mem_size
/ config
->rx_ring_num
);
1199 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
1203 writeq(val64
, &bar0
->rx_queue_cfg
);
1206 * Filling Tx round robin registers
1207 * as per the number of FIFOs
1209 switch (config
->tx_fifo_num
) {
1211 val64
= 0x0000000000000000ULL
;
1212 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1213 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1214 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1215 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1216 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1219 val64
= 0x0000010000010000ULL
;
1220 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1221 val64
= 0x0100000100000100ULL
;
1222 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1223 val64
= 0x0001000001000001ULL
;
1224 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1225 val64
= 0x0000010000010000ULL
;
1226 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1227 val64
= 0x0100000000000000ULL
;
1228 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1231 val64
= 0x0001000102000001ULL
;
1232 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1233 val64
= 0x0001020000010001ULL
;
1234 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1235 val64
= 0x0200000100010200ULL
;
1236 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1237 val64
= 0x0001000102000001ULL
;
1238 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1239 val64
= 0x0001020000000000ULL
;
1240 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1243 val64
= 0x0001020300010200ULL
;
1244 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1245 val64
= 0x0100000102030001ULL
;
1246 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1247 val64
= 0x0200010000010203ULL
;
1248 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1249 val64
= 0x0001020001000001ULL
;
1250 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1251 val64
= 0x0203000100000000ULL
;
1252 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1255 val64
= 0x0001000203000102ULL
;
1256 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1257 val64
= 0x0001020001030004ULL
;
1258 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1259 val64
= 0x0001000203000102ULL
;
1260 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1261 val64
= 0x0001020001030004ULL
;
1262 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1263 val64
= 0x0001000000000000ULL
;
1264 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1267 val64
= 0x0001020304000102ULL
;
1268 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1269 val64
= 0x0304050001020001ULL
;
1270 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1271 val64
= 0x0203000100000102ULL
;
1272 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1273 val64
= 0x0304000102030405ULL
;
1274 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1275 val64
= 0x0001000200000000ULL
;
1276 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1279 val64
= 0x0001020001020300ULL
;
1280 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1281 val64
= 0x0102030400010203ULL
;
1282 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1283 val64
= 0x0405060001020001ULL
;
1284 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1285 val64
= 0x0304050000010200ULL
;
1286 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1287 val64
= 0x0102030000000000ULL
;
1288 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1291 val64
= 0x0001020300040105ULL
;
1292 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1293 val64
= 0x0200030106000204ULL
;
1294 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1295 val64
= 0x0103000502010007ULL
;
1296 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1297 val64
= 0x0304010002060500ULL
;
1298 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1299 val64
= 0x0103020400000000ULL
;
1300 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1304 /* Enable all configured Tx FIFO partitions */
1305 val64
= readq(&bar0
->tx_fifo_partition_0
);
1306 val64
|= (TX_FIFO_PARTITION_EN
);
1307 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1309 /* Filling the Rx round robin registers as per the
1310 * number of Rings and steering based on QoS.
1312 switch (config
->rx_ring_num
) {
1314 val64
= 0x8080808080808080ULL
;
1315 writeq(val64
, &bar0
->rts_qos_steering
);
1318 val64
= 0x0000010000010000ULL
;
1319 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1320 val64
= 0x0100000100000100ULL
;
1321 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1322 val64
= 0x0001000001000001ULL
;
1323 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1324 val64
= 0x0000010000010000ULL
;
1325 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1326 val64
= 0x0100000000000000ULL
;
1327 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1329 val64
= 0x8080808040404040ULL
;
1330 writeq(val64
, &bar0
->rts_qos_steering
);
1333 val64
= 0x0001000102000001ULL
;
1334 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1335 val64
= 0x0001020000010001ULL
;
1336 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1337 val64
= 0x0200000100010200ULL
;
1338 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1339 val64
= 0x0001000102000001ULL
;
1340 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1341 val64
= 0x0001020000000000ULL
;
1342 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1344 val64
= 0x8080804040402020ULL
;
1345 writeq(val64
, &bar0
->rts_qos_steering
);
1348 val64
= 0x0001020300010200ULL
;
1349 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1350 val64
= 0x0100000102030001ULL
;
1351 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1352 val64
= 0x0200010000010203ULL
;
1353 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1354 val64
= 0x0001020001000001ULL
;
1355 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1356 val64
= 0x0203000100000000ULL
;
1357 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1359 val64
= 0x8080404020201010ULL
;
1360 writeq(val64
, &bar0
->rts_qos_steering
);
1363 val64
= 0x0001000203000102ULL
;
1364 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1365 val64
= 0x0001020001030004ULL
;
1366 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1367 val64
= 0x0001000203000102ULL
;
1368 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1369 val64
= 0x0001020001030004ULL
;
1370 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1371 val64
= 0x0001000000000000ULL
;
1372 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1374 val64
= 0x8080404020201008ULL
;
1375 writeq(val64
, &bar0
->rts_qos_steering
);
1378 val64
= 0x0001020304000102ULL
;
1379 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1380 val64
= 0x0304050001020001ULL
;
1381 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1382 val64
= 0x0203000100000102ULL
;
1383 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1384 val64
= 0x0304000102030405ULL
;
1385 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1386 val64
= 0x0001000200000000ULL
;
1387 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1389 val64
= 0x8080404020100804ULL
;
1390 writeq(val64
, &bar0
->rts_qos_steering
);
1393 val64
= 0x0001020001020300ULL
;
1394 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1395 val64
= 0x0102030400010203ULL
;
1396 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1397 val64
= 0x0405060001020001ULL
;
1398 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1399 val64
= 0x0304050000010200ULL
;
1400 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1401 val64
= 0x0102030000000000ULL
;
1402 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1404 val64
= 0x8080402010080402ULL
;
1405 writeq(val64
, &bar0
->rts_qos_steering
);
1408 val64
= 0x0001020300040105ULL
;
1409 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1410 val64
= 0x0200030106000204ULL
;
1411 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1412 val64
= 0x0103000502010007ULL
;
1413 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1414 val64
= 0x0304010002060500ULL
;
1415 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1416 val64
= 0x0103020400000000ULL
;
1417 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1419 val64
= 0x8040201008040201ULL
;
1420 writeq(val64
, &bar0
->rts_qos_steering
);
1426 for (i
= 0; i
< 8; i
++)
1427 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1429 /* Set the default rts frame length for the rings configured */
1430 val64
= MAC_RTS_FRM_LEN_SET(dev
->mtu
+22);
1431 for (i
= 0 ; i
< config
->rx_ring_num
; i
++)
1432 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1434 /* Set the frame length for the configured rings
1435 * desired by the user
1437 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1438 /* If rts_frm_len[i] == 0 then it is assumed that user not
1439 * specified frame length steering.
1440 * If the user provides the frame length then program
1441 * the rts_frm_len register for those values or else
1442 * leave it as it is.
1444 if (rts_frm_len
[i
] != 0) {
1445 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len
[i
]),
1446 &bar0
->rts_frm_len_n
[i
]);
1450 /* Disable differentiated services steering logic */
1451 for (i
= 0; i
< 64; i
++) {
1452 if (rts_ds_steer(nic
, i
, 0) == FAILURE
) {
1453 DBG_PRINT(ERR_DBG
, "%s: failed rts ds steering",
1455 DBG_PRINT(ERR_DBG
, "set on codepoint %d\n", i
);
1460 /* Program statistics memory */
1461 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
1463 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1464 val64
= STAT_BC(0x320);
1465 writeq(val64
, &bar0
->stat_byte_cnt
);
1469 * Initializing the sampling rate for the device to calculate the
1470 * bandwidth utilization.
1472 val64
= MAC_TX_LINK_UTIL_VAL(tmac_util_period
) |
1473 MAC_RX_LINK_UTIL_VAL(rmac_util_period
);
1474 writeq(val64
, &bar0
->mac_link_util
);
1478 * Initializing the Transmit and Receive Traffic Interrupt
1482 * TTI Initialization. Default Tx timer gets us about
1483 * 250 interrupts per sec. Continuous interrupts are enabled
1486 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1487 int count
= (nic
->config
.bus_speed
* 125)/2;
1488 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(count
);
1491 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1493 val64
|= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1494 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1495 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN
;
1496 if (use_continuous_tx_intrs
)
1497 val64
|= TTI_DATA1_MEM_TX_TIMER_CI_EN
;
1498 writeq(val64
, &bar0
->tti_data1_mem
);
1500 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1501 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1502 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1503 writeq(val64
, &bar0
->tti_data2_mem
);
1505 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1506 writeq(val64
, &bar0
->tti_command_mem
);
1509 * Once the operation completes, the Strobe bit of the command
1510 * register will be reset. We poll for this particular condition
1511 * We wait for a maximum of 500ms for the operation to complete,
1512 * if it's not complete by then we return error.
1516 val64
= readq(&bar0
->tti_command_mem
);
1517 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1521 DBG_PRINT(ERR_DBG
, "%s: TTI init Failed\n",
1529 if (nic
->config
.bimodal
) {
1531 for (k
= 0; k
< config
->rx_ring_num
; k
++) {
1532 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1533 val64
|= TTI_CMD_MEM_OFFSET(0x38+k
);
1534 writeq(val64
, &bar0
->tti_command_mem
);
1537 * Once the operation completes, the Strobe bit of the command
1538 * register will be reset. We poll for this particular condition
1539 * We wait for a maximum of 500ms for the operation to complete,
1540 * if it's not complete by then we return error.
1544 val64
= readq(&bar0
->tti_command_mem
);
1545 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1550 "%s: TTI init Failed\n",
1560 /* RTI Initialization */
1561 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1563 * Programmed to generate Apprx 500 Intrs per
1566 int count
= (nic
->config
.bus_speed
* 125)/4;
1567 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(count
);
1569 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1571 val64
|= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1572 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1573 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN
;
1575 writeq(val64
, &bar0
->rti_data1_mem
);
1577 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) |
1578 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1579 if (nic
->intr_type
== MSI_X
)
1580 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1581 RTI_DATA2_MEM_RX_UFC_D(0x40));
1583 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1584 RTI_DATA2_MEM_RX_UFC_D(0x80));
1585 writeq(val64
, &bar0
->rti_data2_mem
);
1587 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1588 val64
= RTI_CMD_MEM_WE
| RTI_CMD_MEM_STROBE_NEW_CMD
1589 | RTI_CMD_MEM_OFFSET(i
);
1590 writeq(val64
, &bar0
->rti_command_mem
);
1593 * Once the operation completes, the Strobe bit of the
1594 * command register will be reset. We poll for this
1595 * particular condition. We wait for a maximum of 500ms
1596 * for the operation to complete, if it's not complete
1597 * by then we return error.
1601 val64
= readq(&bar0
->rti_command_mem
);
1602 if (!(val64
& RTI_CMD_MEM_STROBE_NEW_CMD
)) {
1606 DBG_PRINT(ERR_DBG
, "%s: RTI init Failed\n",
1617 * Initializing proper values as Pause threshold into all
1618 * the 8 Queues on Rx side.
1620 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
1621 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
1623 /* Disable RMAC PAD STRIPPING */
1624 add
= &bar0
->mac_cfg
;
1625 val64
= readq(&bar0
->mac_cfg
);
1626 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
1627 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1628 writel((u32
) (val64
), add
);
1629 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1630 writel((u32
) (val64
>> 32), (add
+ 4));
1631 val64
= readq(&bar0
->mac_cfg
);
1633 /* Enable FCS stripping by adapter */
1634 add
= &bar0
->mac_cfg
;
1635 val64
= readq(&bar0
->mac_cfg
);
1636 val64
|= MAC_CFG_RMAC_STRIP_FCS
;
1637 if (nic
->device_type
== XFRAME_II_DEVICE
)
1638 writeq(val64
, &bar0
->mac_cfg
);
1640 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1641 writel((u32
) (val64
), add
);
1642 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1643 writel((u32
) (val64
>> 32), (add
+ 4));
1647 * Set the time value to be inserted in the pause frame
1648 * generated by xena.
1650 val64
= readq(&bar0
->rmac_pause_cfg
);
1651 val64
&= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1652 val64
|= RMAC_PAUSE_HG_PTIME(nic
->mac_control
.rmac_pause_time
);
1653 writeq(val64
, &bar0
->rmac_pause_cfg
);
1656 * Set the Threshold Limit for Generating the pause frame
1657 * If the amount of data in any Queue exceeds ratio of
1658 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1659 * pause frame is generated
1662 for (i
= 0; i
< 4; i
++) {
1664 (((u64
) 0xFF00 | nic
->mac_control
.
1665 mc_pause_threshold_q0q3
)
1668 writeq(val64
, &bar0
->mc_pause_thresh_q0q3
);
1671 for (i
= 0; i
< 4; i
++) {
1673 (((u64
) 0xFF00 | nic
->mac_control
.
1674 mc_pause_threshold_q4q7
)
1677 writeq(val64
, &bar0
->mc_pause_thresh_q4q7
);
1680 * TxDMA will stop Read request if the number of read split has
1681 * exceeded the limit pointed by shared_splits
1683 val64
= readq(&bar0
->pic_control
);
1684 val64
|= PIC_CNTL_SHARED_SPLITS(shared_splits
);
1685 writeq(val64
, &bar0
->pic_control
);
1687 if (nic
->config
.bus_speed
== 266) {
1688 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN
, &bar0
->txreqtimeout
);
1689 writeq(0x0, &bar0
->read_retry_delay
);
1690 writeq(0x0, &bar0
->write_retry_delay
);
1694 * Programming the Herc to split every write transaction
1695 * that does not start on an ADB to reduce disconnects.
1697 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1698 val64
= FAULT_BEHAVIOUR
| EXT_REQ_EN
|
1699 MISC_LINK_STABILITY_PRD(3);
1700 writeq(val64
, &bar0
->misc_control
);
1701 val64
= readq(&bar0
->pic_control2
);
1702 val64
&= ~(BIT(13)|BIT(14)|BIT(15));
1703 writeq(val64
, &bar0
->pic_control2
);
1705 if (strstr(nic
->product_name
, "CX4")) {
1706 val64
= TMAC_AVG_IPG(0x17);
1707 writeq(val64
, &bar0
->tmac_avg_ipg
);
1712 #define LINK_UP_DOWN_INTERRUPT 1
1713 #define MAC_RMAC_ERR_TIMER 2
1715 static int s2io_link_fault_indication(struct s2io_nic
*nic
)
1717 if (nic
->intr_type
!= INTA
)
1718 return MAC_RMAC_ERR_TIMER
;
1719 if (nic
->device_type
== XFRAME_II_DEVICE
)
1720 return LINK_UP_DOWN_INTERRUPT
;
1722 return MAC_RMAC_ERR_TIMER
;
1726 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1727 * @nic: device private variable,
1728 * @mask: A mask indicating which Intr block must be modified and,
1729 * @flag: A flag indicating whether to enable or disable the Intrs.
1730 * Description: This function will either disable or enable the interrupts
1731 * depending on the flag argument. The mask argument can be used to
1732 * enable/disable any Intr block.
1733 * Return Value: NONE.
1736 static void en_dis_able_nic_intrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
1738 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1739 register u64 val64
= 0, temp64
= 0;
1741 /* Top level interrupt classification */
1742 /* PIC Interrupts */
1743 if ((mask
& (TX_PIC_INTR
| RX_PIC_INTR
))) {
1744 /* Enable PIC Intrs in the general intr mask register */
1745 val64
= TXPIC_INT_M
;
1746 if (flag
== ENABLE_INTRS
) {
1747 temp64
= readq(&bar0
->general_int_mask
);
1748 temp64
&= ~((u64
) val64
);
1749 writeq(temp64
, &bar0
->general_int_mask
);
1751 * If Hercules adapter enable GPIO otherwise
1752 * disable all PCIX, Flash, MDIO, IIC and GPIO
1753 * interrupts for now.
1756 if (s2io_link_fault_indication(nic
) ==
1757 LINK_UP_DOWN_INTERRUPT
) {
1758 temp64
= readq(&bar0
->pic_int_mask
);
1759 temp64
&= ~((u64
) PIC_INT_GPIO
);
1760 writeq(temp64
, &bar0
->pic_int_mask
);
1761 temp64
= readq(&bar0
->gpio_int_mask
);
1762 temp64
&= ~((u64
) GPIO_INT_MASK_LINK_UP
);
1763 writeq(temp64
, &bar0
->gpio_int_mask
);
1765 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1768 * No MSI Support is available presently, so TTI and
1769 * RTI interrupts are also disabled.
1771 } else if (flag
== DISABLE_INTRS
) {
1773 * Disable PIC Intrs in the general
1774 * intr mask register
1776 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1777 temp64
= readq(&bar0
->general_int_mask
);
1779 writeq(val64
, &bar0
->general_int_mask
);
1783 /* MAC Interrupts */
1784 /* Enabling/Disabling MAC interrupts */
1785 if (mask
& (TX_MAC_INTR
| RX_MAC_INTR
)) {
1786 val64
= TXMAC_INT_M
| RXMAC_INT_M
;
1787 if (flag
== ENABLE_INTRS
) {
1788 temp64
= readq(&bar0
->general_int_mask
);
1789 temp64
&= ~((u64
) val64
);
1790 writeq(temp64
, &bar0
->general_int_mask
);
1792 * All MAC block error interrupts are disabled for now
1795 } else if (flag
== DISABLE_INTRS
) {
1797 * Disable MAC Intrs in the general intr mask register
1799 writeq(DISABLE_ALL_INTRS
, &bar0
->mac_int_mask
);
1800 writeq(DISABLE_ALL_INTRS
,
1801 &bar0
->mac_rmac_err_mask
);
1803 temp64
= readq(&bar0
->general_int_mask
);
1805 writeq(val64
, &bar0
->general_int_mask
);
1809 /* Tx traffic interrupts */
1810 if (mask
& TX_TRAFFIC_INTR
) {
1811 val64
= TXTRAFFIC_INT_M
;
1812 if (flag
== ENABLE_INTRS
) {
1813 temp64
= readq(&bar0
->general_int_mask
);
1814 temp64
&= ~((u64
) val64
);
1815 writeq(temp64
, &bar0
->general_int_mask
);
1817 * Enable all the Tx side interrupts
1818 * writing 0 Enables all 64 TX interrupt levels
1820 writeq(0x0, &bar0
->tx_traffic_mask
);
1821 } else if (flag
== DISABLE_INTRS
) {
1823 * Disable Tx Traffic Intrs in the general intr mask
1826 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
1827 temp64
= readq(&bar0
->general_int_mask
);
1829 writeq(val64
, &bar0
->general_int_mask
);
1833 /* Rx traffic interrupts */
1834 if (mask
& RX_TRAFFIC_INTR
) {
1835 val64
= RXTRAFFIC_INT_M
;
1836 if (flag
== ENABLE_INTRS
) {
1837 temp64
= readq(&bar0
->general_int_mask
);
1838 temp64
&= ~((u64
) val64
);
1839 writeq(temp64
, &bar0
->general_int_mask
);
1840 /* writing 0 Enables all 8 RX interrupt levels */
1841 writeq(0x0, &bar0
->rx_traffic_mask
);
1842 } else if (flag
== DISABLE_INTRS
) {
1844 * Disable Rx Traffic Intrs in the general intr mask
1847 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
1848 temp64
= readq(&bar0
->general_int_mask
);
1850 writeq(val64
, &bar0
->general_int_mask
);
1856 * verify_pcc_quiescent- Checks for PCC quiescent state
1857 * Return: 1 If PCC is quiescence
1858 * 0 If PCC is not quiescence
1860 static int verify_pcc_quiescent(struct s2io_nic
*sp
, int flag
)
1863 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1864 u64 val64
= readq(&bar0
->adapter_status
);
1866 herc
= (sp
->device_type
== XFRAME_II_DEVICE
);
1868 if (flag
== FALSE
) {
1869 if ((!herc
&& (get_xena_rev_id(sp
->pdev
) >= 4)) || herc
) {
1870 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
))
1873 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
1877 if ((!herc
&& (get_xena_rev_id(sp
->pdev
) >= 4)) || herc
) {
1878 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
1879 ADAPTER_STATUS_RMAC_PCC_IDLE
))
1882 if (((val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) ==
1883 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
1891 * verify_xena_quiescence - Checks whether the H/W is ready
1892 * Description: Returns whether the H/W is ready to go or not. Depending
1893 * on whether adapter enable bit was written or not the comparison
1894 * differs and the calling function passes the input argument flag to
1896 * Return: 1 If xena is quiescence
1897 * 0 If Xena is not quiescence
1900 static int verify_xena_quiescence(struct s2io_nic
*sp
)
1903 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1904 u64 val64
= readq(&bar0
->adapter_status
);
1905 mode
= s2io_verify_pci_mode(sp
);
1907 if (!(val64
& ADAPTER_STATUS_TDMA_READY
)) {
1908 DBG_PRINT(ERR_DBG
, "%s", "TDMA is not ready!");
1911 if (!(val64
& ADAPTER_STATUS_RDMA_READY
)) {
1912 DBG_PRINT(ERR_DBG
, "%s", "RDMA is not ready!");
1915 if (!(val64
& ADAPTER_STATUS_PFC_READY
)) {
1916 DBG_PRINT(ERR_DBG
, "%s", "PFC is not ready!");
1919 if (!(val64
& ADAPTER_STATUS_TMAC_BUF_EMPTY
)) {
1920 DBG_PRINT(ERR_DBG
, "%s", "TMAC BUF is not empty!");
1923 if (!(val64
& ADAPTER_STATUS_PIC_QUIESCENT
)) {
1924 DBG_PRINT(ERR_DBG
, "%s", "PIC is not QUIESCENT!");
1927 if (!(val64
& ADAPTER_STATUS_MC_DRAM_READY
)) {
1928 DBG_PRINT(ERR_DBG
, "%s", "MC_DRAM is not ready!");
1931 if (!(val64
& ADAPTER_STATUS_MC_QUEUES_READY
)) {
1932 DBG_PRINT(ERR_DBG
, "%s", "MC_QUEUES is not ready!");
1935 if (!(val64
& ADAPTER_STATUS_M_PLL_LOCK
)) {
1936 DBG_PRINT(ERR_DBG
, "%s", "M_PLL is not locked!");
1941 * In PCI 33 mode, the P_PLL is not used, and therefore,
1942 * the the P_PLL_LOCK bit in the adapter_status register will
1945 if (!(val64
& ADAPTER_STATUS_P_PLL_LOCK
) &&
1946 sp
->device_type
== XFRAME_II_DEVICE
&& mode
!=
1948 DBG_PRINT(ERR_DBG
, "%s", "P_PLL is not locked!");
1951 if (!((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1952 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
1953 DBG_PRINT(ERR_DBG
, "%s", "RC_PRC is not QUIESCENT!");
1960 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1961 * @sp: Pointer to device specifc structure
1963 * New procedure to clear mac address reading problems on Alpha platforms
1967 static void fix_mac_address(struct s2io_nic
* sp
)
1969 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1973 while (fix_mac
[i
] != END_SIGN
) {
1974 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
1976 val64
= readq(&bar0
->gpio_control
);
1981 * start_nic - Turns the device on
1982 * @nic : device private variable.
1984 * This function actually turns the device on. Before this function is
1985 * called,all Registers are configured from their reset states
1986 * and shared memory is allocated but the NIC is still quiescent. On
1987 * calling this function, the device interrupts are cleared and the NIC is
1988 * literally switched on by writing into the adapter control register.
1990 * SUCCESS on success and -1 on failure.
1993 static int start_nic(struct s2io_nic
*nic
)
1995 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1996 struct net_device
*dev
= nic
->dev
;
1997 register u64 val64
= 0;
1999 struct mac_info
*mac_control
;
2000 struct config_param
*config
;
2002 mac_control
= &nic
->mac_control
;
2003 config
= &nic
->config
;
2005 /* PRC Initialization and configuration */
2006 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2007 writeq((u64
) mac_control
->rings
[i
].rx_blocks
[0].block_dma_addr
,
2008 &bar0
->prc_rxd0_n
[i
]);
2010 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
2011 if (nic
->config
.bimodal
)
2012 val64
|= PRC_CTRL_BIMODAL_INTERRUPT
;
2013 if (nic
->rxd_mode
== RXD_MODE_1
)
2014 val64
|= PRC_CTRL_RC_ENABLED
;
2016 val64
|= PRC_CTRL_RC_ENABLED
| PRC_CTRL_RING_MODE_3
;
2017 if (nic
->device_type
== XFRAME_II_DEVICE
)
2018 val64
|= PRC_CTRL_GROUP_READS
;
2019 val64
&= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2020 val64
|= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2021 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
2024 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2025 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2026 val64
= readq(&bar0
->rx_pa_cfg
);
2027 val64
|= RX_PA_CFG_IGNORE_L2_ERR
;
2028 writeq(val64
, &bar0
->rx_pa_cfg
);
2031 if (vlan_tag_strip
== 0) {
2032 val64
= readq(&bar0
->rx_pa_cfg
);
2033 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
2034 writeq(val64
, &bar0
->rx_pa_cfg
);
2035 vlan_strip_flag
= 0;
2039 * Enabling MC-RLDRAM. After enabling the device, we timeout
2040 * for around 100ms, which is approximately the time required
2041 * for the device to be ready for operation.
2043 val64
= readq(&bar0
->mc_rldram_mrs
);
2044 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
2045 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
2046 val64
= readq(&bar0
->mc_rldram_mrs
);
2048 msleep(100); /* Delay by around 100 ms. */
2050 /* Enabling ECC Protection. */
2051 val64
= readq(&bar0
->adapter_control
);
2052 val64
&= ~ADAPTER_ECC_EN
;
2053 writeq(val64
, &bar0
->adapter_control
);
2056 * Clearing any possible Link state change interrupts that
2057 * could have popped up just before Enabling the card.
2059 val64
= readq(&bar0
->mac_rmac_err_reg
);
2061 writeq(val64
, &bar0
->mac_rmac_err_reg
);
2064 * Verify if the device is ready to be enabled, if so enable
2067 val64
= readq(&bar0
->adapter_status
);
2068 if (!verify_xena_quiescence(nic
)) {
2069 DBG_PRINT(ERR_DBG
, "%s: device is not ready, ", dev
->name
);
2070 DBG_PRINT(ERR_DBG
, "Adapter status reads: 0x%llx\n",
2071 (unsigned long long) val64
);
2076 * With some switches, link might be already up at this point.
2077 * Because of this weird behavior, when we enable laser,
2078 * we may not get link. We need to handle this. We cannot
2079 * figure out which switch is misbehaving. So we are forced to
2080 * make a global change.
2083 /* Enabling Laser. */
2084 val64
= readq(&bar0
->adapter_control
);
2085 val64
|= ADAPTER_EOI_TX_ON
;
2086 writeq(val64
, &bar0
->adapter_control
);
2088 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
2090 * Dont see link state interrupts initally on some switches,
2091 * so directly scheduling the link state task here.
2093 schedule_work(&nic
->set_link_task
);
2095 /* SXE-002: Initialize link and activity LED */
2096 subid
= nic
->pdev
->subsystem_device
;
2097 if (((subid
& 0xFF) >= 0x07) &&
2098 (nic
->device_type
== XFRAME_I_DEVICE
)) {
2099 val64
= readq(&bar0
->gpio_control
);
2100 val64
|= 0x0000800000000000ULL
;
2101 writeq(val64
, &bar0
->gpio_control
);
2102 val64
= 0x0411040400000000ULL
;
2103 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
2109 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2111 static struct sk_buff
*s2io_txdl_getskb(struct fifo_info
*fifo_data
, struct \
2112 TxD
*txdlp
, int get_off
)
2114 struct s2io_nic
*nic
= fifo_data
->nic
;
2115 struct sk_buff
*skb
;
2120 if (txds
->Host_Control
== (u64
)(long)nic
->ufo_in_band_v
) {
2121 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2122 txds
->Buffer_Pointer
, sizeof(u64
),
2127 skb
= (struct sk_buff
*) ((unsigned long)
2128 txds
->Host_Control
);
2130 memset(txdlp
, 0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2133 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2134 txds
->Buffer_Pointer
,
2135 skb
->len
- skb
->data_len
,
2137 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2140 for (j
= 0; j
< frg_cnt
; j
++, txds
++) {
2141 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
2142 if (!txds
->Buffer_Pointer
)
2144 pci_unmap_page(nic
->pdev
, (dma_addr_t
)
2145 txds
->Buffer_Pointer
,
2146 frag
->size
, PCI_DMA_TODEVICE
);
2149 memset(txdlp
,0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2154 * free_tx_buffers - Free all queued Tx buffers
2155 * @nic : device private variable.
2157 * Free all queued Tx buffers.
2158 * Return Value: void
2161 static void free_tx_buffers(struct s2io_nic
*nic
)
2163 struct net_device
*dev
= nic
->dev
;
2164 struct sk_buff
*skb
;
2167 struct mac_info
*mac_control
;
2168 struct config_param
*config
;
2171 mac_control
= &nic
->mac_control
;
2172 config
= &nic
->config
;
2174 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
2175 for (j
= 0; j
< config
->tx_cfg
[i
].fifo_len
- 1; j
++) {
2176 txdp
= (struct TxD
*) \
2177 mac_control
->fifos
[i
].list_info
[j
].list_virt_addr
;
2178 skb
= s2io_txdl_getskb(&mac_control
->fifos
[i
], txdp
, j
);
2180 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
2187 "%s:forcibly freeing %d skbs on FIFO%d\n",
2189 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
2190 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
2195 * stop_nic - To stop the nic
2196 * @nic ; device private variable.
2198 * This function does exactly the opposite of what the start_nic()
2199 * function does. This function is called to stop the device.
2204 static void stop_nic(struct s2io_nic
*nic
)
2206 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2207 register u64 val64
= 0;
2209 struct mac_info
*mac_control
;
2210 struct config_param
*config
;
2212 mac_control
= &nic
->mac_control
;
2213 config
= &nic
->config
;
2215 /* Disable all interrupts */
2216 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
2217 interruptible
|= TX_PIC_INTR
| RX_PIC_INTR
;
2218 interruptible
|= TX_MAC_INTR
| RX_MAC_INTR
;
2219 en_dis_able_nic_intrs(nic
, interruptible
, DISABLE_INTRS
);
2221 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2222 val64
= readq(&bar0
->adapter_control
);
2223 val64
&= ~(ADAPTER_CNTL_EN
);
2224 writeq(val64
, &bar0
->adapter_control
);
2227 static int fill_rxd_3buf(struct s2io_nic
*nic
, struct RxD_t
*rxdp
, struct \
2230 struct net_device
*dev
= nic
->dev
;
2231 struct sk_buff
*frag_list
;
2234 /* Buffer-1 receives L3/L4 headers */
2235 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= pci_map_single
2236 (nic
->pdev
, skb
->data
, l3l4hdr_size
+ 4,
2237 PCI_DMA_FROMDEVICE
);
2239 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2240 skb_shinfo(skb
)->frag_list
= dev_alloc_skb(dev
->mtu
+ ALIGN_SIZE
);
2241 if (skb_shinfo(skb
)->frag_list
== NULL
) {
2242 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
2243 DBG_PRINT(INFO_DBG
, "%s: dev_alloc_skb failed\n ", dev
->name
);
2246 frag_list
= skb_shinfo(skb
)->frag_list
;
2247 skb
->truesize
+= frag_list
->truesize
;
2248 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
2249 += frag_list
->truesize
;
2250 frag_list
->next
= NULL
;
2251 tmp
= (void *)ALIGN((long)frag_list
->data
, ALIGN_SIZE
+ 1);
2252 frag_list
->data
= tmp
;
2253 skb_reset_tail_pointer(frag_list
);
2255 /* Buffer-2 receives L4 data payload */
2256 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= pci_map_single(nic
->pdev
,
2257 frag_list
->data
, dev
->mtu
,
2258 PCI_DMA_FROMDEVICE
);
2259 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(l3l4hdr_size
+ 4);
2260 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3(dev
->mtu
);
2266 * fill_rx_buffers - Allocates the Rx side skbs
2267 * @nic: device private variable
2268 * @ring_no: ring number
2270 * The function allocates Rx side skbs and puts the physical
2271 * address of these buffers into the RxD buffer pointers, so that the NIC
2272 * can DMA the received frame into these locations.
2273 * The NIC supports 3 receive modes, viz
2275 * 2. three buffer and
2276 * 3. Five buffer modes.
2277 * Each mode defines how many fragments the received frame will be split
2278 * up into by the NIC. The frame is split into L3 header, L4 Header,
2279 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2280 * is split into 3 fragments. As of now only single buffer mode is
2283 * SUCCESS on success or an appropriate -ve value on failure.
2286 static int fill_rx_buffers(struct s2io_nic
*nic
, int ring_no
)
2288 struct net_device
*dev
= nic
->dev
;
2289 struct sk_buff
*skb
;
2291 int off
, off1
, size
, block_no
, block_no1
;
2294 struct mac_info
*mac_control
;
2295 struct config_param
*config
;
2298 unsigned long flags
;
2299 struct RxD_t
*first_rxdp
= NULL
;
2300 u64 Buffer0_ptr
= 0, Buffer1_ptr
= 0;
2302 mac_control
= &nic
->mac_control
;
2303 config
= &nic
->config
;
2304 alloc_cnt
= mac_control
->rings
[ring_no
].pkt_cnt
-
2305 atomic_read(&nic
->rx_bufs_left
[ring_no
]);
2307 block_no1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.block_index
;
2308 off1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.offset
;
2309 while (alloc_tab
< alloc_cnt
) {
2310 block_no
= mac_control
->rings
[ring_no
].rx_curr_put_info
.
2312 off
= mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
;
2314 rxdp
= mac_control
->rings
[ring_no
].
2315 rx_blocks
[block_no
].rxds
[off
].virt_addr
;
2317 if ((block_no
== block_no1
) && (off
== off1
) &&
2318 (rxdp
->Host_Control
)) {
2319 DBG_PRINT(INTR_DBG
, "%s: Get and Put",
2321 DBG_PRINT(INTR_DBG
, " info equated\n");
2324 if (off
&& (off
== rxd_count
[nic
->rxd_mode
])) {
2325 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2327 if (mac_control
->rings
[ring_no
].rx_curr_put_info
.
2328 block_index
== mac_control
->rings
[ring_no
].
2330 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2332 block_no
= mac_control
->rings
[ring_no
].
2333 rx_curr_put_info
.block_index
;
2334 if (off
== rxd_count
[nic
->rxd_mode
])
2336 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2338 rxdp
= mac_control
->rings
[ring_no
].
2339 rx_blocks
[block_no
].block_virt_addr
;
2340 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
2344 spin_lock_irqsave(&nic
->put_lock
, flags
);
2345 mac_control
->rings
[ring_no
].put_pos
=
2346 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2347 spin_unlock_irqrestore(&nic
->put_lock
, flags
);
2349 mac_control
->rings
[ring_no
].put_pos
=
2350 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2352 if ((rxdp
->Control_1
& RXD_OWN_XENA
) &&
2353 ((nic
->rxd_mode
>= RXD_MODE_3A
) &&
2354 (rxdp
->Control_2
& BIT(0)))) {
2355 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2359 /* calculate size of skb based on ring mode */
2360 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
2361 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
2362 if (nic
->rxd_mode
== RXD_MODE_1
)
2363 size
+= NET_IP_ALIGN
;
2364 else if (nic
->rxd_mode
== RXD_MODE_3B
)
2365 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2367 size
= l3l4hdr_size
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2370 skb
= dev_alloc_skb(size
);
2372 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
2373 DBG_PRINT(INFO_DBG
, "memory to allocate SKBs\n");
2376 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2378 nic
->mac_control
.stats_info
->sw_stat
. \
2379 mem_alloc_fail_cnt
++;
2382 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
2384 if (nic
->rxd_mode
== RXD_MODE_1
) {
2385 /* 1 buffer mode - normal operation mode */
2386 memset(rxdp
, 0, sizeof(struct RxD1
));
2387 skb_reserve(skb
, NET_IP_ALIGN
);
2388 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= pci_map_single
2389 (nic
->pdev
, skb
->data
, size
- NET_IP_ALIGN
,
2390 PCI_DMA_FROMDEVICE
);
2392 SET_BUFFER0_SIZE_1(size
- NET_IP_ALIGN
);
2394 } else if (nic
->rxd_mode
>= RXD_MODE_3A
) {
2396 * 2 or 3 buffer mode -
2397 * Both 2 buffer mode and 3 buffer mode provides 128
2398 * byte aligned receive buffers.
2400 * 3 buffer mode provides header separation where in
2401 * skb->data will have L3/L4 headers where as
2402 * skb_shinfo(skb)->frag_list will have the L4 data
2406 /* save buffer pointers to avoid frequent dma mapping */
2407 Buffer0_ptr
= ((struct RxD3
*)rxdp
)->Buffer0_ptr
;
2408 Buffer1_ptr
= ((struct RxD3
*)rxdp
)->Buffer1_ptr
;
2409 memset(rxdp
, 0, sizeof(struct RxD3
));
2410 /* restore the buffer pointers for dma sync*/
2411 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= Buffer0_ptr
;
2412 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= Buffer1_ptr
;
2414 ba
= &mac_control
->rings
[ring_no
].ba
[block_no
][off
];
2415 skb_reserve(skb
, BUF0_LEN
);
2416 tmp
= (u64
)(unsigned long) skb
->data
;
2419 skb
->data
= (void *) (unsigned long)tmp
;
2420 skb_reset_tail_pointer(skb
);
2422 if (!(((struct RxD3
*)rxdp
)->Buffer0_ptr
))
2423 ((struct RxD3
*)rxdp
)->Buffer0_ptr
=
2424 pci_map_single(nic
->pdev
, ba
->ba_0
, BUF0_LEN
,
2425 PCI_DMA_FROMDEVICE
);
2427 pci_dma_sync_single_for_device(nic
->pdev
,
2428 (dma_addr_t
) ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2429 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2430 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
2431 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2432 /* Two buffer mode */
2435 * Buffer2 will have L3/L4 header plus
2438 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= pci_map_single
2439 (nic
->pdev
, skb
->data
, dev
->mtu
+ 4,
2440 PCI_DMA_FROMDEVICE
);
2442 /* Buffer-1 will be dummy buffer. Not used */
2443 if (!(((struct RxD3
*)rxdp
)->Buffer1_ptr
)) {
2444 ((struct RxD3
*)rxdp
)->Buffer1_ptr
=
2445 pci_map_single(nic
->pdev
,
2447 PCI_DMA_FROMDEVICE
);
2449 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
2450 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3
2454 if (fill_rxd_3buf(nic
, rxdp
, skb
) == -ENOMEM
) {
2455 nic
->mac_control
.stats_info
->sw_stat
.\
2456 mem_freed
+= skb
->truesize
;
2457 dev_kfree_skb_irq(skb
);
2460 first_rxdp
->Control_1
|=
2466 rxdp
->Control_2
|= BIT(0);
2468 rxdp
->Host_Control
= (unsigned long) (skb
);
2469 if (alloc_tab
& ((1 << rxsync_frequency
) - 1))
2470 rxdp
->Control_1
|= RXD_OWN_XENA
;
2472 if (off
== (rxd_count
[nic
->rxd_mode
] + 1))
2474 mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
= off
;
2476 rxdp
->Control_2
|= SET_RXD_MARKER
;
2477 if (!(alloc_tab
& ((1 << rxsync_frequency
) - 1))) {
2480 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2484 atomic_inc(&nic
->rx_bufs_left
[ring_no
]);
2489 /* Transfer ownership of first descriptor to adapter just before
2490 * exiting. Before that, use memory barrier so that ownership
2491 * and other fields are seen by adapter correctly.
2495 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2501 static void free_rxd_blk(struct s2io_nic
*sp
, int ring_no
, int blk
)
2503 struct net_device
*dev
= sp
->dev
;
2505 struct sk_buff
*skb
;
2507 struct mac_info
*mac_control
;
2510 mac_control
= &sp
->mac_control
;
2511 for (j
= 0 ; j
< rxd_count
[sp
->rxd_mode
]; j
++) {
2512 rxdp
= mac_control
->rings
[ring_no
].
2513 rx_blocks
[blk
].rxds
[j
].virt_addr
;
2514 skb
= (struct sk_buff
*)
2515 ((unsigned long) rxdp
->Host_Control
);
2519 if (sp
->rxd_mode
== RXD_MODE_1
) {
2520 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2521 ((struct RxD1
*)rxdp
)->Buffer0_ptr
,
2523 HEADER_ETHERNET_II_802_3_SIZE
2524 + HEADER_802_2_SIZE
+
2526 PCI_DMA_FROMDEVICE
);
2527 memset(rxdp
, 0, sizeof(struct RxD1
));
2528 } else if(sp
->rxd_mode
== RXD_MODE_3B
) {
2529 ba
= &mac_control
->rings
[ring_no
].
2531 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2532 ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2534 PCI_DMA_FROMDEVICE
);
2535 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2536 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2538 PCI_DMA_FROMDEVICE
);
2539 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2540 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2542 PCI_DMA_FROMDEVICE
);
2543 memset(rxdp
, 0, sizeof(struct RxD3
));
2545 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2546 ((struct RxD3
*)rxdp
)->Buffer0_ptr
, BUF0_LEN
,
2547 PCI_DMA_FROMDEVICE
);
2548 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2549 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2551 PCI_DMA_FROMDEVICE
);
2552 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2553 ((struct RxD3
*)rxdp
)->Buffer2_ptr
, dev
->mtu
,
2554 PCI_DMA_FROMDEVICE
);
2555 memset(rxdp
, 0, sizeof(struct RxD3
));
2557 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
2559 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
2564 * free_rx_buffers - Frees all Rx buffers
2565 * @sp: device private variable.
2567 * This function will free all Rx buffers allocated by host.
2572 static void free_rx_buffers(struct s2io_nic
*sp
)
2574 struct net_device
*dev
= sp
->dev
;
2575 int i
, blk
= 0, buf_cnt
= 0;
2576 struct mac_info
*mac_control
;
2577 struct config_param
*config
;
2579 mac_control
= &sp
->mac_control
;
2580 config
= &sp
->config
;
2582 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2583 for (blk
= 0; blk
< rx_ring_sz
[i
]; blk
++)
2584 free_rxd_blk(sp
,i
,blk
);
2586 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
2587 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
2588 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
2589 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
2590 atomic_set(&sp
->rx_bufs_left
[i
], 0);
2591 DBG_PRINT(INIT_DBG
, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2592 dev
->name
, buf_cnt
, i
);
2597 * s2io_poll - Rx interrupt handler for NAPI support
2598 * @dev : pointer to the device structure.
2599 * @budget : The number of packets that were budgeted to be processed
2600 * during one pass through the 'Poll" function.
2602 * Comes into picture only if NAPI support has been incorporated. It does
2603 * the same thing that rx_intr_handler does, but not in a interrupt context
2604 * also It will process only a given number of packets.
2606 * 0 on success and 1 if there are No Rx packets to be processed.
2609 static int s2io_poll(struct net_device
*dev
, int *budget
)
2611 struct s2io_nic
*nic
= dev
->priv
;
2612 int pkt_cnt
= 0, org_pkts_to_process
;
2613 struct mac_info
*mac_control
;
2614 struct config_param
*config
;
2615 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2618 atomic_inc(&nic
->isr_cnt
);
2619 mac_control
= &nic
->mac_control
;
2620 config
= &nic
->config
;
2622 nic
->pkts_to_process
= *budget
;
2623 if (nic
->pkts_to_process
> dev
->quota
)
2624 nic
->pkts_to_process
= dev
->quota
;
2625 org_pkts_to_process
= nic
->pkts_to_process
;
2627 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
2628 readl(&bar0
->rx_traffic_int
);
2630 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2631 rx_intr_handler(&mac_control
->rings
[i
]);
2632 pkt_cnt
= org_pkts_to_process
- nic
->pkts_to_process
;
2633 if (!nic
->pkts_to_process
) {
2634 /* Quota for the current iteration has been met */
2641 dev
->quota
-= pkt_cnt
;
2643 netif_rx_complete(dev
);
2645 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2646 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2647 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2648 DBG_PRINT(INFO_DBG
, " in Rx Poll!!\n");
2652 /* Re enable the Rx interrupts. */
2653 writeq(0x0, &bar0
->rx_traffic_mask
);
2654 readl(&bar0
->rx_traffic_mask
);
2655 atomic_dec(&nic
->isr_cnt
);
2659 dev
->quota
-= pkt_cnt
;
2662 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2663 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2664 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2665 DBG_PRINT(INFO_DBG
, " in Rx Poll!!\n");
2669 atomic_dec(&nic
->isr_cnt
);
2673 #ifdef CONFIG_NET_POLL_CONTROLLER
2675 * s2io_netpoll - netpoll event handler entry point
2676 * @dev : pointer to the device structure.
2678 * This function will be called by upper layer to check for events on the
2679 * interface in situations where interrupts are disabled. It is used for
2680 * specific in-kernel networking tasks, such as remote consoles and kernel
2681 * debugging over the network (example netdump in RedHat).
2683 static void s2io_netpoll(struct net_device
*dev
)
2685 struct s2io_nic
*nic
= dev
->priv
;
2686 struct mac_info
*mac_control
;
2687 struct config_param
*config
;
2688 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2689 u64 val64
= 0xFFFFFFFFFFFFFFFFULL
;
2692 disable_irq(dev
->irq
);
2694 atomic_inc(&nic
->isr_cnt
);
2695 mac_control
= &nic
->mac_control
;
2696 config
= &nic
->config
;
2698 writeq(val64
, &bar0
->rx_traffic_int
);
2699 writeq(val64
, &bar0
->tx_traffic_int
);
2701 /* we need to free up the transmitted skbufs or else netpoll will
2702 * run out of skbs and will fail and eventually netpoll application such
2703 * as netdump will fail.
2705 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
2706 tx_intr_handler(&mac_control
->fifos
[i
]);
2708 /* check for received packet and indicate up to network */
2709 for (i
= 0; i
< config
->rx_ring_num
; i
++)
2710 rx_intr_handler(&mac_control
->rings
[i
]);
2712 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2713 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2714 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2715 DBG_PRINT(INFO_DBG
, " in Rx Netpoll!!\n");
2719 atomic_dec(&nic
->isr_cnt
);
2720 enable_irq(dev
->irq
);
2726 * rx_intr_handler - Rx interrupt handler
2727 * @nic: device private variable.
2729 * If the interrupt is because of a received frame or if the
2730 * receive ring contains fresh as yet un-processed frames,this function is
2731 * called. It picks out the RxD at which place the last Rx processing had
2732 * stopped and sends the skb to the OSM's Rx handler and then increments
2737 static void rx_intr_handler(struct ring_info
*ring_data
)
2739 struct s2io_nic
*nic
= ring_data
->nic
;
2740 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2741 int get_block
, put_block
, put_offset
;
2742 struct rx_curr_get_info get_info
, put_info
;
2744 struct sk_buff
*skb
;
2748 spin_lock(&nic
->rx_lock
);
2749 if (atomic_read(&nic
->card_state
) == CARD_DOWN
) {
2750 DBG_PRINT(INTR_DBG
, "%s: %s going down for reset\n",
2751 __FUNCTION__
, dev
->name
);
2752 spin_unlock(&nic
->rx_lock
);
2756 get_info
= ring_data
->rx_curr_get_info
;
2757 get_block
= get_info
.block_index
;
2758 memcpy(&put_info
, &ring_data
->rx_curr_put_info
, sizeof(put_info
));
2759 put_block
= put_info
.block_index
;
2760 rxdp
= ring_data
->rx_blocks
[get_block
].rxds
[get_info
.offset
].virt_addr
;
2762 spin_lock(&nic
->put_lock
);
2763 put_offset
= ring_data
->put_pos
;
2764 spin_unlock(&nic
->put_lock
);
2766 put_offset
= ring_data
->put_pos
;
2768 while (RXD_IS_UP2DT(rxdp
)) {
2770 * If your are next to put index then it's
2771 * FIFO full condition
2773 if ((get_block
== put_block
) &&
2774 (get_info
.offset
+ 1) == put_info
.offset
) {
2775 DBG_PRINT(INTR_DBG
, "%s: Ring Full\n",dev
->name
);
2778 skb
= (struct sk_buff
*) ((unsigned long)rxdp
->Host_Control
);
2780 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
2782 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
2783 spin_unlock(&nic
->rx_lock
);
2786 if (nic
->rxd_mode
== RXD_MODE_1
) {
2787 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2788 ((struct RxD1
*)rxdp
)->Buffer0_ptr
,
2790 HEADER_ETHERNET_II_802_3_SIZE
+
2793 PCI_DMA_FROMDEVICE
);
2794 } else if (nic
->rxd_mode
== RXD_MODE_3B
) {
2795 pci_dma_sync_single_for_cpu(nic
->pdev
, (dma_addr_t
)
2796 ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2797 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2798 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2799 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2801 PCI_DMA_FROMDEVICE
);
2803 pci_dma_sync_single_for_cpu(nic
->pdev
, (dma_addr_t
)
2804 ((struct RxD3
*)rxdp
)->Buffer0_ptr
, BUF0_LEN
,
2805 PCI_DMA_FROMDEVICE
);
2806 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2807 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2809 PCI_DMA_FROMDEVICE
);
2810 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2811 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2812 dev
->mtu
, PCI_DMA_FROMDEVICE
);
2814 prefetch(skb
->data
);
2815 rx_osm_handler(ring_data
, rxdp
);
2817 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2818 rxdp
= ring_data
->rx_blocks
[get_block
].
2819 rxds
[get_info
.offset
].virt_addr
;
2820 if (get_info
.offset
== rxd_count
[nic
->rxd_mode
]) {
2821 get_info
.offset
= 0;
2822 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2824 if (get_block
== ring_data
->block_count
)
2826 ring_data
->rx_curr_get_info
.block_index
= get_block
;
2827 rxdp
= ring_data
->rx_blocks
[get_block
].block_virt_addr
;
2830 nic
->pkts_to_process
-= 1;
2831 if ((napi
) && (!nic
->pkts_to_process
))
2834 if ((indicate_max_pkts
) && (pkt_cnt
> indicate_max_pkts
))
2838 /* Clear all LRO sessions before exiting */
2839 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
2840 struct lro
*lro
= &nic
->lro0_n
[i
];
2842 update_L3L4_header(nic
, lro
);
2843 queue_rx_frame(lro
->parent
);
2844 clear_lro_session(lro
);
2849 spin_unlock(&nic
->rx_lock
);
2853 * tx_intr_handler - Transmit interrupt handler
2854 * @nic : device private variable
2856 * If an interrupt was raised to indicate DMA complete of the
2857 * Tx packet, this function is called. It identifies the last TxD
2858 * whose buffer was freed and frees all skbs whose data have already
2859 * DMA'ed into the NICs internal memory.
2864 static void tx_intr_handler(struct fifo_info
*fifo_data
)
2866 struct s2io_nic
*nic
= fifo_data
->nic
;
2867 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2868 struct tx_curr_get_info get_info
, put_info
;
2869 struct sk_buff
*skb
;
2873 get_info
= fifo_data
->tx_curr_get_info
;
2874 memcpy(&put_info
, &fifo_data
->tx_curr_put_info
, sizeof(put_info
));
2875 txdlp
= (struct TxD
*) fifo_data
->list_info
[get_info
.offset
].
2877 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
2878 (get_info
.offset
!= put_info
.offset
) &&
2879 (txdlp
->Host_Control
)) {
2880 /* Check for TxD errors */
2881 if (txdlp
->Control_1
& TXD_T_CODE
) {
2882 unsigned long long err
;
2883 err
= txdlp
->Control_1
& TXD_T_CODE
;
2885 nic
->mac_control
.stats_info
->sw_stat
.
2889 /* update t_code statistics */
2890 err_mask
= err
>> 48;
2893 nic
->mac_control
.stats_info
->sw_stat
.
2898 nic
->mac_control
.stats_info
->sw_stat
.
2899 tx_desc_abort_cnt
++;
2903 nic
->mac_control
.stats_info
->sw_stat
.
2904 tx_parity_err_cnt
++;
2908 nic
->mac_control
.stats_info
->sw_stat
.
2913 nic
->mac_control
.stats_info
->sw_stat
.
2914 tx_list_proc_err_cnt
++;
2919 skb
= s2io_txdl_getskb(fifo_data
, txdlp
, get_info
.offset
);
2921 DBG_PRINT(ERR_DBG
, "%s: Null skb ",
2923 DBG_PRINT(ERR_DBG
, "in Tx Free Intr\n");
2927 /* Updating the statistics block */
2928 nic
->stats
.tx_bytes
+= skb
->len
;
2929 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
2930 dev_kfree_skb_irq(skb
);
2933 if (get_info
.offset
== get_info
.fifo_len
+ 1)
2934 get_info
.offset
= 0;
2935 txdlp
= (struct TxD
*) fifo_data
->list_info
2936 [get_info
.offset
].list_virt_addr
;
2937 fifo_data
->tx_curr_get_info
.offset
=
2941 spin_lock(&nic
->tx_lock
);
2942 if (netif_queue_stopped(dev
))
2943 netif_wake_queue(dev
);
2944 spin_unlock(&nic
->tx_lock
);
2948 * s2io_mdio_write - Function to write in to MDIO registers
2949 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2950 * @addr : address value
2951 * @value : data value
2952 * @dev : pointer to net_device structure
2954 * This function is used to write values to the MDIO registers
2957 static void s2io_mdio_write(u32 mmd_type
, u64 addr
, u16 value
, struct net_device
*dev
)
2960 struct s2io_nic
*sp
= dev
->priv
;
2961 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2963 //address transaction
2964 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2965 | MDIO_MMD_DEV_ADDR(mmd_type
)
2966 | MDIO_MMS_PRT_ADDR(0x0);
2967 writeq(val64
, &bar0
->mdio_control
);
2968 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2969 writeq(val64
, &bar0
->mdio_control
);
2974 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2975 | MDIO_MMD_DEV_ADDR(mmd_type
)
2976 | MDIO_MMS_PRT_ADDR(0x0)
2977 | MDIO_MDIO_DATA(value
)
2978 | MDIO_OP(MDIO_OP_WRITE_TRANS
);
2979 writeq(val64
, &bar0
->mdio_control
);
2980 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2981 writeq(val64
, &bar0
->mdio_control
);
2985 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2986 | MDIO_MMD_DEV_ADDR(mmd_type
)
2987 | MDIO_MMS_PRT_ADDR(0x0)
2988 | MDIO_OP(MDIO_OP_READ_TRANS
);
2989 writeq(val64
, &bar0
->mdio_control
);
2990 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2991 writeq(val64
, &bar0
->mdio_control
);
2997 * s2io_mdio_read - Function to write in to MDIO registers
2998 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2999 * @addr : address value
3000 * @dev : pointer to net_device structure
3002 * This function is used to read values to the MDIO registers
3005 static u64
s2io_mdio_read(u32 mmd_type
, u64 addr
, struct net_device
*dev
)
3009 struct s2io_nic
*sp
= dev
->priv
;
3010 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3012 /* address transaction */
3013 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3014 | MDIO_MMD_DEV_ADDR(mmd_type
)
3015 | MDIO_MMS_PRT_ADDR(0x0);
3016 writeq(val64
, &bar0
->mdio_control
);
3017 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3018 writeq(val64
, &bar0
->mdio_control
);
3021 /* Data transaction */
3023 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3024 | MDIO_MMD_DEV_ADDR(mmd_type
)
3025 | MDIO_MMS_PRT_ADDR(0x0)
3026 | MDIO_OP(MDIO_OP_READ_TRANS
);
3027 writeq(val64
, &bar0
->mdio_control
);
3028 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3029 writeq(val64
, &bar0
->mdio_control
);
3032 /* Read the value from regs */
3033 rval64
= readq(&bar0
->mdio_control
);
3034 rval64
= rval64
& 0xFFFF0000;
3035 rval64
= rval64
>> 16;
3039 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3040 * @counter : couter value to be updated
3041 * @flag : flag to indicate the status
3042 * @type : counter type
3044 * This function is to check the status of the xpak counters value
3048 static void s2io_chk_xpak_counter(u64
*counter
, u64
* regs_stat
, u32 index
, u16 flag
, u16 type
)
3053 for(i
= 0; i
<index
; i
++)
3058 *counter
= *counter
+ 1;
3059 val64
= *regs_stat
& mask
;
3060 val64
= val64
>> (index
* 0x2);
3067 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3068 "service. Excessive temperatures may "
3069 "result in premature transceiver "
3073 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3074 "service Excessive bias currents may "
3075 "indicate imminent laser diode "
3079 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3080 "service Excessive laser output "
3081 "power may saturate far-end "
3085 DBG_PRINT(ERR_DBG
, "Incorrect XPAK Alarm "
3090 val64
= val64
<< (index
* 0x2);
3091 *regs_stat
= (*regs_stat
& (~mask
)) | (val64
);
3094 *regs_stat
= *regs_stat
& (~mask
);
3099 * s2io_updt_xpak_counter - Function to update the xpak counters
3100 * @dev : pointer to net_device struct
3102 * This function is to upate the status of the xpak counters value
3105 static void s2io_updt_xpak_counter(struct net_device
*dev
)
3113 struct s2io_nic
*sp
= dev
->priv
;
3114 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
3116 /* Check the communication with the MDIO slave */
3119 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3120 if((val64
== 0xFFFF) || (val64
== 0x0000))
3122 DBG_PRINT(ERR_DBG
, "ERR: MDIO slave access failed - "
3123 "Returned %llx\n", (unsigned long long)val64
);
3127 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3130 DBG_PRINT(ERR_DBG
, "Incorrect value at PMA address 0x0000 - ");
3131 DBG_PRINT(ERR_DBG
, "Returned: %llx- Expected: 0x2040\n",
3132 (unsigned long long)val64
);
3136 /* Loading the DOM register to MDIO register */
3138 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR
, addr
, val16
, dev
);
3139 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3141 /* Reading the Alarm flags */
3144 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3146 flag
= CHECKBIT(val64
, 0x7);
3148 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_transceiver_temp_high
,
3149 &stat_info
->xpak_stat
.xpak_regs_stat
,
3152 if(CHECKBIT(val64
, 0x6))
3153 stat_info
->xpak_stat
.alarm_transceiver_temp_low
++;
3155 flag
= CHECKBIT(val64
, 0x3);
3157 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_bias_current_high
,
3158 &stat_info
->xpak_stat
.xpak_regs_stat
,
3161 if(CHECKBIT(val64
, 0x2))
3162 stat_info
->xpak_stat
.alarm_laser_bias_current_low
++;
3164 flag
= CHECKBIT(val64
, 0x1);
3166 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_output_power_high
,
3167 &stat_info
->xpak_stat
.xpak_regs_stat
,
3170 if(CHECKBIT(val64
, 0x0))
3171 stat_info
->xpak_stat
.alarm_laser_output_power_low
++;
3173 /* Reading the Warning flags */
3176 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3178 if(CHECKBIT(val64
, 0x7))
3179 stat_info
->xpak_stat
.warn_transceiver_temp_high
++;
3181 if(CHECKBIT(val64
, 0x6))
3182 stat_info
->xpak_stat
.warn_transceiver_temp_low
++;
3184 if(CHECKBIT(val64
, 0x3))
3185 stat_info
->xpak_stat
.warn_laser_bias_current_high
++;
3187 if(CHECKBIT(val64
, 0x2))
3188 stat_info
->xpak_stat
.warn_laser_bias_current_low
++;
3190 if(CHECKBIT(val64
, 0x1))
3191 stat_info
->xpak_stat
.warn_laser_output_power_high
++;
3193 if(CHECKBIT(val64
, 0x0))
3194 stat_info
->xpak_stat
.warn_laser_output_power_low
++;
3198 * alarm_intr_handler - Alarm Interrrupt handler
3199 * @nic: device private variable
3200 * Description: If the interrupt was neither because of Rx packet or Tx
3201 * complete, this function is called. If the interrupt was to indicate
3202 * a loss of link, the OSM link status handler is invoked for any other
3203 * alarm interrupt the block that raised the interrupt is displayed
3204 * and a H/W reset is issued.
3209 static void alarm_intr_handler(struct s2io_nic
*nic
)
3211 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
3212 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3213 register u64 val64
= 0, err_reg
= 0;
3216 if (atomic_read(&nic
->card_state
) == CARD_DOWN
)
3218 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
= 0;
3219 /* Handling the XPAK counters update */
3220 if(nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
< 72000) {
3221 /* waiting for an hour */
3222 nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
++;
3224 s2io_updt_xpak_counter(dev
);
3225 /* reset the count to zero */
3226 nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
= 0;
3229 /* Handling link status change error Intr */
3230 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
3231 err_reg
= readq(&bar0
->mac_rmac_err_reg
);
3232 writeq(err_reg
, &bar0
->mac_rmac_err_reg
);
3233 if (err_reg
& RMAC_LINK_STATE_CHANGE_INT
) {
3234 schedule_work(&nic
->set_link_task
);
3238 /* Handling Ecc errors */
3239 val64
= readq(&bar0
->mc_err_reg
);
3240 writeq(val64
, &bar0
->mc_err_reg
);
3241 if (val64
& (MC_ERR_REG_ECC_ALL_SNG
| MC_ERR_REG_ECC_ALL_DBL
)) {
3242 if (val64
& MC_ERR_REG_ECC_ALL_DBL
) {
3243 nic
->mac_control
.stats_info
->sw_stat
.
3245 DBG_PRINT(INIT_DBG
, "%s: Device indicates ",
3247 DBG_PRINT(INIT_DBG
, "double ECC error!!\n");
3248 if (nic
->device_type
!= XFRAME_II_DEVICE
) {
3249 /* Reset XframeI only if critical error */
3250 if (val64
& (MC_ERR_REG_MIRI_ECC_DB_ERR_0
|
3251 MC_ERR_REG_MIRI_ECC_DB_ERR_1
)) {
3252 netif_stop_queue(dev
);
3253 schedule_work(&nic
->rst_timer_task
);
3254 nic
->mac_control
.stats_info
->sw_stat
.
3259 nic
->mac_control
.stats_info
->sw_stat
.
3264 /* In case of a serious error, the device will be Reset. */
3265 val64
= readq(&bar0
->serr_source
);
3266 if (val64
& SERR_SOURCE_ANY
) {
3267 nic
->mac_control
.stats_info
->sw_stat
.serious_err_cnt
++;
3268 DBG_PRINT(ERR_DBG
, "%s: Device indicates ", dev
->name
);
3269 DBG_PRINT(ERR_DBG
, "serious error %llx!!\n",
3270 (unsigned long long)val64
);
3271 netif_stop_queue(dev
);
3272 schedule_work(&nic
->rst_timer_task
);
3273 nic
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
3277 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3278 * Error occurs, the adapter will be recycled by disabling the
3279 * adapter enable bit and enabling it again after the device
3280 * becomes Quiescent.
3282 val64
= readq(&bar0
->pcc_err_reg
);
3283 writeq(val64
, &bar0
->pcc_err_reg
);
3284 if (val64
& PCC_FB_ECC_DB_ERR
) {
3285 u64 ac
= readq(&bar0
->adapter_control
);
3286 ac
&= ~(ADAPTER_CNTL_EN
);
3287 writeq(ac
, &bar0
->adapter_control
);
3288 ac
= readq(&bar0
->adapter_control
);
3289 schedule_work(&nic
->set_link_task
);
3291 /* Check for data parity error */
3292 val64
= readq(&bar0
->pic_int_status
);
3293 if (val64
& PIC_INT_GPIO
) {
3294 val64
= readq(&bar0
->gpio_int_reg
);
3295 if (val64
& GPIO_INT_REG_DP_ERR_INT
) {
3296 nic
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
3297 schedule_work(&nic
->rst_timer_task
);
3298 nic
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
3302 /* Check for ring full counter */
3303 if (nic
->device_type
& XFRAME_II_DEVICE
) {
3304 val64
= readq(&bar0
->ring_bump_counter1
);
3305 for (i
=0; i
<4; i
++) {
3306 cnt
= ( val64
& vBIT(0xFFFF,(i
*16),16));
3307 cnt
>>= 64 - ((i
+1)*16);
3308 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
3312 val64
= readq(&bar0
->ring_bump_counter2
);
3313 for (i
=0; i
<4; i
++) {
3314 cnt
= ( val64
& vBIT(0xFFFF,(i
*16),16));
3315 cnt
>>= 64 - ((i
+1)*16);
3316 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
3321 /* Other type of interrupts are not being handled now, TODO */
3325 * wait_for_cmd_complete - waits for a command to complete.
3326 * @sp : private member of the device structure, which is a pointer to the
3327 * s2io_nic structure.
3328 * Description: Function that waits for a command to Write into RMAC
3329 * ADDR DATA registers to be completed and returns either success or
3330 * error depending on whether the command was complete or not.
3332 * SUCCESS on success and FAILURE on failure.
3335 static int wait_for_cmd_complete(void __iomem
*addr
, u64 busy_bit
,
3338 int ret
= FAILURE
, cnt
= 0, delay
= 1;
3341 if ((bit_state
!= S2IO_BIT_RESET
) && (bit_state
!= S2IO_BIT_SET
))
3345 val64
= readq(addr
);
3346 if (bit_state
== S2IO_BIT_RESET
) {
3347 if (!(val64
& busy_bit
)) {
3352 if (!(val64
& busy_bit
)) {
3369 * check_pci_device_id - Checks if the device id is supported
3371 * Description: Function to check if the pci device id is supported by driver.
3372 * Return value: Actual device id if supported else PCI_ANY_ID
3374 static u16
check_pci_device_id(u16 id
)
3377 case PCI_DEVICE_ID_HERC_WIN
:
3378 case PCI_DEVICE_ID_HERC_UNI
:
3379 return XFRAME_II_DEVICE
;
3380 case PCI_DEVICE_ID_S2IO_UNI
:
3381 case PCI_DEVICE_ID_S2IO_WIN
:
3382 return XFRAME_I_DEVICE
;
3389 * s2io_reset - Resets the card.
3390 * @sp : private member of the device structure.
3391 * Description: Function to Reset the card. This function then also
3392 * restores the previously saved PCI configuration space registers as
3393 * the card reset also resets the configuration space.
3398 static void s2io_reset(struct s2io_nic
* sp
)
3400 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3405 unsigned long long up_cnt
, down_cnt
, up_time
, down_time
, reset_cnt
;
3406 unsigned long long mem_alloc_cnt
, mem_free_cnt
, watchdog_cnt
;
3408 DBG_PRINT(INIT_DBG
,"%s - Resetting XFrame card %s\n",
3409 __FUNCTION__
, sp
->dev
->name
);
3411 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3412 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, &(pci_cmd
));
3414 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3416 ret
= pci_set_power_state(sp
->pdev
, 3);
3418 ret
= pci_set_power_state(sp
->pdev
, 0);
3420 DBG_PRINT(ERR_DBG
,"%s PME based SW_Reset failed!\n",
3428 val64
= SW_RESET_ALL
;
3429 writeq(val64
, &bar0
->sw_reset
);
3431 if (strstr(sp
->product_name
, "CX4")) {
3435 for (i
= 0; i
< S2IO_MAX_PCI_CONFIG_SPACE_REINIT
; i
++) {
3437 /* Restore the PCI state saved during initialization. */
3438 pci_restore_state(sp
->pdev
);
3439 pci_read_config_word(sp
->pdev
, 0x2, &val16
);
3440 if (check_pci_device_id(val16
) != (u16
)PCI_ANY_ID
)
3445 if (check_pci_device_id(val16
) == (u16
)PCI_ANY_ID
) {
3446 DBG_PRINT(ERR_DBG
,"%s SW_Reset failed!\n", __FUNCTION__
);
3449 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, pci_cmd
);
3453 /* Set swapper to enable I/O register access */
3454 s2io_set_swapper(sp
);
3456 /* Restore the MSIX table entries from local variables */
3457 restore_xmsi_data(sp
);
3459 /* Clear certain PCI/PCI-X fields after reset */
3460 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3461 /* Clear "detected parity error" bit */
3462 pci_write_config_word(sp
->pdev
, PCI_STATUS
, 0x8000);
3464 /* Clearing PCIX Ecc status register */
3465 pci_write_config_dword(sp
->pdev
, 0x68, 0x7C);
3467 /* Clearing PCI_STATUS error reflected here */
3468 writeq(BIT(62), &bar0
->txpic_int_reg
);
3471 /* Reset device statistics maintained by OS */
3472 memset(&sp
->stats
, 0, sizeof (struct net_device_stats
));
3474 up_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
;
3475 down_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
;
3476 up_time
= sp
->mac_control
.stats_info
->sw_stat
.link_up_time
;
3477 down_time
= sp
->mac_control
.stats_info
->sw_stat
.link_down_time
;
3478 reset_cnt
= sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
;
3479 mem_alloc_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
;
3480 mem_free_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_freed
;
3481 watchdog_cnt
= sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
;
3482 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3483 memset(sp
->mac_control
.stats_info
, 0, sizeof(struct stat_block
));
3484 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3485 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
= up_cnt
;
3486 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
= down_cnt
;
3487 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
= up_time
;
3488 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
= down_time
;
3489 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
= reset_cnt
;
3490 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
= mem_alloc_cnt
;
3491 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
= mem_free_cnt
;
3492 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
= watchdog_cnt
;
3494 /* SXE-002: Configure link and activity LED to turn it off */
3495 subid
= sp
->pdev
->subsystem_device
;
3496 if (((subid
& 0xFF) >= 0x07) &&
3497 (sp
->device_type
== XFRAME_I_DEVICE
)) {
3498 val64
= readq(&bar0
->gpio_control
);
3499 val64
|= 0x0000800000000000ULL
;
3500 writeq(val64
, &bar0
->gpio_control
);
3501 val64
= 0x0411040400000000ULL
;
3502 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
3506 * Clear spurious ECC interrupts that would have occured on
3507 * XFRAME II cards after reset.
3509 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3510 val64
= readq(&bar0
->pcc_err_reg
);
3511 writeq(val64
, &bar0
->pcc_err_reg
);
3514 /* restore the previously assigned mac address */
3515 s2io_set_mac_addr(sp
->dev
, (u8
*)&sp
->def_mac_addr
[0].mac_addr
);
3517 sp
->device_enabled_once
= FALSE
;
3521 * s2io_set_swapper - to set the swapper controle on the card
3522 * @sp : private member of the device structure,
3523 * pointer to the s2io_nic structure.
3524 * Description: Function to set the swapper control on the card
3525 * correctly depending on the 'endianness' of the system.
3527 * SUCCESS on success and FAILURE on failure.
3530 static int s2io_set_swapper(struct s2io_nic
* sp
)
3532 struct net_device
*dev
= sp
->dev
;
3533 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3534 u64 val64
, valt
, valr
;
3537 * Set proper endian settings and verify the same by reading
3538 * the PIF Feed-back register.
3541 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3542 if (val64
!= 0x0123456789ABCDEFULL
) {
3544 u64 value
[] = { 0xC30000C3C30000C3ULL
, /* FE=1, SE=1 */
3545 0x8100008181000081ULL
, /* FE=1, SE=0 */
3546 0x4200004242000042ULL
, /* FE=0, SE=1 */
3547 0}; /* FE=0, SE=0 */
3550 writeq(value
[i
], &bar0
->swapper_ctrl
);
3551 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3552 if (val64
== 0x0123456789ABCDEFULL
)
3557 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3559 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3560 (unsigned long long) val64
);
3565 valr
= readq(&bar0
->swapper_ctrl
);
3568 valt
= 0x0123456789ABCDEFULL
;
3569 writeq(valt
, &bar0
->xmsi_address
);
3570 val64
= readq(&bar0
->xmsi_address
);
3574 u64 value
[] = { 0x00C3C30000C3C300ULL
, /* FE=1, SE=1 */
3575 0x0081810000818100ULL
, /* FE=1, SE=0 */
3576 0x0042420000424200ULL
, /* FE=0, SE=1 */
3577 0}; /* FE=0, SE=0 */
3580 writeq((value
[i
] | valr
), &bar0
->swapper_ctrl
);
3581 writeq(valt
, &bar0
->xmsi_address
);
3582 val64
= readq(&bar0
->xmsi_address
);
3588 unsigned long long x
= val64
;
3589 DBG_PRINT(ERR_DBG
, "Write failed, Xmsi_addr ");
3590 DBG_PRINT(ERR_DBG
, "reads:0x%llx\n", x
);
3594 val64
= readq(&bar0
->swapper_ctrl
);
3595 val64
&= 0xFFFF000000000000ULL
;
3599 * The device by default set to a big endian format, so a
3600 * big endian driver need not set anything.
3602 val64
|= (SWAPPER_CTRL_TXP_FE
|
3603 SWAPPER_CTRL_TXP_SE
|
3604 SWAPPER_CTRL_TXD_R_FE
|
3605 SWAPPER_CTRL_TXD_W_FE
|
3606 SWAPPER_CTRL_TXF_R_FE
|
3607 SWAPPER_CTRL_RXD_R_FE
|
3608 SWAPPER_CTRL_RXD_W_FE
|
3609 SWAPPER_CTRL_RXF_W_FE
|
3610 SWAPPER_CTRL_XMSI_FE
|
3611 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3612 if (sp
->intr_type
== INTA
)
3613 val64
|= SWAPPER_CTRL_XMSI_SE
;
3614 writeq(val64
, &bar0
->swapper_ctrl
);
3617 * Initially we enable all bits to make it accessible by the
3618 * driver, then we selectively enable only those bits that
3621 val64
|= (SWAPPER_CTRL_TXP_FE
|
3622 SWAPPER_CTRL_TXP_SE
|
3623 SWAPPER_CTRL_TXD_R_FE
|
3624 SWAPPER_CTRL_TXD_R_SE
|
3625 SWAPPER_CTRL_TXD_W_FE
|
3626 SWAPPER_CTRL_TXD_W_SE
|
3627 SWAPPER_CTRL_TXF_R_FE
|
3628 SWAPPER_CTRL_RXD_R_FE
|
3629 SWAPPER_CTRL_RXD_R_SE
|
3630 SWAPPER_CTRL_RXD_W_FE
|
3631 SWAPPER_CTRL_RXD_W_SE
|
3632 SWAPPER_CTRL_RXF_W_FE
|
3633 SWAPPER_CTRL_XMSI_FE
|
3634 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3635 if (sp
->intr_type
== INTA
)
3636 val64
|= SWAPPER_CTRL_XMSI_SE
;
3637 writeq(val64
, &bar0
->swapper_ctrl
);
3639 val64
= readq(&bar0
->swapper_ctrl
);
3642 * Verifying if endian settings are accurate by reading a
3643 * feedback register.
3645 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3646 if (val64
!= 0x0123456789ABCDEFULL
) {
3647 /* Endian settings are incorrect, calls for another dekko. */
3648 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3650 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3651 (unsigned long long) val64
);
3658 static int wait_for_msix_trans(struct s2io_nic
*nic
, int i
)
3660 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3662 int ret
= 0, cnt
= 0;
3665 val64
= readq(&bar0
->xmsi_access
);
3666 if (!(val64
& BIT(15)))
3672 DBG_PRINT(ERR_DBG
, "XMSI # %d Access failed\n", i
);
3679 static void restore_xmsi_data(struct s2io_nic
*nic
)
3681 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3685 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3686 writeq(nic
->msix_info
[i
].addr
, &bar0
->xmsi_address
);
3687 writeq(nic
->msix_info
[i
].data
, &bar0
->xmsi_data
);
3688 val64
= (BIT(7) | BIT(15) | vBIT(i
, 26, 6));
3689 writeq(val64
, &bar0
->xmsi_access
);
3690 if (wait_for_msix_trans(nic
, i
)) {
3691 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3697 static void store_xmsi_data(struct s2io_nic
*nic
)
3699 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3700 u64 val64
, addr
, data
;
3703 /* Store and display */
3704 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3705 val64
= (BIT(15) | vBIT(i
, 26, 6));
3706 writeq(val64
, &bar0
->xmsi_access
);
3707 if (wait_for_msix_trans(nic
, i
)) {
3708 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3711 addr
= readq(&bar0
->xmsi_address
);
3712 data
= readq(&bar0
->xmsi_data
);
3714 nic
->msix_info
[i
].addr
= addr
;
3715 nic
->msix_info
[i
].data
= data
;
3720 int s2io_enable_msi(struct s2io_nic
*nic
)
3722 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3723 u16 msi_ctrl
, msg_val
;
3724 struct config_param
*config
= &nic
->config
;
3725 struct net_device
*dev
= nic
->dev
;
3726 u64 val64
, tx_mat
, rx_mat
;
3729 val64
= readq(&bar0
->pic_control
);
3731 writeq(val64
, &bar0
->pic_control
);
3733 err
= pci_enable_msi(nic
->pdev
);
3735 DBG_PRINT(ERR_DBG
, "%s: enabling MSI failed\n",
3741 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3742 * for interrupt handling.
3744 pci_read_config_word(nic
->pdev
, 0x4c, &msg_val
);
3746 pci_write_config_word(nic
->pdev
, 0x4c, msg_val
);
3747 pci_read_config_word(nic
->pdev
, 0x4c, &msg_val
);
3749 pci_read_config_word(nic
->pdev
, 0x42, &msi_ctrl
);
3751 pci_write_config_word(nic
->pdev
, 0x42, msi_ctrl
);
3753 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3754 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3755 for (i
=0; i
<config
->tx_fifo_num
; i
++) {
3756 tx_mat
|= TX_MAT_SET(i
, 1);
3758 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3760 rx_mat
= readq(&bar0
->rx_mat
);
3761 for (i
=0; i
<config
->rx_ring_num
; i
++) {
3762 rx_mat
|= RX_MAT_SET(i
, 1);
3764 writeq(rx_mat
, &bar0
->rx_mat
);
3766 dev
->irq
= nic
->pdev
->irq
;
3770 static int s2io_enable_msi_x(struct s2io_nic
*nic
)
3772 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3774 u16 msi_control
; /* Temp variable */
3775 int ret
, i
, j
, msix_indx
= 1;
3777 nic
->entries
= kmalloc(MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
),
3779 if (nic
->entries
== NULL
) {
3780 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n", \
3782 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3785 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3786 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3787 memset(nic
->entries
, 0,MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3790 kmalloc(MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
),
3792 if (nic
->s2io_entries
== NULL
) {
3793 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n",
3795 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3796 kfree(nic
->entries
);
3797 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3798 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3801 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3802 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3803 memset(nic
->s2io_entries
, 0,
3804 MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3806 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3807 nic
->entries
[i
].entry
= i
;
3808 nic
->s2io_entries
[i
].entry
= i
;
3809 nic
->s2io_entries
[i
].arg
= NULL
;
3810 nic
->s2io_entries
[i
].in_use
= 0;
3813 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3814 for (i
=0; i
<nic
->config
.tx_fifo_num
; i
++, msix_indx
++) {
3815 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3816 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.fifos
[i
];
3817 nic
->s2io_entries
[msix_indx
].type
= MSIX_FIFO_TYPE
;
3818 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3820 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3822 if (!nic
->config
.bimodal
) {
3823 rx_mat
= readq(&bar0
->rx_mat
);
3824 for (j
=0; j
<nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3825 rx_mat
|= RX_MAT_SET(j
, msix_indx
);
3826 nic
->s2io_entries
[msix_indx
].arg
3827 = &nic
->mac_control
.rings
[j
];
3828 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3829 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3831 writeq(rx_mat
, &bar0
->rx_mat
);
3833 tx_mat
= readq(&bar0
->tx_mat0_n
[7]);
3834 for (j
=0; j
<nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3835 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3836 nic
->s2io_entries
[msix_indx
].arg
3837 = &nic
->mac_control
.rings
[j
];
3838 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3839 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3841 writeq(tx_mat
, &bar0
->tx_mat0_n
[7]);
3844 nic
->avail_msix_vectors
= 0;
3845 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, MAX_REQUESTED_MSI_X
);
3846 /* We fail init if error or we get less vectors than min required */
3847 if (ret
>= (nic
->config
.tx_fifo_num
+ nic
->config
.rx_ring_num
+ 1)) {
3848 nic
->avail_msix_vectors
= ret
;
3849 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, ret
);
3852 DBG_PRINT(ERR_DBG
, "%s: Enabling MSIX failed\n", nic
->dev
->name
);
3853 kfree(nic
->entries
);
3854 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3855 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3856 kfree(nic
->s2io_entries
);
3857 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3858 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3859 nic
->entries
= NULL
;
3860 nic
->s2io_entries
= NULL
;
3861 nic
->avail_msix_vectors
= 0;
3864 if (!nic
->avail_msix_vectors
)
3865 nic
->avail_msix_vectors
= MAX_REQUESTED_MSI_X
;
3868 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3869 * in the herc NIC. (Temp change, needs to be removed later)
3871 pci_read_config_word(nic
->pdev
, 0x42, &msi_control
);
3872 msi_control
|= 0x1; /* Enable MSI */
3873 pci_write_config_word(nic
->pdev
, 0x42, msi_control
);
3878 /* ********************************************************* *
3879 * Functions defined below concern the OS part of the driver *
3880 * ********************************************************* */
3883 * s2io_open - open entry point of the driver
3884 * @dev : pointer to the device structure.
3886 * This function is the open entry point of the driver. It mainly calls a
3887 * function to allocate Rx buffers and inserts them into the buffer
3888 * descriptors and then enables the Rx part of the NIC.
3890 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3894 static int s2io_open(struct net_device
*dev
)
3896 struct s2io_nic
*sp
= dev
->priv
;
3900 * Make sure you have link off by default every time
3901 * Nic is initialized
3903 netif_carrier_off(dev
);
3904 sp
->last_link_state
= 0;
3906 /* Initialize H/W and enable interrupts */
3907 err
= s2io_card_up(sp
);
3909 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
3911 goto hw_init_failed
;
3914 if (s2io_set_mac_addr(dev
, dev
->dev_addr
) == FAILURE
) {
3915 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
3918 goto hw_init_failed
;
3921 netif_start_queue(dev
);
3925 if (sp
->intr_type
== MSI_X
) {
3928 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
3929 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3931 if (sp
->s2io_entries
) {
3932 kfree(sp
->s2io_entries
);
3933 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
3934 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3941 * s2io_close -close entry point of the driver
3942 * @dev : device pointer.
3944 * This is the stop entry point of the driver. It needs to undo exactly
3945 * whatever was done by the open entry point,thus it's usually referred to
3946 * as the close function.Among other things this function mainly stops the
3947 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3949 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3953 static int s2io_close(struct net_device
*dev
)
3955 struct s2io_nic
*sp
= dev
->priv
;
3957 netif_stop_queue(dev
);
3958 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3961 sp
->device_close_flag
= TRUE
; /* Device is shut down. */
3966 * s2io_xmit - Tx entry point of te driver
3967 * @skb : the socket buffer containing the Tx data.
3968 * @dev : device pointer.
3970 * This function is the Tx entry point of the driver. S2IO NIC supports
3971 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3972 * NOTE: when device cant queue the pkt,just the trans_start variable will
3975 * 0 on success & 1 on failure.
3978 static int s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3980 struct s2io_nic
*sp
= dev
->priv
;
3981 u16 frg_cnt
, frg_len
, i
, queue
, queue_len
, put_off
, get_off
;
3984 struct TxFIFO_element __iomem
*tx_fifo
;
3985 unsigned long flags
;
3987 int vlan_priority
= 0;
3988 struct mac_info
*mac_control
;
3989 struct config_param
*config
;
3992 mac_control
= &sp
->mac_control
;
3993 config
= &sp
->config
;
3995 DBG_PRINT(TX_DBG
, "%s: In Neterion Tx routine\n", dev
->name
);
3997 if (unlikely(skb
->len
<= 0)) {
3998 DBG_PRINT(TX_DBG
, "%s:Buffer has no data..\n", dev
->name
);
3999 dev_kfree_skb_any(skb
);
4003 spin_lock_irqsave(&sp
->tx_lock
, flags
);
4004 if (atomic_read(&sp
->card_state
) == CARD_DOWN
) {
4005 DBG_PRINT(TX_DBG
, "%s: Card going down for reset\n",
4007 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
4013 /* Get Fifo number to Transmit based on vlan priority */
4014 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
4015 vlan_tag
= vlan_tx_tag_get(skb
);
4016 vlan_priority
= vlan_tag
>> 13;
4017 queue
= config
->fifo_mapping
[vlan_priority
];
4020 put_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_put_info
.offset
;
4021 get_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_get_info
.offset
;
4022 txdp
= (struct TxD
*) mac_control
->fifos
[queue
].list_info
[put_off
].
4025 queue_len
= mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1;
4026 /* Avoid "put" pointer going beyond "get" pointer */
4027 if (txdp
->Host_Control
||
4028 ((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4029 DBG_PRINT(TX_DBG
, "Error in xmit, No free TXDs.\n");
4030 netif_stop_queue(dev
);
4032 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
4036 offload_type
= s2io_offload_type(skb
);
4037 if (offload_type
& (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
4038 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
4039 txdp
->Control_1
|= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb
));
4041 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4043 (TXD_TX_CKO_IPV4_EN
| TXD_TX_CKO_TCP_EN
|
4046 txdp
->Control_1
|= TXD_GATHER_CODE_FIRST
;
4047 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
4048 txdp
->Control_2
|= config
->tx_intr_type
;
4050 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
4051 txdp
->Control_2
|= TXD_VLAN_ENABLE
;
4052 txdp
->Control_2
|= TXD_VLAN_TAG(vlan_tag
);
4055 frg_len
= skb
->len
- skb
->data_len
;
4056 if (offload_type
== SKB_GSO_UDP
) {
4059 ufo_size
= s2io_udp_mss(skb
);
4061 txdp
->Control_1
|= TXD_UFO_EN
;
4062 txdp
->Control_1
|= TXD_UFO_MSS(ufo_size
);
4063 txdp
->Control_1
|= TXD_BUFFER0_SIZE(8);
4065 sp
->ufo_in_band_v
[put_off
] =
4066 (u64
)skb_shinfo(skb
)->ip6_frag_id
;
4068 sp
->ufo_in_band_v
[put_off
] =
4069 (u64
)skb_shinfo(skb
)->ip6_frag_id
<< 32;
4071 txdp
->Host_Control
= (unsigned long)sp
->ufo_in_band_v
;
4072 txdp
->Buffer_Pointer
= pci_map_single(sp
->pdev
,
4074 sizeof(u64
), PCI_DMA_TODEVICE
);
4078 txdp
->Buffer_Pointer
= pci_map_single
4079 (sp
->pdev
, skb
->data
, frg_len
, PCI_DMA_TODEVICE
);
4080 txdp
->Host_Control
= (unsigned long) skb
;
4081 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frg_len
);
4082 if (offload_type
== SKB_GSO_UDP
)
4083 txdp
->Control_1
|= TXD_UFO_EN
;
4085 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
4086 /* For fragmented SKB. */
4087 for (i
= 0; i
< frg_cnt
; i
++) {
4088 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
4089 /* A '0' length fragment will be ignored */
4093 txdp
->Buffer_Pointer
= (u64
) pci_map_page
4094 (sp
->pdev
, frag
->page
, frag
->page_offset
,
4095 frag
->size
, PCI_DMA_TODEVICE
);
4096 txdp
->Control_1
= TXD_BUFFER0_SIZE(frag
->size
);
4097 if (offload_type
== SKB_GSO_UDP
)
4098 txdp
->Control_1
|= TXD_UFO_EN
;
4100 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
4102 if (offload_type
== SKB_GSO_UDP
)
4103 frg_cnt
++; /* as Txd0 was used for inband header */
4105 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
4106 val64
= mac_control
->fifos
[queue
].list_info
[put_off
].list_phy_addr
;
4107 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
4109 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
4112 val64
|= TX_FIFO_SPECIAL_FUNC
;
4114 writeq(val64
, &tx_fifo
->List_Control
);
4119 if (put_off
== mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1)
4121 mac_control
->fifos
[queue
].tx_curr_put_info
.offset
= put_off
;
4123 /* Avoid "put" pointer going beyond "get" pointer */
4124 if (((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4125 sp
->mac_control
.stats_info
->sw_stat
.fifo_full_cnt
++;
4127 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4129 netif_stop_queue(dev
);
4131 mac_control
->stats_info
->sw_stat
.mem_allocated
+= skb
->truesize
;
4132 dev
->trans_start
= jiffies
;
4133 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
4139 s2io_alarm_handle(unsigned long data
)
4141 struct s2io_nic
*sp
= (struct s2io_nic
*)data
;
4143 alarm_intr_handler(sp
);
4144 mod_timer(&sp
->alarm_timer
, jiffies
+ HZ
/ 2);
4147 static int s2io_chk_rx_buffers(struct s2io_nic
*sp
, int rng_n
)
4149 int rxb_size
, level
;
4152 rxb_size
= atomic_read(&sp
->rx_bufs_left
[rng_n
]);
4153 level
= rx_buffer_level(sp
, rxb_size
, rng_n
);
4155 if ((level
== PANIC
) && (!TASKLET_IN_USE
)) {
4157 DBG_PRINT(INTR_DBG
, "%s: Rx BD hit ", __FUNCTION__
);
4158 DBG_PRINT(INTR_DBG
, "PANIC levels\n");
4159 if ((ret
= fill_rx_buffers(sp
, rng_n
)) == -ENOMEM
) {
4160 DBG_PRINT(INFO_DBG
, "Out of memory in %s",
4162 clear_bit(0, (&sp
->tasklet_status
));
4165 clear_bit(0, (&sp
->tasklet_status
));
4166 } else if (level
== LOW
)
4167 tasklet_schedule(&sp
->task
);
4169 } else if (fill_rx_buffers(sp
, rng_n
) == -ENOMEM
) {
4170 DBG_PRINT(INFO_DBG
, "%s:Out of memory", sp
->dev
->name
);
4171 DBG_PRINT(INFO_DBG
, " in Rx Intr!!\n");
4176 static irqreturn_t
s2io_msi_handle(int irq
, void *dev_id
)
4178 struct net_device
*dev
= (struct net_device
*) dev_id
;
4179 struct s2io_nic
*sp
= dev
->priv
;
4181 struct mac_info
*mac_control
;
4182 struct config_param
*config
;
4184 atomic_inc(&sp
->isr_cnt
);
4185 mac_control
= &sp
->mac_control
;
4186 config
= &sp
->config
;
4187 DBG_PRINT(INTR_DBG
, "%s: MSI handler\n", __FUNCTION__
);
4189 /* If Intr is because of Rx Traffic */
4190 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4191 rx_intr_handler(&mac_control
->rings
[i
]);
4193 /* If Intr is because of Tx Traffic */
4194 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4195 tx_intr_handler(&mac_control
->fifos
[i
]);
4198 * If the Rx buffer count is below the panic threshold then
4199 * reallocate the buffers from the interrupt handler itself,
4200 * else schedule a tasklet to reallocate the buffers.
4202 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4203 s2io_chk_rx_buffers(sp
, i
);
4205 atomic_dec(&sp
->isr_cnt
);
4209 static irqreturn_t
s2io_msix_ring_handle(int irq
, void *dev_id
)
4211 struct ring_info
*ring
= (struct ring_info
*)dev_id
;
4212 struct s2io_nic
*sp
= ring
->nic
;
4214 atomic_inc(&sp
->isr_cnt
);
4216 rx_intr_handler(ring
);
4217 s2io_chk_rx_buffers(sp
, ring
->ring_no
);
4219 atomic_dec(&sp
->isr_cnt
);
4223 static irqreturn_t
s2io_msix_fifo_handle(int irq
, void *dev_id
)
4225 struct fifo_info
*fifo
= (struct fifo_info
*)dev_id
;
4226 struct s2io_nic
*sp
= fifo
->nic
;
4228 atomic_inc(&sp
->isr_cnt
);
4229 tx_intr_handler(fifo
);
4230 atomic_dec(&sp
->isr_cnt
);
4233 static void s2io_txpic_intr_handle(struct s2io_nic
*sp
)
4235 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4238 val64
= readq(&bar0
->pic_int_status
);
4239 if (val64
& PIC_INT_GPIO
) {
4240 val64
= readq(&bar0
->gpio_int_reg
);
4241 if ((val64
& GPIO_INT_REG_LINK_DOWN
) &&
4242 (val64
& GPIO_INT_REG_LINK_UP
)) {
4244 * This is unstable state so clear both up/down
4245 * interrupt and adapter to re-evaluate the link state.
4247 val64
|= GPIO_INT_REG_LINK_DOWN
;
4248 val64
|= GPIO_INT_REG_LINK_UP
;
4249 writeq(val64
, &bar0
->gpio_int_reg
);
4250 val64
= readq(&bar0
->gpio_int_mask
);
4251 val64
&= ~(GPIO_INT_MASK_LINK_UP
|
4252 GPIO_INT_MASK_LINK_DOWN
);
4253 writeq(val64
, &bar0
->gpio_int_mask
);
4255 else if (val64
& GPIO_INT_REG_LINK_UP
) {
4256 val64
= readq(&bar0
->adapter_status
);
4257 /* Enable Adapter */
4258 val64
= readq(&bar0
->adapter_control
);
4259 val64
|= ADAPTER_CNTL_EN
;
4260 writeq(val64
, &bar0
->adapter_control
);
4261 val64
|= ADAPTER_LED_ON
;
4262 writeq(val64
, &bar0
->adapter_control
);
4263 if (!sp
->device_enabled_once
)
4264 sp
->device_enabled_once
= 1;
4266 s2io_link(sp
, LINK_UP
);
4268 * unmask link down interrupt and mask link-up
4271 val64
= readq(&bar0
->gpio_int_mask
);
4272 val64
&= ~GPIO_INT_MASK_LINK_DOWN
;
4273 val64
|= GPIO_INT_MASK_LINK_UP
;
4274 writeq(val64
, &bar0
->gpio_int_mask
);
4276 }else if (val64
& GPIO_INT_REG_LINK_DOWN
) {
4277 val64
= readq(&bar0
->adapter_status
);
4278 s2io_link(sp
, LINK_DOWN
);
4279 /* Link is down so unmaks link up interrupt */
4280 val64
= readq(&bar0
->gpio_int_mask
);
4281 val64
&= ~GPIO_INT_MASK_LINK_UP
;
4282 val64
|= GPIO_INT_MASK_LINK_DOWN
;
4283 writeq(val64
, &bar0
->gpio_int_mask
);
4286 val64
= readq(&bar0
->adapter_control
);
4287 val64
= val64
&(~ADAPTER_LED_ON
);
4288 writeq(val64
, &bar0
->adapter_control
);
4291 val64
= readq(&bar0
->gpio_int_mask
);
4295 * s2io_isr - ISR handler of the device .
4296 * @irq: the irq of the device.
4297 * @dev_id: a void pointer to the dev structure of the NIC.
4298 * Description: This function is the ISR handler of the device. It
4299 * identifies the reason for the interrupt and calls the relevant
4300 * service routines. As a contongency measure, this ISR allocates the
4301 * recv buffers, if their numbers are below the panic value which is
4302 * presently set to 25% of the original number of rcv buffers allocated.
4304 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4305 * IRQ_NONE: will be returned if interrupt is not from our device
4307 static irqreturn_t
s2io_isr(int irq
, void *dev_id
)
4309 struct net_device
*dev
= (struct net_device
*) dev_id
;
4310 struct s2io_nic
*sp
= dev
->priv
;
4311 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4314 struct mac_info
*mac_control
;
4315 struct config_param
*config
;
4317 atomic_inc(&sp
->isr_cnt
);
4318 mac_control
= &sp
->mac_control
;
4319 config
= &sp
->config
;
4322 * Identify the cause for interrupt and call the appropriate
4323 * interrupt handler. Causes for the interrupt could be;
4327 * 4. Error in any functional blocks of the NIC.
4329 reason
= readq(&bar0
->general_int_status
);
4332 /* The interrupt was not raised by us. */
4333 atomic_dec(&sp
->isr_cnt
);
4336 else if (unlikely(reason
== S2IO_MINUS_ONE
) ) {
4337 /* Disable device and get out */
4338 atomic_dec(&sp
->isr_cnt
);
4343 if (reason
& GEN_INTR_RXTRAFFIC
) {
4344 if ( likely ( netif_rx_schedule_prep(dev
)) ) {
4345 __netif_rx_schedule(dev
);
4346 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_mask
);
4349 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4353 * Rx handler is called by default, without checking for the
4354 * cause of interrupt.
4355 * rx_traffic_int reg is an R1 register, writing all 1's
4356 * will ensure that the actual interrupt causing bit get's
4357 * cleared and hence a read can be avoided.
4359 if (reason
& GEN_INTR_RXTRAFFIC
)
4360 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4362 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
4363 rx_intr_handler(&mac_control
->rings
[i
]);
4368 * tx_traffic_int reg is an R1 register, writing all 1's
4369 * will ensure that the actual interrupt causing bit get's
4370 * cleared and hence a read can be avoided.
4372 if (reason
& GEN_INTR_TXTRAFFIC
)
4373 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4375 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4376 tx_intr_handler(&mac_control
->fifos
[i
]);
4378 if (reason
& GEN_INTR_TXPIC
)
4379 s2io_txpic_intr_handle(sp
);
4381 * If the Rx buffer count is below the panic threshold then
4382 * reallocate the buffers from the interrupt handler itself,
4383 * else schedule a tasklet to reallocate the buffers.
4386 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4387 s2io_chk_rx_buffers(sp
, i
);
4390 writeq(0, &bar0
->general_int_mask
);
4391 readl(&bar0
->general_int_status
);
4393 atomic_dec(&sp
->isr_cnt
);
4400 static void s2io_updt_stats(struct s2io_nic
*sp
)
4402 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4406 if (atomic_read(&sp
->card_state
) == CARD_UP
) {
4407 /* Apprx 30us on a 133 MHz bus */
4408 val64
= SET_UPDT_CLICKS(10) |
4409 STAT_CFG_ONE_SHOT_EN
| STAT_CFG_STAT_EN
;
4410 writeq(val64
, &bar0
->stat_cfg
);
4413 val64
= readq(&bar0
->stat_cfg
);
4414 if (!(val64
& BIT(0)))
4418 break; /* Updt failed */
4424 * s2io_get_stats - Updates the device statistics structure.
4425 * @dev : pointer to the device structure.
4427 * This function updates the device statistics structure in the s2io_nic
4428 * structure and returns a pointer to the same.
4430 * pointer to the updated net_device_stats structure.
4433 static struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
4435 struct s2io_nic
*sp
= dev
->priv
;
4436 struct mac_info
*mac_control
;
4437 struct config_param
*config
;
4440 mac_control
= &sp
->mac_control
;
4441 config
= &sp
->config
;
4443 /* Configure Stats for immediate updt */
4444 s2io_updt_stats(sp
);
4446 sp
->stats
.tx_packets
=
4447 le32_to_cpu(mac_control
->stats_info
->tmac_frms
);
4448 sp
->stats
.tx_errors
=
4449 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
);
4450 sp
->stats
.rx_errors
=
4451 le64_to_cpu(mac_control
->stats_info
->rmac_drop_frms
);
4452 sp
->stats
.multicast
=
4453 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
);
4454 sp
->stats
.rx_length_errors
=
4455 le64_to_cpu(mac_control
->stats_info
->rmac_long_frms
);
4457 return (&sp
->stats
);
4461 * s2io_set_multicast - entry point for multicast address enable/disable.
4462 * @dev : pointer to the device structure
4464 * This function is a driver entry point which gets called by the kernel
4465 * whenever multicast addresses must be enabled/disabled. This also gets
4466 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4467 * determine, if multicast address must be enabled or if promiscuous mode
4468 * is to be disabled etc.
4473 static void s2io_set_multicast(struct net_device
*dev
)
4476 struct dev_mc_list
*mclist
;
4477 struct s2io_nic
*sp
= dev
->priv
;
4478 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4479 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
4481 u64 dis_addr
= 0xffffffffffffULL
, mac_addr
= 0;
4484 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
4485 /* Enable all Multicast addresses */
4486 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
4487 &bar0
->rmac_addr_data0_mem
);
4488 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
4489 &bar0
->rmac_addr_data1_mem
);
4490 val64
= RMAC_ADDR_CMD_MEM_WE
|
4491 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4492 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET
);
4493 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4494 /* Wait till command completes */
4495 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4496 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4500 sp
->all_multi_pos
= MAC_MC_ALL_MC_ADDR_OFFSET
;
4501 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
4502 /* Disable all Multicast addresses */
4503 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4504 &bar0
->rmac_addr_data0_mem
);
4505 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4506 &bar0
->rmac_addr_data1_mem
);
4507 val64
= RMAC_ADDR_CMD_MEM_WE
|
4508 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4509 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
4510 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4511 /* Wait till command completes */
4512 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4513 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4517 sp
->all_multi_pos
= 0;
4520 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
4521 /* Put the NIC into promiscuous mode */
4522 add
= &bar0
->mac_cfg
;
4523 val64
= readq(&bar0
->mac_cfg
);
4524 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
4526 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4527 writel((u32
) val64
, add
);
4528 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4529 writel((u32
) (val64
>> 32), (add
+ 4));
4531 if (vlan_tag_strip
!= 1) {
4532 val64
= readq(&bar0
->rx_pa_cfg
);
4533 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
4534 writeq(val64
, &bar0
->rx_pa_cfg
);
4535 vlan_strip_flag
= 0;
4538 val64
= readq(&bar0
->mac_cfg
);
4539 sp
->promisc_flg
= 1;
4540 DBG_PRINT(INFO_DBG
, "%s: entered promiscuous mode\n",
4542 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
4543 /* Remove the NIC from promiscuous mode */
4544 add
= &bar0
->mac_cfg
;
4545 val64
= readq(&bar0
->mac_cfg
);
4546 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
4548 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4549 writel((u32
) val64
, add
);
4550 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4551 writel((u32
) (val64
>> 32), (add
+ 4));
4553 if (vlan_tag_strip
!= 0) {
4554 val64
= readq(&bar0
->rx_pa_cfg
);
4555 val64
|= RX_PA_CFG_STRIP_VLAN_TAG
;
4556 writeq(val64
, &bar0
->rx_pa_cfg
);
4557 vlan_strip_flag
= 1;
4560 val64
= readq(&bar0
->mac_cfg
);
4561 sp
->promisc_flg
= 0;
4562 DBG_PRINT(INFO_DBG
, "%s: left promiscuous mode\n",
4566 /* Update individual M_CAST address list */
4567 if ((!sp
->m_cast_flg
) && dev
->mc_count
) {
4569 (MAX_ADDRS_SUPPORTED
- MAC_MC_ADDR_START_OFFSET
- 1)) {
4570 DBG_PRINT(ERR_DBG
, "%s: No more Rx filters ",
4572 DBG_PRINT(ERR_DBG
, "can be added, please enable ");
4573 DBG_PRINT(ERR_DBG
, "ALL_MULTI instead\n");
4577 prev_cnt
= sp
->mc_addr_count
;
4578 sp
->mc_addr_count
= dev
->mc_count
;
4580 /* Clear out the previous list of Mc in the H/W. */
4581 for (i
= 0; i
< prev_cnt
; i
++) {
4582 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4583 &bar0
->rmac_addr_data0_mem
);
4584 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4585 &bar0
->rmac_addr_data1_mem
);
4586 val64
= RMAC_ADDR_CMD_MEM_WE
|
4587 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4588 RMAC_ADDR_CMD_MEM_OFFSET
4589 (MAC_MC_ADDR_START_OFFSET
+ i
);
4590 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4592 /* Wait for command completes */
4593 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4594 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4596 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4598 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4603 /* Create the new Rx filter list and update the same in H/W. */
4604 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
4605 i
++, mclist
= mclist
->next
) {
4606 memcpy(sp
->usr_addrs
[i
].addr
, mclist
->dmi_addr
,
4609 for (j
= 0; j
< ETH_ALEN
; j
++) {
4610 mac_addr
|= mclist
->dmi_addr
[j
];
4614 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4615 &bar0
->rmac_addr_data0_mem
);
4616 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4617 &bar0
->rmac_addr_data1_mem
);
4618 val64
= RMAC_ADDR_CMD_MEM_WE
|
4619 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4620 RMAC_ADDR_CMD_MEM_OFFSET
4621 (i
+ MAC_MC_ADDR_START_OFFSET
);
4622 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4624 /* Wait for command completes */
4625 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4626 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4628 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4630 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4638 * s2io_set_mac_addr - Programs the Xframe mac address
4639 * @dev : pointer to the device structure.
4640 * @addr: a uchar pointer to the new mac address which is to be set.
4641 * Description : This procedure will program the Xframe to receive
4642 * frames with new Mac Address
4643 * Return value: SUCCESS on success and an appropriate (-)ve integer
4644 * as defined in errno.h file on failure.
4647 static int s2io_set_mac_addr(struct net_device
*dev
, u8
* addr
)
4649 struct s2io_nic
*sp
= dev
->priv
;
4650 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4651 register u64 val64
, mac_addr
= 0;
4653 u64 old_mac_addr
= 0;
4656 * Set the new MAC address as the new unicast filter and reflect this
4657 * change on the device address registered with the OS. It will be
4660 for (i
= 0; i
< ETH_ALEN
; i
++) {
4662 mac_addr
|= addr
[i
];
4664 old_mac_addr
|= sp
->def_mac_addr
[0].mac_addr
[i
];
4670 /* Update the internal structure with this new mac address */
4671 if(mac_addr
!= old_mac_addr
) {
4672 memset(sp
->def_mac_addr
[0].mac_addr
, 0, sizeof(ETH_ALEN
));
4673 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_addr
);
4674 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_addr
>> 8);
4675 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_addr
>> 16);
4676 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_addr
>> 24);
4677 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_addr
>> 32);
4678 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_addr
>> 40);
4681 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4682 &bar0
->rmac_addr_data0_mem
);
4685 RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4686 RMAC_ADDR_CMD_MEM_OFFSET(0);
4687 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4688 /* Wait till command completes */
4689 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4690 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
, S2IO_BIT_RESET
)) {
4691 DBG_PRINT(ERR_DBG
, "%s: set_mac_addr failed\n", dev
->name
);
4699 * s2io_ethtool_sset - Sets different link parameters.
4700 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4701 * @info: pointer to the structure with parameters given by ethtool to set
4704 * The function sets different link parameters provided by the user onto
4710 static int s2io_ethtool_sset(struct net_device
*dev
,
4711 struct ethtool_cmd
*info
)
4713 struct s2io_nic
*sp
= dev
->priv
;
4714 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
4715 (info
->speed
!= SPEED_10000
) || (info
->duplex
!= DUPLEX_FULL
))
4718 s2io_close(sp
->dev
);
4726 * s2io_ethtol_gset - Return link specific information.
4727 * @sp : private member of the device structure, pointer to the
4728 * s2io_nic structure.
4729 * @info : pointer to the structure with parameters given by ethtool
4730 * to return link information.
4732 * Returns link specific information like speed, duplex etc.. to ethtool.
4734 * return 0 on success.
4737 static int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
4739 struct s2io_nic
*sp
= dev
->priv
;
4740 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4741 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4742 info
->port
= PORT_FIBRE
;
4743 /* info->transceiver?? TODO */
4745 if (netif_carrier_ok(sp
->dev
)) {
4746 info
->speed
= 10000;
4747 info
->duplex
= DUPLEX_FULL
;
4753 info
->autoneg
= AUTONEG_DISABLE
;
4758 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4759 * @sp : private member of the device structure, which is a pointer to the
4760 * s2io_nic structure.
4761 * @info : pointer to the structure with parameters given by ethtool to
4762 * return driver information.
4764 * Returns driver specefic information like name, version etc.. to ethtool.
4769 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
4770 struct ethtool_drvinfo
*info
)
4772 struct s2io_nic
*sp
= dev
->priv
;
4774 strncpy(info
->driver
, s2io_driver_name
, sizeof(info
->driver
));
4775 strncpy(info
->version
, s2io_driver_version
, sizeof(info
->version
));
4776 strncpy(info
->fw_version
, "", sizeof(info
->fw_version
));
4777 strncpy(info
->bus_info
, pci_name(sp
->pdev
), sizeof(info
->bus_info
));
4778 info
->regdump_len
= XENA_REG_SPACE
;
4779 info
->eedump_len
= XENA_EEPROM_SPACE
;
4780 info
->testinfo_len
= S2IO_TEST_LEN
;
4782 if (sp
->device_type
== XFRAME_I_DEVICE
)
4783 info
->n_stats
= XFRAME_I_STAT_LEN
;
4785 info
->n_stats
= XFRAME_II_STAT_LEN
;
4789 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4790 * @sp: private member of the device structure, which is a pointer to the
4791 * s2io_nic structure.
4792 * @regs : pointer to the structure with parameters given by ethtool for
4793 * dumping the registers.
4794 * @reg_space: The input argumnet into which all the registers are dumped.
4796 * Dumps the entire register space of xFrame NIC into the user given
4802 static void s2io_ethtool_gregs(struct net_device
*dev
,
4803 struct ethtool_regs
*regs
, void *space
)
4807 u8
*reg_space
= (u8
*) space
;
4808 struct s2io_nic
*sp
= dev
->priv
;
4810 regs
->len
= XENA_REG_SPACE
;
4811 regs
->version
= sp
->pdev
->subsystem_device
;
4813 for (i
= 0; i
< regs
->len
; i
+= 8) {
4814 reg
= readq(sp
->bar0
+ i
);
4815 memcpy((reg_space
+ i
), ®
, 8);
4820 * s2io_phy_id - timer function that alternates adapter LED.
4821 * @data : address of the private member of the device structure, which
4822 * is a pointer to the s2io_nic structure, provided as an u32.
4823 * Description: This is actually the timer function that alternates the
4824 * adapter LED bit of the adapter control bit to set/reset every time on
4825 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4826 * once every second.
4828 static void s2io_phy_id(unsigned long data
)
4830 struct s2io_nic
*sp
= (struct s2io_nic
*) data
;
4831 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4835 subid
= sp
->pdev
->subsystem_device
;
4836 if ((sp
->device_type
== XFRAME_II_DEVICE
) ||
4837 ((subid
& 0xFF) >= 0x07)) {
4838 val64
= readq(&bar0
->gpio_control
);
4839 val64
^= GPIO_CTRL_GPIO_0
;
4840 writeq(val64
, &bar0
->gpio_control
);
4842 val64
= readq(&bar0
->adapter_control
);
4843 val64
^= ADAPTER_LED_ON
;
4844 writeq(val64
, &bar0
->adapter_control
);
4847 mod_timer(&sp
->id_timer
, jiffies
+ HZ
/ 2);
4851 * s2io_ethtool_idnic - To physically identify the nic on the system.
4852 * @sp : private member of the device structure, which is a pointer to the
4853 * s2io_nic structure.
4854 * @id : pointer to the structure with identification parameters given by
4856 * Description: Used to physically identify the NIC on the system.
4857 * The Link LED will blink for a time specified by the user for
4859 * NOTE: The Link has to be Up to be able to blink the LED. Hence
4860 * identification is possible only if it's link is up.
4862 * int , returns 0 on success
4865 static int s2io_ethtool_idnic(struct net_device
*dev
, u32 data
)
4867 u64 val64
= 0, last_gpio_ctrl_val
;
4868 struct s2io_nic
*sp
= dev
->priv
;
4869 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4872 subid
= sp
->pdev
->subsystem_device
;
4873 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
4874 if ((sp
->device_type
== XFRAME_I_DEVICE
) &&
4875 ((subid
& 0xFF) < 0x07)) {
4876 val64
= readq(&bar0
->adapter_control
);
4877 if (!(val64
& ADAPTER_CNTL_EN
)) {
4879 "Adapter Link down, cannot blink LED\n");
4883 if (sp
->id_timer
.function
== NULL
) {
4884 init_timer(&sp
->id_timer
);
4885 sp
->id_timer
.function
= s2io_phy_id
;
4886 sp
->id_timer
.data
= (unsigned long) sp
;
4888 mod_timer(&sp
->id_timer
, jiffies
);
4890 msleep_interruptible(data
* HZ
);
4892 msleep_interruptible(MAX_FLICKER_TIME
);
4893 del_timer_sync(&sp
->id_timer
);
4895 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp
->device_type
, subid
)) {
4896 writeq(last_gpio_ctrl_val
, &bar0
->gpio_control
);
4897 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
4903 static void s2io_ethtool_gringparam(struct net_device
*dev
,
4904 struct ethtool_ringparam
*ering
)
4906 struct s2io_nic
*sp
= dev
->priv
;
4907 int i
,tx_desc_count
=0,rx_desc_count
=0;
4909 if (sp
->rxd_mode
== RXD_MODE_1
)
4910 ering
->rx_max_pending
= MAX_RX_DESC_1
;
4911 else if (sp
->rxd_mode
== RXD_MODE_3B
)
4912 ering
->rx_max_pending
= MAX_RX_DESC_2
;
4913 else if (sp
->rxd_mode
== RXD_MODE_3A
)
4914 ering
->rx_max_pending
= MAX_RX_DESC_3
;
4916 ering
->tx_max_pending
= MAX_TX_DESC
;
4917 for (i
= 0 ; i
< sp
->config
.tx_fifo_num
; i
++) {
4918 tx_desc_count
+= sp
->config
.tx_cfg
[i
].fifo_len
;
4920 DBG_PRINT(INFO_DBG
,"\nmax txds : %d\n",sp
->config
.max_txds
);
4921 ering
->tx_pending
= tx_desc_count
;
4923 for (i
= 0 ; i
< sp
->config
.rx_ring_num
; i
++) {
4924 rx_desc_count
+= sp
->config
.rx_cfg
[i
].num_rxd
;
4926 ering
->rx_pending
= rx_desc_count
;
4928 ering
->rx_mini_max_pending
= 0;
4929 ering
->rx_mini_pending
= 0;
4930 if(sp
->rxd_mode
== RXD_MODE_1
)
4931 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_1
;
4932 else if (sp
->rxd_mode
== RXD_MODE_3B
)
4933 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_2
;
4934 ering
->rx_jumbo_pending
= rx_desc_count
;
4938 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4939 * @sp : private member of the device structure, which is a pointer to the
4940 * s2io_nic structure.
4941 * @ep : pointer to the structure with pause parameters given by ethtool.
4943 * Returns the Pause frame generation and reception capability of the NIC.
4947 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
4948 struct ethtool_pauseparam
*ep
)
4951 struct s2io_nic
*sp
= dev
->priv
;
4952 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4954 val64
= readq(&bar0
->rmac_pause_cfg
);
4955 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
4956 ep
->tx_pause
= TRUE
;
4957 if (val64
& RMAC_PAUSE_RX_ENABLE
)
4958 ep
->rx_pause
= TRUE
;
4959 ep
->autoneg
= FALSE
;
4963 * s2io_ethtool_setpause_data - set/reset pause frame generation.
4964 * @sp : private member of the device structure, which is a pointer to the
4965 * s2io_nic structure.
4966 * @ep : pointer to the structure with pause parameters given by ethtool.
4968 * It can be used to set or reset Pause frame generation or reception
4969 * support of the NIC.
4971 * int, returns 0 on Success
4974 static int s2io_ethtool_setpause_data(struct net_device
*dev
,
4975 struct ethtool_pauseparam
*ep
)
4978 struct s2io_nic
*sp
= dev
->priv
;
4979 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4981 val64
= readq(&bar0
->rmac_pause_cfg
);
4983 val64
|= RMAC_PAUSE_GEN_ENABLE
;
4985 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
4987 val64
|= RMAC_PAUSE_RX_ENABLE
;
4989 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
4990 writeq(val64
, &bar0
->rmac_pause_cfg
);
4995 * read_eeprom - reads 4 bytes of data from user given offset.
4996 * @sp : private member of the device structure, which is a pointer to the
4997 * s2io_nic structure.
4998 * @off : offset at which the data must be written
4999 * @data : Its an output parameter where the data read at the given
5002 * Will read 4 bytes of data from the user given offset and return the
5004 * NOTE: Will allow to read only part of the EEPROM visible through the
5007 * -1 on failure and 0 on success.
5010 #define S2IO_DEV_ID 5
5011 static int read_eeprom(struct s2io_nic
* sp
, int off
, u64
* data
)
5016 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5018 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5019 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5020 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ
|
5021 I2C_CONTROL_CNTL_START
;
5022 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5024 while (exit_cnt
< 5) {
5025 val64
= readq(&bar0
->i2c_control
);
5026 if (I2C_CONTROL_CNTL_END(val64
)) {
5027 *data
= I2C_CONTROL_GET_DATA(val64
);
5036 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5037 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5038 SPI_CONTROL_BYTECNT(0x3) |
5039 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off
);
5040 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5041 val64
|= SPI_CONTROL_REQ
;
5042 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5043 while (exit_cnt
< 5) {
5044 val64
= readq(&bar0
->spi_control
);
5045 if (val64
& SPI_CONTROL_NACK
) {
5048 } else if (val64
& SPI_CONTROL_DONE
) {
5049 *data
= readq(&bar0
->spi_data
);
5062 * write_eeprom - actually writes the relevant part of the data value.
5063 * @sp : private member of the device structure, which is a pointer to the
5064 * s2io_nic structure.
5065 * @off : offset at which the data must be written
5066 * @data : The data that is to be written
5067 * @cnt : Number of bytes of the data that are actually to be written into
5068 * the Eeprom. (max of 3)
5070 * Actually writes the relevant part of the data value into the Eeprom
5071 * through the I2C bus.
5073 * 0 on success, -1 on failure.
5076 static int write_eeprom(struct s2io_nic
* sp
, int off
, u64 data
, int cnt
)
5078 int exit_cnt
= 0, ret
= -1;
5080 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5082 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5083 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5084 I2C_CONTROL_BYTE_CNT(cnt
) | I2C_CONTROL_SET_DATA((u32
)data
) |
5085 I2C_CONTROL_CNTL_START
;
5086 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5088 while (exit_cnt
< 5) {
5089 val64
= readq(&bar0
->i2c_control
);
5090 if (I2C_CONTROL_CNTL_END(val64
)) {
5091 if (!(val64
& I2C_CONTROL_NACK
))
5100 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5101 int write_cnt
= (cnt
== 8) ? 0 : cnt
;
5102 writeq(SPI_DATA_WRITE(data
,(cnt
<<3)), &bar0
->spi_data
);
5104 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5105 SPI_CONTROL_BYTECNT(write_cnt
) |
5106 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off
);
5107 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5108 val64
|= SPI_CONTROL_REQ
;
5109 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5110 while (exit_cnt
< 5) {
5111 val64
= readq(&bar0
->spi_control
);
5112 if (val64
& SPI_CONTROL_NACK
) {
5115 } else if (val64
& SPI_CONTROL_DONE
) {
5125 static void s2io_vpd_read(struct s2io_nic
*nic
)
5129 int i
=0, cnt
, fail
= 0;
5130 int vpd_addr
= 0x80;
5132 if (nic
->device_type
== XFRAME_II_DEVICE
) {
5133 strcpy(nic
->product_name
, "Xframe II 10GbE network adapter");
5137 strcpy(nic
->product_name
, "Xframe I 10GbE network adapter");
5140 strcpy(nic
->serial_num
, "NOT AVAILABLE");
5142 vpd_data
= kmalloc(256, GFP_KERNEL
);
5144 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
5147 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
+= 256;
5149 for (i
= 0; i
< 256; i
+=4 ) {
5150 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 2), i
);
5151 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 2), &data
);
5152 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 3), 0);
5153 for (cnt
= 0; cnt
<5; cnt
++) {
5155 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 3), &data
);
5160 DBG_PRINT(ERR_DBG
, "Read of VPD data failed\n");
5164 pci_read_config_dword(nic
->pdev
, (vpd_addr
+ 4),
5165 (u32
*)&vpd_data
[i
]);
5169 /* read serial number of adapter */
5170 for (cnt
= 0; cnt
< 256; cnt
++) {
5171 if ((vpd_data
[cnt
] == 'S') &&
5172 (vpd_data
[cnt
+1] == 'N') &&
5173 (vpd_data
[cnt
+2] < VPD_STRING_LEN
)) {
5174 memset(nic
->serial_num
, 0, VPD_STRING_LEN
);
5175 memcpy(nic
->serial_num
, &vpd_data
[cnt
+ 3],
5182 if ((!fail
) && (vpd_data
[1] < VPD_STRING_LEN
)) {
5183 memset(nic
->product_name
, 0, vpd_data
[1]);
5184 memcpy(nic
->product_name
, &vpd_data
[3], vpd_data
[1]);
5187 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= 256;
5191 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5192 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5193 * @eeprom : pointer to the user level structure provided by ethtool,
5194 * containing all relevant information.
5195 * @data_buf : user defined value to be written into Eeprom.
5196 * Description: Reads the values stored in the Eeprom at given offset
5197 * for a given length. Stores these values int the input argument data
5198 * buffer 'data_buf' and returns these to the caller (ethtool.)
5203 static int s2io_ethtool_geeprom(struct net_device
*dev
,
5204 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
5208 struct s2io_nic
*sp
= dev
->priv
;
5210 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
5212 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
5213 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
5215 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
5216 if (read_eeprom(sp
, (eeprom
->offset
+ i
), &data
)) {
5217 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
5221 memcpy((data_buf
+ i
), &valid
, 4);
5227 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5228 * @sp : private member of the device structure, which is a pointer to the
5229 * s2io_nic structure.
5230 * @eeprom : pointer to the user level structure provided by ethtool,
5231 * containing all relevant information.
5232 * @data_buf ; user defined value to be written into Eeprom.
5234 * Tries to write the user provided value in the Eeprom, at the offset
5235 * given by the user.
5237 * 0 on success, -EFAULT on failure.
5240 static int s2io_ethtool_seeprom(struct net_device
*dev
,
5241 struct ethtool_eeprom
*eeprom
,
5244 int len
= eeprom
->len
, cnt
= 0;
5245 u64 valid
= 0, data
;
5246 struct s2io_nic
*sp
= dev
->priv
;
5248 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
5250 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5251 DBG_PRINT(ERR_DBG
, "is wrong, Its not 0x%x\n",
5257 data
= (u32
) data_buf
[cnt
] & 0x000000FF;
5259 valid
= (u32
) (data
<< 24);
5263 if (write_eeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
5265 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5267 "write into the specified offset\n");
5278 * s2io_register_test - reads and writes into all clock domains.
5279 * @sp : private member of the device structure, which is a pointer to the
5280 * s2io_nic structure.
5281 * @data : variable that returns the result of each of the test conducted b
5284 * Read and write into all clock domains. The NIC has 3 clock domains,
5285 * see that registers in all the three regions are accessible.
5290 static int s2io_register_test(struct s2io_nic
* sp
, uint64_t * data
)
5292 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5293 u64 val64
= 0, exp_val
;
5296 val64
= readq(&bar0
->pif_rd_swapper_fb
);
5297 if (val64
!= 0x123456789abcdefULL
) {
5299 DBG_PRINT(INFO_DBG
, "Read Test level 1 fails\n");
5302 val64
= readq(&bar0
->rmac_pause_cfg
);
5303 if (val64
!= 0xc000ffff00000000ULL
) {
5305 DBG_PRINT(INFO_DBG
, "Read Test level 2 fails\n");
5308 val64
= readq(&bar0
->rx_queue_cfg
);
5309 if (sp
->device_type
== XFRAME_II_DEVICE
)
5310 exp_val
= 0x0404040404040404ULL
;
5312 exp_val
= 0x0808080808080808ULL
;
5313 if (val64
!= exp_val
) {
5315 DBG_PRINT(INFO_DBG
, "Read Test level 3 fails\n");
5318 val64
= readq(&bar0
->xgxs_efifo_cfg
);
5319 if (val64
!= 0x000000001923141EULL
) {
5321 DBG_PRINT(INFO_DBG
, "Read Test level 4 fails\n");
5324 val64
= 0x5A5A5A5A5A5A5A5AULL
;
5325 writeq(val64
, &bar0
->xmsi_data
);
5326 val64
= readq(&bar0
->xmsi_data
);
5327 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
5329 DBG_PRINT(ERR_DBG
, "Write Test level 1 fails\n");
5332 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
5333 writeq(val64
, &bar0
->xmsi_data
);
5334 val64
= readq(&bar0
->xmsi_data
);
5335 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
5337 DBG_PRINT(ERR_DBG
, "Write Test level 2 fails\n");
5345 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5346 * @sp : private member of the device structure, which is a pointer to the
5347 * s2io_nic structure.
5348 * @data:variable that returns the result of each of the test conducted by
5351 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5357 static int s2io_eeprom_test(struct s2io_nic
* sp
, uint64_t * data
)
5360 u64 ret_data
, org_4F0
, org_7F0
;
5361 u8 saved_4F0
= 0, saved_7F0
= 0;
5362 struct net_device
*dev
= sp
->dev
;
5364 /* Test Write Error at offset 0 */
5365 /* Note that SPI interface allows write access to all areas
5366 * of EEPROM. Hence doing all negative testing only for Xframe I.
5368 if (sp
->device_type
== XFRAME_I_DEVICE
)
5369 if (!write_eeprom(sp
, 0, 0, 3))
5372 /* Save current values at offsets 0x4F0 and 0x7F0 */
5373 if (!read_eeprom(sp
, 0x4F0, &org_4F0
))
5375 if (!read_eeprom(sp
, 0x7F0, &org_7F0
))
5378 /* Test Write at offset 4f0 */
5379 if (write_eeprom(sp
, 0x4F0, 0x012345, 3))
5381 if (read_eeprom(sp
, 0x4F0, &ret_data
))
5384 if (ret_data
!= 0x012345) {
5385 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x4F0. "
5386 "Data written %llx Data read %llx\n",
5387 dev
->name
, (unsigned long long)0x12345,
5388 (unsigned long long)ret_data
);
5392 /* Reset the EEPROM data go FFFF */
5393 write_eeprom(sp
, 0x4F0, 0xFFFFFF, 3);
5395 /* Test Write Request Error at offset 0x7c */
5396 if (sp
->device_type
== XFRAME_I_DEVICE
)
5397 if (!write_eeprom(sp
, 0x07C, 0, 3))
5400 /* Test Write Request at offset 0x7f0 */
5401 if (write_eeprom(sp
, 0x7F0, 0x012345, 3))
5403 if (read_eeprom(sp
, 0x7F0, &ret_data
))
5406 if (ret_data
!= 0x012345) {
5407 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x7F0. "
5408 "Data written %llx Data read %llx\n",
5409 dev
->name
, (unsigned long long)0x12345,
5410 (unsigned long long)ret_data
);
5414 /* Reset the EEPROM data go FFFF */
5415 write_eeprom(sp
, 0x7F0, 0xFFFFFF, 3);
5417 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5418 /* Test Write Error at offset 0x80 */
5419 if (!write_eeprom(sp
, 0x080, 0, 3))
5422 /* Test Write Error at offset 0xfc */
5423 if (!write_eeprom(sp
, 0x0FC, 0, 3))
5426 /* Test Write Error at offset 0x100 */
5427 if (!write_eeprom(sp
, 0x100, 0, 3))
5430 /* Test Write Error at offset 4ec */
5431 if (!write_eeprom(sp
, 0x4EC, 0, 3))
5435 /* Restore values at offsets 0x4F0 and 0x7F0 */
5437 write_eeprom(sp
, 0x4F0, org_4F0
, 3);
5439 write_eeprom(sp
, 0x7F0, org_7F0
, 3);
5446 * s2io_bist_test - invokes the MemBist test of the card .
5447 * @sp : private member of the device structure, which is a pointer to the
5448 * s2io_nic structure.
5449 * @data:variable that returns the result of each of the test conducted by
5452 * This invokes the MemBist test of the card. We give around
5453 * 2 secs time for the Test to complete. If it's still not complete
5454 * within this peiod, we consider that the test failed.
5456 * 0 on success and -1 on failure.
5459 static int s2io_bist_test(struct s2io_nic
* sp
, uint64_t * data
)
5462 int cnt
= 0, ret
= -1;
5464 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
5465 bist
|= PCI_BIST_START
;
5466 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
5469 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
5470 if (!(bist
& PCI_BIST_START
)) {
5471 *data
= (bist
& PCI_BIST_CODE_MASK
);
5483 * s2io-link_test - verifies the link state of the nic
5484 * @sp ; private member of the device structure, which is a pointer to the
5485 * s2io_nic structure.
5486 * @data: variable that returns the result of each of the test conducted by
5489 * The function verifies the link state of the NIC and updates the input
5490 * argument 'data' appropriately.
5495 static int s2io_link_test(struct s2io_nic
* sp
, uint64_t * data
)
5497 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5500 val64
= readq(&bar0
->adapter_status
);
5501 if(!(LINK_IS_UP(val64
)))
5510 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5511 * @sp - private member of the device structure, which is a pointer to the
5512 * s2io_nic structure.
5513 * @data - variable that returns the result of each of the test
5514 * conducted by the driver.
5516 * This is one of the offline test that tests the read and write
5517 * access to the RldRam chip on the NIC.
5522 static int s2io_rldram_test(struct s2io_nic
* sp
, uint64_t * data
)
5524 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5526 int cnt
, iteration
= 0, test_fail
= 0;
5528 val64
= readq(&bar0
->adapter_control
);
5529 val64
&= ~ADAPTER_ECC_EN
;
5530 writeq(val64
, &bar0
->adapter_control
);
5532 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5533 val64
|= MC_RLDRAM_TEST_MODE
;
5534 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5536 val64
= readq(&bar0
->mc_rldram_mrs
);
5537 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
5538 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
5540 val64
|= MC_RLDRAM_MRS_ENABLE
;
5541 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
5543 while (iteration
< 2) {
5544 val64
= 0x55555555aaaa0000ULL
;
5545 if (iteration
== 1) {
5546 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5548 writeq(val64
, &bar0
->mc_rldram_test_d0
);
5550 val64
= 0xaaaa5a5555550000ULL
;
5551 if (iteration
== 1) {
5552 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5554 writeq(val64
, &bar0
->mc_rldram_test_d1
);
5556 val64
= 0x55aaaaaaaa5a0000ULL
;
5557 if (iteration
== 1) {
5558 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5560 writeq(val64
, &bar0
->mc_rldram_test_d2
);
5562 val64
= (u64
) (0x0000003ffffe0100ULL
);
5563 writeq(val64
, &bar0
->mc_rldram_test_add
);
5565 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_WRITE
|
5567 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5569 for (cnt
= 0; cnt
< 5; cnt
++) {
5570 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5571 if (val64
& MC_RLDRAM_TEST_DONE
)
5579 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
5580 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5582 for (cnt
= 0; cnt
< 5; cnt
++) {
5583 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5584 if (val64
& MC_RLDRAM_TEST_DONE
)
5592 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5593 if (!(val64
& MC_RLDRAM_TEST_PASS
))
5601 /* Bring the adapter out of test mode */
5602 SPECIAL_REG_WRITE(0, &bar0
->mc_rldram_test_ctrl
, LF
);
5608 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5609 * @sp : private member of the device structure, which is a pointer to the
5610 * s2io_nic structure.
5611 * @ethtest : pointer to a ethtool command specific structure that will be
5612 * returned to the user.
5613 * @data : variable that returns the result of each of the test
5614 * conducted by the driver.
5616 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5617 * the health of the card.
5622 static void s2io_ethtool_test(struct net_device
*dev
,
5623 struct ethtool_test
*ethtest
,
5626 struct s2io_nic
*sp
= dev
->priv
;
5627 int orig_state
= netif_running(sp
->dev
);
5629 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
5630 /* Offline Tests. */
5632 s2io_close(sp
->dev
);
5634 if (s2io_register_test(sp
, &data
[0]))
5635 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5639 if (s2io_rldram_test(sp
, &data
[3]))
5640 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5644 if (s2io_eeprom_test(sp
, &data
[1]))
5645 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5647 if (s2io_bist_test(sp
, &data
[4]))
5648 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5658 "%s: is not up, cannot run test\n",
5667 if (s2io_link_test(sp
, &data
[2]))
5668 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5677 static void s2io_get_ethtool_stats(struct net_device
*dev
,
5678 struct ethtool_stats
*estats
,
5682 struct s2io_nic
*sp
= dev
->priv
;
5683 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
5685 s2io_updt_stats(sp
);
5687 (u64
)le32_to_cpu(stat_info
->tmac_frms_oflow
) << 32 |
5688 le32_to_cpu(stat_info
->tmac_frms
);
5690 (u64
)le32_to_cpu(stat_info
->tmac_data_octets_oflow
) << 32 |
5691 le32_to_cpu(stat_info
->tmac_data_octets
);
5692 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_drop_frms
);
5694 (u64
)le32_to_cpu(stat_info
->tmac_mcst_frms_oflow
) << 32 |
5695 le32_to_cpu(stat_info
->tmac_mcst_frms
);
5697 (u64
)le32_to_cpu(stat_info
->tmac_bcst_frms_oflow
) << 32 |
5698 le32_to_cpu(stat_info
->tmac_bcst_frms
);
5699 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_pause_ctrl_frms
);
5701 (u64
)le32_to_cpu(stat_info
->tmac_ttl_octets_oflow
) << 32 |
5702 le32_to_cpu(stat_info
->tmac_ttl_octets
);
5704 (u64
)le32_to_cpu(stat_info
->tmac_ucst_frms_oflow
) << 32 |
5705 le32_to_cpu(stat_info
->tmac_ucst_frms
);
5707 (u64
)le32_to_cpu(stat_info
->tmac_nucst_frms_oflow
) << 32 |
5708 le32_to_cpu(stat_info
->tmac_nucst_frms
);
5710 (u64
)le32_to_cpu(stat_info
->tmac_any_err_frms_oflow
) << 32 |
5711 le32_to_cpu(stat_info
->tmac_any_err_frms
);
5712 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_ttl_less_fb_octets
);
5713 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_vld_ip_octets
);
5715 (u64
)le32_to_cpu(stat_info
->tmac_vld_ip_oflow
) << 32 |
5716 le32_to_cpu(stat_info
->tmac_vld_ip
);
5718 (u64
)le32_to_cpu(stat_info
->tmac_drop_ip_oflow
) << 32 |
5719 le32_to_cpu(stat_info
->tmac_drop_ip
);
5721 (u64
)le32_to_cpu(stat_info
->tmac_icmp_oflow
) << 32 |
5722 le32_to_cpu(stat_info
->tmac_icmp
);
5724 (u64
)le32_to_cpu(stat_info
->tmac_rst_tcp_oflow
) << 32 |
5725 le32_to_cpu(stat_info
->tmac_rst_tcp
);
5726 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_tcp
);
5727 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->tmac_udp_oflow
) << 32 |
5728 le32_to_cpu(stat_info
->tmac_udp
);
5730 (u64
)le32_to_cpu(stat_info
->rmac_vld_frms_oflow
) << 32 |
5731 le32_to_cpu(stat_info
->rmac_vld_frms
);
5733 (u64
)le32_to_cpu(stat_info
->rmac_data_octets_oflow
) << 32 |
5734 le32_to_cpu(stat_info
->rmac_data_octets
);
5735 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_fcs_err_frms
);
5736 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_drop_frms
);
5738 (u64
)le32_to_cpu(stat_info
->rmac_vld_mcst_frms_oflow
) << 32 |
5739 le32_to_cpu(stat_info
->rmac_vld_mcst_frms
);
5741 (u64
)le32_to_cpu(stat_info
->rmac_vld_bcst_frms_oflow
) << 32 |
5742 le32_to_cpu(stat_info
->rmac_vld_bcst_frms
);
5743 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_in_rng_len_err_frms
);
5744 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_out_rng_len_err_frms
);
5745 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_long_frms
);
5746 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_pause_ctrl_frms
);
5747 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_unsup_ctrl_frms
);
5749 (u64
)le32_to_cpu(stat_info
->rmac_ttl_octets_oflow
) << 32 |
5750 le32_to_cpu(stat_info
->rmac_ttl_octets
);
5752 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ucst_frms_oflow
)
5753 << 32 | le32_to_cpu(stat_info
->rmac_accepted_ucst_frms
);
5755 (u64
)le32_to_cpu(stat_info
->rmac_accepted_nucst_frms_oflow
)
5756 << 32 | le32_to_cpu(stat_info
->rmac_accepted_nucst_frms
);
5758 (u64
)le32_to_cpu(stat_info
->rmac_discarded_frms_oflow
) << 32 |
5759 le32_to_cpu(stat_info
->rmac_discarded_frms
);
5761 (u64
)le32_to_cpu(stat_info
->rmac_drop_events_oflow
)
5762 << 32 | le32_to_cpu(stat_info
->rmac_drop_events
);
5763 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_less_fb_octets
);
5764 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_frms
);
5766 (u64
)le32_to_cpu(stat_info
->rmac_usized_frms_oflow
) << 32 |
5767 le32_to_cpu(stat_info
->rmac_usized_frms
);
5769 (u64
)le32_to_cpu(stat_info
->rmac_osized_frms_oflow
) << 32 |
5770 le32_to_cpu(stat_info
->rmac_osized_frms
);
5772 (u64
)le32_to_cpu(stat_info
->rmac_frag_frms_oflow
) << 32 |
5773 le32_to_cpu(stat_info
->rmac_frag_frms
);
5775 (u64
)le32_to_cpu(stat_info
->rmac_jabber_frms_oflow
) << 32 |
5776 le32_to_cpu(stat_info
->rmac_jabber_frms
);
5777 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_64_frms
);
5778 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_65_127_frms
);
5779 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_128_255_frms
);
5780 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_256_511_frms
);
5781 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_512_1023_frms
);
5782 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_1024_1518_frms
);
5784 (u64
)le32_to_cpu(stat_info
->rmac_ip_oflow
) << 32 |
5785 le32_to_cpu(stat_info
->rmac_ip
);
5786 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ip_octets
);
5787 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_hdr_err_ip
);
5789 (u64
)le32_to_cpu(stat_info
->rmac_drop_ip_oflow
) << 32 |
5790 le32_to_cpu(stat_info
->rmac_drop_ip
);
5792 (u64
)le32_to_cpu(stat_info
->rmac_icmp_oflow
) << 32 |
5793 le32_to_cpu(stat_info
->rmac_icmp
);
5794 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_tcp
);
5796 (u64
)le32_to_cpu(stat_info
->rmac_udp_oflow
) << 32 |
5797 le32_to_cpu(stat_info
->rmac_udp
);
5799 (u64
)le32_to_cpu(stat_info
->rmac_err_drp_udp_oflow
) << 32 |
5800 le32_to_cpu(stat_info
->rmac_err_drp_udp
);
5801 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_err_sym
);
5802 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q0
);
5803 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q1
);
5804 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q2
);
5805 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q3
);
5806 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q4
);
5807 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q5
);
5808 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q6
);
5809 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q7
);
5810 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q0
);
5811 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q1
);
5812 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q2
);
5813 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q3
);
5814 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q4
);
5815 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q5
);
5816 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q6
);
5817 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q7
);
5819 (u64
)le32_to_cpu(stat_info
->rmac_pause_cnt_oflow
) << 32 |
5820 le32_to_cpu(stat_info
->rmac_pause_cnt
);
5821 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_data_err_cnt
);
5822 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_ctrl_err_cnt
);
5824 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ip_oflow
) << 32 |
5825 le32_to_cpu(stat_info
->rmac_accepted_ip
);
5826 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_err_tcp
);
5827 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_req_cnt
);
5828 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_cnt
);
5829 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_rtry_cnt
);
5830 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_cnt
);
5831 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_rd_ack_cnt
);
5832 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_req_cnt
);
5833 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_cnt
);
5834 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_rtry_cnt
);
5835 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_cnt
);
5836 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_disc_cnt
);
5837 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_wr_ack_cnt
);
5838 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txp_wr_cnt
);
5839 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_rd_cnt
);
5840 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_wr_cnt
);
5841 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_rd_cnt
);
5842 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_wr_cnt
);
5843 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txf_rd_cnt
);
5844 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxf_wr_cnt
);
5846 /* Enhanced statistics exist only for Hercules */
5847 if(sp
->device_type
== XFRAME_II_DEVICE
) {
5849 le64_to_cpu(stat_info
->rmac_ttl_1519_4095_frms
);
5851 le64_to_cpu(stat_info
->rmac_ttl_4096_8191_frms
);
5853 le64_to_cpu(stat_info
->rmac_ttl_8192_max_frms
);
5854 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_gt_max_frms
);
5855 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_osized_alt_frms
);
5856 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_jabber_alt_frms
);
5857 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_gt_max_alt_frms
);
5858 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_vlan_frms
);
5859 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_len_discard
);
5860 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_fcs_discard
);
5861 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_pf_discard
);
5862 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_da_discard
);
5863 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_red_discard
);
5864 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_rts_discard
);
5865 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_ingm_full_discard
);
5866 tmp_stats
[i
++] = le32_to_cpu(stat_info
->link_fault_cnt
);
5870 tmp_stats
[i
++] = stat_info
->sw_stat
.single_ecc_errs
;
5871 tmp_stats
[i
++] = stat_info
->sw_stat
.double_ecc_errs
;
5872 tmp_stats
[i
++] = stat_info
->sw_stat
.parity_err_cnt
;
5873 tmp_stats
[i
++] = stat_info
->sw_stat
.serious_err_cnt
;
5874 tmp_stats
[i
++] = stat_info
->sw_stat
.soft_reset_cnt
;
5875 tmp_stats
[i
++] = stat_info
->sw_stat
.fifo_full_cnt
;
5876 tmp_stats
[i
++] = stat_info
->sw_stat
.ring_full_cnt
;
5877 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_high
;
5878 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_low
;
5879 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_high
;
5880 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_low
;
5881 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_high
;
5882 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_low
;
5883 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_high
;
5884 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_low
;
5885 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_high
;
5886 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_low
;
5887 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_high
;
5888 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_low
;
5889 tmp_stats
[i
++] = stat_info
->sw_stat
.clubbed_frms_cnt
;
5890 tmp_stats
[i
++] = stat_info
->sw_stat
.sending_both
;
5891 tmp_stats
[i
++] = stat_info
->sw_stat
.outof_sequence_pkts
;
5892 tmp_stats
[i
++] = stat_info
->sw_stat
.flush_max_pkts
;
5893 if (stat_info
->sw_stat
.num_aggregations
) {
5894 u64 tmp
= stat_info
->sw_stat
.sum_avg_pkts_aggregated
;
5897 * Since 64-bit divide does not work on all platforms,
5898 * do repeated subtraction.
5900 while (tmp
>= stat_info
->sw_stat
.num_aggregations
) {
5901 tmp
-= stat_info
->sw_stat
.num_aggregations
;
5904 tmp_stats
[i
++] = count
;
5908 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_alloc_fail_cnt
;
5909 tmp_stats
[i
++] = stat_info
->sw_stat
.watchdog_timer_cnt
;
5910 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_allocated
;
5911 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_freed
;
5912 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_cnt
;
5913 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_cnt
;
5914 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_time
;
5915 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_time
;
5917 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_buf_abort_cnt
;
5918 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_desc_abort_cnt
;
5919 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_parity_err_cnt
;
5920 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_link_loss_cnt
;
5921 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_list_proc_err_cnt
;
5923 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_err_cnt
;
5924 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_abort_cnt
;
5925 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_abort_cnt
;
5926 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rda_fail_cnt
;
5927 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_prot_cnt
;
5928 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_fcs_err_cnt
;
5929 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_buf_size_err_cnt
;
5930 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rxd_corrupt_cnt
;
5931 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_err_cnt
;
5934 static int s2io_ethtool_get_regs_len(struct net_device
*dev
)
5936 return (XENA_REG_SPACE
);
5940 static u32
s2io_ethtool_get_rx_csum(struct net_device
* dev
)
5942 struct s2io_nic
*sp
= dev
->priv
;
5944 return (sp
->rx_csum
);
5947 static int s2io_ethtool_set_rx_csum(struct net_device
*dev
, u32 data
)
5949 struct s2io_nic
*sp
= dev
->priv
;
5959 static int s2io_get_eeprom_len(struct net_device
*dev
)
5961 return (XENA_EEPROM_SPACE
);
5964 static int s2io_ethtool_self_test_count(struct net_device
*dev
)
5966 return (S2IO_TEST_LEN
);
5969 static void s2io_ethtool_get_strings(struct net_device
*dev
,
5970 u32 stringset
, u8
* data
)
5973 struct s2io_nic
*sp
= dev
->priv
;
5975 switch (stringset
) {
5977 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
5980 stat_size
= sizeof(ethtool_xena_stats_keys
);
5981 memcpy(data
, ðtool_xena_stats_keys
,stat_size
);
5982 if(sp
->device_type
== XFRAME_II_DEVICE
) {
5983 memcpy(data
+ stat_size
,
5984 ðtool_enhanced_stats_keys
,
5985 sizeof(ethtool_enhanced_stats_keys
));
5986 stat_size
+= sizeof(ethtool_enhanced_stats_keys
);
5989 memcpy(data
+ stat_size
, ðtool_driver_stats_keys
,
5990 sizeof(ethtool_driver_stats_keys
));
5993 static int s2io_ethtool_get_stats_count(struct net_device
*dev
)
5995 struct s2io_nic
*sp
= dev
->priv
;
5997 switch(sp
->device_type
) {
5998 case XFRAME_I_DEVICE
:
5999 stat_count
= XFRAME_I_STAT_LEN
;
6002 case XFRAME_II_DEVICE
:
6003 stat_count
= XFRAME_II_STAT_LEN
;
6010 static int s2io_ethtool_op_set_tx_csum(struct net_device
*dev
, u32 data
)
6013 dev
->features
|= NETIF_F_IP_CSUM
;
6015 dev
->features
&= ~NETIF_F_IP_CSUM
;
6020 static u32
s2io_ethtool_op_get_tso(struct net_device
*dev
)
6022 return (dev
->features
& NETIF_F_TSO
) != 0;
6024 static int s2io_ethtool_op_set_tso(struct net_device
*dev
, u32 data
)
6027 dev
->features
|= (NETIF_F_TSO
| NETIF_F_TSO6
);
6029 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
6034 static const struct ethtool_ops netdev_ethtool_ops
= {
6035 .get_settings
= s2io_ethtool_gset
,
6036 .set_settings
= s2io_ethtool_sset
,
6037 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
6038 .get_regs_len
= s2io_ethtool_get_regs_len
,
6039 .get_regs
= s2io_ethtool_gregs
,
6040 .get_link
= ethtool_op_get_link
,
6041 .get_eeprom_len
= s2io_get_eeprom_len
,
6042 .get_eeprom
= s2io_ethtool_geeprom
,
6043 .set_eeprom
= s2io_ethtool_seeprom
,
6044 .get_ringparam
= s2io_ethtool_gringparam
,
6045 .get_pauseparam
= s2io_ethtool_getpause_data
,
6046 .set_pauseparam
= s2io_ethtool_setpause_data
,
6047 .get_rx_csum
= s2io_ethtool_get_rx_csum
,
6048 .set_rx_csum
= s2io_ethtool_set_rx_csum
,
6049 .get_tx_csum
= ethtool_op_get_tx_csum
,
6050 .set_tx_csum
= s2io_ethtool_op_set_tx_csum
,
6051 .get_sg
= ethtool_op_get_sg
,
6052 .set_sg
= ethtool_op_set_sg
,
6053 .get_tso
= s2io_ethtool_op_get_tso
,
6054 .set_tso
= s2io_ethtool_op_set_tso
,
6055 .get_ufo
= ethtool_op_get_ufo
,
6056 .set_ufo
= ethtool_op_set_ufo
,
6057 .self_test_count
= s2io_ethtool_self_test_count
,
6058 .self_test
= s2io_ethtool_test
,
6059 .get_strings
= s2io_ethtool_get_strings
,
6060 .phys_id
= s2io_ethtool_idnic
,
6061 .get_stats_count
= s2io_ethtool_get_stats_count
,
6062 .get_ethtool_stats
= s2io_get_ethtool_stats
6066 * s2io_ioctl - Entry point for the Ioctl
6067 * @dev : Device pointer.
6068 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6069 * a proprietary structure used to pass information to the driver.
6070 * @cmd : This is used to distinguish between the different commands that
6071 * can be passed to the IOCTL functions.
6073 * Currently there are no special functionality supported in IOCTL, hence
6074 * function always return EOPNOTSUPPORTED
6077 static int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
6083 * s2io_change_mtu - entry point to change MTU size for the device.
6084 * @dev : device pointer.
6085 * @new_mtu : the new MTU size for the device.
6086 * Description: A driver entry point to change MTU size for the device.
6087 * Before changing the MTU the device must be stopped.
6089 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6093 static int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
6095 struct s2io_nic
*sp
= dev
->priv
;
6097 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
6098 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n",
6104 if (netif_running(dev
)) {
6106 netif_stop_queue(dev
);
6107 if (s2io_card_up(sp
)) {
6108 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6111 if (netif_queue_stopped(dev
))
6112 netif_wake_queue(dev
);
6113 } else { /* Device is down */
6114 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6115 u64 val64
= new_mtu
;
6117 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
6124 * s2io_tasklet - Bottom half of the ISR.
6125 * @dev_adr : address of the device structure in dma_addr_t format.
6127 * This is the tasklet or the bottom half of the ISR. This is
6128 * an extension of the ISR which is scheduled by the scheduler to be run
6129 * when the load on the CPU is low. All low priority tasks of the ISR can
6130 * be pushed into the tasklet. For now the tasklet is used only to
6131 * replenish the Rx buffers in the Rx buffer descriptors.
6136 static void s2io_tasklet(unsigned long dev_addr
)
6138 struct net_device
*dev
= (struct net_device
*) dev_addr
;
6139 struct s2io_nic
*sp
= dev
->priv
;
6141 struct mac_info
*mac_control
;
6142 struct config_param
*config
;
6144 mac_control
= &sp
->mac_control
;
6145 config
= &sp
->config
;
6147 if (!TASKLET_IN_USE
) {
6148 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6149 ret
= fill_rx_buffers(sp
, i
);
6150 if (ret
== -ENOMEM
) {
6151 DBG_PRINT(INFO_DBG
, "%s: Out of ",
6153 DBG_PRINT(INFO_DBG
, "memory in tasklet\n");
6155 } else if (ret
== -EFILL
) {
6157 "%s: Rx Ring %d is full\n",
6162 clear_bit(0, (&sp
->tasklet_status
));
6167 * s2io_set_link - Set the LInk status
6168 * @data: long pointer to device private structue
6169 * Description: Sets the link status for the adapter
6172 static void s2io_set_link(struct work_struct
*work
)
6174 struct s2io_nic
*nic
= container_of(work
, struct s2io_nic
, set_link_task
);
6175 struct net_device
*dev
= nic
->dev
;
6176 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
6182 if (!netif_running(dev
))
6185 if (test_and_set_bit(0, &(nic
->link_state
))) {
6186 /* The card is being reset, no point doing anything */
6190 subid
= nic
->pdev
->subsystem_device
;
6191 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
6193 * Allow a small delay for the NICs self initiated
6194 * cleanup to complete.
6199 val64
= readq(&bar0
->adapter_status
);
6200 if (LINK_IS_UP(val64
)) {
6201 if (!(readq(&bar0
->adapter_control
) & ADAPTER_CNTL_EN
)) {
6202 if (verify_xena_quiescence(nic
)) {
6203 val64
= readq(&bar0
->adapter_control
);
6204 val64
|= ADAPTER_CNTL_EN
;
6205 writeq(val64
, &bar0
->adapter_control
);
6206 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6207 nic
->device_type
, subid
)) {
6208 val64
= readq(&bar0
->gpio_control
);
6209 val64
|= GPIO_CTRL_GPIO_0
;
6210 writeq(val64
, &bar0
->gpio_control
);
6211 val64
= readq(&bar0
->gpio_control
);
6213 val64
|= ADAPTER_LED_ON
;
6214 writeq(val64
, &bar0
->adapter_control
);
6216 nic
->device_enabled_once
= TRUE
;
6218 DBG_PRINT(ERR_DBG
, "%s: Error: ", dev
->name
);
6219 DBG_PRINT(ERR_DBG
, "device is not Quiescent\n");
6220 netif_stop_queue(dev
);
6223 val64
= readq(&bar0
->adapter_status
);
6224 if (!LINK_IS_UP(val64
)) {
6225 DBG_PRINT(ERR_DBG
, "%s:", dev
->name
);
6226 DBG_PRINT(ERR_DBG
, " Link down after enabling ");
6227 DBG_PRINT(ERR_DBG
, "device \n");
6229 s2io_link(nic
, LINK_UP
);
6231 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
6233 val64
= readq(&bar0
->gpio_control
);
6234 val64
&= ~GPIO_CTRL_GPIO_0
;
6235 writeq(val64
, &bar0
->gpio_control
);
6236 val64
= readq(&bar0
->gpio_control
);
6238 s2io_link(nic
, LINK_DOWN
);
6240 clear_bit(0, &(nic
->link_state
));
6246 static int set_rxd_buffer_pointer(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6248 struct sk_buff
**skb
, u64
*temp0
, u64
*temp1
,
6249 u64
*temp2
, int size
)
6251 struct net_device
*dev
= sp
->dev
;
6252 struct sk_buff
*frag_list
;
6254 if ((sp
->rxd_mode
== RXD_MODE_1
) && (rxdp
->Host_Control
== 0)) {
6257 DBG_PRINT(INFO_DBG
, "SKB is not NULL\n");
6259 * As Rx frame are not going to be processed,
6260 * using same mapped address for the Rxd
6263 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= *temp0
;
6265 *skb
= dev_alloc_skb(size
);
6267 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6268 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6269 DBG_PRINT(INFO_DBG
, "1 buf mode SKBs\n");
6270 sp
->mac_control
.stats_info
->sw_stat
. \
6271 mem_alloc_fail_cnt
++;
6274 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6275 += (*skb
)->truesize
;
6276 /* storing the mapped addr in a temp variable
6277 * such it will be used for next rxd whose
6278 * Host Control is NULL
6280 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= *temp0
=
6281 pci_map_single( sp
->pdev
, (*skb
)->data
,
6282 size
- NET_IP_ALIGN
,
6283 PCI_DMA_FROMDEVICE
);
6284 rxdp
->Host_Control
= (unsigned long) (*skb
);
6286 } else if ((sp
->rxd_mode
== RXD_MODE_3B
) && (rxdp
->Host_Control
== 0)) {
6287 /* Two buffer Mode */
6289 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
;
6290 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
;
6291 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
;
6293 *skb
= dev_alloc_skb(size
);
6295 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6296 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6297 DBG_PRINT(INFO_DBG
, "2 buf mode SKBs\n");
6298 sp
->mac_control
.stats_info
->sw_stat
. \
6299 mem_alloc_fail_cnt
++;
6302 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6303 += (*skb
)->truesize
;
6304 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
=
6305 pci_map_single(sp
->pdev
, (*skb
)->data
,
6307 PCI_DMA_FROMDEVICE
);
6308 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
=
6309 pci_map_single( sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
6310 PCI_DMA_FROMDEVICE
);
6311 rxdp
->Host_Control
= (unsigned long) (*skb
);
6313 /* Buffer-1 will be dummy buffer not used */
6314 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
=
6315 pci_map_single(sp
->pdev
, ba
->ba_1
, BUF1_LEN
,
6316 PCI_DMA_FROMDEVICE
);
6318 } else if ((rxdp
->Host_Control
== 0)) {
6319 /* Three buffer mode */
6321 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
;
6322 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
;
6323 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
;
6325 *skb
= dev_alloc_skb(size
);
6327 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6328 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6329 DBG_PRINT(INFO_DBG
, "3 buf mode SKBs\n");
6330 sp
->mac_control
.stats_info
->sw_stat
. \
6331 mem_alloc_fail_cnt
++;
6334 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6335 += (*skb
)->truesize
;
6336 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
=
6337 pci_map_single(sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
6338 PCI_DMA_FROMDEVICE
);
6339 /* Buffer-1 receives L3/L4 headers */
6340 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
=
6341 pci_map_single( sp
->pdev
, (*skb
)->data
,
6343 PCI_DMA_FROMDEVICE
);
6345 * skb_shinfo(skb)->frag_list will have L4
6348 skb_shinfo(*skb
)->frag_list
= dev_alloc_skb(dev
->mtu
+
6350 if (skb_shinfo(*skb
)->frag_list
== NULL
) {
6351 DBG_PRINT(ERR_DBG
, "%s: dev_alloc_skb \
6352 failed\n ", dev
->name
);
6353 sp
->mac_control
.stats_info
->sw_stat
. \
6354 mem_alloc_fail_cnt
++;
6357 frag_list
= skb_shinfo(*skb
)->frag_list
;
6358 frag_list
->next
= NULL
;
6359 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6360 += frag_list
->truesize
;
6362 * Buffer-2 receives L4 data payload
6364 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
=
6365 pci_map_single( sp
->pdev
, frag_list
->data
,
6366 dev
->mtu
, PCI_DMA_FROMDEVICE
);
6371 static void set_rxd_buffer_size(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6374 struct net_device
*dev
= sp
->dev
;
6375 if (sp
->rxd_mode
== RXD_MODE_1
) {
6376 rxdp
->Control_2
= SET_BUFFER0_SIZE_1( size
- NET_IP_ALIGN
);
6377 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
6378 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6379 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
6380 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3( dev
->mtu
+ 4);
6382 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6383 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(l3l4hdr_size
+ 4);
6384 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3(dev
->mtu
);
6388 static int rxd_owner_bit_reset(struct s2io_nic
*sp
)
6390 int i
, j
, k
, blk_cnt
= 0, size
;
6391 struct mac_info
* mac_control
= &sp
->mac_control
;
6392 struct config_param
*config
= &sp
->config
;
6393 struct net_device
*dev
= sp
->dev
;
6394 struct RxD_t
*rxdp
= NULL
;
6395 struct sk_buff
*skb
= NULL
;
6396 struct buffAdd
*ba
= NULL
;
6397 u64 temp0_64
= 0, temp1_64
= 0, temp2_64
= 0;
6399 /* Calculate the size based on ring mode */
6400 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
6401 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
6402 if (sp
->rxd_mode
== RXD_MODE_1
)
6403 size
+= NET_IP_ALIGN
;
6404 else if (sp
->rxd_mode
== RXD_MODE_3B
)
6405 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6407 size
= l3l4hdr_size
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6409 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6410 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
6411 (rxd_count
[sp
->rxd_mode
] +1);
6413 for (j
= 0; j
< blk_cnt
; j
++) {
6414 for (k
= 0; k
< rxd_count
[sp
->rxd_mode
]; k
++) {
6415 rxdp
= mac_control
->rings
[i
].
6416 rx_blocks
[j
].rxds
[k
].virt_addr
;
6417 if(sp
->rxd_mode
>= RXD_MODE_3A
)
6418 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
6419 if (set_rxd_buffer_pointer(sp
, rxdp
, ba
,
6420 &skb
,(u64
*)&temp0_64
,
6427 set_rxd_buffer_size(sp
, rxdp
, size
);
6429 /* flip the Ownership bit to Hardware */
6430 rxdp
->Control_1
|= RXD_OWN_XENA
;
6438 static int s2io_add_isr(struct s2io_nic
* sp
)
6441 struct net_device
*dev
= sp
->dev
;
6444 if (sp
->intr_type
== MSI
)
6445 ret
= s2io_enable_msi(sp
);
6446 else if (sp
->intr_type
== MSI_X
)
6447 ret
= s2io_enable_msi_x(sp
);
6449 DBG_PRINT(ERR_DBG
, "%s: Defaulting to INTA\n", dev
->name
);
6450 sp
->intr_type
= INTA
;
6453 /* Store the values of the MSIX table in the struct s2io_nic structure */
6454 store_xmsi_data(sp
);
6456 /* After proper initialization of H/W, register ISR */
6457 if (sp
->intr_type
== MSI
) {
6458 err
= request_irq((int) sp
->pdev
->irq
, s2io_msi_handle
,
6459 IRQF_SHARED
, sp
->name
, dev
);
6461 pci_disable_msi(sp
->pdev
);
6462 DBG_PRINT(ERR_DBG
, "%s: MSI registration failed\n",
6467 if (sp
->intr_type
== MSI_X
) {
6468 int i
, msix_tx_cnt
=0,msix_rx_cnt
=0;
6470 for (i
=1; (sp
->s2io_entries
[i
].in_use
== MSIX_FLG
); i
++) {
6471 if (sp
->s2io_entries
[i
].type
== MSIX_FIFO_TYPE
) {
6472 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-TX",
6474 err
= request_irq(sp
->entries
[i
].vector
,
6475 s2io_msix_fifo_handle
, 0, sp
->desc
[i
],
6476 sp
->s2io_entries
[i
].arg
);
6477 /* If either data or addr is zero print it */
6478 if(!(sp
->msix_info
[i
].addr
&&
6479 sp
->msix_info
[i
].data
)) {
6480 DBG_PRINT(ERR_DBG
, "%s @ Addr:0x%llx"
6481 "Data:0x%lx\n",sp
->desc
[i
],
6482 (unsigned long long)
6483 sp
->msix_info
[i
].addr
,
6485 ntohl(sp
->msix_info
[i
].data
));
6490 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-RX",
6492 err
= request_irq(sp
->entries
[i
].vector
,
6493 s2io_msix_ring_handle
, 0, sp
->desc
[i
],
6494 sp
->s2io_entries
[i
].arg
);
6495 /* If either data or addr is zero print it */
6496 if(!(sp
->msix_info
[i
].addr
&&
6497 sp
->msix_info
[i
].data
)) {
6498 DBG_PRINT(ERR_DBG
, "%s @ Addr:0x%llx"
6499 "Data:0x%lx\n",sp
->desc
[i
],
6500 (unsigned long long)
6501 sp
->msix_info
[i
].addr
,
6503 ntohl(sp
->msix_info
[i
].data
));
6509 DBG_PRINT(ERR_DBG
,"%s:MSI-X-%d registration "
6510 "failed\n", dev
->name
, i
);
6511 DBG_PRINT(ERR_DBG
, "Returned: %d\n", err
);
6514 sp
->s2io_entries
[i
].in_use
= MSIX_REGISTERED_SUCCESS
;
6516 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt
);
6517 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt
);
6519 if (sp
->intr_type
== INTA
) {
6520 err
= request_irq((int) sp
->pdev
->irq
, s2io_isr
, IRQF_SHARED
,
6523 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
6530 static void s2io_rem_isr(struct s2io_nic
* sp
)
6533 struct net_device
*dev
= sp
->dev
;
6535 if (sp
->intr_type
== MSI_X
) {
6539 for (i
=1; (sp
->s2io_entries
[i
].in_use
==
6540 MSIX_REGISTERED_SUCCESS
); i
++) {
6541 int vector
= sp
->entries
[i
].vector
;
6542 void *arg
= sp
->s2io_entries
[i
].arg
;
6544 free_irq(vector
, arg
);
6546 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
6547 msi_control
&= 0xFFFE; /* Disable MSI */
6548 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
6550 pci_disable_msix(sp
->pdev
);
6552 free_irq(sp
->pdev
->irq
, dev
);
6553 if (sp
->intr_type
== MSI
) {
6556 pci_disable_msi(sp
->pdev
);
6557 pci_read_config_word(sp
->pdev
, 0x4c, &val
);
6559 pci_write_config_word(sp
->pdev
, 0x4c, val
);
6562 /* Waiting till all Interrupt handlers are complete */
6566 if (!atomic_read(&sp
->isr_cnt
))
6572 static void s2io_card_down(struct s2io_nic
* sp
)
6575 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6576 unsigned long flags
;
6577 register u64 val64
= 0;
6579 del_timer_sync(&sp
->alarm_timer
);
6580 /* If s2io_set_link task is executing, wait till it completes. */
6581 while (test_and_set_bit(0, &(sp
->link_state
))) {
6584 atomic_set(&sp
->card_state
, CARD_DOWN
);
6586 /* disable Tx and Rx traffic on the NIC */
6592 tasklet_kill(&sp
->task
);
6594 /* Check if the device is Quiescent and then Reset the NIC */
6596 /* As per the HW requirement we need to replenish the
6597 * receive buffer to avoid the ring bump. Since there is
6598 * no intention of processing the Rx frame at this pointwe are
6599 * just settting the ownership bit of rxd in Each Rx
6600 * ring to HW and set the appropriate buffer size
6601 * based on the ring mode
6603 rxd_owner_bit_reset(sp
);
6605 val64
= readq(&bar0
->adapter_status
);
6606 if (verify_xena_quiescence(sp
)) {
6607 if(verify_pcc_quiescent(sp
, sp
->device_enabled_once
))
6615 "s2io_close:Device not Quiescent ");
6616 DBG_PRINT(ERR_DBG
, "adaper status reads 0x%llx\n",
6617 (unsigned long long) val64
);
6623 spin_lock_irqsave(&sp
->tx_lock
, flags
);
6624 /* Free all Tx buffers */
6625 free_tx_buffers(sp
);
6626 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
6628 /* Free all Rx buffers */
6629 spin_lock_irqsave(&sp
->rx_lock
, flags
);
6630 free_rx_buffers(sp
);
6631 spin_unlock_irqrestore(&sp
->rx_lock
, flags
);
6633 clear_bit(0, &(sp
->link_state
));
6636 static int s2io_card_up(struct s2io_nic
* sp
)
6639 struct mac_info
*mac_control
;
6640 struct config_param
*config
;
6641 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
6644 /* Initialize the H/W I/O registers */
6645 if (init_nic(sp
) != 0) {
6646 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
6653 * Initializing the Rx buffers. For now we are considering only 1
6654 * Rx ring and initializing buffers into 30 Rx blocks
6656 mac_control
= &sp
->mac_control
;
6657 config
= &sp
->config
;
6659 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6660 if ((ret
= fill_rx_buffers(sp
, i
))) {
6661 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
6664 free_rx_buffers(sp
);
6667 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
6668 atomic_read(&sp
->rx_bufs_left
[i
]));
6670 /* Maintain the state prior to the open */
6671 if (sp
->promisc_flg
)
6672 sp
->promisc_flg
= 0;
6673 if (sp
->m_cast_flg
) {
6675 sp
->all_multi_pos
= 0;
6678 /* Setting its receive mode */
6679 s2io_set_multicast(dev
);
6682 /* Initialize max aggregatable pkts per session based on MTU */
6683 sp
->lro_max_aggr_per_sess
= ((1<<16) - 1) / dev
->mtu
;
6684 /* Check if we can use(if specified) user provided value */
6685 if (lro_max_pkts
< sp
->lro_max_aggr_per_sess
)
6686 sp
->lro_max_aggr_per_sess
= lro_max_pkts
;
6689 /* Enable Rx Traffic and interrupts on the NIC */
6690 if (start_nic(sp
)) {
6691 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
6693 free_rx_buffers(sp
);
6697 /* Add interrupt service routine */
6698 if (s2io_add_isr(sp
) != 0) {
6699 if (sp
->intr_type
== MSI_X
)
6702 free_rx_buffers(sp
);
6706 S2IO_TIMER_CONF(sp
->alarm_timer
, s2io_alarm_handle
, sp
, (HZ
/2));
6708 /* Enable tasklet for the device */
6709 tasklet_init(&sp
->task
, s2io_tasklet
, (unsigned long) dev
);
6711 /* Enable select interrupts */
6712 if (sp
->intr_type
!= INTA
)
6713 en_dis_able_nic_intrs(sp
, ENA_ALL_INTRS
, DISABLE_INTRS
);
6715 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
6716 interruptible
|= TX_PIC_INTR
| RX_PIC_INTR
;
6717 interruptible
|= TX_MAC_INTR
| RX_MAC_INTR
;
6718 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
6722 atomic_set(&sp
->card_state
, CARD_UP
);
6727 * s2io_restart_nic - Resets the NIC.
6728 * @data : long pointer to the device private structure
6730 * This function is scheduled to be run by the s2io_tx_watchdog
6731 * function after 0.5 secs to reset the NIC. The idea is to reduce
6732 * the run time of the watch dog routine which is run holding a
6736 static void s2io_restart_nic(struct work_struct
*work
)
6738 struct s2io_nic
*sp
= container_of(work
, struct s2io_nic
, rst_timer_task
);
6739 struct net_device
*dev
= sp
->dev
;
6743 if (!netif_running(dev
))
6747 if (s2io_card_up(sp
)) {
6748 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6751 netif_wake_queue(dev
);
6752 DBG_PRINT(ERR_DBG
, "%s: was reset by Tx watchdog timer\n",
6759 * s2io_tx_watchdog - Watchdog for transmit side.
6760 * @dev : Pointer to net device structure
6762 * This function is triggered if the Tx Queue is stopped
6763 * for a pre-defined amount of time when the Interface is still up.
6764 * If the Interface is jammed in such a situation, the hardware is
6765 * reset (by s2io_close) and restarted again (by s2io_open) to
6766 * overcome any problem that might have been caused in the hardware.
6771 static void s2io_tx_watchdog(struct net_device
*dev
)
6773 struct s2io_nic
*sp
= dev
->priv
;
6775 if (netif_carrier_ok(dev
)) {
6776 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
++;
6777 schedule_work(&sp
->rst_timer_task
);
6778 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
6783 * rx_osm_handler - To perform some OS related operations on SKB.
6784 * @sp: private member of the device structure,pointer to s2io_nic structure.
6785 * @skb : the socket buffer pointer.
6786 * @len : length of the packet
6787 * @cksum : FCS checksum of the frame.
6788 * @ring_no : the ring from which this RxD was extracted.
6790 * This function is called by the Rx interrupt serivce routine to perform
6791 * some OS related operations on the SKB before passing it to the upper
6792 * layers. It mainly checks if the checksum is OK, if so adds it to the
6793 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6794 * to the upper layer. If the checksum is wrong, it increments the Rx
6795 * packet error count, frees the SKB and returns error.
6797 * SUCCESS on success and -1 on failure.
6799 static int rx_osm_handler(struct ring_info
*ring_data
, struct RxD_t
* rxdp
)
6801 struct s2io_nic
*sp
= ring_data
->nic
;
6802 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
6803 struct sk_buff
*skb
= (struct sk_buff
*)
6804 ((unsigned long) rxdp
->Host_Control
);
6805 int ring_no
= ring_data
->ring_no
;
6806 u16 l3_csum
, l4_csum
;
6807 unsigned long long err
= rxdp
->Control_1
& RXD_T_CODE
;
6814 /* Check for parity error */
6816 sp
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
6818 err_mask
= err
>> 48;
6821 sp
->mac_control
.stats_info
->sw_stat
.
6822 rx_parity_err_cnt
++;
6826 sp
->mac_control
.stats_info
->sw_stat
.
6831 sp
->mac_control
.stats_info
->sw_stat
.
6832 rx_parity_abort_cnt
++;
6836 sp
->mac_control
.stats_info
->sw_stat
.
6841 sp
->mac_control
.stats_info
->sw_stat
.
6846 sp
->mac_control
.stats_info
->sw_stat
.
6851 sp
->mac_control
.stats_info
->sw_stat
.
6852 rx_buf_size_err_cnt
++;
6856 sp
->mac_control
.stats_info
->sw_stat
.
6857 rx_rxd_corrupt_cnt
++;
6861 sp
->mac_control
.stats_info
->sw_stat
.
6866 * Drop the packet if bad transfer code. Exception being
6867 * 0x5, which could be due to unsupported IPv6 extension header.
6868 * In this case, we let stack handle the packet.
6869 * Note that in this case, since checksum will be incorrect,
6870 * stack will validate the same.
6872 if (err_mask
!= 0x5) {
6873 DBG_PRINT(ERR_DBG
, "%s: Rx error Value: 0x%x\n",
6874 dev
->name
, err_mask
);
6875 sp
->stats
.rx_crc_errors
++;
6876 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
6879 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
6880 rxdp
->Host_Control
= 0;
6885 /* Updating statistics */
6886 rxdp
->Host_Control
= 0;
6887 if (sp
->rxd_mode
== RXD_MODE_1
) {
6888 int len
= RXD_GET_BUFFER0_SIZE_1(rxdp
->Control_2
);
6890 sp
->stats
.rx_bytes
+= len
;
6893 } else if (sp
->rxd_mode
>= RXD_MODE_3A
) {
6894 int get_block
= ring_data
->rx_curr_get_info
.block_index
;
6895 int get_off
= ring_data
->rx_curr_get_info
.offset
;
6896 int buf0_len
= RXD_GET_BUFFER0_SIZE_3(rxdp
->Control_2
);
6897 int buf2_len
= RXD_GET_BUFFER2_SIZE_3(rxdp
->Control_2
);
6898 unsigned char *buff
= skb_push(skb
, buf0_len
);
6900 struct buffAdd
*ba
= &ring_data
->ba
[get_block
][get_off
];
6901 sp
->stats
.rx_bytes
+= buf0_len
+ buf2_len
;
6902 memcpy(buff
, ba
->ba_0
, buf0_len
);
6904 if (sp
->rxd_mode
== RXD_MODE_3A
) {
6905 int buf1_len
= RXD_GET_BUFFER1_SIZE_3(rxdp
->Control_2
);
6907 skb_put(skb
, buf1_len
);
6908 skb
->len
+= buf2_len
;
6909 skb
->data_len
+= buf2_len
;
6910 skb_put(skb_shinfo(skb
)->frag_list
, buf2_len
);
6911 sp
->stats
.rx_bytes
+= buf1_len
;
6914 skb_put(skb
, buf2_len
);
6917 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) && ((!sp
->lro
) ||
6918 (sp
->lro
&& (!(rxdp
->Control_1
& RXD_FRAME_IP_FRAG
)))) &&
6920 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
6921 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
6922 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
6924 * NIC verifies if the Checksum of the received
6925 * frame is Ok or not and accordingly returns
6926 * a flag in the RxD.
6928 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6934 ret
= s2io_club_tcp_session(skb
->data
, &tcp
,
6935 &tcp_len
, &lro
, rxdp
, sp
);
6937 case 3: /* Begin anew */
6940 case 1: /* Aggregate */
6942 lro_append_pkt(sp
, lro
,
6946 case 4: /* Flush session */
6948 lro_append_pkt(sp
, lro
,
6950 queue_rx_frame(lro
->parent
);
6951 clear_lro_session(lro
);
6952 sp
->mac_control
.stats_info
->
6953 sw_stat
.flush_max_pkts
++;
6956 case 2: /* Flush both */
6957 lro
->parent
->data_len
=
6959 sp
->mac_control
.stats_info
->
6960 sw_stat
.sending_both
++;
6961 queue_rx_frame(lro
->parent
);
6962 clear_lro_session(lro
);
6964 case 0: /* sessions exceeded */
6965 case -1: /* non-TCP or not
6969 * First pkt in session not
6970 * L3/L4 aggregatable
6975 "%s: Samadhana!!\n",
6982 * Packet with erroneous checksum, let the
6983 * upper layers deal with it.
6985 skb
->ip_summed
= CHECKSUM_NONE
;
6988 skb
->ip_summed
= CHECKSUM_NONE
;
6990 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
6992 skb
->protocol
= eth_type_trans(skb
, dev
);
6993 if ((sp
->vlgrp
&& RXD_GET_VLAN_TAG(rxdp
->Control_2
) &&
6995 /* Queueing the vlan frame to the upper layer */
6997 vlan_hwaccel_receive_skb(skb
, sp
->vlgrp
,
6998 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7000 vlan_hwaccel_rx(skb
, sp
->vlgrp
,
7001 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7004 netif_receive_skb(skb
);
7010 queue_rx_frame(skb
);
7012 dev
->last_rx
= jiffies
;
7014 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
7019 * s2io_link - stops/starts the Tx queue.
7020 * @sp : private member of the device structure, which is a pointer to the
7021 * s2io_nic structure.
7022 * @link : inidicates whether link is UP/DOWN.
7024 * This function stops/starts the Tx queue depending on whether the link
7025 * status of the NIC is is down or up. This is called by the Alarm
7026 * interrupt handler whenever a link change interrupt comes up.
7031 static void s2io_link(struct s2io_nic
* sp
, int link
)
7033 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
7035 if (link
!= sp
->last_link_state
) {
7036 if (link
== LINK_DOWN
) {
7037 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
7038 netif_carrier_off(dev
);
7039 if(sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
)
7040 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
=
7041 jiffies
- sp
->start_time
;
7042 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
++;
7044 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
7045 if (sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
)
7046 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
=
7047 jiffies
- sp
->start_time
;
7048 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
++;
7049 netif_carrier_on(dev
);
7052 sp
->last_link_state
= link
;
7053 sp
->start_time
= jiffies
;
7057 * get_xena_rev_id - to identify revision ID of xena.
7058 * @pdev : PCI Dev structure
7060 * Function to identify the Revision ID of xena.
7062 * returns the revision ID of the device.
7065 static int get_xena_rev_id(struct pci_dev
*pdev
)
7069 ret
= pci_read_config_byte(pdev
, PCI_REVISION_ID
, (u8
*) & id
);
7074 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7075 * @sp : private member of the device structure, which is a pointer to the
7076 * s2io_nic structure.
7078 * This function initializes a few of the PCI and PCI-X configuration registers
7079 * with recommended values.
7084 static void s2io_init_pci(struct s2io_nic
* sp
)
7086 u16 pci_cmd
= 0, pcix_cmd
= 0;
7088 /* Enable Data Parity Error Recovery in PCI-X command register. */
7089 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7091 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7093 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7096 /* Set the PErr Response bit in PCI command register. */
7097 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7098 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
7099 (pci_cmd
| PCI_COMMAND_PARITY
));
7100 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7103 static int s2io_verify_parm(struct pci_dev
*pdev
, u8
*dev_intr_type
)
7105 if ( tx_fifo_num
> 8) {
7106 DBG_PRINT(ERR_DBG
, "s2io: Requested number of Tx fifos not "
7108 DBG_PRINT(ERR_DBG
, "s2io: Default to 8 Tx fifos\n");
7111 if ( rx_ring_num
> 8) {
7112 DBG_PRINT(ERR_DBG
, "s2io: Requested number of Rx rings not "
7114 DBG_PRINT(ERR_DBG
, "s2io: Default to 8 Rx rings\n");
7117 if (*dev_intr_type
!= INTA
)
7120 #ifndef CONFIG_PCI_MSI
7121 if (*dev_intr_type
!= INTA
) {
7122 DBG_PRINT(ERR_DBG
, "s2io: This kernel does not support"
7123 "MSI/MSI-X. Defaulting to INTA\n");
7124 *dev_intr_type
= INTA
;
7127 if (*dev_intr_type
> MSI_X
) {
7128 DBG_PRINT(ERR_DBG
, "s2io: Wrong intr_type requested. "
7129 "Defaulting to INTA\n");
7130 *dev_intr_type
= INTA
;
7133 if ((*dev_intr_type
== MSI_X
) &&
7134 ((pdev
->device
!= PCI_DEVICE_ID_HERC_WIN
) &&
7135 (pdev
->device
!= PCI_DEVICE_ID_HERC_UNI
))) {
7136 DBG_PRINT(ERR_DBG
, "s2io: Xframe I does not support MSI_X. "
7137 "Defaulting to INTA\n");
7138 *dev_intr_type
= INTA
;
7141 if (rx_ring_mode
> 3) {
7142 DBG_PRINT(ERR_DBG
, "s2io: Requested ring mode not supported\n");
7143 DBG_PRINT(ERR_DBG
, "s2io: Defaulting to 3-buffer mode\n");
7150 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7151 * or Traffic class respectively.
7152 * @nic: device peivate variable
7153 * Description: The function configures the receive steering to
7154 * desired receive ring.
7155 * Return Value: SUCCESS on success and
7156 * '-1' on failure (endian settings incorrect).
7158 static int rts_ds_steer(struct s2io_nic
*nic
, u8 ds_codepoint
, u8 ring
)
7160 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
7161 register u64 val64
= 0;
7163 if (ds_codepoint
> 63)
7166 val64
= RTS_DS_MEM_DATA(ring
);
7167 writeq(val64
, &bar0
->rts_ds_mem_data
);
7169 val64
= RTS_DS_MEM_CTRL_WE
|
7170 RTS_DS_MEM_CTRL_STROBE_NEW_CMD
|
7171 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint
);
7173 writeq(val64
, &bar0
->rts_ds_mem_ctrl
);
7175 return wait_for_cmd_complete(&bar0
->rts_ds_mem_ctrl
,
7176 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED
,
7181 * s2io_init_nic - Initialization of the adapter .
7182 * @pdev : structure containing the PCI related information of the device.
7183 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7185 * The function initializes an adapter identified by the pci_dec structure.
7186 * All OS related initialization including memory and device structure and
7187 * initlaization of the device private variable is done. Also the swapper
7188 * control register is initialized to enable read and write into the I/O
7189 * registers of the device.
7191 * returns 0 on success and negative on failure.
7194 static int __devinit
7195 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
7197 struct s2io_nic
*sp
;
7198 struct net_device
*dev
;
7200 int dma_flag
= FALSE
;
7201 u32 mac_up
, mac_down
;
7202 u64 val64
= 0, tmp64
= 0;
7203 struct XENA_dev_config __iomem
*bar0
= NULL
;
7205 struct mac_info
*mac_control
;
7206 struct config_param
*config
;
7208 u8 dev_intr_type
= intr_type
;
7210 if ((ret
= s2io_verify_parm(pdev
, &dev_intr_type
)))
7213 if ((ret
= pci_enable_device(pdev
))) {
7215 "s2io_init_nic: pci_enable_device failed\n");
7219 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
7220 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 64bit DMA\n");
7222 if (pci_set_consistent_dma_mask
7223 (pdev
, DMA_64BIT_MASK
)) {
7225 "Unable to obtain 64bit DMA for \
7226 consistent allocations\n");
7227 pci_disable_device(pdev
);
7230 } else if (!pci_set_dma_mask(pdev
, DMA_32BIT_MASK
)) {
7231 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 32bit DMA\n");
7233 pci_disable_device(pdev
);
7236 if (dev_intr_type
!= MSI_X
) {
7237 if (pci_request_regions(pdev
, s2io_driver_name
)) {
7238 DBG_PRINT(ERR_DBG
, "Request Regions failed\n");
7239 pci_disable_device(pdev
);
7244 if (!(request_mem_region(pci_resource_start(pdev
, 0),
7245 pci_resource_len(pdev
, 0), s2io_driver_name
))) {
7246 DBG_PRINT(ERR_DBG
, "bar0 Request Regions failed\n");
7247 pci_disable_device(pdev
);
7250 if (!(request_mem_region(pci_resource_start(pdev
, 2),
7251 pci_resource_len(pdev
, 2), s2io_driver_name
))) {
7252 DBG_PRINT(ERR_DBG
, "bar1 Request Regions failed\n");
7253 release_mem_region(pci_resource_start(pdev
, 0),
7254 pci_resource_len(pdev
, 0));
7255 pci_disable_device(pdev
);
7260 dev
= alloc_etherdev(sizeof(struct s2io_nic
));
7262 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
7263 pci_disable_device(pdev
);
7264 pci_release_regions(pdev
);
7268 pci_set_master(pdev
);
7269 pci_set_drvdata(pdev
, dev
);
7270 SET_MODULE_OWNER(dev
);
7271 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7273 /* Private member variable initialized to s2io NIC structure */
7275 memset(sp
, 0, sizeof(struct s2io_nic
));
7278 sp
->high_dma_flag
= dma_flag
;
7279 sp
->device_enabled_once
= FALSE
;
7280 if (rx_ring_mode
== 1)
7281 sp
->rxd_mode
= RXD_MODE_1
;
7282 if (rx_ring_mode
== 2)
7283 sp
->rxd_mode
= RXD_MODE_3B
;
7284 if (rx_ring_mode
== 3)
7285 sp
->rxd_mode
= RXD_MODE_3A
;
7287 sp
->intr_type
= dev_intr_type
;
7289 if ((pdev
->device
== PCI_DEVICE_ID_HERC_WIN
) ||
7290 (pdev
->device
== PCI_DEVICE_ID_HERC_UNI
))
7291 sp
->device_type
= XFRAME_II_DEVICE
;
7293 sp
->device_type
= XFRAME_I_DEVICE
;
7297 /* Initialize some PCI/PCI-X fields of the NIC. */
7301 * Setting the device configuration parameters.
7302 * Most of these parameters can be specified by the user during
7303 * module insertion as they are module loadable parameters. If
7304 * these parameters are not not specified during load time, they
7305 * are initialized with default values.
7307 mac_control
= &sp
->mac_control
;
7308 config
= &sp
->config
;
7310 /* Tx side parameters. */
7311 config
->tx_fifo_num
= tx_fifo_num
;
7312 for (i
= 0; i
< MAX_TX_FIFOS
; i
++) {
7313 config
->tx_cfg
[i
].fifo_len
= tx_fifo_len
[i
];
7314 config
->tx_cfg
[i
].fifo_priority
= i
;
7317 /* mapping the QoS priority to the configured fifos */
7318 for (i
= 0; i
< MAX_TX_FIFOS
; i
++)
7319 config
->fifo_mapping
[i
] = fifo_map
[config
->tx_fifo_num
][i
];
7321 config
->tx_intr_type
= TXD_INT_TYPE_UTILZ
;
7322 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7323 config
->tx_cfg
[i
].f_no_snoop
=
7324 (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
7325 if (config
->tx_cfg
[i
].fifo_len
< 65) {
7326 config
->tx_intr_type
= TXD_INT_TYPE_PER_LIST
;
7330 /* + 2 because one Txd for skb->data and one Txd for UFO */
7331 config
->max_txds
= MAX_SKB_FRAGS
+ 2;
7333 /* Rx side parameters. */
7334 config
->rx_ring_num
= rx_ring_num
;
7335 for (i
= 0; i
< MAX_RX_RINGS
; i
++) {
7336 config
->rx_cfg
[i
].num_rxd
= rx_ring_sz
[i
] *
7337 (rxd_count
[sp
->rxd_mode
] + 1);
7338 config
->rx_cfg
[i
].ring_priority
= i
;
7341 for (i
= 0; i
< rx_ring_num
; i
++) {
7342 config
->rx_cfg
[i
].ring_org
= RING_ORG_BUFF1
;
7343 config
->rx_cfg
[i
].f_no_snoop
=
7344 (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
7347 /* Setting Mac Control parameters */
7348 mac_control
->rmac_pause_time
= rmac_pause_time
;
7349 mac_control
->mc_pause_threshold_q0q3
= mc_pause_threshold_q0q3
;
7350 mac_control
->mc_pause_threshold_q4q7
= mc_pause_threshold_q4q7
;
7353 /* Initialize Ring buffer parameters. */
7354 for (i
= 0; i
< config
->rx_ring_num
; i
++)
7355 atomic_set(&sp
->rx_bufs_left
[i
], 0);
7357 /* Initialize the number of ISRs currently running */
7358 atomic_set(&sp
->isr_cnt
, 0);
7360 /* initialize the shared memory used by the NIC and the host */
7361 if (init_shared_mem(sp
)) {
7362 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n",
7365 goto mem_alloc_failed
;
7368 sp
->bar0
= ioremap(pci_resource_start(pdev
, 0),
7369 pci_resource_len(pdev
, 0));
7371 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem1\n",
7374 goto bar0_remap_failed
;
7377 sp
->bar1
= ioremap(pci_resource_start(pdev
, 2),
7378 pci_resource_len(pdev
, 2));
7380 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem2\n",
7383 goto bar1_remap_failed
;
7386 dev
->irq
= pdev
->irq
;
7387 dev
->base_addr
= (unsigned long) sp
->bar0
;
7389 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7390 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
7391 mac_control
->tx_FIFO_start
[j
] = (struct TxFIFO_element __iomem
*)
7392 (sp
->bar1
+ (j
* 0x00020000));
7395 /* Driver entry points */
7396 dev
->open
= &s2io_open
;
7397 dev
->stop
= &s2io_close
;
7398 dev
->hard_start_xmit
= &s2io_xmit
;
7399 dev
->get_stats
= &s2io_get_stats
;
7400 dev
->set_multicast_list
= &s2io_set_multicast
;
7401 dev
->do_ioctl
= &s2io_ioctl
;
7402 dev
->change_mtu
= &s2io_change_mtu
;
7403 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
7404 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
7405 dev
->vlan_rx_register
= s2io_vlan_rx_register
;
7408 * will use eth_mac_addr() for dev->set_mac_address
7409 * mac address will be set every time dev->open() is called
7411 dev
->poll
= s2io_poll
;
7414 #ifdef CONFIG_NET_POLL_CONTROLLER
7415 dev
->poll_controller
= s2io_netpoll
;
7418 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
7419 if (sp
->high_dma_flag
== TRUE
)
7420 dev
->features
|= NETIF_F_HIGHDMA
;
7421 dev
->features
|= NETIF_F_TSO
;
7422 dev
->features
|= NETIF_F_TSO6
;
7423 if ((sp
->device_type
& XFRAME_II_DEVICE
) && (ufo
)) {
7424 dev
->features
|= NETIF_F_UFO
;
7425 dev
->features
|= NETIF_F_HW_CSUM
;
7428 dev
->tx_timeout
= &s2io_tx_watchdog
;
7429 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
7430 INIT_WORK(&sp
->rst_timer_task
, s2io_restart_nic
);
7431 INIT_WORK(&sp
->set_link_task
, s2io_set_link
);
7433 pci_save_state(sp
->pdev
);
7435 /* Setting swapper control on the NIC, for proper reset operation */
7436 if (s2io_set_swapper(sp
)) {
7437 DBG_PRINT(ERR_DBG
, "%s:swapper settings are wrong\n",
7440 goto set_swap_failed
;
7443 /* Verify if the Herc works on the slot its placed into */
7444 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7445 mode
= s2io_verify_pci_mode(sp
);
7447 DBG_PRINT(ERR_DBG
, "%s: ", __FUNCTION__
);
7448 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
7450 goto set_swap_failed
;
7454 /* Not needed for Herc */
7455 if (sp
->device_type
& XFRAME_I_DEVICE
) {
7457 * Fix for all "FFs" MAC address problems observed on
7460 fix_mac_address(sp
);
7465 * MAC address initialization.
7466 * For now only one mac address will be read and used.
7469 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
7470 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET
);
7471 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
7472 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
7473 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
, S2IO_BIT_RESET
);
7474 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
7475 mac_down
= (u32
) tmp64
;
7476 mac_up
= (u32
) (tmp64
>> 32);
7478 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_up
);
7479 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
7480 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
7481 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
7482 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
7483 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
7485 /* Set the factory defined MAC address initially */
7486 dev
->addr_len
= ETH_ALEN
;
7487 memcpy(dev
->dev_addr
, sp
->def_mac_addr
, ETH_ALEN
);
7489 /* reset Nic and bring it to known state */
7493 * Initialize the tasklet status and link state flags
7494 * and the card state parameter
7496 atomic_set(&(sp
->card_state
), 0);
7497 sp
->tasklet_status
= 0;
7500 /* Initialize spinlocks */
7501 spin_lock_init(&sp
->tx_lock
);
7504 spin_lock_init(&sp
->put_lock
);
7505 spin_lock_init(&sp
->rx_lock
);
7508 * SXE-002: Configure link and activity LED to init state
7511 subid
= sp
->pdev
->subsystem_device
;
7512 if ((subid
& 0xFF) >= 0x07) {
7513 val64
= readq(&bar0
->gpio_control
);
7514 val64
|= 0x0000800000000000ULL
;
7515 writeq(val64
, &bar0
->gpio_control
);
7516 val64
= 0x0411040400000000ULL
;
7517 writeq(val64
, (void __iomem
*) bar0
+ 0x2700);
7518 val64
= readq(&bar0
->gpio_control
);
7521 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
7523 if (register_netdev(dev
)) {
7524 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
7526 goto register_failed
;
7529 DBG_PRINT(ERR_DBG
, "Copyright(c) 2002-2007 Neterion Inc.\n");
7530 DBG_PRINT(ERR_DBG
, "%s: Neterion %s (rev %d)\n",dev
->name
,
7531 sp
->product_name
, get_xena_rev_id(sp
->pdev
));
7532 DBG_PRINT(ERR_DBG
, "%s: Driver version %s\n", dev
->name
,
7533 s2io_driver_version
);
7534 DBG_PRINT(ERR_DBG
, "%s: MAC ADDR: "
7535 "%02x:%02x:%02x:%02x:%02x:%02x", dev
->name
,
7536 sp
->def_mac_addr
[0].mac_addr
[0],
7537 sp
->def_mac_addr
[0].mac_addr
[1],
7538 sp
->def_mac_addr
[0].mac_addr
[2],
7539 sp
->def_mac_addr
[0].mac_addr
[3],
7540 sp
->def_mac_addr
[0].mac_addr
[4],
7541 sp
->def_mac_addr
[0].mac_addr
[5]);
7542 DBG_PRINT(ERR_DBG
, "SERIAL NUMBER: %s\n", sp
->serial_num
);
7543 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7544 mode
= s2io_print_pci_mode(sp
);
7546 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
7548 unregister_netdev(dev
);
7549 goto set_swap_failed
;
7552 switch(sp
->rxd_mode
) {
7554 DBG_PRINT(ERR_DBG
, "%s: 1-Buffer receive mode enabled\n",
7558 DBG_PRINT(ERR_DBG
, "%s: 2-Buffer receive mode enabled\n",
7562 DBG_PRINT(ERR_DBG
, "%s: 3-Buffer receive mode enabled\n",
7568 DBG_PRINT(ERR_DBG
, "%s: NAPI enabled\n", dev
->name
);
7569 switch(sp
->intr_type
) {
7571 DBG_PRINT(ERR_DBG
, "%s: Interrupt type INTA\n", dev
->name
);
7574 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI\n", dev
->name
);
7577 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI-X\n", dev
->name
);
7581 DBG_PRINT(ERR_DBG
, "%s: Large receive offload enabled\n",
7584 DBG_PRINT(ERR_DBG
, "%s: UDP Fragmentation Offload(UFO)"
7585 " enabled\n", dev
->name
);
7586 /* Initialize device name */
7587 sprintf(sp
->name
, "%s Neterion %s", dev
->name
, sp
->product_name
);
7589 /* Initialize bimodal Interrupts */
7590 sp
->config
.bimodal
= bimodal
;
7591 if (!(sp
->device_type
& XFRAME_II_DEVICE
) && bimodal
) {
7592 sp
->config
.bimodal
= 0;
7593 DBG_PRINT(ERR_DBG
,"%s:Bimodal intr not supported by Xframe I\n",
7598 * Make Link state as off at this point, when the Link change
7599 * interrupt comes the state will be automatically changed to
7602 netif_carrier_off(dev
);
7613 free_shared_mem(sp
);
7614 pci_disable_device(pdev
);
7615 if (dev_intr_type
!= MSI_X
)
7616 pci_release_regions(pdev
);
7618 release_mem_region(pci_resource_start(pdev
, 0),
7619 pci_resource_len(pdev
, 0));
7620 release_mem_region(pci_resource_start(pdev
, 2),
7621 pci_resource_len(pdev
, 2));
7623 pci_set_drvdata(pdev
, NULL
);
7630 * s2io_rem_nic - Free the PCI device
7631 * @pdev: structure containing the PCI related information of the device.
7632 * Description: This function is called by the Pci subsystem to release a
7633 * PCI device and free up all resource held up by the device. This could
7634 * be in response to a Hot plug event or when the driver is to be removed
7638 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
7640 struct net_device
*dev
=
7641 (struct net_device
*) pci_get_drvdata(pdev
);
7642 struct s2io_nic
*sp
;
7645 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
7649 flush_scheduled_work();
7652 unregister_netdev(dev
);
7654 free_shared_mem(sp
);
7657 if (sp
->intr_type
!= MSI_X
)
7658 pci_release_regions(pdev
);
7660 release_mem_region(pci_resource_start(pdev
, 0),
7661 pci_resource_len(pdev
, 0));
7662 release_mem_region(pci_resource_start(pdev
, 2),
7663 pci_resource_len(pdev
, 2));
7665 pci_set_drvdata(pdev
, NULL
);
7667 pci_disable_device(pdev
);
7671 * s2io_starter - Entry point for the driver
7672 * Description: This function is the entry point for the driver. It verifies
7673 * the module loadable parameters and initializes PCI configuration space.
7676 int __init
s2io_starter(void)
7678 return pci_register_driver(&s2io_driver
);
7682 * s2io_closer - Cleanup routine for the driver
7683 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7686 static __exit
void s2io_closer(void)
7688 pci_unregister_driver(&s2io_driver
);
7689 DBG_PRINT(INIT_DBG
, "cleanup done\n");
7692 module_init(s2io_starter
);
7693 module_exit(s2io_closer
);
7695 static int check_L2_lro_capable(u8
*buffer
, struct iphdr
**ip
,
7696 struct tcphdr
**tcp
, struct RxD_t
*rxdp
)
7699 u8 l2_type
= (u8
)((rxdp
->Control_1
>> 37) & 0x7), ip_len
;
7701 if (!(rxdp
->Control_1
& RXD_FRAME_PROTO_TCP
)) {
7702 DBG_PRINT(INIT_DBG
,"%s: Non-TCP frames not supported for LRO\n",
7708 * By default the VLAN field in the MAC is stripped by the card, if this
7709 * feature is turned off in rx_pa_cfg register, then the ip_off field
7710 * has to be shifted by a further 2 bytes
7713 case 0: /* DIX type */
7714 case 4: /* DIX type with VLAN */
7715 ip_off
= HEADER_ETHERNET_II_802_3_SIZE
;
7717 /* LLC, SNAP etc are considered non-mergeable */
7722 *ip
= (struct iphdr
*)((u8
*)buffer
+ ip_off
);
7723 ip_len
= (u8
)((*ip
)->ihl
);
7725 *tcp
= (struct tcphdr
*)((unsigned long)*ip
+ ip_len
);
7730 static int check_for_socket_match(struct lro
*lro
, struct iphdr
*ip
,
7733 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7734 if ((lro
->iph
->saddr
!= ip
->saddr
) || (lro
->iph
->daddr
!= ip
->daddr
) ||
7735 (lro
->tcph
->source
!= tcp
->source
) || (lro
->tcph
->dest
!= tcp
->dest
))
7740 static inline int get_l4_pyld_length(struct iphdr
*ip
, struct tcphdr
*tcp
)
7742 return(ntohs(ip
->tot_len
) - (ip
->ihl
<< 2) - (tcp
->doff
<< 2));
7745 static void initiate_new_session(struct lro
*lro
, u8
*l2h
,
7746 struct iphdr
*ip
, struct tcphdr
*tcp
, u32 tcp_pyld_len
)
7748 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7752 lro
->tcp_next_seq
= tcp_pyld_len
+ ntohl(tcp
->seq
);
7753 lro
->tcp_ack
= ntohl(tcp
->ack_seq
);
7755 lro
->total_len
= ntohs(ip
->tot_len
);
7758 * check if we saw TCP timestamp. Other consistency checks have
7759 * already been done.
7761 if (tcp
->doff
== 8) {
7763 ptr
= (u32
*)(tcp
+1);
7765 lro
->cur_tsval
= *(ptr
+1);
7766 lro
->cur_tsecr
= *(ptr
+2);
7771 static void update_L3L4_header(struct s2io_nic
*sp
, struct lro
*lro
)
7773 struct iphdr
*ip
= lro
->iph
;
7774 struct tcphdr
*tcp
= lro
->tcph
;
7776 struct stat_block
*statinfo
= sp
->mac_control
.stats_info
;
7777 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7779 /* Update L3 header */
7780 ip
->tot_len
= htons(lro
->total_len
);
7782 nchk
= ip_fast_csum((u8
*)lro
->iph
, ip
->ihl
);
7785 /* Update L4 header */
7786 tcp
->ack_seq
= lro
->tcp_ack
;
7787 tcp
->window
= lro
->window
;
7789 /* Update tsecr field if this session has timestamps enabled */
7791 u32
*ptr
= (u32
*)(tcp
+ 1);
7792 *(ptr
+2) = lro
->cur_tsecr
;
7795 /* Update counters required for calculation of
7796 * average no. of packets aggregated.
7798 statinfo
->sw_stat
.sum_avg_pkts_aggregated
+= lro
->sg_num
;
7799 statinfo
->sw_stat
.num_aggregations
++;
7802 static void aggregate_new_rx(struct lro
*lro
, struct iphdr
*ip
,
7803 struct tcphdr
*tcp
, u32 l4_pyld
)
7805 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7806 lro
->total_len
+= l4_pyld
;
7807 lro
->frags_len
+= l4_pyld
;
7808 lro
->tcp_next_seq
+= l4_pyld
;
7811 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7812 lro
->tcp_ack
= tcp
->ack_seq
;
7813 lro
->window
= tcp
->window
;
7817 /* Update tsecr and tsval from this packet */
7818 ptr
= (u32
*) (tcp
+ 1);
7819 lro
->cur_tsval
= *(ptr
+ 1);
7820 lro
->cur_tsecr
= *(ptr
+ 2);
7824 static int verify_l3_l4_lro_capable(struct lro
*l_lro
, struct iphdr
*ip
,
7825 struct tcphdr
*tcp
, u32 tcp_pyld_len
)
7829 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7831 if (!tcp_pyld_len
) {
7832 /* Runt frame or a pure ack */
7836 if (ip
->ihl
!= 5) /* IP has options */
7839 /* If we see CE codepoint in IP header, packet is not mergeable */
7840 if (INET_ECN_is_ce(ipv4_get_dsfield(ip
)))
7843 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7844 if (tcp
->urg
|| tcp
->psh
|| tcp
->rst
|| tcp
->syn
|| tcp
->fin
||
7845 tcp
->ece
|| tcp
->cwr
|| !tcp
->ack
) {
7847 * Currently recognize only the ack control word and
7848 * any other control field being set would result in
7849 * flushing the LRO session
7855 * Allow only one TCP timestamp option. Don't aggregate if
7856 * any other options are detected.
7858 if (tcp
->doff
!= 5 && tcp
->doff
!= 8)
7861 if (tcp
->doff
== 8) {
7862 ptr
= (u8
*)(tcp
+ 1);
7863 while (*ptr
== TCPOPT_NOP
)
7865 if (*ptr
!= TCPOPT_TIMESTAMP
|| *(ptr
+1) != TCPOLEN_TIMESTAMP
)
7868 /* Ensure timestamp value increases monotonically */
7870 if (l_lro
->cur_tsval
> *((u32
*)(ptr
+2)))
7873 /* timestamp echo reply should be non-zero */
7874 if (*((u32
*)(ptr
+6)) == 0)
7882 s2io_club_tcp_session(u8
*buffer
, u8
**tcp
, u32
*tcp_len
, struct lro
**lro
,
7883 struct RxD_t
*rxdp
, struct s2io_nic
*sp
)
7886 struct tcphdr
*tcph
;
7889 if (!(ret
= check_L2_lro_capable(buffer
, &ip
, (struct tcphdr
**)tcp
,
7891 DBG_PRINT(INFO_DBG
,"IP Saddr: %x Daddr: %x\n",
7892 ip
->saddr
, ip
->daddr
);
7897 tcph
= (struct tcphdr
*)*tcp
;
7898 *tcp_len
= get_l4_pyld_length(ip
, tcph
);
7899 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
7900 struct lro
*l_lro
= &sp
->lro0_n
[i
];
7901 if (l_lro
->in_use
) {
7902 if (check_for_socket_match(l_lro
, ip
, tcph
))
7904 /* Sock pair matched */
7907 if ((*lro
)->tcp_next_seq
!= ntohl(tcph
->seq
)) {
7908 DBG_PRINT(INFO_DBG
, "%s:Out of order. expected "
7909 "0x%x, actual 0x%x\n", __FUNCTION__
,
7910 (*lro
)->tcp_next_seq
,
7913 sp
->mac_control
.stats_info
->
7914 sw_stat
.outof_sequence_pkts
++;
7919 if (!verify_l3_l4_lro_capable(l_lro
, ip
, tcph
,*tcp_len
))
7920 ret
= 1; /* Aggregate */
7922 ret
= 2; /* Flush both */
7928 /* Before searching for available LRO objects,
7929 * check if the pkt is L3/L4 aggregatable. If not
7930 * don't create new LRO session. Just send this
7933 if (verify_l3_l4_lro_capable(NULL
, ip
, tcph
, *tcp_len
)) {
7937 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
7938 struct lro
*l_lro
= &sp
->lro0_n
[i
];
7939 if (!(l_lro
->in_use
)) {
7941 ret
= 3; /* Begin anew */
7947 if (ret
== 0) { /* sessions exceeded */
7948 DBG_PRINT(INFO_DBG
,"%s:All LRO sessions already in use\n",
7956 initiate_new_session(*lro
, buffer
, ip
, tcph
, *tcp_len
);
7959 update_L3L4_header(sp
, *lro
);
7962 aggregate_new_rx(*lro
, ip
, tcph
, *tcp_len
);
7963 if ((*lro
)->sg_num
== sp
->lro_max_aggr_per_sess
) {
7964 update_L3L4_header(sp
, *lro
);
7965 ret
= 4; /* Flush the LRO */
7969 DBG_PRINT(ERR_DBG
,"%s:Dont know, can't say!!\n",
7977 static void clear_lro_session(struct lro
*lro
)
7979 static u16 lro_struct_size
= sizeof(struct lro
);
7981 memset(lro
, 0, lro_struct_size
);
7984 static void queue_rx_frame(struct sk_buff
*skb
)
7986 struct net_device
*dev
= skb
->dev
;
7988 skb
->protocol
= eth_type_trans(skb
, dev
);
7990 netif_receive_skb(skb
);
7995 static void lro_append_pkt(struct s2io_nic
*sp
, struct lro
*lro
,
7996 struct sk_buff
*skb
,
7999 struct sk_buff
*first
= lro
->parent
;
8001 first
->len
+= tcp_len
;
8002 first
->data_len
= lro
->frags_len
;
8003 skb_pull(skb
, (skb
->len
- tcp_len
));
8004 if (skb_shinfo(first
)->frag_list
)
8005 lro
->last_frag
->next
= skb
;
8007 skb_shinfo(first
)->frag_list
= skb
;
8008 first
->truesize
+= skb
->truesize
;
8009 lro
->last_frag
= skb
;
8010 sp
->mac_control
.stats_info
->sw_stat
.clubbed_frms_cnt
++;