1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 ************************************************************************/
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/skbuff.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/stddef.h>
68 #include <linux/ioctl.h>
69 #include <linux/timex.h>
70 #include <linux/ethtool.h>
71 #include <linux/workqueue.h>
72 #include <linux/if_vlan.h>
74 #include <linux/tcp.h>
77 #include <asm/system.h>
78 #include <asm/uaccess.h>
80 #include <asm/div64.h>
85 #include "s2io-regs.h"
87 #define DRV_VERSION "2.0.23.1"
89 /* S2io Driver name & version. */
90 static char s2io_driver_name
[] = "Neterion";
91 static char s2io_driver_version
[] = DRV_VERSION
;
93 static int rxd_size
[4] = {32,48,48,64};
94 static int rxd_count
[4] = {127,85,85,63};
96 static inline int RXD_IS_UP2DT(struct RxD_t
*rxdp
)
100 ret
= ((!(rxdp
->Control_1
& RXD_OWN_XENA
)) &&
101 (GET_RXD_MARKER(rxdp
->Control_2
) != THE_RXD_MARK
));
107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
121 static inline int rx_buffer_level(struct s2io_nic
* sp
, int rxb_size
, int ring
)
123 struct mac_info
*mac_control
;
125 mac_control
= &sp
->mac_control
;
126 if (rxb_size
<= rxd_count
[sp
->rxd_mode
])
128 else if ((mac_control
->rings
[ring
].pkt_cnt
- rxb_size
) > 16)
133 /* Ethtool related variables and Macros. */
134 static char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
135 "Register test\t(offline)",
136 "Eeprom test\t(offline)",
137 "Link test\t(online)",
138 "RLDRAM test\t(offline)",
139 "BIST Test\t(offline)"
142 static char ethtool_xena_stats_keys
[][ETH_GSTRING_LEN
] = {
144 {"tmac_data_octets"},
148 {"tmac_pause_ctrl_frms"},
152 {"tmac_any_err_frms"},
153 {"tmac_ttl_less_fb_octets"},
154 {"tmac_vld_ip_octets"},
162 {"rmac_data_octets"},
163 {"rmac_fcs_err_frms"},
165 {"rmac_vld_mcst_frms"},
166 {"rmac_vld_bcst_frms"},
167 {"rmac_in_rng_len_err_frms"},
168 {"rmac_out_rng_len_err_frms"},
170 {"rmac_pause_ctrl_frms"},
171 {"rmac_unsup_ctrl_frms"},
173 {"rmac_accepted_ucst_frms"},
174 {"rmac_accepted_nucst_frms"},
175 {"rmac_discarded_frms"},
176 {"rmac_drop_events"},
177 {"rmac_ttl_less_fb_octets"},
179 {"rmac_usized_frms"},
180 {"rmac_osized_frms"},
182 {"rmac_jabber_frms"},
183 {"rmac_ttl_64_frms"},
184 {"rmac_ttl_65_127_frms"},
185 {"rmac_ttl_128_255_frms"},
186 {"rmac_ttl_256_511_frms"},
187 {"rmac_ttl_512_1023_frms"},
188 {"rmac_ttl_1024_1518_frms"},
196 {"rmac_err_drp_udp"},
197 {"rmac_xgmii_err_sym"},
215 {"rmac_xgmii_data_err_cnt"},
216 {"rmac_xgmii_ctrl_err_cnt"},
217 {"rmac_accepted_ip"},
221 {"new_rd_req_rtry_cnt"},
223 {"wr_rtry_rd_ack_cnt"},
226 {"new_wr_req_rtry_cnt"},
229 {"rd_rtry_wr_ack_cnt"},
239 static char ethtool_enhanced_stats_keys
[][ETH_GSTRING_LEN
] = {
240 {"rmac_ttl_1519_4095_frms"},
241 {"rmac_ttl_4096_8191_frms"},
242 {"rmac_ttl_8192_max_frms"},
243 {"rmac_ttl_gt_max_frms"},
244 {"rmac_osized_alt_frms"},
245 {"rmac_jabber_alt_frms"},
246 {"rmac_gt_max_alt_frms"},
248 {"rmac_len_discard"},
249 {"rmac_fcs_discard"},
252 {"rmac_red_discard"},
253 {"rmac_rts_discard"},
254 {"rmac_ingm_full_discard"},
258 static char ethtool_driver_stats_keys
[][ETH_GSTRING_LEN
] = {
259 {"\n DRIVER STATISTICS"},
260 {"single_bit_ecc_errs"},
261 {"double_bit_ecc_errs"},
267 ("alarm_transceiver_temp_high"),
268 ("alarm_transceiver_temp_low"),
269 ("alarm_laser_bias_current_high"),
270 ("alarm_laser_bias_current_low"),
271 ("alarm_laser_output_power_high"),
272 ("alarm_laser_output_power_low"),
273 ("warn_transceiver_temp_high"),
274 ("warn_transceiver_temp_low"),
275 ("warn_laser_bias_current_high"),
276 ("warn_laser_bias_current_low"),
277 ("warn_laser_output_power_high"),
278 ("warn_laser_output_power_low"),
279 ("lro_aggregated_pkts"),
280 ("lro_flush_both_count"),
281 ("lro_out_of_sequence_pkts"),
282 ("lro_flush_due_to_max_pkts"),
283 ("lro_avg_aggr_pkts"),
284 ("mem_alloc_fail_cnt"),
285 ("watchdog_timer_cnt"),
292 ("tx_tcode_buf_abort_cnt"),
293 ("tx_tcode_desc_abort_cnt"),
294 ("tx_tcode_parity_err_cnt"),
295 ("tx_tcode_link_loss_cnt"),
296 ("tx_tcode_list_proc_err_cnt"),
297 ("rx_tcode_parity_err_cnt"),
298 ("rx_tcode_abort_cnt"),
299 ("rx_tcode_parity_abort_cnt"),
300 ("rx_tcode_rda_fail_cnt"),
301 ("rx_tcode_unkn_prot_cnt"),
302 ("rx_tcode_fcs_err_cnt"),
303 ("rx_tcode_buf_size_err_cnt"),
304 ("rx_tcode_rxd_corrupt_cnt"),
305 ("rx_tcode_unkn_err_cnt")
308 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
309 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
311 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
313 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
314 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
316 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
317 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
319 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
320 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
322 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
323 init_timer(&timer); \
324 timer.function = handle; \
325 timer.data = (unsigned long) arg; \
326 mod_timer(&timer, (jiffies + exp)) \
329 static void s2io_vlan_rx_register(struct net_device
*dev
,
330 struct vlan_group
*grp
)
332 struct s2io_nic
*nic
= dev
->priv
;
335 spin_lock_irqsave(&nic
->tx_lock
, flags
);
337 spin_unlock_irqrestore(&nic
->tx_lock
, flags
);
340 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
341 static int vlan_strip_flag
;
344 * Constants to be programmed into the Xena's registers, to configure
349 static const u64 herc_act_dtx_cfg
[] = {
351 0x8000051536750000ULL
, 0x80000515367500E0ULL
,
353 0x8000051536750004ULL
, 0x80000515367500E4ULL
,
355 0x80010515003F0000ULL
, 0x80010515003F00E0ULL
,
357 0x80010515003F0004ULL
, 0x80010515003F00E4ULL
,
359 0x801205150D440000ULL
, 0x801205150D4400E0ULL
,
361 0x801205150D440004ULL
, 0x801205150D4400E4ULL
,
363 0x80020515F2100000ULL
, 0x80020515F21000E0ULL
,
365 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
370 static const u64 xena_dtx_cfg
[] = {
372 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
374 0x80000515D9350004ULL
, 0x80000515D93500E4ULL
,
376 0x8001051500000000ULL
, 0x80010515000000E0ULL
,
378 0x80010515001E0004ULL
, 0x80010515001E00E4ULL
,
380 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
382 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
387 * Constants for Fixing the MacAddress problem seen mostly on
390 static const u64 fix_mac
[] = {
391 0x0060000000000000ULL
, 0x0060600000000000ULL
,
392 0x0040600000000000ULL
, 0x0000600000000000ULL
,
393 0x0020600000000000ULL
, 0x0060600000000000ULL
,
394 0x0020600000000000ULL
, 0x0060600000000000ULL
,
395 0x0020600000000000ULL
, 0x0060600000000000ULL
,
396 0x0020600000000000ULL
, 0x0060600000000000ULL
,
397 0x0020600000000000ULL
, 0x0060600000000000ULL
,
398 0x0020600000000000ULL
, 0x0060600000000000ULL
,
399 0x0020600000000000ULL
, 0x0060600000000000ULL
,
400 0x0020600000000000ULL
, 0x0060600000000000ULL
,
401 0x0020600000000000ULL
, 0x0060600000000000ULL
,
402 0x0020600000000000ULL
, 0x0060600000000000ULL
,
403 0x0020600000000000ULL
, 0x0000600000000000ULL
,
404 0x0040600000000000ULL
, 0x0060600000000000ULL
,
408 MODULE_LICENSE("GPL");
409 MODULE_VERSION(DRV_VERSION
);
412 /* Module Loadable parameters. */
413 S2IO_PARM_INT(tx_fifo_num
, 1);
414 S2IO_PARM_INT(rx_ring_num
, 1);
417 S2IO_PARM_INT(rx_ring_mode
, 1);
418 S2IO_PARM_INT(use_continuous_tx_intrs
, 1);
419 S2IO_PARM_INT(rmac_pause_time
, 0x100);
420 S2IO_PARM_INT(mc_pause_threshold_q0q3
, 187);
421 S2IO_PARM_INT(mc_pause_threshold_q4q7
, 187);
422 S2IO_PARM_INT(shared_splits
, 0);
423 S2IO_PARM_INT(tmac_util_period
, 5);
424 S2IO_PARM_INT(rmac_util_period
, 5);
425 S2IO_PARM_INT(bimodal
, 0);
426 S2IO_PARM_INT(l3l4hdr_size
, 128);
427 /* Frequency of Rx desc syncs expressed as power of 2 */
428 S2IO_PARM_INT(rxsync_frequency
, 3);
429 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
430 S2IO_PARM_INT(intr_type
, 0);
431 /* Large receive offload feature */
432 S2IO_PARM_INT(lro
, 0);
433 /* Max pkts to be aggregated by LRO at one time. If not specified,
434 * aggregation happens until we hit max IP pkt size(64K)
436 S2IO_PARM_INT(lro_max_pkts
, 0xFFFF);
437 S2IO_PARM_INT(indicate_max_pkts
, 0);
439 S2IO_PARM_INT(napi
, 1);
440 S2IO_PARM_INT(ufo
, 0);
441 S2IO_PARM_INT(vlan_tag_strip
, NO_STRIP_IN_PROMISC
);
443 static unsigned int tx_fifo_len
[MAX_TX_FIFOS
] =
444 {DEFAULT_FIFO_0_LEN
, [1 ...(MAX_TX_FIFOS
- 1)] = DEFAULT_FIFO_1_7_LEN
};
445 static unsigned int rx_ring_sz
[MAX_RX_RINGS
] =
446 {[0 ...(MAX_RX_RINGS
- 1)] = SMALL_BLK_CNT
};
447 static unsigned int rts_frm_len
[MAX_RX_RINGS
] =
448 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
450 module_param_array(tx_fifo_len
, uint
, NULL
, 0);
451 module_param_array(rx_ring_sz
, uint
, NULL
, 0);
452 module_param_array(rts_frm_len
, uint
, NULL
, 0);
456 * This table lists all the devices that this driver supports.
458 static struct pci_device_id s2io_tbl
[] __devinitdata
= {
459 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
460 PCI_ANY_ID
, PCI_ANY_ID
},
461 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
462 PCI_ANY_ID
, PCI_ANY_ID
},
463 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_WIN
,
464 PCI_ANY_ID
, PCI_ANY_ID
},
465 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_UNI
,
466 PCI_ANY_ID
, PCI_ANY_ID
},
470 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
472 static struct pci_error_handlers s2io_err_handler
= {
473 .error_detected
= s2io_io_error_detected
,
474 .slot_reset
= s2io_io_slot_reset
,
475 .resume
= s2io_io_resume
,
478 static struct pci_driver s2io_driver
= {
480 .id_table
= s2io_tbl
,
481 .probe
= s2io_init_nic
,
482 .remove
= __devexit_p(s2io_rem_nic
),
483 .err_handler
= &s2io_err_handler
,
486 /* A simplifier macro used both by init and free shared_mem Fns(). */
487 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
490 * init_shared_mem - Allocation and Initialization of Memory
491 * @nic: Device private variable.
492 * Description: The function allocates all the memory areas shared
493 * between the NIC and the driver. This includes Tx descriptors,
494 * Rx descriptors and the statistics block.
497 static int init_shared_mem(struct s2io_nic
*nic
)
500 void *tmp_v_addr
, *tmp_v_addr_next
;
501 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
502 struct RxD_block
*pre_rxd_blk
= NULL
;
504 int lst_size
, lst_per_page
;
505 struct net_device
*dev
= nic
->dev
;
509 struct mac_info
*mac_control
;
510 struct config_param
*config
;
511 unsigned long long mem_allocated
= 0;
513 mac_control
= &nic
->mac_control
;
514 config
= &nic
->config
;
517 /* Allocation and initialization of TXDLs in FIOFs */
519 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
520 size
+= config
->tx_cfg
[i
].fifo_len
;
522 if (size
> MAX_AVAILABLE_TXDS
) {
523 DBG_PRINT(ERR_DBG
, "s2io: Requested TxDs too high, ");
524 DBG_PRINT(ERR_DBG
, "Requested: %d, max supported: 8192\n", size
);
528 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
529 lst_per_page
= PAGE_SIZE
/ lst_size
;
531 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
532 int fifo_len
= config
->tx_cfg
[i
].fifo_len
;
533 int list_holder_size
= fifo_len
* sizeof(struct list_info_hold
);
534 mac_control
->fifos
[i
].list_info
= kmalloc(list_holder_size
,
536 if (!mac_control
->fifos
[i
].list_info
) {
538 "Malloc failed for list_info\n");
541 mem_allocated
+= list_holder_size
;
542 memset(mac_control
->fifos
[i
].list_info
, 0, list_holder_size
);
544 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
545 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
547 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
548 mac_control
->fifos
[i
].tx_curr_put_info
.fifo_len
=
549 config
->tx_cfg
[i
].fifo_len
- 1;
550 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
551 mac_control
->fifos
[i
].tx_curr_get_info
.fifo_len
=
552 config
->tx_cfg
[i
].fifo_len
- 1;
553 mac_control
->fifos
[i
].fifo_no
= i
;
554 mac_control
->fifos
[i
].nic
= nic
;
555 mac_control
->fifos
[i
].max_txds
= MAX_SKB_FRAGS
+ 2;
557 for (j
= 0; j
< page_num
; j
++) {
561 tmp_v
= pci_alloc_consistent(nic
->pdev
,
565 "pci_alloc_consistent ");
566 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
569 /* If we got a zero DMA address(can happen on
570 * certain platforms like PPC), reallocate.
571 * Store virtual address of page we don't want,
575 mac_control
->zerodma_virt_addr
= tmp_v
;
577 "%s: Zero DMA address for TxDL. ", dev
->name
);
579 "Virtual address %p\n", tmp_v
);
580 tmp_v
= pci_alloc_consistent(nic
->pdev
,
584 "pci_alloc_consistent ");
585 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
588 mem_allocated
+= PAGE_SIZE
;
590 while (k
< lst_per_page
) {
591 int l
= (j
* lst_per_page
) + k
;
592 if (l
== config
->tx_cfg
[i
].fifo_len
)
594 mac_control
->fifos
[i
].list_info
[l
].list_virt_addr
=
595 tmp_v
+ (k
* lst_size
);
596 mac_control
->fifos
[i
].list_info
[l
].list_phy_addr
=
597 tmp_p
+ (k
* lst_size
);
603 nic
->ufo_in_band_v
= kcalloc(size
, sizeof(u64
), GFP_KERNEL
);
604 if (!nic
->ufo_in_band_v
)
606 mem_allocated
+= (size
* sizeof(u64
));
608 /* Allocation and initialization of RXDs in Rings */
610 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
611 if (config
->rx_cfg
[i
].num_rxd
%
612 (rxd_count
[nic
->rxd_mode
] + 1)) {
613 DBG_PRINT(ERR_DBG
, "%s: RxD count of ", dev
->name
);
614 DBG_PRINT(ERR_DBG
, "Ring%d is not a multiple of ",
616 DBG_PRINT(ERR_DBG
, "RxDs per Block");
619 size
+= config
->rx_cfg
[i
].num_rxd
;
620 mac_control
->rings
[i
].block_count
=
621 config
->rx_cfg
[i
].num_rxd
/
622 (rxd_count
[nic
->rxd_mode
] + 1 );
623 mac_control
->rings
[i
].pkt_cnt
= config
->rx_cfg
[i
].num_rxd
-
624 mac_control
->rings
[i
].block_count
;
626 if (nic
->rxd_mode
== RXD_MODE_1
)
627 size
= (size
* (sizeof(struct RxD1
)));
629 size
= (size
* (sizeof(struct RxD3
)));
631 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
632 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
633 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
634 mac_control
->rings
[i
].rx_curr_get_info
.ring_len
=
635 config
->rx_cfg
[i
].num_rxd
- 1;
636 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
637 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
638 mac_control
->rings
[i
].rx_curr_put_info
.ring_len
=
639 config
->rx_cfg
[i
].num_rxd
- 1;
640 mac_control
->rings
[i
].nic
= nic
;
641 mac_control
->rings
[i
].ring_no
= i
;
643 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
644 (rxd_count
[nic
->rxd_mode
] + 1);
645 /* Allocating all the Rx blocks */
646 for (j
= 0; j
< blk_cnt
; j
++) {
647 struct rx_block_info
*rx_blocks
;
650 rx_blocks
= &mac_control
->rings
[i
].rx_blocks
[j
];
651 size
= SIZE_OF_BLOCK
; //size is always page size
652 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
654 if (tmp_v_addr
== NULL
) {
656 * In case of failure, free_shared_mem()
657 * is called, which should free any
658 * memory that was alloced till the
661 rx_blocks
->block_virt_addr
= tmp_v_addr
;
664 mem_allocated
+= size
;
665 memset(tmp_v_addr
, 0, size
);
666 rx_blocks
->block_virt_addr
= tmp_v_addr
;
667 rx_blocks
->block_dma_addr
= tmp_p_addr
;
668 rx_blocks
->rxds
= kmalloc(sizeof(struct rxd_info
)*
669 rxd_count
[nic
->rxd_mode
],
671 if (!rx_blocks
->rxds
)
674 (sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
675 for (l
=0; l
<rxd_count
[nic
->rxd_mode
];l
++) {
676 rx_blocks
->rxds
[l
].virt_addr
=
677 rx_blocks
->block_virt_addr
+
678 (rxd_size
[nic
->rxd_mode
] * l
);
679 rx_blocks
->rxds
[l
].dma_addr
=
680 rx_blocks
->block_dma_addr
+
681 (rxd_size
[nic
->rxd_mode
] * l
);
684 /* Interlinking all Rx Blocks */
685 for (j
= 0; j
< blk_cnt
; j
++) {
687 mac_control
->rings
[i
].rx_blocks
[j
].block_virt_addr
;
689 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
690 blk_cnt
].block_virt_addr
;
692 mac_control
->rings
[i
].rx_blocks
[j
].block_dma_addr
;
694 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
695 blk_cnt
].block_dma_addr
;
697 pre_rxd_blk
= (struct RxD_block
*) tmp_v_addr
;
698 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
699 (unsigned long) tmp_v_addr_next
;
700 pre_rxd_blk
->pNext_RxD_Blk_physical
=
701 (u64
) tmp_p_addr_next
;
704 if (nic
->rxd_mode
>= RXD_MODE_3A
) {
706 * Allocation of Storages for buffer addresses in 2BUFF mode
707 * and the buffers as well.
709 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
710 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
711 (rxd_count
[nic
->rxd_mode
]+ 1);
712 mac_control
->rings
[i
].ba
=
713 kmalloc((sizeof(struct buffAdd
*) * blk_cnt
),
715 if (!mac_control
->rings
[i
].ba
)
717 mem_allocated
+=(sizeof(struct buffAdd
*) * blk_cnt
);
718 for (j
= 0; j
< blk_cnt
; j
++) {
720 mac_control
->rings
[i
].ba
[j
] =
721 kmalloc((sizeof(struct buffAdd
) *
722 (rxd_count
[nic
->rxd_mode
] + 1)),
724 if (!mac_control
->rings
[i
].ba
[j
])
726 mem_allocated
+= (sizeof(struct buffAdd
) * \
727 (rxd_count
[nic
->rxd_mode
] + 1));
728 while (k
!= rxd_count
[nic
->rxd_mode
]) {
729 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
731 ba
->ba_0_org
= (void *) kmalloc
732 (BUF0_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
736 (BUF0_LEN
+ ALIGN_SIZE
);
737 tmp
= (unsigned long)ba
->ba_0_org
;
739 tmp
&= ~((unsigned long) ALIGN_SIZE
);
740 ba
->ba_0
= (void *) tmp
;
742 ba
->ba_1_org
= (void *) kmalloc
743 (BUF1_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
747 += (BUF1_LEN
+ ALIGN_SIZE
);
748 tmp
= (unsigned long) ba
->ba_1_org
;
750 tmp
&= ~((unsigned long) ALIGN_SIZE
);
751 ba
->ba_1
= (void *) tmp
;
758 /* Allocation and initialization of Statistics block */
759 size
= sizeof(struct stat_block
);
760 mac_control
->stats_mem
= pci_alloc_consistent
761 (nic
->pdev
, size
, &mac_control
->stats_mem_phy
);
763 if (!mac_control
->stats_mem
) {
765 * In case of failure, free_shared_mem() is called, which
766 * should free any memory that was alloced till the
771 mem_allocated
+= size
;
772 mac_control
->stats_mem_sz
= size
;
774 tmp_v_addr
= mac_control
->stats_mem
;
775 mac_control
->stats_info
= (struct stat_block
*) tmp_v_addr
;
776 memset(tmp_v_addr
, 0, size
);
777 DBG_PRINT(INIT_DBG
, "%s:Ring Mem PHY: 0x%llx\n", dev
->name
,
778 (unsigned long long) tmp_p_addr
);
779 mac_control
->stats_info
->sw_stat
.mem_allocated
+= mem_allocated
;
784 * free_shared_mem - Free the allocated Memory
785 * @nic: Device private variable.
786 * Description: This function is to free all memory locations allocated by
787 * the init_shared_mem() function and return it to the kernel.
790 static void free_shared_mem(struct s2io_nic
*nic
)
792 int i
, j
, blk_cnt
, size
;
795 dma_addr_t tmp_p_addr
;
796 struct mac_info
*mac_control
;
797 struct config_param
*config
;
798 int lst_size
, lst_per_page
;
799 struct net_device
*dev
;
807 mac_control
= &nic
->mac_control
;
808 config
= &nic
->config
;
810 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
811 lst_per_page
= PAGE_SIZE
/ lst_size
;
813 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
814 ufo_size
+= config
->tx_cfg
[i
].fifo_len
;
815 page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
817 for (j
= 0; j
< page_num
; j
++) {
818 int mem_blks
= (j
* lst_per_page
);
819 if (!mac_control
->fifos
[i
].list_info
)
821 if (!mac_control
->fifos
[i
].list_info
[mem_blks
].
824 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
825 mac_control
->fifos
[i
].
828 mac_control
->fifos
[i
].
831 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
834 /* If we got a zero DMA address during allocation,
837 if (mac_control
->zerodma_virt_addr
) {
838 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
839 mac_control
->zerodma_virt_addr
,
842 "%s: Freeing TxDL with zero DMA addr. ",
844 DBG_PRINT(INIT_DBG
, "Virtual address %p\n",
845 mac_control
->zerodma_virt_addr
);
846 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
849 kfree(mac_control
->fifos
[i
].list_info
);
850 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
851 (nic
->config
.tx_cfg
[i
].fifo_len
*sizeof(struct list_info_hold
));
854 size
= SIZE_OF_BLOCK
;
855 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
856 blk_cnt
= mac_control
->rings
[i
].block_count
;
857 for (j
= 0; j
< blk_cnt
; j
++) {
858 tmp_v_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
860 tmp_p_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
862 if (tmp_v_addr
== NULL
)
864 pci_free_consistent(nic
->pdev
, size
,
865 tmp_v_addr
, tmp_p_addr
);
866 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= size
;
867 kfree(mac_control
->rings
[i
].rx_blocks
[j
].rxds
);
868 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
869 ( sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
873 if (nic
->rxd_mode
>= RXD_MODE_3A
) {
874 /* Freeing buffer storage addresses in 2BUFF mode. */
875 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
876 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
877 (rxd_count
[nic
->rxd_mode
] + 1);
878 for (j
= 0; j
< blk_cnt
; j
++) {
880 if (!mac_control
->rings
[i
].ba
[j
])
882 while (k
!= rxd_count
[nic
->rxd_mode
]) {
884 &mac_control
->rings
[i
].ba
[j
][k
];
886 nic
->mac_control
.stats_info
->sw_stat
.\
887 mem_freed
+= (BUF0_LEN
+ ALIGN_SIZE
);
889 nic
->mac_control
.stats_info
->sw_stat
.\
890 mem_freed
+= (BUF1_LEN
+ ALIGN_SIZE
);
893 kfree(mac_control
->rings
[i
].ba
[j
]);
894 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= (sizeof(struct buffAdd
) *
895 (rxd_count
[nic
->rxd_mode
] + 1));
897 kfree(mac_control
->rings
[i
].ba
);
898 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
899 (sizeof(struct buffAdd
*) * blk_cnt
);
903 if (mac_control
->stats_mem
) {
904 pci_free_consistent(nic
->pdev
,
905 mac_control
->stats_mem_sz
,
906 mac_control
->stats_mem
,
907 mac_control
->stats_mem_phy
);
908 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
909 mac_control
->stats_mem_sz
;
911 if (nic
->ufo_in_band_v
) {
912 kfree(nic
->ufo_in_band_v
);
913 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
914 += (ufo_size
* sizeof(u64
));
919 * s2io_verify_pci_mode -
922 static int s2io_verify_pci_mode(struct s2io_nic
*nic
)
924 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
925 register u64 val64
= 0;
928 val64
= readq(&bar0
->pci_mode
);
929 mode
= (u8
)GET_PCI_MODE(val64
);
931 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
932 return -1; /* Unknown PCI mode */
936 #define NEC_VENID 0x1033
937 #define NEC_DEVID 0x0125
938 static int s2io_on_nec_bridge(struct pci_dev
*s2io_pdev
)
940 struct pci_dev
*tdev
= NULL
;
941 while ((tdev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, tdev
)) != NULL
) {
942 if (tdev
->vendor
== NEC_VENID
&& tdev
->device
== NEC_DEVID
) {
943 if (tdev
->bus
== s2io_pdev
->bus
->parent
)
951 static int bus_speed
[8] = {33, 133, 133, 200, 266, 133, 200, 266};
953 * s2io_print_pci_mode -
955 static int s2io_print_pci_mode(struct s2io_nic
*nic
)
957 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
958 register u64 val64
= 0;
960 struct config_param
*config
= &nic
->config
;
962 val64
= readq(&bar0
->pci_mode
);
963 mode
= (u8
)GET_PCI_MODE(val64
);
965 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
966 return -1; /* Unknown PCI mode */
968 config
->bus_speed
= bus_speed
[mode
];
970 if (s2io_on_nec_bridge(nic
->pdev
)) {
971 DBG_PRINT(ERR_DBG
, "%s: Device is on PCI-E bus\n",
976 if (val64
& PCI_MODE_32_BITS
) {
977 DBG_PRINT(ERR_DBG
, "%s: Device is on 32 bit ", nic
->dev
->name
);
979 DBG_PRINT(ERR_DBG
, "%s: Device is on 64 bit ", nic
->dev
->name
);
983 case PCI_MODE_PCI_33
:
984 DBG_PRINT(ERR_DBG
, "33MHz PCI bus\n");
986 case PCI_MODE_PCI_66
:
987 DBG_PRINT(ERR_DBG
, "66MHz PCI bus\n");
989 case PCI_MODE_PCIX_M1_66
:
990 DBG_PRINT(ERR_DBG
, "66MHz PCIX(M1) bus\n");
992 case PCI_MODE_PCIX_M1_100
:
993 DBG_PRINT(ERR_DBG
, "100MHz PCIX(M1) bus\n");
995 case PCI_MODE_PCIX_M1_133
:
996 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M1) bus\n");
998 case PCI_MODE_PCIX_M2_66
:
999 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M2) bus\n");
1001 case PCI_MODE_PCIX_M2_100
:
1002 DBG_PRINT(ERR_DBG
, "200MHz PCIX(M2) bus\n");
1004 case PCI_MODE_PCIX_M2_133
:
1005 DBG_PRINT(ERR_DBG
, "266MHz PCIX(M2) bus\n");
1008 return -1; /* Unsupported bus speed */
1015 * init_nic - Initialization of hardware
1016 * @nic: device peivate variable
1017 * Description: The function sequentially configures every block
1018 * of the H/W from their reset values.
1019 * Return Value: SUCCESS on success and
1020 * '-1' on failure (endian settings incorrect).
1023 static int init_nic(struct s2io_nic
*nic
)
1025 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1026 struct net_device
*dev
= nic
->dev
;
1027 register u64 val64
= 0;
1031 struct mac_info
*mac_control
;
1032 struct config_param
*config
;
1034 unsigned long long mem_share
;
1037 mac_control
= &nic
->mac_control
;
1038 config
= &nic
->config
;
1040 /* to set the swapper controle on the card */
1041 if(s2io_set_swapper(nic
)) {
1042 DBG_PRINT(ERR_DBG
,"ERROR: Setting Swapper failed\n");
1047 * Herc requires EOI to be removed from reset before XGXS, so..
1049 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1050 val64
= 0xA500000000ULL
;
1051 writeq(val64
, &bar0
->sw_reset
);
1053 val64
= readq(&bar0
->sw_reset
);
1056 /* Remove XGXS from reset state */
1058 writeq(val64
, &bar0
->sw_reset
);
1060 val64
= readq(&bar0
->sw_reset
);
1062 /* Enable Receiving broadcasts */
1063 add
= &bar0
->mac_cfg
;
1064 val64
= readq(&bar0
->mac_cfg
);
1065 val64
|= MAC_RMAC_BCAST_ENABLE
;
1066 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1067 writel((u32
) val64
, add
);
1068 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1069 writel((u32
) (val64
>> 32), (add
+ 4));
1071 /* Read registers in all blocks */
1072 val64
= readq(&bar0
->mac_int_mask
);
1073 val64
= readq(&bar0
->mc_int_mask
);
1074 val64
= readq(&bar0
->xgxs_int_mask
);
1078 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
1080 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1081 while (herc_act_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1082 SPECIAL_REG_WRITE(herc_act_dtx_cfg
[dtx_cnt
],
1083 &bar0
->dtx_control
, UF
);
1085 msleep(1); /* Necessary!! */
1089 while (xena_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1090 SPECIAL_REG_WRITE(xena_dtx_cfg
[dtx_cnt
],
1091 &bar0
->dtx_control
, UF
);
1092 val64
= readq(&bar0
->dtx_control
);
1097 /* Tx DMA Initialization */
1099 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1100 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1101 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1102 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1105 for (i
= 0, j
= 0; i
< config
->tx_fifo_num
; i
++) {
1107 vBIT(config
->tx_cfg
[i
].fifo_len
- 1, ((i
* 32) + 19),
1108 13) | vBIT(config
->tx_cfg
[i
].fifo_priority
,
1111 if (i
== (config
->tx_fifo_num
- 1)) {
1118 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1122 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1126 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1130 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1136 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1137 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1139 if ((nic
->device_type
== XFRAME_I_DEVICE
) &&
1140 (get_xena_rev_id(nic
->pdev
) < 4))
1141 writeq(PCC_ENABLE_FOUR
, &bar0
->pcc_enable
);
1143 val64
= readq(&bar0
->tx_fifo_partition_0
);
1144 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
1145 &bar0
->tx_fifo_partition_0
, (unsigned long long) val64
);
1148 * Initialization of Tx_PA_CONFIG register to ignore packet
1149 * integrity checking.
1151 val64
= readq(&bar0
->tx_pa_cfg
);
1152 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
| TX_PA_CFG_IGNORE_SNAP_OUI
|
1153 TX_PA_CFG_IGNORE_LLC_CTRL
| TX_PA_CFG_IGNORE_L2_ERR
;
1154 writeq(val64
, &bar0
->tx_pa_cfg
);
1156 /* Rx DMA intialization. */
1158 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1160 vBIT(config
->rx_cfg
[i
].ring_priority
, (5 + (i
* 8)),
1163 writeq(val64
, &bar0
->rx_queue_priority
);
1166 * Allocating equal share of memory to all the
1170 if (nic
->device_type
& XFRAME_II_DEVICE
)
1175 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1178 mem_share
= (mem_size
/ config
->rx_ring_num
+
1179 mem_size
% config
->rx_ring_num
);
1180 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
1183 mem_share
= (mem_size
/ config
->rx_ring_num
);
1184 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
1187 mem_share
= (mem_size
/ config
->rx_ring_num
);
1188 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
1191 mem_share
= (mem_size
/ config
->rx_ring_num
);
1192 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
1195 mem_share
= (mem_size
/ config
->rx_ring_num
);
1196 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
1199 mem_share
= (mem_size
/ config
->rx_ring_num
);
1200 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
1203 mem_share
= (mem_size
/ config
->rx_ring_num
);
1204 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
1207 mem_share
= (mem_size
/ config
->rx_ring_num
);
1208 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
1212 writeq(val64
, &bar0
->rx_queue_cfg
);
1215 * Filling Tx round robin registers
1216 * as per the number of FIFOs
1218 switch (config
->tx_fifo_num
) {
1220 val64
= 0x0000000000000000ULL
;
1221 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1222 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1223 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1224 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1225 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1228 val64
= 0x0000010000010000ULL
;
1229 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1230 val64
= 0x0100000100000100ULL
;
1231 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1232 val64
= 0x0001000001000001ULL
;
1233 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1234 val64
= 0x0000010000010000ULL
;
1235 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1236 val64
= 0x0100000000000000ULL
;
1237 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1240 val64
= 0x0001000102000001ULL
;
1241 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1242 val64
= 0x0001020000010001ULL
;
1243 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1244 val64
= 0x0200000100010200ULL
;
1245 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1246 val64
= 0x0001000102000001ULL
;
1247 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1248 val64
= 0x0001020000000000ULL
;
1249 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1252 val64
= 0x0001020300010200ULL
;
1253 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1254 val64
= 0x0100000102030001ULL
;
1255 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1256 val64
= 0x0200010000010203ULL
;
1257 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1258 val64
= 0x0001020001000001ULL
;
1259 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1260 val64
= 0x0203000100000000ULL
;
1261 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1264 val64
= 0x0001000203000102ULL
;
1265 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1266 val64
= 0x0001020001030004ULL
;
1267 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1268 val64
= 0x0001000203000102ULL
;
1269 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1270 val64
= 0x0001020001030004ULL
;
1271 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1272 val64
= 0x0001000000000000ULL
;
1273 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1276 val64
= 0x0001020304000102ULL
;
1277 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1278 val64
= 0x0304050001020001ULL
;
1279 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1280 val64
= 0x0203000100000102ULL
;
1281 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1282 val64
= 0x0304000102030405ULL
;
1283 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1284 val64
= 0x0001000200000000ULL
;
1285 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1288 val64
= 0x0001020001020300ULL
;
1289 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1290 val64
= 0x0102030400010203ULL
;
1291 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1292 val64
= 0x0405060001020001ULL
;
1293 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1294 val64
= 0x0304050000010200ULL
;
1295 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1296 val64
= 0x0102030000000000ULL
;
1297 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1300 val64
= 0x0001020300040105ULL
;
1301 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1302 val64
= 0x0200030106000204ULL
;
1303 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1304 val64
= 0x0103000502010007ULL
;
1305 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1306 val64
= 0x0304010002060500ULL
;
1307 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1308 val64
= 0x0103020400000000ULL
;
1309 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1313 /* Enable all configured Tx FIFO partitions */
1314 val64
= readq(&bar0
->tx_fifo_partition_0
);
1315 val64
|= (TX_FIFO_PARTITION_EN
);
1316 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1318 /* Filling the Rx round robin registers as per the
1319 * number of Rings and steering based on QoS.
1321 switch (config
->rx_ring_num
) {
1323 val64
= 0x8080808080808080ULL
;
1324 writeq(val64
, &bar0
->rts_qos_steering
);
1327 val64
= 0x0000010000010000ULL
;
1328 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1329 val64
= 0x0100000100000100ULL
;
1330 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1331 val64
= 0x0001000001000001ULL
;
1332 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1333 val64
= 0x0000010000010000ULL
;
1334 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1335 val64
= 0x0100000000000000ULL
;
1336 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1338 val64
= 0x8080808040404040ULL
;
1339 writeq(val64
, &bar0
->rts_qos_steering
);
1342 val64
= 0x0001000102000001ULL
;
1343 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1344 val64
= 0x0001020000010001ULL
;
1345 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1346 val64
= 0x0200000100010200ULL
;
1347 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1348 val64
= 0x0001000102000001ULL
;
1349 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1350 val64
= 0x0001020000000000ULL
;
1351 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1353 val64
= 0x8080804040402020ULL
;
1354 writeq(val64
, &bar0
->rts_qos_steering
);
1357 val64
= 0x0001020300010200ULL
;
1358 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1359 val64
= 0x0100000102030001ULL
;
1360 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1361 val64
= 0x0200010000010203ULL
;
1362 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1363 val64
= 0x0001020001000001ULL
;
1364 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1365 val64
= 0x0203000100000000ULL
;
1366 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1368 val64
= 0x8080404020201010ULL
;
1369 writeq(val64
, &bar0
->rts_qos_steering
);
1372 val64
= 0x0001000203000102ULL
;
1373 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1374 val64
= 0x0001020001030004ULL
;
1375 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1376 val64
= 0x0001000203000102ULL
;
1377 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1378 val64
= 0x0001020001030004ULL
;
1379 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1380 val64
= 0x0001000000000000ULL
;
1381 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1383 val64
= 0x8080404020201008ULL
;
1384 writeq(val64
, &bar0
->rts_qos_steering
);
1387 val64
= 0x0001020304000102ULL
;
1388 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1389 val64
= 0x0304050001020001ULL
;
1390 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1391 val64
= 0x0203000100000102ULL
;
1392 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1393 val64
= 0x0304000102030405ULL
;
1394 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1395 val64
= 0x0001000200000000ULL
;
1396 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1398 val64
= 0x8080404020100804ULL
;
1399 writeq(val64
, &bar0
->rts_qos_steering
);
1402 val64
= 0x0001020001020300ULL
;
1403 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1404 val64
= 0x0102030400010203ULL
;
1405 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1406 val64
= 0x0405060001020001ULL
;
1407 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1408 val64
= 0x0304050000010200ULL
;
1409 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1410 val64
= 0x0102030000000000ULL
;
1411 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1413 val64
= 0x8080402010080402ULL
;
1414 writeq(val64
, &bar0
->rts_qos_steering
);
1417 val64
= 0x0001020300040105ULL
;
1418 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1419 val64
= 0x0200030106000204ULL
;
1420 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1421 val64
= 0x0103000502010007ULL
;
1422 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1423 val64
= 0x0304010002060500ULL
;
1424 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1425 val64
= 0x0103020400000000ULL
;
1426 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1428 val64
= 0x8040201008040201ULL
;
1429 writeq(val64
, &bar0
->rts_qos_steering
);
1435 for (i
= 0; i
< 8; i
++)
1436 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1438 /* Set the default rts frame length for the rings configured */
1439 val64
= MAC_RTS_FRM_LEN_SET(dev
->mtu
+22);
1440 for (i
= 0 ; i
< config
->rx_ring_num
; i
++)
1441 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1443 /* Set the frame length for the configured rings
1444 * desired by the user
1446 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1447 /* If rts_frm_len[i] == 0 then it is assumed that user not
1448 * specified frame length steering.
1449 * If the user provides the frame length then program
1450 * the rts_frm_len register for those values or else
1451 * leave it as it is.
1453 if (rts_frm_len
[i
] != 0) {
1454 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len
[i
]),
1455 &bar0
->rts_frm_len_n
[i
]);
1459 /* Disable differentiated services steering logic */
1460 for (i
= 0; i
< 64; i
++) {
1461 if (rts_ds_steer(nic
, i
, 0) == FAILURE
) {
1462 DBG_PRINT(ERR_DBG
, "%s: failed rts ds steering",
1464 DBG_PRINT(ERR_DBG
, "set on codepoint %d\n", i
);
1469 /* Program statistics memory */
1470 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
1472 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1473 val64
= STAT_BC(0x320);
1474 writeq(val64
, &bar0
->stat_byte_cnt
);
1478 * Initializing the sampling rate for the device to calculate the
1479 * bandwidth utilization.
1481 val64
= MAC_TX_LINK_UTIL_VAL(tmac_util_period
) |
1482 MAC_RX_LINK_UTIL_VAL(rmac_util_period
);
1483 writeq(val64
, &bar0
->mac_link_util
);
1487 * Initializing the Transmit and Receive Traffic Interrupt
1491 * TTI Initialization. Default Tx timer gets us about
1492 * 250 interrupts per sec. Continuous interrupts are enabled
1495 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1496 int count
= (nic
->config
.bus_speed
* 125)/2;
1497 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(count
);
1500 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1502 val64
|= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1503 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1504 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN
;
1505 if (use_continuous_tx_intrs
)
1506 val64
|= TTI_DATA1_MEM_TX_TIMER_CI_EN
;
1507 writeq(val64
, &bar0
->tti_data1_mem
);
1509 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1510 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1511 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1512 writeq(val64
, &bar0
->tti_data2_mem
);
1514 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1515 writeq(val64
, &bar0
->tti_command_mem
);
1518 * Once the operation completes, the Strobe bit of the command
1519 * register will be reset. We poll for this particular condition
1520 * We wait for a maximum of 500ms for the operation to complete,
1521 * if it's not complete by then we return error.
1525 val64
= readq(&bar0
->tti_command_mem
);
1526 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1530 DBG_PRINT(ERR_DBG
, "%s: TTI init Failed\n",
1538 if (nic
->config
.bimodal
) {
1540 for (k
= 0; k
< config
->rx_ring_num
; k
++) {
1541 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1542 val64
|= TTI_CMD_MEM_OFFSET(0x38+k
);
1543 writeq(val64
, &bar0
->tti_command_mem
);
1546 * Once the operation completes, the Strobe bit of the command
1547 * register will be reset. We poll for this particular condition
1548 * We wait for a maximum of 500ms for the operation to complete,
1549 * if it's not complete by then we return error.
1553 val64
= readq(&bar0
->tti_command_mem
);
1554 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1559 "%s: TTI init Failed\n",
1569 /* RTI Initialization */
1570 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1572 * Programmed to generate Apprx 500 Intrs per
1575 int count
= (nic
->config
.bus_speed
* 125)/4;
1576 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(count
);
1578 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1580 val64
|= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1581 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1582 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN
;
1584 writeq(val64
, &bar0
->rti_data1_mem
);
1586 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) |
1587 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1588 if (nic
->intr_type
== MSI_X
)
1589 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1590 RTI_DATA2_MEM_RX_UFC_D(0x40));
1592 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1593 RTI_DATA2_MEM_RX_UFC_D(0x80));
1594 writeq(val64
, &bar0
->rti_data2_mem
);
1596 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1597 val64
= RTI_CMD_MEM_WE
| RTI_CMD_MEM_STROBE_NEW_CMD
1598 | RTI_CMD_MEM_OFFSET(i
);
1599 writeq(val64
, &bar0
->rti_command_mem
);
1602 * Once the operation completes, the Strobe bit of the
1603 * command register will be reset. We poll for this
1604 * particular condition. We wait for a maximum of 500ms
1605 * for the operation to complete, if it's not complete
1606 * by then we return error.
1610 val64
= readq(&bar0
->rti_command_mem
);
1611 if (!(val64
& RTI_CMD_MEM_STROBE_NEW_CMD
)) {
1615 DBG_PRINT(ERR_DBG
, "%s: RTI init Failed\n",
1626 * Initializing proper values as Pause threshold into all
1627 * the 8 Queues on Rx side.
1629 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
1630 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
1632 /* Disable RMAC PAD STRIPPING */
1633 add
= &bar0
->mac_cfg
;
1634 val64
= readq(&bar0
->mac_cfg
);
1635 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
1636 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1637 writel((u32
) (val64
), add
);
1638 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1639 writel((u32
) (val64
>> 32), (add
+ 4));
1640 val64
= readq(&bar0
->mac_cfg
);
1642 /* Enable FCS stripping by adapter */
1643 add
= &bar0
->mac_cfg
;
1644 val64
= readq(&bar0
->mac_cfg
);
1645 val64
|= MAC_CFG_RMAC_STRIP_FCS
;
1646 if (nic
->device_type
== XFRAME_II_DEVICE
)
1647 writeq(val64
, &bar0
->mac_cfg
);
1649 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1650 writel((u32
) (val64
), add
);
1651 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1652 writel((u32
) (val64
>> 32), (add
+ 4));
1656 * Set the time value to be inserted in the pause frame
1657 * generated by xena.
1659 val64
= readq(&bar0
->rmac_pause_cfg
);
1660 val64
&= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1661 val64
|= RMAC_PAUSE_HG_PTIME(nic
->mac_control
.rmac_pause_time
);
1662 writeq(val64
, &bar0
->rmac_pause_cfg
);
1665 * Set the Threshold Limit for Generating the pause frame
1666 * If the amount of data in any Queue exceeds ratio of
1667 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1668 * pause frame is generated
1671 for (i
= 0; i
< 4; i
++) {
1673 (((u64
) 0xFF00 | nic
->mac_control
.
1674 mc_pause_threshold_q0q3
)
1677 writeq(val64
, &bar0
->mc_pause_thresh_q0q3
);
1680 for (i
= 0; i
< 4; i
++) {
1682 (((u64
) 0xFF00 | nic
->mac_control
.
1683 mc_pause_threshold_q4q7
)
1686 writeq(val64
, &bar0
->mc_pause_thresh_q4q7
);
1689 * TxDMA will stop Read request if the number of read split has
1690 * exceeded the limit pointed by shared_splits
1692 val64
= readq(&bar0
->pic_control
);
1693 val64
|= PIC_CNTL_SHARED_SPLITS(shared_splits
);
1694 writeq(val64
, &bar0
->pic_control
);
1696 if (nic
->config
.bus_speed
== 266) {
1697 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN
, &bar0
->txreqtimeout
);
1698 writeq(0x0, &bar0
->read_retry_delay
);
1699 writeq(0x0, &bar0
->write_retry_delay
);
1703 * Programming the Herc to split every write transaction
1704 * that does not start on an ADB to reduce disconnects.
1706 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1707 val64
= FAULT_BEHAVIOUR
| EXT_REQ_EN
|
1708 MISC_LINK_STABILITY_PRD(3);
1709 writeq(val64
, &bar0
->misc_control
);
1710 val64
= readq(&bar0
->pic_control2
);
1711 val64
&= ~(BIT(13)|BIT(14)|BIT(15));
1712 writeq(val64
, &bar0
->pic_control2
);
1714 if (strstr(nic
->product_name
, "CX4")) {
1715 val64
= TMAC_AVG_IPG(0x17);
1716 writeq(val64
, &bar0
->tmac_avg_ipg
);
1721 #define LINK_UP_DOWN_INTERRUPT 1
1722 #define MAC_RMAC_ERR_TIMER 2
1724 static int s2io_link_fault_indication(struct s2io_nic
*nic
)
1726 if (nic
->intr_type
!= INTA
)
1727 return MAC_RMAC_ERR_TIMER
;
1728 if (nic
->device_type
== XFRAME_II_DEVICE
)
1729 return LINK_UP_DOWN_INTERRUPT
;
1731 return MAC_RMAC_ERR_TIMER
;
1735 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1736 * @nic: device private variable,
1737 * @mask: A mask indicating which Intr block must be modified and,
1738 * @flag: A flag indicating whether to enable or disable the Intrs.
1739 * Description: This function will either disable or enable the interrupts
1740 * depending on the flag argument. The mask argument can be used to
1741 * enable/disable any Intr block.
1742 * Return Value: NONE.
1745 static void en_dis_able_nic_intrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
1747 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1748 register u64 val64
= 0, temp64
= 0;
1750 /* Top level interrupt classification */
1751 /* PIC Interrupts */
1752 if ((mask
& (TX_PIC_INTR
| RX_PIC_INTR
))) {
1753 /* Enable PIC Intrs in the general intr mask register */
1754 val64
= TXPIC_INT_M
;
1755 if (flag
== ENABLE_INTRS
) {
1756 temp64
= readq(&bar0
->general_int_mask
);
1757 temp64
&= ~((u64
) val64
);
1758 writeq(temp64
, &bar0
->general_int_mask
);
1760 * If Hercules adapter enable GPIO otherwise
1761 * disable all PCIX, Flash, MDIO, IIC and GPIO
1762 * interrupts for now.
1765 if (s2io_link_fault_indication(nic
) ==
1766 LINK_UP_DOWN_INTERRUPT
) {
1767 temp64
= readq(&bar0
->pic_int_mask
);
1768 temp64
&= ~((u64
) PIC_INT_GPIO
);
1769 writeq(temp64
, &bar0
->pic_int_mask
);
1770 temp64
= readq(&bar0
->gpio_int_mask
);
1771 temp64
&= ~((u64
) GPIO_INT_MASK_LINK_UP
);
1772 writeq(temp64
, &bar0
->gpio_int_mask
);
1774 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1777 * No MSI Support is available presently, so TTI and
1778 * RTI interrupts are also disabled.
1780 } else if (flag
== DISABLE_INTRS
) {
1782 * Disable PIC Intrs in the general
1783 * intr mask register
1785 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1786 temp64
= readq(&bar0
->general_int_mask
);
1788 writeq(val64
, &bar0
->general_int_mask
);
1792 /* MAC Interrupts */
1793 /* Enabling/Disabling MAC interrupts */
1794 if (mask
& (TX_MAC_INTR
| RX_MAC_INTR
)) {
1795 val64
= TXMAC_INT_M
| RXMAC_INT_M
;
1796 if (flag
== ENABLE_INTRS
) {
1797 temp64
= readq(&bar0
->general_int_mask
);
1798 temp64
&= ~((u64
) val64
);
1799 writeq(temp64
, &bar0
->general_int_mask
);
1801 * All MAC block error interrupts are disabled for now
1804 } else if (flag
== DISABLE_INTRS
) {
1806 * Disable MAC Intrs in the general intr mask register
1808 writeq(DISABLE_ALL_INTRS
, &bar0
->mac_int_mask
);
1809 writeq(DISABLE_ALL_INTRS
,
1810 &bar0
->mac_rmac_err_mask
);
1812 temp64
= readq(&bar0
->general_int_mask
);
1814 writeq(val64
, &bar0
->general_int_mask
);
1818 /* Tx traffic interrupts */
1819 if (mask
& TX_TRAFFIC_INTR
) {
1820 val64
= TXTRAFFIC_INT_M
;
1821 if (flag
== ENABLE_INTRS
) {
1822 temp64
= readq(&bar0
->general_int_mask
);
1823 temp64
&= ~((u64
) val64
);
1824 writeq(temp64
, &bar0
->general_int_mask
);
1826 * Enable all the Tx side interrupts
1827 * writing 0 Enables all 64 TX interrupt levels
1829 writeq(0x0, &bar0
->tx_traffic_mask
);
1830 } else if (flag
== DISABLE_INTRS
) {
1832 * Disable Tx Traffic Intrs in the general intr mask
1835 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
1836 temp64
= readq(&bar0
->general_int_mask
);
1838 writeq(val64
, &bar0
->general_int_mask
);
1842 /* Rx traffic interrupts */
1843 if (mask
& RX_TRAFFIC_INTR
) {
1844 val64
= RXTRAFFIC_INT_M
;
1845 if (flag
== ENABLE_INTRS
) {
1846 temp64
= readq(&bar0
->general_int_mask
);
1847 temp64
&= ~((u64
) val64
);
1848 writeq(temp64
, &bar0
->general_int_mask
);
1849 /* writing 0 Enables all 8 RX interrupt levels */
1850 writeq(0x0, &bar0
->rx_traffic_mask
);
1851 } else if (flag
== DISABLE_INTRS
) {
1853 * Disable Rx Traffic Intrs in the general intr mask
1856 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
1857 temp64
= readq(&bar0
->general_int_mask
);
1859 writeq(val64
, &bar0
->general_int_mask
);
1865 * verify_pcc_quiescent- Checks for PCC quiescent state
1866 * Return: 1 If PCC is quiescence
1867 * 0 If PCC is not quiescence
1869 static int verify_pcc_quiescent(struct s2io_nic
*sp
, int flag
)
1872 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1873 u64 val64
= readq(&bar0
->adapter_status
);
1875 herc
= (sp
->device_type
== XFRAME_II_DEVICE
);
1877 if (flag
== FALSE
) {
1878 if ((!herc
&& (get_xena_rev_id(sp
->pdev
) >= 4)) || herc
) {
1879 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
))
1882 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
1886 if ((!herc
&& (get_xena_rev_id(sp
->pdev
) >= 4)) || herc
) {
1887 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
1888 ADAPTER_STATUS_RMAC_PCC_IDLE
))
1891 if (((val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) ==
1892 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
1900 * verify_xena_quiescence - Checks whether the H/W is ready
1901 * Description: Returns whether the H/W is ready to go or not. Depending
1902 * on whether adapter enable bit was written or not the comparison
1903 * differs and the calling function passes the input argument flag to
1905 * Return: 1 If xena is quiescence
1906 * 0 If Xena is not quiescence
1909 static int verify_xena_quiescence(struct s2io_nic
*sp
)
1912 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1913 u64 val64
= readq(&bar0
->adapter_status
);
1914 mode
= s2io_verify_pci_mode(sp
);
1916 if (!(val64
& ADAPTER_STATUS_TDMA_READY
)) {
1917 DBG_PRINT(ERR_DBG
, "%s", "TDMA is not ready!");
1920 if (!(val64
& ADAPTER_STATUS_RDMA_READY
)) {
1921 DBG_PRINT(ERR_DBG
, "%s", "RDMA is not ready!");
1924 if (!(val64
& ADAPTER_STATUS_PFC_READY
)) {
1925 DBG_PRINT(ERR_DBG
, "%s", "PFC is not ready!");
1928 if (!(val64
& ADAPTER_STATUS_TMAC_BUF_EMPTY
)) {
1929 DBG_PRINT(ERR_DBG
, "%s", "TMAC BUF is not empty!");
1932 if (!(val64
& ADAPTER_STATUS_PIC_QUIESCENT
)) {
1933 DBG_PRINT(ERR_DBG
, "%s", "PIC is not QUIESCENT!");
1936 if (!(val64
& ADAPTER_STATUS_MC_DRAM_READY
)) {
1937 DBG_PRINT(ERR_DBG
, "%s", "MC_DRAM is not ready!");
1940 if (!(val64
& ADAPTER_STATUS_MC_QUEUES_READY
)) {
1941 DBG_PRINT(ERR_DBG
, "%s", "MC_QUEUES is not ready!");
1944 if (!(val64
& ADAPTER_STATUS_M_PLL_LOCK
)) {
1945 DBG_PRINT(ERR_DBG
, "%s", "M_PLL is not locked!");
1950 * In PCI 33 mode, the P_PLL is not used, and therefore,
1951 * the the P_PLL_LOCK bit in the adapter_status register will
1954 if (!(val64
& ADAPTER_STATUS_P_PLL_LOCK
) &&
1955 sp
->device_type
== XFRAME_II_DEVICE
&& mode
!=
1957 DBG_PRINT(ERR_DBG
, "%s", "P_PLL is not locked!");
1960 if (!((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1961 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
1962 DBG_PRINT(ERR_DBG
, "%s", "RC_PRC is not QUIESCENT!");
1969 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1970 * @sp: Pointer to device specifc structure
1972 * New procedure to clear mac address reading problems on Alpha platforms
1976 static void fix_mac_address(struct s2io_nic
* sp
)
1978 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1982 while (fix_mac
[i
] != END_SIGN
) {
1983 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
1985 val64
= readq(&bar0
->gpio_control
);
1990 * start_nic - Turns the device on
1991 * @nic : device private variable.
1993 * This function actually turns the device on. Before this function is
1994 * called,all Registers are configured from their reset states
1995 * and shared memory is allocated but the NIC is still quiescent. On
1996 * calling this function, the device interrupts are cleared and the NIC is
1997 * literally switched on by writing into the adapter control register.
1999 * SUCCESS on success and -1 on failure.
2002 static int start_nic(struct s2io_nic
*nic
)
2004 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2005 struct net_device
*dev
= nic
->dev
;
2006 register u64 val64
= 0;
2008 struct mac_info
*mac_control
;
2009 struct config_param
*config
;
2011 mac_control
= &nic
->mac_control
;
2012 config
= &nic
->config
;
2014 /* PRC Initialization and configuration */
2015 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2016 writeq((u64
) mac_control
->rings
[i
].rx_blocks
[0].block_dma_addr
,
2017 &bar0
->prc_rxd0_n
[i
]);
2019 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
2020 if (nic
->config
.bimodal
)
2021 val64
|= PRC_CTRL_BIMODAL_INTERRUPT
;
2022 if (nic
->rxd_mode
== RXD_MODE_1
)
2023 val64
|= PRC_CTRL_RC_ENABLED
;
2025 val64
|= PRC_CTRL_RC_ENABLED
| PRC_CTRL_RING_MODE_3
;
2026 if (nic
->device_type
== XFRAME_II_DEVICE
)
2027 val64
|= PRC_CTRL_GROUP_READS
;
2028 val64
&= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2029 val64
|= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2030 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
2033 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2034 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2035 val64
= readq(&bar0
->rx_pa_cfg
);
2036 val64
|= RX_PA_CFG_IGNORE_L2_ERR
;
2037 writeq(val64
, &bar0
->rx_pa_cfg
);
2040 if (vlan_tag_strip
== 0) {
2041 val64
= readq(&bar0
->rx_pa_cfg
);
2042 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
2043 writeq(val64
, &bar0
->rx_pa_cfg
);
2044 vlan_strip_flag
= 0;
2048 * Enabling MC-RLDRAM. After enabling the device, we timeout
2049 * for around 100ms, which is approximately the time required
2050 * for the device to be ready for operation.
2052 val64
= readq(&bar0
->mc_rldram_mrs
);
2053 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
2054 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
2055 val64
= readq(&bar0
->mc_rldram_mrs
);
2057 msleep(100); /* Delay by around 100 ms. */
2059 /* Enabling ECC Protection. */
2060 val64
= readq(&bar0
->adapter_control
);
2061 val64
&= ~ADAPTER_ECC_EN
;
2062 writeq(val64
, &bar0
->adapter_control
);
2065 * Clearing any possible Link state change interrupts that
2066 * could have popped up just before Enabling the card.
2068 val64
= readq(&bar0
->mac_rmac_err_reg
);
2070 writeq(val64
, &bar0
->mac_rmac_err_reg
);
2073 * Verify if the device is ready to be enabled, if so enable
2076 val64
= readq(&bar0
->adapter_status
);
2077 if (!verify_xena_quiescence(nic
)) {
2078 DBG_PRINT(ERR_DBG
, "%s: device is not ready, ", dev
->name
);
2079 DBG_PRINT(ERR_DBG
, "Adapter status reads: 0x%llx\n",
2080 (unsigned long long) val64
);
2085 * With some switches, link might be already up at this point.
2086 * Because of this weird behavior, when we enable laser,
2087 * we may not get link. We need to handle this. We cannot
2088 * figure out which switch is misbehaving. So we are forced to
2089 * make a global change.
2092 /* Enabling Laser. */
2093 val64
= readq(&bar0
->adapter_control
);
2094 val64
|= ADAPTER_EOI_TX_ON
;
2095 writeq(val64
, &bar0
->adapter_control
);
2097 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
2099 * Dont see link state interrupts initally on some switches,
2100 * so directly scheduling the link state task here.
2102 schedule_work(&nic
->set_link_task
);
2104 /* SXE-002: Initialize link and activity LED */
2105 subid
= nic
->pdev
->subsystem_device
;
2106 if (((subid
& 0xFF) >= 0x07) &&
2107 (nic
->device_type
== XFRAME_I_DEVICE
)) {
2108 val64
= readq(&bar0
->gpio_control
);
2109 val64
|= 0x0000800000000000ULL
;
2110 writeq(val64
, &bar0
->gpio_control
);
2111 val64
= 0x0411040400000000ULL
;
2112 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
2118 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2120 static struct sk_buff
*s2io_txdl_getskb(struct fifo_info
*fifo_data
, struct \
2121 TxD
*txdlp
, int get_off
)
2123 struct s2io_nic
*nic
= fifo_data
->nic
;
2124 struct sk_buff
*skb
;
2129 if (txds
->Host_Control
== (u64
)(long)nic
->ufo_in_band_v
) {
2130 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2131 txds
->Buffer_Pointer
, sizeof(u64
),
2136 skb
= (struct sk_buff
*) ((unsigned long)
2137 txds
->Host_Control
);
2139 memset(txdlp
, 0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2142 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2143 txds
->Buffer_Pointer
,
2144 skb
->len
- skb
->data_len
,
2146 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2149 for (j
= 0; j
< frg_cnt
; j
++, txds
++) {
2150 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
2151 if (!txds
->Buffer_Pointer
)
2153 pci_unmap_page(nic
->pdev
, (dma_addr_t
)
2154 txds
->Buffer_Pointer
,
2155 frag
->size
, PCI_DMA_TODEVICE
);
2158 memset(txdlp
,0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2163 * free_tx_buffers - Free all queued Tx buffers
2164 * @nic : device private variable.
2166 * Free all queued Tx buffers.
2167 * Return Value: void
2170 static void free_tx_buffers(struct s2io_nic
*nic
)
2172 struct net_device
*dev
= nic
->dev
;
2173 struct sk_buff
*skb
;
2176 struct mac_info
*mac_control
;
2177 struct config_param
*config
;
2180 mac_control
= &nic
->mac_control
;
2181 config
= &nic
->config
;
2183 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
2184 for (j
= 0; j
< config
->tx_cfg
[i
].fifo_len
- 1; j
++) {
2185 txdp
= (struct TxD
*) \
2186 mac_control
->fifos
[i
].list_info
[j
].list_virt_addr
;
2187 skb
= s2io_txdl_getskb(&mac_control
->fifos
[i
], txdp
, j
);
2189 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
2196 "%s:forcibly freeing %d skbs on FIFO%d\n",
2198 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
2199 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
2204 * stop_nic - To stop the nic
2205 * @nic ; device private variable.
2207 * This function does exactly the opposite of what the start_nic()
2208 * function does. This function is called to stop the device.
2213 static void stop_nic(struct s2io_nic
*nic
)
2215 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2216 register u64 val64
= 0;
2218 struct mac_info
*mac_control
;
2219 struct config_param
*config
;
2221 mac_control
= &nic
->mac_control
;
2222 config
= &nic
->config
;
2224 /* Disable all interrupts */
2225 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
2226 interruptible
|= TX_PIC_INTR
| RX_PIC_INTR
;
2227 interruptible
|= TX_MAC_INTR
| RX_MAC_INTR
;
2228 en_dis_able_nic_intrs(nic
, interruptible
, DISABLE_INTRS
);
2230 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2231 val64
= readq(&bar0
->adapter_control
);
2232 val64
&= ~(ADAPTER_CNTL_EN
);
2233 writeq(val64
, &bar0
->adapter_control
);
2236 static int fill_rxd_3buf(struct s2io_nic
*nic
, struct RxD_t
*rxdp
, struct \
2239 struct net_device
*dev
= nic
->dev
;
2240 struct sk_buff
*frag_list
;
2243 /* Buffer-1 receives L3/L4 headers */
2244 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= pci_map_single
2245 (nic
->pdev
, skb
->data
, l3l4hdr_size
+ 4,
2246 PCI_DMA_FROMDEVICE
);
2248 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2249 skb_shinfo(skb
)->frag_list
= dev_alloc_skb(dev
->mtu
+ ALIGN_SIZE
);
2250 if (skb_shinfo(skb
)->frag_list
== NULL
) {
2251 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
2252 DBG_PRINT(INFO_DBG
, "%s: dev_alloc_skb failed\n ", dev
->name
);
2255 frag_list
= skb_shinfo(skb
)->frag_list
;
2256 skb
->truesize
+= frag_list
->truesize
;
2257 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
2258 += frag_list
->truesize
;
2259 frag_list
->next
= NULL
;
2260 tmp
= (void *)ALIGN((long)frag_list
->data
, ALIGN_SIZE
+ 1);
2261 frag_list
->data
= tmp
;
2262 skb_reset_tail_pointer(frag_list
);
2264 /* Buffer-2 receives L4 data payload */
2265 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= pci_map_single(nic
->pdev
,
2266 frag_list
->data
, dev
->mtu
,
2267 PCI_DMA_FROMDEVICE
);
2268 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(l3l4hdr_size
+ 4);
2269 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3(dev
->mtu
);
2275 * fill_rx_buffers - Allocates the Rx side skbs
2276 * @nic: device private variable
2277 * @ring_no: ring number
2279 * The function allocates Rx side skbs and puts the physical
2280 * address of these buffers into the RxD buffer pointers, so that the NIC
2281 * can DMA the received frame into these locations.
2282 * The NIC supports 3 receive modes, viz
2284 * 2. three buffer and
2285 * 3. Five buffer modes.
2286 * Each mode defines how many fragments the received frame will be split
2287 * up into by the NIC. The frame is split into L3 header, L4 Header,
2288 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2289 * is split into 3 fragments. As of now only single buffer mode is
2292 * SUCCESS on success or an appropriate -ve value on failure.
2295 static int fill_rx_buffers(struct s2io_nic
*nic
, int ring_no
)
2297 struct net_device
*dev
= nic
->dev
;
2298 struct sk_buff
*skb
;
2300 int off
, off1
, size
, block_no
, block_no1
;
2303 struct mac_info
*mac_control
;
2304 struct config_param
*config
;
2307 unsigned long flags
;
2308 struct RxD_t
*first_rxdp
= NULL
;
2309 u64 Buffer0_ptr
= 0, Buffer1_ptr
= 0;
2311 mac_control
= &nic
->mac_control
;
2312 config
= &nic
->config
;
2313 alloc_cnt
= mac_control
->rings
[ring_no
].pkt_cnt
-
2314 atomic_read(&nic
->rx_bufs_left
[ring_no
]);
2316 block_no1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.block_index
;
2317 off1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.offset
;
2318 while (alloc_tab
< alloc_cnt
) {
2319 block_no
= mac_control
->rings
[ring_no
].rx_curr_put_info
.
2321 off
= mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
;
2323 rxdp
= mac_control
->rings
[ring_no
].
2324 rx_blocks
[block_no
].rxds
[off
].virt_addr
;
2326 if ((block_no
== block_no1
) && (off
== off1
) &&
2327 (rxdp
->Host_Control
)) {
2328 DBG_PRINT(INTR_DBG
, "%s: Get and Put",
2330 DBG_PRINT(INTR_DBG
, " info equated\n");
2333 if (off
&& (off
== rxd_count
[nic
->rxd_mode
])) {
2334 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2336 if (mac_control
->rings
[ring_no
].rx_curr_put_info
.
2337 block_index
== mac_control
->rings
[ring_no
].
2339 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2341 block_no
= mac_control
->rings
[ring_no
].
2342 rx_curr_put_info
.block_index
;
2343 if (off
== rxd_count
[nic
->rxd_mode
])
2345 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2347 rxdp
= mac_control
->rings
[ring_no
].
2348 rx_blocks
[block_no
].block_virt_addr
;
2349 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
2353 spin_lock_irqsave(&nic
->put_lock
, flags
);
2354 mac_control
->rings
[ring_no
].put_pos
=
2355 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2356 spin_unlock_irqrestore(&nic
->put_lock
, flags
);
2358 mac_control
->rings
[ring_no
].put_pos
=
2359 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2361 if ((rxdp
->Control_1
& RXD_OWN_XENA
) &&
2362 ((nic
->rxd_mode
>= RXD_MODE_3A
) &&
2363 (rxdp
->Control_2
& BIT(0)))) {
2364 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2368 /* calculate size of skb based on ring mode */
2369 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
2370 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
2371 if (nic
->rxd_mode
== RXD_MODE_1
)
2372 size
+= NET_IP_ALIGN
;
2373 else if (nic
->rxd_mode
== RXD_MODE_3B
)
2374 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2376 size
= l3l4hdr_size
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2379 skb
= dev_alloc_skb(size
);
2381 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
2382 DBG_PRINT(INFO_DBG
, "memory to allocate SKBs\n");
2385 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2387 nic
->mac_control
.stats_info
->sw_stat
. \
2388 mem_alloc_fail_cnt
++;
2391 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
2393 if (nic
->rxd_mode
== RXD_MODE_1
) {
2394 /* 1 buffer mode - normal operation mode */
2395 memset(rxdp
, 0, sizeof(struct RxD1
));
2396 skb_reserve(skb
, NET_IP_ALIGN
);
2397 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= pci_map_single
2398 (nic
->pdev
, skb
->data
, size
- NET_IP_ALIGN
,
2399 PCI_DMA_FROMDEVICE
);
2401 SET_BUFFER0_SIZE_1(size
- NET_IP_ALIGN
);
2403 } else if (nic
->rxd_mode
>= RXD_MODE_3A
) {
2405 * 2 or 3 buffer mode -
2406 * Both 2 buffer mode and 3 buffer mode provides 128
2407 * byte aligned receive buffers.
2409 * 3 buffer mode provides header separation where in
2410 * skb->data will have L3/L4 headers where as
2411 * skb_shinfo(skb)->frag_list will have the L4 data
2415 /* save buffer pointers to avoid frequent dma mapping */
2416 Buffer0_ptr
= ((struct RxD3
*)rxdp
)->Buffer0_ptr
;
2417 Buffer1_ptr
= ((struct RxD3
*)rxdp
)->Buffer1_ptr
;
2418 memset(rxdp
, 0, sizeof(struct RxD3
));
2419 /* restore the buffer pointers for dma sync*/
2420 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= Buffer0_ptr
;
2421 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= Buffer1_ptr
;
2423 ba
= &mac_control
->rings
[ring_no
].ba
[block_no
][off
];
2424 skb_reserve(skb
, BUF0_LEN
);
2425 tmp
= (u64
)(unsigned long) skb
->data
;
2428 skb
->data
= (void *) (unsigned long)tmp
;
2429 skb_reset_tail_pointer(skb
);
2431 if (!(((struct RxD3
*)rxdp
)->Buffer0_ptr
))
2432 ((struct RxD3
*)rxdp
)->Buffer0_ptr
=
2433 pci_map_single(nic
->pdev
, ba
->ba_0
, BUF0_LEN
,
2434 PCI_DMA_FROMDEVICE
);
2436 pci_dma_sync_single_for_device(nic
->pdev
,
2437 (dma_addr_t
) ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2438 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2439 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
2440 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2441 /* Two buffer mode */
2444 * Buffer2 will have L3/L4 header plus
2447 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= pci_map_single
2448 (nic
->pdev
, skb
->data
, dev
->mtu
+ 4,
2449 PCI_DMA_FROMDEVICE
);
2451 /* Buffer-1 will be dummy buffer. Not used */
2452 if (!(((struct RxD3
*)rxdp
)->Buffer1_ptr
)) {
2453 ((struct RxD3
*)rxdp
)->Buffer1_ptr
=
2454 pci_map_single(nic
->pdev
,
2456 PCI_DMA_FROMDEVICE
);
2458 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
2459 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3
2463 if (fill_rxd_3buf(nic
, rxdp
, skb
) == -ENOMEM
) {
2464 nic
->mac_control
.stats_info
->sw_stat
.\
2465 mem_freed
+= skb
->truesize
;
2466 dev_kfree_skb_irq(skb
);
2469 first_rxdp
->Control_1
|=
2475 rxdp
->Control_2
|= BIT(0);
2477 rxdp
->Host_Control
= (unsigned long) (skb
);
2478 if (alloc_tab
& ((1 << rxsync_frequency
) - 1))
2479 rxdp
->Control_1
|= RXD_OWN_XENA
;
2481 if (off
== (rxd_count
[nic
->rxd_mode
] + 1))
2483 mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
= off
;
2485 rxdp
->Control_2
|= SET_RXD_MARKER
;
2486 if (!(alloc_tab
& ((1 << rxsync_frequency
) - 1))) {
2489 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2493 atomic_inc(&nic
->rx_bufs_left
[ring_no
]);
2498 /* Transfer ownership of first descriptor to adapter just before
2499 * exiting. Before that, use memory barrier so that ownership
2500 * and other fields are seen by adapter correctly.
2504 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2510 static void free_rxd_blk(struct s2io_nic
*sp
, int ring_no
, int blk
)
2512 struct net_device
*dev
= sp
->dev
;
2514 struct sk_buff
*skb
;
2516 struct mac_info
*mac_control
;
2519 mac_control
= &sp
->mac_control
;
2520 for (j
= 0 ; j
< rxd_count
[sp
->rxd_mode
]; j
++) {
2521 rxdp
= mac_control
->rings
[ring_no
].
2522 rx_blocks
[blk
].rxds
[j
].virt_addr
;
2523 skb
= (struct sk_buff
*)
2524 ((unsigned long) rxdp
->Host_Control
);
2528 if (sp
->rxd_mode
== RXD_MODE_1
) {
2529 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2530 ((struct RxD1
*)rxdp
)->Buffer0_ptr
,
2532 HEADER_ETHERNET_II_802_3_SIZE
2533 + HEADER_802_2_SIZE
+
2535 PCI_DMA_FROMDEVICE
);
2536 memset(rxdp
, 0, sizeof(struct RxD1
));
2537 } else if(sp
->rxd_mode
== RXD_MODE_3B
) {
2538 ba
= &mac_control
->rings
[ring_no
].
2540 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2541 ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2543 PCI_DMA_FROMDEVICE
);
2544 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2545 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2547 PCI_DMA_FROMDEVICE
);
2548 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2549 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2551 PCI_DMA_FROMDEVICE
);
2552 memset(rxdp
, 0, sizeof(struct RxD3
));
2554 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2555 ((struct RxD3
*)rxdp
)->Buffer0_ptr
, BUF0_LEN
,
2556 PCI_DMA_FROMDEVICE
);
2557 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2558 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2560 PCI_DMA_FROMDEVICE
);
2561 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2562 ((struct RxD3
*)rxdp
)->Buffer2_ptr
, dev
->mtu
,
2563 PCI_DMA_FROMDEVICE
);
2564 memset(rxdp
, 0, sizeof(struct RxD3
));
2566 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
2568 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
2573 * free_rx_buffers - Frees all Rx buffers
2574 * @sp: device private variable.
2576 * This function will free all Rx buffers allocated by host.
2581 static void free_rx_buffers(struct s2io_nic
*sp
)
2583 struct net_device
*dev
= sp
->dev
;
2584 int i
, blk
= 0, buf_cnt
= 0;
2585 struct mac_info
*mac_control
;
2586 struct config_param
*config
;
2588 mac_control
= &sp
->mac_control
;
2589 config
= &sp
->config
;
2591 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2592 for (blk
= 0; blk
< rx_ring_sz
[i
]; blk
++)
2593 free_rxd_blk(sp
,i
,blk
);
2595 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
2596 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
2597 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
2598 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
2599 atomic_set(&sp
->rx_bufs_left
[i
], 0);
2600 DBG_PRINT(INIT_DBG
, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2601 dev
->name
, buf_cnt
, i
);
2606 * s2io_poll - Rx interrupt handler for NAPI support
2607 * @dev : pointer to the device structure.
2608 * @budget : The number of packets that were budgeted to be processed
2609 * during one pass through the 'Poll" function.
2611 * Comes into picture only if NAPI support has been incorporated. It does
2612 * the same thing that rx_intr_handler does, but not in a interrupt context
2613 * also It will process only a given number of packets.
2615 * 0 on success and 1 if there are No Rx packets to be processed.
2618 static int s2io_poll(struct net_device
*dev
, int *budget
)
2620 struct s2io_nic
*nic
= dev
->priv
;
2621 int pkt_cnt
= 0, org_pkts_to_process
;
2622 struct mac_info
*mac_control
;
2623 struct config_param
*config
;
2624 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2627 atomic_inc(&nic
->isr_cnt
);
2628 mac_control
= &nic
->mac_control
;
2629 config
= &nic
->config
;
2631 nic
->pkts_to_process
= *budget
;
2632 if (nic
->pkts_to_process
> dev
->quota
)
2633 nic
->pkts_to_process
= dev
->quota
;
2634 org_pkts_to_process
= nic
->pkts_to_process
;
2636 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
2637 readl(&bar0
->rx_traffic_int
);
2639 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2640 rx_intr_handler(&mac_control
->rings
[i
]);
2641 pkt_cnt
= org_pkts_to_process
- nic
->pkts_to_process
;
2642 if (!nic
->pkts_to_process
) {
2643 /* Quota for the current iteration has been met */
2650 dev
->quota
-= pkt_cnt
;
2652 netif_rx_complete(dev
);
2654 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2655 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2656 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2657 DBG_PRINT(INFO_DBG
, " in Rx Poll!!\n");
2661 /* Re enable the Rx interrupts. */
2662 writeq(0x0, &bar0
->rx_traffic_mask
);
2663 readl(&bar0
->rx_traffic_mask
);
2664 atomic_dec(&nic
->isr_cnt
);
2668 dev
->quota
-= pkt_cnt
;
2671 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2672 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2673 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2674 DBG_PRINT(INFO_DBG
, " in Rx Poll!!\n");
2678 atomic_dec(&nic
->isr_cnt
);
2682 #ifdef CONFIG_NET_POLL_CONTROLLER
2684 * s2io_netpoll - netpoll event handler entry point
2685 * @dev : pointer to the device structure.
2687 * This function will be called by upper layer to check for events on the
2688 * interface in situations where interrupts are disabled. It is used for
2689 * specific in-kernel networking tasks, such as remote consoles and kernel
2690 * debugging over the network (example netdump in RedHat).
2692 static void s2io_netpoll(struct net_device
*dev
)
2694 struct s2io_nic
*nic
= dev
->priv
;
2695 struct mac_info
*mac_control
;
2696 struct config_param
*config
;
2697 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2698 u64 val64
= 0xFFFFFFFFFFFFFFFFULL
;
2701 if (pci_channel_offline(nic
->pdev
))
2704 disable_irq(dev
->irq
);
2706 atomic_inc(&nic
->isr_cnt
);
2707 mac_control
= &nic
->mac_control
;
2708 config
= &nic
->config
;
2710 writeq(val64
, &bar0
->rx_traffic_int
);
2711 writeq(val64
, &bar0
->tx_traffic_int
);
2713 /* we need to free up the transmitted skbufs or else netpoll will
2714 * run out of skbs and will fail and eventually netpoll application such
2715 * as netdump will fail.
2717 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
2718 tx_intr_handler(&mac_control
->fifos
[i
]);
2720 /* check for received packet and indicate up to network */
2721 for (i
= 0; i
< config
->rx_ring_num
; i
++)
2722 rx_intr_handler(&mac_control
->rings
[i
]);
2724 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2725 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2726 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2727 DBG_PRINT(INFO_DBG
, " in Rx Netpoll!!\n");
2731 atomic_dec(&nic
->isr_cnt
);
2732 enable_irq(dev
->irq
);
2738 * rx_intr_handler - Rx interrupt handler
2739 * @nic: device private variable.
2741 * If the interrupt is because of a received frame or if the
2742 * receive ring contains fresh as yet un-processed frames,this function is
2743 * called. It picks out the RxD at which place the last Rx processing had
2744 * stopped and sends the skb to the OSM's Rx handler and then increments
2749 static void rx_intr_handler(struct ring_info
*ring_data
)
2751 struct s2io_nic
*nic
= ring_data
->nic
;
2752 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2753 int get_block
, put_block
, put_offset
;
2754 struct rx_curr_get_info get_info
, put_info
;
2756 struct sk_buff
*skb
;
2760 spin_lock(&nic
->rx_lock
);
2761 if (atomic_read(&nic
->card_state
) == CARD_DOWN
) {
2762 DBG_PRINT(INTR_DBG
, "%s: %s going down for reset\n",
2763 __FUNCTION__
, dev
->name
);
2764 spin_unlock(&nic
->rx_lock
);
2768 get_info
= ring_data
->rx_curr_get_info
;
2769 get_block
= get_info
.block_index
;
2770 memcpy(&put_info
, &ring_data
->rx_curr_put_info
, sizeof(put_info
));
2771 put_block
= put_info
.block_index
;
2772 rxdp
= ring_data
->rx_blocks
[get_block
].rxds
[get_info
.offset
].virt_addr
;
2774 spin_lock(&nic
->put_lock
);
2775 put_offset
= ring_data
->put_pos
;
2776 spin_unlock(&nic
->put_lock
);
2778 put_offset
= ring_data
->put_pos
;
2780 while (RXD_IS_UP2DT(rxdp
)) {
2782 * If your are next to put index then it's
2783 * FIFO full condition
2785 if ((get_block
== put_block
) &&
2786 (get_info
.offset
+ 1) == put_info
.offset
) {
2787 DBG_PRINT(INTR_DBG
, "%s: Ring Full\n",dev
->name
);
2790 skb
= (struct sk_buff
*) ((unsigned long)rxdp
->Host_Control
);
2792 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
2794 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
2795 spin_unlock(&nic
->rx_lock
);
2798 if (nic
->rxd_mode
== RXD_MODE_1
) {
2799 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2800 ((struct RxD1
*)rxdp
)->Buffer0_ptr
,
2802 HEADER_ETHERNET_II_802_3_SIZE
+
2805 PCI_DMA_FROMDEVICE
);
2806 } else if (nic
->rxd_mode
== RXD_MODE_3B
) {
2807 pci_dma_sync_single_for_cpu(nic
->pdev
, (dma_addr_t
)
2808 ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2809 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2810 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2811 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2813 PCI_DMA_FROMDEVICE
);
2815 pci_dma_sync_single_for_cpu(nic
->pdev
, (dma_addr_t
)
2816 ((struct RxD3
*)rxdp
)->Buffer0_ptr
, BUF0_LEN
,
2817 PCI_DMA_FROMDEVICE
);
2818 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2819 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2821 PCI_DMA_FROMDEVICE
);
2822 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2823 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2824 dev
->mtu
, PCI_DMA_FROMDEVICE
);
2826 prefetch(skb
->data
);
2827 rx_osm_handler(ring_data
, rxdp
);
2829 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2830 rxdp
= ring_data
->rx_blocks
[get_block
].
2831 rxds
[get_info
.offset
].virt_addr
;
2832 if (get_info
.offset
== rxd_count
[nic
->rxd_mode
]) {
2833 get_info
.offset
= 0;
2834 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2836 if (get_block
== ring_data
->block_count
)
2838 ring_data
->rx_curr_get_info
.block_index
= get_block
;
2839 rxdp
= ring_data
->rx_blocks
[get_block
].block_virt_addr
;
2842 nic
->pkts_to_process
-= 1;
2843 if ((napi
) && (!nic
->pkts_to_process
))
2846 if ((indicate_max_pkts
) && (pkt_cnt
> indicate_max_pkts
))
2850 /* Clear all LRO sessions before exiting */
2851 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
2852 struct lro
*lro
= &nic
->lro0_n
[i
];
2854 update_L3L4_header(nic
, lro
);
2855 queue_rx_frame(lro
->parent
);
2856 clear_lro_session(lro
);
2861 spin_unlock(&nic
->rx_lock
);
2865 * tx_intr_handler - Transmit interrupt handler
2866 * @nic : device private variable
2868 * If an interrupt was raised to indicate DMA complete of the
2869 * Tx packet, this function is called. It identifies the last TxD
2870 * whose buffer was freed and frees all skbs whose data have already
2871 * DMA'ed into the NICs internal memory.
2876 static void tx_intr_handler(struct fifo_info
*fifo_data
)
2878 struct s2io_nic
*nic
= fifo_data
->nic
;
2879 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2880 struct tx_curr_get_info get_info
, put_info
;
2881 struct sk_buff
*skb
;
2885 get_info
= fifo_data
->tx_curr_get_info
;
2886 memcpy(&put_info
, &fifo_data
->tx_curr_put_info
, sizeof(put_info
));
2887 txdlp
= (struct TxD
*) fifo_data
->list_info
[get_info
.offset
].
2889 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
2890 (get_info
.offset
!= put_info
.offset
) &&
2891 (txdlp
->Host_Control
)) {
2892 /* Check for TxD errors */
2893 if (txdlp
->Control_1
& TXD_T_CODE
) {
2894 unsigned long long err
;
2895 err
= txdlp
->Control_1
& TXD_T_CODE
;
2897 nic
->mac_control
.stats_info
->sw_stat
.
2901 /* update t_code statistics */
2902 err_mask
= err
>> 48;
2905 nic
->mac_control
.stats_info
->sw_stat
.
2910 nic
->mac_control
.stats_info
->sw_stat
.
2911 tx_desc_abort_cnt
++;
2915 nic
->mac_control
.stats_info
->sw_stat
.
2916 tx_parity_err_cnt
++;
2920 nic
->mac_control
.stats_info
->sw_stat
.
2925 nic
->mac_control
.stats_info
->sw_stat
.
2926 tx_list_proc_err_cnt
++;
2931 skb
= s2io_txdl_getskb(fifo_data
, txdlp
, get_info
.offset
);
2933 DBG_PRINT(ERR_DBG
, "%s: Null skb ",
2935 DBG_PRINT(ERR_DBG
, "in Tx Free Intr\n");
2939 /* Updating the statistics block */
2940 nic
->stats
.tx_bytes
+= skb
->len
;
2941 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
2942 dev_kfree_skb_irq(skb
);
2945 if (get_info
.offset
== get_info
.fifo_len
+ 1)
2946 get_info
.offset
= 0;
2947 txdlp
= (struct TxD
*) fifo_data
->list_info
2948 [get_info
.offset
].list_virt_addr
;
2949 fifo_data
->tx_curr_get_info
.offset
=
2953 spin_lock(&nic
->tx_lock
);
2954 if (netif_queue_stopped(dev
))
2955 netif_wake_queue(dev
);
2956 spin_unlock(&nic
->tx_lock
);
2960 * s2io_mdio_write - Function to write in to MDIO registers
2961 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2962 * @addr : address value
2963 * @value : data value
2964 * @dev : pointer to net_device structure
2966 * This function is used to write values to the MDIO registers
2969 static void s2io_mdio_write(u32 mmd_type
, u64 addr
, u16 value
, struct net_device
*dev
)
2972 struct s2io_nic
*sp
= dev
->priv
;
2973 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2975 //address transaction
2976 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2977 | MDIO_MMD_DEV_ADDR(mmd_type
)
2978 | MDIO_MMS_PRT_ADDR(0x0);
2979 writeq(val64
, &bar0
->mdio_control
);
2980 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2981 writeq(val64
, &bar0
->mdio_control
);
2986 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2987 | MDIO_MMD_DEV_ADDR(mmd_type
)
2988 | MDIO_MMS_PRT_ADDR(0x0)
2989 | MDIO_MDIO_DATA(value
)
2990 | MDIO_OP(MDIO_OP_WRITE_TRANS
);
2991 writeq(val64
, &bar0
->mdio_control
);
2992 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2993 writeq(val64
, &bar0
->mdio_control
);
2997 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2998 | MDIO_MMD_DEV_ADDR(mmd_type
)
2999 | MDIO_MMS_PRT_ADDR(0x0)
3000 | MDIO_OP(MDIO_OP_READ_TRANS
);
3001 writeq(val64
, &bar0
->mdio_control
);
3002 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3003 writeq(val64
, &bar0
->mdio_control
);
3009 * s2io_mdio_read - Function to write in to MDIO registers
3010 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3011 * @addr : address value
3012 * @dev : pointer to net_device structure
3014 * This function is used to read values to the MDIO registers
3017 static u64
s2io_mdio_read(u32 mmd_type
, u64 addr
, struct net_device
*dev
)
3021 struct s2io_nic
*sp
= dev
->priv
;
3022 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3024 /* address transaction */
3025 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3026 | MDIO_MMD_DEV_ADDR(mmd_type
)
3027 | MDIO_MMS_PRT_ADDR(0x0);
3028 writeq(val64
, &bar0
->mdio_control
);
3029 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3030 writeq(val64
, &bar0
->mdio_control
);
3033 /* Data transaction */
3035 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3036 | MDIO_MMD_DEV_ADDR(mmd_type
)
3037 | MDIO_MMS_PRT_ADDR(0x0)
3038 | MDIO_OP(MDIO_OP_READ_TRANS
);
3039 writeq(val64
, &bar0
->mdio_control
);
3040 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3041 writeq(val64
, &bar0
->mdio_control
);
3044 /* Read the value from regs */
3045 rval64
= readq(&bar0
->mdio_control
);
3046 rval64
= rval64
& 0xFFFF0000;
3047 rval64
= rval64
>> 16;
3051 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3052 * @counter : couter value to be updated
3053 * @flag : flag to indicate the status
3054 * @type : counter type
3056 * This function is to check the status of the xpak counters value
3060 static void s2io_chk_xpak_counter(u64
*counter
, u64
* regs_stat
, u32 index
, u16 flag
, u16 type
)
3065 for(i
= 0; i
<index
; i
++)
3070 *counter
= *counter
+ 1;
3071 val64
= *regs_stat
& mask
;
3072 val64
= val64
>> (index
* 0x2);
3079 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3080 "service. Excessive temperatures may "
3081 "result in premature transceiver "
3085 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3086 "service Excessive bias currents may "
3087 "indicate imminent laser diode "
3091 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3092 "service Excessive laser output "
3093 "power may saturate far-end "
3097 DBG_PRINT(ERR_DBG
, "Incorrect XPAK Alarm "
3102 val64
= val64
<< (index
* 0x2);
3103 *regs_stat
= (*regs_stat
& (~mask
)) | (val64
);
3106 *regs_stat
= *regs_stat
& (~mask
);
3111 * s2io_updt_xpak_counter - Function to update the xpak counters
3112 * @dev : pointer to net_device struct
3114 * This function is to upate the status of the xpak counters value
3117 static void s2io_updt_xpak_counter(struct net_device
*dev
)
3125 struct s2io_nic
*sp
= dev
->priv
;
3126 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
3128 /* Check the communication with the MDIO slave */
3131 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3132 if((val64
== 0xFFFF) || (val64
== 0x0000))
3134 DBG_PRINT(ERR_DBG
, "ERR: MDIO slave access failed - "
3135 "Returned %llx\n", (unsigned long long)val64
);
3139 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3142 DBG_PRINT(ERR_DBG
, "Incorrect value at PMA address 0x0000 - ");
3143 DBG_PRINT(ERR_DBG
, "Returned: %llx- Expected: 0x2040\n",
3144 (unsigned long long)val64
);
3148 /* Loading the DOM register to MDIO register */
3150 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR
, addr
, val16
, dev
);
3151 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3153 /* Reading the Alarm flags */
3156 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3158 flag
= CHECKBIT(val64
, 0x7);
3160 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_transceiver_temp_high
,
3161 &stat_info
->xpak_stat
.xpak_regs_stat
,
3164 if(CHECKBIT(val64
, 0x6))
3165 stat_info
->xpak_stat
.alarm_transceiver_temp_low
++;
3167 flag
= CHECKBIT(val64
, 0x3);
3169 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_bias_current_high
,
3170 &stat_info
->xpak_stat
.xpak_regs_stat
,
3173 if(CHECKBIT(val64
, 0x2))
3174 stat_info
->xpak_stat
.alarm_laser_bias_current_low
++;
3176 flag
= CHECKBIT(val64
, 0x1);
3178 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_output_power_high
,
3179 &stat_info
->xpak_stat
.xpak_regs_stat
,
3182 if(CHECKBIT(val64
, 0x0))
3183 stat_info
->xpak_stat
.alarm_laser_output_power_low
++;
3185 /* Reading the Warning flags */
3188 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3190 if(CHECKBIT(val64
, 0x7))
3191 stat_info
->xpak_stat
.warn_transceiver_temp_high
++;
3193 if(CHECKBIT(val64
, 0x6))
3194 stat_info
->xpak_stat
.warn_transceiver_temp_low
++;
3196 if(CHECKBIT(val64
, 0x3))
3197 stat_info
->xpak_stat
.warn_laser_bias_current_high
++;
3199 if(CHECKBIT(val64
, 0x2))
3200 stat_info
->xpak_stat
.warn_laser_bias_current_low
++;
3202 if(CHECKBIT(val64
, 0x1))
3203 stat_info
->xpak_stat
.warn_laser_output_power_high
++;
3205 if(CHECKBIT(val64
, 0x0))
3206 stat_info
->xpak_stat
.warn_laser_output_power_low
++;
3210 * alarm_intr_handler - Alarm Interrrupt handler
3211 * @nic: device private variable
3212 * Description: If the interrupt was neither because of Rx packet or Tx
3213 * complete, this function is called. If the interrupt was to indicate
3214 * a loss of link, the OSM link status handler is invoked for any other
3215 * alarm interrupt the block that raised the interrupt is displayed
3216 * and a H/W reset is issued.
3221 static void alarm_intr_handler(struct s2io_nic
*nic
)
3223 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
3224 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3225 register u64 val64
= 0, err_reg
= 0;
3228 if (atomic_read(&nic
->card_state
) == CARD_DOWN
)
3230 if (pci_channel_offline(nic
->pdev
))
3232 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
= 0;
3233 /* Handling the XPAK counters update */
3234 if(nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
< 72000) {
3235 /* waiting for an hour */
3236 nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
++;
3238 s2io_updt_xpak_counter(dev
);
3239 /* reset the count to zero */
3240 nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
= 0;
3243 /* Handling link status change error Intr */
3244 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
3245 err_reg
= readq(&bar0
->mac_rmac_err_reg
);
3246 writeq(err_reg
, &bar0
->mac_rmac_err_reg
);
3247 if (err_reg
& RMAC_LINK_STATE_CHANGE_INT
) {
3248 schedule_work(&nic
->set_link_task
);
3252 /* Handling Ecc errors */
3253 val64
= readq(&bar0
->mc_err_reg
);
3254 writeq(val64
, &bar0
->mc_err_reg
);
3255 if (val64
& (MC_ERR_REG_ECC_ALL_SNG
| MC_ERR_REG_ECC_ALL_DBL
)) {
3256 if (val64
& MC_ERR_REG_ECC_ALL_DBL
) {
3257 nic
->mac_control
.stats_info
->sw_stat
.
3259 DBG_PRINT(INIT_DBG
, "%s: Device indicates ",
3261 DBG_PRINT(INIT_DBG
, "double ECC error!!\n");
3262 if (nic
->device_type
!= XFRAME_II_DEVICE
) {
3263 /* Reset XframeI only if critical error */
3264 if (val64
& (MC_ERR_REG_MIRI_ECC_DB_ERR_0
|
3265 MC_ERR_REG_MIRI_ECC_DB_ERR_1
)) {
3266 netif_stop_queue(dev
);
3267 schedule_work(&nic
->rst_timer_task
);
3268 nic
->mac_control
.stats_info
->sw_stat
.
3273 nic
->mac_control
.stats_info
->sw_stat
.
3278 /* In case of a serious error, the device will be Reset. */
3279 val64
= readq(&bar0
->serr_source
);
3280 if (val64
& SERR_SOURCE_ANY
) {
3281 nic
->mac_control
.stats_info
->sw_stat
.serious_err_cnt
++;
3282 DBG_PRINT(ERR_DBG
, "%s: Device indicates ", dev
->name
);
3283 DBG_PRINT(ERR_DBG
, "serious error %llx!!\n",
3284 (unsigned long long)val64
);
3285 netif_stop_queue(dev
);
3286 schedule_work(&nic
->rst_timer_task
);
3287 nic
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
3291 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3292 * Error occurs, the adapter will be recycled by disabling the
3293 * adapter enable bit and enabling it again after the device
3294 * becomes Quiescent.
3296 val64
= readq(&bar0
->pcc_err_reg
);
3297 writeq(val64
, &bar0
->pcc_err_reg
);
3298 if (val64
& PCC_FB_ECC_DB_ERR
) {
3299 u64 ac
= readq(&bar0
->adapter_control
);
3300 ac
&= ~(ADAPTER_CNTL_EN
);
3301 writeq(ac
, &bar0
->adapter_control
);
3302 ac
= readq(&bar0
->adapter_control
);
3303 schedule_work(&nic
->set_link_task
);
3305 /* Check for data parity error */
3306 val64
= readq(&bar0
->pic_int_status
);
3307 if (val64
& PIC_INT_GPIO
) {
3308 val64
= readq(&bar0
->gpio_int_reg
);
3309 if (val64
& GPIO_INT_REG_DP_ERR_INT
) {
3310 nic
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
3311 schedule_work(&nic
->rst_timer_task
);
3312 nic
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
3316 /* Check for ring full counter */
3317 if (nic
->device_type
& XFRAME_II_DEVICE
) {
3318 val64
= readq(&bar0
->ring_bump_counter1
);
3319 for (i
=0; i
<4; i
++) {
3320 cnt
= ( val64
& vBIT(0xFFFF,(i
*16),16));
3321 cnt
>>= 64 - ((i
+1)*16);
3322 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
3326 val64
= readq(&bar0
->ring_bump_counter2
);
3327 for (i
=0; i
<4; i
++) {
3328 cnt
= ( val64
& vBIT(0xFFFF,(i
*16),16));
3329 cnt
>>= 64 - ((i
+1)*16);
3330 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
3335 /* Other type of interrupts are not being handled now, TODO */
3339 * wait_for_cmd_complete - waits for a command to complete.
3340 * @sp : private member of the device structure, which is a pointer to the
3341 * s2io_nic structure.
3342 * Description: Function that waits for a command to Write into RMAC
3343 * ADDR DATA registers to be completed and returns either success or
3344 * error depending on whether the command was complete or not.
3346 * SUCCESS on success and FAILURE on failure.
3349 static int wait_for_cmd_complete(void __iomem
*addr
, u64 busy_bit
,
3352 int ret
= FAILURE
, cnt
= 0, delay
= 1;
3355 if ((bit_state
!= S2IO_BIT_RESET
) && (bit_state
!= S2IO_BIT_SET
))
3359 val64
= readq(addr
);
3360 if (bit_state
== S2IO_BIT_RESET
) {
3361 if (!(val64
& busy_bit
)) {
3366 if (!(val64
& busy_bit
)) {
3383 * check_pci_device_id - Checks if the device id is supported
3385 * Description: Function to check if the pci device id is supported by driver.
3386 * Return value: Actual device id if supported else PCI_ANY_ID
3388 static u16
check_pci_device_id(u16 id
)
3391 case PCI_DEVICE_ID_HERC_WIN
:
3392 case PCI_DEVICE_ID_HERC_UNI
:
3393 return XFRAME_II_DEVICE
;
3394 case PCI_DEVICE_ID_S2IO_UNI
:
3395 case PCI_DEVICE_ID_S2IO_WIN
:
3396 return XFRAME_I_DEVICE
;
3403 * s2io_reset - Resets the card.
3404 * @sp : private member of the device structure.
3405 * Description: Function to Reset the card. This function then also
3406 * restores the previously saved PCI configuration space registers as
3407 * the card reset also resets the configuration space.
3412 static void s2io_reset(struct s2io_nic
* sp
)
3414 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3419 unsigned long long up_cnt
, down_cnt
, up_time
, down_time
, reset_cnt
;
3420 unsigned long long mem_alloc_cnt
, mem_free_cnt
, watchdog_cnt
;
3422 DBG_PRINT(INIT_DBG
,"%s - Resetting XFrame card %s\n",
3423 __FUNCTION__
, sp
->dev
->name
);
3425 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3426 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, &(pci_cmd
));
3428 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3430 ret
= pci_set_power_state(sp
->pdev
, 3);
3432 ret
= pci_set_power_state(sp
->pdev
, 0);
3434 DBG_PRINT(ERR_DBG
,"%s PME based SW_Reset failed!\n",
3442 val64
= SW_RESET_ALL
;
3443 writeq(val64
, &bar0
->sw_reset
);
3445 if (strstr(sp
->product_name
, "CX4")) {
3449 for (i
= 0; i
< S2IO_MAX_PCI_CONFIG_SPACE_REINIT
; i
++) {
3451 /* Restore the PCI state saved during initialization. */
3452 pci_restore_state(sp
->pdev
);
3453 pci_read_config_word(sp
->pdev
, 0x2, &val16
);
3454 if (check_pci_device_id(val16
) != (u16
)PCI_ANY_ID
)
3459 if (check_pci_device_id(val16
) == (u16
)PCI_ANY_ID
) {
3460 DBG_PRINT(ERR_DBG
,"%s SW_Reset failed!\n", __FUNCTION__
);
3463 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, pci_cmd
);
3467 /* Set swapper to enable I/O register access */
3468 s2io_set_swapper(sp
);
3470 /* Restore the MSIX table entries from local variables */
3471 restore_xmsi_data(sp
);
3473 /* Clear certain PCI/PCI-X fields after reset */
3474 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3475 /* Clear "detected parity error" bit */
3476 pci_write_config_word(sp
->pdev
, PCI_STATUS
, 0x8000);
3478 /* Clearing PCIX Ecc status register */
3479 pci_write_config_dword(sp
->pdev
, 0x68, 0x7C);
3481 /* Clearing PCI_STATUS error reflected here */
3482 writeq(BIT(62), &bar0
->txpic_int_reg
);
3485 /* Reset device statistics maintained by OS */
3486 memset(&sp
->stats
, 0, sizeof (struct net_device_stats
));
3488 up_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
;
3489 down_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
;
3490 up_time
= sp
->mac_control
.stats_info
->sw_stat
.link_up_time
;
3491 down_time
= sp
->mac_control
.stats_info
->sw_stat
.link_down_time
;
3492 reset_cnt
= sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
;
3493 mem_alloc_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
;
3494 mem_free_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_freed
;
3495 watchdog_cnt
= sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
;
3496 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3497 memset(sp
->mac_control
.stats_info
, 0, sizeof(struct stat_block
));
3498 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3499 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
= up_cnt
;
3500 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
= down_cnt
;
3501 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
= up_time
;
3502 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
= down_time
;
3503 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
= reset_cnt
;
3504 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
= mem_alloc_cnt
;
3505 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
= mem_free_cnt
;
3506 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
= watchdog_cnt
;
3508 /* SXE-002: Configure link and activity LED to turn it off */
3509 subid
= sp
->pdev
->subsystem_device
;
3510 if (((subid
& 0xFF) >= 0x07) &&
3511 (sp
->device_type
== XFRAME_I_DEVICE
)) {
3512 val64
= readq(&bar0
->gpio_control
);
3513 val64
|= 0x0000800000000000ULL
;
3514 writeq(val64
, &bar0
->gpio_control
);
3515 val64
= 0x0411040400000000ULL
;
3516 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
3520 * Clear spurious ECC interrupts that would have occured on
3521 * XFRAME II cards after reset.
3523 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3524 val64
= readq(&bar0
->pcc_err_reg
);
3525 writeq(val64
, &bar0
->pcc_err_reg
);
3528 /* restore the previously assigned mac address */
3529 s2io_set_mac_addr(sp
->dev
, (u8
*)&sp
->def_mac_addr
[0].mac_addr
);
3531 sp
->device_enabled_once
= FALSE
;
3535 * s2io_set_swapper - to set the swapper controle on the card
3536 * @sp : private member of the device structure,
3537 * pointer to the s2io_nic structure.
3538 * Description: Function to set the swapper control on the card
3539 * correctly depending on the 'endianness' of the system.
3541 * SUCCESS on success and FAILURE on failure.
3544 static int s2io_set_swapper(struct s2io_nic
* sp
)
3546 struct net_device
*dev
= sp
->dev
;
3547 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3548 u64 val64
, valt
, valr
;
3551 * Set proper endian settings and verify the same by reading
3552 * the PIF Feed-back register.
3555 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3556 if (val64
!= 0x0123456789ABCDEFULL
) {
3558 u64 value
[] = { 0xC30000C3C30000C3ULL
, /* FE=1, SE=1 */
3559 0x8100008181000081ULL
, /* FE=1, SE=0 */
3560 0x4200004242000042ULL
, /* FE=0, SE=1 */
3561 0}; /* FE=0, SE=0 */
3564 writeq(value
[i
], &bar0
->swapper_ctrl
);
3565 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3566 if (val64
== 0x0123456789ABCDEFULL
)
3571 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3573 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3574 (unsigned long long) val64
);
3579 valr
= readq(&bar0
->swapper_ctrl
);
3582 valt
= 0x0123456789ABCDEFULL
;
3583 writeq(valt
, &bar0
->xmsi_address
);
3584 val64
= readq(&bar0
->xmsi_address
);
3588 u64 value
[] = { 0x00C3C30000C3C300ULL
, /* FE=1, SE=1 */
3589 0x0081810000818100ULL
, /* FE=1, SE=0 */
3590 0x0042420000424200ULL
, /* FE=0, SE=1 */
3591 0}; /* FE=0, SE=0 */
3594 writeq((value
[i
] | valr
), &bar0
->swapper_ctrl
);
3595 writeq(valt
, &bar0
->xmsi_address
);
3596 val64
= readq(&bar0
->xmsi_address
);
3602 unsigned long long x
= val64
;
3603 DBG_PRINT(ERR_DBG
, "Write failed, Xmsi_addr ");
3604 DBG_PRINT(ERR_DBG
, "reads:0x%llx\n", x
);
3608 val64
= readq(&bar0
->swapper_ctrl
);
3609 val64
&= 0xFFFF000000000000ULL
;
3613 * The device by default set to a big endian format, so a
3614 * big endian driver need not set anything.
3616 val64
|= (SWAPPER_CTRL_TXP_FE
|
3617 SWAPPER_CTRL_TXP_SE
|
3618 SWAPPER_CTRL_TXD_R_FE
|
3619 SWAPPER_CTRL_TXD_W_FE
|
3620 SWAPPER_CTRL_TXF_R_FE
|
3621 SWAPPER_CTRL_RXD_R_FE
|
3622 SWAPPER_CTRL_RXD_W_FE
|
3623 SWAPPER_CTRL_RXF_W_FE
|
3624 SWAPPER_CTRL_XMSI_FE
|
3625 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3626 if (sp
->intr_type
== INTA
)
3627 val64
|= SWAPPER_CTRL_XMSI_SE
;
3628 writeq(val64
, &bar0
->swapper_ctrl
);
3631 * Initially we enable all bits to make it accessible by the
3632 * driver, then we selectively enable only those bits that
3635 val64
|= (SWAPPER_CTRL_TXP_FE
|
3636 SWAPPER_CTRL_TXP_SE
|
3637 SWAPPER_CTRL_TXD_R_FE
|
3638 SWAPPER_CTRL_TXD_R_SE
|
3639 SWAPPER_CTRL_TXD_W_FE
|
3640 SWAPPER_CTRL_TXD_W_SE
|
3641 SWAPPER_CTRL_TXF_R_FE
|
3642 SWAPPER_CTRL_RXD_R_FE
|
3643 SWAPPER_CTRL_RXD_R_SE
|
3644 SWAPPER_CTRL_RXD_W_FE
|
3645 SWAPPER_CTRL_RXD_W_SE
|
3646 SWAPPER_CTRL_RXF_W_FE
|
3647 SWAPPER_CTRL_XMSI_FE
|
3648 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3649 if (sp
->intr_type
== INTA
)
3650 val64
|= SWAPPER_CTRL_XMSI_SE
;
3651 writeq(val64
, &bar0
->swapper_ctrl
);
3653 val64
= readq(&bar0
->swapper_ctrl
);
3656 * Verifying if endian settings are accurate by reading a
3657 * feedback register.
3659 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3660 if (val64
!= 0x0123456789ABCDEFULL
) {
3661 /* Endian settings are incorrect, calls for another dekko. */
3662 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3664 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3665 (unsigned long long) val64
);
3672 static int wait_for_msix_trans(struct s2io_nic
*nic
, int i
)
3674 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3676 int ret
= 0, cnt
= 0;
3679 val64
= readq(&bar0
->xmsi_access
);
3680 if (!(val64
& BIT(15)))
3686 DBG_PRINT(ERR_DBG
, "XMSI # %d Access failed\n", i
);
3693 static void restore_xmsi_data(struct s2io_nic
*nic
)
3695 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3699 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3700 writeq(nic
->msix_info
[i
].addr
, &bar0
->xmsi_address
);
3701 writeq(nic
->msix_info
[i
].data
, &bar0
->xmsi_data
);
3702 val64
= (BIT(7) | BIT(15) | vBIT(i
, 26, 6));
3703 writeq(val64
, &bar0
->xmsi_access
);
3704 if (wait_for_msix_trans(nic
, i
)) {
3705 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3711 static void store_xmsi_data(struct s2io_nic
*nic
)
3713 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3714 u64 val64
, addr
, data
;
3717 /* Store and display */
3718 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3719 val64
= (BIT(15) | vBIT(i
, 26, 6));
3720 writeq(val64
, &bar0
->xmsi_access
);
3721 if (wait_for_msix_trans(nic
, i
)) {
3722 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3725 addr
= readq(&bar0
->xmsi_address
);
3726 data
= readq(&bar0
->xmsi_data
);
3728 nic
->msix_info
[i
].addr
= addr
;
3729 nic
->msix_info
[i
].data
= data
;
3734 int s2io_enable_msi(struct s2io_nic
*nic
)
3736 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3737 u16 msi_ctrl
, msg_val
;
3738 struct config_param
*config
= &nic
->config
;
3739 struct net_device
*dev
= nic
->dev
;
3740 u64 val64
, tx_mat
, rx_mat
;
3743 val64
= readq(&bar0
->pic_control
);
3745 writeq(val64
, &bar0
->pic_control
);
3747 err
= pci_enable_msi(nic
->pdev
);
3749 DBG_PRINT(ERR_DBG
, "%s: enabling MSI failed\n",
3755 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3756 * for interrupt handling.
3758 pci_read_config_word(nic
->pdev
, 0x4c, &msg_val
);
3760 pci_write_config_word(nic
->pdev
, 0x4c, msg_val
);
3761 pci_read_config_word(nic
->pdev
, 0x4c, &msg_val
);
3763 pci_read_config_word(nic
->pdev
, 0x42, &msi_ctrl
);
3765 pci_write_config_word(nic
->pdev
, 0x42, msi_ctrl
);
3767 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3768 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3769 for (i
=0; i
<config
->tx_fifo_num
; i
++) {
3770 tx_mat
|= TX_MAT_SET(i
, 1);
3772 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3774 rx_mat
= readq(&bar0
->rx_mat
);
3775 for (i
=0; i
<config
->rx_ring_num
; i
++) {
3776 rx_mat
|= RX_MAT_SET(i
, 1);
3778 writeq(rx_mat
, &bar0
->rx_mat
);
3780 dev
->irq
= nic
->pdev
->irq
;
3784 static int s2io_enable_msi_x(struct s2io_nic
*nic
)
3786 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3788 u16 msi_control
; /* Temp variable */
3789 int ret
, i
, j
, msix_indx
= 1;
3791 nic
->entries
= kmalloc(MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
),
3793 if (nic
->entries
== NULL
) {
3794 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n", \
3796 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3799 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3800 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3801 memset(nic
->entries
, 0,MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3804 kmalloc(MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
),
3806 if (nic
->s2io_entries
== NULL
) {
3807 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n",
3809 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3810 kfree(nic
->entries
);
3811 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3812 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3815 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3816 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3817 memset(nic
->s2io_entries
, 0,
3818 MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3820 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3821 nic
->entries
[i
].entry
= i
;
3822 nic
->s2io_entries
[i
].entry
= i
;
3823 nic
->s2io_entries
[i
].arg
= NULL
;
3824 nic
->s2io_entries
[i
].in_use
= 0;
3827 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3828 for (i
=0; i
<nic
->config
.tx_fifo_num
; i
++, msix_indx
++) {
3829 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3830 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.fifos
[i
];
3831 nic
->s2io_entries
[msix_indx
].type
= MSIX_FIFO_TYPE
;
3832 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3834 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3836 if (!nic
->config
.bimodal
) {
3837 rx_mat
= readq(&bar0
->rx_mat
);
3838 for (j
=0; j
<nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3839 rx_mat
|= RX_MAT_SET(j
, msix_indx
);
3840 nic
->s2io_entries
[msix_indx
].arg
3841 = &nic
->mac_control
.rings
[j
];
3842 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3843 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3845 writeq(rx_mat
, &bar0
->rx_mat
);
3847 tx_mat
= readq(&bar0
->tx_mat0_n
[7]);
3848 for (j
=0; j
<nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3849 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3850 nic
->s2io_entries
[msix_indx
].arg
3851 = &nic
->mac_control
.rings
[j
];
3852 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3853 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3855 writeq(tx_mat
, &bar0
->tx_mat0_n
[7]);
3858 nic
->avail_msix_vectors
= 0;
3859 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, MAX_REQUESTED_MSI_X
);
3860 /* We fail init if error or we get less vectors than min required */
3861 if (ret
>= (nic
->config
.tx_fifo_num
+ nic
->config
.rx_ring_num
+ 1)) {
3862 nic
->avail_msix_vectors
= ret
;
3863 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, ret
);
3866 DBG_PRINT(ERR_DBG
, "%s: Enabling MSIX failed\n", nic
->dev
->name
);
3867 kfree(nic
->entries
);
3868 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3869 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3870 kfree(nic
->s2io_entries
);
3871 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3872 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3873 nic
->entries
= NULL
;
3874 nic
->s2io_entries
= NULL
;
3875 nic
->avail_msix_vectors
= 0;
3878 if (!nic
->avail_msix_vectors
)
3879 nic
->avail_msix_vectors
= MAX_REQUESTED_MSI_X
;
3882 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3883 * in the herc NIC. (Temp change, needs to be removed later)
3885 pci_read_config_word(nic
->pdev
, 0x42, &msi_control
);
3886 msi_control
|= 0x1; /* Enable MSI */
3887 pci_write_config_word(nic
->pdev
, 0x42, msi_control
);
3892 /* ********************************************************* *
3893 * Functions defined below concern the OS part of the driver *
3894 * ********************************************************* */
3897 * s2io_open - open entry point of the driver
3898 * @dev : pointer to the device structure.
3900 * This function is the open entry point of the driver. It mainly calls a
3901 * function to allocate Rx buffers and inserts them into the buffer
3902 * descriptors and then enables the Rx part of the NIC.
3904 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3908 static int s2io_open(struct net_device
*dev
)
3910 struct s2io_nic
*sp
= dev
->priv
;
3914 * Make sure you have link off by default every time
3915 * Nic is initialized
3917 netif_carrier_off(dev
);
3918 sp
->last_link_state
= 0;
3920 /* Initialize H/W and enable interrupts */
3921 err
= s2io_card_up(sp
);
3923 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
3925 goto hw_init_failed
;
3928 if (s2io_set_mac_addr(dev
, dev
->dev_addr
) == FAILURE
) {
3929 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
3932 goto hw_init_failed
;
3935 netif_start_queue(dev
);
3939 if (sp
->intr_type
== MSI_X
) {
3942 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
3943 += (MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3945 if (sp
->s2io_entries
) {
3946 kfree(sp
->s2io_entries
);
3947 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
3948 += (MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3955 * s2io_close -close entry point of the driver
3956 * @dev : device pointer.
3958 * This is the stop entry point of the driver. It needs to undo exactly
3959 * whatever was done by the open entry point,thus it's usually referred to
3960 * as the close function.Among other things this function mainly stops the
3961 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3963 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3967 static int s2io_close(struct net_device
*dev
)
3969 struct s2io_nic
*sp
= dev
->priv
;
3971 netif_stop_queue(dev
);
3972 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3979 * s2io_xmit - Tx entry point of te driver
3980 * @skb : the socket buffer containing the Tx data.
3981 * @dev : device pointer.
3983 * This function is the Tx entry point of the driver. S2IO NIC supports
3984 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3985 * NOTE: when device cant queue the pkt,just the trans_start variable will
3988 * 0 on success & 1 on failure.
3991 static int s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3993 struct s2io_nic
*sp
= dev
->priv
;
3994 u16 frg_cnt
, frg_len
, i
, queue
, queue_len
, put_off
, get_off
;
3997 struct TxFIFO_element __iomem
*tx_fifo
;
3998 unsigned long flags
;
4000 int vlan_priority
= 0;
4001 struct mac_info
*mac_control
;
4002 struct config_param
*config
;
4005 mac_control
= &sp
->mac_control
;
4006 config
= &sp
->config
;
4008 DBG_PRINT(TX_DBG
, "%s: In Neterion Tx routine\n", dev
->name
);
4010 if (unlikely(skb
->len
<= 0)) {
4011 DBG_PRINT(TX_DBG
, "%s:Buffer has no data..\n", dev
->name
);
4012 dev_kfree_skb_any(skb
);
4016 spin_lock_irqsave(&sp
->tx_lock
, flags
);
4017 if (atomic_read(&sp
->card_state
) == CARD_DOWN
) {
4018 DBG_PRINT(TX_DBG
, "%s: Card going down for reset\n",
4020 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
4026 /* Get Fifo number to Transmit based on vlan priority */
4027 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
4028 vlan_tag
= vlan_tx_tag_get(skb
);
4029 vlan_priority
= vlan_tag
>> 13;
4030 queue
= config
->fifo_mapping
[vlan_priority
];
4033 put_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_put_info
.offset
;
4034 get_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_get_info
.offset
;
4035 txdp
= (struct TxD
*) mac_control
->fifos
[queue
].list_info
[put_off
].
4038 queue_len
= mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1;
4039 /* Avoid "put" pointer going beyond "get" pointer */
4040 if (txdp
->Host_Control
||
4041 ((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4042 DBG_PRINT(TX_DBG
, "Error in xmit, No free TXDs.\n");
4043 netif_stop_queue(dev
);
4045 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
4049 offload_type
= s2io_offload_type(skb
);
4050 if (offload_type
& (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
4051 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
4052 txdp
->Control_1
|= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb
));
4054 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4056 (TXD_TX_CKO_IPV4_EN
| TXD_TX_CKO_TCP_EN
|
4059 txdp
->Control_1
|= TXD_GATHER_CODE_FIRST
;
4060 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
4061 txdp
->Control_2
|= config
->tx_intr_type
;
4063 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
4064 txdp
->Control_2
|= TXD_VLAN_ENABLE
;
4065 txdp
->Control_2
|= TXD_VLAN_TAG(vlan_tag
);
4068 frg_len
= skb
->len
- skb
->data_len
;
4069 if (offload_type
== SKB_GSO_UDP
) {
4072 ufo_size
= s2io_udp_mss(skb
);
4074 txdp
->Control_1
|= TXD_UFO_EN
;
4075 txdp
->Control_1
|= TXD_UFO_MSS(ufo_size
);
4076 txdp
->Control_1
|= TXD_BUFFER0_SIZE(8);
4078 sp
->ufo_in_band_v
[put_off
] =
4079 (u64
)skb_shinfo(skb
)->ip6_frag_id
;
4081 sp
->ufo_in_band_v
[put_off
] =
4082 (u64
)skb_shinfo(skb
)->ip6_frag_id
<< 32;
4084 txdp
->Host_Control
= (unsigned long)sp
->ufo_in_band_v
;
4085 txdp
->Buffer_Pointer
= pci_map_single(sp
->pdev
,
4087 sizeof(u64
), PCI_DMA_TODEVICE
);
4091 txdp
->Buffer_Pointer
= pci_map_single
4092 (sp
->pdev
, skb
->data
, frg_len
, PCI_DMA_TODEVICE
);
4093 txdp
->Host_Control
= (unsigned long) skb
;
4094 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frg_len
);
4095 if (offload_type
== SKB_GSO_UDP
)
4096 txdp
->Control_1
|= TXD_UFO_EN
;
4098 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
4099 /* For fragmented SKB. */
4100 for (i
= 0; i
< frg_cnt
; i
++) {
4101 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
4102 /* A '0' length fragment will be ignored */
4106 txdp
->Buffer_Pointer
= (u64
) pci_map_page
4107 (sp
->pdev
, frag
->page
, frag
->page_offset
,
4108 frag
->size
, PCI_DMA_TODEVICE
);
4109 txdp
->Control_1
= TXD_BUFFER0_SIZE(frag
->size
);
4110 if (offload_type
== SKB_GSO_UDP
)
4111 txdp
->Control_1
|= TXD_UFO_EN
;
4113 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
4115 if (offload_type
== SKB_GSO_UDP
)
4116 frg_cnt
++; /* as Txd0 was used for inband header */
4118 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
4119 val64
= mac_control
->fifos
[queue
].list_info
[put_off
].list_phy_addr
;
4120 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
4122 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
4125 val64
|= TX_FIFO_SPECIAL_FUNC
;
4127 writeq(val64
, &tx_fifo
->List_Control
);
4132 if (put_off
== mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1)
4134 mac_control
->fifos
[queue
].tx_curr_put_info
.offset
= put_off
;
4136 /* Avoid "put" pointer going beyond "get" pointer */
4137 if (((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4138 sp
->mac_control
.stats_info
->sw_stat
.fifo_full_cnt
++;
4140 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4142 netif_stop_queue(dev
);
4144 mac_control
->stats_info
->sw_stat
.mem_allocated
+= skb
->truesize
;
4145 dev
->trans_start
= jiffies
;
4146 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
4152 s2io_alarm_handle(unsigned long data
)
4154 struct s2io_nic
*sp
= (struct s2io_nic
*)data
;
4156 alarm_intr_handler(sp
);
4157 mod_timer(&sp
->alarm_timer
, jiffies
+ HZ
/ 2);
4160 static int s2io_chk_rx_buffers(struct s2io_nic
*sp
, int rng_n
)
4162 int rxb_size
, level
;
4165 rxb_size
= atomic_read(&sp
->rx_bufs_left
[rng_n
]);
4166 level
= rx_buffer_level(sp
, rxb_size
, rng_n
);
4168 if ((level
== PANIC
) && (!TASKLET_IN_USE
)) {
4170 DBG_PRINT(INTR_DBG
, "%s: Rx BD hit ", __FUNCTION__
);
4171 DBG_PRINT(INTR_DBG
, "PANIC levels\n");
4172 if ((ret
= fill_rx_buffers(sp
, rng_n
)) == -ENOMEM
) {
4173 DBG_PRINT(INFO_DBG
, "Out of memory in %s",
4175 clear_bit(0, (&sp
->tasklet_status
));
4178 clear_bit(0, (&sp
->tasklet_status
));
4179 } else if (level
== LOW
)
4180 tasklet_schedule(&sp
->task
);
4182 } else if (fill_rx_buffers(sp
, rng_n
) == -ENOMEM
) {
4183 DBG_PRINT(INFO_DBG
, "%s:Out of memory", sp
->dev
->name
);
4184 DBG_PRINT(INFO_DBG
, " in Rx Intr!!\n");
4189 static irqreturn_t
s2io_msi_handle(int irq
, void *dev_id
)
4191 struct net_device
*dev
= (struct net_device
*) dev_id
;
4192 struct s2io_nic
*sp
= dev
->priv
;
4194 struct mac_info
*mac_control
;
4195 struct config_param
*config
;
4197 atomic_inc(&sp
->isr_cnt
);
4198 mac_control
= &sp
->mac_control
;
4199 config
= &sp
->config
;
4200 DBG_PRINT(INTR_DBG
, "%s: MSI handler\n", __FUNCTION__
);
4202 /* If Intr is because of Rx Traffic */
4203 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4204 rx_intr_handler(&mac_control
->rings
[i
]);
4206 /* If Intr is because of Tx Traffic */
4207 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4208 tx_intr_handler(&mac_control
->fifos
[i
]);
4211 * If the Rx buffer count is below the panic threshold then
4212 * reallocate the buffers from the interrupt handler itself,
4213 * else schedule a tasklet to reallocate the buffers.
4215 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4216 s2io_chk_rx_buffers(sp
, i
);
4218 atomic_dec(&sp
->isr_cnt
);
4222 static irqreturn_t
s2io_msix_ring_handle(int irq
, void *dev_id
)
4224 struct ring_info
*ring
= (struct ring_info
*)dev_id
;
4225 struct s2io_nic
*sp
= ring
->nic
;
4227 atomic_inc(&sp
->isr_cnt
);
4229 rx_intr_handler(ring
);
4230 s2io_chk_rx_buffers(sp
, ring
->ring_no
);
4232 atomic_dec(&sp
->isr_cnt
);
4236 static irqreturn_t
s2io_msix_fifo_handle(int irq
, void *dev_id
)
4238 struct fifo_info
*fifo
= (struct fifo_info
*)dev_id
;
4239 struct s2io_nic
*sp
= fifo
->nic
;
4241 atomic_inc(&sp
->isr_cnt
);
4242 tx_intr_handler(fifo
);
4243 atomic_dec(&sp
->isr_cnt
);
4246 static void s2io_txpic_intr_handle(struct s2io_nic
*sp
)
4248 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4251 val64
= readq(&bar0
->pic_int_status
);
4252 if (val64
& PIC_INT_GPIO
) {
4253 val64
= readq(&bar0
->gpio_int_reg
);
4254 if ((val64
& GPIO_INT_REG_LINK_DOWN
) &&
4255 (val64
& GPIO_INT_REG_LINK_UP
)) {
4257 * This is unstable state so clear both up/down
4258 * interrupt and adapter to re-evaluate the link state.
4260 val64
|= GPIO_INT_REG_LINK_DOWN
;
4261 val64
|= GPIO_INT_REG_LINK_UP
;
4262 writeq(val64
, &bar0
->gpio_int_reg
);
4263 val64
= readq(&bar0
->gpio_int_mask
);
4264 val64
&= ~(GPIO_INT_MASK_LINK_UP
|
4265 GPIO_INT_MASK_LINK_DOWN
);
4266 writeq(val64
, &bar0
->gpio_int_mask
);
4268 else if (val64
& GPIO_INT_REG_LINK_UP
) {
4269 val64
= readq(&bar0
->adapter_status
);
4270 /* Enable Adapter */
4271 val64
= readq(&bar0
->adapter_control
);
4272 val64
|= ADAPTER_CNTL_EN
;
4273 writeq(val64
, &bar0
->adapter_control
);
4274 val64
|= ADAPTER_LED_ON
;
4275 writeq(val64
, &bar0
->adapter_control
);
4276 if (!sp
->device_enabled_once
)
4277 sp
->device_enabled_once
= 1;
4279 s2io_link(sp
, LINK_UP
);
4281 * unmask link down interrupt and mask link-up
4284 val64
= readq(&bar0
->gpio_int_mask
);
4285 val64
&= ~GPIO_INT_MASK_LINK_DOWN
;
4286 val64
|= GPIO_INT_MASK_LINK_UP
;
4287 writeq(val64
, &bar0
->gpio_int_mask
);
4289 }else if (val64
& GPIO_INT_REG_LINK_DOWN
) {
4290 val64
= readq(&bar0
->adapter_status
);
4291 s2io_link(sp
, LINK_DOWN
);
4292 /* Link is down so unmaks link up interrupt */
4293 val64
= readq(&bar0
->gpio_int_mask
);
4294 val64
&= ~GPIO_INT_MASK_LINK_UP
;
4295 val64
|= GPIO_INT_MASK_LINK_DOWN
;
4296 writeq(val64
, &bar0
->gpio_int_mask
);
4299 val64
= readq(&bar0
->adapter_control
);
4300 val64
= val64
&(~ADAPTER_LED_ON
);
4301 writeq(val64
, &bar0
->adapter_control
);
4304 val64
= readq(&bar0
->gpio_int_mask
);
4308 * s2io_isr - ISR handler of the device .
4309 * @irq: the irq of the device.
4310 * @dev_id: a void pointer to the dev structure of the NIC.
4311 * Description: This function is the ISR handler of the device. It
4312 * identifies the reason for the interrupt and calls the relevant
4313 * service routines. As a contongency measure, this ISR allocates the
4314 * recv buffers, if their numbers are below the panic value which is
4315 * presently set to 25% of the original number of rcv buffers allocated.
4317 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4318 * IRQ_NONE: will be returned if interrupt is not from our device
4320 static irqreturn_t
s2io_isr(int irq
, void *dev_id
)
4322 struct net_device
*dev
= (struct net_device
*) dev_id
;
4323 struct s2io_nic
*sp
= dev
->priv
;
4324 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4327 struct mac_info
*mac_control
;
4328 struct config_param
*config
;
4330 /* Pretend we handled any irq's from a disconnected card */
4331 if (pci_channel_offline(sp
->pdev
))
4334 atomic_inc(&sp
->isr_cnt
);
4335 mac_control
= &sp
->mac_control
;
4336 config
= &sp
->config
;
4339 * Identify the cause for interrupt and call the appropriate
4340 * interrupt handler. Causes for the interrupt could be;
4344 * 4. Error in any functional blocks of the NIC.
4346 reason
= readq(&bar0
->general_int_status
);
4349 /* The interrupt was not raised by us. */
4350 atomic_dec(&sp
->isr_cnt
);
4353 else if (unlikely(reason
== S2IO_MINUS_ONE
) ) {
4354 /* Disable device and get out */
4355 atomic_dec(&sp
->isr_cnt
);
4360 if (reason
& GEN_INTR_RXTRAFFIC
) {
4361 if ( likely ( netif_rx_schedule_prep(dev
)) ) {
4362 __netif_rx_schedule(dev
);
4363 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_mask
);
4366 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4370 * Rx handler is called by default, without checking for the
4371 * cause of interrupt.
4372 * rx_traffic_int reg is an R1 register, writing all 1's
4373 * will ensure that the actual interrupt causing bit get's
4374 * cleared and hence a read can be avoided.
4376 if (reason
& GEN_INTR_RXTRAFFIC
)
4377 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4379 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
4380 rx_intr_handler(&mac_control
->rings
[i
]);
4385 * tx_traffic_int reg is an R1 register, writing all 1's
4386 * will ensure that the actual interrupt causing bit get's
4387 * cleared and hence a read can be avoided.
4389 if (reason
& GEN_INTR_TXTRAFFIC
)
4390 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4392 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4393 tx_intr_handler(&mac_control
->fifos
[i
]);
4395 if (reason
& GEN_INTR_TXPIC
)
4396 s2io_txpic_intr_handle(sp
);
4398 * If the Rx buffer count is below the panic threshold then
4399 * reallocate the buffers from the interrupt handler itself,
4400 * else schedule a tasklet to reallocate the buffers.
4403 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4404 s2io_chk_rx_buffers(sp
, i
);
4407 writeq(0, &bar0
->general_int_mask
);
4408 readl(&bar0
->general_int_status
);
4410 atomic_dec(&sp
->isr_cnt
);
4417 static void s2io_updt_stats(struct s2io_nic
*sp
)
4419 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4423 if (atomic_read(&sp
->card_state
) == CARD_UP
) {
4424 /* Apprx 30us on a 133 MHz bus */
4425 val64
= SET_UPDT_CLICKS(10) |
4426 STAT_CFG_ONE_SHOT_EN
| STAT_CFG_STAT_EN
;
4427 writeq(val64
, &bar0
->stat_cfg
);
4430 val64
= readq(&bar0
->stat_cfg
);
4431 if (!(val64
& BIT(0)))
4435 break; /* Updt failed */
4441 * s2io_get_stats - Updates the device statistics structure.
4442 * @dev : pointer to the device structure.
4444 * This function updates the device statistics structure in the s2io_nic
4445 * structure and returns a pointer to the same.
4447 * pointer to the updated net_device_stats structure.
4450 static struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
4452 struct s2io_nic
*sp
= dev
->priv
;
4453 struct mac_info
*mac_control
;
4454 struct config_param
*config
;
4457 mac_control
= &sp
->mac_control
;
4458 config
= &sp
->config
;
4460 /* Configure Stats for immediate updt */
4461 s2io_updt_stats(sp
);
4463 sp
->stats
.tx_packets
=
4464 le32_to_cpu(mac_control
->stats_info
->tmac_frms
);
4465 sp
->stats
.tx_errors
=
4466 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
);
4467 sp
->stats
.rx_errors
=
4468 le64_to_cpu(mac_control
->stats_info
->rmac_drop_frms
);
4469 sp
->stats
.multicast
=
4470 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
);
4471 sp
->stats
.rx_length_errors
=
4472 le64_to_cpu(mac_control
->stats_info
->rmac_long_frms
);
4474 return (&sp
->stats
);
4478 * s2io_set_multicast - entry point for multicast address enable/disable.
4479 * @dev : pointer to the device structure
4481 * This function is a driver entry point which gets called by the kernel
4482 * whenever multicast addresses must be enabled/disabled. This also gets
4483 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4484 * determine, if multicast address must be enabled or if promiscuous mode
4485 * is to be disabled etc.
4490 static void s2io_set_multicast(struct net_device
*dev
)
4493 struct dev_mc_list
*mclist
;
4494 struct s2io_nic
*sp
= dev
->priv
;
4495 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4496 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
4498 u64 dis_addr
= 0xffffffffffffULL
, mac_addr
= 0;
4501 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
4502 /* Enable all Multicast addresses */
4503 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
4504 &bar0
->rmac_addr_data0_mem
);
4505 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
4506 &bar0
->rmac_addr_data1_mem
);
4507 val64
= RMAC_ADDR_CMD_MEM_WE
|
4508 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4509 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET
);
4510 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4511 /* Wait till command completes */
4512 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4513 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4517 sp
->all_multi_pos
= MAC_MC_ALL_MC_ADDR_OFFSET
;
4518 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
4519 /* Disable all Multicast addresses */
4520 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4521 &bar0
->rmac_addr_data0_mem
);
4522 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4523 &bar0
->rmac_addr_data1_mem
);
4524 val64
= RMAC_ADDR_CMD_MEM_WE
|
4525 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4526 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
4527 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4528 /* Wait till command completes */
4529 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4530 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4534 sp
->all_multi_pos
= 0;
4537 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
4538 /* Put the NIC into promiscuous mode */
4539 add
= &bar0
->mac_cfg
;
4540 val64
= readq(&bar0
->mac_cfg
);
4541 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
4543 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4544 writel((u32
) val64
, add
);
4545 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4546 writel((u32
) (val64
>> 32), (add
+ 4));
4548 if (vlan_tag_strip
!= 1) {
4549 val64
= readq(&bar0
->rx_pa_cfg
);
4550 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
4551 writeq(val64
, &bar0
->rx_pa_cfg
);
4552 vlan_strip_flag
= 0;
4555 val64
= readq(&bar0
->mac_cfg
);
4556 sp
->promisc_flg
= 1;
4557 DBG_PRINT(INFO_DBG
, "%s: entered promiscuous mode\n",
4559 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
4560 /* Remove the NIC from promiscuous mode */
4561 add
= &bar0
->mac_cfg
;
4562 val64
= readq(&bar0
->mac_cfg
);
4563 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
4565 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4566 writel((u32
) val64
, add
);
4567 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4568 writel((u32
) (val64
>> 32), (add
+ 4));
4570 if (vlan_tag_strip
!= 0) {
4571 val64
= readq(&bar0
->rx_pa_cfg
);
4572 val64
|= RX_PA_CFG_STRIP_VLAN_TAG
;
4573 writeq(val64
, &bar0
->rx_pa_cfg
);
4574 vlan_strip_flag
= 1;
4577 val64
= readq(&bar0
->mac_cfg
);
4578 sp
->promisc_flg
= 0;
4579 DBG_PRINT(INFO_DBG
, "%s: left promiscuous mode\n",
4583 /* Update individual M_CAST address list */
4584 if ((!sp
->m_cast_flg
) && dev
->mc_count
) {
4586 (MAX_ADDRS_SUPPORTED
- MAC_MC_ADDR_START_OFFSET
- 1)) {
4587 DBG_PRINT(ERR_DBG
, "%s: No more Rx filters ",
4589 DBG_PRINT(ERR_DBG
, "can be added, please enable ");
4590 DBG_PRINT(ERR_DBG
, "ALL_MULTI instead\n");
4594 prev_cnt
= sp
->mc_addr_count
;
4595 sp
->mc_addr_count
= dev
->mc_count
;
4597 /* Clear out the previous list of Mc in the H/W. */
4598 for (i
= 0; i
< prev_cnt
; i
++) {
4599 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4600 &bar0
->rmac_addr_data0_mem
);
4601 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4602 &bar0
->rmac_addr_data1_mem
);
4603 val64
= RMAC_ADDR_CMD_MEM_WE
|
4604 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4605 RMAC_ADDR_CMD_MEM_OFFSET
4606 (MAC_MC_ADDR_START_OFFSET
+ i
);
4607 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4609 /* Wait for command completes */
4610 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4611 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4613 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4615 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4620 /* Create the new Rx filter list and update the same in H/W. */
4621 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
4622 i
++, mclist
= mclist
->next
) {
4623 memcpy(sp
->usr_addrs
[i
].addr
, mclist
->dmi_addr
,
4626 for (j
= 0; j
< ETH_ALEN
; j
++) {
4627 mac_addr
|= mclist
->dmi_addr
[j
];
4631 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4632 &bar0
->rmac_addr_data0_mem
);
4633 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4634 &bar0
->rmac_addr_data1_mem
);
4635 val64
= RMAC_ADDR_CMD_MEM_WE
|
4636 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4637 RMAC_ADDR_CMD_MEM_OFFSET
4638 (i
+ MAC_MC_ADDR_START_OFFSET
);
4639 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4641 /* Wait for command completes */
4642 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4643 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4645 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4647 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4655 * s2io_set_mac_addr - Programs the Xframe mac address
4656 * @dev : pointer to the device structure.
4657 * @addr: a uchar pointer to the new mac address which is to be set.
4658 * Description : This procedure will program the Xframe to receive
4659 * frames with new Mac Address
4660 * Return value: SUCCESS on success and an appropriate (-)ve integer
4661 * as defined in errno.h file on failure.
4664 static int s2io_set_mac_addr(struct net_device
*dev
, u8
* addr
)
4666 struct s2io_nic
*sp
= dev
->priv
;
4667 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4668 register u64 val64
, mac_addr
= 0;
4670 u64 old_mac_addr
= 0;
4673 * Set the new MAC address as the new unicast filter and reflect this
4674 * change on the device address registered with the OS. It will be
4677 for (i
= 0; i
< ETH_ALEN
; i
++) {
4679 mac_addr
|= addr
[i
];
4681 old_mac_addr
|= sp
->def_mac_addr
[0].mac_addr
[i
];
4687 /* Update the internal structure with this new mac address */
4688 if(mac_addr
!= old_mac_addr
) {
4689 memset(sp
->def_mac_addr
[0].mac_addr
, 0, sizeof(ETH_ALEN
));
4690 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_addr
);
4691 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_addr
>> 8);
4692 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_addr
>> 16);
4693 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_addr
>> 24);
4694 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_addr
>> 32);
4695 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_addr
>> 40);
4698 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4699 &bar0
->rmac_addr_data0_mem
);
4702 RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4703 RMAC_ADDR_CMD_MEM_OFFSET(0);
4704 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4705 /* Wait till command completes */
4706 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4707 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
, S2IO_BIT_RESET
)) {
4708 DBG_PRINT(ERR_DBG
, "%s: set_mac_addr failed\n", dev
->name
);
4716 * s2io_ethtool_sset - Sets different link parameters.
4717 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4718 * @info: pointer to the structure with parameters given by ethtool to set
4721 * The function sets different link parameters provided by the user onto
4727 static int s2io_ethtool_sset(struct net_device
*dev
,
4728 struct ethtool_cmd
*info
)
4730 struct s2io_nic
*sp
= dev
->priv
;
4731 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
4732 (info
->speed
!= SPEED_10000
) || (info
->duplex
!= DUPLEX_FULL
))
4735 s2io_close(sp
->dev
);
4743 * s2io_ethtol_gset - Return link specific information.
4744 * @sp : private member of the device structure, pointer to the
4745 * s2io_nic structure.
4746 * @info : pointer to the structure with parameters given by ethtool
4747 * to return link information.
4749 * Returns link specific information like speed, duplex etc.. to ethtool.
4751 * return 0 on success.
4754 static int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
4756 struct s2io_nic
*sp
= dev
->priv
;
4757 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4758 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4759 info
->port
= PORT_FIBRE
;
4760 /* info->transceiver?? TODO */
4762 if (netif_carrier_ok(sp
->dev
)) {
4763 info
->speed
= 10000;
4764 info
->duplex
= DUPLEX_FULL
;
4770 info
->autoneg
= AUTONEG_DISABLE
;
4775 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4776 * @sp : private member of the device structure, which is a pointer to the
4777 * s2io_nic structure.
4778 * @info : pointer to the structure with parameters given by ethtool to
4779 * return driver information.
4781 * Returns driver specefic information like name, version etc.. to ethtool.
4786 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
4787 struct ethtool_drvinfo
*info
)
4789 struct s2io_nic
*sp
= dev
->priv
;
4791 strncpy(info
->driver
, s2io_driver_name
, sizeof(info
->driver
));
4792 strncpy(info
->version
, s2io_driver_version
, sizeof(info
->version
));
4793 strncpy(info
->fw_version
, "", sizeof(info
->fw_version
));
4794 strncpy(info
->bus_info
, pci_name(sp
->pdev
), sizeof(info
->bus_info
));
4795 info
->regdump_len
= XENA_REG_SPACE
;
4796 info
->eedump_len
= XENA_EEPROM_SPACE
;
4797 info
->testinfo_len
= S2IO_TEST_LEN
;
4799 if (sp
->device_type
== XFRAME_I_DEVICE
)
4800 info
->n_stats
= XFRAME_I_STAT_LEN
;
4802 info
->n_stats
= XFRAME_II_STAT_LEN
;
4806 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4807 * @sp: private member of the device structure, which is a pointer to the
4808 * s2io_nic structure.
4809 * @regs : pointer to the structure with parameters given by ethtool for
4810 * dumping the registers.
4811 * @reg_space: The input argumnet into which all the registers are dumped.
4813 * Dumps the entire register space of xFrame NIC into the user given
4819 static void s2io_ethtool_gregs(struct net_device
*dev
,
4820 struct ethtool_regs
*regs
, void *space
)
4824 u8
*reg_space
= (u8
*) space
;
4825 struct s2io_nic
*sp
= dev
->priv
;
4827 regs
->len
= XENA_REG_SPACE
;
4828 regs
->version
= sp
->pdev
->subsystem_device
;
4830 for (i
= 0; i
< regs
->len
; i
+= 8) {
4831 reg
= readq(sp
->bar0
+ i
);
4832 memcpy((reg_space
+ i
), ®
, 8);
4837 * s2io_phy_id - timer function that alternates adapter LED.
4838 * @data : address of the private member of the device structure, which
4839 * is a pointer to the s2io_nic structure, provided as an u32.
4840 * Description: This is actually the timer function that alternates the
4841 * adapter LED bit of the adapter control bit to set/reset every time on
4842 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4843 * once every second.
4845 static void s2io_phy_id(unsigned long data
)
4847 struct s2io_nic
*sp
= (struct s2io_nic
*) data
;
4848 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4852 subid
= sp
->pdev
->subsystem_device
;
4853 if ((sp
->device_type
== XFRAME_II_DEVICE
) ||
4854 ((subid
& 0xFF) >= 0x07)) {
4855 val64
= readq(&bar0
->gpio_control
);
4856 val64
^= GPIO_CTRL_GPIO_0
;
4857 writeq(val64
, &bar0
->gpio_control
);
4859 val64
= readq(&bar0
->adapter_control
);
4860 val64
^= ADAPTER_LED_ON
;
4861 writeq(val64
, &bar0
->adapter_control
);
4864 mod_timer(&sp
->id_timer
, jiffies
+ HZ
/ 2);
4868 * s2io_ethtool_idnic - To physically identify the nic on the system.
4869 * @sp : private member of the device structure, which is a pointer to the
4870 * s2io_nic structure.
4871 * @id : pointer to the structure with identification parameters given by
4873 * Description: Used to physically identify the NIC on the system.
4874 * The Link LED will blink for a time specified by the user for
4876 * NOTE: The Link has to be Up to be able to blink the LED. Hence
4877 * identification is possible only if it's link is up.
4879 * int , returns 0 on success
4882 static int s2io_ethtool_idnic(struct net_device
*dev
, u32 data
)
4884 u64 val64
= 0, last_gpio_ctrl_val
;
4885 struct s2io_nic
*sp
= dev
->priv
;
4886 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4889 subid
= sp
->pdev
->subsystem_device
;
4890 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
4891 if ((sp
->device_type
== XFRAME_I_DEVICE
) &&
4892 ((subid
& 0xFF) < 0x07)) {
4893 val64
= readq(&bar0
->adapter_control
);
4894 if (!(val64
& ADAPTER_CNTL_EN
)) {
4896 "Adapter Link down, cannot blink LED\n");
4900 if (sp
->id_timer
.function
== NULL
) {
4901 init_timer(&sp
->id_timer
);
4902 sp
->id_timer
.function
= s2io_phy_id
;
4903 sp
->id_timer
.data
= (unsigned long) sp
;
4905 mod_timer(&sp
->id_timer
, jiffies
);
4907 msleep_interruptible(data
* HZ
);
4909 msleep_interruptible(MAX_FLICKER_TIME
);
4910 del_timer_sync(&sp
->id_timer
);
4912 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp
->device_type
, subid
)) {
4913 writeq(last_gpio_ctrl_val
, &bar0
->gpio_control
);
4914 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
4920 static void s2io_ethtool_gringparam(struct net_device
*dev
,
4921 struct ethtool_ringparam
*ering
)
4923 struct s2io_nic
*sp
= dev
->priv
;
4924 int i
,tx_desc_count
=0,rx_desc_count
=0;
4926 if (sp
->rxd_mode
== RXD_MODE_1
)
4927 ering
->rx_max_pending
= MAX_RX_DESC_1
;
4928 else if (sp
->rxd_mode
== RXD_MODE_3B
)
4929 ering
->rx_max_pending
= MAX_RX_DESC_2
;
4930 else if (sp
->rxd_mode
== RXD_MODE_3A
)
4931 ering
->rx_max_pending
= MAX_RX_DESC_3
;
4933 ering
->tx_max_pending
= MAX_TX_DESC
;
4934 for (i
= 0 ; i
< sp
->config
.tx_fifo_num
; i
++) {
4935 tx_desc_count
+= sp
->config
.tx_cfg
[i
].fifo_len
;
4937 DBG_PRINT(INFO_DBG
,"\nmax txds : %d\n",sp
->config
.max_txds
);
4938 ering
->tx_pending
= tx_desc_count
;
4940 for (i
= 0 ; i
< sp
->config
.rx_ring_num
; i
++) {
4941 rx_desc_count
+= sp
->config
.rx_cfg
[i
].num_rxd
;
4943 ering
->rx_pending
= rx_desc_count
;
4945 ering
->rx_mini_max_pending
= 0;
4946 ering
->rx_mini_pending
= 0;
4947 if(sp
->rxd_mode
== RXD_MODE_1
)
4948 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_1
;
4949 else if (sp
->rxd_mode
== RXD_MODE_3B
)
4950 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_2
;
4951 ering
->rx_jumbo_pending
= rx_desc_count
;
4955 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4956 * @sp : private member of the device structure, which is a pointer to the
4957 * s2io_nic structure.
4958 * @ep : pointer to the structure with pause parameters given by ethtool.
4960 * Returns the Pause frame generation and reception capability of the NIC.
4964 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
4965 struct ethtool_pauseparam
*ep
)
4968 struct s2io_nic
*sp
= dev
->priv
;
4969 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4971 val64
= readq(&bar0
->rmac_pause_cfg
);
4972 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
4973 ep
->tx_pause
= TRUE
;
4974 if (val64
& RMAC_PAUSE_RX_ENABLE
)
4975 ep
->rx_pause
= TRUE
;
4976 ep
->autoneg
= FALSE
;
4980 * s2io_ethtool_setpause_data - set/reset pause frame generation.
4981 * @sp : private member of the device structure, which is a pointer to the
4982 * s2io_nic structure.
4983 * @ep : pointer to the structure with pause parameters given by ethtool.
4985 * It can be used to set or reset Pause frame generation or reception
4986 * support of the NIC.
4988 * int, returns 0 on Success
4991 static int s2io_ethtool_setpause_data(struct net_device
*dev
,
4992 struct ethtool_pauseparam
*ep
)
4995 struct s2io_nic
*sp
= dev
->priv
;
4996 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4998 val64
= readq(&bar0
->rmac_pause_cfg
);
5000 val64
|= RMAC_PAUSE_GEN_ENABLE
;
5002 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
5004 val64
|= RMAC_PAUSE_RX_ENABLE
;
5006 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
5007 writeq(val64
, &bar0
->rmac_pause_cfg
);
5012 * read_eeprom - reads 4 bytes of data from user given offset.
5013 * @sp : private member of the device structure, which is a pointer to the
5014 * s2io_nic structure.
5015 * @off : offset at which the data must be written
5016 * @data : Its an output parameter where the data read at the given
5019 * Will read 4 bytes of data from the user given offset and return the
5021 * NOTE: Will allow to read only part of the EEPROM visible through the
5024 * -1 on failure and 0 on success.
5027 #define S2IO_DEV_ID 5
5028 static int read_eeprom(struct s2io_nic
* sp
, int off
, u64
* data
)
5033 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5035 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5036 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5037 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ
|
5038 I2C_CONTROL_CNTL_START
;
5039 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5041 while (exit_cnt
< 5) {
5042 val64
= readq(&bar0
->i2c_control
);
5043 if (I2C_CONTROL_CNTL_END(val64
)) {
5044 *data
= I2C_CONTROL_GET_DATA(val64
);
5053 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5054 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5055 SPI_CONTROL_BYTECNT(0x3) |
5056 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off
);
5057 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5058 val64
|= SPI_CONTROL_REQ
;
5059 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5060 while (exit_cnt
< 5) {
5061 val64
= readq(&bar0
->spi_control
);
5062 if (val64
& SPI_CONTROL_NACK
) {
5065 } else if (val64
& SPI_CONTROL_DONE
) {
5066 *data
= readq(&bar0
->spi_data
);
5079 * write_eeprom - actually writes the relevant part of the data value.
5080 * @sp : private member of the device structure, which is a pointer to the
5081 * s2io_nic structure.
5082 * @off : offset at which the data must be written
5083 * @data : The data that is to be written
5084 * @cnt : Number of bytes of the data that are actually to be written into
5085 * the Eeprom. (max of 3)
5087 * Actually writes the relevant part of the data value into the Eeprom
5088 * through the I2C bus.
5090 * 0 on success, -1 on failure.
5093 static int write_eeprom(struct s2io_nic
* sp
, int off
, u64 data
, int cnt
)
5095 int exit_cnt
= 0, ret
= -1;
5097 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5099 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5100 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5101 I2C_CONTROL_BYTE_CNT(cnt
) | I2C_CONTROL_SET_DATA((u32
)data
) |
5102 I2C_CONTROL_CNTL_START
;
5103 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5105 while (exit_cnt
< 5) {
5106 val64
= readq(&bar0
->i2c_control
);
5107 if (I2C_CONTROL_CNTL_END(val64
)) {
5108 if (!(val64
& I2C_CONTROL_NACK
))
5117 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5118 int write_cnt
= (cnt
== 8) ? 0 : cnt
;
5119 writeq(SPI_DATA_WRITE(data
,(cnt
<<3)), &bar0
->spi_data
);
5121 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5122 SPI_CONTROL_BYTECNT(write_cnt
) |
5123 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off
);
5124 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5125 val64
|= SPI_CONTROL_REQ
;
5126 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5127 while (exit_cnt
< 5) {
5128 val64
= readq(&bar0
->spi_control
);
5129 if (val64
& SPI_CONTROL_NACK
) {
5132 } else if (val64
& SPI_CONTROL_DONE
) {
5142 static void s2io_vpd_read(struct s2io_nic
*nic
)
5146 int i
=0, cnt
, fail
= 0;
5147 int vpd_addr
= 0x80;
5149 if (nic
->device_type
== XFRAME_II_DEVICE
) {
5150 strcpy(nic
->product_name
, "Xframe II 10GbE network adapter");
5154 strcpy(nic
->product_name
, "Xframe I 10GbE network adapter");
5157 strcpy(nic
->serial_num
, "NOT AVAILABLE");
5159 vpd_data
= kmalloc(256, GFP_KERNEL
);
5161 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
5164 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
+= 256;
5166 for (i
= 0; i
< 256; i
+=4 ) {
5167 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 2), i
);
5168 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 2), &data
);
5169 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 3), 0);
5170 for (cnt
= 0; cnt
<5; cnt
++) {
5172 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 3), &data
);
5177 DBG_PRINT(ERR_DBG
, "Read of VPD data failed\n");
5181 pci_read_config_dword(nic
->pdev
, (vpd_addr
+ 4),
5182 (u32
*)&vpd_data
[i
]);
5186 /* read serial number of adapter */
5187 for (cnt
= 0; cnt
< 256; cnt
++) {
5188 if ((vpd_data
[cnt
] == 'S') &&
5189 (vpd_data
[cnt
+1] == 'N') &&
5190 (vpd_data
[cnt
+2] < VPD_STRING_LEN
)) {
5191 memset(nic
->serial_num
, 0, VPD_STRING_LEN
);
5192 memcpy(nic
->serial_num
, &vpd_data
[cnt
+ 3],
5199 if ((!fail
) && (vpd_data
[1] < VPD_STRING_LEN
)) {
5200 memset(nic
->product_name
, 0, vpd_data
[1]);
5201 memcpy(nic
->product_name
, &vpd_data
[3], vpd_data
[1]);
5204 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= 256;
5208 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5209 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5210 * @eeprom : pointer to the user level structure provided by ethtool,
5211 * containing all relevant information.
5212 * @data_buf : user defined value to be written into Eeprom.
5213 * Description: Reads the values stored in the Eeprom at given offset
5214 * for a given length. Stores these values int the input argument data
5215 * buffer 'data_buf' and returns these to the caller (ethtool.)
5220 static int s2io_ethtool_geeprom(struct net_device
*dev
,
5221 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
5225 struct s2io_nic
*sp
= dev
->priv
;
5227 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
5229 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
5230 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
5232 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
5233 if (read_eeprom(sp
, (eeprom
->offset
+ i
), &data
)) {
5234 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
5238 memcpy((data_buf
+ i
), &valid
, 4);
5244 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5245 * @sp : private member of the device structure, which is a pointer to the
5246 * s2io_nic structure.
5247 * @eeprom : pointer to the user level structure provided by ethtool,
5248 * containing all relevant information.
5249 * @data_buf ; user defined value to be written into Eeprom.
5251 * Tries to write the user provided value in the Eeprom, at the offset
5252 * given by the user.
5254 * 0 on success, -EFAULT on failure.
5257 static int s2io_ethtool_seeprom(struct net_device
*dev
,
5258 struct ethtool_eeprom
*eeprom
,
5261 int len
= eeprom
->len
, cnt
= 0;
5262 u64 valid
= 0, data
;
5263 struct s2io_nic
*sp
= dev
->priv
;
5265 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
5267 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5268 DBG_PRINT(ERR_DBG
, "is wrong, Its not 0x%x\n",
5274 data
= (u32
) data_buf
[cnt
] & 0x000000FF;
5276 valid
= (u32
) (data
<< 24);
5280 if (write_eeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
5282 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5284 "write into the specified offset\n");
5295 * s2io_register_test - reads and writes into all clock domains.
5296 * @sp : private member of the device structure, which is a pointer to the
5297 * s2io_nic structure.
5298 * @data : variable that returns the result of each of the test conducted b
5301 * Read and write into all clock domains. The NIC has 3 clock domains,
5302 * see that registers in all the three regions are accessible.
5307 static int s2io_register_test(struct s2io_nic
* sp
, uint64_t * data
)
5309 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5310 u64 val64
= 0, exp_val
;
5313 val64
= readq(&bar0
->pif_rd_swapper_fb
);
5314 if (val64
!= 0x123456789abcdefULL
) {
5316 DBG_PRINT(INFO_DBG
, "Read Test level 1 fails\n");
5319 val64
= readq(&bar0
->rmac_pause_cfg
);
5320 if (val64
!= 0xc000ffff00000000ULL
) {
5322 DBG_PRINT(INFO_DBG
, "Read Test level 2 fails\n");
5325 val64
= readq(&bar0
->rx_queue_cfg
);
5326 if (sp
->device_type
== XFRAME_II_DEVICE
)
5327 exp_val
= 0x0404040404040404ULL
;
5329 exp_val
= 0x0808080808080808ULL
;
5330 if (val64
!= exp_val
) {
5332 DBG_PRINT(INFO_DBG
, "Read Test level 3 fails\n");
5335 val64
= readq(&bar0
->xgxs_efifo_cfg
);
5336 if (val64
!= 0x000000001923141EULL
) {
5338 DBG_PRINT(INFO_DBG
, "Read Test level 4 fails\n");
5341 val64
= 0x5A5A5A5A5A5A5A5AULL
;
5342 writeq(val64
, &bar0
->xmsi_data
);
5343 val64
= readq(&bar0
->xmsi_data
);
5344 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
5346 DBG_PRINT(ERR_DBG
, "Write Test level 1 fails\n");
5349 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
5350 writeq(val64
, &bar0
->xmsi_data
);
5351 val64
= readq(&bar0
->xmsi_data
);
5352 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
5354 DBG_PRINT(ERR_DBG
, "Write Test level 2 fails\n");
5362 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5363 * @sp : private member of the device structure, which is a pointer to the
5364 * s2io_nic structure.
5365 * @data:variable that returns the result of each of the test conducted by
5368 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5374 static int s2io_eeprom_test(struct s2io_nic
* sp
, uint64_t * data
)
5377 u64 ret_data
, org_4F0
, org_7F0
;
5378 u8 saved_4F0
= 0, saved_7F0
= 0;
5379 struct net_device
*dev
= sp
->dev
;
5381 /* Test Write Error at offset 0 */
5382 /* Note that SPI interface allows write access to all areas
5383 * of EEPROM. Hence doing all negative testing only for Xframe I.
5385 if (sp
->device_type
== XFRAME_I_DEVICE
)
5386 if (!write_eeprom(sp
, 0, 0, 3))
5389 /* Save current values at offsets 0x4F0 and 0x7F0 */
5390 if (!read_eeprom(sp
, 0x4F0, &org_4F0
))
5392 if (!read_eeprom(sp
, 0x7F0, &org_7F0
))
5395 /* Test Write at offset 4f0 */
5396 if (write_eeprom(sp
, 0x4F0, 0x012345, 3))
5398 if (read_eeprom(sp
, 0x4F0, &ret_data
))
5401 if (ret_data
!= 0x012345) {
5402 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x4F0. "
5403 "Data written %llx Data read %llx\n",
5404 dev
->name
, (unsigned long long)0x12345,
5405 (unsigned long long)ret_data
);
5409 /* Reset the EEPROM data go FFFF */
5410 write_eeprom(sp
, 0x4F0, 0xFFFFFF, 3);
5412 /* Test Write Request Error at offset 0x7c */
5413 if (sp
->device_type
== XFRAME_I_DEVICE
)
5414 if (!write_eeprom(sp
, 0x07C, 0, 3))
5417 /* Test Write Request at offset 0x7f0 */
5418 if (write_eeprom(sp
, 0x7F0, 0x012345, 3))
5420 if (read_eeprom(sp
, 0x7F0, &ret_data
))
5423 if (ret_data
!= 0x012345) {
5424 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x7F0. "
5425 "Data written %llx Data read %llx\n",
5426 dev
->name
, (unsigned long long)0x12345,
5427 (unsigned long long)ret_data
);
5431 /* Reset the EEPROM data go FFFF */
5432 write_eeprom(sp
, 0x7F0, 0xFFFFFF, 3);
5434 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5435 /* Test Write Error at offset 0x80 */
5436 if (!write_eeprom(sp
, 0x080, 0, 3))
5439 /* Test Write Error at offset 0xfc */
5440 if (!write_eeprom(sp
, 0x0FC, 0, 3))
5443 /* Test Write Error at offset 0x100 */
5444 if (!write_eeprom(sp
, 0x100, 0, 3))
5447 /* Test Write Error at offset 4ec */
5448 if (!write_eeprom(sp
, 0x4EC, 0, 3))
5452 /* Restore values at offsets 0x4F0 and 0x7F0 */
5454 write_eeprom(sp
, 0x4F0, org_4F0
, 3);
5456 write_eeprom(sp
, 0x7F0, org_7F0
, 3);
5463 * s2io_bist_test - invokes the MemBist test of the card .
5464 * @sp : private member of the device structure, which is a pointer to the
5465 * s2io_nic structure.
5466 * @data:variable that returns the result of each of the test conducted by
5469 * This invokes the MemBist test of the card. We give around
5470 * 2 secs time for the Test to complete. If it's still not complete
5471 * within this peiod, we consider that the test failed.
5473 * 0 on success and -1 on failure.
5476 static int s2io_bist_test(struct s2io_nic
* sp
, uint64_t * data
)
5479 int cnt
= 0, ret
= -1;
5481 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
5482 bist
|= PCI_BIST_START
;
5483 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
5486 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
5487 if (!(bist
& PCI_BIST_START
)) {
5488 *data
= (bist
& PCI_BIST_CODE_MASK
);
5500 * s2io-link_test - verifies the link state of the nic
5501 * @sp ; private member of the device structure, which is a pointer to the
5502 * s2io_nic structure.
5503 * @data: variable that returns the result of each of the test conducted by
5506 * The function verifies the link state of the NIC and updates the input
5507 * argument 'data' appropriately.
5512 static int s2io_link_test(struct s2io_nic
* sp
, uint64_t * data
)
5514 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5517 val64
= readq(&bar0
->adapter_status
);
5518 if(!(LINK_IS_UP(val64
)))
5527 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5528 * @sp - private member of the device structure, which is a pointer to the
5529 * s2io_nic structure.
5530 * @data - variable that returns the result of each of the test
5531 * conducted by the driver.
5533 * This is one of the offline test that tests the read and write
5534 * access to the RldRam chip on the NIC.
5539 static int s2io_rldram_test(struct s2io_nic
* sp
, uint64_t * data
)
5541 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5543 int cnt
, iteration
= 0, test_fail
= 0;
5545 val64
= readq(&bar0
->adapter_control
);
5546 val64
&= ~ADAPTER_ECC_EN
;
5547 writeq(val64
, &bar0
->adapter_control
);
5549 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5550 val64
|= MC_RLDRAM_TEST_MODE
;
5551 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5553 val64
= readq(&bar0
->mc_rldram_mrs
);
5554 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
5555 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
5557 val64
|= MC_RLDRAM_MRS_ENABLE
;
5558 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
5560 while (iteration
< 2) {
5561 val64
= 0x55555555aaaa0000ULL
;
5562 if (iteration
== 1) {
5563 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5565 writeq(val64
, &bar0
->mc_rldram_test_d0
);
5567 val64
= 0xaaaa5a5555550000ULL
;
5568 if (iteration
== 1) {
5569 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5571 writeq(val64
, &bar0
->mc_rldram_test_d1
);
5573 val64
= 0x55aaaaaaaa5a0000ULL
;
5574 if (iteration
== 1) {
5575 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5577 writeq(val64
, &bar0
->mc_rldram_test_d2
);
5579 val64
= (u64
) (0x0000003ffffe0100ULL
);
5580 writeq(val64
, &bar0
->mc_rldram_test_add
);
5582 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_WRITE
|
5584 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5586 for (cnt
= 0; cnt
< 5; cnt
++) {
5587 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5588 if (val64
& MC_RLDRAM_TEST_DONE
)
5596 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
5597 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5599 for (cnt
= 0; cnt
< 5; cnt
++) {
5600 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5601 if (val64
& MC_RLDRAM_TEST_DONE
)
5609 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5610 if (!(val64
& MC_RLDRAM_TEST_PASS
))
5618 /* Bring the adapter out of test mode */
5619 SPECIAL_REG_WRITE(0, &bar0
->mc_rldram_test_ctrl
, LF
);
5625 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5626 * @sp : private member of the device structure, which is a pointer to the
5627 * s2io_nic structure.
5628 * @ethtest : pointer to a ethtool command specific structure that will be
5629 * returned to the user.
5630 * @data : variable that returns the result of each of the test
5631 * conducted by the driver.
5633 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5634 * the health of the card.
5639 static void s2io_ethtool_test(struct net_device
*dev
,
5640 struct ethtool_test
*ethtest
,
5643 struct s2io_nic
*sp
= dev
->priv
;
5644 int orig_state
= netif_running(sp
->dev
);
5646 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
5647 /* Offline Tests. */
5649 s2io_close(sp
->dev
);
5651 if (s2io_register_test(sp
, &data
[0]))
5652 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5656 if (s2io_rldram_test(sp
, &data
[3]))
5657 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5661 if (s2io_eeprom_test(sp
, &data
[1]))
5662 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5664 if (s2io_bist_test(sp
, &data
[4]))
5665 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5675 "%s: is not up, cannot run test\n",
5684 if (s2io_link_test(sp
, &data
[2]))
5685 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5694 static void s2io_get_ethtool_stats(struct net_device
*dev
,
5695 struct ethtool_stats
*estats
,
5699 struct s2io_nic
*sp
= dev
->priv
;
5700 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
5702 s2io_updt_stats(sp
);
5704 (u64
)le32_to_cpu(stat_info
->tmac_frms_oflow
) << 32 |
5705 le32_to_cpu(stat_info
->tmac_frms
);
5707 (u64
)le32_to_cpu(stat_info
->tmac_data_octets_oflow
) << 32 |
5708 le32_to_cpu(stat_info
->tmac_data_octets
);
5709 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_drop_frms
);
5711 (u64
)le32_to_cpu(stat_info
->tmac_mcst_frms_oflow
) << 32 |
5712 le32_to_cpu(stat_info
->tmac_mcst_frms
);
5714 (u64
)le32_to_cpu(stat_info
->tmac_bcst_frms_oflow
) << 32 |
5715 le32_to_cpu(stat_info
->tmac_bcst_frms
);
5716 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_pause_ctrl_frms
);
5718 (u64
)le32_to_cpu(stat_info
->tmac_ttl_octets_oflow
) << 32 |
5719 le32_to_cpu(stat_info
->tmac_ttl_octets
);
5721 (u64
)le32_to_cpu(stat_info
->tmac_ucst_frms_oflow
) << 32 |
5722 le32_to_cpu(stat_info
->tmac_ucst_frms
);
5724 (u64
)le32_to_cpu(stat_info
->tmac_nucst_frms_oflow
) << 32 |
5725 le32_to_cpu(stat_info
->tmac_nucst_frms
);
5727 (u64
)le32_to_cpu(stat_info
->tmac_any_err_frms_oflow
) << 32 |
5728 le32_to_cpu(stat_info
->tmac_any_err_frms
);
5729 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_ttl_less_fb_octets
);
5730 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_vld_ip_octets
);
5732 (u64
)le32_to_cpu(stat_info
->tmac_vld_ip_oflow
) << 32 |
5733 le32_to_cpu(stat_info
->tmac_vld_ip
);
5735 (u64
)le32_to_cpu(stat_info
->tmac_drop_ip_oflow
) << 32 |
5736 le32_to_cpu(stat_info
->tmac_drop_ip
);
5738 (u64
)le32_to_cpu(stat_info
->tmac_icmp_oflow
) << 32 |
5739 le32_to_cpu(stat_info
->tmac_icmp
);
5741 (u64
)le32_to_cpu(stat_info
->tmac_rst_tcp_oflow
) << 32 |
5742 le32_to_cpu(stat_info
->tmac_rst_tcp
);
5743 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_tcp
);
5744 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->tmac_udp_oflow
) << 32 |
5745 le32_to_cpu(stat_info
->tmac_udp
);
5747 (u64
)le32_to_cpu(stat_info
->rmac_vld_frms_oflow
) << 32 |
5748 le32_to_cpu(stat_info
->rmac_vld_frms
);
5750 (u64
)le32_to_cpu(stat_info
->rmac_data_octets_oflow
) << 32 |
5751 le32_to_cpu(stat_info
->rmac_data_octets
);
5752 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_fcs_err_frms
);
5753 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_drop_frms
);
5755 (u64
)le32_to_cpu(stat_info
->rmac_vld_mcst_frms_oflow
) << 32 |
5756 le32_to_cpu(stat_info
->rmac_vld_mcst_frms
);
5758 (u64
)le32_to_cpu(stat_info
->rmac_vld_bcst_frms_oflow
) << 32 |
5759 le32_to_cpu(stat_info
->rmac_vld_bcst_frms
);
5760 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_in_rng_len_err_frms
);
5761 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_out_rng_len_err_frms
);
5762 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_long_frms
);
5763 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_pause_ctrl_frms
);
5764 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_unsup_ctrl_frms
);
5766 (u64
)le32_to_cpu(stat_info
->rmac_ttl_octets_oflow
) << 32 |
5767 le32_to_cpu(stat_info
->rmac_ttl_octets
);
5769 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ucst_frms_oflow
)
5770 << 32 | le32_to_cpu(stat_info
->rmac_accepted_ucst_frms
);
5772 (u64
)le32_to_cpu(stat_info
->rmac_accepted_nucst_frms_oflow
)
5773 << 32 | le32_to_cpu(stat_info
->rmac_accepted_nucst_frms
);
5775 (u64
)le32_to_cpu(stat_info
->rmac_discarded_frms_oflow
) << 32 |
5776 le32_to_cpu(stat_info
->rmac_discarded_frms
);
5778 (u64
)le32_to_cpu(stat_info
->rmac_drop_events_oflow
)
5779 << 32 | le32_to_cpu(stat_info
->rmac_drop_events
);
5780 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_less_fb_octets
);
5781 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_frms
);
5783 (u64
)le32_to_cpu(stat_info
->rmac_usized_frms_oflow
) << 32 |
5784 le32_to_cpu(stat_info
->rmac_usized_frms
);
5786 (u64
)le32_to_cpu(stat_info
->rmac_osized_frms_oflow
) << 32 |
5787 le32_to_cpu(stat_info
->rmac_osized_frms
);
5789 (u64
)le32_to_cpu(stat_info
->rmac_frag_frms_oflow
) << 32 |
5790 le32_to_cpu(stat_info
->rmac_frag_frms
);
5792 (u64
)le32_to_cpu(stat_info
->rmac_jabber_frms_oflow
) << 32 |
5793 le32_to_cpu(stat_info
->rmac_jabber_frms
);
5794 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_64_frms
);
5795 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_65_127_frms
);
5796 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_128_255_frms
);
5797 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_256_511_frms
);
5798 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_512_1023_frms
);
5799 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_1024_1518_frms
);
5801 (u64
)le32_to_cpu(stat_info
->rmac_ip_oflow
) << 32 |
5802 le32_to_cpu(stat_info
->rmac_ip
);
5803 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ip_octets
);
5804 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_hdr_err_ip
);
5806 (u64
)le32_to_cpu(stat_info
->rmac_drop_ip_oflow
) << 32 |
5807 le32_to_cpu(stat_info
->rmac_drop_ip
);
5809 (u64
)le32_to_cpu(stat_info
->rmac_icmp_oflow
) << 32 |
5810 le32_to_cpu(stat_info
->rmac_icmp
);
5811 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_tcp
);
5813 (u64
)le32_to_cpu(stat_info
->rmac_udp_oflow
) << 32 |
5814 le32_to_cpu(stat_info
->rmac_udp
);
5816 (u64
)le32_to_cpu(stat_info
->rmac_err_drp_udp_oflow
) << 32 |
5817 le32_to_cpu(stat_info
->rmac_err_drp_udp
);
5818 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_err_sym
);
5819 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q0
);
5820 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q1
);
5821 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q2
);
5822 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q3
);
5823 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q4
);
5824 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q5
);
5825 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q6
);
5826 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q7
);
5827 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q0
);
5828 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q1
);
5829 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q2
);
5830 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q3
);
5831 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q4
);
5832 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q5
);
5833 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q6
);
5834 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q7
);
5836 (u64
)le32_to_cpu(stat_info
->rmac_pause_cnt_oflow
) << 32 |
5837 le32_to_cpu(stat_info
->rmac_pause_cnt
);
5838 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_data_err_cnt
);
5839 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_ctrl_err_cnt
);
5841 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ip_oflow
) << 32 |
5842 le32_to_cpu(stat_info
->rmac_accepted_ip
);
5843 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_err_tcp
);
5844 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_req_cnt
);
5845 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_cnt
);
5846 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_rtry_cnt
);
5847 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_cnt
);
5848 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_rd_ack_cnt
);
5849 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_req_cnt
);
5850 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_cnt
);
5851 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_rtry_cnt
);
5852 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_cnt
);
5853 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_disc_cnt
);
5854 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_wr_ack_cnt
);
5855 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txp_wr_cnt
);
5856 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_rd_cnt
);
5857 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_wr_cnt
);
5858 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_rd_cnt
);
5859 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_wr_cnt
);
5860 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txf_rd_cnt
);
5861 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxf_wr_cnt
);
5863 /* Enhanced statistics exist only for Hercules */
5864 if(sp
->device_type
== XFRAME_II_DEVICE
) {
5866 le64_to_cpu(stat_info
->rmac_ttl_1519_4095_frms
);
5868 le64_to_cpu(stat_info
->rmac_ttl_4096_8191_frms
);
5870 le64_to_cpu(stat_info
->rmac_ttl_8192_max_frms
);
5871 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_gt_max_frms
);
5872 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_osized_alt_frms
);
5873 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_jabber_alt_frms
);
5874 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_gt_max_alt_frms
);
5875 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_vlan_frms
);
5876 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_len_discard
);
5877 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_fcs_discard
);
5878 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_pf_discard
);
5879 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_da_discard
);
5880 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_red_discard
);
5881 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_rts_discard
);
5882 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_ingm_full_discard
);
5883 tmp_stats
[i
++] = le32_to_cpu(stat_info
->link_fault_cnt
);
5887 tmp_stats
[i
++] = stat_info
->sw_stat
.single_ecc_errs
;
5888 tmp_stats
[i
++] = stat_info
->sw_stat
.double_ecc_errs
;
5889 tmp_stats
[i
++] = stat_info
->sw_stat
.parity_err_cnt
;
5890 tmp_stats
[i
++] = stat_info
->sw_stat
.serious_err_cnt
;
5891 tmp_stats
[i
++] = stat_info
->sw_stat
.soft_reset_cnt
;
5892 tmp_stats
[i
++] = stat_info
->sw_stat
.fifo_full_cnt
;
5893 tmp_stats
[i
++] = stat_info
->sw_stat
.ring_full_cnt
;
5894 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_high
;
5895 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_low
;
5896 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_high
;
5897 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_low
;
5898 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_high
;
5899 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_low
;
5900 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_high
;
5901 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_low
;
5902 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_high
;
5903 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_low
;
5904 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_high
;
5905 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_low
;
5906 tmp_stats
[i
++] = stat_info
->sw_stat
.clubbed_frms_cnt
;
5907 tmp_stats
[i
++] = stat_info
->sw_stat
.sending_both
;
5908 tmp_stats
[i
++] = stat_info
->sw_stat
.outof_sequence_pkts
;
5909 tmp_stats
[i
++] = stat_info
->sw_stat
.flush_max_pkts
;
5910 if (stat_info
->sw_stat
.num_aggregations
) {
5911 u64 tmp
= stat_info
->sw_stat
.sum_avg_pkts_aggregated
;
5914 * Since 64-bit divide does not work on all platforms,
5915 * do repeated subtraction.
5917 while (tmp
>= stat_info
->sw_stat
.num_aggregations
) {
5918 tmp
-= stat_info
->sw_stat
.num_aggregations
;
5921 tmp_stats
[i
++] = count
;
5925 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_alloc_fail_cnt
;
5926 tmp_stats
[i
++] = stat_info
->sw_stat
.watchdog_timer_cnt
;
5927 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_allocated
;
5928 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_freed
;
5929 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_cnt
;
5930 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_cnt
;
5931 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_time
;
5932 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_time
;
5934 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_buf_abort_cnt
;
5935 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_desc_abort_cnt
;
5936 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_parity_err_cnt
;
5937 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_link_loss_cnt
;
5938 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_list_proc_err_cnt
;
5940 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_err_cnt
;
5941 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_abort_cnt
;
5942 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_abort_cnt
;
5943 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rda_fail_cnt
;
5944 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_prot_cnt
;
5945 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_fcs_err_cnt
;
5946 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_buf_size_err_cnt
;
5947 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rxd_corrupt_cnt
;
5948 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_err_cnt
;
5951 static int s2io_ethtool_get_regs_len(struct net_device
*dev
)
5953 return (XENA_REG_SPACE
);
5957 static u32
s2io_ethtool_get_rx_csum(struct net_device
* dev
)
5959 struct s2io_nic
*sp
= dev
->priv
;
5961 return (sp
->rx_csum
);
5964 static int s2io_ethtool_set_rx_csum(struct net_device
*dev
, u32 data
)
5966 struct s2io_nic
*sp
= dev
->priv
;
5976 static int s2io_get_eeprom_len(struct net_device
*dev
)
5978 return (XENA_EEPROM_SPACE
);
5981 static int s2io_ethtool_self_test_count(struct net_device
*dev
)
5983 return (S2IO_TEST_LEN
);
5986 static void s2io_ethtool_get_strings(struct net_device
*dev
,
5987 u32 stringset
, u8
* data
)
5990 struct s2io_nic
*sp
= dev
->priv
;
5992 switch (stringset
) {
5994 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
5997 stat_size
= sizeof(ethtool_xena_stats_keys
);
5998 memcpy(data
, ðtool_xena_stats_keys
,stat_size
);
5999 if(sp
->device_type
== XFRAME_II_DEVICE
) {
6000 memcpy(data
+ stat_size
,
6001 ðtool_enhanced_stats_keys
,
6002 sizeof(ethtool_enhanced_stats_keys
));
6003 stat_size
+= sizeof(ethtool_enhanced_stats_keys
);
6006 memcpy(data
+ stat_size
, ðtool_driver_stats_keys
,
6007 sizeof(ethtool_driver_stats_keys
));
6010 static int s2io_ethtool_get_stats_count(struct net_device
*dev
)
6012 struct s2io_nic
*sp
= dev
->priv
;
6014 switch(sp
->device_type
) {
6015 case XFRAME_I_DEVICE
:
6016 stat_count
= XFRAME_I_STAT_LEN
;
6019 case XFRAME_II_DEVICE
:
6020 stat_count
= XFRAME_II_STAT_LEN
;
6027 static int s2io_ethtool_op_set_tx_csum(struct net_device
*dev
, u32 data
)
6030 dev
->features
|= NETIF_F_IP_CSUM
;
6032 dev
->features
&= ~NETIF_F_IP_CSUM
;
6037 static u32
s2io_ethtool_op_get_tso(struct net_device
*dev
)
6039 return (dev
->features
& NETIF_F_TSO
) != 0;
6041 static int s2io_ethtool_op_set_tso(struct net_device
*dev
, u32 data
)
6044 dev
->features
|= (NETIF_F_TSO
| NETIF_F_TSO6
);
6046 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
6051 static const struct ethtool_ops netdev_ethtool_ops
= {
6052 .get_settings
= s2io_ethtool_gset
,
6053 .set_settings
= s2io_ethtool_sset
,
6054 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
6055 .get_regs_len
= s2io_ethtool_get_regs_len
,
6056 .get_regs
= s2io_ethtool_gregs
,
6057 .get_link
= ethtool_op_get_link
,
6058 .get_eeprom_len
= s2io_get_eeprom_len
,
6059 .get_eeprom
= s2io_ethtool_geeprom
,
6060 .set_eeprom
= s2io_ethtool_seeprom
,
6061 .get_ringparam
= s2io_ethtool_gringparam
,
6062 .get_pauseparam
= s2io_ethtool_getpause_data
,
6063 .set_pauseparam
= s2io_ethtool_setpause_data
,
6064 .get_rx_csum
= s2io_ethtool_get_rx_csum
,
6065 .set_rx_csum
= s2io_ethtool_set_rx_csum
,
6066 .get_tx_csum
= ethtool_op_get_tx_csum
,
6067 .set_tx_csum
= s2io_ethtool_op_set_tx_csum
,
6068 .get_sg
= ethtool_op_get_sg
,
6069 .set_sg
= ethtool_op_set_sg
,
6070 .get_tso
= s2io_ethtool_op_get_tso
,
6071 .set_tso
= s2io_ethtool_op_set_tso
,
6072 .get_ufo
= ethtool_op_get_ufo
,
6073 .set_ufo
= ethtool_op_set_ufo
,
6074 .self_test_count
= s2io_ethtool_self_test_count
,
6075 .self_test
= s2io_ethtool_test
,
6076 .get_strings
= s2io_ethtool_get_strings
,
6077 .phys_id
= s2io_ethtool_idnic
,
6078 .get_stats_count
= s2io_ethtool_get_stats_count
,
6079 .get_ethtool_stats
= s2io_get_ethtool_stats
6083 * s2io_ioctl - Entry point for the Ioctl
6084 * @dev : Device pointer.
6085 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6086 * a proprietary structure used to pass information to the driver.
6087 * @cmd : This is used to distinguish between the different commands that
6088 * can be passed to the IOCTL functions.
6090 * Currently there are no special functionality supported in IOCTL, hence
6091 * function always return EOPNOTSUPPORTED
6094 static int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
6100 * s2io_change_mtu - entry point to change MTU size for the device.
6101 * @dev : device pointer.
6102 * @new_mtu : the new MTU size for the device.
6103 * Description: A driver entry point to change MTU size for the device.
6104 * Before changing the MTU the device must be stopped.
6106 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6110 static int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
6112 struct s2io_nic
*sp
= dev
->priv
;
6114 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
6115 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n",
6121 if (netif_running(dev
)) {
6123 netif_stop_queue(dev
);
6124 if (s2io_card_up(sp
)) {
6125 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6128 if (netif_queue_stopped(dev
))
6129 netif_wake_queue(dev
);
6130 } else { /* Device is down */
6131 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6132 u64 val64
= new_mtu
;
6134 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
6141 * s2io_tasklet - Bottom half of the ISR.
6142 * @dev_adr : address of the device structure in dma_addr_t format.
6144 * This is the tasklet or the bottom half of the ISR. This is
6145 * an extension of the ISR which is scheduled by the scheduler to be run
6146 * when the load on the CPU is low. All low priority tasks of the ISR can
6147 * be pushed into the tasklet. For now the tasklet is used only to
6148 * replenish the Rx buffers in the Rx buffer descriptors.
6153 static void s2io_tasklet(unsigned long dev_addr
)
6155 struct net_device
*dev
= (struct net_device
*) dev_addr
;
6156 struct s2io_nic
*sp
= dev
->priv
;
6158 struct mac_info
*mac_control
;
6159 struct config_param
*config
;
6161 mac_control
= &sp
->mac_control
;
6162 config
= &sp
->config
;
6164 if (!TASKLET_IN_USE
) {
6165 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6166 ret
= fill_rx_buffers(sp
, i
);
6167 if (ret
== -ENOMEM
) {
6168 DBG_PRINT(INFO_DBG
, "%s: Out of ",
6170 DBG_PRINT(INFO_DBG
, "memory in tasklet\n");
6172 } else if (ret
== -EFILL
) {
6174 "%s: Rx Ring %d is full\n",
6179 clear_bit(0, (&sp
->tasklet_status
));
6184 * s2io_set_link - Set the LInk status
6185 * @data: long pointer to device private structue
6186 * Description: Sets the link status for the adapter
6189 static void s2io_set_link(struct work_struct
*work
)
6191 struct s2io_nic
*nic
= container_of(work
, struct s2io_nic
, set_link_task
);
6192 struct net_device
*dev
= nic
->dev
;
6193 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
6199 if (!netif_running(dev
))
6202 if (test_and_set_bit(0, &(nic
->link_state
))) {
6203 /* The card is being reset, no point doing anything */
6207 subid
= nic
->pdev
->subsystem_device
;
6208 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
6210 * Allow a small delay for the NICs self initiated
6211 * cleanup to complete.
6216 val64
= readq(&bar0
->adapter_status
);
6217 if (LINK_IS_UP(val64
)) {
6218 if (!(readq(&bar0
->adapter_control
) & ADAPTER_CNTL_EN
)) {
6219 if (verify_xena_quiescence(nic
)) {
6220 val64
= readq(&bar0
->adapter_control
);
6221 val64
|= ADAPTER_CNTL_EN
;
6222 writeq(val64
, &bar0
->adapter_control
);
6223 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6224 nic
->device_type
, subid
)) {
6225 val64
= readq(&bar0
->gpio_control
);
6226 val64
|= GPIO_CTRL_GPIO_0
;
6227 writeq(val64
, &bar0
->gpio_control
);
6228 val64
= readq(&bar0
->gpio_control
);
6230 val64
|= ADAPTER_LED_ON
;
6231 writeq(val64
, &bar0
->adapter_control
);
6233 nic
->device_enabled_once
= TRUE
;
6235 DBG_PRINT(ERR_DBG
, "%s: Error: ", dev
->name
);
6236 DBG_PRINT(ERR_DBG
, "device is not Quiescent\n");
6237 netif_stop_queue(dev
);
6240 val64
= readq(&bar0
->adapter_status
);
6241 if (!LINK_IS_UP(val64
)) {
6242 DBG_PRINT(ERR_DBG
, "%s:", dev
->name
);
6243 DBG_PRINT(ERR_DBG
, " Link down after enabling ");
6244 DBG_PRINT(ERR_DBG
, "device \n");
6246 s2io_link(nic
, LINK_UP
);
6248 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
6250 val64
= readq(&bar0
->gpio_control
);
6251 val64
&= ~GPIO_CTRL_GPIO_0
;
6252 writeq(val64
, &bar0
->gpio_control
);
6253 val64
= readq(&bar0
->gpio_control
);
6255 s2io_link(nic
, LINK_DOWN
);
6257 clear_bit(0, &(nic
->link_state
));
6263 static int set_rxd_buffer_pointer(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6265 struct sk_buff
**skb
, u64
*temp0
, u64
*temp1
,
6266 u64
*temp2
, int size
)
6268 struct net_device
*dev
= sp
->dev
;
6269 struct sk_buff
*frag_list
;
6271 if ((sp
->rxd_mode
== RXD_MODE_1
) && (rxdp
->Host_Control
== 0)) {
6274 DBG_PRINT(INFO_DBG
, "SKB is not NULL\n");
6276 * As Rx frame are not going to be processed,
6277 * using same mapped address for the Rxd
6280 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= *temp0
;
6282 *skb
= dev_alloc_skb(size
);
6284 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6285 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6286 DBG_PRINT(INFO_DBG
, "1 buf mode SKBs\n");
6287 sp
->mac_control
.stats_info
->sw_stat
. \
6288 mem_alloc_fail_cnt
++;
6291 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6292 += (*skb
)->truesize
;
6293 /* storing the mapped addr in a temp variable
6294 * such it will be used for next rxd whose
6295 * Host Control is NULL
6297 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= *temp0
=
6298 pci_map_single( sp
->pdev
, (*skb
)->data
,
6299 size
- NET_IP_ALIGN
,
6300 PCI_DMA_FROMDEVICE
);
6301 rxdp
->Host_Control
= (unsigned long) (*skb
);
6303 } else if ((sp
->rxd_mode
== RXD_MODE_3B
) && (rxdp
->Host_Control
== 0)) {
6304 /* Two buffer Mode */
6306 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
;
6307 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
;
6308 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
;
6310 *skb
= dev_alloc_skb(size
);
6312 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6313 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6314 DBG_PRINT(INFO_DBG
, "2 buf mode SKBs\n");
6315 sp
->mac_control
.stats_info
->sw_stat
. \
6316 mem_alloc_fail_cnt
++;
6319 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6320 += (*skb
)->truesize
;
6321 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
=
6322 pci_map_single(sp
->pdev
, (*skb
)->data
,
6324 PCI_DMA_FROMDEVICE
);
6325 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
=
6326 pci_map_single( sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
6327 PCI_DMA_FROMDEVICE
);
6328 rxdp
->Host_Control
= (unsigned long) (*skb
);
6330 /* Buffer-1 will be dummy buffer not used */
6331 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
=
6332 pci_map_single(sp
->pdev
, ba
->ba_1
, BUF1_LEN
,
6333 PCI_DMA_FROMDEVICE
);
6335 } else if ((rxdp
->Host_Control
== 0)) {
6336 /* Three buffer mode */
6338 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
;
6339 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
;
6340 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
;
6342 *skb
= dev_alloc_skb(size
);
6344 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6345 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6346 DBG_PRINT(INFO_DBG
, "3 buf mode SKBs\n");
6347 sp
->mac_control
.stats_info
->sw_stat
. \
6348 mem_alloc_fail_cnt
++;
6351 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6352 += (*skb
)->truesize
;
6353 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
=
6354 pci_map_single(sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
6355 PCI_DMA_FROMDEVICE
);
6356 /* Buffer-1 receives L3/L4 headers */
6357 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
=
6358 pci_map_single( sp
->pdev
, (*skb
)->data
,
6360 PCI_DMA_FROMDEVICE
);
6362 * skb_shinfo(skb)->frag_list will have L4
6365 skb_shinfo(*skb
)->frag_list
= dev_alloc_skb(dev
->mtu
+
6367 if (skb_shinfo(*skb
)->frag_list
== NULL
) {
6368 DBG_PRINT(ERR_DBG
, "%s: dev_alloc_skb \
6369 failed\n ", dev
->name
);
6370 sp
->mac_control
.stats_info
->sw_stat
. \
6371 mem_alloc_fail_cnt
++;
6374 frag_list
= skb_shinfo(*skb
)->frag_list
;
6375 frag_list
->next
= NULL
;
6376 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6377 += frag_list
->truesize
;
6379 * Buffer-2 receives L4 data payload
6381 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
=
6382 pci_map_single( sp
->pdev
, frag_list
->data
,
6383 dev
->mtu
, PCI_DMA_FROMDEVICE
);
6388 static void set_rxd_buffer_size(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6391 struct net_device
*dev
= sp
->dev
;
6392 if (sp
->rxd_mode
== RXD_MODE_1
) {
6393 rxdp
->Control_2
= SET_BUFFER0_SIZE_1( size
- NET_IP_ALIGN
);
6394 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
6395 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6396 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
6397 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3( dev
->mtu
+ 4);
6399 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6400 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(l3l4hdr_size
+ 4);
6401 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3(dev
->mtu
);
6405 static int rxd_owner_bit_reset(struct s2io_nic
*sp
)
6407 int i
, j
, k
, blk_cnt
= 0, size
;
6408 struct mac_info
* mac_control
= &sp
->mac_control
;
6409 struct config_param
*config
= &sp
->config
;
6410 struct net_device
*dev
= sp
->dev
;
6411 struct RxD_t
*rxdp
= NULL
;
6412 struct sk_buff
*skb
= NULL
;
6413 struct buffAdd
*ba
= NULL
;
6414 u64 temp0_64
= 0, temp1_64
= 0, temp2_64
= 0;
6416 /* Calculate the size based on ring mode */
6417 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
6418 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
6419 if (sp
->rxd_mode
== RXD_MODE_1
)
6420 size
+= NET_IP_ALIGN
;
6421 else if (sp
->rxd_mode
== RXD_MODE_3B
)
6422 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6424 size
= l3l4hdr_size
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6426 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6427 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
6428 (rxd_count
[sp
->rxd_mode
] +1);
6430 for (j
= 0; j
< blk_cnt
; j
++) {
6431 for (k
= 0; k
< rxd_count
[sp
->rxd_mode
]; k
++) {
6432 rxdp
= mac_control
->rings
[i
].
6433 rx_blocks
[j
].rxds
[k
].virt_addr
;
6434 if(sp
->rxd_mode
>= RXD_MODE_3A
)
6435 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
6436 if (set_rxd_buffer_pointer(sp
, rxdp
, ba
,
6437 &skb
,(u64
*)&temp0_64
,
6444 set_rxd_buffer_size(sp
, rxdp
, size
);
6446 /* flip the Ownership bit to Hardware */
6447 rxdp
->Control_1
|= RXD_OWN_XENA
;
6455 static int s2io_add_isr(struct s2io_nic
* sp
)
6458 struct net_device
*dev
= sp
->dev
;
6461 if (sp
->intr_type
== MSI
)
6462 ret
= s2io_enable_msi(sp
);
6463 else if (sp
->intr_type
== MSI_X
)
6464 ret
= s2io_enable_msi_x(sp
);
6466 DBG_PRINT(ERR_DBG
, "%s: Defaulting to INTA\n", dev
->name
);
6467 sp
->intr_type
= INTA
;
6470 /* Store the values of the MSIX table in the struct s2io_nic structure */
6471 store_xmsi_data(sp
);
6473 /* After proper initialization of H/W, register ISR */
6474 if (sp
->intr_type
== MSI
) {
6475 err
= request_irq((int) sp
->pdev
->irq
, s2io_msi_handle
,
6476 IRQF_SHARED
, sp
->name
, dev
);
6478 pci_disable_msi(sp
->pdev
);
6479 DBG_PRINT(ERR_DBG
, "%s: MSI registration failed\n",
6484 if (sp
->intr_type
== MSI_X
) {
6485 int i
, msix_tx_cnt
=0,msix_rx_cnt
=0;
6487 for (i
=1; (sp
->s2io_entries
[i
].in_use
== MSIX_FLG
); i
++) {
6488 if (sp
->s2io_entries
[i
].type
== MSIX_FIFO_TYPE
) {
6489 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-TX",
6491 err
= request_irq(sp
->entries
[i
].vector
,
6492 s2io_msix_fifo_handle
, 0, sp
->desc
[i
],
6493 sp
->s2io_entries
[i
].arg
);
6494 /* If either data or addr is zero print it */
6495 if(!(sp
->msix_info
[i
].addr
&&
6496 sp
->msix_info
[i
].data
)) {
6497 DBG_PRINT(ERR_DBG
, "%s @ Addr:0x%llx"
6498 "Data:0x%lx\n",sp
->desc
[i
],
6499 (unsigned long long)
6500 sp
->msix_info
[i
].addr
,
6502 ntohl(sp
->msix_info
[i
].data
));
6507 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-RX",
6509 err
= request_irq(sp
->entries
[i
].vector
,
6510 s2io_msix_ring_handle
, 0, sp
->desc
[i
],
6511 sp
->s2io_entries
[i
].arg
);
6512 /* If either data or addr is zero print it */
6513 if(!(sp
->msix_info
[i
].addr
&&
6514 sp
->msix_info
[i
].data
)) {
6515 DBG_PRINT(ERR_DBG
, "%s @ Addr:0x%llx"
6516 "Data:0x%lx\n",sp
->desc
[i
],
6517 (unsigned long long)
6518 sp
->msix_info
[i
].addr
,
6520 ntohl(sp
->msix_info
[i
].data
));
6526 DBG_PRINT(ERR_DBG
,"%s:MSI-X-%d registration "
6527 "failed\n", dev
->name
, i
);
6528 DBG_PRINT(ERR_DBG
, "Returned: %d\n", err
);
6531 sp
->s2io_entries
[i
].in_use
= MSIX_REGISTERED_SUCCESS
;
6533 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt
);
6534 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt
);
6536 if (sp
->intr_type
== INTA
) {
6537 err
= request_irq((int) sp
->pdev
->irq
, s2io_isr
, IRQF_SHARED
,
6540 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
6547 static void s2io_rem_isr(struct s2io_nic
* sp
)
6550 struct net_device
*dev
= sp
->dev
;
6552 if (sp
->intr_type
== MSI_X
) {
6556 for (i
=1; (sp
->s2io_entries
[i
].in_use
==
6557 MSIX_REGISTERED_SUCCESS
); i
++) {
6558 int vector
= sp
->entries
[i
].vector
;
6559 void *arg
= sp
->s2io_entries
[i
].arg
;
6561 free_irq(vector
, arg
);
6563 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
6564 msi_control
&= 0xFFFE; /* Disable MSI */
6565 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
6567 pci_disable_msix(sp
->pdev
);
6569 free_irq(sp
->pdev
->irq
, dev
);
6570 if (sp
->intr_type
== MSI
) {
6573 pci_disable_msi(sp
->pdev
);
6574 pci_read_config_word(sp
->pdev
, 0x4c, &val
);
6576 pci_write_config_word(sp
->pdev
, 0x4c, val
);
6579 /* Waiting till all Interrupt handlers are complete */
6583 if (!atomic_read(&sp
->isr_cnt
))
6589 static void do_s2io_card_down(struct s2io_nic
* sp
, int do_io
)
6592 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6593 unsigned long flags
;
6594 register u64 val64
= 0;
6596 del_timer_sync(&sp
->alarm_timer
);
6597 /* If s2io_set_link task is executing, wait till it completes. */
6598 while (test_and_set_bit(0, &(sp
->link_state
))) {
6601 atomic_set(&sp
->card_state
, CARD_DOWN
);
6603 /* disable Tx and Rx traffic on the NIC */
6610 tasklet_kill(&sp
->task
);
6612 /* Check if the device is Quiescent and then Reset the NIC */
6614 /* As per the HW requirement we need to replenish the
6615 * receive buffer to avoid the ring bump. Since there is
6616 * no intention of processing the Rx frame at this pointwe are
6617 * just settting the ownership bit of rxd in Each Rx
6618 * ring to HW and set the appropriate buffer size
6619 * based on the ring mode
6621 rxd_owner_bit_reset(sp
);
6623 val64
= readq(&bar0
->adapter_status
);
6624 if (verify_xena_quiescence(sp
)) {
6625 if(verify_pcc_quiescent(sp
, sp
->device_enabled_once
))
6633 "s2io_close:Device not Quiescent ");
6634 DBG_PRINT(ERR_DBG
, "adaper status reads 0x%llx\n",
6635 (unsigned long long) val64
);
6642 spin_lock_irqsave(&sp
->tx_lock
, flags
);
6643 /* Free all Tx buffers */
6644 free_tx_buffers(sp
);
6645 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
6647 /* Free all Rx buffers */
6648 spin_lock_irqsave(&sp
->rx_lock
, flags
);
6649 free_rx_buffers(sp
);
6650 spin_unlock_irqrestore(&sp
->rx_lock
, flags
);
6652 clear_bit(0, &(sp
->link_state
));
6655 static void s2io_card_down(struct s2io_nic
* sp
)
6657 do_s2io_card_down(sp
, 1);
6660 static int s2io_card_up(struct s2io_nic
* sp
)
6663 struct mac_info
*mac_control
;
6664 struct config_param
*config
;
6665 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
6668 /* Initialize the H/W I/O registers */
6669 if (init_nic(sp
) != 0) {
6670 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
6677 * Initializing the Rx buffers. For now we are considering only 1
6678 * Rx ring and initializing buffers into 30 Rx blocks
6680 mac_control
= &sp
->mac_control
;
6681 config
= &sp
->config
;
6683 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6684 if ((ret
= fill_rx_buffers(sp
, i
))) {
6685 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
6688 free_rx_buffers(sp
);
6691 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
6692 atomic_read(&sp
->rx_bufs_left
[i
]));
6694 /* Maintain the state prior to the open */
6695 if (sp
->promisc_flg
)
6696 sp
->promisc_flg
= 0;
6697 if (sp
->m_cast_flg
) {
6699 sp
->all_multi_pos
= 0;
6702 /* Setting its receive mode */
6703 s2io_set_multicast(dev
);
6706 /* Initialize max aggregatable pkts per session based on MTU */
6707 sp
->lro_max_aggr_per_sess
= ((1<<16) - 1) / dev
->mtu
;
6708 /* Check if we can use(if specified) user provided value */
6709 if (lro_max_pkts
< sp
->lro_max_aggr_per_sess
)
6710 sp
->lro_max_aggr_per_sess
= lro_max_pkts
;
6713 /* Enable Rx Traffic and interrupts on the NIC */
6714 if (start_nic(sp
)) {
6715 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
6717 free_rx_buffers(sp
);
6721 /* Add interrupt service routine */
6722 if (s2io_add_isr(sp
) != 0) {
6723 if (sp
->intr_type
== MSI_X
)
6726 free_rx_buffers(sp
);
6730 S2IO_TIMER_CONF(sp
->alarm_timer
, s2io_alarm_handle
, sp
, (HZ
/2));
6732 /* Enable tasklet for the device */
6733 tasklet_init(&sp
->task
, s2io_tasklet
, (unsigned long) dev
);
6735 /* Enable select interrupts */
6736 if (sp
->intr_type
!= INTA
)
6737 en_dis_able_nic_intrs(sp
, ENA_ALL_INTRS
, DISABLE_INTRS
);
6739 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
6740 interruptible
|= TX_PIC_INTR
| RX_PIC_INTR
;
6741 interruptible
|= TX_MAC_INTR
| RX_MAC_INTR
;
6742 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
6746 atomic_set(&sp
->card_state
, CARD_UP
);
6751 * s2io_restart_nic - Resets the NIC.
6752 * @data : long pointer to the device private structure
6754 * This function is scheduled to be run by the s2io_tx_watchdog
6755 * function after 0.5 secs to reset the NIC. The idea is to reduce
6756 * the run time of the watch dog routine which is run holding a
6760 static void s2io_restart_nic(struct work_struct
*work
)
6762 struct s2io_nic
*sp
= container_of(work
, struct s2io_nic
, rst_timer_task
);
6763 struct net_device
*dev
= sp
->dev
;
6767 if (!netif_running(dev
))
6771 if (s2io_card_up(sp
)) {
6772 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6775 netif_wake_queue(dev
);
6776 DBG_PRINT(ERR_DBG
, "%s: was reset by Tx watchdog timer\n",
6783 * s2io_tx_watchdog - Watchdog for transmit side.
6784 * @dev : Pointer to net device structure
6786 * This function is triggered if the Tx Queue is stopped
6787 * for a pre-defined amount of time when the Interface is still up.
6788 * If the Interface is jammed in such a situation, the hardware is
6789 * reset (by s2io_close) and restarted again (by s2io_open) to
6790 * overcome any problem that might have been caused in the hardware.
6795 static void s2io_tx_watchdog(struct net_device
*dev
)
6797 struct s2io_nic
*sp
= dev
->priv
;
6799 if (netif_carrier_ok(dev
)) {
6800 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
++;
6801 schedule_work(&sp
->rst_timer_task
);
6802 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
6807 * rx_osm_handler - To perform some OS related operations on SKB.
6808 * @sp: private member of the device structure,pointer to s2io_nic structure.
6809 * @skb : the socket buffer pointer.
6810 * @len : length of the packet
6811 * @cksum : FCS checksum of the frame.
6812 * @ring_no : the ring from which this RxD was extracted.
6814 * This function is called by the Rx interrupt serivce routine to perform
6815 * some OS related operations on the SKB before passing it to the upper
6816 * layers. It mainly checks if the checksum is OK, if so adds it to the
6817 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6818 * to the upper layer. If the checksum is wrong, it increments the Rx
6819 * packet error count, frees the SKB and returns error.
6821 * SUCCESS on success and -1 on failure.
6823 static int rx_osm_handler(struct ring_info
*ring_data
, struct RxD_t
* rxdp
)
6825 struct s2io_nic
*sp
= ring_data
->nic
;
6826 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
6827 struct sk_buff
*skb
= (struct sk_buff
*)
6828 ((unsigned long) rxdp
->Host_Control
);
6829 int ring_no
= ring_data
->ring_no
;
6830 u16 l3_csum
, l4_csum
;
6831 unsigned long long err
= rxdp
->Control_1
& RXD_T_CODE
;
6838 /* Check for parity error */
6840 sp
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
6842 err_mask
= err
>> 48;
6845 sp
->mac_control
.stats_info
->sw_stat
.
6846 rx_parity_err_cnt
++;
6850 sp
->mac_control
.stats_info
->sw_stat
.
6855 sp
->mac_control
.stats_info
->sw_stat
.
6856 rx_parity_abort_cnt
++;
6860 sp
->mac_control
.stats_info
->sw_stat
.
6865 sp
->mac_control
.stats_info
->sw_stat
.
6870 sp
->mac_control
.stats_info
->sw_stat
.
6875 sp
->mac_control
.stats_info
->sw_stat
.
6876 rx_buf_size_err_cnt
++;
6880 sp
->mac_control
.stats_info
->sw_stat
.
6881 rx_rxd_corrupt_cnt
++;
6885 sp
->mac_control
.stats_info
->sw_stat
.
6890 * Drop the packet if bad transfer code. Exception being
6891 * 0x5, which could be due to unsupported IPv6 extension header.
6892 * In this case, we let stack handle the packet.
6893 * Note that in this case, since checksum will be incorrect,
6894 * stack will validate the same.
6896 if (err_mask
!= 0x5) {
6897 DBG_PRINT(ERR_DBG
, "%s: Rx error Value: 0x%x\n",
6898 dev
->name
, err_mask
);
6899 sp
->stats
.rx_crc_errors
++;
6900 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
6903 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
6904 rxdp
->Host_Control
= 0;
6909 /* Updating statistics */
6910 rxdp
->Host_Control
= 0;
6911 if (sp
->rxd_mode
== RXD_MODE_1
) {
6912 int len
= RXD_GET_BUFFER0_SIZE_1(rxdp
->Control_2
);
6914 sp
->stats
.rx_bytes
+= len
;
6917 } else if (sp
->rxd_mode
>= RXD_MODE_3A
) {
6918 int get_block
= ring_data
->rx_curr_get_info
.block_index
;
6919 int get_off
= ring_data
->rx_curr_get_info
.offset
;
6920 int buf0_len
= RXD_GET_BUFFER0_SIZE_3(rxdp
->Control_2
);
6921 int buf2_len
= RXD_GET_BUFFER2_SIZE_3(rxdp
->Control_2
);
6922 unsigned char *buff
= skb_push(skb
, buf0_len
);
6924 struct buffAdd
*ba
= &ring_data
->ba
[get_block
][get_off
];
6925 sp
->stats
.rx_bytes
+= buf0_len
+ buf2_len
;
6926 memcpy(buff
, ba
->ba_0
, buf0_len
);
6928 if (sp
->rxd_mode
== RXD_MODE_3A
) {
6929 int buf1_len
= RXD_GET_BUFFER1_SIZE_3(rxdp
->Control_2
);
6931 skb_put(skb
, buf1_len
);
6932 skb
->len
+= buf2_len
;
6933 skb
->data_len
+= buf2_len
;
6934 skb_put(skb_shinfo(skb
)->frag_list
, buf2_len
);
6935 sp
->stats
.rx_bytes
+= buf1_len
;
6938 skb_put(skb
, buf2_len
);
6941 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) && ((!sp
->lro
) ||
6942 (sp
->lro
&& (!(rxdp
->Control_1
& RXD_FRAME_IP_FRAG
)))) &&
6944 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
6945 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
6946 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
6948 * NIC verifies if the Checksum of the received
6949 * frame is Ok or not and accordingly returns
6950 * a flag in the RxD.
6952 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6958 ret
= s2io_club_tcp_session(skb
->data
, &tcp
,
6959 &tcp_len
, &lro
, rxdp
, sp
);
6961 case 3: /* Begin anew */
6964 case 1: /* Aggregate */
6966 lro_append_pkt(sp
, lro
,
6970 case 4: /* Flush session */
6972 lro_append_pkt(sp
, lro
,
6974 queue_rx_frame(lro
->parent
);
6975 clear_lro_session(lro
);
6976 sp
->mac_control
.stats_info
->
6977 sw_stat
.flush_max_pkts
++;
6980 case 2: /* Flush both */
6981 lro
->parent
->data_len
=
6983 sp
->mac_control
.stats_info
->
6984 sw_stat
.sending_both
++;
6985 queue_rx_frame(lro
->parent
);
6986 clear_lro_session(lro
);
6988 case 0: /* sessions exceeded */
6989 case -1: /* non-TCP or not
6993 * First pkt in session not
6994 * L3/L4 aggregatable
6999 "%s: Samadhana!!\n",
7006 * Packet with erroneous checksum, let the
7007 * upper layers deal with it.
7009 skb
->ip_summed
= CHECKSUM_NONE
;
7012 skb
->ip_summed
= CHECKSUM_NONE
;
7014 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
7016 skb
->protocol
= eth_type_trans(skb
, dev
);
7017 if ((sp
->vlgrp
&& RXD_GET_VLAN_TAG(rxdp
->Control_2
) &&
7019 /* Queueing the vlan frame to the upper layer */
7021 vlan_hwaccel_receive_skb(skb
, sp
->vlgrp
,
7022 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7024 vlan_hwaccel_rx(skb
, sp
->vlgrp
,
7025 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7028 netif_receive_skb(skb
);
7034 queue_rx_frame(skb
);
7036 dev
->last_rx
= jiffies
;
7038 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
7043 * s2io_link - stops/starts the Tx queue.
7044 * @sp : private member of the device structure, which is a pointer to the
7045 * s2io_nic structure.
7046 * @link : inidicates whether link is UP/DOWN.
7048 * This function stops/starts the Tx queue depending on whether the link
7049 * status of the NIC is is down or up. This is called by the Alarm
7050 * interrupt handler whenever a link change interrupt comes up.
7055 static void s2io_link(struct s2io_nic
* sp
, int link
)
7057 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
7059 if (link
!= sp
->last_link_state
) {
7060 if (link
== LINK_DOWN
) {
7061 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
7062 netif_carrier_off(dev
);
7063 if(sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
)
7064 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
=
7065 jiffies
- sp
->start_time
;
7066 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
++;
7068 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
7069 if (sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
)
7070 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
=
7071 jiffies
- sp
->start_time
;
7072 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
++;
7073 netif_carrier_on(dev
);
7076 sp
->last_link_state
= link
;
7077 sp
->start_time
= jiffies
;
7081 * get_xena_rev_id - to identify revision ID of xena.
7082 * @pdev : PCI Dev structure
7084 * Function to identify the Revision ID of xena.
7086 * returns the revision ID of the device.
7089 static int get_xena_rev_id(struct pci_dev
*pdev
)
7093 ret
= pci_read_config_byte(pdev
, PCI_REVISION_ID
, (u8
*) & id
);
7098 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7099 * @sp : private member of the device structure, which is a pointer to the
7100 * s2io_nic structure.
7102 * This function initializes a few of the PCI and PCI-X configuration registers
7103 * with recommended values.
7108 static void s2io_init_pci(struct s2io_nic
* sp
)
7110 u16 pci_cmd
= 0, pcix_cmd
= 0;
7112 /* Enable Data Parity Error Recovery in PCI-X command register. */
7113 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7115 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7117 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7120 /* Set the PErr Response bit in PCI command register. */
7121 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7122 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
7123 (pci_cmd
| PCI_COMMAND_PARITY
));
7124 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7127 static int s2io_verify_parm(struct pci_dev
*pdev
, u8
*dev_intr_type
)
7129 if ( tx_fifo_num
> 8) {
7130 DBG_PRINT(ERR_DBG
, "s2io: Requested number of Tx fifos not "
7132 DBG_PRINT(ERR_DBG
, "s2io: Default to 8 Tx fifos\n");
7135 if ( rx_ring_num
> 8) {
7136 DBG_PRINT(ERR_DBG
, "s2io: Requested number of Rx rings not "
7138 DBG_PRINT(ERR_DBG
, "s2io: Default to 8 Rx rings\n");
7141 if (*dev_intr_type
!= INTA
)
7144 #ifndef CONFIG_PCI_MSI
7145 if (*dev_intr_type
!= INTA
) {
7146 DBG_PRINT(ERR_DBG
, "s2io: This kernel does not support"
7147 "MSI/MSI-X. Defaulting to INTA\n");
7148 *dev_intr_type
= INTA
;
7151 if (*dev_intr_type
> MSI_X
) {
7152 DBG_PRINT(ERR_DBG
, "s2io: Wrong intr_type requested. "
7153 "Defaulting to INTA\n");
7154 *dev_intr_type
= INTA
;
7157 if ((*dev_intr_type
== MSI_X
) &&
7158 ((pdev
->device
!= PCI_DEVICE_ID_HERC_WIN
) &&
7159 (pdev
->device
!= PCI_DEVICE_ID_HERC_UNI
))) {
7160 DBG_PRINT(ERR_DBG
, "s2io: Xframe I does not support MSI_X. "
7161 "Defaulting to INTA\n");
7162 *dev_intr_type
= INTA
;
7165 if (rx_ring_mode
> 3) {
7166 DBG_PRINT(ERR_DBG
, "s2io: Requested ring mode not supported\n");
7167 DBG_PRINT(ERR_DBG
, "s2io: Defaulting to 3-buffer mode\n");
7174 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7175 * or Traffic class respectively.
7176 * @nic: device peivate variable
7177 * Description: The function configures the receive steering to
7178 * desired receive ring.
7179 * Return Value: SUCCESS on success and
7180 * '-1' on failure (endian settings incorrect).
7182 static int rts_ds_steer(struct s2io_nic
*nic
, u8 ds_codepoint
, u8 ring
)
7184 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
7185 register u64 val64
= 0;
7187 if (ds_codepoint
> 63)
7190 val64
= RTS_DS_MEM_DATA(ring
);
7191 writeq(val64
, &bar0
->rts_ds_mem_data
);
7193 val64
= RTS_DS_MEM_CTRL_WE
|
7194 RTS_DS_MEM_CTRL_STROBE_NEW_CMD
|
7195 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint
);
7197 writeq(val64
, &bar0
->rts_ds_mem_ctrl
);
7199 return wait_for_cmd_complete(&bar0
->rts_ds_mem_ctrl
,
7200 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED
,
7205 * s2io_init_nic - Initialization of the adapter .
7206 * @pdev : structure containing the PCI related information of the device.
7207 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7209 * The function initializes an adapter identified by the pci_dec structure.
7210 * All OS related initialization including memory and device structure and
7211 * initlaization of the device private variable is done. Also the swapper
7212 * control register is initialized to enable read and write into the I/O
7213 * registers of the device.
7215 * returns 0 on success and negative on failure.
7218 static int __devinit
7219 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
7221 struct s2io_nic
*sp
;
7222 struct net_device
*dev
;
7224 int dma_flag
= FALSE
;
7225 u32 mac_up
, mac_down
;
7226 u64 val64
= 0, tmp64
= 0;
7227 struct XENA_dev_config __iomem
*bar0
= NULL
;
7229 struct mac_info
*mac_control
;
7230 struct config_param
*config
;
7232 u8 dev_intr_type
= intr_type
;
7234 if ((ret
= s2io_verify_parm(pdev
, &dev_intr_type
)))
7237 if ((ret
= pci_enable_device(pdev
))) {
7239 "s2io_init_nic: pci_enable_device failed\n");
7243 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
7244 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 64bit DMA\n");
7246 if (pci_set_consistent_dma_mask
7247 (pdev
, DMA_64BIT_MASK
)) {
7249 "Unable to obtain 64bit DMA for \
7250 consistent allocations\n");
7251 pci_disable_device(pdev
);
7254 } else if (!pci_set_dma_mask(pdev
, DMA_32BIT_MASK
)) {
7255 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 32bit DMA\n");
7257 pci_disable_device(pdev
);
7260 if (dev_intr_type
!= MSI_X
) {
7261 if (pci_request_regions(pdev
, s2io_driver_name
)) {
7262 DBG_PRINT(ERR_DBG
, "Request Regions failed\n");
7263 pci_disable_device(pdev
);
7268 if (!(request_mem_region(pci_resource_start(pdev
, 0),
7269 pci_resource_len(pdev
, 0), s2io_driver_name
))) {
7270 DBG_PRINT(ERR_DBG
, "bar0 Request Regions failed\n");
7271 pci_disable_device(pdev
);
7274 if (!(request_mem_region(pci_resource_start(pdev
, 2),
7275 pci_resource_len(pdev
, 2), s2io_driver_name
))) {
7276 DBG_PRINT(ERR_DBG
, "bar1 Request Regions failed\n");
7277 release_mem_region(pci_resource_start(pdev
, 0),
7278 pci_resource_len(pdev
, 0));
7279 pci_disable_device(pdev
);
7284 dev
= alloc_etherdev(sizeof(struct s2io_nic
));
7286 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
7287 pci_disable_device(pdev
);
7288 pci_release_regions(pdev
);
7292 pci_set_master(pdev
);
7293 pci_set_drvdata(pdev
, dev
);
7294 SET_MODULE_OWNER(dev
);
7295 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7297 /* Private member variable initialized to s2io NIC structure */
7299 memset(sp
, 0, sizeof(struct s2io_nic
));
7302 sp
->high_dma_flag
= dma_flag
;
7303 sp
->device_enabled_once
= FALSE
;
7304 if (rx_ring_mode
== 1)
7305 sp
->rxd_mode
= RXD_MODE_1
;
7306 if (rx_ring_mode
== 2)
7307 sp
->rxd_mode
= RXD_MODE_3B
;
7308 if (rx_ring_mode
== 3)
7309 sp
->rxd_mode
= RXD_MODE_3A
;
7311 sp
->intr_type
= dev_intr_type
;
7313 if ((pdev
->device
== PCI_DEVICE_ID_HERC_WIN
) ||
7314 (pdev
->device
== PCI_DEVICE_ID_HERC_UNI
))
7315 sp
->device_type
= XFRAME_II_DEVICE
;
7317 sp
->device_type
= XFRAME_I_DEVICE
;
7321 /* Initialize some PCI/PCI-X fields of the NIC. */
7325 * Setting the device configuration parameters.
7326 * Most of these parameters can be specified by the user during
7327 * module insertion as they are module loadable parameters. If
7328 * these parameters are not not specified during load time, they
7329 * are initialized with default values.
7331 mac_control
= &sp
->mac_control
;
7332 config
= &sp
->config
;
7334 /* Tx side parameters. */
7335 config
->tx_fifo_num
= tx_fifo_num
;
7336 for (i
= 0; i
< MAX_TX_FIFOS
; i
++) {
7337 config
->tx_cfg
[i
].fifo_len
= tx_fifo_len
[i
];
7338 config
->tx_cfg
[i
].fifo_priority
= i
;
7341 /* mapping the QoS priority to the configured fifos */
7342 for (i
= 0; i
< MAX_TX_FIFOS
; i
++)
7343 config
->fifo_mapping
[i
] = fifo_map
[config
->tx_fifo_num
][i
];
7345 config
->tx_intr_type
= TXD_INT_TYPE_UTILZ
;
7346 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7347 config
->tx_cfg
[i
].f_no_snoop
=
7348 (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
7349 if (config
->tx_cfg
[i
].fifo_len
< 65) {
7350 config
->tx_intr_type
= TXD_INT_TYPE_PER_LIST
;
7354 /* + 2 because one Txd for skb->data and one Txd for UFO */
7355 config
->max_txds
= MAX_SKB_FRAGS
+ 2;
7357 /* Rx side parameters. */
7358 config
->rx_ring_num
= rx_ring_num
;
7359 for (i
= 0; i
< MAX_RX_RINGS
; i
++) {
7360 config
->rx_cfg
[i
].num_rxd
= rx_ring_sz
[i
] *
7361 (rxd_count
[sp
->rxd_mode
] + 1);
7362 config
->rx_cfg
[i
].ring_priority
= i
;
7365 for (i
= 0; i
< rx_ring_num
; i
++) {
7366 config
->rx_cfg
[i
].ring_org
= RING_ORG_BUFF1
;
7367 config
->rx_cfg
[i
].f_no_snoop
=
7368 (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
7371 /* Setting Mac Control parameters */
7372 mac_control
->rmac_pause_time
= rmac_pause_time
;
7373 mac_control
->mc_pause_threshold_q0q3
= mc_pause_threshold_q0q3
;
7374 mac_control
->mc_pause_threshold_q4q7
= mc_pause_threshold_q4q7
;
7377 /* Initialize Ring buffer parameters. */
7378 for (i
= 0; i
< config
->rx_ring_num
; i
++)
7379 atomic_set(&sp
->rx_bufs_left
[i
], 0);
7381 /* Initialize the number of ISRs currently running */
7382 atomic_set(&sp
->isr_cnt
, 0);
7384 /* initialize the shared memory used by the NIC and the host */
7385 if (init_shared_mem(sp
)) {
7386 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n",
7389 goto mem_alloc_failed
;
7392 sp
->bar0
= ioremap(pci_resource_start(pdev
, 0),
7393 pci_resource_len(pdev
, 0));
7395 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem1\n",
7398 goto bar0_remap_failed
;
7401 sp
->bar1
= ioremap(pci_resource_start(pdev
, 2),
7402 pci_resource_len(pdev
, 2));
7404 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem2\n",
7407 goto bar1_remap_failed
;
7410 dev
->irq
= pdev
->irq
;
7411 dev
->base_addr
= (unsigned long) sp
->bar0
;
7413 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7414 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
7415 mac_control
->tx_FIFO_start
[j
] = (struct TxFIFO_element __iomem
*)
7416 (sp
->bar1
+ (j
* 0x00020000));
7419 /* Driver entry points */
7420 dev
->open
= &s2io_open
;
7421 dev
->stop
= &s2io_close
;
7422 dev
->hard_start_xmit
= &s2io_xmit
;
7423 dev
->get_stats
= &s2io_get_stats
;
7424 dev
->set_multicast_list
= &s2io_set_multicast
;
7425 dev
->do_ioctl
= &s2io_ioctl
;
7426 dev
->change_mtu
= &s2io_change_mtu
;
7427 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
7428 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
7429 dev
->vlan_rx_register
= s2io_vlan_rx_register
;
7432 * will use eth_mac_addr() for dev->set_mac_address
7433 * mac address will be set every time dev->open() is called
7435 dev
->poll
= s2io_poll
;
7438 #ifdef CONFIG_NET_POLL_CONTROLLER
7439 dev
->poll_controller
= s2io_netpoll
;
7442 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
7443 if (sp
->high_dma_flag
== TRUE
)
7444 dev
->features
|= NETIF_F_HIGHDMA
;
7445 dev
->features
|= NETIF_F_TSO
;
7446 dev
->features
|= NETIF_F_TSO6
;
7447 if ((sp
->device_type
& XFRAME_II_DEVICE
) && (ufo
)) {
7448 dev
->features
|= NETIF_F_UFO
;
7449 dev
->features
|= NETIF_F_HW_CSUM
;
7452 dev
->tx_timeout
= &s2io_tx_watchdog
;
7453 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
7454 INIT_WORK(&sp
->rst_timer_task
, s2io_restart_nic
);
7455 INIT_WORK(&sp
->set_link_task
, s2io_set_link
);
7457 pci_save_state(sp
->pdev
);
7459 /* Setting swapper control on the NIC, for proper reset operation */
7460 if (s2io_set_swapper(sp
)) {
7461 DBG_PRINT(ERR_DBG
, "%s:swapper settings are wrong\n",
7464 goto set_swap_failed
;
7467 /* Verify if the Herc works on the slot its placed into */
7468 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7469 mode
= s2io_verify_pci_mode(sp
);
7471 DBG_PRINT(ERR_DBG
, "%s: ", __FUNCTION__
);
7472 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
7474 goto set_swap_failed
;
7478 /* Not needed for Herc */
7479 if (sp
->device_type
& XFRAME_I_DEVICE
) {
7481 * Fix for all "FFs" MAC address problems observed on
7484 fix_mac_address(sp
);
7489 * MAC address initialization.
7490 * For now only one mac address will be read and used.
7493 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
7494 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET
);
7495 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
7496 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
7497 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
, S2IO_BIT_RESET
);
7498 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
7499 mac_down
= (u32
) tmp64
;
7500 mac_up
= (u32
) (tmp64
>> 32);
7502 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_up
);
7503 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
7504 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
7505 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
7506 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
7507 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
7509 /* Set the factory defined MAC address initially */
7510 dev
->addr_len
= ETH_ALEN
;
7511 memcpy(dev
->dev_addr
, sp
->def_mac_addr
, ETH_ALEN
);
7513 /* reset Nic and bring it to known state */
7517 * Initialize the tasklet status and link state flags
7518 * and the card state parameter
7520 atomic_set(&(sp
->card_state
), 0);
7521 sp
->tasklet_status
= 0;
7524 /* Initialize spinlocks */
7525 spin_lock_init(&sp
->tx_lock
);
7528 spin_lock_init(&sp
->put_lock
);
7529 spin_lock_init(&sp
->rx_lock
);
7532 * SXE-002: Configure link and activity LED to init state
7535 subid
= sp
->pdev
->subsystem_device
;
7536 if ((subid
& 0xFF) >= 0x07) {
7537 val64
= readq(&bar0
->gpio_control
);
7538 val64
|= 0x0000800000000000ULL
;
7539 writeq(val64
, &bar0
->gpio_control
);
7540 val64
= 0x0411040400000000ULL
;
7541 writeq(val64
, (void __iomem
*) bar0
+ 0x2700);
7542 val64
= readq(&bar0
->gpio_control
);
7545 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
7547 if (register_netdev(dev
)) {
7548 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
7550 goto register_failed
;
7553 DBG_PRINT(ERR_DBG
, "Copyright(c) 2002-2007 Neterion Inc.\n");
7554 DBG_PRINT(ERR_DBG
, "%s: Neterion %s (rev %d)\n",dev
->name
,
7555 sp
->product_name
, get_xena_rev_id(sp
->pdev
));
7556 DBG_PRINT(ERR_DBG
, "%s: Driver version %s\n", dev
->name
,
7557 s2io_driver_version
);
7558 DBG_PRINT(ERR_DBG
, "%s: MAC ADDR: "
7559 "%02x:%02x:%02x:%02x:%02x:%02x", dev
->name
,
7560 sp
->def_mac_addr
[0].mac_addr
[0],
7561 sp
->def_mac_addr
[0].mac_addr
[1],
7562 sp
->def_mac_addr
[0].mac_addr
[2],
7563 sp
->def_mac_addr
[0].mac_addr
[3],
7564 sp
->def_mac_addr
[0].mac_addr
[4],
7565 sp
->def_mac_addr
[0].mac_addr
[5]);
7566 DBG_PRINT(ERR_DBG
, "SERIAL NUMBER: %s\n", sp
->serial_num
);
7567 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7568 mode
= s2io_print_pci_mode(sp
);
7570 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
7572 unregister_netdev(dev
);
7573 goto set_swap_failed
;
7576 switch(sp
->rxd_mode
) {
7578 DBG_PRINT(ERR_DBG
, "%s: 1-Buffer receive mode enabled\n",
7582 DBG_PRINT(ERR_DBG
, "%s: 2-Buffer receive mode enabled\n",
7586 DBG_PRINT(ERR_DBG
, "%s: 3-Buffer receive mode enabled\n",
7592 DBG_PRINT(ERR_DBG
, "%s: NAPI enabled\n", dev
->name
);
7593 switch(sp
->intr_type
) {
7595 DBG_PRINT(ERR_DBG
, "%s: Interrupt type INTA\n", dev
->name
);
7598 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI\n", dev
->name
);
7601 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI-X\n", dev
->name
);
7605 DBG_PRINT(ERR_DBG
, "%s: Large receive offload enabled\n",
7608 DBG_PRINT(ERR_DBG
, "%s: UDP Fragmentation Offload(UFO)"
7609 " enabled\n", dev
->name
);
7610 /* Initialize device name */
7611 sprintf(sp
->name
, "%s Neterion %s", dev
->name
, sp
->product_name
);
7613 /* Initialize bimodal Interrupts */
7614 sp
->config
.bimodal
= bimodal
;
7615 if (!(sp
->device_type
& XFRAME_II_DEVICE
) && bimodal
) {
7616 sp
->config
.bimodal
= 0;
7617 DBG_PRINT(ERR_DBG
,"%s:Bimodal intr not supported by Xframe I\n",
7622 * Make Link state as off at this point, when the Link change
7623 * interrupt comes the state will be automatically changed to
7626 netif_carrier_off(dev
);
7637 free_shared_mem(sp
);
7638 pci_disable_device(pdev
);
7639 if (dev_intr_type
!= MSI_X
)
7640 pci_release_regions(pdev
);
7642 release_mem_region(pci_resource_start(pdev
, 0),
7643 pci_resource_len(pdev
, 0));
7644 release_mem_region(pci_resource_start(pdev
, 2),
7645 pci_resource_len(pdev
, 2));
7647 pci_set_drvdata(pdev
, NULL
);
7654 * s2io_rem_nic - Free the PCI device
7655 * @pdev: structure containing the PCI related information of the device.
7656 * Description: This function is called by the Pci subsystem to release a
7657 * PCI device and free up all resource held up by the device. This could
7658 * be in response to a Hot plug event or when the driver is to be removed
7662 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
7664 struct net_device
*dev
=
7665 (struct net_device
*) pci_get_drvdata(pdev
);
7666 struct s2io_nic
*sp
;
7669 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
7673 flush_scheduled_work();
7676 unregister_netdev(dev
);
7678 free_shared_mem(sp
);
7681 if (sp
->intr_type
!= MSI_X
)
7682 pci_release_regions(pdev
);
7684 release_mem_region(pci_resource_start(pdev
, 0),
7685 pci_resource_len(pdev
, 0));
7686 release_mem_region(pci_resource_start(pdev
, 2),
7687 pci_resource_len(pdev
, 2));
7689 pci_set_drvdata(pdev
, NULL
);
7691 pci_disable_device(pdev
);
7695 * s2io_starter - Entry point for the driver
7696 * Description: This function is the entry point for the driver. It verifies
7697 * the module loadable parameters and initializes PCI configuration space.
7700 int __init
s2io_starter(void)
7702 return pci_register_driver(&s2io_driver
);
7706 * s2io_closer - Cleanup routine for the driver
7707 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7710 static __exit
void s2io_closer(void)
7712 pci_unregister_driver(&s2io_driver
);
7713 DBG_PRINT(INIT_DBG
, "cleanup done\n");
7716 module_init(s2io_starter
);
7717 module_exit(s2io_closer
);
7719 static int check_L2_lro_capable(u8
*buffer
, struct iphdr
**ip
,
7720 struct tcphdr
**tcp
, struct RxD_t
*rxdp
)
7723 u8 l2_type
= (u8
)((rxdp
->Control_1
>> 37) & 0x7), ip_len
;
7725 if (!(rxdp
->Control_1
& RXD_FRAME_PROTO_TCP
)) {
7726 DBG_PRINT(INIT_DBG
,"%s: Non-TCP frames not supported for LRO\n",
7732 * By default the VLAN field in the MAC is stripped by the card, if this
7733 * feature is turned off in rx_pa_cfg register, then the ip_off field
7734 * has to be shifted by a further 2 bytes
7737 case 0: /* DIX type */
7738 case 4: /* DIX type with VLAN */
7739 ip_off
= HEADER_ETHERNET_II_802_3_SIZE
;
7741 /* LLC, SNAP etc are considered non-mergeable */
7746 *ip
= (struct iphdr
*)((u8
*)buffer
+ ip_off
);
7747 ip_len
= (u8
)((*ip
)->ihl
);
7749 *tcp
= (struct tcphdr
*)((unsigned long)*ip
+ ip_len
);
7754 static int check_for_socket_match(struct lro
*lro
, struct iphdr
*ip
,
7757 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7758 if ((lro
->iph
->saddr
!= ip
->saddr
) || (lro
->iph
->daddr
!= ip
->daddr
) ||
7759 (lro
->tcph
->source
!= tcp
->source
) || (lro
->tcph
->dest
!= tcp
->dest
))
7764 static inline int get_l4_pyld_length(struct iphdr
*ip
, struct tcphdr
*tcp
)
7766 return(ntohs(ip
->tot_len
) - (ip
->ihl
<< 2) - (tcp
->doff
<< 2));
7769 static void initiate_new_session(struct lro
*lro
, u8
*l2h
,
7770 struct iphdr
*ip
, struct tcphdr
*tcp
, u32 tcp_pyld_len
)
7772 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7776 lro
->tcp_next_seq
= tcp_pyld_len
+ ntohl(tcp
->seq
);
7777 lro
->tcp_ack
= ntohl(tcp
->ack_seq
);
7779 lro
->total_len
= ntohs(ip
->tot_len
);
7782 * check if we saw TCP timestamp. Other consistency checks have
7783 * already been done.
7785 if (tcp
->doff
== 8) {
7787 ptr
= (u32
*)(tcp
+1);
7789 lro
->cur_tsval
= *(ptr
+1);
7790 lro
->cur_tsecr
= *(ptr
+2);
7795 static void update_L3L4_header(struct s2io_nic
*sp
, struct lro
*lro
)
7797 struct iphdr
*ip
= lro
->iph
;
7798 struct tcphdr
*tcp
= lro
->tcph
;
7800 struct stat_block
*statinfo
= sp
->mac_control
.stats_info
;
7801 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7803 /* Update L3 header */
7804 ip
->tot_len
= htons(lro
->total_len
);
7806 nchk
= ip_fast_csum((u8
*)lro
->iph
, ip
->ihl
);
7809 /* Update L4 header */
7810 tcp
->ack_seq
= lro
->tcp_ack
;
7811 tcp
->window
= lro
->window
;
7813 /* Update tsecr field if this session has timestamps enabled */
7815 u32
*ptr
= (u32
*)(tcp
+ 1);
7816 *(ptr
+2) = lro
->cur_tsecr
;
7819 /* Update counters required for calculation of
7820 * average no. of packets aggregated.
7822 statinfo
->sw_stat
.sum_avg_pkts_aggregated
+= lro
->sg_num
;
7823 statinfo
->sw_stat
.num_aggregations
++;
7826 static void aggregate_new_rx(struct lro
*lro
, struct iphdr
*ip
,
7827 struct tcphdr
*tcp
, u32 l4_pyld
)
7829 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7830 lro
->total_len
+= l4_pyld
;
7831 lro
->frags_len
+= l4_pyld
;
7832 lro
->tcp_next_seq
+= l4_pyld
;
7835 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7836 lro
->tcp_ack
= tcp
->ack_seq
;
7837 lro
->window
= tcp
->window
;
7841 /* Update tsecr and tsval from this packet */
7842 ptr
= (u32
*) (tcp
+ 1);
7843 lro
->cur_tsval
= *(ptr
+ 1);
7844 lro
->cur_tsecr
= *(ptr
+ 2);
7848 static int verify_l3_l4_lro_capable(struct lro
*l_lro
, struct iphdr
*ip
,
7849 struct tcphdr
*tcp
, u32 tcp_pyld_len
)
7853 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7855 if (!tcp_pyld_len
) {
7856 /* Runt frame or a pure ack */
7860 if (ip
->ihl
!= 5) /* IP has options */
7863 /* If we see CE codepoint in IP header, packet is not mergeable */
7864 if (INET_ECN_is_ce(ipv4_get_dsfield(ip
)))
7867 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7868 if (tcp
->urg
|| tcp
->psh
|| tcp
->rst
|| tcp
->syn
|| tcp
->fin
||
7869 tcp
->ece
|| tcp
->cwr
|| !tcp
->ack
) {
7871 * Currently recognize only the ack control word and
7872 * any other control field being set would result in
7873 * flushing the LRO session
7879 * Allow only one TCP timestamp option. Don't aggregate if
7880 * any other options are detected.
7882 if (tcp
->doff
!= 5 && tcp
->doff
!= 8)
7885 if (tcp
->doff
== 8) {
7886 ptr
= (u8
*)(tcp
+ 1);
7887 while (*ptr
== TCPOPT_NOP
)
7889 if (*ptr
!= TCPOPT_TIMESTAMP
|| *(ptr
+1) != TCPOLEN_TIMESTAMP
)
7892 /* Ensure timestamp value increases monotonically */
7894 if (l_lro
->cur_tsval
> *((u32
*)(ptr
+2)))
7897 /* timestamp echo reply should be non-zero */
7898 if (*((u32
*)(ptr
+6)) == 0)
7906 s2io_club_tcp_session(u8
*buffer
, u8
**tcp
, u32
*tcp_len
, struct lro
**lro
,
7907 struct RxD_t
*rxdp
, struct s2io_nic
*sp
)
7910 struct tcphdr
*tcph
;
7913 if (!(ret
= check_L2_lro_capable(buffer
, &ip
, (struct tcphdr
**)tcp
,
7915 DBG_PRINT(INFO_DBG
,"IP Saddr: %x Daddr: %x\n",
7916 ip
->saddr
, ip
->daddr
);
7921 tcph
= (struct tcphdr
*)*tcp
;
7922 *tcp_len
= get_l4_pyld_length(ip
, tcph
);
7923 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
7924 struct lro
*l_lro
= &sp
->lro0_n
[i
];
7925 if (l_lro
->in_use
) {
7926 if (check_for_socket_match(l_lro
, ip
, tcph
))
7928 /* Sock pair matched */
7931 if ((*lro
)->tcp_next_seq
!= ntohl(tcph
->seq
)) {
7932 DBG_PRINT(INFO_DBG
, "%s:Out of order. expected "
7933 "0x%x, actual 0x%x\n", __FUNCTION__
,
7934 (*lro
)->tcp_next_seq
,
7937 sp
->mac_control
.stats_info
->
7938 sw_stat
.outof_sequence_pkts
++;
7943 if (!verify_l3_l4_lro_capable(l_lro
, ip
, tcph
,*tcp_len
))
7944 ret
= 1; /* Aggregate */
7946 ret
= 2; /* Flush both */
7952 /* Before searching for available LRO objects,
7953 * check if the pkt is L3/L4 aggregatable. If not
7954 * don't create new LRO session. Just send this
7957 if (verify_l3_l4_lro_capable(NULL
, ip
, tcph
, *tcp_len
)) {
7961 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
7962 struct lro
*l_lro
= &sp
->lro0_n
[i
];
7963 if (!(l_lro
->in_use
)) {
7965 ret
= 3; /* Begin anew */
7971 if (ret
== 0) { /* sessions exceeded */
7972 DBG_PRINT(INFO_DBG
,"%s:All LRO sessions already in use\n",
7980 initiate_new_session(*lro
, buffer
, ip
, tcph
, *tcp_len
);
7983 update_L3L4_header(sp
, *lro
);
7986 aggregate_new_rx(*lro
, ip
, tcph
, *tcp_len
);
7987 if ((*lro
)->sg_num
== sp
->lro_max_aggr_per_sess
) {
7988 update_L3L4_header(sp
, *lro
);
7989 ret
= 4; /* Flush the LRO */
7993 DBG_PRINT(ERR_DBG
,"%s:Dont know, can't say!!\n",
8001 static void clear_lro_session(struct lro
*lro
)
8003 static u16 lro_struct_size
= sizeof(struct lro
);
8005 memset(lro
, 0, lro_struct_size
);
8008 static void queue_rx_frame(struct sk_buff
*skb
)
8010 struct net_device
*dev
= skb
->dev
;
8012 skb
->protocol
= eth_type_trans(skb
, dev
);
8014 netif_receive_skb(skb
);
8019 static void lro_append_pkt(struct s2io_nic
*sp
, struct lro
*lro
,
8020 struct sk_buff
*skb
,
8023 struct sk_buff
*first
= lro
->parent
;
8025 first
->len
+= tcp_len
;
8026 first
->data_len
= lro
->frags_len
;
8027 skb_pull(skb
, (skb
->len
- tcp_len
));
8028 if (skb_shinfo(first
)->frag_list
)
8029 lro
->last_frag
->next
= skb
;
8031 skb_shinfo(first
)->frag_list
= skb
;
8032 first
->truesize
+= skb
->truesize
;
8033 lro
->last_frag
= skb
;
8034 sp
->mac_control
.stats_info
->sw_stat
.clubbed_frms_cnt
++;
8039 * s2io_io_error_detected - called when PCI error is detected
8040 * @pdev: Pointer to PCI device
8041 * @state: The current pci connection state
8043 * This function is called after a PCI bus error affecting
8044 * this device has been detected.
8046 static pci_ers_result_t
s2io_io_error_detected(struct pci_dev
*pdev
,
8047 pci_channel_state_t state
)
8049 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8050 struct s2io_nic
*sp
= netdev
->priv
;
8052 netif_device_detach(netdev
);
8054 if (netif_running(netdev
)) {
8055 /* Bring down the card, while avoiding PCI I/O */
8056 do_s2io_card_down(sp
, 0);
8058 pci_disable_device(pdev
);
8060 return PCI_ERS_RESULT_NEED_RESET
;
8064 * s2io_io_slot_reset - called after the pci bus has been reset.
8065 * @pdev: Pointer to PCI device
8067 * Restart the card from scratch, as if from a cold-boot.
8068 * At this point, the card has exprienced a hard reset,
8069 * followed by fixups by BIOS, and has its config space
8070 * set up identically to what it was at cold boot.
8072 static pci_ers_result_t
s2io_io_slot_reset(struct pci_dev
*pdev
)
8074 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8075 struct s2io_nic
*sp
= netdev
->priv
;
8077 if (pci_enable_device(pdev
)) {
8078 printk(KERN_ERR
"s2io: "
8079 "Cannot re-enable PCI device after reset.\n");
8080 return PCI_ERS_RESULT_DISCONNECT
;
8083 pci_set_master(pdev
);
8086 return PCI_ERS_RESULT_RECOVERED
;
8090 * s2io_io_resume - called when traffic can start flowing again.
8091 * @pdev: Pointer to PCI device
8093 * This callback is called when the error recovery driver tells
8094 * us that its OK to resume normal operation.
8096 static void s2io_io_resume(struct pci_dev
*pdev
)
8098 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8099 struct s2io_nic
*sp
= netdev
->priv
;
8101 if (netif_running(netdev
)) {
8102 if (s2io_card_up(sp
)) {
8103 printk(KERN_ERR
"s2io: "
8104 "Can't bring device back up after reset.\n");
8108 if (s2io_set_mac_addr(netdev
, netdev
->dev_addr
) == FAILURE
) {
8110 printk(KERN_ERR
"s2io: "
8111 "Can't resetore mac addr after reset.\n");
8116 netif_device_attach(netdev
);
8117 netif_wake_queue(netdev
);