drivers/net/s2io.h

   1 /************************************************************************
   2  * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  ************************************************************************/
  13 #ifndef _S2IO_H
  14 #define _S2IO_H
  15
  16 #define TBD 0
  17 #define BIT(loc)                (0x8000000000000000ULL >> (loc))
  18 #define vBIT(val, loc, sz)      (((u64)val) << (64-loc-sz))
  19 #define INV(d)  ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  20
  21 #ifndef BOOL
  22 #define BOOL    int
  23 #endif
  24
  25 #ifndef TRUE
  26 #define TRUE    1
  27 #define FALSE   0
  28 #endif
  29
  30 #undef SUCCESS
  31 #define SUCCESS 0
  32 #define FAILURE -1
  33
  34 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
  35 #define MAX_FLICKER_TIME        60000 /* 60 Secs */
  36
  37 /* Maximum outstanding splits to be configured into xena. */
  38 typedef enum xena_max_outstanding_splits {
  39         XENA_ONE_SPLIT_TRANSACTION = 0,
  40         XENA_TWO_SPLIT_TRANSACTION = 1,
  41         XENA_THREE_SPLIT_TRANSACTION = 2,
  42         XENA_FOUR_SPLIT_TRANSACTION = 3,
  43         XENA_EIGHT_SPLIT_TRANSACTION = 4,
  44         XENA_TWELVE_SPLIT_TRANSACTION = 5,
  45         XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  46         XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  47 } xena_max_outstanding_splits;
  48 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  49
  50 /*  OS concerned variables and constants */
  51 #define WATCH_DOG_TIMEOUT               15*HZ
  52 #define EFILL                           0x1234
  53 #define ALIGN_SIZE                      127
  54 #define PCIX_COMMAND_REGISTER           0x62
  55
  56 /*
  57  * Debug related variables.
  58  */
  59 /* different debug levels. */
  60 #define ERR_DBG         0
  61 #define INIT_DBG        1
  62 #define INFO_DBG        2
  63 #define TX_DBG          3
  64 #define INTR_DBG        4
  65
  66 /* Global variable that defines the present debug level of the driver. */
  67 int debug_level = ERR_DBG;      /* Default level. */
  68
  69 /* DEBUG message print. */
  70 #define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args)
  71
  72 /* Protocol assist features of the NIC */
  73 #define L3_CKSUM_OK 0xFFFF
  74 #define L4_CKSUM_OK 0xFFFF
  75 #define S2IO_JUMBO_SIZE 9600
  76
  77 /* Driver statistics maintained by driver */
  78 typedef struct {
  79         unsigned long long single_ecc_errs;
  80         unsigned long long double_ecc_errs;
  81 } swStat_t;
  82
  83 /* The statistics block of Xena */
  84 typedef struct stat_block {
  85 /* Tx MAC statistics counters. */
  86         u32 tmac_data_octets;
  87         u32 tmac_frms;
  88         u64 tmac_drop_frms;
  89         u32 tmac_bcst_frms;
  90         u32 tmac_mcst_frms;
  91         u64 tmac_pause_ctrl_frms;
  92         u32 tmac_ucst_frms;
  93         u32 tmac_ttl_octets;
  94         u32 tmac_any_err_frms;
  95         u32 tmac_nucst_frms;
  96         u64 tmac_ttl_less_fb_octets;
  97         u64 tmac_vld_ip_octets;
  98         u32 tmac_drop_ip;
  99         u32 tmac_vld_ip;
 100         u32 tmac_rst_tcp;
 101         u32 tmac_icmp;
 102         u64 tmac_tcp;
 103         u32 reserved_0;
 104         u32 tmac_udp;
 105
 106 /* Rx MAC Statistics counters. */
 107         u32 rmac_data_octets;
 108         u32 rmac_vld_frms;
 109         u64 rmac_fcs_err_frms;
 110         u64 rmac_drop_frms;
 111         u32 rmac_vld_bcst_frms;
 112         u32 rmac_vld_mcst_frms;
 113         u32 rmac_out_rng_len_err_frms;
 114         u32 rmac_in_rng_len_err_frms;
 115         u64 rmac_long_frms;
 116         u64 rmac_pause_ctrl_frms;
 117         u64 rmac_unsup_ctrl_frms;
 118         u32 rmac_accepted_ucst_frms;
 119         u32 rmac_ttl_octets;
 120         u32 rmac_discarded_frms;
 121         u32 rmac_accepted_nucst_frms;
 122         u32 reserved_1;
 123         u32 rmac_drop_events;
 124         u64 rmac_ttl_less_fb_octets;
 125         u64 rmac_ttl_frms;
 126         u64 reserved_2;
 127         u32 rmac_usized_frms;
 128         u32 reserved_3;
 129         u32 rmac_frag_frms;
 130         u32 rmac_osized_frms;
 131         u32 reserved_4;
 132         u32 rmac_jabber_frms;
 133         u64 rmac_ttl_64_frms;
 134         u64 rmac_ttl_65_127_frms;
 135         u64 reserved_5;
 136         u64 rmac_ttl_128_255_frms;
 137         u64 rmac_ttl_256_511_frms;
 138         u64 reserved_6;
 139         u64 rmac_ttl_512_1023_frms;
 140         u64 rmac_ttl_1024_1518_frms;
 141         u32 rmac_ip;
 142         u32 reserved_7;
 143         u64 rmac_ip_octets;
 144         u32 rmac_drop_ip;
 145         u32 rmac_hdr_err_ip;
 146         u32 reserved_8;
 147         u32 rmac_icmp;
 148         u64 rmac_tcp;
 149         u32 rmac_err_drp_udp;
 150         u32 rmac_udp;
 151         u64 rmac_xgmii_err_sym;
 152         u64 rmac_frms_q0;
 153         u64 rmac_frms_q1;
 154         u64 rmac_frms_q2;
 155         u64 rmac_frms_q3;
 156         u64 rmac_frms_q4;
 157         u64 rmac_frms_q5;
 158         u64 rmac_frms_q6;
 159         u64 rmac_frms_q7;
 160         u16 rmac_full_q3;
 161         u16 rmac_full_q2;
 162         u16 rmac_full_q1;
 163         u16 rmac_full_q0;
 164         u16 rmac_full_q7;
 165         u16 rmac_full_q6;
 166         u16 rmac_full_q5;
 167         u16 rmac_full_q4;
 168         u32 reserved_9;
 169         u32 rmac_pause_cnt;
 170         u64 rmac_xgmii_data_err_cnt;
 171         u64 rmac_xgmii_ctrl_err_cnt;
 172         u32 rmac_err_tcp;
 173         u32 rmac_accepted_ip;
 174
 175 /* PCI/PCI-X Read transaction statistics. */
 176         u32 new_rd_req_cnt;
 177         u32 rd_req_cnt;
 178         u32 rd_rtry_cnt;
 179         u32 new_rd_req_rtry_cnt;
 180
 181 /* PCI/PCI-X Write/Read transaction statistics. */
 182         u32 wr_req_cnt;
 183         u32 wr_rtry_rd_ack_cnt;
 184         u32 new_wr_req_rtry_cnt;
 185         u32 new_wr_req_cnt;
 186         u32 wr_disc_cnt;
 187         u32 wr_rtry_cnt;
 188
 189 /*      PCI/PCI-X Write / DMA Transaction statistics. */
 190         u32 txp_wr_cnt;
 191         u32 rd_rtry_wr_ack_cnt;
 192         u32 txd_wr_cnt;
 193         u32 txd_rd_cnt;
 194         u32 rxd_wr_cnt;
 195         u32 rxd_rd_cnt;
 196         u32 rxf_wr_cnt;
 197         u32 txf_rd_cnt;
 198
 199 /* Tx MAC statistics overflow counters. */
 200         u32 tmac_data_octets_oflow;
 201         u32 tmac_frms_oflow;
 202         u32 tmac_bcst_frms_oflow;
 203         u32 tmac_mcst_frms_oflow;
 204         u32 tmac_ucst_frms_oflow;
 205         u32 tmac_ttl_octets_oflow;
 206         u32 tmac_any_err_frms_oflow;
 207         u32 tmac_nucst_frms_oflow;
 208         u64 tmac_vlan_frms;
 209         u32 tmac_drop_ip_oflow;
 210         u32 tmac_vld_ip_oflow;
 211         u32 tmac_rst_tcp_oflow;
 212         u32 tmac_icmp_oflow;
 213         u32 tpa_unknown_protocol;
 214         u32 tmac_udp_oflow;
 215         u32 reserved_10;
 216         u32 tpa_parse_failure;
 217
 218 /* Rx MAC Statistics overflow counters. */
 219         u32 rmac_data_octets_oflow;
 220         u32 rmac_vld_frms_oflow;
 221         u32 rmac_vld_bcst_frms_oflow;
 222         u32 rmac_vld_mcst_frms_oflow;
 223         u32 rmac_accepted_ucst_frms_oflow;
 224         u32 rmac_ttl_octets_oflow;
 225         u32 rmac_discarded_frms_oflow;
 226         u32 rmac_accepted_nucst_frms_oflow;
 227         u32 rmac_usized_frms_oflow;
 228         u32 rmac_drop_events_oflow;
 229         u32 rmac_frag_frms_oflow;
 230         u32 rmac_osized_frms_oflow;
 231         u32 rmac_ip_oflow;
 232         u32 rmac_jabber_frms_oflow;
 233         u32 rmac_icmp_oflow;
 234         u32 rmac_drop_ip_oflow;
 235         u32 rmac_err_drp_udp_oflow;
 236         u32 rmac_udp_oflow;
 237         u32 reserved_11;
 238         u32 rmac_pause_cnt_oflow;
 239         u64 rmac_ttl_1519_4095_frms;
 240         u64 rmac_ttl_4096_8191_frms;
 241         u64 rmac_ttl_8192_max_frms;
 242         u64 rmac_ttl_gt_max_frms;
 243         u64 rmac_osized_alt_frms;
 244         u64 rmac_jabber_alt_frms;
 245         u64 rmac_gt_max_alt_frms;
 246         u64 rmac_vlan_frms;
 247         u32 rmac_len_discard;
 248         u32 rmac_fcs_discard;
 249         u32 rmac_pf_discard;
 250         u32 rmac_da_discard;
 251         u32 rmac_red_discard;
 252         u32 rmac_rts_discard;
 253         u32 reserved_12;
 254         u32 rmac_ingm_full_discard;
 255         u32 reserved_13;
 256         u32 rmac_accepted_ip_oflow;
 257         u32 reserved_14;
 258         u32 link_fault_cnt;
 259         swStat_t sw_stat;
 260 } StatInfo_t;
 261
 262 /*
 263  * Structures representing different init time configuration
 264  * parameters of the NIC.
 265  */
 266
 267 #define MAX_TX_FIFOS 8
 268 #define MAX_RX_RINGS 8
 269
 270 /* FIFO mappings for all possible number of fifos configured */
 271 int fifo_map[][MAX_TX_FIFOS] = {
 272         {0, 0, 0, 0, 0, 0, 0, 0},
 273         {0, 0, 0, 0, 1, 1, 1, 1},
 274         {0, 0, 0, 1, 1, 1, 2, 2},
 275         {0, 0, 1, 1, 2, 2, 3, 3},
 276         {0, 0, 1, 1, 2, 2, 3, 4},
 277         {0, 0, 1, 1, 2, 3, 4, 5},
 278         {0, 0, 1, 2, 3, 4, 5, 6},
 279         {0, 1, 2, 3, 4, 5, 6, 7},
 280 };
 281
 282 /* Maintains Per FIFO related information. */
 283 typedef struct tx_fifo_config {
 284 #define MAX_AVAILABLE_TXDS      8192
 285         u32 fifo_len;           /* specifies len of FIFO upto 8192, ie no of TxDLs */
 286 /* Priority definition */
 287 #define TX_FIFO_PRI_0               0   /*Highest */
 288 #define TX_FIFO_PRI_1               1
 289 #define TX_FIFO_PRI_2               2
 290 #define TX_FIFO_PRI_3               3
 291 #define TX_FIFO_PRI_4               4
 292 #define TX_FIFO_PRI_5               5
 293 #define TX_FIFO_PRI_6               6
 294 #define TX_FIFO_PRI_7               7   /*lowest */
 295         u8 fifo_priority;       /* specifies pointer level for FIFO */
 296         /* user should not set twos fifos with same pri */
 297         u8 f_no_snoop;
 298 #define NO_SNOOP_TXD                0x01
 299 #define NO_SNOOP_TXD_BUFFER          0x02
 300 } tx_fifo_config_t;
 301
 302
 303 /* Maintains per Ring related information */
 304 typedef struct rx_ring_config {
 305         u32 num_rxd;            /*No of RxDs per Rx Ring */
 306 #define RX_RING_PRI_0               0   /* highest */
 307 #define RX_RING_PRI_1               1
 308 #define RX_RING_PRI_2               2
 309 #define RX_RING_PRI_3               3
 310 #define RX_RING_PRI_4               4
 311 #define RX_RING_PRI_5               5
 312 #define RX_RING_PRI_6               6
 313 #define RX_RING_PRI_7               7   /* lowest */
 314
 315         u8 ring_priority;       /*Specifies service priority of ring */
 316         /* OSM should not set any two rings with same priority */
 317         u8 ring_org;            /*Organization of ring */
 318 #define RING_ORG_BUFF1          0x01
 319 #define RX_RING_ORG_BUFF3       0x03
 320 #define RX_RING_ORG_BUFF5       0x05
 321
 322         u8 f_no_snoop;
 323 #define NO_SNOOP_RXD                0x01
 324 #define NO_SNOOP_RXD_BUFFER         0x02
 325 } rx_ring_config_t;
 326
 327 /* This structure provides contains values of the tunable parameters
 328  * of the H/W
 329  */
 330 struct config_param {
 331 /* Tx Side */
 332         u32 tx_fifo_num;        /*Number of Tx FIFOs */
 333
 334         u8 fifo_mapping[MAX_TX_FIFOS];
 335         tx_fifo_config_t tx_cfg[MAX_TX_FIFOS];  /*Per-Tx FIFO config */
 336         u32 max_txds;           /*Max no. of Tx buffer descriptor per TxDL */
 337         u64 tx_intr_type;
 338         /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
 339
 340 /* Rx Side */
 341         u32 rx_ring_num;        /*Number of receive rings */
 342 #define MAX_RX_BLOCKS_PER_RING  150
 343
 344         rx_ring_config_t rx_cfg[MAX_RX_RINGS];  /*Per-Rx Ring config */
 345         u8 bimodal;             /*Flag for setting bimodal interrupts*/
 346
 347 #define HEADER_ETHERNET_II_802_3_SIZE 14
 348 #define HEADER_802_2_SIZE              3
 349 #define HEADER_SNAP_SIZE               5
 350 #define HEADER_VLAN_SIZE               4
 351
 352 #define MIN_MTU                       46
 353 #define MAX_PYLD                    1500
 354 #define MAX_MTU                     (MAX_PYLD+18)
 355 #define MAX_MTU_VLAN                (MAX_PYLD+22)
 356 #define MAX_PYLD_JUMBO              9600
 357 #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
 358 #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
 359         u16 bus_speed;
 360 };
 361
 362 /* Structure representing MAC Addrs */
 363 typedef struct mac_addr {
 364         u8 mac_addr[ETH_ALEN];
 365 } macaddr_t;
 366
 367 /* Structure that represent every FIFO element in the BAR1
 368  * Address location.
 369  */
 370 typedef struct _TxFIFO_element {
 371         u64 TxDL_Pointer;
 372
 373         u64 List_Control;
 374 #define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
 375 #define TX_FIFO_FIRST_LIST             BIT(14)
 376 #define TX_FIFO_LAST_LIST              BIT(15)
 377 #define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
 378 #define TX_FIFO_SPECIAL_FUNC           BIT(23)
 379 #define TX_FIFO_DS_NO_SNOOP            BIT(31)
 380 #define TX_FIFO_BUFF_NO_SNOOP          BIT(30)
 381 } TxFIFO_element_t;
 382
 383 /* Tx descriptor structure */
 384 typedef struct _TxD {
 385         u64 Control_1;
 386 /* bit mask */
 387 #define TXD_LIST_OWN_XENA       BIT(7)
 388 #define TXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 389 #define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
 390 #define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
 391 #define TXD_GATHER_CODE         (BIT(22) | BIT(23))
 392 #define TXD_GATHER_CODE_FIRST   BIT(22)
 393 #define TXD_GATHER_CODE_LAST    BIT(23)
 394 #define TXD_TCP_LSO_EN          BIT(30)
 395 #define TXD_UDP_COF_EN          BIT(31)
 396 #define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
 397 #define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
 398
 399         u64 Control_2;
 400 #define TXD_TX_CKO_CONTROL      (BIT(5)|BIT(6)|BIT(7))
 401 #define TXD_TX_CKO_IPV4_EN      BIT(5)
 402 #define TXD_TX_CKO_TCP_EN       BIT(6)
 403 #define TXD_TX_CKO_UDP_EN       BIT(7)
 404 #define TXD_VLAN_ENABLE         BIT(15)
 405 #define TXD_VLAN_TAG(val)       vBIT(val,16,16)
 406 #define TXD_INT_NUMBER(val)     vBIT(val,34,6)
 407 #define TXD_INT_TYPE_PER_LIST   BIT(47)
 408 #define TXD_INT_TYPE_UTILZ      BIT(46)
 409 #define TXD_SET_MARKER         vBIT(0x6,0,4)
 410
 411         u64 Buffer_Pointer;
 412         u64 Host_Control;       /* reserved for host */
 413 } TxD_t;
 414
 415 /* Structure to hold the phy and virt addr of every TxDL. */
 416 typedef struct list_info_hold {
 417         dma_addr_t list_phy_addr;
 418         void *list_virt_addr;
 419 } list_info_hold_t;
 420
 421 /* Rx descriptor structure */
 422 typedef struct _RxD_t {
 423         u64 Host_Control;       /* reserved for host */
 424         u64 Control_1;
 425 #define RXD_OWN_XENA            BIT(7)
 426 #define RXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 427 #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
 428 #define RXD_FRAME_PROTO_IPV4    BIT(27)
 429 #define RXD_FRAME_PROTO_IPV6    BIT(28)
 430 #define RXD_FRAME_IP_FRAG       BIT(29)
 431 #define RXD_FRAME_PROTO_TCP     BIT(30)
 432 #define RXD_FRAME_PROTO_UDP     BIT(31)
 433 #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
 434 #define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
 435 #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
 436
 437         u64 Control_2;
 438 #define THE_RXD_MARK            0x3
 439 #define SET_RXD_MARKER          vBIT(THE_RXD_MARK, 0, 2)
 440 #define GET_RXD_MARKER(ctrl)    ((ctrl & SET_RXD_MARKER) >> 62)
 441
 442 #ifndef CONFIG_2BUFF_MODE
 443 #define MASK_BUFFER0_SIZE       vBIT(0x3FFF,2,14)
 444 #define SET_BUFFER0_SIZE(val)   vBIT(val,2,14)
 445 #else
 446 #define MASK_BUFFER0_SIZE       vBIT(0xFF,2,14)
 447 #define MASK_BUFFER1_SIZE       vBIT(0xFFFF,16,16)
 448 #define MASK_BUFFER2_SIZE       vBIT(0xFFFF,32,16)
 449 #define SET_BUFFER0_SIZE(val)   vBIT(val,8,8)
 450 #define SET_BUFFER1_SIZE(val)   vBIT(val,16,16)
 451 #define SET_BUFFER2_SIZE(val)   vBIT(val,32,16)
 452 #endif
 453
 454 #define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
 455 #define SET_VLAN_TAG(val)       vBIT(val,48,16)
 456 #define SET_NUM_TAG(val)       vBIT(val,16,32)
 457
 458 #ifndef CONFIG_2BUFF_MODE
 459 #define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
 460 #else
 461 #define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
 462                                                         >> 48)
 463 #define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \
 464                                                         >> 32)
 465 #define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \
 466                                                         >> 16)
 467 #define BUF0_LEN        40
 468 #define BUF1_LEN        1
 469 #endif
 470
 471         u64 Buffer0_ptr;
 472 #ifdef CONFIG_2BUFF_MODE
 473         u64 Buffer1_ptr;
 474         u64 Buffer2_ptr;
 475 #endif
 476 } RxD_t;
 477
 478 /* Structure that represents the Rx descriptor block which contains
 479  * 128 Rx descriptors.
 480  */
 481 #ifndef CONFIG_2BUFF_MODE
 482 typedef struct _RxD_block {
 483 #define MAX_RXDS_PER_BLOCK             127
 484         RxD_t rxd[MAX_RXDS_PER_BLOCK];
 485
 486         u64 reserved_0;
 487 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 488         u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last
 489                                  * Rxd in this blk */
 490         u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
 491         u64 pNext_RxD_Blk_physical;     /* Buff0_ptr.In a 32 bit arch
 492                                          * the upper 32 bits should
 493                                          * be 0 */
 494 } RxD_block_t;
 495 #else
 496 typedef struct _RxD_block {
 497 #define MAX_RXDS_PER_BLOCK             85
 498         RxD_t rxd[MAX_RXDS_PER_BLOCK];
 499
 500 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 501         u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
 502                                  * in this blk */
 503         u64 pNext_RxD_Blk_physical;     /* Phy ponter to next blk. */
 504 } RxD_block_t;
 505 #define SIZE_OF_BLOCK   4096
 506
 507 /* Structure to hold virtual addresses of Buf0 and Buf1 in
 508  * 2buf mode. */
 509 typedef struct bufAdd {
 510         void *ba_0_org;
 511         void *ba_1_org;
 512         void *ba_0;
 513         void *ba_1;
 514 } buffAdd_t;
 515 #endif
 516
 517 /* Structure which stores all the MAC control parameters */
 518
 519 /* This structure stores the offset of the RxD in the ring
 520  * from which the Rx Interrupt processor can start picking
 521  * up the RxDs for processing.
 522  */
 523 typedef struct _rx_curr_get_info_t {
 524         u32 block_index;
 525         u32 offset;
 526         u32 ring_len;
 527 } rx_curr_get_info_t;
 528
 529 typedef rx_curr_get_info_t rx_curr_put_info_t;
 530
 531 /* This structure stores the offset of the TxDl in the FIFO
 532  * from which the Tx Interrupt processor can start picking
 533  * up the TxDLs for send complete interrupt processing.
 534  */
 535 typedef struct {
 536         u32 offset;
 537         u32 fifo_len;
 538 } tx_curr_get_info_t;
 539
 540 typedef tx_curr_get_info_t tx_curr_put_info_t;
 541
 542 /* Structure that holds the Phy and virt addresses of the Blocks */
 543 typedef struct rx_block_info {
 544         RxD_t *block_virt_addr;
 545         dma_addr_t block_dma_addr;
 546 } rx_block_info_t;
 547
 548 /* pre declaration of the nic structure */
 549 typedef struct s2io_nic nic_t;
 550
 551 /* Ring specific structure */
 552 typedef struct ring_info {
 553         /* The ring number */
 554         int ring_no;
 555
 556         /*
 557          *  Place holders for the virtual and physical addresses of
 558          *  all the Rx Blocks
 559          */
 560         rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
 561         int block_count;
 562         int pkt_cnt;
 563
 564         /*
 565          * Put pointer info which indictes which RxD has to be replenished
 566          * with a new buffer.
 567          */
 568         rx_curr_put_info_t rx_curr_put_info;
 569
 570         /*
 571          * Get pointer info which indictes which is the last RxD that was
 572          * processed by the driver.
 573          */
 574         rx_curr_get_info_t rx_curr_get_info;
 575
 576 #ifndef CONFIG_S2IO_NAPI
 577         /* Index to the absolute position of the put pointer of Rx ring */
 578         int put_pos;
 579 #endif
 580
 581 #ifdef CONFIG_2BUFF_MODE
 582         /* Buffer Address store. */
 583         buffAdd_t **ba;
 584 #endif
 585         nic_t *nic;
 586 } ring_info_t;
 587
 588 /* Fifo specific structure */
 589 typedef struct fifo_info {
 590         /* FIFO number */
 591         int fifo_no;
 592
 593         /* Maximum TxDs per TxDL */
 594         int max_txds;
 595
 596         /* Place holder of all the TX List's Phy and Virt addresses. */
 597         list_info_hold_t *list_info;
 598
 599         /*
 600          * Current offset within the tx FIFO where driver would write
 601          * new Tx frame
 602          */
 603         tx_curr_put_info_t tx_curr_put_info;
 604
 605         /*
 606          * Current offset within tx FIFO from where the driver would start freeing
 607          * the buffers
 608          */
 609         tx_curr_get_info_t tx_curr_get_info;
 610
 611         nic_t *nic;
 612 }fifo_info_t;
 613
 614 /* Infomation related to the Tx and Rx FIFOs and Rings of Xena
 615  * is maintained in this structure.
 616  */
 617 typedef struct mac_info {
 618 /* tx side stuff */
 619         /* logical pointer of start of each Tx FIFO */
 620         TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
 621
 622         /* Fifo specific structure */
 623         fifo_info_t fifos[MAX_TX_FIFOS];
 624
 625 /* rx side stuff */
 626         /* Ring specific structure */
 627         ring_info_t rings[MAX_RX_RINGS];
 628
 629         u16 rmac_pause_time;
 630         u16 mc_pause_threshold_q0q3;
 631         u16 mc_pause_threshold_q4q7;
 632
 633         void *stats_mem;        /* orignal pointer to allocated mem */
 634         dma_addr_t stats_mem_phy;       /* Physical address of the stat block */
 635         u32 stats_mem_sz;
 636         StatInfo_t *stats_info; /* Logical address of the stat block */
 637 } mac_info_t;
 638
 639 /* structure representing the user defined MAC addresses */
 640 typedef struct {
 641         char addr[ETH_ALEN];
 642         int usage_cnt;
 643 } usr_addr_t;
 644
 645 /* Default Tunable parameters of the NIC. */
 646 #define DEFAULT_FIFO_LEN 4096
 647 #define SMALL_RXD_CNT   30 * (MAX_RXDS_PER_BLOCK+1)
 648 #define LARGE_RXD_CNT   100 * (MAX_RXDS_PER_BLOCK+1)
 649 #define SMALL_BLK_CNT   30
 650 #define LARGE_BLK_CNT   100
 651
 652 /* Structure representing one instance of the NIC */
 653 struct s2io_nic {
 654 #ifdef CONFIG_S2IO_NAPI
 655         /*
 656          * Count of packets to be processed in a given iteration, it will be indicated
 657          * by the quota field of the device structure when NAPI is enabled.
 658          */
 659         int pkts_to_process;
 660 #endif
 661         struct net_device *dev;
 662         mac_info_t mac_control;
 663         struct config_param config;
 664         struct pci_dev *pdev;
 665         void __iomem *bar0;
 666         void __iomem *bar1;
 667 #define MAX_MAC_SUPPORTED   16
 668 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
 669
 670         macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
 671         macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
 672
 673         struct net_device_stats stats;
 674         int high_dma_flag;
 675         int device_close_flag;
 676         int device_enabled_once;
 677
 678         char name[50];
 679         struct tasklet_struct task;
 680         volatile unsigned long tasklet_status;
 681
 682         /* Timer that handles I/O errors/exceptions */
 683         struct timer_list alarm_timer;
 684
 685         /* Space to back up the PCI config space */
 686         u32 config_space[256 / sizeof(u32)];
 687
 688         atomic_t rx_bufs_left[MAX_RX_RINGS];
 689
 690         spinlock_t tx_lock;
 691 #ifndef CONFIG_S2IO_NAPI
 692         spinlock_t put_lock;
 693 #endif
 694
 695 #define PROMISC     1
 696 #define ALL_MULTI   2
 697
 698 #define MAX_ADDRS_SUPPORTED 64
 699         u16 usr_addr_count;
 700         u16 mc_addr_count;
 701         usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
 702
 703         u16 m_cast_flg;
 704         u16 all_multi_pos;
 705         u16 promisc_flg;
 706
 707         u16 tx_pkt_count;
 708         u16 rx_pkt_count;
 709         u16 tx_err_count;
 710         u16 rx_err_count;
 711
 712         /*  Id timer, used to blink NIC to physically identify NIC. */
 713         struct timer_list id_timer;
 714
 715         /*  Restart timer, used to restart NIC if the device is stuck and
 716          *  a schedule task that will set the correct Link state once the
 717          *  NIC's PHY has stabilized after a state change.
 718          */
 719 #ifdef INIT_TQUEUE
 720         struct tq_struct rst_timer_task;
 721         struct tq_struct set_link_task;
 722 #else
 723         struct work_struct rst_timer_task;
 724         struct work_struct set_link_task;
 725 #endif
 726
 727         /* Flag that can be used to turn on or turn off the Rx checksum
 728          * offload feature.
 729          */
 730         int rx_csum;
 731
 732         /*  after blink, the adapter must be restored with original
 733          *  values.
 734          */
 735         u64 adapt_ctrl_org;
 736
 737         /* Last known link state. */
 738         u16 last_link_state;
 739 #define LINK_DOWN       1
 740 #define LINK_UP         2
 741
 742         int task_flag;
 743 #define CARD_DOWN 1
 744 #define CARD_UP 2
 745         atomic_t card_state;
 746         volatile unsigned long link_state;
 747         struct vlan_group *vlgrp;
 748 #define XFRAME_I_DEVICE         1
 749 #define XFRAME_II_DEVICE        2
 750         u8 device_type;
 751
 752         spinlock_t      rx_lock;
 753         atomic_t        isr_cnt;
 754 };
 755
 756 #define RESET_ERROR 1;
 757 #define CMD_ERROR   2;
 758
 759 /*  OS related system calls */
 760 #ifndef readq
 761 static inline u64 readq(void __iomem *addr)
 762 {
 763         u64 ret = 0;
 764         ret = readl(addr + 4);
 765         ret <<= 32;
 766         ret |= readl(addr);
 767
 768         return ret;
 769 }
 770 #endif
 771
 772 #ifndef writeq
 773 static inline void writeq(u64 val, void __iomem *addr)
 774 {
 775         writel((u32) (val), addr);
 776         writel((u32) (val >> 32), (addr + 4));
 777 }
 778
 779 /* In 32 bit modes, some registers have to be written in a
 780  * particular order to expect correct hardware operation. The
 781  * macro SPECIAL_REG_WRITE is used to perform such ordered
 782  * writes. Defines UF (Upper First) and LF (Lower First) will
 783  * be used to specify the required write order.
 784  */
 785 #define UF      1
 786 #define LF      2
 787 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
 788 {
 789         if (order == LF) {
 790                 writel((u32) (val), addr);
 791                 writel((u32) (val >> 32), (addr + 4));
 792         } else {
 793                 writel((u32) (val >> 32), (addr + 4));
 794                 writel((u32) (val), addr);
 795         }
 796 }
 797 #else
 798 #define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
 799 #endif
 800
 801 /*  Interrupt related values of Xena */
 802
 803 #define ENABLE_INTRS    1
 804 #define DISABLE_INTRS   2
 805
 806 /*  Highest level interrupt blocks */
 807 #define TX_PIC_INTR     (0x0001<<0)
 808 #define TX_DMA_INTR     (0x0001<<1)
 809 #define TX_MAC_INTR     (0x0001<<2)
 810 #define TX_XGXS_INTR    (0x0001<<3)
 811 #define TX_TRAFFIC_INTR (0x0001<<4)
 812 #define RX_PIC_INTR     (0x0001<<5)
 813 #define RX_DMA_INTR     (0x0001<<6)
 814 #define RX_MAC_INTR     (0x0001<<7)
 815 #define RX_XGXS_INTR    (0x0001<<8)
 816 #define RX_TRAFFIC_INTR (0x0001<<9)
 817 #define MC_INTR         (0x0001<<10)
 818 #define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
 819                             TX_DMA_INTR     | \
 820                             TX_MAC_INTR     | \
 821                             TX_XGXS_INTR    | \
 822                             TX_TRAFFIC_INTR | \
 823                             RX_PIC_INTR     | \
 824                             RX_DMA_INTR     | \
 825                             RX_MAC_INTR     | \
 826                             RX_XGXS_INTR    | \
 827                             RX_TRAFFIC_INTR | \
 828                             MC_INTR )
 829
 830 /*  Interrupt masks for the general interrupt mask register */
 831 #define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
 832
 833 #define TXPIC_INT_M         BIT(0)
 834 #define TXDMA_INT_M         BIT(1)
 835 #define TXMAC_INT_M         BIT(2)
 836 #define TXXGXS_INT_M        BIT(3)
 837 #define TXTRAFFIC_INT_M     BIT(8)
 838 #define PIC_RX_INT_M        BIT(32)
 839 #define RXDMA_INT_M         BIT(33)
 840 #define RXMAC_INT_M         BIT(34)
 841 #define MC_INT_M            BIT(35)
 842 #define RXXGXS_INT_M        BIT(36)
 843 #define RXTRAFFIC_INT_M     BIT(40)
 844
 845 /*  PIC level Interrupts TODO*/
 846
 847 /*  DMA level Inressupts */
 848 #define TXDMA_PFC_INT_M     BIT(0)
 849 #define TXDMA_PCC_INT_M     BIT(2)
 850
 851 /*  PFC block interrupts */
 852 #define PFC_MISC_ERR_1      BIT(0)      /* Interrupt to indicate FIFO full */
 853
 854 /* PCC block interrupts. */
 855 #define PCC_FB_ECC_ERR     vBIT(0xff, 16, 8)    /* Interrupt to indicate
 856                                                    PCC_FB_ECC Error. */
 857
 858 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
 859 /*
 860  * Prototype declaration.
 861  */
 862 static int __devinit s2io_init_nic(struct pci_dev *pdev,
 863                                    const struct pci_device_id *pre);
 864 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
 865 static int init_shared_mem(struct s2io_nic *sp);
 866 static void free_shared_mem(struct s2io_nic *sp);
 867 static int init_nic(struct s2io_nic *nic);
 868 static void rx_intr_handler(ring_info_t *ring_data);
 869 static void tx_intr_handler(fifo_info_t *fifo_data);
 870 static void alarm_intr_handler(struct s2io_nic *sp);
 871
 872 static int s2io_starter(void);
 873 void s2io_closer(void);
 874 static void s2io_tx_watchdog(struct net_device *dev);
 875 static void s2io_tasklet(unsigned long dev_addr);
 876 static void s2io_set_multicast(struct net_device *dev);
 877 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
 878 void s2io_link(nic_t * sp, int link);
 879 void s2io_reset(nic_t * sp);
 880 #if defined(CONFIG_S2IO_NAPI)
 881 static int s2io_poll(struct net_device *dev, int *budget);
 882 #endif
 883 static void s2io_init_pci(nic_t * sp);
 884 int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
 885 static void s2io_alarm_handle(unsigned long data);
 886 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
 887 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
 888 static struct ethtool_ops netdev_ethtool_ops;
 889 static void s2io_set_link(unsigned long data);
 890 int s2io_set_swapper(nic_t * sp);
 891 static void s2io_card_down(nic_t *nic);
 892 static int s2io_card_up(nic_t *nic);
 893 int get_xena_rev_id(struct pci_dev *pdev);
 894 #endif                          /* _S2IO_H */