drivers/net/s2io.h

   1 /************************************************************************
   2  * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  ************************************************************************/
  13 #ifndef _S2IO_H
  14 #define _S2IO_H
  15
  16 #define TBD 0
  17 #define s2BIT(loc)              (0x8000000000000000ULL >> (loc))
  18 #define vBIT(val, loc, sz)      (((u64)val) << (64-loc-sz))
  19 #define INV(d)  ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  20
  21 #ifndef BOOL
  22 #define BOOL    int
  23 #endif
  24
  25 #ifndef TRUE
  26 #define TRUE    1
  27 #define FALSE   0
  28 #endif
  29
  30 #undef SUCCESS
  31 #define SUCCESS 0
  32 #define FAILURE -1
  33 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
  34 #define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
  35 #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
  36 #define S2IO_BIT_RESET 1
  37 #define S2IO_BIT_SET 2
  38 #define CHECKBIT(value, nbit) (value & (1 << nbit))
  39
  40 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
  41 #define MAX_FLICKER_TIME        60000 /* 60 Secs */
  42
  43 /* Maximum outstanding splits to be configured into xena. */
  44 enum {
  45         XENA_ONE_SPLIT_TRANSACTION = 0,
  46         XENA_TWO_SPLIT_TRANSACTION = 1,
  47         XENA_THREE_SPLIT_TRANSACTION = 2,
  48         XENA_FOUR_SPLIT_TRANSACTION = 3,
  49         XENA_EIGHT_SPLIT_TRANSACTION = 4,
  50         XENA_TWELVE_SPLIT_TRANSACTION = 5,
  51         XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  52         XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  53 };
  54 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  55
  56 /*  OS concerned variables and constants */
  57 #define WATCH_DOG_TIMEOUT               15*HZ
  58 #define EFILL                           0x1234
  59 #define ALIGN_SIZE                      127
  60 #define PCIX_COMMAND_REGISTER           0x62
  61
  62 /*
  63  * Debug related variables.
  64  */
  65 /* different debug levels. */
  66 #define ERR_DBG         0
  67 #define INIT_DBG        1
  68 #define INFO_DBG        2
  69 #define TX_DBG          3
  70 #define INTR_DBG        4
  71
  72 /* Global variable that defines the present debug level of the driver. */
  73 static int debug_level = ERR_DBG;
  74
  75 /* DEBUG message print. */
  76 #define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args)
  77
  78 #ifndef DMA_ERROR_CODE
  79 #define DMA_ERROR_CODE          (~(dma_addr_t)0x0)
  80 #endif
  81
  82 /* Protocol assist features of the NIC */
  83 #define L3_CKSUM_OK 0xFFFF
  84 #define L4_CKSUM_OK 0xFFFF
  85 #define S2IO_JUMBO_SIZE 9600
  86
  87 /* Driver statistics maintained by driver */
  88 struct swStat {
  89         unsigned long long single_ecc_errs;
  90         unsigned long long double_ecc_errs;
  91         unsigned long long parity_err_cnt;
  92         unsigned long long serious_err_cnt;
  93         unsigned long long soft_reset_cnt;
  94         unsigned long long fifo_full_cnt;
  95         unsigned long long ring_full_cnt[8];
  96         /* LRO statistics */
  97         unsigned long long clubbed_frms_cnt;
  98         unsigned long long sending_both;
  99         unsigned long long outof_sequence_pkts;
 100         unsigned long long flush_max_pkts;
 101         unsigned long long sum_avg_pkts_aggregated;
 102         unsigned long long num_aggregations;
 103         /* Other statistics */
 104         unsigned long long mem_alloc_fail_cnt;
 105         unsigned long long pci_map_fail_cnt;
 106         unsigned long long watchdog_timer_cnt;
 107         unsigned long long mem_allocated;
 108         unsigned long long mem_freed;
 109         unsigned long long link_up_cnt;
 110         unsigned long long link_down_cnt;
 111         unsigned long long link_up_time;
 112         unsigned long long link_down_time;
 113
 114         /* Transfer Code statistics */
 115         unsigned long long tx_buf_abort_cnt;
 116         unsigned long long tx_desc_abort_cnt;
 117         unsigned long long tx_parity_err_cnt;
 118         unsigned long long tx_link_loss_cnt;
 119         unsigned long long tx_list_proc_err_cnt;
 120
 121         unsigned long long rx_parity_err_cnt;
 122         unsigned long long rx_abort_cnt;
 123         unsigned long long rx_parity_abort_cnt;
 124         unsigned long long rx_rda_fail_cnt;
 125         unsigned long long rx_unkn_prot_cnt;
 126         unsigned long long rx_fcs_err_cnt;
 127         unsigned long long rx_buf_size_err_cnt;
 128         unsigned long long rx_rxd_corrupt_cnt;
 129         unsigned long long rx_unkn_err_cnt;
 130
 131         /* Error/alarm statistics*/
 132         unsigned long long tda_err_cnt;
 133         unsigned long long pfc_err_cnt;
 134         unsigned long long pcc_err_cnt;
 135         unsigned long long tti_err_cnt;
 136         unsigned long long lso_err_cnt;
 137         unsigned long long tpa_err_cnt;
 138         unsigned long long sm_err_cnt;
 139         unsigned long long mac_tmac_err_cnt;
 140         unsigned long long mac_rmac_err_cnt;
 141         unsigned long long xgxs_txgxs_err_cnt;
 142         unsigned long long xgxs_rxgxs_err_cnt;
 143         unsigned long long rc_err_cnt;
 144         unsigned long long prc_pcix_err_cnt;
 145         unsigned long long rpa_err_cnt;
 146         unsigned long long rda_err_cnt;
 147         unsigned long long rti_err_cnt;
 148         unsigned long long mc_err_cnt;
 149
 150 };
 151
 152 /* Xpak releated alarm and warnings */
 153 struct xpakStat {
 154         u64 alarm_transceiver_temp_high;
 155         u64 alarm_transceiver_temp_low;
 156         u64 alarm_laser_bias_current_high;
 157         u64 alarm_laser_bias_current_low;
 158         u64 alarm_laser_output_power_high;
 159         u64 alarm_laser_output_power_low;
 160         u64 warn_transceiver_temp_high;
 161         u64 warn_transceiver_temp_low;
 162         u64 warn_laser_bias_current_high;
 163         u64 warn_laser_bias_current_low;
 164         u64 warn_laser_output_power_high;
 165         u64 warn_laser_output_power_low;
 166         u64 xpak_regs_stat;
 167         u32 xpak_timer_count;
 168 };
 169
 170
 171 /* The statistics block of Xena */
 172 struct stat_block {
 173 /* Tx MAC statistics counters. */
 174         __le32 tmac_data_octets;
 175         __le32 tmac_frms;
 176         __le64 tmac_drop_frms;
 177         __le32 tmac_bcst_frms;
 178         __le32 tmac_mcst_frms;
 179         __le64 tmac_pause_ctrl_frms;
 180         __le32 tmac_ucst_frms;
 181         __le32 tmac_ttl_octets;
 182         __le32 tmac_any_err_frms;
 183         __le32 tmac_nucst_frms;
 184         __le64 tmac_ttl_less_fb_octets;
 185         __le64 tmac_vld_ip_octets;
 186         __le32 tmac_drop_ip;
 187         __le32 tmac_vld_ip;
 188         __le32 tmac_rst_tcp;
 189         __le32 tmac_icmp;
 190         __le64 tmac_tcp;
 191         __le32 reserved_0;
 192         __le32 tmac_udp;
 193
 194 /* Rx MAC Statistics counters. */
 195         __le32 rmac_data_octets;
 196         __le32 rmac_vld_frms;
 197         __le64 rmac_fcs_err_frms;
 198         __le64 rmac_drop_frms;
 199         __le32 rmac_vld_bcst_frms;
 200         __le32 rmac_vld_mcst_frms;
 201         __le32 rmac_out_rng_len_err_frms;
 202         __le32 rmac_in_rng_len_err_frms;
 203         __le64 rmac_long_frms;
 204         __le64 rmac_pause_ctrl_frms;
 205         __le64 rmac_unsup_ctrl_frms;
 206         __le32 rmac_accepted_ucst_frms;
 207         __le32 rmac_ttl_octets;
 208         __le32 rmac_discarded_frms;
 209         __le32 rmac_accepted_nucst_frms;
 210         __le32 reserved_1;
 211         __le32 rmac_drop_events;
 212         __le64 rmac_ttl_less_fb_octets;
 213         __le64 rmac_ttl_frms;
 214         __le64 reserved_2;
 215         __le32 rmac_usized_frms;
 216         __le32 reserved_3;
 217         __le32 rmac_frag_frms;
 218         __le32 rmac_osized_frms;
 219         __le32 reserved_4;
 220         __le32 rmac_jabber_frms;
 221         __le64 rmac_ttl_64_frms;
 222         __le64 rmac_ttl_65_127_frms;
 223         __le64 reserved_5;
 224         __le64 rmac_ttl_128_255_frms;
 225         __le64 rmac_ttl_256_511_frms;
 226         __le64 reserved_6;
 227         __le64 rmac_ttl_512_1023_frms;
 228         __le64 rmac_ttl_1024_1518_frms;
 229         __le32 rmac_ip;
 230         __le32 reserved_7;
 231         __le64 rmac_ip_octets;
 232         __le32 rmac_drop_ip;
 233         __le32 rmac_hdr_err_ip;
 234         __le32 reserved_8;
 235         __le32 rmac_icmp;
 236         __le64 rmac_tcp;
 237         __le32 rmac_err_drp_udp;
 238         __le32 rmac_udp;
 239         __le64 rmac_xgmii_err_sym;
 240         __le64 rmac_frms_q0;
 241         __le64 rmac_frms_q1;
 242         __le64 rmac_frms_q2;
 243         __le64 rmac_frms_q3;
 244         __le64 rmac_frms_q4;
 245         __le64 rmac_frms_q5;
 246         __le64 rmac_frms_q6;
 247         __le64 rmac_frms_q7;
 248         __le16 rmac_full_q3;
 249         __le16 rmac_full_q2;
 250         __le16 rmac_full_q1;
 251         __le16 rmac_full_q0;
 252         __le16 rmac_full_q7;
 253         __le16 rmac_full_q6;
 254         __le16 rmac_full_q5;
 255         __le16 rmac_full_q4;
 256         __le32 reserved_9;
 257         __le32 rmac_pause_cnt;
 258         __le64 rmac_xgmii_data_err_cnt;
 259         __le64 rmac_xgmii_ctrl_err_cnt;
 260         __le32 rmac_err_tcp;
 261         __le32 rmac_accepted_ip;
 262
 263 /* PCI/PCI-X Read transaction statistics. */
 264         __le32 new_rd_req_cnt;
 265         __le32 rd_req_cnt;
 266         __le32 rd_rtry_cnt;
 267         __le32 new_rd_req_rtry_cnt;
 268
 269 /* PCI/PCI-X Write/Read transaction statistics. */
 270         __le32 wr_req_cnt;
 271         __le32 wr_rtry_rd_ack_cnt;
 272         __le32 new_wr_req_rtry_cnt;
 273         __le32 new_wr_req_cnt;
 274         __le32 wr_disc_cnt;
 275         __le32 wr_rtry_cnt;
 276
 277 /*      PCI/PCI-X Write / DMA Transaction statistics. */
 278         __le32 txp_wr_cnt;
 279         __le32 rd_rtry_wr_ack_cnt;
 280         __le32 txd_wr_cnt;
 281         __le32 txd_rd_cnt;
 282         __le32 rxd_wr_cnt;
 283         __le32 rxd_rd_cnt;
 284         __le32 rxf_wr_cnt;
 285         __le32 txf_rd_cnt;
 286
 287 /* Tx MAC statistics overflow counters. */
 288         __le32 tmac_data_octets_oflow;
 289         __le32 tmac_frms_oflow;
 290         __le32 tmac_bcst_frms_oflow;
 291         __le32 tmac_mcst_frms_oflow;
 292         __le32 tmac_ucst_frms_oflow;
 293         __le32 tmac_ttl_octets_oflow;
 294         __le32 tmac_any_err_frms_oflow;
 295         __le32 tmac_nucst_frms_oflow;
 296         __le64 tmac_vlan_frms;
 297         __le32 tmac_drop_ip_oflow;
 298         __le32 tmac_vld_ip_oflow;
 299         __le32 tmac_rst_tcp_oflow;
 300         __le32 tmac_icmp_oflow;
 301         __le32 tpa_unknown_protocol;
 302         __le32 tmac_udp_oflow;
 303         __le32 reserved_10;
 304         __le32 tpa_parse_failure;
 305
 306 /* Rx MAC Statistics overflow counters. */
 307         __le32 rmac_data_octets_oflow;
 308         __le32 rmac_vld_frms_oflow;
 309         __le32 rmac_vld_bcst_frms_oflow;
 310         __le32 rmac_vld_mcst_frms_oflow;
 311         __le32 rmac_accepted_ucst_frms_oflow;
 312         __le32 rmac_ttl_octets_oflow;
 313         __le32 rmac_discarded_frms_oflow;
 314         __le32 rmac_accepted_nucst_frms_oflow;
 315         __le32 rmac_usized_frms_oflow;
 316         __le32 rmac_drop_events_oflow;
 317         __le32 rmac_frag_frms_oflow;
 318         __le32 rmac_osized_frms_oflow;
 319         __le32 rmac_ip_oflow;
 320         __le32 rmac_jabber_frms_oflow;
 321         __le32 rmac_icmp_oflow;
 322         __le32 rmac_drop_ip_oflow;
 323         __le32 rmac_err_drp_udp_oflow;
 324         __le32 rmac_udp_oflow;
 325         __le32 reserved_11;
 326         __le32 rmac_pause_cnt_oflow;
 327         __le64 rmac_ttl_1519_4095_frms;
 328         __le64 rmac_ttl_4096_8191_frms;
 329         __le64 rmac_ttl_8192_max_frms;
 330         __le64 rmac_ttl_gt_max_frms;
 331         __le64 rmac_osized_alt_frms;
 332         __le64 rmac_jabber_alt_frms;
 333         __le64 rmac_gt_max_alt_frms;
 334         __le64 rmac_vlan_frms;
 335         __le32 rmac_len_discard;
 336         __le32 rmac_fcs_discard;
 337         __le32 rmac_pf_discard;
 338         __le32 rmac_da_discard;
 339         __le32 rmac_red_discard;
 340         __le32 rmac_rts_discard;
 341         __le32 reserved_12;
 342         __le32 rmac_ingm_full_discard;
 343         __le32 reserved_13;
 344         __le32 rmac_accepted_ip_oflow;
 345         __le32 reserved_14;
 346         __le32 link_fault_cnt;
 347         u8  buffer[20];
 348         struct swStat sw_stat;
 349         struct xpakStat xpak_stat;
 350 };
 351
 352 /* Default value for 'vlan_strip_tag' configuration parameter */
 353 #define NO_STRIP_IN_PROMISC 2
 354
 355 /*
 356  * Structures representing different init time configuration
 357  * parameters of the NIC.
 358  */
 359
 360 #define MAX_TX_FIFOS 8
 361 #define MAX_RX_RINGS 8
 362
 363 #define FIFO_DEFAULT_NUM        5
 364 #define FIFO_UDP_MAX_NUM                        2 /* 0 - even, 1 -odd ports */
 365 #define FIFO_OTHER_MAX_NUM                      1
 366
 367
 368 #define MAX_RX_DESC_1  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
 369 #define MAX_RX_DESC_2  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
 370 #define MAX_RX_DESC_3  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
 371 #define MAX_TX_DESC    (MAX_AVAILABLE_TXDS)
 372
 373 /* FIFO mappings for all possible number of fifos configured */
 374 static int fifo_map[][MAX_TX_FIFOS] = {
 375         {0, 0, 0, 0, 0, 0, 0, 0},
 376         {0, 0, 0, 0, 1, 1, 1, 1},
 377         {0, 0, 0, 1, 1, 1, 2, 2},
 378         {0, 0, 1, 1, 2, 2, 3, 3},
 379         {0, 0, 1, 1, 2, 2, 3, 4},
 380         {0, 0, 1, 1, 2, 3, 4, 5},
 381         {0, 0, 1, 2, 3, 4, 5, 6},
 382         {0, 1, 2, 3, 4, 5, 6, 7},
 383 };
 384
 385 static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
 386
 387 /* Maintains Per FIFO related information. */
 388 struct tx_fifo_config {
 389 #define MAX_AVAILABLE_TXDS      8192
 390         u32 fifo_len;           /* specifies len of FIFO upto 8192, ie no of TxDLs */
 391 /* Priority definition */
 392 #define TX_FIFO_PRI_0               0   /*Highest */
 393 #define TX_FIFO_PRI_1               1
 394 #define TX_FIFO_PRI_2               2
 395 #define TX_FIFO_PRI_3               3
 396 #define TX_FIFO_PRI_4               4
 397 #define TX_FIFO_PRI_5               5
 398 #define TX_FIFO_PRI_6               6
 399 #define TX_FIFO_PRI_7               7   /*lowest */
 400         u8 fifo_priority;       /* specifies pointer level for FIFO */
 401         /* user should not set twos fifos with same pri */
 402         u8 f_no_snoop;
 403 #define NO_SNOOP_TXD                0x01
 404 #define NO_SNOOP_TXD_BUFFER          0x02
 405 };
 406
 407
 408 /* Maintains per Ring related information */
 409 struct rx_ring_config {
 410         u32 num_rxd;            /*No of RxDs per Rx Ring */
 411 #define RX_RING_PRI_0               0   /* highest */
 412 #define RX_RING_PRI_1               1
 413 #define RX_RING_PRI_2               2
 414 #define RX_RING_PRI_3               3
 415 #define RX_RING_PRI_4               4
 416 #define RX_RING_PRI_5               5
 417 #define RX_RING_PRI_6               6
 418 #define RX_RING_PRI_7               7   /* lowest */
 419
 420         u8 ring_priority;       /*Specifies service priority of ring */
 421         /* OSM should not set any two rings with same priority */
 422         u8 ring_org;            /*Organization of ring */
 423 #define RING_ORG_BUFF1          0x01
 424 #define RX_RING_ORG_BUFF3       0x03
 425 #define RX_RING_ORG_BUFF5       0x05
 426
 427         u8 f_no_snoop;
 428 #define NO_SNOOP_RXD                0x01
 429 #define NO_SNOOP_RXD_BUFFER         0x02
 430 };
 431
 432 /* This structure provides contains values of the tunable parameters
 433  * of the H/W
 434  */
 435 struct config_param {
 436 /* Tx Side */
 437         u32 tx_fifo_num;        /*Number of Tx FIFOs */
 438
 439         /* 0-No steering, 1-Priority steering, 2-Default fifo map */
 440 #define NO_STEERING                             0
 441 #define TX_PRIORITY_STEERING                    0x1
 442 #define TX_DEFAULT_STEERING                     0x2
 443         u8 tx_steering_type;
 444
 445         u8 fifo_mapping[MAX_TX_FIFOS];
 446         struct tx_fifo_config tx_cfg[MAX_TX_FIFOS];     /*Per-Tx FIFO config */
 447         u32 max_txds;           /*Max no. of Tx buffer descriptor per TxDL */
 448         u64 tx_intr_type;
 449 #define INTA    0
 450 #define MSI_X   2
 451         u8 intr_type;
 452         u8 napi;
 453
 454         /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
 455
 456 /* Rx Side */
 457         u32 rx_ring_num;        /*Number of receive rings */
 458 #define MAX_RX_BLOCKS_PER_RING  150
 459
 460         struct rx_ring_config rx_cfg[MAX_RX_RINGS];     /*Per-Rx Ring config */
 461
 462 #define HEADER_ETHERNET_II_802_3_SIZE 14
 463 #define HEADER_802_2_SIZE              3
 464 #define HEADER_SNAP_SIZE               5
 465 #define HEADER_VLAN_SIZE               4
 466
 467 #define MIN_MTU                       46
 468 #define MAX_PYLD                    1500
 469 #define MAX_MTU                     (MAX_PYLD+18)
 470 #define MAX_MTU_VLAN                (MAX_PYLD+22)
 471 #define MAX_PYLD_JUMBO              9600
 472 #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
 473 #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
 474         u16 bus_speed;
 475         int max_mc_addr;        /* xena=64 herc=256 */
 476         int max_mac_addr;       /* xena=16 herc=64 */
 477         int mc_start_offset;    /* xena=16 herc=64 */
 478         u8 multiq;
 479 };
 480
 481 /* Structure representing MAC Addrs */
 482 struct mac_addr {
 483         u8 mac_addr[ETH_ALEN];
 484 };
 485
 486 /* Structure that represent every FIFO element in the BAR1
 487  * Address location.
 488  */
 489 struct TxFIFO_element {
 490         u64 TxDL_Pointer;
 491
 492         u64 List_Control;
 493 #define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
 494 #define TX_FIFO_FIRST_LIST             s2BIT(14)
 495 #define TX_FIFO_LAST_LIST              s2BIT(15)
 496 #define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
 497 #define TX_FIFO_SPECIAL_FUNC           s2BIT(23)
 498 #define TX_FIFO_DS_NO_SNOOP            s2BIT(31)
 499 #define TX_FIFO_BUFF_NO_SNOOP          s2BIT(30)
 500 };
 501
 502 /* Tx descriptor structure */
 503 struct TxD {
 504         u64 Control_1;
 505 /* bit mask */
 506 #define TXD_LIST_OWN_XENA       s2BIT(7)
 507 #define TXD_T_CODE              (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
 508 #define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
 509 #define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
 510 #define TXD_GATHER_CODE         (s2BIT(22) | s2BIT(23))
 511 #define TXD_GATHER_CODE_FIRST   s2BIT(22)
 512 #define TXD_GATHER_CODE_LAST    s2BIT(23)
 513 #define TXD_TCP_LSO_EN          s2BIT(30)
 514 #define TXD_UDP_COF_EN          s2BIT(31)
 515 #define TXD_UFO_EN              s2BIT(31) | s2BIT(30)
 516 #define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
 517 #define TXD_UFO_MSS(val)        vBIT(val,34,14)
 518 #define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
 519
 520         u64 Control_2;
 521 #define TXD_TX_CKO_CONTROL      (s2BIT(5)|s2BIT(6)|s2BIT(7))
 522 #define TXD_TX_CKO_IPV4_EN      s2BIT(5)
 523 #define TXD_TX_CKO_TCP_EN       s2BIT(6)
 524 #define TXD_TX_CKO_UDP_EN       s2BIT(7)
 525 #define TXD_VLAN_ENABLE         s2BIT(15)
 526 #define TXD_VLAN_TAG(val)       vBIT(val,16,16)
 527 #define TXD_INT_NUMBER(val)     vBIT(val,34,6)
 528 #define TXD_INT_TYPE_PER_LIST   s2BIT(47)
 529 #define TXD_INT_TYPE_UTILZ      s2BIT(46)
 530 #define TXD_SET_MARKER         vBIT(0x6,0,4)
 531
 532         u64 Buffer_Pointer;
 533         u64 Host_Control;       /* reserved for host */
 534 };
 535
 536 /* Structure to hold the phy and virt addr of every TxDL. */
 537 struct list_info_hold {
 538         dma_addr_t list_phy_addr;
 539         void *list_virt_addr;
 540 };
 541
 542 /* Rx descriptor structure for 1 buffer mode */
 543 struct RxD_t {
 544         u64 Host_Control;       /* reserved for host */
 545         u64 Control_1;
 546 #define RXD_OWN_XENA            s2BIT(7)
 547 #define RXD_T_CODE              (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
 548 #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
 549 #define RXD_FRAME_PROTO_IPV4    s2BIT(27)
 550 #define RXD_FRAME_PROTO_IPV6    s2BIT(28)
 551 #define RXD_FRAME_IP_FRAG       s2BIT(29)
 552 #define RXD_FRAME_PROTO_TCP     s2BIT(30)
 553 #define RXD_FRAME_PROTO_UDP     s2BIT(31)
 554 #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
 555 #define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
 556 #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
 557
 558         u64 Control_2;
 559 #define THE_RXD_MARK            0x3
 560 #define SET_RXD_MARKER          vBIT(THE_RXD_MARK, 0, 2)
 561 #define GET_RXD_MARKER(ctrl)    ((ctrl & SET_RXD_MARKER) >> 62)
 562
 563 #define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
 564 #define SET_VLAN_TAG(val)       vBIT(val,48,16)
 565 #define SET_NUM_TAG(val)       vBIT(val,16,32)
 566
 567
 568 };
 569 /* Rx descriptor structure for 1 buffer mode */
 570 struct RxD1 {
 571         struct RxD_t h;
 572
 573 #define MASK_BUFFER0_SIZE_1       vBIT(0x3FFF,2,14)
 574 #define SET_BUFFER0_SIZE_1(val)   vBIT(val,2,14)
 575 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
 576         (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
 577         u64 Buffer0_ptr;
 578 };
 579 /* Rx descriptor structure for 3 or 2 buffer mode */
 580
 581 struct RxD3 {
 582         struct RxD_t h;
 583
 584 #define MASK_BUFFER0_SIZE_3       vBIT(0xFF,2,14)
 585 #define MASK_BUFFER1_SIZE_3       vBIT(0xFFFF,16,16)
 586 #define MASK_BUFFER2_SIZE_3       vBIT(0xFFFF,32,16)
 587 #define SET_BUFFER0_SIZE_3(val)   vBIT(val,8,8)
 588 #define SET_BUFFER1_SIZE_3(val)   vBIT(val,16,16)
 589 #define SET_BUFFER2_SIZE_3(val)   vBIT(val,32,16)
 590 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
 591         (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
 592 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
 593         (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
 594 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
 595         (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
 596 #define BUF0_LEN        40
 597 #define BUF1_LEN        1
 598
 599         u64 Buffer0_ptr;
 600         u64 Buffer1_ptr;
 601         u64 Buffer2_ptr;
 602 };
 603
 604
 605 /* Structure that represents the Rx descriptor block which contains
 606  * 128 Rx descriptors.
 607  */
 608 struct RxD_block {
 609 #define MAX_RXDS_PER_BLOCK_1            127
 610         struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
 611
 612         u64 reserved_0;
 613 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 614         u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last
 615                                  * Rxd in this blk */
 616         u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
 617         u64 pNext_RxD_Blk_physical;     /* Buff0_ptr.In a 32 bit arch
 618                                          * the upper 32 bits should
 619                                          * be 0 */
 620 };
 621
 622 #define SIZE_OF_BLOCK   4096
 623
 624 #define RXD_MODE_1      0 /* One Buffer mode */
 625 #define RXD_MODE_3B     1 /* Two Buffer mode */
 626
 627 /* Structure to hold virtual addresses of Buf0 and Buf1 in
 628  * 2buf mode. */
 629 struct buffAdd {
 630         void *ba_0_org;
 631         void *ba_1_org;
 632         void *ba_0;
 633         void *ba_1;
 634 };
 635
 636 /* Structure which stores all the MAC control parameters */
 637
 638 /* This structure stores the offset of the RxD in the ring
 639  * from which the Rx Interrupt processor can start picking
 640  * up the RxDs for processing.
 641  */
 642 struct rx_curr_get_info {
 643         u32 block_index;
 644         u32 offset;
 645         u32 ring_len;
 646 };
 647
 648 struct rx_curr_put_info {
 649         u32 block_index;
 650         u32 offset;
 651         u32 ring_len;
 652 };
 653
 654 /* This structure stores the offset of the TxDl in the FIFO
 655  * from which the Tx Interrupt processor can start picking
 656  * up the TxDLs for send complete interrupt processing.
 657  */
 658 struct tx_curr_get_info {
 659         u32 offset;
 660         u32 fifo_len;
 661 };
 662
 663 struct tx_curr_put_info {
 664         u32 offset;
 665         u32 fifo_len;
 666 };
 667
 668 struct rxd_info {
 669         void *virt_addr;
 670         dma_addr_t dma_addr;
 671 };
 672
 673 /* Structure that holds the Phy and virt addresses of the Blocks */
 674 struct rx_block_info {
 675         void *block_virt_addr;
 676         dma_addr_t block_dma_addr;
 677         struct rxd_info *rxds;
 678 };
 679
 680 /* Ring specific structure */
 681 struct ring_info {
 682         /* The ring number */
 683         int ring_no;
 684
 685         /*
 686          *  Place holders for the virtual and physical addresses of
 687          *  all the Rx Blocks
 688          */
 689         struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
 690         int block_count;
 691         int pkt_cnt;
 692
 693         /*
 694          * Put pointer info which indictes which RxD has to be replenished
 695          * with a new buffer.
 696          */
 697         struct rx_curr_put_info rx_curr_put_info;
 698
 699         /*
 700          * Get pointer info which indictes which is the last RxD that was
 701          * processed by the driver.
 702          */
 703         struct rx_curr_get_info rx_curr_get_info;
 704
 705         /* Index to the absolute position of the put pointer of Rx ring */
 706         int put_pos;
 707
 708         /* Buffer Address store. */
 709         struct buffAdd **ba;
 710         struct s2io_nic *nic;
 711 };
 712
 713 /* Fifo specific structure */
 714 struct fifo_info {
 715         /* FIFO number */
 716         int fifo_no;
 717
 718         /* Maximum TxDs per TxDL */
 719         int max_txds;
 720
 721         /* Place holder of all the TX List's Phy and Virt addresses. */
 722         struct list_info_hold *list_info;
 723
 724         /*
 725          * Current offset within the tx FIFO where driver would write
 726          * new Tx frame
 727          */
 728         struct tx_curr_put_info tx_curr_put_info;
 729
 730         /*
 731          * Current offset within tx FIFO from where the driver would start freeing
 732          * the buffers
 733          */
 734         struct tx_curr_get_info tx_curr_get_info;
 735 #define FIFO_QUEUE_START 0
 736 #define FIFO_QUEUE_STOP 1
 737         int queue_state;
 738
 739         /* copy of sp->dev pointer */
 740         struct net_device *dev;
 741
 742         /* copy of multiq status */
 743         u8 multiq;
 744
 745         /* Per fifo lock */
 746         spinlock_t tx_lock;
 747
 748         /* Per fifo UFO in band structure */
 749         u64 *ufo_in_band_v;
 750
 751         struct s2io_nic *nic;
 752 } ____cacheline_aligned;
 753
 754 /* Information related to the Tx and Rx FIFOs and Rings of Xena
 755  * is maintained in this structure.
 756  */
 757 struct mac_info {
 758 /* tx side stuff */
 759         /* logical pointer of start of each Tx FIFO */
 760         struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
 761
 762         /* Fifo specific structure */
 763         struct fifo_info fifos[MAX_TX_FIFOS];
 764
 765         /* Save virtual address of TxD page with zero DMA addr(if any) */
 766         void *zerodma_virt_addr;
 767
 768 /* rx side stuff */
 769         /* Ring specific structure */
 770         struct ring_info rings[MAX_RX_RINGS];
 771
 772         u16 rmac_pause_time;
 773         u16 mc_pause_threshold_q0q3;
 774         u16 mc_pause_threshold_q4q7;
 775
 776         void *stats_mem;        /* orignal pointer to allocated mem */
 777         dma_addr_t stats_mem_phy;       /* Physical address of the stat block */
 778         u32 stats_mem_sz;
 779         struct stat_block *stats_info;  /* Logical address of the stat block */
 780 };
 781
 782 /* structure representing the user defined MAC addresses */
 783 struct usr_addr {
 784         char addr[ETH_ALEN];
 785         int usage_cnt;
 786 };
 787
 788 /* Default Tunable parameters of the NIC. */
 789 #define DEFAULT_FIFO_0_LEN 4096
 790 #define DEFAULT_FIFO_1_7_LEN 512
 791 #define SMALL_BLK_CNT   30
 792 #define LARGE_BLK_CNT   100
 793
 794 /*
 795  * Structure to keep track of the MSI-X vectors and the corresponding
 796  * argument registered against each vector
 797  */
 798 #define MAX_REQUESTED_MSI_X     17
 799 struct s2io_msix_entry
 800 {
 801         u16 vector;
 802         u16 entry;
 803         void *arg;
 804
 805         u8 type;
 806 #define MSIX_FIFO_TYPE  1
 807 #define MSIX_RING_TYPE  2
 808
 809         u8 in_use;
 810 #define MSIX_REGISTERED_SUCCESS 0xAA
 811 };
 812
 813 struct msix_info_st {
 814         u64 addr;
 815         u64 data;
 816 };
 817
 818 /* Data structure to represent a LRO session */
 819 struct lro {
 820         struct sk_buff  *parent;
 821         struct sk_buff  *last_frag;
 822         u8              *l2h;
 823         struct iphdr    *iph;
 824         struct tcphdr   *tcph;
 825         u32             tcp_next_seq;
 826         __be32          tcp_ack;
 827         int             total_len;
 828         int             frags_len;
 829         int             sg_num;
 830         int             in_use;
 831         __be16          window;
 832         u32             cur_tsval;
 833         __be32          cur_tsecr;
 834         u8              saw_ts;
 835 };
 836
 837 /* These flags represent the devices temporary state */
 838 enum s2io_device_state_t
 839 {
 840         __S2IO_STATE_LINK_TASK=0,
 841         __S2IO_STATE_CARD_UP
 842 };
 843
 844 /* Structure representing one instance of the NIC */
 845 struct s2io_nic {
 846         int rxd_mode;
 847         /*
 848          * Count of packets to be processed in a given iteration, it will be indicated
 849          * by the quota field of the device structure when NAPI is enabled.
 850          */
 851         int pkts_to_process;
 852         struct net_device *dev;
 853         struct napi_struct napi;
 854         struct mac_info mac_control;
 855         struct config_param config;
 856         struct pci_dev *pdev;
 857         void __iomem *bar0;
 858         void __iomem *bar1;
 859 #define MAX_MAC_SUPPORTED   16
 860 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
 861
 862         struct mac_addr def_mac_addr[256];
 863
 864         struct net_device_stats stats;
 865         int high_dma_flag;
 866         int device_enabled_once;
 867
 868         char name[60];
 869         struct tasklet_struct task;
 870         volatile unsigned long tasklet_status;
 871
 872         /* Timer that handles I/O errors/exceptions */
 873         struct timer_list alarm_timer;
 874
 875         /* Space to back up the PCI config space */
 876         u32 config_space[256 / sizeof(u32)];
 877
 878         atomic_t rx_bufs_left[MAX_RX_RINGS];
 879
 880         spinlock_t put_lock;
 881
 882 #define PROMISC     1
 883 #define ALL_MULTI   2
 884
 885 #define MAX_ADDRS_SUPPORTED 64
 886         u16 usr_addr_count;
 887         u16 mc_addr_count;
 888         struct usr_addr usr_addrs[256];
 889
 890         u16 m_cast_flg;
 891         u16 all_multi_pos;
 892         u16 promisc_flg;
 893
 894         /*  Id timer, used to blink NIC to physically identify NIC. */
 895         struct timer_list id_timer;
 896
 897         /*  Restart timer, used to restart NIC if the device is stuck and
 898          *  a schedule task that will set the correct Link state once the
 899          *  NIC's PHY has stabilized after a state change.
 900          */
 901         struct work_struct rst_timer_task;
 902         struct work_struct set_link_task;
 903
 904         /* Flag that can be used to turn on or turn off the Rx checksum
 905          * offload feature.
 906          */
 907         int rx_csum;
 908
 909         /* Below variables are used for fifo selection to transmit a packet */
 910         u16 fifo_selector[MAX_TX_FIFOS];
 911
 912         /* Total fifos for tcp packets */
 913         u8 total_tcp_fifos;
 914
 915         /*
 916         * Beginning index of udp for udp packets
 917         * Value will be equal to
 918         * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
 919         */
 920         u8 udp_fifo_idx;
 921
 922         u8 total_udp_fifos;
 923
 924         /*
 925          * Beginning index of fifo for all other packets
 926          * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
 927         */
 928         u8 other_fifo_idx;
 929
 930         /*  after blink, the adapter must be restored with original
 931          *  values.
 932          */
 933         u64 adapt_ctrl_org;
 934
 935         /* Last known link state. */
 936         u16 last_link_state;
 937 #define LINK_DOWN       1
 938 #define LINK_UP         2
 939
 940         int task_flag;
 941         unsigned long long start_time;
 942         struct vlan_group *vlgrp;
 943 #define MSIX_FLG                0xA5
 944         struct msix_entry *entries;
 945         int msi_detected;
 946         wait_queue_head_t msi_wait;
 947         struct s2io_msix_entry *s2io_entries;
 948         char desc[MAX_REQUESTED_MSI_X][25];
 949
 950         int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
 951
 952         struct msix_info_st msix_info[0x3f];
 953
 954 #define XFRAME_I_DEVICE         1
 955 #define XFRAME_II_DEVICE        2
 956         u8 device_type;
 957
 958 #define MAX_LRO_SESSIONS        32
 959         struct lro lro0_n[MAX_LRO_SESSIONS];
 960         unsigned long   clubbed_frms_cnt;
 961         unsigned long   sending_both;
 962         u8              lro;
 963         u16             lro_max_aggr_per_sess;
 964         volatile unsigned long state;
 965         spinlock_t      rx_lock;
 966         u64             general_int_mask;
 967 #define VPD_STRING_LEN 80
 968         u8  product_name[VPD_STRING_LEN];
 969         u8  serial_num[VPD_STRING_LEN];
 970 };
 971
 972 #define RESET_ERROR 1;
 973 #define CMD_ERROR   2;
 974
 975 /*  OS related system calls */
 976 #ifndef readq
 977 static inline u64 readq(void __iomem *addr)
 978 {
 979         u64 ret = 0;
 980         ret = readl(addr + 4);
 981         ret <<= 32;
 982         ret |= readl(addr);
 983
 984         return ret;
 985 }
 986 #endif
 987
 988 #ifndef writeq
 989 static inline void writeq(u64 val, void __iomem *addr)
 990 {
 991         writel((u32) (val), addr);
 992         writel((u32) (val >> 32), (addr + 4));
 993 }
 994 #endif
 995
 996 /*
 997  * Some registers have to be written in a particular order to
 998  * expect correct hardware operation. The macro SPECIAL_REG_WRITE
 999  * is used to perform such ordered writes. Defines UF (Upper First)
1000  * and LF (Lower First) will be used to specify the required write order.
1001  */
1002 #define UF      1
1003 #define LF      2
1004 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
1005 {
1006         u32 ret;
1007
1008         if (order == LF) {
1009                 writel((u32) (val), addr);
1010                 ret = readl(addr);
1011                 writel((u32) (val >> 32), (addr + 4));
1012                 ret = readl(addr + 4);
1013         } else {
1014                 writel((u32) (val >> 32), (addr + 4));
1015                 ret = readl(addr + 4);
1016                 writel((u32) (val), addr);
1017                 ret = readl(addr);
1018         }
1019 }
1020
1021 /*  Interrupt related values of Xena */
1022
1023 #define ENABLE_INTRS    1
1024 #define DISABLE_INTRS   2
1025
1026 /*  Highest level interrupt blocks */
1027 #define TX_PIC_INTR     (0x0001<<0)
1028 #define TX_DMA_INTR     (0x0001<<1)
1029 #define TX_MAC_INTR     (0x0001<<2)
1030 #define TX_XGXS_INTR    (0x0001<<3)
1031 #define TX_TRAFFIC_INTR (0x0001<<4)
1032 #define RX_PIC_INTR     (0x0001<<5)
1033 #define RX_DMA_INTR     (0x0001<<6)
1034 #define RX_MAC_INTR     (0x0001<<7)
1035 #define RX_XGXS_INTR    (0x0001<<8)
1036 #define RX_TRAFFIC_INTR (0x0001<<9)
1037 #define MC_INTR         (0x0001<<10)
1038 #define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
1039                             TX_DMA_INTR     | \
1040                             TX_MAC_INTR     | \
1041                             TX_XGXS_INTR    | \
1042                             TX_TRAFFIC_INTR | \
1043                             RX_PIC_INTR     | \
1044                             RX_DMA_INTR     | \
1045                             RX_MAC_INTR     | \
1046                             RX_XGXS_INTR    | \
1047                             RX_TRAFFIC_INTR | \
1048                             MC_INTR )
1049
1050 /*  Interrupt masks for the general interrupt mask register */
1051 #define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
1052
1053 #define TXPIC_INT_M         s2BIT(0)
1054 #define TXDMA_INT_M         s2BIT(1)
1055 #define TXMAC_INT_M         s2BIT(2)
1056 #define TXXGXS_INT_M        s2BIT(3)
1057 #define TXTRAFFIC_INT_M     s2BIT(8)
1058 #define PIC_RX_INT_M        s2BIT(32)
1059 #define RXDMA_INT_M         s2BIT(33)
1060 #define RXMAC_INT_M         s2BIT(34)
1061 #define MC_INT_M            s2BIT(35)
1062 #define RXXGXS_INT_M        s2BIT(36)
1063 #define RXTRAFFIC_INT_M     s2BIT(40)
1064
1065 /*  PIC level Interrupts TODO*/
1066
1067 /*  DMA level Inressupts */
1068 #define TXDMA_PFC_INT_M     s2BIT(0)
1069 #define TXDMA_PCC_INT_M     s2BIT(2)
1070
1071 /*  PFC block interrupts */
1072 #define PFC_MISC_ERR_1      s2BIT(0)    /* Interrupt to indicate FIFO full */
1073
1074 /* PCC block interrupts. */
1075 #define PCC_FB_ECC_ERR     vBIT(0xff, 16, 8)    /* Interrupt to indicate
1076                                                    PCC_FB_ECC Error. */
1077
1078 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1079 /*
1080  * Prototype declaration.
1081  */
1082 static int __devinit s2io_init_nic(struct pci_dev *pdev,
1083                                    const struct pci_device_id *pre);
1084 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1085 static int init_shared_mem(struct s2io_nic *sp);
1086 static void free_shared_mem(struct s2io_nic *sp);
1087 static int init_nic(struct s2io_nic *nic);
1088 static void rx_intr_handler(struct ring_info *ring_data);
1089 static void tx_intr_handler(struct fifo_info *fifo_data);
1090 static void s2io_handle_errors(void * dev_id);
1091
1092 static int s2io_starter(void);
1093 static void s2io_closer(void);
1094 static void s2io_tx_watchdog(struct net_device *dev);
1095 static void s2io_tasklet(unsigned long dev_addr);
1096 static void s2io_set_multicast(struct net_device *dev);
1097 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1098 static void s2io_link(struct s2io_nic * sp, int link);
1099 static void s2io_reset(struct s2io_nic * sp);
1100 static int s2io_poll(struct napi_struct *napi, int budget);
1101 static void s2io_init_pci(struct s2io_nic * sp);
1102 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
1103 static void s2io_alarm_handle(unsigned long data);
1104 static irqreturn_t
1105 s2io_msix_ring_handle(int irq, void *dev_id);
1106 static irqreturn_t
1107 s2io_msix_fifo_handle(int irq, void *dev_id);
1108 static irqreturn_t s2io_isr(int irq, void *dev_id);
1109 static int verify_xena_quiescence(struct s2io_nic *sp);
1110 static const struct ethtool_ops netdev_ethtool_ops;
1111 static void s2io_set_link(struct work_struct *work);
1112 static int s2io_set_swapper(struct s2io_nic * sp);
1113 static void s2io_card_down(struct s2io_nic *nic);
1114 static int s2io_card_up(struct s2io_nic *nic);
1115 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1116                                         int bit_state);
1117 static int s2io_add_isr(struct s2io_nic * sp);
1118 static void s2io_rem_isr(struct s2io_nic * sp);
1119
1120 static void restore_xmsi_data(struct s2io_nic *nic);
1121 static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1122 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1123 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1124 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1125 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1126 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
1127
1128 static int
1129 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1130                       struct RxD_t *rxdp, struct s2io_nic *sp);
1131 static void clear_lro_session(struct lro *lro);
1132 static void queue_rx_frame(struct sk_buff *skb);
1133 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1134 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1135                            struct sk_buff *skb, u32 tcp_len);
1136 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1137
1138 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1139                                               pci_channel_state_t state);
1140 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1141 static void s2io_io_resume(struct pci_dev *pdev);
1142
1143 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1144 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1145 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1146
1147 #define S2IO_PARM_INT(X, def_val) \
1148         static unsigned int X = def_val;\
1149                 module_param(X , uint, 0);
1150
1151 #endif                          /* _S2IO_H */