projects / deliverable / linux.git / blob
? search:


6001ab47fba074e8a5ac703f916120e708c5a271
[deliverable/linux.git] / drivers / net / sb1250-mac.c
1 /*
2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 *
19 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
21 */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <asm/processor.h> /* Processor type for cache alignment. */
36 #include <asm/io.h>
37 #include <asm/cache.h>
38
39 /* This is only here until the firmware is ready. In that case,
40 the firmware leaves the ethernet address in the register for us. */
41 #ifdef CONFIG_SIBYTE_STANDALONE
42 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
43 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
44 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
45 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
46 #endif
47
48
49 /* These identify the driver base version and may not be removed. */
50 #if 0
51 static char version1[] __devinitdata =
52 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
53 #endif
54
55
56 /* Operational parameters that usually are not changed. */
57
58 #define CONFIG_SBMAC_COALESCE
59
60 #define MAX_UNITS 4 /* More are supported, limit only on options */
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (2*HZ)
64
65
66 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
67 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
68
69 /* A few user-configurable values which may be modified when a driver
70 module is loaded. */
71
72 /* 1 normal messages, 0 quiet .. 7 verbose. */
73 static int debug = 1;
74 module_param(debug, int, S_IRUGO);
75 MODULE_PARM_DESC(debug, "Debug messages");
76
77 /* mii status msgs */
78 static int noisy_mii = 1;
79 module_param(noisy_mii, int, S_IRUGO);
80 MODULE_PARM_DESC(noisy_mii, "MII status messages");
81
82 /* Used to pass the media type, etc.
83 Both 'options[]' and 'full_duplex[]' should exist for driver
84 interoperability.
85 The media type is usually passed in 'options[]'.
86 */
87 #ifdef MODULE
88 static int options[MAX_UNITS] = {-1, -1, -1, -1};
89 module_param_array(options, int, NULL, S_IRUGO);
90 MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
91
92 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
93 module_param_array(full_duplex, int, NULL, S_IRUGO);
94 MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
95 #endif
96
97 #ifdef CONFIG_SBMAC_COALESCE
98 static int int_pktcnt_tx = 255;
99 module_param(int_pktcnt_tx, int, S_IRUGO);
100 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
101
102 static int int_timeout_tx = 255;
103 module_param(int_timeout_tx, int, S_IRUGO);
104 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
105
106 static int int_pktcnt_rx = 64;
107 module_param(int_pktcnt_rx, int, S_IRUGO);
108 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
109
110 static int int_timeout_rx = 64;
111 module_param(int_timeout_rx, int, S_IRUGO);
112 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
113 #endif
114
115 #include <asm/sibyte/sb1250.h>
116 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
117 #include <asm/sibyte/bcm1480_regs.h>
118 #include <asm/sibyte/bcm1480_int.h>
119 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
120 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
121 #include <asm/sibyte/sb1250_regs.h>
122 #include <asm/sibyte/sb1250_int.h>
123 #else
124 #error invalid SiByte MAC configuation
125 #endif
126 #include <asm/sibyte/sb1250_scd.h>
127 #include <asm/sibyte/sb1250_mac.h>
128 #include <asm/sibyte/sb1250_dma.h>
129
130 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
131 #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
132 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
133 #define UNIT_INT(n) (K_INT_MAC_0 + (n))
134 #else
135 #error invalid SiByte MAC configuation
136 #endif
137
138 /**********************************************************************
139 * Simple types
140 ********************************************************************* */
141
142
143 typedef enum { sbmac_speed_auto, sbmac_speed_10,
144 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
145
146 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
147 sbmac_duplex_full } sbmac_duplex_t;
148
149 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
150 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
151
152 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
153 sbmac_state_broken } sbmac_state_t;
154
155
156 /**********************************************************************
157 * Macros
158 ********************************************************************* */
159
160
161 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
162 (d)->sbdma_dscrtable : (d)->f+1)
163
164
165 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
166
167 #define SBMAC_MAX_TXDESCR 256
168 #define SBMAC_MAX_RXDESCR 256
169
170 #define ETHER_ALIGN 2
171 #define ETHER_ADDR_LEN 6
172 #define ENET_PACKET_SIZE 1518
173 /*#define ENET_PACKET_SIZE 9216 */
174
175 /**********************************************************************
176 * DMA Descriptor structure
177 ********************************************************************* */
178
179 typedef struct sbdmadscr_s {
180 uint64_t dscr_a;
181 uint64_t dscr_b;
182 } sbdmadscr_t;
183
184 typedef unsigned long paddr_t;
185
186 /**********************************************************************
187 * DMA Controller structure
188 ********************************************************************* */
189
190 typedef struct sbmacdma_s {
191
192 /*
193 * This stuff is used to identify the channel and the registers
194 * associated with it.
195 */
196
197 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
198 int sbdma_channel; /* channel number */
199 int sbdma_txdir; /* direction (1=transmit) */
200 int sbdma_maxdescr; /* total # of descriptors in ring */
201 #ifdef CONFIG_SBMAC_COALESCE
202 int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/
203 int sbdma_int_timeout; /* # usec rx/tx interrupt */
204 #endif
205
206 volatile void __iomem *sbdma_config0; /* DMA config register 0 */
207 volatile void __iomem *sbdma_config1; /* DMA config register 1 */
208 volatile void __iomem *sbdma_dscrbase; /* Descriptor base address */
209 volatile void __iomem *sbdma_dscrcnt; /* Descriptor count register */
210 volatile void __iomem *sbdma_curdscr; /* current descriptor address */
211 volatile void __iomem *sbdma_oodpktlost;/* pkt drop (rx only) */
212
213
214 /*
215 * This stuff is for maintenance of the ring
216 */
217
218 sbdmadscr_t *sbdma_dscrtable_unaligned;
219 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */
220 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */
221
222 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */
223
224 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */
225 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */
226 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */
227 } sbmacdma_t;
228
229
230 /**********************************************************************
231 * Ethernet softc structure
232 ********************************************************************* */
233
234 struct sbmac_softc {
235
236 /*
237 * Linux-specific things
238 */
239
240 struct net_device *sbm_dev; /* pointer to linux device */
241 struct napi_struct napi;
242 spinlock_t sbm_lock; /* spin lock */
243 struct timer_list sbm_timer; /* for monitoring MII */
244 int sbm_devflags; /* current device flags */
245
246 int sbm_phy_oldbmsr;
247 int sbm_phy_oldanlpar;
248 int sbm_phy_oldk1stsr;
249 int sbm_phy_oldlinkstat;
250 int sbm_buffersize;
251
252 unsigned char sbm_phys[2];
253
254 /*
255 * Controller-specific things
256 */
257
258 void __iomem *sbm_base; /* MAC's base address */
259 sbmac_state_t sbm_state; /* current state */
260
261 volatile void __iomem *sbm_macenable; /* MAC Enable Register */
262 volatile void __iomem *sbm_maccfg; /* MAC Configuration Register */
263 volatile void __iomem *sbm_fifocfg; /* FIFO configuration register */
264 volatile void __iomem *sbm_framecfg; /* Frame configuration register */
265 volatile void __iomem *sbm_rxfilter; /* receive filter register */
266 volatile void __iomem *sbm_isr; /* Interrupt status register */
267 volatile void __iomem *sbm_imr; /* Interrupt mask register */
268 volatile void __iomem *sbm_mdio; /* MDIO register */
269
270 sbmac_speed_t sbm_speed; /* current speed */
271 sbmac_duplex_t sbm_duplex; /* current duplex */
272 sbmac_fc_t sbm_fc; /* current flow control setting */
273
274 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
275
276 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
277 sbmacdma_t sbm_rxdma;
278 int rx_hw_checksum;
279 int sbe_idx;
280 };
281
282
283 /**********************************************************************
284 * Externs
285 ********************************************************************* */
286
287 /**********************************************************************
288 * Prototypes
289 ********************************************************************* */
290
291 static void sbdma_initctx(sbmacdma_t *d,
292 struct sbmac_softc *s,
293 int chan,
294 int txrx,
295 int maxdescr);
296 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
297 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
298 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
299 static void sbdma_emptyring(sbmacdma_t *d);
300 static void sbdma_fillring(sbmacdma_t *d);
301 static int sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d, int work_to_do, int poll);
302 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d, int poll);
303 static int sbmac_initctx(struct sbmac_softc *s);
304 static void sbmac_channel_start(struct sbmac_softc *s);
305 static void sbmac_channel_stop(struct sbmac_softc *s);
306 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
307 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
308 static uint64_t sbmac_addr2reg(unsigned char *ptr);
309 static irqreturn_t sbmac_intr(int irq,void *dev_instance);
310 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
311 static void sbmac_setmulti(struct sbmac_softc *sc);
312 static int sbmac_init(struct net_device *dev, int idx);
313 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
314 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
315
316 static int sbmac_open(struct net_device *dev);
317 static void sbmac_timer(unsigned long data);
318 static void sbmac_tx_timeout (struct net_device *dev);
319 static void sbmac_set_rx_mode(struct net_device *dev);
320 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
321 static int sbmac_close(struct net_device *dev);
322 static int sbmac_poll(struct napi_struct *napi, int budget);
323
324 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
325 static int sbmac_mii_probe(struct net_device *dev);
326
327 static void sbmac_mii_sync(struct sbmac_softc *s);
328 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
329 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
330 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
331 unsigned int regval);
332
333
334 /**********************************************************************
335 * Globals
336 ********************************************************************* */
337
338 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
339
340
341 /**********************************************************************
342 * MDIO constants
343 ********************************************************************* */
344
345 #define MII_COMMAND_START 0x01
346 #define MII_COMMAND_READ 0x02
347 #define MII_COMMAND_WRITE 0x01
348 #define MII_COMMAND_ACK 0x02
349
350 #define BMCR_RESET 0x8000
351 #define BMCR_LOOPBACK 0x4000
352 #define BMCR_SPEED0 0x2000
353 #define BMCR_ANENABLE 0x1000
354 #define BMCR_POWERDOWN 0x0800
355 #define BMCR_ISOLATE 0x0400
356 #define BMCR_RESTARTAN 0x0200
357 #define BMCR_DUPLEX 0x0100
358 #define BMCR_COLTEST 0x0080
359 #define BMCR_SPEED1 0x0040
360 #define BMCR_SPEED1000 BMCR_SPEED1
361 #define BMCR_SPEED100 BMCR_SPEED0
362 #define BMCR_SPEED10 0
363
364 #define BMSR_100BT4 0x8000
365 #define BMSR_100BT_FDX 0x4000
366 #define BMSR_100BT_HDX 0x2000
367 #define BMSR_10BT_FDX 0x1000
368 #define BMSR_10BT_HDX 0x0800
369 #define BMSR_100BT2_FDX 0x0400
370 #define BMSR_100BT2_HDX 0x0200
371 #define BMSR_1000BT_XSR 0x0100
372 #define BMSR_PRESUP 0x0040
373 #define BMSR_ANCOMPLT 0x0020
374 #define BMSR_REMFAULT 0x0010
375 #define BMSR_AUTONEG 0x0008
376 #define BMSR_LINKSTAT 0x0004
377 #define BMSR_JABDETECT 0x0002
378 #define BMSR_EXTCAPAB 0x0001
379
380 #define PHYIDR1 0x2000
381 #define PHYIDR2 0x5C60
382
383 #define ANAR_NP 0x8000
384 #define ANAR_RF 0x2000
385 #define ANAR_ASYPAUSE 0x0800
386 #define ANAR_PAUSE 0x0400
387 #define ANAR_T4 0x0200
388 #define ANAR_TXFD 0x0100
389 #define ANAR_TXHD 0x0080
390 #define ANAR_10FD 0x0040
391 #define ANAR_10HD 0x0020
392 #define ANAR_PSB 0x0001
393
394 #define ANLPAR_NP 0x8000
395 #define ANLPAR_ACK 0x4000
396 #define ANLPAR_RF 0x2000
397 #define ANLPAR_ASYPAUSE 0x0800
398 #define ANLPAR_PAUSE 0x0400
399 #define ANLPAR_T4 0x0200
400 #define ANLPAR_TXFD 0x0100
401 #define ANLPAR_TXHD 0x0080
402 #define ANLPAR_10FD 0x0040
403 #define ANLPAR_10HD 0x0020
404 #define ANLPAR_PSB 0x0001 /* 802.3 */
405
406 #define ANER_PDF 0x0010
407 #define ANER_LPNPABLE 0x0008
408 #define ANER_NPABLE 0x0004
409 #define ANER_PAGERX 0x0002
410 #define ANER_LPANABLE 0x0001
411
412 #define ANNPTR_NP 0x8000
413 #define ANNPTR_MP 0x2000
414 #define ANNPTR_ACK2 0x1000
415 #define ANNPTR_TOGTX 0x0800
416 #define ANNPTR_CODE 0x0008
417
418 #define ANNPRR_NP 0x8000
419 #define ANNPRR_MP 0x2000
420 #define ANNPRR_ACK3 0x1000
421 #define ANNPRR_TOGTX 0x0800
422 #define ANNPRR_CODE 0x0008
423
424 #define K1TCR_TESTMODE 0x0000
425 #define K1TCR_MSMCE 0x1000
426 #define K1TCR_MSCV 0x0800
427 #define K1TCR_RPTR 0x0400
428 #define K1TCR_1000BT_FDX 0x200
429 #define K1TCR_1000BT_HDX 0x100
430
431 #define K1STSR_MSMCFLT 0x8000
432 #define K1STSR_MSCFGRES 0x4000
433 #define K1STSR_LRSTAT 0x2000
434 #define K1STSR_RRSTAT 0x1000
435 #define K1STSR_LP1KFD 0x0800
436 #define K1STSR_LP1KHD 0x0400
437 #define K1STSR_LPASMDIR 0x0200
438
439 #define K1SCR_1KX_FDX 0x8000
440 #define K1SCR_1KX_HDX 0x4000
441 #define K1SCR_1KT_FDX 0x2000
442 #define K1SCR_1KT_HDX 0x1000
443
444 #define STRAP_PHY1 0x0800
445 #define STRAP_NCMODE 0x0400
446 #define STRAP_MANMSCFG 0x0200
447 #define STRAP_ANENABLE 0x0100
448 #define STRAP_MSVAL 0x0080
449 #define STRAP_1KHDXADV 0x0010
450 #define STRAP_1KFDXADV 0x0008
451 #define STRAP_100ADV 0x0004
452 #define STRAP_SPEEDSEL 0x0000
453 #define STRAP_SPEED100 0x0001
454
455 #define PHYSUP_SPEED1000 0x10
456 #define PHYSUP_SPEED100 0x08
457 #define PHYSUP_SPEED10 0x00
458 #define PHYSUP_LINKUP 0x04
459 #define PHYSUP_FDX 0x02
460
461 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
462 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
463 #define MII_PHYIDR1 0x02
464 #define MII_PHYIDR2 0x03
465
466 #define MII_K1STSR 0x0A /* 1K Status Register (ro) */
467 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
468
469
470 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
471
472 #define ENABLE 1
473 #define DISABLE 0
474
475 /**********************************************************************
476 * SBMAC_MII_SYNC(s)
477 *
478 * Synchronize with the MII - send a pattern of bits to the MII
479 * that will guarantee that it is ready to accept a command.
480 *
481 * Input parameters:
482 * s - sbmac structure
483 *
484 * Return value:
485 * nothing
486 ********************************************************************* */
487
488 static void sbmac_mii_sync(struct sbmac_softc *s)
489 {
490 int cnt;
491 uint64_t bits;
492 int mac_mdio_genc;
493
494 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
495
496 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
497
498 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
499
500 for (cnt = 0; cnt < 32; cnt++) {
501 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
502 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
503 }
504 }
505
506 /**********************************************************************
507 * SBMAC_MII_SENDDATA(s,data,bitcnt)
508 *
509 * Send some bits to the MII. The bits to be sent are right-
510 * justified in the 'data' parameter.
511 *
512 * Input parameters:
513 * s - sbmac structure
514 * data - data to send
515 * bitcnt - number of bits to send
516 ********************************************************************* */
517
518 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
519 {
520 int i;
521 uint64_t bits;
522 unsigned int curmask;
523 int mac_mdio_genc;
524
525 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
526
527 bits = M_MAC_MDIO_DIR_OUTPUT;
528 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
529
530 curmask = 1 << (bitcnt - 1);
531
532 for (i = 0; i < bitcnt; i++) {
533 if (data & curmask)
534 bits |= M_MAC_MDIO_OUT;
535 else bits &= ~M_MAC_MDIO_OUT;
536 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
537 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
538 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
539 curmask >>= 1;
540 }
541 }
542
543
544
545 /**********************************************************************
546 * SBMAC_MII_READ(s,phyaddr,regidx)
547 *
548 * Read a PHY register.
549 *
550 * Input parameters:
551 * s - sbmac structure
552 * phyaddr - PHY's address
553 * regidx = index of register to read
554 *
555 * Return value:
556 * value read, or 0 if an error occurred.
557 ********************************************************************* */
558
559 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
560 {
561 int idx;
562 int error;
563 int regval;
564 int mac_mdio_genc;
565
566 /*
567 * Synchronize ourselves so that the PHY knows the next
568 * thing coming down is a command
569 */
570
571 sbmac_mii_sync(s);
572
573 /*
574 * Send the data to the PHY. The sequence is
575 * a "start" command (2 bits)
576 * a "read" command (2 bits)
577 * the PHY addr (5 bits)
578 * the register index (5 bits)
579 */
580
581 sbmac_mii_senddata(s,MII_COMMAND_START, 2);
582 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
583 sbmac_mii_senddata(s,phyaddr, 5);
584 sbmac_mii_senddata(s,regidx, 5);
585
586 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
587
588 /*
589 * Switch the port around without a clock transition.
590 */
591 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
592
593 /*
594 * Send out a clock pulse to signal we want the status
595 */
596
597 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
598 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
599
600 /*
601 * If an error occurred, the PHY will signal '1' back
602 */
603 error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
604
605 /*
606 * Issue an 'idle' clock pulse, but keep the direction
607 * the same.
608 */
609 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
610 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
611
612 regval = 0;
613
614 for (idx = 0; idx < 16; idx++) {
615 regval <<= 1;
616
617 if (error == 0) {
618 if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
619 regval |= 1;
620 }
621
622 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
623 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
624 }
625
626 /* Switch back to output */
627 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
628
629 if (error == 0)
630 return regval;
631 return 0;
632 }
633
634
635 /**********************************************************************
636 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
637 *
638 * Write a value to a PHY register.
639 *
640 * Input parameters:
641 * s - sbmac structure
642 * phyaddr - PHY to use
643 * regidx - register within the PHY
644 * regval - data to write to register
645 *
646 * Return value:
647 * nothing
648 ********************************************************************* */
649
650 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
651 unsigned int regval)
652 {
653 int mac_mdio_genc;
654
655 sbmac_mii_sync(s);
656
657 sbmac_mii_senddata(s,MII_COMMAND_START,2);
658 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
659 sbmac_mii_senddata(s,phyaddr, 5);
660 sbmac_mii_senddata(s,regidx, 5);
661 sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
662 sbmac_mii_senddata(s,regval,16);
663
664 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
665
666 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
667 }
668
669
670
671 /**********************************************************************
672 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
673 *
674 * Initialize a DMA channel context. Since there are potentially
675 * eight DMA channels per MAC, it's nice to do this in a standard
676 * way.
677 *
678 * Input parameters:
679 * d - sbmacdma_t structure (DMA channel context)
680 * s - sbmac_softc structure (pointer to a MAC)
681 * chan - channel number (0..1 right now)
682 * txrx - Identifies DMA_TX or DMA_RX for channel direction
683 * maxdescr - number of descriptors
684 *
685 * Return value:
686 * nothing
687 ********************************************************************* */
688
689 static void sbdma_initctx(sbmacdma_t *d,
690 struct sbmac_softc *s,
691 int chan,
692 int txrx,
693 int maxdescr)
694 {
695 #ifdef CONFIG_SBMAC_COALESCE
696 int int_pktcnt, int_timeout;
697 #endif
698
699 /*
700 * Save away interesting stuff in the structure
701 */
702
703 d->sbdma_eth = s;
704 d->sbdma_channel = chan;
705 d->sbdma_txdir = txrx;
706
707 #if 0
708 /* RMON clearing */
709 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
710 #endif
711
712 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
713 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
714 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
715 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
716 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
717 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
718 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
719 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
720 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
721 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
722 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
723 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
724 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
725 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
726 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
727 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
728 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
729 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
730 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
731 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
732 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
733
734 /*
735 * initialize register pointers
736 */
737
738 d->sbdma_config0 =
739 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
740 d->sbdma_config1 =
741 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
742 d->sbdma_dscrbase =
743 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
744 d->sbdma_dscrcnt =
745 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
746 d->sbdma_curdscr =
747 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
748 if (d->sbdma_txdir)
749 d->sbdma_oodpktlost = NULL;
750 else
751 d->sbdma_oodpktlost =
752 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
753
754 /*
755 * Allocate memory for the ring
756 */
757
758 d->sbdma_maxdescr = maxdescr;
759
760 d->sbdma_dscrtable_unaligned =
761 d->sbdma_dscrtable = (sbdmadscr_t *)
762 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
763
764 /*
765 * The descriptor table must be aligned to at least 16 bytes or the
766 * MAC will corrupt it.
767 */
768 d->sbdma_dscrtable = (sbdmadscr_t *)
769 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
770
771 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
772
773 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
774
775 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
776
777 /*
778 * And context table
779 */
780
781 d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
782 sizeof(struct sk_buff *), GFP_KERNEL);
783
784 #ifdef CONFIG_SBMAC_COALESCE
785 /*
786 * Setup Rx/Tx DMA coalescing defaults
787 */
788
789 int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
790 if ( int_pktcnt ) {
791 d->sbdma_int_pktcnt = int_pktcnt;
792 } else {
793 d->sbdma_int_pktcnt = 1;
794 }
795
796 int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
797 if ( int_timeout ) {
798 d->sbdma_int_timeout = int_timeout;
799 } else {
800 d->sbdma_int_timeout = 0;
801 }
802 #endif
803
804 }
805
806 /**********************************************************************
807 * SBDMA_CHANNEL_START(d)
808 *
809 * Initialize the hardware registers for a DMA channel.
810 *
811 * Input parameters:
812 * d - DMA channel to init (context must be previously init'd
813 * rxtx - DMA_RX or DMA_TX depending on what type of channel
814 *
815 * Return value:
816 * nothing
817 ********************************************************************* */
818
819 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
820 {
821 /*
822 * Turn on the DMA channel
823 */
824
825 #ifdef CONFIG_SBMAC_COALESCE
826 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
827 0, d->sbdma_config1);
828 __raw_writeq(M_DMA_EOP_INT_EN |
829 V_DMA_RINGSZ(d->sbdma_maxdescr) |
830 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
831 0, d->sbdma_config0);
832 #else
833 __raw_writeq(0, d->sbdma_config1);
834 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
835 0, d->sbdma_config0);
836 #endif
837
838 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
839
840 /*
841 * Initialize ring pointers
842 */
843
844 d->sbdma_addptr = d->sbdma_dscrtable;
845 d->sbdma_remptr = d->sbdma_dscrtable;
846 }
847
848 /**********************************************************************
849 * SBDMA_CHANNEL_STOP(d)
850 *
851 * Initialize the hardware registers for a DMA channel.
852 *
853 * Input parameters:
854 * d - DMA channel to init (context must be previously init'd
855 *
856 * Return value:
857 * nothing
858 ********************************************************************* */
859
860 static void sbdma_channel_stop(sbmacdma_t *d)
861 {
862 /*
863 * Turn off the DMA channel
864 */
865
866 __raw_writeq(0, d->sbdma_config1);
867
868 __raw_writeq(0, d->sbdma_dscrbase);
869
870 __raw_writeq(0, d->sbdma_config0);
871
872 /*
873 * Zero ring pointers
874 */
875
876 d->sbdma_addptr = NULL;
877 d->sbdma_remptr = NULL;
878 }
879
880 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
881 {
882 unsigned long addr;
883 unsigned long newaddr;
884
885 addr = (unsigned long) skb->data;
886
887 newaddr = (addr + power2 - 1) & ~(power2 - 1);
888
889 skb_reserve(skb,newaddr-addr+offset);
890 }
891
892
893 /**********************************************************************
894 * SBDMA_ADD_RCVBUFFER(d,sb)
895 *
896 * Add a buffer to the specified DMA channel. For receive channels,
897 * this queues a buffer for inbound packets.
898 *
899 * Input parameters:
900 * d - DMA channel descriptor
901 * sb - sk_buff to add, or NULL if we should allocate one
902 *
903 * Return value:
904 * 0 if buffer could not be added (ring is full)
905 * 1 if buffer added successfully
906 ********************************************************************* */
907
908
909 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
910 {
911 sbdmadscr_t *dsc;
912 sbdmadscr_t *nextdsc;
913 struct sk_buff *sb_new = NULL;
914 int pktsize = ENET_PACKET_SIZE;
915
916 /* get pointer to our current place in the ring */
917
918 dsc = d->sbdma_addptr;
919 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
920
921 /*
922 * figure out if the ring is full - if the next descriptor
923 * is the same as the one that we're going to remove from
924 * the ring, the ring is full
925 */
926
927 if (nextdsc == d->sbdma_remptr) {
928 return -ENOSPC;
929 }
930
931 /*
932 * Allocate a sk_buff if we don't already have one.
933 * If we do have an sk_buff, reset it so that it's empty.
934 *
935 * Note: sk_buffs don't seem to be guaranteed to have any sort
936 * of alignment when they are allocated. Therefore, allocate enough
937 * extra space to make sure that:
938 *
939 * 1. the data does not start in the middle of a cache line.
940 * 2. The data does not end in the middle of a cache line
941 * 3. The buffer can be aligned such that the IP addresses are
942 * naturally aligned.
943 *
944 * Remember, the SOCs MAC writes whole cache lines at a time,
945 * without reading the old contents first. So, if the sk_buff's
946 * data portion starts in the middle of a cache line, the SOC
947 * DMA will trash the beginning (and ending) portions.
948 */
949
950 if (sb == NULL) {
951 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
952 if (sb_new == NULL) {
953 printk(KERN_INFO "%s: sk_buff allocation failed\n",
954 d->sbdma_eth->sbm_dev->name);
955 return -ENOBUFS;
956 }
957
958 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
959 }
960 else {
961 sb_new = sb;
962 /*
963 * nothing special to reinit buffer, it's already aligned
964 * and sb->data already points to a good place.
965 */
966 }
967
968 /*
969 * fill in the descriptor
970 */
971
972 #ifdef CONFIG_SBMAC_COALESCE
973 /*
974 * Do not interrupt per DMA transfer.
975 */
976 dsc->dscr_a = virt_to_phys(sb_new->data) |
977 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
978 #else
979 dsc->dscr_a = virt_to_phys(sb_new->data) |
980 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
981 M_DMA_DSCRA_INTERRUPT;
982 #endif
983
984 /* receiving: no options */
985 dsc->dscr_b = 0;
986
987 /*
988 * fill in the context
989 */
990
991 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
992
993 /*
994 * point at next packet
995 */
996
997 d->sbdma_addptr = nextdsc;
998
999 /*
1000 * Give the buffer to the DMA engine.
1001 */
1002
1003 __raw_writeq(1, d->sbdma_dscrcnt);
1004
1005 return 0; /* we did it */
1006 }
1007
1008 /**********************************************************************
1009 * SBDMA_ADD_TXBUFFER(d,sb)
1010 *
1011 * Add a transmit buffer to the specified DMA channel, causing a
1012 * transmit to start.
1013 *
1014 * Input parameters:
1015 * d - DMA channel descriptor
1016 * sb - sk_buff to add
1017 *
1018 * Return value:
1019 * 0 transmit queued successfully
1020 * otherwise error code
1021 ********************************************************************* */
1022
1023
1024 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1025 {
1026 sbdmadscr_t *dsc;
1027 sbdmadscr_t *nextdsc;
1028 uint64_t phys;
1029 uint64_t ncb;
1030 int length;
1031
1032 /* get pointer to our current place in the ring */
1033
1034 dsc = d->sbdma_addptr;
1035 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1036
1037 /*
1038 * figure out if the ring is full - if the next descriptor
1039 * is the same as the one that we're going to remove from
1040 * the ring, the ring is full
1041 */
1042
1043 if (nextdsc == d->sbdma_remptr) {
1044 return -ENOSPC;
1045 }
1046
1047 /*
1048 * Under Linux, it's not necessary to copy/coalesce buffers
1049 * like it is on NetBSD. We think they're all contiguous,
1050 * but that may not be true for GBE.
1051 */
1052
1053 length = sb->len;
1054
1055 /*
1056 * fill in the descriptor. Note that the number of cache
1057 * blocks in the descriptor is the number of blocks
1058 * *spanned*, so we need to add in the offset (if any)
1059 * while doing the calculation.
1060 */
1061
1062 phys = virt_to_phys(sb->data);
1063 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1064
1065 dsc->dscr_a = phys |
1066 V_DMA_DSCRA_A_SIZE(ncb) |
1067 #ifndef CONFIG_SBMAC_COALESCE
1068 M_DMA_DSCRA_INTERRUPT |
1069 #endif
1070 M_DMA_ETHTX_SOP;
1071
1072 /* transmitting: set outbound options and length */
1073
1074 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1075 V_DMA_DSCRB_PKT_SIZE(length);
1076
1077 /*
1078 * fill in the context
1079 */
1080
1081 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1082
1083 /*
1084 * point at next packet
1085 */
1086
1087 d->sbdma_addptr = nextdsc;
1088
1089 /*
1090 * Give the buffer to the DMA engine.
1091 */
1092
1093 __raw_writeq(1, d->sbdma_dscrcnt);
1094
1095 return 0; /* we did it */
1096 }
1097
1098
1099
1100
1101 /**********************************************************************
1102 * SBDMA_EMPTYRING(d)
1103 *
1104 * Free all allocated sk_buffs on the specified DMA channel;
1105 *
1106 * Input parameters:
1107 * d - DMA channel
1108 *
1109 * Return value:
1110 * nothing
1111 ********************************************************************* */
1112
1113 static void sbdma_emptyring(sbmacdma_t *d)
1114 {
1115 int idx;
1116 struct sk_buff *sb;
1117
1118 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1119 sb = d->sbdma_ctxtable[idx];
1120 if (sb) {
1121 dev_kfree_skb(sb);
1122 d->sbdma_ctxtable[idx] = NULL;
1123 }
1124 }
1125 }
1126
1127
1128 /**********************************************************************
1129 * SBDMA_FILLRING(d)
1130 *
1131 * Fill the specified DMA channel (must be receive channel)
1132 * with sk_buffs
1133 *
1134 * Input parameters:
1135 * d - DMA channel
1136 *
1137 * Return value:
1138 * nothing
1139 ********************************************************************* */
1140
1141 static void sbdma_fillring(sbmacdma_t *d)
1142 {
1143 int idx;
1144
1145 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1146 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1147 break;
1148 }
1149 }
1150
1151 #ifdef CONFIG_NET_POLL_CONTROLLER
1152 static void sbmac_netpoll(struct net_device *netdev)
1153 {
1154 struct sbmac_softc *sc = netdev_priv(netdev);
1155 int irq = sc->sbm_dev->irq;
1156
1157 __raw_writeq(0, sc->sbm_imr);
1158
1159 sbmac_intr(irq, netdev);
1160
1161 #ifdef CONFIG_SBMAC_COALESCE
1162 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1163 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1164 sc->sbm_imr);
1165 #else
1166 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1167 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1168 #endif
1169 }
1170 #endif
1171
1172 /**********************************************************************
1173 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1174 *
1175 * Process "completed" receive buffers on the specified DMA channel.
1176 *
1177 * Input parameters:
1178 * sc - softc structure
1179 * d - DMA channel context
1180 * work_to_do - no. of packets to process before enabling interrupt
1181 * again (for NAPI)
1182 * poll - 1: using polling (for NAPI)
1183 *
1184 * Return value:
1185 * nothing
1186 ********************************************************************* */
1187
1188 static int sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d,
1189 int work_to_do, int poll)
1190 {
1191 struct net_device *dev = sc->sbm_dev;
1192 int curidx;
1193 int hwidx;
1194 sbdmadscr_t *dsc;
1195 struct sk_buff *sb;
1196 int len;
1197 int work_done = 0;
1198 int dropped = 0;
1199
1200 prefetch(d);
1201
1202 again:
1203 /* Check if the HW dropped any frames */
1204 dev->stats.rx_fifo_errors
1205 += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1206 __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1207
1208 while (work_to_do-- > 0) {
1209 /*
1210 * figure out where we are (as an index) and where
1211 * the hardware is (also as an index)
1212 *
1213 * This could be done faster if (for example) the
1214 * descriptor table was page-aligned and contiguous in
1215 * both virtual and physical memory -- you could then
1216 * just compare the low-order bits of the virtual address
1217 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1218 */
1219
1220 dsc = d->sbdma_remptr;
1221 curidx = dsc - d->sbdma_dscrtable;
1222
1223 prefetch(dsc);
1224 prefetch(&d->sbdma_ctxtable[curidx]);
1225
1226 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1227 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1228
1229 /*
1230 * If they're the same, that means we've processed all
1231 * of the descriptors up to (but not including) the one that
1232 * the hardware is working on right now.
1233 */
1234
1235 if (curidx == hwidx)
1236 goto done;
1237
1238 /*
1239 * Otherwise, get the packet's sk_buff ptr back
1240 */
1241
1242 sb = d->sbdma_ctxtable[curidx];
1243 d->sbdma_ctxtable[curidx] = NULL;
1244
1245 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1246
1247 /*
1248 * Check packet status. If good, process it.
1249 * If not, silently drop it and put it back on the
1250 * receive ring.
1251 */
1252
1253 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1254
1255 /*
1256 * Add a new buffer to replace the old one. If we fail
1257 * to allocate a buffer, we're going to drop this
1258 * packet and put it right back on the receive ring.
1259 */
1260
1261 if (unlikely (sbdma_add_rcvbuffer(d,NULL) ==
1262 -ENOBUFS)) {
1263 dev->stats.rx_dropped++;
1264 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1265 /* No point in continuing at the moment */
1266 printk(KERN_ERR "dropped packet (1)\n");
1267 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1268 goto done;
1269 } else {
1270 /*
1271 * Set length into the packet
1272 */
1273 skb_put(sb,len);
1274
1275 /*
1276 * Buffer has been replaced on the
1277 * receive ring. Pass the buffer to
1278 * the kernel
1279 */
1280 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1281 /* Check hw IPv4/TCP checksum if supported */
1282 if (sc->rx_hw_checksum == ENABLE) {
1283 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1284 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1285 sb->ip_summed = CHECKSUM_UNNECESSARY;
1286 /* don't need to set sb->csum */
1287 } else {
1288 sb->ip_summed = CHECKSUM_NONE;
1289 }
1290 }
1291 prefetch(sb->data);
1292 prefetch((const void *)(((char *)sb->data)+32));
1293 if (poll)
1294 dropped = netif_receive_skb(sb);
1295 else
1296 dropped = netif_rx(sb);
1297
1298 if (dropped == NET_RX_DROP) {
1299 dev->stats.rx_dropped++;
1300 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1301 goto done;
1302 }
1303 else {
1304 dev->stats.rx_bytes += len;
1305 dev->stats.rx_packets++;
1306 }
1307 }
1308 } else {
1309 /*
1310 * Packet was mangled somehow. Just drop it and
1311 * put it back on the receive ring.
1312 */
1313 dev->stats.rx_errors++;
1314 sbdma_add_rcvbuffer(d,sb);
1315 }
1316
1317
1318 /*
1319 * .. and advance to the next buffer.
1320 */
1321
1322 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1323 work_done++;
1324 }
1325 if (!poll) {
1326 work_to_do = 32;
1327 goto again; /* collect fifo drop statistics again */
1328 }
1329 done:
1330 return work_done;
1331 }
1332
1333 /**********************************************************************
1334 * SBDMA_TX_PROCESS(sc,d)
1335 *
1336 * Process "completed" transmit buffers on the specified DMA channel.
1337 * This is normally called within the interrupt service routine.
1338 * Note that this isn't really ideal for priority channels, since
1339 * it processes all of the packets on a given channel before
1340 * returning.
1341 *
1342 * Input parameters:
1343 * sc - softc structure
1344 * d - DMA channel context
1345 * poll - 1: using polling (for NAPI)
1346 *
1347 * Return value:
1348 * nothing
1349 ********************************************************************* */
1350
1351 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d, int poll)
1352 {
1353 struct net_device *dev = sc->sbm_dev;
1354 int curidx;
1355 int hwidx;
1356 sbdmadscr_t *dsc;
1357 struct sk_buff *sb;
1358 unsigned long flags;
1359 int packets_handled = 0;
1360
1361 spin_lock_irqsave(&(sc->sbm_lock), flags);
1362
1363 if (d->sbdma_remptr == d->sbdma_addptr)
1364 goto end_unlock;
1365
1366 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1367 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1368
1369 for (;;) {
1370 /*
1371 * figure out where we are (as an index) and where
1372 * the hardware is (also as an index)
1373 *
1374 * This could be done faster if (for example) the
1375 * descriptor table was page-aligned and contiguous in
1376 * both virtual and physical memory -- you could then
1377 * just compare the low-order bits of the virtual address
1378 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1379 */
1380
1381 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1382
1383 /*
1384 * If they're the same, that means we've processed all
1385 * of the descriptors up to (but not including) the one that
1386 * the hardware is working on right now.
1387 */
1388
1389 if (curidx == hwidx)
1390 break;
1391
1392 /*
1393 * Otherwise, get the packet's sk_buff ptr back
1394 */
1395
1396 dsc = &(d->sbdma_dscrtable[curidx]);
1397 sb = d->sbdma_ctxtable[curidx];
1398 d->sbdma_ctxtable[curidx] = NULL;
1399
1400 /*
1401 * Stats
1402 */
1403
1404 dev->stats.tx_bytes += sb->len;
1405 dev->stats.tx_packets++;
1406
1407 /*
1408 * for transmits, we just free buffers.
1409 */
1410
1411 dev_kfree_skb_irq(sb);
1412
1413 /*
1414 * .. and advance to the next buffer.
1415 */
1416
1417 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1418
1419 packets_handled++;
1420
1421 }
1422
1423 /*
1424 * Decide if we should wake up the protocol or not.
1425 * Other drivers seem to do this when we reach a low
1426 * watermark on the transmit queue.
1427 */
1428
1429 if (packets_handled)
1430 netif_wake_queue(d->sbdma_eth->sbm_dev);
1431
1432 end_unlock:
1433 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1434
1435 }
1436
1437
1438
1439 /**********************************************************************
1440 * SBMAC_INITCTX(s)
1441 *
1442 * Initialize an Ethernet context structure - this is called
1443 * once per MAC on the 1250. Memory is allocated here, so don't
1444 * call it again from inside the ioctl routines that bring the
1445 * interface up/down
1446 *
1447 * Input parameters:
1448 * s - sbmac context structure
1449 *
1450 * Return value:
1451 * 0
1452 ********************************************************************* */
1453
1454 static int sbmac_initctx(struct sbmac_softc *s)
1455 {
1456
1457 /*
1458 * figure out the addresses of some ports
1459 */
1460
1461 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1462 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1463 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1464 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1465 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1466 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1467 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1468 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1469
1470 s->sbm_phys[0] = 1;
1471 s->sbm_phys[1] = 0;
1472
1473 s->sbm_phy_oldbmsr = 0;
1474 s->sbm_phy_oldanlpar = 0;
1475 s->sbm_phy_oldk1stsr = 0;
1476 s->sbm_phy_oldlinkstat = 0;
1477
1478 /*
1479 * Initialize the DMA channels. Right now, only one per MAC is used
1480 * Note: Only do this _once_, as it allocates memory from the kernel!
1481 */
1482
1483 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1484 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1485
1486 /*
1487 * initial state is OFF
1488 */
1489
1490 s->sbm_state = sbmac_state_off;
1491
1492 /*
1493 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1494 */
1495
1496 s->sbm_speed = sbmac_speed_10;
1497 s->sbm_duplex = sbmac_duplex_half;
1498 s->sbm_fc = sbmac_fc_disabled;
1499
1500 return 0;
1501 }
1502
1503
1504 static void sbdma_uninitctx(struct sbmacdma_s *d)
1505 {
1506 if (d->sbdma_dscrtable_unaligned) {
1507 kfree(d->sbdma_dscrtable_unaligned);
1508 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1509 }
1510
1511 if (d->sbdma_ctxtable) {
1512 kfree(d->sbdma_ctxtable);
1513 d->sbdma_ctxtable = NULL;
1514 }
1515 }
1516
1517
1518 static void sbmac_uninitctx(struct sbmac_softc *sc)
1519 {
1520 sbdma_uninitctx(&(sc->sbm_txdma));
1521 sbdma_uninitctx(&(sc->sbm_rxdma));
1522 }
1523
1524
1525 /**********************************************************************
1526 * SBMAC_CHANNEL_START(s)
1527 *
1528 * Start packet processing on this MAC.
1529 *
1530 * Input parameters:
1531 * s - sbmac structure
1532 *
1533 * Return value:
1534 * nothing
1535 ********************************************************************* */
1536
1537 static void sbmac_channel_start(struct sbmac_softc *s)
1538 {
1539 uint64_t reg;
1540 volatile void __iomem *port;
1541 uint64_t cfg,fifo,framecfg;
1542 int idx, th_value;
1543
1544 /*
1545 * Don't do this if running
1546 */
1547
1548 if (s->sbm_state == sbmac_state_on)
1549 return;
1550
1551 /*
1552 * Bring the controller out of reset, but leave it off.
1553 */
1554
1555 __raw_writeq(0, s->sbm_macenable);
1556
1557 /*
1558 * Ignore all received packets
1559 */
1560
1561 __raw_writeq(0, s->sbm_rxfilter);
1562
1563 /*
1564 * Calculate values for various control registers.
1565 */
1566
1567 cfg = M_MAC_RETRY_EN |
1568 M_MAC_TX_HOLD_SOP_EN |
1569 V_MAC_TX_PAUSE_CNT_16K |
1570 M_MAC_AP_STAT_EN |
1571 M_MAC_FAST_SYNC |
1572 M_MAC_SS_EN |
1573 0;
1574
1575 /*
1576 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1577 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1578 * Use a larger RD_THRSH for gigabit
1579 */
1580 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1581 th_value = 28;
1582 else
1583 th_value = 64;
1584
1585 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1586 ((s->sbm_speed == sbmac_speed_1000)
1587 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1588 V_MAC_TX_RL_THRSH(4) |
1589 V_MAC_RX_PL_THRSH(4) |
1590 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1591 V_MAC_RX_PL_THRSH(4) |
1592 V_MAC_RX_RL_THRSH(8) |
1593 0;
1594
1595 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1596 V_MAC_MAX_FRAMESZ_DEFAULT |
1597 V_MAC_BACKOFF_SEL(1);
1598
1599 /*
1600 * Clear out the hash address map
1601 */
1602
1603 port = s->sbm_base + R_MAC_HASH_BASE;
1604 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1605 __raw_writeq(0, port);
1606 port += sizeof(uint64_t);
1607 }
1608
1609 /*
1610 * Clear out the exact-match table
1611 */
1612
1613 port = s->sbm_base + R_MAC_ADDR_BASE;
1614 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1615 __raw_writeq(0, port);
1616 port += sizeof(uint64_t);
1617 }
1618
1619 /*
1620 * Clear out the DMA Channel mapping table registers
1621 */
1622
1623 port = s->sbm_base + R_MAC_CHUP0_BASE;
1624 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1625 __raw_writeq(0, port);
1626 port += sizeof(uint64_t);
1627 }
1628
1629
1630 port = s->sbm_base + R_MAC_CHLO0_BASE;
1631 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1632 __raw_writeq(0, port);
1633 port += sizeof(uint64_t);
1634 }
1635
1636 /*
1637 * Program the hardware address. It goes into the hardware-address
1638 * register as well as the first filter register.
1639 */
1640
1641 reg = sbmac_addr2reg(s->sbm_hwaddr);
1642
1643 port = s->sbm_base + R_MAC_ADDR_BASE;
1644 __raw_writeq(reg, port);
1645 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1646
1647 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1648 /*
1649 * Pass1 SOCs do not receive packets addressed to the
1650 * destination address in the R_MAC_ETHERNET_ADDR register.
1651 * Set the value to zero.
1652 */
1653 __raw_writeq(0, port);
1654 #else
1655 __raw_writeq(reg, port);
1656 #endif
1657
1658 /*
1659 * Set the receive filter for no packets, and write values
1660 * to the various config registers
1661 */
1662
1663 __raw_writeq(0, s->sbm_rxfilter);
1664 __raw_writeq(0, s->sbm_imr);
1665 __raw_writeq(framecfg, s->sbm_framecfg);
1666 __raw_writeq(fifo, s->sbm_fifocfg);
1667 __raw_writeq(cfg, s->sbm_maccfg);
1668
1669 /*
1670 * Initialize DMA channels (rings should be ok now)
1671 */
1672
1673 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1674 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1675
1676 /*
1677 * Configure the speed, duplex, and flow control
1678 */
1679
1680 sbmac_set_speed(s,s->sbm_speed);
1681 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1682
1683 /*
1684 * Fill the receive ring
1685 */
1686
1687 sbdma_fillring(&(s->sbm_rxdma));
1688
1689 /*
1690 * Turn on the rest of the bits in the enable register
1691 */
1692
1693 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1694 __raw_writeq(M_MAC_RXDMA_EN0 |
1695 M_MAC_TXDMA_EN0, s->sbm_macenable);
1696 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1697 __raw_writeq(M_MAC_RXDMA_EN0 |
1698 M_MAC_TXDMA_EN0 |
1699 M_MAC_RX_ENABLE |
1700 M_MAC_TX_ENABLE, s->sbm_macenable);
1701 #else
1702 #error invalid SiByte MAC configuation
1703 #endif
1704
1705 #ifdef CONFIG_SBMAC_COALESCE
1706 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1707 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1708 #else
1709 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1710 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1711 #endif
1712
1713 /*
1714 * Enable receiving unicasts and broadcasts
1715 */
1716
1717 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1718
1719 /*
1720 * we're running now.
1721 */
1722
1723 s->sbm_state = sbmac_state_on;
1724
1725 /*
1726 * Program multicast addresses
1727 */
1728
1729 sbmac_setmulti(s);
1730
1731 /*
1732 * If channel was in promiscuous mode before, turn that on
1733 */
1734
1735 if (s->sbm_devflags & IFF_PROMISC) {
1736 sbmac_promiscuous_mode(s,1);
1737 }
1738
1739 }
1740
1741
1742 /**********************************************************************
1743 * SBMAC_CHANNEL_STOP(s)
1744 *
1745 * Stop packet processing on this MAC.
1746 *
1747 * Input parameters:
1748 * s - sbmac structure
1749 *
1750 * Return value:
1751 * nothing
1752 ********************************************************************* */
1753
1754 static void sbmac_channel_stop(struct sbmac_softc *s)
1755 {
1756 /* don't do this if already stopped */
1757
1758 if (s->sbm_state == sbmac_state_off)
1759 return;
1760
1761 /* don't accept any packets, disable all interrupts */
1762
1763 __raw_writeq(0, s->sbm_rxfilter);
1764 __raw_writeq(0, s->sbm_imr);
1765
1766 /* Turn off ticker */
1767
1768 /* XXX */
1769
1770 /* turn off receiver and transmitter */
1771
1772 __raw_writeq(0, s->sbm_macenable);
1773
1774 /* We're stopped now. */
1775
1776 s->sbm_state = sbmac_state_off;
1777
1778 /*
1779 * Stop DMA channels (rings should be ok now)
1780 */
1781
1782 sbdma_channel_stop(&(s->sbm_rxdma));
1783 sbdma_channel_stop(&(s->sbm_txdma));
1784
1785 /* Empty the receive and transmit rings */
1786
1787 sbdma_emptyring(&(s->sbm_rxdma));
1788 sbdma_emptyring(&(s->sbm_txdma));
1789
1790 }
1791
1792 /**********************************************************************
1793 * SBMAC_SET_CHANNEL_STATE(state)
1794 *
1795 * Set the channel's state ON or OFF
1796 *
1797 * Input parameters:
1798 * state - new state
1799 *
1800 * Return value:
1801 * old state
1802 ********************************************************************* */
1803 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1804 sbmac_state_t state)
1805 {
1806 sbmac_state_t oldstate = sc->sbm_state;
1807
1808 /*
1809 * If same as previous state, return
1810 */
1811
1812 if (state == oldstate) {
1813 return oldstate;
1814 }
1815
1816 /*
1817 * If new state is ON, turn channel on
1818 */
1819
1820 if (state == sbmac_state_on) {
1821 sbmac_channel_start(sc);
1822 }
1823 else {
1824 sbmac_channel_stop(sc);
1825 }
1826
1827 /*
1828 * Return previous state
1829 */
1830
1831 return oldstate;
1832 }
1833
1834
1835 /**********************************************************************
1836 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1837 *
1838 * Turn on or off promiscuous mode
1839 *
1840 * Input parameters:
1841 * sc - softc
1842 * onoff - 1 to turn on, 0 to turn off
1843 *
1844 * Return value:
1845 * nothing
1846 ********************************************************************* */
1847
1848 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1849 {
1850 uint64_t reg;
1851
1852 if (sc->sbm_state != sbmac_state_on)
1853 return;
1854
1855 if (onoff) {
1856 reg = __raw_readq(sc->sbm_rxfilter);
1857 reg |= M_MAC_ALLPKT_EN;
1858 __raw_writeq(reg, sc->sbm_rxfilter);
1859 }
1860 else {
1861 reg = __raw_readq(sc->sbm_rxfilter);
1862 reg &= ~M_MAC_ALLPKT_EN;
1863 __raw_writeq(reg, sc->sbm_rxfilter);
1864 }
1865 }
1866
1867 /**********************************************************************
1868 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1869 *
1870 * Set the iphdr offset as 15 assuming ethernet encapsulation
1871 *
1872 * Input parameters:
1873 * sc - softc
1874 *
1875 * Return value:
1876 * nothing
1877 ********************************************************************* */
1878
1879 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1880 {
1881 uint64_t reg;
1882
1883 /* Hard code the off set to 15 for now */
1884 reg = __raw_readq(sc->sbm_rxfilter);
1885 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1886 __raw_writeq(reg, sc->sbm_rxfilter);
1887
1888 /* BCM1250 pass1 didn't have hardware checksum. Everything
1889 later does. */
1890 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1891 sc->rx_hw_checksum = DISABLE;
1892 } else {
1893 sc->rx_hw_checksum = ENABLE;
1894 }
1895 }
1896
1897
1898 /**********************************************************************
1899 * SBMAC_ADDR2REG(ptr)
1900 *
1901 * Convert six bytes into the 64-bit register value that
1902 * we typically write into the SBMAC's address/mcast registers
1903 *
1904 * Input parameters:
1905 * ptr - pointer to 6 bytes
1906 *
1907 * Return value:
1908 * register value
1909 ********************************************************************* */
1910
1911 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1912 {
1913 uint64_t reg = 0;
1914
1915 ptr += 6;
1916
1917 reg |= (uint64_t) *(--ptr);
1918 reg <<= 8;
1919 reg |= (uint64_t) *(--ptr);
1920 reg <<= 8;
1921 reg |= (uint64_t) *(--ptr);
1922 reg <<= 8;
1923 reg |= (uint64_t) *(--ptr);
1924 reg <<= 8;
1925 reg |= (uint64_t) *(--ptr);
1926 reg <<= 8;
1927 reg |= (uint64_t) *(--ptr);
1928
1929 return reg;
1930 }
1931
1932
1933 /**********************************************************************
1934 * SBMAC_SET_SPEED(s,speed)
1935 *
1936 * Configure LAN speed for the specified MAC.
1937 * Warning: must be called when MAC is off!
1938 *
1939 * Input parameters:
1940 * s - sbmac structure
1941 * speed - speed to set MAC to (see sbmac_speed_t enum)
1942 *
1943 * Return value:
1944 * 1 if successful
1945 * 0 indicates invalid parameters
1946 ********************************************************************* */
1947
1948 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1949 {
1950 uint64_t cfg;
1951 uint64_t framecfg;
1952
1953 /*
1954 * Save new current values
1955 */
1956
1957 s->sbm_speed = speed;
1958
1959 if (s->sbm_state == sbmac_state_on)
1960 return 0; /* save for next restart */
1961
1962 /*
1963 * Read current register values
1964 */
1965
1966 cfg = __raw_readq(s->sbm_maccfg);
1967 framecfg = __raw_readq(s->sbm_framecfg);
1968
1969 /*
1970 * Mask out the stuff we want to change
1971 */
1972
1973 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1974 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1975 M_MAC_SLOT_SIZE);
1976
1977 /*
1978 * Now add in the new bits
1979 */
1980
1981 switch (speed) {
1982 case sbmac_speed_10:
1983 framecfg |= V_MAC_IFG_RX_10 |
1984 V_MAC_IFG_TX_10 |
1985 K_MAC_IFG_THRSH_10 |
1986 V_MAC_SLOT_SIZE_10;
1987 cfg |= V_MAC_SPEED_SEL_10MBPS;
1988 break;
1989
1990 case sbmac_speed_100:
1991 framecfg |= V_MAC_IFG_RX_100 |
1992 V_MAC_IFG_TX_100 |
1993 V_MAC_IFG_THRSH_100 |
1994 V_MAC_SLOT_SIZE_100;
1995 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1996 break;
1997
1998 case sbmac_speed_1000:
1999 framecfg |= V_MAC_IFG_RX_1000 |
2000 V_MAC_IFG_TX_1000 |
2001 V_MAC_IFG_THRSH_1000 |
2002 V_MAC_SLOT_SIZE_1000;
2003 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
2004 break;
2005
2006 case sbmac_speed_auto: /* XXX not implemented */
2007 /* fall through */
2008 default:
2009 return 0;
2010 }
2011
2012 /*
2013 * Send the bits back to the hardware
2014 */
2015
2016 __raw_writeq(framecfg, s->sbm_framecfg);
2017 __raw_writeq(cfg, s->sbm_maccfg);
2018
2019 return 1;
2020 }
2021
2022 /**********************************************************************
2023 * SBMAC_SET_DUPLEX(s,duplex,fc)
2024 *
2025 * Set Ethernet duplex and flow control options for this MAC
2026 * Warning: must be called when MAC is off!
2027 *
2028 * Input parameters:
2029 * s - sbmac structure
2030 * duplex - duplex setting (see sbmac_duplex_t)
2031 * fc - flow control setting (see sbmac_fc_t)
2032 *
2033 * Return value:
2034 * 1 if ok
2035 * 0 if an invalid parameter combination was specified
2036 ********************************************************************* */
2037
2038 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
2039 {
2040 uint64_t cfg;
2041
2042 /*
2043 * Save new current values
2044 */
2045
2046 s->sbm_duplex = duplex;
2047 s->sbm_fc = fc;
2048
2049 if (s->sbm_state == sbmac_state_on)
2050 return 0; /* save for next restart */
2051
2052 /*
2053 * Read current register values
2054 */
2055
2056 cfg = __raw_readq(s->sbm_maccfg);
2057
2058 /*
2059 * Mask off the stuff we're about to change
2060 */
2061
2062 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
2063
2064
2065 switch (duplex) {
2066 case sbmac_duplex_half:
2067 switch (fc) {
2068 case sbmac_fc_disabled:
2069 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2070 break;
2071
2072 case sbmac_fc_collision:
2073 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2074 break;
2075
2076 case sbmac_fc_carrier:
2077 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2078 break;
2079
2080 case sbmac_fc_auto: /* XXX not implemented */
2081 /* fall through */
2082 case sbmac_fc_frame: /* not valid in half duplex */
2083 default: /* invalid selection */
2084 return 0;
2085 }
2086 break;
2087
2088 case sbmac_duplex_full:
2089 switch (fc) {
2090 case sbmac_fc_disabled:
2091 cfg |= V_MAC_FC_CMD_DISABLED;
2092 break;
2093
2094 case sbmac_fc_frame:
2095 cfg |= V_MAC_FC_CMD_ENABLED;
2096 break;
2097
2098 case sbmac_fc_collision: /* not valid in full duplex */
2099 case sbmac_fc_carrier: /* not valid in full duplex */
2100 case sbmac_fc_auto: /* XXX not implemented */
2101 /* fall through */
2102 default:
2103 return 0;
2104 }
2105 break;
2106 case sbmac_duplex_auto:
2107 /* XXX not implemented */
2108 break;
2109 }
2110
2111 /*
2112 * Send the bits back to the hardware
2113 */
2114
2115 __raw_writeq(cfg, s->sbm_maccfg);
2116
2117 return 1;
2118 }
2119
2120
2121
2122
2123 /**********************************************************************
2124 * SBMAC_INTR()
2125 *
2126 * Interrupt handler for MAC interrupts
2127 *
2128 * Input parameters:
2129 * MAC structure
2130 *
2131 * Return value:
2132 * nothing
2133 ********************************************************************* */
2134 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
2135 {
2136 struct net_device *dev = (struct net_device *) dev_instance;
2137 struct sbmac_softc *sc = netdev_priv(dev);
2138 uint64_t isr;
2139 int handled = 0;
2140
2141 /*
2142 * Read the ISR (this clears the bits in the real
2143 * register, except for counter addr)
2144 */
2145
2146 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2147
2148 if (isr == 0)
2149 return IRQ_RETVAL(0);
2150 handled = 1;
2151
2152 /*
2153 * Transmits on channel 0
2154 */
2155
2156 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2157 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2158
2159 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2160 if (netif_rx_schedule_prep(dev, &sc->napi)) {
2161 __raw_writeq(0, sc->sbm_imr);
2162 __netif_rx_schedule(dev, &sc->napi);
2163 /* Depend on the exit from poll to reenable intr */
2164 }
2165 else {
2166 /* may leave some packets behind */
2167 sbdma_rx_process(sc,&(sc->sbm_rxdma),
2168 SBMAC_MAX_RXDESCR * 2, 0);
2169 }
2170 }
2171 return IRQ_RETVAL(handled);
2172 }
2173
2174 /**********************************************************************
2175 * SBMAC_START_TX(skb,dev)
2176 *
2177 * Start output on the specified interface. Basically, we
2178 * queue as many buffers as we can until the ring fills up, or
2179 * we run off the end of the queue, whichever comes first.
2180 *
2181 * Input parameters:
2182 *
2183 *
2184 * Return value:
2185 * nothing
2186 ********************************************************************* */
2187 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2188 {
2189 struct sbmac_softc *sc = netdev_priv(dev);
2190
2191 /* lock eth irq */
2192 spin_lock_irq (&sc->sbm_lock);
2193
2194 /*
2195 * Put the buffer on the transmit ring. If we
2196 * don't have room, stop the queue.
2197 */
2198
2199 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2200 /* XXX save skb that we could not send */
2201 netif_stop_queue(dev);
2202 spin_unlock_irq(&sc->sbm_lock);
2203
2204 return 1;
2205 }
2206
2207 dev->trans_start = jiffies;
2208
2209 spin_unlock_irq (&sc->sbm_lock);
2210
2211 return 0;
2212 }
2213
2214 /**********************************************************************
2215 * SBMAC_SETMULTI(sc)
2216 *
2217 * Reprogram the multicast table into the hardware, given
2218 * the list of multicasts associated with the interface
2219 * structure.
2220 *
2221 * Input parameters:
2222 * sc - softc
2223 *
2224 * Return value:
2225 * nothing
2226 ********************************************************************* */
2227
2228 static void sbmac_setmulti(struct sbmac_softc *sc)
2229 {
2230 uint64_t reg;
2231 volatile void __iomem *port;
2232 int idx;
2233 struct dev_mc_list *mclist;
2234 struct net_device *dev = sc->sbm_dev;
2235
2236 /*
2237 * Clear out entire multicast table. We do this by nuking
2238 * the entire hash table and all the direct matches except
2239 * the first one, which is used for our station address
2240 */
2241
2242 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2243 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2244 __raw_writeq(0, port);
2245 }
2246
2247 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2248 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2249 __raw_writeq(0, port);
2250 }
2251
2252 /*
2253 * Clear the filter to say we don't want any multicasts.
2254 */
2255
2256 reg = __raw_readq(sc->sbm_rxfilter);
2257 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2258 __raw_writeq(reg, sc->sbm_rxfilter);
2259
2260 if (dev->flags & IFF_ALLMULTI) {
2261 /*
2262 * Enable ALL multicasts. Do this by inverting the
2263 * multicast enable bit.
2264 */
2265 reg = __raw_readq(sc->sbm_rxfilter);
2266 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2267 __raw_writeq(reg, sc->sbm_rxfilter);
2268 return;
2269 }
2270
2271
2272 /*
2273 * Progam new multicast entries. For now, only use the
2274 * perfect filter. In the future we'll need to use the
2275 * hash filter if the perfect filter overflows
2276 */
2277
2278 /* XXX only using perfect filter for now, need to use hash
2279 * XXX if the table overflows */
2280
2281 idx = 1; /* skip station address */
2282 mclist = dev->mc_list;
2283 while (mclist && (idx < MAC_ADDR_COUNT)) {
2284 reg = sbmac_addr2reg(mclist->dmi_addr);
2285 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2286 __raw_writeq(reg, port);
2287 idx++;
2288 mclist = mclist->next;
2289 }
2290
2291 /*
2292 * Enable the "accept multicast bits" if we programmed at least one
2293 * multicast.
2294 */
2295
2296 if (idx > 1) {
2297 reg = __raw_readq(sc->sbm_rxfilter);
2298 reg |= M_MAC_MCAST_EN;
2299 __raw_writeq(reg, sc->sbm_rxfilter);
2300 }
2301 }
2302
2303 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2304 /**********************************************************************
2305 * SBMAC_PARSE_XDIGIT(str)
2306 *
2307 * Parse a hex digit, returning its value
2308 *
2309 * Input parameters:
2310 * str - character
2311 *
2312 * Return value:
2313 * hex value, or -1 if invalid
2314 ********************************************************************* */
2315
2316 static int sbmac_parse_xdigit(char str)
2317 {
2318 int digit;
2319
2320 if ((str >= '0') && (str <= '9'))
2321 digit = str - '0';
2322 else if ((str >= 'a') && (str <= 'f'))
2323 digit = str - 'a' + 10;
2324 else if ((str >= 'A') && (str <= 'F'))
2325 digit = str - 'A' + 10;
2326 else
2327 return -1;
2328
2329 return digit;
2330 }
2331
2332 /**********************************************************************
2333 * SBMAC_PARSE_HWADDR(str,hwaddr)
2334 *
2335 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2336 * Ethernet address.
2337 *
2338 * Input parameters:
2339 * str - string
2340 * hwaddr - pointer to hardware address
2341 *
2342 * Return value:
2343 * 0 if ok, else -1
2344 ********************************************************************* */
2345
2346 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2347 {
2348 int digit1,digit2;
2349 int idx = 6;
2350
2351 while (*str && (idx > 0)) {
2352 digit1 = sbmac_parse_xdigit(*str);
2353 if (digit1 < 0)
2354 return -1;
2355 str++;
2356 if (!*str)
2357 return -1;
2358
2359 if ((*str == ':') || (*str == '-')) {
2360 digit2 = digit1;
2361 digit1 = 0;
2362 }
2363 else {
2364 digit2 = sbmac_parse_xdigit(*str);
2365 if (digit2 < 0)
2366 return -1;
2367 str++;
2368 }
2369
2370 *hwaddr++ = (digit1 << 4) | digit2;
2371 idx--;
2372
2373 if (*str == '-')
2374 str++;
2375 if (*str == ':')
2376 str++;
2377 }
2378 return 0;
2379 }
2380 #endif
2381
2382 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2383 {
2384 if (new_mtu > ENET_PACKET_SIZE)
2385 return -EINVAL;
2386 _dev->mtu = new_mtu;
2387 printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2388 return 0;
2389 }
2390
2391 /**********************************************************************
2392 * SBMAC_INIT(dev)
2393 *
2394 * Attach routine - init hardware and hook ourselves into linux
2395 *
2396 * Input parameters:
2397 * dev - net_device structure
2398 *
2399 * Return value:
2400 * status
2401 ********************************************************************* */
2402
2403 static int sbmac_init(struct net_device *dev, int idx)
2404 {
2405 struct sbmac_softc *sc;
2406 unsigned char *eaddr;
2407 uint64_t ea_reg;
2408 int i;
2409 int err;
2410 DECLARE_MAC_BUF(mac);
2411
2412 sc = netdev_priv(dev);
2413
2414 /* Determine controller base address */
2415
2416 sc->sbm_base = IOADDR(dev->base_addr);
2417 sc->sbm_dev = dev;
2418 sc->sbe_idx = idx;
2419
2420 eaddr = sc->sbm_hwaddr;
2421
2422 /*
2423 * Read the ethernet address. The firwmare left this programmed
2424 * for us in the ethernet address register for each mac.
2425 */
2426
2427 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2428 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2429 for (i = 0; i < 6; i++) {
2430 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2431 ea_reg >>= 8;
2432 }
2433
2434 for (i = 0; i < 6; i++) {
2435 dev->dev_addr[i] = eaddr[i];
2436 }
2437
2438
2439 /*
2440 * Init packet size
2441 */
2442
2443 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2444
2445 /*
2446 * Initialize context (get pointers to registers and stuff), then
2447 * allocate the memory for the descriptor tables.
2448 */
2449
2450 sbmac_initctx(sc);
2451
2452 /*
2453 * Set up Linux device callins
2454 */
2455
2456 spin_lock_init(&(sc->sbm_lock));
2457
2458 dev->open = sbmac_open;
2459 dev->hard_start_xmit = sbmac_start_tx;
2460 dev->stop = sbmac_close;
2461 dev->set_multicast_list = sbmac_set_rx_mode;
2462 dev->do_ioctl = sbmac_mii_ioctl;
2463 dev->tx_timeout = sbmac_tx_timeout;
2464 dev->watchdog_timeo = TX_TIMEOUT;
2465
2466 netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2467
2468 dev->change_mtu = sb1250_change_mtu;
2469 #ifdef CONFIG_NET_POLL_CONTROLLER
2470 dev->poll_controller = sbmac_netpoll;
2471 #endif
2472
2473 /* This is needed for PASS2 for Rx H/W checksum feature */
2474 sbmac_set_iphdr_offset(sc);
2475
2476 err = register_netdev(dev);
2477 if (err)
2478 goto out_uninit;
2479
2480 if (sc->rx_hw_checksum == ENABLE) {
2481 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2482 sc->sbm_dev->name);
2483 }
2484
2485 /*
2486 * Display Ethernet address (this is called during the config
2487 * process so we need to finish off the config message that
2488 * was being displayed)
2489 */
2490 printk(KERN_INFO
2491 "%s: SiByte Ethernet at 0x%08lX, address: %s\n",
2492 dev->name, dev->base_addr, print_mac(mac, eaddr));
2493
2494 return 0;
2495
2496 out_uninit:
2497 sbmac_uninitctx(sc);
2498
2499 return err;
2500 }
2501
2502
2503 static int sbmac_open(struct net_device *dev)
2504 {
2505 struct sbmac_softc *sc = netdev_priv(dev);
2506
2507 if (debug > 1) {
2508 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2509 }
2510
2511 /*
2512 * map/route interrupt (clear status first, in case something
2513 * weird is pending; we haven't initialized the mac registers
2514 * yet)
2515 */
2516
2517 __raw_readq(sc->sbm_isr);
2518 if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev))
2519 return -EBUSY;
2520
2521 /*
2522 * Probe phy address
2523 */
2524
2525 if(sbmac_mii_probe(dev) == -1) {
2526 printk("%s: failed to probe PHY.\n", dev->name);
2527 return -EINVAL;
2528 }
2529
2530 napi_enable(&sc->napi);
2531
2532 /*
2533 * Configure default speed
2534 */
2535
2536 sbmac_mii_poll(sc,noisy_mii);
2537
2538 /*
2539 * Turn on the channel
2540 */
2541
2542 sbmac_set_channel_state(sc,sbmac_state_on);
2543
2544 /*
2545 * XXX Station address is in dev->dev_addr
2546 */
2547
2548 if (dev->if_port == 0)
2549 dev->if_port = 0;
2550
2551 netif_start_queue(dev);
2552
2553 sbmac_set_rx_mode(dev);
2554
2555 /* Set the timer to check for link beat. */
2556 init_timer(&sc->sbm_timer);
2557 sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2558 sc->sbm_timer.data = (unsigned long)dev;
2559 sc->sbm_timer.function = &sbmac_timer;
2560 add_timer(&sc->sbm_timer);
2561
2562 return 0;
2563 }
2564
2565 static int sbmac_mii_probe(struct net_device *dev)
2566 {
2567 int i;
2568 struct sbmac_softc *s = netdev_priv(dev);
2569 u16 bmsr, id1, id2;
2570 u32 vendor, device;
2571
2572 for (i=1; i<31; i++) {
2573 bmsr = sbmac_mii_read(s, i, MII_BMSR);
2574 if (bmsr != 0) {
2575 s->sbm_phys[0] = i;
2576 id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2577 id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2578 vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2579 device = (id2 >> 4) & 0x3f;
2580
2581 printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2582 dev->name, i, vendor, device);
2583 return i;
2584 }
2585 }
2586 return -1;
2587 }
2588
2589
2590 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2591 {
2592 int bmsr,bmcr,k1stsr,anlpar;
2593 int chg;
2594 char buffer[100];
2595 char *p = buffer;
2596
2597 /* Read the mode status and mode control registers. */
2598 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2599 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2600
2601 /* get the link partner status */
2602 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2603
2604 /* if supported, read the 1000baseT register */
2605 if (bmsr & BMSR_1000BT_XSR) {
2606 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2607 }
2608 else {
2609 k1stsr = 0;
2610 }
2611
2612 chg = 0;
2613
2614 if ((bmsr & BMSR_LINKSTAT) == 0) {
2615 /*
2616 * If link status is down, clear out old info so that when
2617 * it comes back up it will force us to reconfigure speed
2618 */
2619 s->sbm_phy_oldbmsr = 0;
2620 s->sbm_phy_oldanlpar = 0;
2621 s->sbm_phy_oldk1stsr = 0;
2622 return 0;
2623 }
2624
2625 if ((s->sbm_phy_oldbmsr != bmsr) ||
2626 (s->sbm_phy_oldanlpar != anlpar) ||
2627 (s->sbm_phy_oldk1stsr != k1stsr)) {
2628 if (debug > 1) {
2629 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2630 s->sbm_dev->name,
2631 s->sbm_phy_oldbmsr,bmsr,
2632 s->sbm_phy_oldanlpar,anlpar,
2633 s->sbm_phy_oldk1stsr,k1stsr);
2634 }
2635 s->sbm_phy_oldbmsr = bmsr;
2636 s->sbm_phy_oldanlpar = anlpar;
2637 s->sbm_phy_oldk1stsr = k1stsr;
2638 chg = 1;
2639 }
2640
2641 if (chg == 0)
2642 return 0;
2643
2644 p += sprintf(p,"Link speed: ");
2645
2646 if (k1stsr & K1STSR_LP1KFD) {
2647 s->sbm_speed = sbmac_speed_1000;
2648 s->sbm_duplex = sbmac_duplex_full;
2649 s->sbm_fc = sbmac_fc_frame;
2650 p += sprintf(p,"1000BaseT FDX");
2651 }
2652 else if (k1stsr & K1STSR_LP1KHD) {
2653 s->sbm_speed = sbmac_speed_1000;
2654 s->sbm_duplex = sbmac_duplex_half;
2655 s->sbm_fc = sbmac_fc_disabled;
2656 p += sprintf(p,"1000BaseT HDX");
2657 }
2658 else if (anlpar & ANLPAR_TXFD) {
2659 s->sbm_speed = sbmac_speed_100;
2660 s->sbm_duplex = sbmac_duplex_full;
2661 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2662 p += sprintf(p,"100BaseT FDX");
2663 }
2664 else if (anlpar & ANLPAR_TXHD) {
2665 s->sbm_speed = sbmac_speed_100;
2666 s->sbm_duplex = sbmac_duplex_half;
2667 s->sbm_fc = sbmac_fc_disabled;
2668 p += sprintf(p,"100BaseT HDX");
2669 }
2670 else if (anlpar & ANLPAR_10FD) {
2671 s->sbm_speed = sbmac_speed_10;
2672 s->sbm_duplex = sbmac_duplex_full;
2673 s->sbm_fc = sbmac_fc_frame;
2674 p += sprintf(p,"10BaseT FDX");
2675 }
2676 else if (anlpar & ANLPAR_10HD) {
2677 s->sbm_speed = sbmac_speed_10;
2678 s->sbm_duplex = sbmac_duplex_half;
2679 s->sbm_fc = sbmac_fc_collision;
2680 p += sprintf(p,"10BaseT HDX");
2681 }
2682 else {
2683 p += sprintf(p,"Unknown");
2684 }
2685
2686 if (noisy) {
2687 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2688 }
2689
2690 return 1;
2691 }
2692
2693
2694 static void sbmac_timer(unsigned long data)
2695 {
2696 struct net_device *dev = (struct net_device *)data;
2697 struct sbmac_softc *sc = netdev_priv(dev);
2698 int next_tick = HZ;
2699 int mii_status;
2700
2701 spin_lock_irq (&sc->sbm_lock);
2702
2703 /* make IFF_RUNNING follow the MII status bit "Link established" */
2704 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2705
2706 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2707 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2708 if (mii_status & BMSR_LINKSTAT) {
2709 netif_carrier_on(dev);
2710 }
2711 else {
2712 netif_carrier_off(dev);
2713 }
2714 }
2715
2716 /*
2717 * Poll the PHY to see what speed we should be running at
2718 */
2719
2720 if (sbmac_mii_poll(sc,noisy_mii)) {
2721 if (sc->sbm_state != sbmac_state_off) {
2722 /*
2723 * something changed, restart the channel
2724 */
2725 if (debug > 1) {
2726 printk("%s: restarting channel because speed changed\n",
2727 sc->sbm_dev->name);
2728 }
2729 sbmac_channel_stop(sc);
2730 sbmac_channel_start(sc);
2731 }
2732 }
2733
2734 spin_unlock_irq (&sc->sbm_lock);
2735
2736 sc->sbm_timer.expires = jiffies + next_tick;
2737 add_timer(&sc->sbm_timer);
2738 }
2739
2740
2741 static void sbmac_tx_timeout (struct net_device *dev)
2742 {
2743 struct sbmac_softc *sc = netdev_priv(dev);
2744
2745 spin_lock_irq (&sc->sbm_lock);
2746
2747
2748 dev->trans_start = jiffies;
2749 dev->stats.tx_errors++;
2750
2751 spin_unlock_irq (&sc->sbm_lock);
2752
2753 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2754 }
2755
2756
2757
2758
2759 static void sbmac_set_rx_mode(struct net_device *dev)
2760 {
2761 unsigned long flags;
2762 struct sbmac_softc *sc = netdev_priv(dev);
2763
2764 spin_lock_irqsave(&sc->sbm_lock, flags);
2765 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2766 /*
2767 * Promiscuous changed.
2768 */
2769
2770 if (dev->flags & IFF_PROMISC) {
2771 sbmac_promiscuous_mode(sc,1);
2772 }
2773 else {
2774 sbmac_promiscuous_mode(sc,0);
2775 }
2776 }
2777 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2778
2779 /*
2780 * Program the multicasts. Do this every time.
2781 */
2782
2783 sbmac_setmulti(sc);
2784
2785 }
2786
2787 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2788 {
2789 struct sbmac_softc *sc = netdev_priv(dev);
2790 u16 *data = (u16 *)&rq->ifr_ifru;
2791 unsigned long flags;
2792 int retval;
2793
2794 spin_lock_irqsave(&sc->sbm_lock, flags);
2795 retval = 0;
2796
2797 switch(cmd) {
2798 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2799 data[0] = sc->sbm_phys[0] & 0x1f;
2800 /* Fall Through */
2801 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2802 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2803 break;
2804 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2805 if (!capable(CAP_NET_ADMIN)) {
2806 retval = -EPERM;
2807 break;
2808 }
2809 if (debug > 1) {
2810 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2811 data[0],data[1],data[2]);
2812 }
2813 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2814 break;
2815 default:
2816 retval = -EOPNOTSUPP;
2817 }
2818
2819 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2820 return retval;
2821 }
2822
2823 static int sbmac_close(struct net_device *dev)
2824 {
2825 struct sbmac_softc *sc = netdev_priv(dev);
2826 unsigned long flags;
2827 int irq;
2828
2829 napi_disable(&sc->napi);
2830
2831 sbmac_set_channel_state(sc,sbmac_state_off);
2832
2833 del_timer_sync(&sc->sbm_timer);
2834
2835 spin_lock_irqsave(&sc->sbm_lock, flags);
2836
2837 netif_stop_queue(dev);
2838
2839 if (debug > 1) {
2840 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2841 }
2842
2843 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2844
2845 irq = dev->irq;
2846 synchronize_irq(irq);
2847 free_irq(irq, dev);
2848
2849 sbdma_emptyring(&(sc->sbm_txdma));
2850 sbdma_emptyring(&(sc->sbm_rxdma));
2851
2852 return 0;
2853 }
2854
2855 static int sbmac_poll(struct napi_struct *napi, int budget)
2856 {
2857 struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2858 struct net_device *dev = sc->sbm_dev;
2859 int work_done;
2860
2861 work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2862 sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2863
2864 if (work_done < budget) {
2865 netif_rx_complete(dev, napi);
2866
2867 #ifdef CONFIG_SBMAC_COALESCE
2868 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2869 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2870 sc->sbm_imr);
2871 #else
2872 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2873 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2874 #endif
2875 }
2876
2877 return work_done;
2878 }
2879
2880 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2881 static void
2882 sbmac_setup_hwaddr(int chan,char *addr)
2883 {
2884 uint8_t eaddr[6];
2885 uint64_t val;
2886 unsigned long port;
2887
2888 port = A_MAC_CHANNEL_BASE(chan);
2889 sbmac_parse_hwaddr(addr,eaddr);
2890 val = sbmac_addr2reg(eaddr);
2891 __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2892 val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2893 }
2894 #endif
2895
2896 static struct net_device *dev_sbmac[MAX_UNITS];
2897
2898 static int __init
2899 sbmac_init_module(void)
2900 {
2901 int idx;
2902 struct net_device *dev;
2903 unsigned long port;
2904 int chip_max_units;
2905
2906 /* Set the number of available units based on the SOC type. */
2907 switch (soc_type) {
2908 case K_SYS_SOC_TYPE_BCM1250:
2909 case K_SYS_SOC_TYPE_BCM1250_ALT:
2910 chip_max_units = 3;
2911 break;
2912 case K_SYS_SOC_TYPE_BCM1120:
2913 case K_SYS_SOC_TYPE_BCM1125:
2914 case K_SYS_SOC_TYPE_BCM1125H:
2915 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2916 chip_max_units = 2;
2917 break;
2918 case K_SYS_SOC_TYPE_BCM1x55:
2919 case K_SYS_SOC_TYPE_BCM1x80:
2920 chip_max_units = 4;
2921 break;
2922 default:
2923 chip_max_units = 0;
2924 break;
2925 }
2926 if (chip_max_units > MAX_UNITS)
2927 chip_max_units = MAX_UNITS;
2928
2929 /*
2930 * For bringup when not using the firmware, we can pre-fill
2931 * the MAC addresses using the environment variables
2932 * specified in this file (or maybe from the config file?)
2933 */
2934 #ifdef SBMAC_ETH0_HWADDR
2935 if (chip_max_units > 0)
2936 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2937 #endif
2938 #ifdef SBMAC_ETH1_HWADDR
2939 if (chip_max_units > 1)
2940 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2941 #endif
2942 #ifdef SBMAC_ETH2_HWADDR
2943 if (chip_max_units > 2)
2944 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2945 #endif
2946 #ifdef SBMAC_ETH3_HWADDR
2947 if (chip_max_units > 3)
2948 sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
2949 #endif
2950
2951 /*
2952 * Walk through the Ethernet controllers and find
2953 * those who have their MAC addresses set.
2954 */
2955 for (idx = 0; idx < chip_max_units; idx++) {
2956
2957 /*
2958 * This is the base address of the MAC.
2959 */
2960
2961 port = A_MAC_CHANNEL_BASE(idx);
2962
2963 /*
2964 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2965 * value for us by the firmware if we are going to use this MAC.
2966 * If we find a zero, skip this MAC.
2967 */
2968
2969 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2970 if (sbmac_orig_hwaddr[idx] == 0) {
2971 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2972 "%lx\n", port);
2973 continue;
2974 }
2975
2976 /*
2977 * Okay, cool. Initialize this MAC.
2978 */
2979
2980 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2981 if (!dev)
2982 return -ENOMEM;
2983
2984 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2985
2986 dev->irq = UNIT_INT(idx);
2987 dev->base_addr = port;
2988 dev->mem_end = 0;
2989 if (sbmac_init(dev, idx)) {
2990 port = A_MAC_CHANNEL_BASE(idx);
2991 __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
2992 free_netdev(dev);
2993 continue;
2994 }
2995 dev_sbmac[idx] = dev;
2996 }
2997 return 0;
2998 }
2999
3000
3001 static void __exit
3002 sbmac_cleanup_module(void)
3003 {
3004 struct net_device *dev;
3005 int idx;
3006
3007 for (idx = 0; idx < MAX_UNITS; idx++) {
3008 struct sbmac_softc *sc;
3009 dev = dev_sbmac[idx];
3010 if (!dev)
3011 continue;
3012
3013 sc = netdev_priv(dev);
3014 unregister_netdev(dev);
3015 sbmac_uninitctx(sc);
3016 free_netdev(dev);
3017 }
3018 }
3019
3020 module_init(sbmac_init_module);
3021 module_exit(sbmac_cleanup_module);
Linux kernel - Deliverables
This page took 0.116317 seconds and 5 git commands to generate.