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drivers/net/sb1250-mac.c: kmalloc + memset conversion to kcalloc
[deliverable/linux.git] / drivers / net / sb1250-mac.c
1 /*
2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 *
19 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
21 */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <asm/processor.h> /* Processor type for cache alignment. */
36 #include <asm/io.h>
37 #include <asm/cache.h>
38
39 /* This is only here until the firmware is ready. In that case,
40 the firmware leaves the ethernet address in the register for us. */
41 #ifdef CONFIG_SIBYTE_STANDALONE
42 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
43 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
44 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
45 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
46 #endif
47
48
49 /* These identify the driver base version and may not be removed. */
50 #if 0
51 static char version1[] __devinitdata =
52 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
53 #endif
54
55
56 /* Operational parameters that usually are not changed. */
57
58 #define CONFIG_SBMAC_COALESCE
59
60 #define MAX_UNITS 4 /* More are supported, limit only on options */
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (2*HZ)
64
65
66 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
67 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
68
69 /* A few user-configurable values which may be modified when a driver
70 module is loaded. */
71
72 /* 1 normal messages, 0 quiet .. 7 verbose. */
73 static int debug = 1;
74 module_param(debug, int, S_IRUGO);
75 MODULE_PARM_DESC(debug, "Debug messages");
76
77 /* mii status msgs */
78 static int noisy_mii = 1;
79 module_param(noisy_mii, int, S_IRUGO);
80 MODULE_PARM_DESC(noisy_mii, "MII status messages");
81
82 /* Used to pass the media type, etc.
83 Both 'options[]' and 'full_duplex[]' should exist for driver
84 interoperability.
85 The media type is usually passed in 'options[]'.
86 */
87 #ifdef MODULE
88 static int options[MAX_UNITS] = {-1, -1, -1, -1};
89 module_param_array(options, int, NULL, S_IRUGO);
90 MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
91
92 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
93 module_param_array(full_duplex, int, NULL, S_IRUGO);
94 MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
95 #endif
96
97 #ifdef CONFIG_SBMAC_COALESCE
98 static int int_pktcnt_tx = 255;
99 module_param(int_pktcnt_tx, int, S_IRUGO);
100 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
101
102 static int int_timeout_tx = 255;
103 module_param(int_timeout_tx, int, S_IRUGO);
104 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
105
106 static int int_pktcnt_rx = 64;
107 module_param(int_pktcnt_rx, int, S_IRUGO);
108 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
109
110 static int int_timeout_rx = 64;
111 module_param(int_timeout_rx, int, S_IRUGO);
112 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
113 #endif
114
115 #include <asm/sibyte/sb1250.h>
116 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
117 #include <asm/sibyte/bcm1480_regs.h>
118 #include <asm/sibyte/bcm1480_int.h>
119 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
120 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
121 #include <asm/sibyte/sb1250_regs.h>
122 #include <asm/sibyte/sb1250_int.h>
123 #else
124 #error invalid SiByte MAC configuation
125 #endif
126 #include <asm/sibyte/sb1250_scd.h>
127 #include <asm/sibyte/sb1250_mac.h>
128 #include <asm/sibyte/sb1250_dma.h>
129
130 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
131 #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
132 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
133 #define UNIT_INT(n) (K_INT_MAC_0 + (n))
134 #else
135 #error invalid SiByte MAC configuation
136 #endif
137
138 /**********************************************************************
139 * Simple types
140 ********************************************************************* */
141
142
143 typedef enum { sbmac_speed_auto, sbmac_speed_10,
144 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
145
146 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
147 sbmac_duplex_full } sbmac_duplex_t;
148
149 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
150 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
151
152 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
153 sbmac_state_broken } sbmac_state_t;
154
155
156 /**********************************************************************
157 * Macros
158 ********************************************************************* */
159
160
161 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
162 (d)->sbdma_dscrtable : (d)->f+1)
163
164
165 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
166
167 #define SBMAC_MAX_TXDESCR 256
168 #define SBMAC_MAX_RXDESCR 256
169
170 #define ETHER_ALIGN 2
171 #define ETHER_ADDR_LEN 6
172 #define ENET_PACKET_SIZE 1518
173 /*#define ENET_PACKET_SIZE 9216 */
174
175 /**********************************************************************
176 * DMA Descriptor structure
177 ********************************************************************* */
178
179 typedef struct sbdmadscr_s {
180 uint64_t dscr_a;
181 uint64_t dscr_b;
182 } sbdmadscr_t;
183
184 typedef unsigned long paddr_t;
185
186 /**********************************************************************
187 * DMA Controller structure
188 ********************************************************************* */
189
190 typedef struct sbmacdma_s {
191
192 /*
193 * This stuff is used to identify the channel and the registers
194 * associated with it.
195 */
196
197 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
198 int sbdma_channel; /* channel number */
199 int sbdma_txdir; /* direction (1=transmit) */
200 int sbdma_maxdescr; /* total # of descriptors in ring */
201 #ifdef CONFIG_SBMAC_COALESCE
202 int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/
203 int sbdma_int_timeout; /* # usec rx/tx interrupt */
204 #endif
205
206 volatile void __iomem *sbdma_config0; /* DMA config register 0 */
207 volatile void __iomem *sbdma_config1; /* DMA config register 1 */
208 volatile void __iomem *sbdma_dscrbase; /* Descriptor base address */
209 volatile void __iomem *sbdma_dscrcnt; /* Descriptor count register */
210 volatile void __iomem *sbdma_curdscr; /* current descriptor address */
211 volatile void __iomem *sbdma_oodpktlost;/* pkt drop (rx only) */
212
213
214 /*
215 * This stuff is for maintenance of the ring
216 */
217
218 sbdmadscr_t *sbdma_dscrtable_unaligned;
219 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */
220 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */
221
222 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */
223
224 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */
225 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */
226 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */
227 } sbmacdma_t;
228
229
230 /**********************************************************************
231 * Ethernet softc structure
232 ********************************************************************* */
233
234 struct sbmac_softc {
235
236 /*
237 * Linux-specific things
238 */
239
240 struct net_device *sbm_dev; /* pointer to linux device */
241 struct napi_struct napi;
242 spinlock_t sbm_lock; /* spin lock */
243 struct timer_list sbm_timer; /* for monitoring MII */
244 struct net_device_stats sbm_stats;
245 int sbm_devflags; /* current device flags */
246
247 int sbm_phy_oldbmsr;
248 int sbm_phy_oldanlpar;
249 int sbm_phy_oldk1stsr;
250 int sbm_phy_oldlinkstat;
251 int sbm_buffersize;
252
253 unsigned char sbm_phys[2];
254
255 /*
256 * Controller-specific things
257 */
258
259 void __iomem *sbm_base; /* MAC's base address */
260 sbmac_state_t sbm_state; /* current state */
261
262 volatile void __iomem *sbm_macenable; /* MAC Enable Register */
263 volatile void __iomem *sbm_maccfg; /* MAC Configuration Register */
264 volatile void __iomem *sbm_fifocfg; /* FIFO configuration register */
265 volatile void __iomem *sbm_framecfg; /* Frame configuration register */
266 volatile void __iomem *sbm_rxfilter; /* receive filter register */
267 volatile void __iomem *sbm_isr; /* Interrupt status register */
268 volatile void __iomem *sbm_imr; /* Interrupt mask register */
269 volatile void __iomem *sbm_mdio; /* MDIO register */
270
271 sbmac_speed_t sbm_speed; /* current speed */
272 sbmac_duplex_t sbm_duplex; /* current duplex */
273 sbmac_fc_t sbm_fc; /* current flow control setting */
274
275 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
276
277 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
278 sbmacdma_t sbm_rxdma;
279 int rx_hw_checksum;
280 int sbe_idx;
281 };
282
283
284 /**********************************************************************
285 * Externs
286 ********************************************************************* */
287
288 /**********************************************************************
289 * Prototypes
290 ********************************************************************* */
291
292 static void sbdma_initctx(sbmacdma_t *d,
293 struct sbmac_softc *s,
294 int chan,
295 int txrx,
296 int maxdescr);
297 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
298 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
299 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
300 static void sbdma_emptyring(sbmacdma_t *d);
301 static void sbdma_fillring(sbmacdma_t *d);
302 static int sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d, int work_to_do, int poll);
303 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d, int poll);
304 static int sbmac_initctx(struct sbmac_softc *s);
305 static void sbmac_channel_start(struct sbmac_softc *s);
306 static void sbmac_channel_stop(struct sbmac_softc *s);
307 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
308 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
309 static uint64_t sbmac_addr2reg(unsigned char *ptr);
310 static irqreturn_t sbmac_intr(int irq,void *dev_instance);
311 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
312 static void sbmac_setmulti(struct sbmac_softc *sc);
313 static int sbmac_init(struct net_device *dev, int idx);
314 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
315 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
316
317 static int sbmac_open(struct net_device *dev);
318 static void sbmac_timer(unsigned long data);
319 static void sbmac_tx_timeout (struct net_device *dev);
320 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
321 static void sbmac_set_rx_mode(struct net_device *dev);
322 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
323 static int sbmac_close(struct net_device *dev);
324 static int sbmac_poll(struct napi_struct *napi, int budget);
325
326 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
327 static int sbmac_mii_probe(struct net_device *dev);
328
329 static void sbmac_mii_sync(struct sbmac_softc *s);
330 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
331 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
332 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
333 unsigned int regval);
334
335
336 /**********************************************************************
337 * Globals
338 ********************************************************************* */
339
340 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
341
342
343 /**********************************************************************
344 * MDIO constants
345 ********************************************************************* */
346
347 #define MII_COMMAND_START 0x01
348 #define MII_COMMAND_READ 0x02
349 #define MII_COMMAND_WRITE 0x01
350 #define MII_COMMAND_ACK 0x02
351
352 #define BMCR_RESET 0x8000
353 #define BMCR_LOOPBACK 0x4000
354 #define BMCR_SPEED0 0x2000
355 #define BMCR_ANENABLE 0x1000
356 #define BMCR_POWERDOWN 0x0800
357 #define BMCR_ISOLATE 0x0400
358 #define BMCR_RESTARTAN 0x0200
359 #define BMCR_DUPLEX 0x0100
360 #define BMCR_COLTEST 0x0080
361 #define BMCR_SPEED1 0x0040
362 #define BMCR_SPEED1000 BMCR_SPEED1
363 #define BMCR_SPEED100 BMCR_SPEED0
364 #define BMCR_SPEED10 0
365
366 #define BMSR_100BT4 0x8000
367 #define BMSR_100BT_FDX 0x4000
368 #define BMSR_100BT_HDX 0x2000
369 #define BMSR_10BT_FDX 0x1000
370 #define BMSR_10BT_HDX 0x0800
371 #define BMSR_100BT2_FDX 0x0400
372 #define BMSR_100BT2_HDX 0x0200
373 #define BMSR_1000BT_XSR 0x0100
374 #define BMSR_PRESUP 0x0040
375 #define BMSR_ANCOMPLT 0x0020
376 #define BMSR_REMFAULT 0x0010
377 #define BMSR_AUTONEG 0x0008
378 #define BMSR_LINKSTAT 0x0004
379 #define BMSR_JABDETECT 0x0002
380 #define BMSR_EXTCAPAB 0x0001
381
382 #define PHYIDR1 0x2000
383 #define PHYIDR2 0x5C60
384
385 #define ANAR_NP 0x8000
386 #define ANAR_RF 0x2000
387 #define ANAR_ASYPAUSE 0x0800
388 #define ANAR_PAUSE 0x0400
389 #define ANAR_T4 0x0200
390 #define ANAR_TXFD 0x0100
391 #define ANAR_TXHD 0x0080
392 #define ANAR_10FD 0x0040
393 #define ANAR_10HD 0x0020
394 #define ANAR_PSB 0x0001
395
396 #define ANLPAR_NP 0x8000
397 #define ANLPAR_ACK 0x4000
398 #define ANLPAR_RF 0x2000
399 #define ANLPAR_ASYPAUSE 0x0800
400 #define ANLPAR_PAUSE 0x0400
401 #define ANLPAR_T4 0x0200
402 #define ANLPAR_TXFD 0x0100
403 #define ANLPAR_TXHD 0x0080
404 #define ANLPAR_10FD 0x0040
405 #define ANLPAR_10HD 0x0020
406 #define ANLPAR_PSB 0x0001 /* 802.3 */
407
408 #define ANER_PDF 0x0010
409 #define ANER_LPNPABLE 0x0008
410 #define ANER_NPABLE 0x0004
411 #define ANER_PAGERX 0x0002
412 #define ANER_LPANABLE 0x0001
413
414 #define ANNPTR_NP 0x8000
415 #define ANNPTR_MP 0x2000
416 #define ANNPTR_ACK2 0x1000
417 #define ANNPTR_TOGTX 0x0800
418 #define ANNPTR_CODE 0x0008
419
420 #define ANNPRR_NP 0x8000
421 #define ANNPRR_MP 0x2000
422 #define ANNPRR_ACK3 0x1000
423 #define ANNPRR_TOGTX 0x0800
424 #define ANNPRR_CODE 0x0008
425
426 #define K1TCR_TESTMODE 0x0000
427 #define K1TCR_MSMCE 0x1000
428 #define K1TCR_MSCV 0x0800
429 #define K1TCR_RPTR 0x0400
430 #define K1TCR_1000BT_FDX 0x200
431 #define K1TCR_1000BT_HDX 0x100
432
433 #define K1STSR_MSMCFLT 0x8000
434 #define K1STSR_MSCFGRES 0x4000
435 #define K1STSR_LRSTAT 0x2000
436 #define K1STSR_RRSTAT 0x1000
437 #define K1STSR_LP1KFD 0x0800
438 #define K1STSR_LP1KHD 0x0400
439 #define K1STSR_LPASMDIR 0x0200
440
441 #define K1SCR_1KX_FDX 0x8000
442 #define K1SCR_1KX_HDX 0x4000
443 #define K1SCR_1KT_FDX 0x2000
444 #define K1SCR_1KT_HDX 0x1000
445
446 #define STRAP_PHY1 0x0800
447 #define STRAP_NCMODE 0x0400
448 #define STRAP_MANMSCFG 0x0200
449 #define STRAP_ANENABLE 0x0100
450 #define STRAP_MSVAL 0x0080
451 #define STRAP_1KHDXADV 0x0010
452 #define STRAP_1KFDXADV 0x0008
453 #define STRAP_100ADV 0x0004
454 #define STRAP_SPEEDSEL 0x0000
455 #define STRAP_SPEED100 0x0001
456
457 #define PHYSUP_SPEED1000 0x10
458 #define PHYSUP_SPEED100 0x08
459 #define PHYSUP_SPEED10 0x00
460 #define PHYSUP_LINKUP 0x04
461 #define PHYSUP_FDX 0x02
462
463 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
464 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
465 #define MII_PHYIDR1 0x02
466 #define MII_PHYIDR2 0x03
467
468 #define MII_K1STSR 0x0A /* 1K Status Register (ro) */
469 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
470
471
472 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
473
474 #define ENABLE 1
475 #define DISABLE 0
476
477 /**********************************************************************
478 * SBMAC_MII_SYNC(s)
479 *
480 * Synchronize with the MII - send a pattern of bits to the MII
481 * that will guarantee that it is ready to accept a command.
482 *
483 * Input parameters:
484 * s - sbmac structure
485 *
486 * Return value:
487 * nothing
488 ********************************************************************* */
489
490 static void sbmac_mii_sync(struct sbmac_softc *s)
491 {
492 int cnt;
493 uint64_t bits;
494 int mac_mdio_genc;
495
496 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
497
498 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
499
500 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
501
502 for (cnt = 0; cnt < 32; cnt++) {
503 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
504 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
505 }
506 }
507
508 /**********************************************************************
509 * SBMAC_MII_SENDDATA(s,data,bitcnt)
510 *
511 * Send some bits to the MII. The bits to be sent are right-
512 * justified in the 'data' parameter.
513 *
514 * Input parameters:
515 * s - sbmac structure
516 * data - data to send
517 * bitcnt - number of bits to send
518 ********************************************************************* */
519
520 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
521 {
522 int i;
523 uint64_t bits;
524 unsigned int curmask;
525 int mac_mdio_genc;
526
527 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
528
529 bits = M_MAC_MDIO_DIR_OUTPUT;
530 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
531
532 curmask = 1 << (bitcnt - 1);
533
534 for (i = 0; i < bitcnt; i++) {
535 if (data & curmask)
536 bits |= M_MAC_MDIO_OUT;
537 else bits &= ~M_MAC_MDIO_OUT;
538 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
539 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
540 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
541 curmask >>= 1;
542 }
543 }
544
545
546
547 /**********************************************************************
548 * SBMAC_MII_READ(s,phyaddr,regidx)
549 *
550 * Read a PHY register.
551 *
552 * Input parameters:
553 * s - sbmac structure
554 * phyaddr - PHY's address
555 * regidx = index of register to read
556 *
557 * Return value:
558 * value read, or 0 if an error occurred.
559 ********************************************************************* */
560
561 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
562 {
563 int idx;
564 int error;
565 int regval;
566 int mac_mdio_genc;
567
568 /*
569 * Synchronize ourselves so that the PHY knows the next
570 * thing coming down is a command
571 */
572
573 sbmac_mii_sync(s);
574
575 /*
576 * Send the data to the PHY. The sequence is
577 * a "start" command (2 bits)
578 * a "read" command (2 bits)
579 * the PHY addr (5 bits)
580 * the register index (5 bits)
581 */
582
583 sbmac_mii_senddata(s,MII_COMMAND_START, 2);
584 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
585 sbmac_mii_senddata(s,phyaddr, 5);
586 sbmac_mii_senddata(s,regidx, 5);
587
588 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
589
590 /*
591 * Switch the port around without a clock transition.
592 */
593 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
594
595 /*
596 * Send out a clock pulse to signal we want the status
597 */
598
599 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
600 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
601
602 /*
603 * If an error occurred, the PHY will signal '1' back
604 */
605 error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
606
607 /*
608 * Issue an 'idle' clock pulse, but keep the direction
609 * the same.
610 */
611 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
612 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
613
614 regval = 0;
615
616 for (idx = 0; idx < 16; idx++) {
617 regval <<= 1;
618
619 if (error == 0) {
620 if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
621 regval |= 1;
622 }
623
624 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
625 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
626 }
627
628 /* Switch back to output */
629 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
630
631 if (error == 0)
632 return regval;
633 return 0;
634 }
635
636
637 /**********************************************************************
638 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
639 *
640 * Write a value to a PHY register.
641 *
642 * Input parameters:
643 * s - sbmac structure
644 * phyaddr - PHY to use
645 * regidx - register within the PHY
646 * regval - data to write to register
647 *
648 * Return value:
649 * nothing
650 ********************************************************************* */
651
652 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
653 unsigned int regval)
654 {
655 int mac_mdio_genc;
656
657 sbmac_mii_sync(s);
658
659 sbmac_mii_senddata(s,MII_COMMAND_START,2);
660 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
661 sbmac_mii_senddata(s,phyaddr, 5);
662 sbmac_mii_senddata(s,regidx, 5);
663 sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
664 sbmac_mii_senddata(s,regval,16);
665
666 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
667
668 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
669 }
670
671
672
673 /**********************************************************************
674 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
675 *
676 * Initialize a DMA channel context. Since there are potentially
677 * eight DMA channels per MAC, it's nice to do this in a standard
678 * way.
679 *
680 * Input parameters:
681 * d - sbmacdma_t structure (DMA channel context)
682 * s - sbmac_softc structure (pointer to a MAC)
683 * chan - channel number (0..1 right now)
684 * txrx - Identifies DMA_TX or DMA_RX for channel direction
685 * maxdescr - number of descriptors
686 *
687 * Return value:
688 * nothing
689 ********************************************************************* */
690
691 static void sbdma_initctx(sbmacdma_t *d,
692 struct sbmac_softc *s,
693 int chan,
694 int txrx,
695 int maxdescr)
696 {
697 #ifdef CONFIG_SBMAC_COALESCE
698 int int_pktcnt, int_timeout;
699 #endif
700
701 /*
702 * Save away interesting stuff in the structure
703 */
704
705 d->sbdma_eth = s;
706 d->sbdma_channel = chan;
707 d->sbdma_txdir = txrx;
708
709 #if 0
710 /* RMON clearing */
711 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
712 #endif
713
714 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
715 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
716 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
717 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
718 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
719 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
720 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
721 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
722 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
723 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
724 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
725 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
726 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
727 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
728 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
729 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
730 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
731 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
732 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
733 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
734 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
735
736 /*
737 * initialize register pointers
738 */
739
740 d->sbdma_config0 =
741 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
742 d->sbdma_config1 =
743 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
744 d->sbdma_dscrbase =
745 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
746 d->sbdma_dscrcnt =
747 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
748 d->sbdma_curdscr =
749 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
750 if (d->sbdma_txdir)
751 d->sbdma_oodpktlost = NULL;
752 else
753 d->sbdma_oodpktlost =
754 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
755
756 /*
757 * Allocate memory for the ring
758 */
759
760 d->sbdma_maxdescr = maxdescr;
761
762 d->sbdma_dscrtable_unaligned =
763 d->sbdma_dscrtable = (sbdmadscr_t *)
764 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
765
766 /*
767 * The descriptor table must be aligned to at least 16 bytes or the
768 * MAC will corrupt it.
769 */
770 d->sbdma_dscrtable = (sbdmadscr_t *)
771 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
772
773 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
774
775 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
776
777 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
778
779 /*
780 * And context table
781 */
782
783 d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
784 sizeof(struct sk_buff *), GFP_KERNEL);
785
786 #ifdef CONFIG_SBMAC_COALESCE
787 /*
788 * Setup Rx/Tx DMA coalescing defaults
789 */
790
791 int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
792 if ( int_pktcnt ) {
793 d->sbdma_int_pktcnt = int_pktcnt;
794 } else {
795 d->sbdma_int_pktcnt = 1;
796 }
797
798 int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
799 if ( int_timeout ) {
800 d->sbdma_int_timeout = int_timeout;
801 } else {
802 d->sbdma_int_timeout = 0;
803 }
804 #endif
805
806 }
807
808 /**********************************************************************
809 * SBDMA_CHANNEL_START(d)
810 *
811 * Initialize the hardware registers for a DMA channel.
812 *
813 * Input parameters:
814 * d - DMA channel to init (context must be previously init'd
815 * rxtx - DMA_RX or DMA_TX depending on what type of channel
816 *
817 * Return value:
818 * nothing
819 ********************************************************************* */
820
821 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
822 {
823 /*
824 * Turn on the DMA channel
825 */
826
827 #ifdef CONFIG_SBMAC_COALESCE
828 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
829 0, d->sbdma_config1);
830 __raw_writeq(M_DMA_EOP_INT_EN |
831 V_DMA_RINGSZ(d->sbdma_maxdescr) |
832 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
833 0, d->sbdma_config0);
834 #else
835 __raw_writeq(0, d->sbdma_config1);
836 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
837 0, d->sbdma_config0);
838 #endif
839
840 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
841
842 /*
843 * Initialize ring pointers
844 */
845
846 d->sbdma_addptr = d->sbdma_dscrtable;
847 d->sbdma_remptr = d->sbdma_dscrtable;
848 }
849
850 /**********************************************************************
851 * SBDMA_CHANNEL_STOP(d)
852 *
853 * Initialize the hardware registers for a DMA channel.
854 *
855 * Input parameters:
856 * d - DMA channel to init (context must be previously init'd
857 *
858 * Return value:
859 * nothing
860 ********************************************************************* */
861
862 static void sbdma_channel_stop(sbmacdma_t *d)
863 {
864 /*
865 * Turn off the DMA channel
866 */
867
868 __raw_writeq(0, d->sbdma_config1);
869
870 __raw_writeq(0, d->sbdma_dscrbase);
871
872 __raw_writeq(0, d->sbdma_config0);
873
874 /*
875 * Zero ring pointers
876 */
877
878 d->sbdma_addptr = NULL;
879 d->sbdma_remptr = NULL;
880 }
881
882 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
883 {
884 unsigned long addr;
885 unsigned long newaddr;
886
887 addr = (unsigned long) skb->data;
888
889 newaddr = (addr + power2 - 1) & ~(power2 - 1);
890
891 skb_reserve(skb,newaddr-addr+offset);
892 }
893
894
895 /**********************************************************************
896 * SBDMA_ADD_RCVBUFFER(d,sb)
897 *
898 * Add a buffer to the specified DMA channel. For receive channels,
899 * this queues a buffer for inbound packets.
900 *
901 * Input parameters:
902 * d - DMA channel descriptor
903 * sb - sk_buff to add, or NULL if we should allocate one
904 *
905 * Return value:
906 * 0 if buffer could not be added (ring is full)
907 * 1 if buffer added successfully
908 ********************************************************************* */
909
910
911 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
912 {
913 sbdmadscr_t *dsc;
914 sbdmadscr_t *nextdsc;
915 struct sk_buff *sb_new = NULL;
916 int pktsize = ENET_PACKET_SIZE;
917
918 /* get pointer to our current place in the ring */
919
920 dsc = d->sbdma_addptr;
921 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
922
923 /*
924 * figure out if the ring is full - if the next descriptor
925 * is the same as the one that we're going to remove from
926 * the ring, the ring is full
927 */
928
929 if (nextdsc == d->sbdma_remptr) {
930 return -ENOSPC;
931 }
932
933 /*
934 * Allocate a sk_buff if we don't already have one.
935 * If we do have an sk_buff, reset it so that it's empty.
936 *
937 * Note: sk_buffs don't seem to be guaranteed to have any sort
938 * of alignment when they are allocated. Therefore, allocate enough
939 * extra space to make sure that:
940 *
941 * 1. the data does not start in the middle of a cache line.
942 * 2. The data does not end in the middle of a cache line
943 * 3. The buffer can be aligned such that the IP addresses are
944 * naturally aligned.
945 *
946 * Remember, the SOCs MAC writes whole cache lines at a time,
947 * without reading the old contents first. So, if the sk_buff's
948 * data portion starts in the middle of a cache line, the SOC
949 * DMA will trash the beginning (and ending) portions.
950 */
951
952 if (sb == NULL) {
953 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
954 if (sb_new == NULL) {
955 printk(KERN_INFO "%s: sk_buff allocation failed\n",
956 d->sbdma_eth->sbm_dev->name);
957 return -ENOBUFS;
958 }
959
960 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
961 }
962 else {
963 sb_new = sb;
964 /*
965 * nothing special to reinit buffer, it's already aligned
966 * and sb->data already points to a good place.
967 */
968 }
969
970 /*
971 * fill in the descriptor
972 */
973
974 #ifdef CONFIG_SBMAC_COALESCE
975 /*
976 * Do not interrupt per DMA transfer.
977 */
978 dsc->dscr_a = virt_to_phys(sb_new->data) |
979 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
980 #else
981 dsc->dscr_a = virt_to_phys(sb_new->data) |
982 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
983 M_DMA_DSCRA_INTERRUPT;
984 #endif
985
986 /* receiving: no options */
987 dsc->dscr_b = 0;
988
989 /*
990 * fill in the context
991 */
992
993 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
994
995 /*
996 * point at next packet
997 */
998
999 d->sbdma_addptr = nextdsc;
1000
1001 /*
1002 * Give the buffer to the DMA engine.
1003 */
1004
1005 __raw_writeq(1, d->sbdma_dscrcnt);
1006
1007 return 0; /* we did it */
1008 }
1009
1010 /**********************************************************************
1011 * SBDMA_ADD_TXBUFFER(d,sb)
1012 *
1013 * Add a transmit buffer to the specified DMA channel, causing a
1014 * transmit to start.
1015 *
1016 * Input parameters:
1017 * d - DMA channel descriptor
1018 * sb - sk_buff to add
1019 *
1020 * Return value:
1021 * 0 transmit queued successfully
1022 * otherwise error code
1023 ********************************************************************* */
1024
1025
1026 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1027 {
1028 sbdmadscr_t *dsc;
1029 sbdmadscr_t *nextdsc;
1030 uint64_t phys;
1031 uint64_t ncb;
1032 int length;
1033
1034 /* get pointer to our current place in the ring */
1035
1036 dsc = d->sbdma_addptr;
1037 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1038
1039 /*
1040 * figure out if the ring is full - if the next descriptor
1041 * is the same as the one that we're going to remove from
1042 * the ring, the ring is full
1043 */
1044
1045 if (nextdsc == d->sbdma_remptr) {
1046 return -ENOSPC;
1047 }
1048
1049 /*
1050 * Under Linux, it's not necessary to copy/coalesce buffers
1051 * like it is on NetBSD. We think they're all contiguous,
1052 * but that may not be true for GBE.
1053 */
1054
1055 length = sb->len;
1056
1057 /*
1058 * fill in the descriptor. Note that the number of cache
1059 * blocks in the descriptor is the number of blocks
1060 * *spanned*, so we need to add in the offset (if any)
1061 * while doing the calculation.
1062 */
1063
1064 phys = virt_to_phys(sb->data);
1065 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1066
1067 dsc->dscr_a = phys |
1068 V_DMA_DSCRA_A_SIZE(ncb) |
1069 #ifndef CONFIG_SBMAC_COALESCE
1070 M_DMA_DSCRA_INTERRUPT |
1071 #endif
1072 M_DMA_ETHTX_SOP;
1073
1074 /* transmitting: set outbound options and length */
1075
1076 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1077 V_DMA_DSCRB_PKT_SIZE(length);
1078
1079 /*
1080 * fill in the context
1081 */
1082
1083 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1084
1085 /*
1086 * point at next packet
1087 */
1088
1089 d->sbdma_addptr = nextdsc;
1090
1091 /*
1092 * Give the buffer to the DMA engine.
1093 */
1094
1095 __raw_writeq(1, d->sbdma_dscrcnt);
1096
1097 return 0; /* we did it */
1098 }
1099
1100
1101
1102
1103 /**********************************************************************
1104 * SBDMA_EMPTYRING(d)
1105 *
1106 * Free all allocated sk_buffs on the specified DMA channel;
1107 *
1108 * Input parameters:
1109 * d - DMA channel
1110 *
1111 * Return value:
1112 * nothing
1113 ********************************************************************* */
1114
1115 static void sbdma_emptyring(sbmacdma_t *d)
1116 {
1117 int idx;
1118 struct sk_buff *sb;
1119
1120 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1121 sb = d->sbdma_ctxtable[idx];
1122 if (sb) {
1123 dev_kfree_skb(sb);
1124 d->sbdma_ctxtable[idx] = NULL;
1125 }
1126 }
1127 }
1128
1129
1130 /**********************************************************************
1131 * SBDMA_FILLRING(d)
1132 *
1133 * Fill the specified DMA channel (must be receive channel)
1134 * with sk_buffs
1135 *
1136 * Input parameters:
1137 * d - DMA channel
1138 *
1139 * Return value:
1140 * nothing
1141 ********************************************************************* */
1142
1143 static void sbdma_fillring(sbmacdma_t *d)
1144 {
1145 int idx;
1146
1147 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1148 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1149 break;
1150 }
1151 }
1152
1153 #ifdef CONFIG_NET_POLL_CONTROLLER
1154 static void sbmac_netpoll(struct net_device *netdev)
1155 {
1156 struct sbmac_softc *sc = netdev_priv(netdev);
1157 int irq = sc->sbm_dev->irq;
1158
1159 __raw_writeq(0, sc->sbm_imr);
1160
1161 sbmac_intr(irq, netdev);
1162
1163 #ifdef CONFIG_SBMAC_COALESCE
1164 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1165 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1166 sc->sbm_imr);
1167 #else
1168 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1169 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1170 #endif
1171 }
1172 #endif
1173
1174 /**********************************************************************
1175 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1176 *
1177 * Process "completed" receive buffers on the specified DMA channel.
1178 *
1179 * Input parameters:
1180 * sc - softc structure
1181 * d - DMA channel context
1182 * work_to_do - no. of packets to process before enabling interrupt
1183 * again (for NAPI)
1184 * poll - 1: using polling (for NAPI)
1185 *
1186 * Return value:
1187 * nothing
1188 ********************************************************************* */
1189
1190 static int sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d,
1191 int work_to_do, int poll)
1192 {
1193 int curidx;
1194 int hwidx;
1195 sbdmadscr_t *dsc;
1196 struct sk_buff *sb;
1197 int len;
1198 int work_done = 0;
1199 int dropped = 0;
1200
1201 prefetch(d);
1202
1203 again:
1204 /* Check if the HW dropped any frames */
1205 sc->sbm_stats.rx_fifo_errors
1206 += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1207 __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1208
1209 while (work_to_do-- > 0) {
1210 /*
1211 * figure out where we are (as an index) and where
1212 * the hardware is (also as an index)
1213 *
1214 * This could be done faster if (for example) the
1215 * descriptor table was page-aligned and contiguous in
1216 * both virtual and physical memory -- you could then
1217 * just compare the low-order bits of the virtual address
1218 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1219 */
1220
1221 dsc = d->sbdma_remptr;
1222 curidx = dsc - d->sbdma_dscrtable;
1223
1224 prefetch(dsc);
1225 prefetch(&d->sbdma_ctxtable[curidx]);
1226
1227 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1228 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1229
1230 /*
1231 * If they're the same, that means we've processed all
1232 * of the descriptors up to (but not including) the one that
1233 * the hardware is working on right now.
1234 */
1235
1236 if (curidx == hwidx)
1237 goto done;
1238
1239 /*
1240 * Otherwise, get the packet's sk_buff ptr back
1241 */
1242
1243 sb = d->sbdma_ctxtable[curidx];
1244 d->sbdma_ctxtable[curidx] = NULL;
1245
1246 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1247
1248 /*
1249 * Check packet status. If good, process it.
1250 * If not, silently drop it and put it back on the
1251 * receive ring.
1252 */
1253
1254 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1255
1256 /*
1257 * Add a new buffer to replace the old one. If we fail
1258 * to allocate a buffer, we're going to drop this
1259 * packet and put it right back on the receive ring.
1260 */
1261
1262 if (unlikely (sbdma_add_rcvbuffer(d,NULL) ==
1263 -ENOBUFS)) {
1264 sc->sbm_stats.rx_dropped++;
1265 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1266 /* No point in continuing at the moment */
1267 printk(KERN_ERR "dropped packet (1)\n");
1268 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1269 goto done;
1270 } else {
1271 /*
1272 * Set length into the packet
1273 */
1274 skb_put(sb,len);
1275
1276 /*
1277 * Buffer has been replaced on the
1278 * receive ring. Pass the buffer to
1279 * the kernel
1280 */
1281 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1282 /* Check hw IPv4/TCP checksum if supported */
1283 if (sc->rx_hw_checksum == ENABLE) {
1284 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1285 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1286 sb->ip_summed = CHECKSUM_UNNECESSARY;
1287 /* don't need to set sb->csum */
1288 } else {
1289 sb->ip_summed = CHECKSUM_NONE;
1290 }
1291 }
1292 prefetch(sb->data);
1293 prefetch((const void *)(((char *)sb->data)+32));
1294 if (poll)
1295 dropped = netif_receive_skb(sb);
1296 else
1297 dropped = netif_rx(sb);
1298
1299 if (dropped == NET_RX_DROP) {
1300 sc->sbm_stats.rx_dropped++;
1301 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1302 goto done;
1303 }
1304 else {
1305 sc->sbm_stats.rx_bytes += len;
1306 sc->sbm_stats.rx_packets++;
1307 }
1308 }
1309 } else {
1310 /*
1311 * Packet was mangled somehow. Just drop it and
1312 * put it back on the receive ring.
1313 */
1314 sc->sbm_stats.rx_errors++;
1315 sbdma_add_rcvbuffer(d,sb);
1316 }
1317
1318
1319 /*
1320 * .. and advance to the next buffer.
1321 */
1322
1323 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1324 work_done++;
1325 }
1326 if (!poll) {
1327 work_to_do = 32;
1328 goto again; /* collect fifo drop statistics again */
1329 }
1330 done:
1331 return work_done;
1332 }
1333
1334 /**********************************************************************
1335 * SBDMA_TX_PROCESS(sc,d)
1336 *
1337 * Process "completed" transmit buffers on the specified DMA channel.
1338 * This is normally called within the interrupt service routine.
1339 * Note that this isn't really ideal for priority channels, since
1340 * it processes all of the packets on a given channel before
1341 * returning.
1342 *
1343 * Input parameters:
1344 * sc - softc structure
1345 * d - DMA channel context
1346 * poll - 1: using polling (for NAPI)
1347 *
1348 * Return value:
1349 * nothing
1350 ********************************************************************* */
1351
1352 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d, int poll)
1353 {
1354 int curidx;
1355 int hwidx;
1356 sbdmadscr_t *dsc;
1357 struct sk_buff *sb;
1358 unsigned long flags;
1359 int packets_handled = 0;
1360
1361 spin_lock_irqsave(&(sc->sbm_lock), flags);
1362
1363 if (d->sbdma_remptr == d->sbdma_addptr)
1364 goto end_unlock;
1365
1366 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1367 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1368
1369 for (;;) {
1370 /*
1371 * figure out where we are (as an index) and where
1372 * the hardware is (also as an index)
1373 *
1374 * This could be done faster if (for example) the
1375 * descriptor table was page-aligned and contiguous in
1376 * both virtual and physical memory -- you could then
1377 * just compare the low-order bits of the virtual address
1378 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1379 */
1380
1381 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1382
1383 /*
1384 * If they're the same, that means we've processed all
1385 * of the descriptors up to (but not including) the one that
1386 * the hardware is working on right now.
1387 */
1388
1389 if (curidx == hwidx)
1390 break;
1391
1392 /*
1393 * Otherwise, get the packet's sk_buff ptr back
1394 */
1395
1396 dsc = &(d->sbdma_dscrtable[curidx]);
1397 sb = d->sbdma_ctxtable[curidx];
1398 d->sbdma_ctxtable[curidx] = NULL;
1399
1400 /*
1401 * Stats
1402 */
1403
1404 sc->sbm_stats.tx_bytes += sb->len;
1405 sc->sbm_stats.tx_packets++;
1406
1407 /*
1408 * for transmits, we just free buffers.
1409 */
1410
1411 dev_kfree_skb_irq(sb);
1412
1413 /*
1414 * .. and advance to the next buffer.
1415 */
1416
1417 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1418
1419 packets_handled++;
1420
1421 }
1422
1423 /*
1424 * Decide if we should wake up the protocol or not.
1425 * Other drivers seem to do this when we reach a low
1426 * watermark on the transmit queue.
1427 */
1428
1429 if (packets_handled)
1430 netif_wake_queue(d->sbdma_eth->sbm_dev);
1431
1432 end_unlock:
1433 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1434
1435 }
1436
1437
1438
1439 /**********************************************************************
1440 * SBMAC_INITCTX(s)
1441 *
1442 * Initialize an Ethernet context structure - this is called
1443 * once per MAC on the 1250. Memory is allocated here, so don't
1444 * call it again from inside the ioctl routines that bring the
1445 * interface up/down
1446 *
1447 * Input parameters:
1448 * s - sbmac context structure
1449 *
1450 * Return value:
1451 * 0
1452 ********************************************************************* */
1453
1454 static int sbmac_initctx(struct sbmac_softc *s)
1455 {
1456
1457 /*
1458 * figure out the addresses of some ports
1459 */
1460
1461 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1462 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1463 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1464 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1465 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1466 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1467 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1468 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1469
1470 s->sbm_phys[0] = 1;
1471 s->sbm_phys[1] = 0;
1472
1473 s->sbm_phy_oldbmsr = 0;
1474 s->sbm_phy_oldanlpar = 0;
1475 s->sbm_phy_oldk1stsr = 0;
1476 s->sbm_phy_oldlinkstat = 0;
1477
1478 /*
1479 * Initialize the DMA channels. Right now, only one per MAC is used
1480 * Note: Only do this _once_, as it allocates memory from the kernel!
1481 */
1482
1483 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1484 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1485
1486 /*
1487 * initial state is OFF
1488 */
1489
1490 s->sbm_state = sbmac_state_off;
1491
1492 /*
1493 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1494 */
1495
1496 s->sbm_speed = sbmac_speed_10;
1497 s->sbm_duplex = sbmac_duplex_half;
1498 s->sbm_fc = sbmac_fc_disabled;
1499
1500 return 0;
1501 }
1502
1503
1504 static void sbdma_uninitctx(struct sbmacdma_s *d)
1505 {
1506 if (d->sbdma_dscrtable_unaligned) {
1507 kfree(d->sbdma_dscrtable_unaligned);
1508 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1509 }
1510
1511 if (d->sbdma_ctxtable) {
1512 kfree(d->sbdma_ctxtable);
1513 d->sbdma_ctxtable = NULL;
1514 }
1515 }
1516
1517
1518 static void sbmac_uninitctx(struct sbmac_softc *sc)
1519 {
1520 sbdma_uninitctx(&(sc->sbm_txdma));
1521 sbdma_uninitctx(&(sc->sbm_rxdma));
1522 }
1523
1524
1525 /**********************************************************************
1526 * SBMAC_CHANNEL_START(s)
1527 *
1528 * Start packet processing on this MAC.
1529 *
1530 * Input parameters:
1531 * s - sbmac structure
1532 *
1533 * Return value:
1534 * nothing
1535 ********************************************************************* */
1536
1537 static void sbmac_channel_start(struct sbmac_softc *s)
1538 {
1539 uint64_t reg;
1540 volatile void __iomem *port;
1541 uint64_t cfg,fifo,framecfg;
1542 int idx, th_value;
1543
1544 /*
1545 * Don't do this if running
1546 */
1547
1548 if (s->sbm_state == sbmac_state_on)
1549 return;
1550
1551 /*
1552 * Bring the controller out of reset, but leave it off.
1553 */
1554
1555 __raw_writeq(0, s->sbm_macenable);
1556
1557 /*
1558 * Ignore all received packets
1559 */
1560
1561 __raw_writeq(0, s->sbm_rxfilter);
1562
1563 /*
1564 * Calculate values for various control registers.
1565 */
1566
1567 cfg = M_MAC_RETRY_EN |
1568 M_MAC_TX_HOLD_SOP_EN |
1569 V_MAC_TX_PAUSE_CNT_16K |
1570 M_MAC_AP_STAT_EN |
1571 M_MAC_FAST_SYNC |
1572 M_MAC_SS_EN |
1573 0;
1574
1575 /*
1576 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1577 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1578 * Use a larger RD_THRSH for gigabit
1579 */
1580 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1581 th_value = 28;
1582 else
1583 th_value = 64;
1584
1585 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1586 ((s->sbm_speed == sbmac_speed_1000)
1587 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1588 V_MAC_TX_RL_THRSH(4) |
1589 V_MAC_RX_PL_THRSH(4) |
1590 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1591 V_MAC_RX_PL_THRSH(4) |
1592 V_MAC_RX_RL_THRSH(8) |
1593 0;
1594
1595 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1596 V_MAC_MAX_FRAMESZ_DEFAULT |
1597 V_MAC_BACKOFF_SEL(1);
1598
1599 /*
1600 * Clear out the hash address map
1601 */
1602
1603 port = s->sbm_base + R_MAC_HASH_BASE;
1604 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1605 __raw_writeq(0, port);
1606 port += sizeof(uint64_t);
1607 }
1608
1609 /*
1610 * Clear out the exact-match table
1611 */
1612
1613 port = s->sbm_base + R_MAC_ADDR_BASE;
1614 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1615 __raw_writeq(0, port);
1616 port += sizeof(uint64_t);
1617 }
1618
1619 /*
1620 * Clear out the DMA Channel mapping table registers
1621 */
1622
1623 port = s->sbm_base + R_MAC_CHUP0_BASE;
1624 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1625 __raw_writeq(0, port);
1626 port += sizeof(uint64_t);
1627 }
1628
1629
1630 port = s->sbm_base + R_MAC_CHLO0_BASE;
1631 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1632 __raw_writeq(0, port);
1633 port += sizeof(uint64_t);
1634 }
1635
1636 /*
1637 * Program the hardware address. It goes into the hardware-address
1638 * register as well as the first filter register.
1639 */
1640
1641 reg = sbmac_addr2reg(s->sbm_hwaddr);
1642
1643 port = s->sbm_base + R_MAC_ADDR_BASE;
1644 __raw_writeq(reg, port);
1645 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1646
1647 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1648 /*
1649 * Pass1 SOCs do not receive packets addressed to the
1650 * destination address in the R_MAC_ETHERNET_ADDR register.
1651 * Set the value to zero.
1652 */
1653 __raw_writeq(0, port);
1654 #else
1655 __raw_writeq(reg, port);
1656 #endif
1657
1658 /*
1659 * Set the receive filter for no packets, and write values
1660 * to the various config registers
1661 */
1662
1663 __raw_writeq(0, s->sbm_rxfilter);
1664 __raw_writeq(0, s->sbm_imr);
1665 __raw_writeq(framecfg, s->sbm_framecfg);
1666 __raw_writeq(fifo, s->sbm_fifocfg);
1667 __raw_writeq(cfg, s->sbm_maccfg);
1668
1669 /*
1670 * Initialize DMA channels (rings should be ok now)
1671 */
1672
1673 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1674 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1675
1676 /*
1677 * Configure the speed, duplex, and flow control
1678 */
1679
1680 sbmac_set_speed(s,s->sbm_speed);
1681 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1682
1683 /*
1684 * Fill the receive ring
1685 */
1686
1687 sbdma_fillring(&(s->sbm_rxdma));
1688
1689 /*
1690 * Turn on the rest of the bits in the enable register
1691 */
1692
1693 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1694 __raw_writeq(M_MAC_RXDMA_EN0 |
1695 M_MAC_TXDMA_EN0, s->sbm_macenable);
1696 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1697 __raw_writeq(M_MAC_RXDMA_EN0 |
1698 M_MAC_TXDMA_EN0 |
1699 M_MAC_RX_ENABLE |
1700 M_MAC_TX_ENABLE, s->sbm_macenable);
1701 #else
1702 #error invalid SiByte MAC configuation
1703 #endif
1704
1705 #ifdef CONFIG_SBMAC_COALESCE
1706 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1707 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1708 #else
1709 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1710 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1711 #endif
1712
1713 /*
1714 * Enable receiving unicasts and broadcasts
1715 */
1716
1717 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1718
1719 /*
1720 * we're running now.
1721 */
1722
1723 s->sbm_state = sbmac_state_on;
1724
1725 /*
1726 * Program multicast addresses
1727 */
1728
1729 sbmac_setmulti(s);
1730
1731 /*
1732 * If channel was in promiscuous mode before, turn that on
1733 */
1734
1735 if (s->sbm_devflags & IFF_PROMISC) {
1736 sbmac_promiscuous_mode(s,1);
1737 }
1738
1739 }
1740
1741
1742 /**********************************************************************
1743 * SBMAC_CHANNEL_STOP(s)
1744 *
1745 * Stop packet processing on this MAC.
1746 *
1747 * Input parameters:
1748 * s - sbmac structure
1749 *
1750 * Return value:
1751 * nothing
1752 ********************************************************************* */
1753
1754 static void sbmac_channel_stop(struct sbmac_softc *s)
1755 {
1756 /* don't do this if already stopped */
1757
1758 if (s->sbm_state == sbmac_state_off)
1759 return;
1760
1761 /* don't accept any packets, disable all interrupts */
1762
1763 __raw_writeq(0, s->sbm_rxfilter);
1764 __raw_writeq(0, s->sbm_imr);
1765
1766 /* Turn off ticker */
1767
1768 /* XXX */
1769
1770 /* turn off receiver and transmitter */
1771
1772 __raw_writeq(0, s->sbm_macenable);
1773
1774 /* We're stopped now. */
1775
1776 s->sbm_state = sbmac_state_off;
1777
1778 /*
1779 * Stop DMA channels (rings should be ok now)
1780 */
1781
1782 sbdma_channel_stop(&(s->sbm_rxdma));
1783 sbdma_channel_stop(&(s->sbm_txdma));
1784
1785 /* Empty the receive and transmit rings */
1786
1787 sbdma_emptyring(&(s->sbm_rxdma));
1788 sbdma_emptyring(&(s->sbm_txdma));
1789
1790 }
1791
1792 /**********************************************************************
1793 * SBMAC_SET_CHANNEL_STATE(state)
1794 *
1795 * Set the channel's state ON or OFF
1796 *
1797 * Input parameters:
1798 * state - new state
1799 *
1800 * Return value:
1801 * old state
1802 ********************************************************************* */
1803 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1804 sbmac_state_t state)
1805 {
1806 sbmac_state_t oldstate = sc->sbm_state;
1807
1808 /*
1809 * If same as previous state, return
1810 */
1811
1812 if (state == oldstate) {
1813 return oldstate;
1814 }
1815
1816 /*
1817 * If new state is ON, turn channel on
1818 */
1819
1820 if (state == sbmac_state_on) {
1821 sbmac_channel_start(sc);
1822 }
1823 else {
1824 sbmac_channel_stop(sc);
1825 }
1826
1827 /*
1828 * Return previous state
1829 */
1830
1831 return oldstate;
1832 }
1833
1834
1835 /**********************************************************************
1836 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1837 *
1838 * Turn on or off promiscuous mode
1839 *
1840 * Input parameters:
1841 * sc - softc
1842 * onoff - 1 to turn on, 0 to turn off
1843 *
1844 * Return value:
1845 * nothing
1846 ********************************************************************* */
1847
1848 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1849 {
1850 uint64_t reg;
1851
1852 if (sc->sbm_state != sbmac_state_on)
1853 return;
1854
1855 if (onoff) {
1856 reg = __raw_readq(sc->sbm_rxfilter);
1857 reg |= M_MAC_ALLPKT_EN;
1858 __raw_writeq(reg, sc->sbm_rxfilter);
1859 }
1860 else {
1861 reg = __raw_readq(sc->sbm_rxfilter);
1862 reg &= ~M_MAC_ALLPKT_EN;
1863 __raw_writeq(reg, sc->sbm_rxfilter);
1864 }
1865 }
1866
1867 /**********************************************************************
1868 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1869 *
1870 * Set the iphdr offset as 15 assuming ethernet encapsulation
1871 *
1872 * Input parameters:
1873 * sc - softc
1874 *
1875 * Return value:
1876 * nothing
1877 ********************************************************************* */
1878
1879 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1880 {
1881 uint64_t reg;
1882
1883 /* Hard code the off set to 15 for now */
1884 reg = __raw_readq(sc->sbm_rxfilter);
1885 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1886 __raw_writeq(reg, sc->sbm_rxfilter);
1887
1888 /* BCM1250 pass1 didn't have hardware checksum. Everything
1889 later does. */
1890 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1891 sc->rx_hw_checksum = DISABLE;
1892 } else {
1893 sc->rx_hw_checksum = ENABLE;
1894 }
1895 }
1896
1897
1898 /**********************************************************************
1899 * SBMAC_ADDR2REG(ptr)
1900 *
1901 * Convert six bytes into the 64-bit register value that
1902 * we typically write into the SBMAC's address/mcast registers
1903 *
1904 * Input parameters:
1905 * ptr - pointer to 6 bytes
1906 *
1907 * Return value:
1908 * register value
1909 ********************************************************************* */
1910
1911 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1912 {
1913 uint64_t reg = 0;
1914
1915 ptr += 6;
1916
1917 reg |= (uint64_t) *(--ptr);
1918 reg <<= 8;
1919 reg |= (uint64_t) *(--ptr);
1920 reg <<= 8;
1921 reg |= (uint64_t) *(--ptr);
1922 reg <<= 8;
1923 reg |= (uint64_t) *(--ptr);
1924 reg <<= 8;
1925 reg |= (uint64_t) *(--ptr);
1926 reg <<= 8;
1927 reg |= (uint64_t) *(--ptr);
1928
1929 return reg;
1930 }
1931
1932
1933 /**********************************************************************
1934 * SBMAC_SET_SPEED(s,speed)
1935 *
1936 * Configure LAN speed for the specified MAC.
1937 * Warning: must be called when MAC is off!
1938 *
1939 * Input parameters:
1940 * s - sbmac structure
1941 * speed - speed to set MAC to (see sbmac_speed_t enum)
1942 *
1943 * Return value:
1944 * 1 if successful
1945 * 0 indicates invalid parameters
1946 ********************************************************************* */
1947
1948 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1949 {
1950 uint64_t cfg;
1951 uint64_t framecfg;
1952
1953 /*
1954 * Save new current values
1955 */
1956
1957 s->sbm_speed = speed;
1958
1959 if (s->sbm_state == sbmac_state_on)
1960 return 0; /* save for next restart */
1961
1962 /*
1963 * Read current register values
1964 */
1965
1966 cfg = __raw_readq(s->sbm_maccfg);
1967 framecfg = __raw_readq(s->sbm_framecfg);
1968
1969 /*
1970 * Mask out the stuff we want to change
1971 */
1972
1973 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1974 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1975 M_MAC_SLOT_SIZE);
1976
1977 /*
1978 * Now add in the new bits
1979 */
1980
1981 switch (speed) {
1982 case sbmac_speed_10:
1983 framecfg |= V_MAC_IFG_RX_10 |
1984 V_MAC_IFG_TX_10 |
1985 K_MAC_IFG_THRSH_10 |
1986 V_MAC_SLOT_SIZE_10;
1987 cfg |= V_MAC_SPEED_SEL_10MBPS;
1988 break;
1989
1990 case sbmac_speed_100:
1991 framecfg |= V_MAC_IFG_RX_100 |
1992 V_MAC_IFG_TX_100 |
1993 V_MAC_IFG_THRSH_100 |
1994 V_MAC_SLOT_SIZE_100;
1995 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1996 break;
1997
1998 case sbmac_speed_1000:
1999 framecfg |= V_MAC_IFG_RX_1000 |
2000 V_MAC_IFG_TX_1000 |
2001 V_MAC_IFG_THRSH_1000 |
2002 V_MAC_SLOT_SIZE_1000;
2003 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
2004 break;
2005
2006 case sbmac_speed_auto: /* XXX not implemented */
2007 /* fall through */
2008 default:
2009 return 0;
2010 }
2011
2012 /*
2013 * Send the bits back to the hardware
2014 */
2015
2016 __raw_writeq(framecfg, s->sbm_framecfg);
2017 __raw_writeq(cfg, s->sbm_maccfg);
2018
2019 return 1;
2020 }
2021
2022 /**********************************************************************
2023 * SBMAC_SET_DUPLEX(s,duplex,fc)
2024 *
2025 * Set Ethernet duplex and flow control options for this MAC
2026 * Warning: must be called when MAC is off!
2027 *
2028 * Input parameters:
2029 * s - sbmac structure
2030 * duplex - duplex setting (see sbmac_duplex_t)
2031 * fc - flow control setting (see sbmac_fc_t)
2032 *
2033 * Return value:
2034 * 1 if ok
2035 * 0 if an invalid parameter combination was specified
2036 ********************************************************************* */
2037
2038 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
2039 {
2040 uint64_t cfg;
2041
2042 /*
2043 * Save new current values
2044 */
2045
2046 s->sbm_duplex = duplex;
2047 s->sbm_fc = fc;
2048
2049 if (s->sbm_state == sbmac_state_on)
2050 return 0; /* save for next restart */
2051
2052 /*
2053 * Read current register values
2054 */
2055
2056 cfg = __raw_readq(s->sbm_maccfg);
2057
2058 /*
2059 * Mask off the stuff we're about to change
2060 */
2061
2062 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
2063
2064
2065 switch (duplex) {
2066 case sbmac_duplex_half:
2067 switch (fc) {
2068 case sbmac_fc_disabled:
2069 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2070 break;
2071
2072 case sbmac_fc_collision:
2073 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2074 break;
2075
2076 case sbmac_fc_carrier:
2077 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2078 break;
2079
2080 case sbmac_fc_auto: /* XXX not implemented */
2081 /* fall through */
2082 case sbmac_fc_frame: /* not valid in half duplex */
2083 default: /* invalid selection */
2084 return 0;
2085 }
2086 break;
2087
2088 case sbmac_duplex_full:
2089 switch (fc) {
2090 case sbmac_fc_disabled:
2091 cfg |= V_MAC_FC_CMD_DISABLED;
2092 break;
2093
2094 case sbmac_fc_frame:
2095 cfg |= V_MAC_FC_CMD_ENABLED;
2096 break;
2097
2098 case sbmac_fc_collision: /* not valid in full duplex */
2099 case sbmac_fc_carrier: /* not valid in full duplex */
2100 case sbmac_fc_auto: /* XXX not implemented */
2101 /* fall through */
2102 default:
2103 return 0;
2104 }
2105 break;
2106 case sbmac_duplex_auto:
2107 /* XXX not implemented */
2108 break;
2109 }
2110
2111 /*
2112 * Send the bits back to the hardware
2113 */
2114
2115 __raw_writeq(cfg, s->sbm_maccfg);
2116
2117 return 1;
2118 }
2119
2120
2121
2122
2123 /**********************************************************************
2124 * SBMAC_INTR()
2125 *
2126 * Interrupt handler for MAC interrupts
2127 *
2128 * Input parameters:
2129 * MAC structure
2130 *
2131 * Return value:
2132 * nothing
2133 ********************************************************************* */
2134 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
2135 {
2136 struct net_device *dev = (struct net_device *) dev_instance;
2137 struct sbmac_softc *sc = netdev_priv(dev);
2138 uint64_t isr;
2139 int handled = 0;
2140
2141 /*
2142 * Read the ISR (this clears the bits in the real
2143 * register, except for counter addr)
2144 */
2145
2146 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2147
2148 if (isr == 0)
2149 return IRQ_RETVAL(0);
2150 handled = 1;
2151
2152 /*
2153 * Transmits on channel 0
2154 */
2155
2156 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2157 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2158
2159 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2160 if (netif_rx_schedule_prep(dev, &sc->napi)) {
2161 __raw_writeq(0, sc->sbm_imr);
2162 __netif_rx_schedule(dev, &sc->napi);
2163 /* Depend on the exit from poll to reenable intr */
2164 }
2165 else {
2166 /* may leave some packets behind */
2167 sbdma_rx_process(sc,&(sc->sbm_rxdma),
2168 SBMAC_MAX_RXDESCR * 2, 0);
2169 }
2170 }
2171 return IRQ_RETVAL(handled);
2172 }
2173
2174 /**********************************************************************
2175 * SBMAC_START_TX(skb,dev)
2176 *
2177 * Start output on the specified interface. Basically, we
2178 * queue as many buffers as we can until the ring fills up, or
2179 * we run off the end of the queue, whichever comes first.
2180 *
2181 * Input parameters:
2182 *
2183 *
2184 * Return value:
2185 * nothing
2186 ********************************************************************* */
2187 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2188 {
2189 struct sbmac_softc *sc = netdev_priv(dev);
2190
2191 /* lock eth irq */
2192 spin_lock_irq (&sc->sbm_lock);
2193
2194 /*
2195 * Put the buffer on the transmit ring. If we
2196 * don't have room, stop the queue.
2197 */
2198
2199 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2200 /* XXX save skb that we could not send */
2201 netif_stop_queue(dev);
2202 spin_unlock_irq(&sc->sbm_lock);
2203
2204 return 1;
2205 }
2206
2207 dev->trans_start = jiffies;
2208
2209 spin_unlock_irq (&sc->sbm_lock);
2210
2211 return 0;
2212 }
2213
2214 /**********************************************************************
2215 * SBMAC_SETMULTI(sc)
2216 *
2217 * Reprogram the multicast table into the hardware, given
2218 * the list of multicasts associated with the interface
2219 * structure.
2220 *
2221 * Input parameters:
2222 * sc - softc
2223 *
2224 * Return value:
2225 * nothing
2226 ********************************************************************* */
2227
2228 static void sbmac_setmulti(struct sbmac_softc *sc)
2229 {
2230 uint64_t reg;
2231 volatile void __iomem *port;
2232 int idx;
2233 struct dev_mc_list *mclist;
2234 struct net_device *dev = sc->sbm_dev;
2235
2236 /*
2237 * Clear out entire multicast table. We do this by nuking
2238 * the entire hash table and all the direct matches except
2239 * the first one, which is used for our station address
2240 */
2241
2242 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2243 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2244 __raw_writeq(0, port);
2245 }
2246
2247 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2248 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2249 __raw_writeq(0, port);
2250 }
2251
2252 /*
2253 * Clear the filter to say we don't want any multicasts.
2254 */
2255
2256 reg = __raw_readq(sc->sbm_rxfilter);
2257 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2258 __raw_writeq(reg, sc->sbm_rxfilter);
2259
2260 if (dev->flags & IFF_ALLMULTI) {
2261 /*
2262 * Enable ALL multicasts. Do this by inverting the
2263 * multicast enable bit.
2264 */
2265 reg = __raw_readq(sc->sbm_rxfilter);
2266 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2267 __raw_writeq(reg, sc->sbm_rxfilter);
2268 return;
2269 }
2270
2271
2272 /*
2273 * Progam new multicast entries. For now, only use the
2274 * perfect filter. In the future we'll need to use the
2275 * hash filter if the perfect filter overflows
2276 */
2277
2278 /* XXX only using perfect filter for now, need to use hash
2279 * XXX if the table overflows */
2280
2281 idx = 1; /* skip station address */
2282 mclist = dev->mc_list;
2283 while (mclist && (idx < MAC_ADDR_COUNT)) {
2284 reg = sbmac_addr2reg(mclist->dmi_addr);
2285 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2286 __raw_writeq(reg, port);
2287 idx++;
2288 mclist = mclist->next;
2289 }
2290
2291 /*
2292 * Enable the "accept multicast bits" if we programmed at least one
2293 * multicast.
2294 */
2295
2296 if (idx > 1) {
2297 reg = __raw_readq(sc->sbm_rxfilter);
2298 reg |= M_MAC_MCAST_EN;
2299 __raw_writeq(reg, sc->sbm_rxfilter);
2300 }
2301 }
2302
2303 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2304 /**********************************************************************
2305 * SBMAC_PARSE_XDIGIT(str)
2306 *
2307 * Parse a hex digit, returning its value
2308 *
2309 * Input parameters:
2310 * str - character
2311 *
2312 * Return value:
2313 * hex value, or -1 if invalid
2314 ********************************************************************* */
2315
2316 static int sbmac_parse_xdigit(char str)
2317 {
2318 int digit;
2319
2320 if ((str >= '0') && (str <= '9'))
2321 digit = str - '0';
2322 else if ((str >= 'a') && (str <= 'f'))
2323 digit = str - 'a' + 10;
2324 else if ((str >= 'A') && (str <= 'F'))
2325 digit = str - 'A' + 10;
2326 else
2327 return -1;
2328
2329 return digit;
2330 }
2331
2332 /**********************************************************************
2333 * SBMAC_PARSE_HWADDR(str,hwaddr)
2334 *
2335 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2336 * Ethernet address.
2337 *
2338 * Input parameters:
2339 * str - string
2340 * hwaddr - pointer to hardware address
2341 *
2342 * Return value:
2343 * 0 if ok, else -1
2344 ********************************************************************* */
2345
2346 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2347 {
2348 int digit1,digit2;
2349 int idx = 6;
2350
2351 while (*str && (idx > 0)) {
2352 digit1 = sbmac_parse_xdigit(*str);
2353 if (digit1 < 0)
2354 return -1;
2355 str++;
2356 if (!*str)
2357 return -1;
2358
2359 if ((*str == ':') || (*str == '-')) {
2360 digit2 = digit1;
2361 digit1 = 0;
2362 }
2363 else {
2364 digit2 = sbmac_parse_xdigit(*str);
2365 if (digit2 < 0)
2366 return -1;
2367 str++;
2368 }
2369
2370 *hwaddr++ = (digit1 << 4) | digit2;
2371 idx--;
2372
2373 if (*str == '-')
2374 str++;
2375 if (*str == ':')
2376 str++;
2377 }
2378 return 0;
2379 }
2380 #endif
2381
2382 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2383 {
2384 if (new_mtu > ENET_PACKET_SIZE)
2385 return -EINVAL;
2386 _dev->mtu = new_mtu;
2387 printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2388 return 0;
2389 }
2390
2391 /**********************************************************************
2392 * SBMAC_INIT(dev)
2393 *
2394 * Attach routine - init hardware and hook ourselves into linux
2395 *
2396 * Input parameters:
2397 * dev - net_device structure
2398 *
2399 * Return value:
2400 * status
2401 ********************************************************************* */
2402
2403 static int sbmac_init(struct net_device *dev, int idx)
2404 {
2405 struct sbmac_softc *sc;
2406 unsigned char *eaddr;
2407 uint64_t ea_reg;
2408 int i;
2409 int err;
2410
2411 sc = netdev_priv(dev);
2412
2413 /* Determine controller base address */
2414
2415 sc->sbm_base = IOADDR(dev->base_addr);
2416 sc->sbm_dev = dev;
2417 sc->sbe_idx = idx;
2418
2419 eaddr = sc->sbm_hwaddr;
2420
2421 /*
2422 * Read the ethernet address. The firwmare left this programmed
2423 * for us in the ethernet address register for each mac.
2424 */
2425
2426 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2427 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2428 for (i = 0; i < 6; i++) {
2429 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2430 ea_reg >>= 8;
2431 }
2432
2433 for (i = 0; i < 6; i++) {
2434 dev->dev_addr[i] = eaddr[i];
2435 }
2436
2437
2438 /*
2439 * Init packet size
2440 */
2441
2442 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2443
2444 /*
2445 * Initialize context (get pointers to registers and stuff), then
2446 * allocate the memory for the descriptor tables.
2447 */
2448
2449 sbmac_initctx(sc);
2450
2451 /*
2452 * Set up Linux device callins
2453 */
2454
2455 spin_lock_init(&(sc->sbm_lock));
2456
2457 dev->open = sbmac_open;
2458 dev->hard_start_xmit = sbmac_start_tx;
2459 dev->stop = sbmac_close;
2460 dev->get_stats = sbmac_get_stats;
2461 dev->set_multicast_list = sbmac_set_rx_mode;
2462 dev->do_ioctl = sbmac_mii_ioctl;
2463 dev->tx_timeout = sbmac_tx_timeout;
2464 dev->watchdog_timeo = TX_TIMEOUT;
2465
2466 netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2467
2468 dev->change_mtu = sb1250_change_mtu;
2469 #ifdef CONFIG_NET_POLL_CONTROLLER
2470 dev->poll_controller = sbmac_netpoll;
2471 #endif
2472
2473 /* This is needed for PASS2 for Rx H/W checksum feature */
2474 sbmac_set_iphdr_offset(sc);
2475
2476 err = register_netdev(dev);
2477 if (err)
2478 goto out_uninit;
2479
2480 if (sc->rx_hw_checksum == ENABLE) {
2481 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2482 sc->sbm_dev->name);
2483 }
2484
2485 /*
2486 * Display Ethernet address (this is called during the config
2487 * process so we need to finish off the config message that
2488 * was being displayed)
2489 */
2490 printk(KERN_INFO
2491 "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2492 dev->name, dev->base_addr,
2493 eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2494
2495
2496 return 0;
2497
2498 out_uninit:
2499 sbmac_uninitctx(sc);
2500
2501 return err;
2502 }
2503
2504
2505 static int sbmac_open(struct net_device *dev)
2506 {
2507 struct sbmac_softc *sc = netdev_priv(dev);
2508
2509 if (debug > 1) {
2510 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2511 }
2512
2513 /*
2514 * map/route interrupt (clear status first, in case something
2515 * weird is pending; we haven't initialized the mac registers
2516 * yet)
2517 */
2518
2519 __raw_readq(sc->sbm_isr);
2520 if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev))
2521 return -EBUSY;
2522
2523 /*
2524 * Probe phy address
2525 */
2526
2527 if(sbmac_mii_probe(dev) == -1) {
2528 printk("%s: failed to probe PHY.\n", dev->name);
2529 return -EINVAL;
2530 }
2531
2532 napi_enable(&sc->napi);
2533
2534 /*
2535 * Configure default speed
2536 */
2537
2538 sbmac_mii_poll(sc,noisy_mii);
2539
2540 /*
2541 * Turn on the channel
2542 */
2543
2544 sbmac_set_channel_state(sc,sbmac_state_on);
2545
2546 /*
2547 * XXX Station address is in dev->dev_addr
2548 */
2549
2550 if (dev->if_port == 0)
2551 dev->if_port = 0;
2552
2553 netif_start_queue(dev);
2554
2555 sbmac_set_rx_mode(dev);
2556
2557 /* Set the timer to check for link beat. */
2558 init_timer(&sc->sbm_timer);
2559 sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2560 sc->sbm_timer.data = (unsigned long)dev;
2561 sc->sbm_timer.function = &sbmac_timer;
2562 add_timer(&sc->sbm_timer);
2563
2564 return 0;
2565 }
2566
2567 static int sbmac_mii_probe(struct net_device *dev)
2568 {
2569 int i;
2570 struct sbmac_softc *s = netdev_priv(dev);
2571 u16 bmsr, id1, id2;
2572 u32 vendor, device;
2573
2574 for (i=1; i<31; i++) {
2575 bmsr = sbmac_mii_read(s, i, MII_BMSR);
2576 if (bmsr != 0) {
2577 s->sbm_phys[0] = i;
2578 id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2579 id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2580 vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2581 device = (id2 >> 4) & 0x3f;
2582
2583 printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2584 dev->name, i, vendor, device);
2585 return i;
2586 }
2587 }
2588 return -1;
2589 }
2590
2591
2592 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2593 {
2594 int bmsr,bmcr,k1stsr,anlpar;
2595 int chg;
2596 char buffer[100];
2597 char *p = buffer;
2598
2599 /* Read the mode status and mode control registers. */
2600 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2601 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2602
2603 /* get the link partner status */
2604 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2605
2606 /* if supported, read the 1000baseT register */
2607 if (bmsr & BMSR_1000BT_XSR) {
2608 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2609 }
2610 else {
2611 k1stsr = 0;
2612 }
2613
2614 chg = 0;
2615
2616 if ((bmsr & BMSR_LINKSTAT) == 0) {
2617 /*
2618 * If link status is down, clear out old info so that when
2619 * it comes back up it will force us to reconfigure speed
2620 */
2621 s->sbm_phy_oldbmsr = 0;
2622 s->sbm_phy_oldanlpar = 0;
2623 s->sbm_phy_oldk1stsr = 0;
2624 return 0;
2625 }
2626
2627 if ((s->sbm_phy_oldbmsr != bmsr) ||
2628 (s->sbm_phy_oldanlpar != anlpar) ||
2629 (s->sbm_phy_oldk1stsr != k1stsr)) {
2630 if (debug > 1) {
2631 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2632 s->sbm_dev->name,
2633 s->sbm_phy_oldbmsr,bmsr,
2634 s->sbm_phy_oldanlpar,anlpar,
2635 s->sbm_phy_oldk1stsr,k1stsr);
2636 }
2637 s->sbm_phy_oldbmsr = bmsr;
2638 s->sbm_phy_oldanlpar = anlpar;
2639 s->sbm_phy_oldk1stsr = k1stsr;
2640 chg = 1;
2641 }
2642
2643 if (chg == 0)
2644 return 0;
2645
2646 p += sprintf(p,"Link speed: ");
2647
2648 if (k1stsr & K1STSR_LP1KFD) {
2649 s->sbm_speed = sbmac_speed_1000;
2650 s->sbm_duplex = sbmac_duplex_full;
2651 s->sbm_fc = sbmac_fc_frame;
2652 p += sprintf(p,"1000BaseT FDX");
2653 }
2654 else if (k1stsr & K1STSR_LP1KHD) {
2655 s->sbm_speed = sbmac_speed_1000;
2656 s->sbm_duplex = sbmac_duplex_half;
2657 s->sbm_fc = sbmac_fc_disabled;
2658 p += sprintf(p,"1000BaseT HDX");
2659 }
2660 else if (anlpar & ANLPAR_TXFD) {
2661 s->sbm_speed = sbmac_speed_100;
2662 s->sbm_duplex = sbmac_duplex_full;
2663 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2664 p += sprintf(p,"100BaseT FDX");
2665 }
2666 else if (anlpar & ANLPAR_TXHD) {
2667 s->sbm_speed = sbmac_speed_100;
2668 s->sbm_duplex = sbmac_duplex_half;
2669 s->sbm_fc = sbmac_fc_disabled;
2670 p += sprintf(p,"100BaseT HDX");
2671 }
2672 else if (anlpar & ANLPAR_10FD) {
2673 s->sbm_speed = sbmac_speed_10;
2674 s->sbm_duplex = sbmac_duplex_full;
2675 s->sbm_fc = sbmac_fc_frame;
2676 p += sprintf(p,"10BaseT FDX");
2677 }
2678 else if (anlpar & ANLPAR_10HD) {
2679 s->sbm_speed = sbmac_speed_10;
2680 s->sbm_duplex = sbmac_duplex_half;
2681 s->sbm_fc = sbmac_fc_collision;
2682 p += sprintf(p,"10BaseT HDX");
2683 }
2684 else {
2685 p += sprintf(p,"Unknown");
2686 }
2687
2688 if (noisy) {
2689 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2690 }
2691
2692 return 1;
2693 }
2694
2695
2696 static void sbmac_timer(unsigned long data)
2697 {
2698 struct net_device *dev = (struct net_device *)data;
2699 struct sbmac_softc *sc = netdev_priv(dev);
2700 int next_tick = HZ;
2701 int mii_status;
2702
2703 spin_lock_irq (&sc->sbm_lock);
2704
2705 /* make IFF_RUNNING follow the MII status bit "Link established" */
2706 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2707
2708 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2709 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2710 if (mii_status & BMSR_LINKSTAT) {
2711 netif_carrier_on(dev);
2712 }
2713 else {
2714 netif_carrier_off(dev);
2715 }
2716 }
2717
2718 /*
2719 * Poll the PHY to see what speed we should be running at
2720 */
2721
2722 if (sbmac_mii_poll(sc,noisy_mii)) {
2723 if (sc->sbm_state != sbmac_state_off) {
2724 /*
2725 * something changed, restart the channel
2726 */
2727 if (debug > 1) {
2728 printk("%s: restarting channel because speed changed\n",
2729 sc->sbm_dev->name);
2730 }
2731 sbmac_channel_stop(sc);
2732 sbmac_channel_start(sc);
2733 }
2734 }
2735
2736 spin_unlock_irq (&sc->sbm_lock);
2737
2738 sc->sbm_timer.expires = jiffies + next_tick;
2739 add_timer(&sc->sbm_timer);
2740 }
2741
2742
2743 static void sbmac_tx_timeout (struct net_device *dev)
2744 {
2745 struct sbmac_softc *sc = netdev_priv(dev);
2746
2747 spin_lock_irq (&sc->sbm_lock);
2748
2749
2750 dev->trans_start = jiffies;
2751 sc->sbm_stats.tx_errors++;
2752
2753 spin_unlock_irq (&sc->sbm_lock);
2754
2755 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2756 }
2757
2758
2759
2760
2761 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2762 {
2763 struct sbmac_softc *sc = netdev_priv(dev);
2764 unsigned long flags;
2765
2766 spin_lock_irqsave(&sc->sbm_lock, flags);
2767
2768 /* XXX update other stats here */
2769
2770 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2771
2772 return &sc->sbm_stats;
2773 }
2774
2775
2776
2777 static void sbmac_set_rx_mode(struct net_device *dev)
2778 {
2779 unsigned long flags;
2780 struct sbmac_softc *sc = netdev_priv(dev);
2781
2782 spin_lock_irqsave(&sc->sbm_lock, flags);
2783 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2784 /*
2785 * Promiscuous changed.
2786 */
2787
2788 if (dev->flags & IFF_PROMISC) {
2789 sbmac_promiscuous_mode(sc,1);
2790 }
2791 else {
2792 sbmac_promiscuous_mode(sc,0);
2793 }
2794 }
2795 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2796
2797 /*
2798 * Program the multicasts. Do this every time.
2799 */
2800
2801 sbmac_setmulti(sc);
2802
2803 }
2804
2805 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2806 {
2807 struct sbmac_softc *sc = netdev_priv(dev);
2808 u16 *data = (u16 *)&rq->ifr_ifru;
2809 unsigned long flags;
2810 int retval;
2811
2812 spin_lock_irqsave(&sc->sbm_lock, flags);
2813 retval = 0;
2814
2815 switch(cmd) {
2816 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2817 data[0] = sc->sbm_phys[0] & 0x1f;
2818 /* Fall Through */
2819 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2820 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2821 break;
2822 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2823 if (!capable(CAP_NET_ADMIN)) {
2824 retval = -EPERM;
2825 break;
2826 }
2827 if (debug > 1) {
2828 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2829 data[0],data[1],data[2]);
2830 }
2831 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2832 break;
2833 default:
2834 retval = -EOPNOTSUPP;
2835 }
2836
2837 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2838 return retval;
2839 }
2840
2841 static int sbmac_close(struct net_device *dev)
2842 {
2843 struct sbmac_softc *sc = netdev_priv(dev);
2844 unsigned long flags;
2845 int irq;
2846
2847 napi_disable(&sc->napi);
2848
2849 sbmac_set_channel_state(sc,sbmac_state_off);
2850
2851 del_timer_sync(&sc->sbm_timer);
2852
2853 spin_lock_irqsave(&sc->sbm_lock, flags);
2854
2855 netif_stop_queue(dev);
2856
2857 if (debug > 1) {
2858 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2859 }
2860
2861 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2862
2863 irq = dev->irq;
2864 synchronize_irq(irq);
2865 free_irq(irq, dev);
2866
2867 sbdma_emptyring(&(sc->sbm_txdma));
2868 sbdma_emptyring(&(sc->sbm_rxdma));
2869
2870 return 0;
2871 }
2872
2873 static int sbmac_poll(struct napi_struct *napi, int budget)
2874 {
2875 struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2876 struct net_device *dev = sc->sbm_dev;
2877 int work_done;
2878
2879 work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2880 sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2881
2882 if (work_done < budget) {
2883 netif_rx_complete(dev, napi);
2884
2885 #ifdef CONFIG_SBMAC_COALESCE
2886 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2887 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2888 sc->sbm_imr);
2889 #else
2890 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2891 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2892 #endif
2893 }
2894
2895 return work_done;
2896 }
2897
2898 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2899 static void
2900 sbmac_setup_hwaddr(int chan,char *addr)
2901 {
2902 uint8_t eaddr[6];
2903 uint64_t val;
2904 unsigned long port;
2905
2906 port = A_MAC_CHANNEL_BASE(chan);
2907 sbmac_parse_hwaddr(addr,eaddr);
2908 val = sbmac_addr2reg(eaddr);
2909 __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2910 val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2911 }
2912 #endif
2913
2914 static struct net_device *dev_sbmac[MAX_UNITS];
2915
2916 static int __init
2917 sbmac_init_module(void)
2918 {
2919 int idx;
2920 struct net_device *dev;
2921 unsigned long port;
2922 int chip_max_units;
2923
2924 /* Set the number of available units based on the SOC type. */
2925 switch (soc_type) {
2926 case K_SYS_SOC_TYPE_BCM1250:
2927 case K_SYS_SOC_TYPE_BCM1250_ALT:
2928 chip_max_units = 3;
2929 break;
2930 case K_SYS_SOC_TYPE_BCM1120:
2931 case K_SYS_SOC_TYPE_BCM1125:
2932 case K_SYS_SOC_TYPE_BCM1125H:
2933 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2934 chip_max_units = 2;
2935 break;
2936 case K_SYS_SOC_TYPE_BCM1x55:
2937 case K_SYS_SOC_TYPE_BCM1x80:
2938 chip_max_units = 4;
2939 break;
2940 default:
2941 chip_max_units = 0;
2942 break;
2943 }
2944 if (chip_max_units > MAX_UNITS)
2945 chip_max_units = MAX_UNITS;
2946
2947 /*
2948 * For bringup when not using the firmware, we can pre-fill
2949 * the MAC addresses using the environment variables
2950 * specified in this file (or maybe from the config file?)
2951 */
2952 #ifdef SBMAC_ETH0_HWADDR
2953 if (chip_max_units > 0)
2954 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2955 #endif
2956 #ifdef SBMAC_ETH1_HWADDR
2957 if (chip_max_units > 1)
2958 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2959 #endif
2960 #ifdef SBMAC_ETH2_HWADDR
2961 if (chip_max_units > 2)
2962 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2963 #endif
2964 #ifdef SBMAC_ETH3_HWADDR
2965 if (chip_max_units > 3)
2966 sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
2967 #endif
2968
2969 /*
2970 * Walk through the Ethernet controllers and find
2971 * those who have their MAC addresses set.
2972 */
2973 for (idx = 0; idx < chip_max_units; idx++) {
2974
2975 /*
2976 * This is the base address of the MAC.
2977 */
2978
2979 port = A_MAC_CHANNEL_BASE(idx);
2980
2981 /*
2982 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2983 * value for us by the firmware if we are going to use this MAC.
2984 * If we find a zero, skip this MAC.
2985 */
2986
2987 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2988 if (sbmac_orig_hwaddr[idx] == 0) {
2989 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2990 "%lx\n", port);
2991 continue;
2992 }
2993
2994 /*
2995 * Okay, cool. Initialize this MAC.
2996 */
2997
2998 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2999 if (!dev)
3000 return -ENOMEM;
3001
3002 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
3003
3004 dev->irq = UNIT_INT(idx);
3005 dev->base_addr = port;
3006 dev->mem_end = 0;
3007 if (sbmac_init(dev, idx)) {
3008 port = A_MAC_CHANNEL_BASE(idx);
3009 __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
3010 free_netdev(dev);
3011 continue;
3012 }
3013 dev_sbmac[idx] = dev;
3014 }
3015 return 0;
3016 }
3017
3018
3019 static void __exit
3020 sbmac_cleanup_module(void)
3021 {
3022 struct net_device *dev;
3023 int idx;
3024
3025 for (idx = 0; idx < MAX_UNITS; idx++) {
3026 struct sbmac_softc *sc;
3027 dev = dev_sbmac[idx];
3028 if (!dev)
3029 continue;
3030
3031 sc = netdev_priv(dev);
3032 unregister_netdev(dev);
3033 sbmac_uninitctx(sc);
3034 free_netdev(dev);
3035 }
3036 }
3037
3038 module_init(sbmac_init_module);
3039 module_exit(sbmac_cleanup_module);
Linux kernel - Deliverables
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