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sfc: Rename register I/O header and functions used by both Falcon and Siena
[deliverable/linux.git] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "falcon.h"
25 #include "regs.h"
26 #include "io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "workarounds.h"
30
31 /* Falcon hardware control.
32 * Falcon is the internal codename for the SFC4000 controller that is
33 * present in SFE400X evaluation boards
34 */
35
36 /**
37 * struct falcon_nic_data - Falcon NIC state
38 * @next_buffer_table: First available buffer table id
39 * @pci_dev2: The secondary PCI device if present
40 * @i2c_data: Operations and state for I2C bit-bashing algorithm
41 * @int_error_count: Number of internal errors seen recently
42 * @int_error_expire: Time at which error count will be expired
43 */
44 struct falcon_nic_data {
45 unsigned next_buffer_table;
46 struct pci_dev *pci_dev2;
47 struct i2c_algo_bit_data i2c_data;
48
49 unsigned int_error_count;
50 unsigned long int_error_expire;
51 };
52
53 /**************************************************************************
54 *
55 * Configurable values
56 *
57 **************************************************************************
58 */
59
60 static int disable_dma_stats;
61
62 /* This is set to 16 for a good reason. In summary, if larger than
63 * 16, the descriptor cache holds more than a default socket
64 * buffer's worth of packets (for UDP we can only have at most one
65 * socket buffer's worth outstanding). This combined with the fact
66 * that we only get 1 TX event per descriptor cache means the NIC
67 * goes idle.
68 */
69 #define TX_DC_ENTRIES 16
70 #define TX_DC_ENTRIES_ORDER 0
71 #define TX_DC_BASE 0x130000
72
73 #define RX_DC_ENTRIES 64
74 #define RX_DC_ENTRIES_ORDER 2
75 #define RX_DC_BASE 0x100000
76
77 static const unsigned int
78 /* "Large" EEPROM device: Atmel AT25640 or similar
79 * 8 KB, 16-bit address, 32 B write block */
80 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
81 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
82 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
83 /* Default flash device: Atmel AT25F1024
84 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
85 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
86 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
87 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
88 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
89 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
90
91 /* RX FIFO XOFF watermark
92 *
93 * When the amount of the RX FIFO increases used increases past this
94 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
95 * This also has an effect on RX/TX arbitration
96 */
97 static int rx_xoff_thresh_bytes = -1;
98 module_param(rx_xoff_thresh_bytes, int, 0644);
99 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
100
101 /* RX FIFO XON watermark
102 *
103 * When the amount of the RX FIFO used decreases below this
104 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
105 * This also has an effect on RX/TX arbitration
106 */
107 static int rx_xon_thresh_bytes = -1;
108 module_param(rx_xon_thresh_bytes, int, 0644);
109 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
110
111 /* TX descriptor ring size - min 512 max 4k */
112 #define FALCON_TXD_RING_ORDER FFE_AZ_TX_DESCQ_SIZE_1K
113 #define FALCON_TXD_RING_SIZE 1024
114 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
115
116 /* RX descriptor ring size - min 512 max 4k */
117 #define FALCON_RXD_RING_ORDER FFE_AZ_RX_DESCQ_SIZE_1K
118 #define FALCON_RXD_RING_SIZE 1024
119 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
120
121 /* Event queue size - max 32k */
122 #define FALCON_EVQ_ORDER FFE_AZ_EVQ_SIZE_4K
123 #define FALCON_EVQ_SIZE 4096
124 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
125
126 /* If FALCON_MAX_INT_ERRORS internal errors occur within
127 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
128 * disable it.
129 */
130 #define FALCON_INT_ERROR_EXPIRE 3600
131 #define FALCON_MAX_INT_ERRORS 5
132
133 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
134 */
135 #define FALCON_FLUSH_INTERVAL 10
136 #define FALCON_FLUSH_POLL_COUNT 100
137
138 /**************************************************************************
139 *
140 * Falcon constants
141 *
142 **************************************************************************
143 */
144
145 /* DMA address mask */
146 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
147
148 /* TX DMA length mask (13-bit) */
149 #define FALCON_TX_DMA_MASK (4096 - 1)
150
151 /* Size and alignment of special buffers (4KB) */
152 #define FALCON_BUF_SIZE 4096
153
154 /* Dummy SRAM size code */
155 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
156
157 #define FALCON_IS_DUAL_FUNC(efx) \
158 (falcon_rev(efx) < FALCON_REV_B0)
159
160 /**************************************************************************
161 *
162 * Falcon hardware access
163 *
164 **************************************************************************/
165
166 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
167 unsigned int index)
168 {
169 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
170 value, index);
171 }
172
173 /* Read the current event from the event queue */
174 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
175 unsigned int index)
176 {
177 return (((efx_qword_t *) (channel->eventq.addr)) + index);
178 }
179
180 /* See if an event is present
181 *
182 * We check both the high and low dword of the event for all ones. We
183 * wrote all ones when we cleared the event, and no valid event can
184 * have all ones in either its high or low dwords. This approach is
185 * robust against reordering.
186 *
187 * Note that using a single 64-bit comparison is incorrect; even
188 * though the CPU read will be atomic, the DMA write may not be.
189 */
190 static inline int falcon_event_present(efx_qword_t *event)
191 {
192 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
193 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
194 }
195
196 /**************************************************************************
197 *
198 * I2C bus - this is a bit-bashing interface using GPIO pins
199 * Note that it uses the output enables to tristate the outputs
200 * SDA is the data pin and SCL is the clock
201 *
202 **************************************************************************
203 */
204 static void falcon_setsda(void *data, int state)
205 {
206 struct efx_nic *efx = (struct efx_nic *)data;
207 efx_oword_t reg;
208
209 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
210 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
211 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
212 }
213
214 static void falcon_setscl(void *data, int state)
215 {
216 struct efx_nic *efx = (struct efx_nic *)data;
217 efx_oword_t reg;
218
219 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
220 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
221 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
222 }
223
224 static int falcon_getsda(void *data)
225 {
226 struct efx_nic *efx = (struct efx_nic *)data;
227 efx_oword_t reg;
228
229 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
230 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
231 }
232
233 static int falcon_getscl(void *data)
234 {
235 struct efx_nic *efx = (struct efx_nic *)data;
236 efx_oword_t reg;
237
238 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
239 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
240 }
241
242 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
243 .setsda = falcon_setsda,
244 .setscl = falcon_setscl,
245 .getsda = falcon_getsda,
246 .getscl = falcon_getscl,
247 .udelay = 5,
248 /* Wait up to 50 ms for slave to let us pull SCL high */
249 .timeout = DIV_ROUND_UP(HZ, 20),
250 };
251
252 /**************************************************************************
253 *
254 * Falcon special buffer handling
255 * Special buffers are used for event queues and the TX and RX
256 * descriptor rings.
257 *
258 *************************************************************************/
259
260 /*
261 * Initialise a Falcon special buffer
262 *
263 * This will define a buffer (previously allocated via
264 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
265 * it to be used for event queues, descriptor rings etc.
266 */
267 static void
268 falcon_init_special_buffer(struct efx_nic *efx,
269 struct efx_special_buffer *buffer)
270 {
271 efx_qword_t buf_desc;
272 int index;
273 dma_addr_t dma_addr;
274 int i;
275
276 EFX_BUG_ON_PARANOID(!buffer->addr);
277
278 /* Write buffer descriptors to NIC */
279 for (i = 0; i < buffer->entries; i++) {
280 index = buffer->index + i;
281 dma_addr = buffer->dma_addr + (i * 4096);
282 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
283 index, (unsigned long long)dma_addr);
284 EFX_POPULATE_QWORD_3(buf_desc,
285 FRF_AZ_BUF_ADR_REGION, 0,
286 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
287 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
288 falcon_write_buf_tbl(efx, &buf_desc, index);
289 }
290 }
291
292 /* Unmaps a buffer from Falcon and clears the buffer table entries */
293 static void
294 falcon_fini_special_buffer(struct efx_nic *efx,
295 struct efx_special_buffer *buffer)
296 {
297 efx_oword_t buf_tbl_upd;
298 unsigned int start = buffer->index;
299 unsigned int end = (buffer->index + buffer->entries - 1);
300
301 if (!buffer->entries)
302 return;
303
304 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
305 buffer->index, buffer->index + buffer->entries - 1);
306
307 EFX_POPULATE_OWORD_4(buf_tbl_upd,
308 FRF_AZ_BUF_UPD_CMD, 0,
309 FRF_AZ_BUF_CLR_CMD, 1,
310 FRF_AZ_BUF_CLR_END_ID, end,
311 FRF_AZ_BUF_CLR_START_ID, start);
312 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
313 }
314
315 /*
316 * Allocate a new Falcon special buffer
317 *
318 * This allocates memory for a new buffer, clears it and allocates a
319 * new buffer ID range. It does not write into Falcon's buffer table.
320 *
321 * This call will allocate 4KB buffers, since Falcon can't use 8KB
322 * buffers for event queues and descriptor rings.
323 */
324 static int falcon_alloc_special_buffer(struct efx_nic *efx,
325 struct efx_special_buffer *buffer,
326 unsigned int len)
327 {
328 struct falcon_nic_data *nic_data = efx->nic_data;
329
330 len = ALIGN(len, FALCON_BUF_SIZE);
331
332 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
333 &buffer->dma_addr);
334 if (!buffer->addr)
335 return -ENOMEM;
336 buffer->len = len;
337 buffer->entries = len / FALCON_BUF_SIZE;
338 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
339
340 /* All zeros is a potentially valid event so memset to 0xff */
341 memset(buffer->addr, 0xff, len);
342
343 /* Select new buffer ID */
344 buffer->index = nic_data->next_buffer_table;
345 nic_data->next_buffer_table += buffer->entries;
346
347 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
348 "(virt %p phys %llx)\n", buffer->index,
349 buffer->index + buffer->entries - 1,
350 (u64)buffer->dma_addr, len,
351 buffer->addr, (u64)virt_to_phys(buffer->addr));
352
353 return 0;
354 }
355
356 static void falcon_free_special_buffer(struct efx_nic *efx,
357 struct efx_special_buffer *buffer)
358 {
359 if (!buffer->addr)
360 return;
361
362 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
363 "(virt %p phys %llx)\n", buffer->index,
364 buffer->index + buffer->entries - 1,
365 (u64)buffer->dma_addr, buffer->len,
366 buffer->addr, (u64)virt_to_phys(buffer->addr));
367
368 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
369 buffer->dma_addr);
370 buffer->addr = NULL;
371 buffer->entries = 0;
372 }
373
374 /**************************************************************************
375 *
376 * Falcon generic buffer handling
377 * These buffers are used for interrupt status and MAC stats
378 *
379 **************************************************************************/
380
381 static int falcon_alloc_buffer(struct efx_nic *efx,
382 struct efx_buffer *buffer, unsigned int len)
383 {
384 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
385 &buffer->dma_addr);
386 if (!buffer->addr)
387 return -ENOMEM;
388 buffer->len = len;
389 memset(buffer->addr, 0, len);
390 return 0;
391 }
392
393 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
394 {
395 if (buffer->addr) {
396 pci_free_consistent(efx->pci_dev, buffer->len,
397 buffer->addr, buffer->dma_addr);
398 buffer->addr = NULL;
399 }
400 }
401
402 /**************************************************************************
403 *
404 * Falcon TX path
405 *
406 **************************************************************************/
407
408 /* Returns a pointer to the specified transmit descriptor in the TX
409 * descriptor queue belonging to the specified channel.
410 */
411 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
412 unsigned int index)
413 {
414 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
415 }
416
417 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
418 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
419 {
420 unsigned write_ptr;
421 efx_dword_t reg;
422
423 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
424 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
425 efx_writed_page(tx_queue->efx, &reg,
426 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
427 }
428
429
430 /* For each entry inserted into the software descriptor ring, create a
431 * descriptor in the hardware TX descriptor ring (in host memory), and
432 * write a doorbell.
433 */
434 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
435 {
436
437 struct efx_tx_buffer *buffer;
438 efx_qword_t *txd;
439 unsigned write_ptr;
440
441 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
442
443 do {
444 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
445 buffer = &tx_queue->buffer[write_ptr];
446 txd = falcon_tx_desc(tx_queue, write_ptr);
447 ++tx_queue->write_count;
448
449 /* Create TX descriptor ring entry */
450 EFX_POPULATE_QWORD_4(*txd,
451 FSF_AZ_TX_KER_CONT, buffer->continuation,
452 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
453 FSF_AZ_TX_KER_BUF_REGION, 0,
454 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
455 } while (tx_queue->write_count != tx_queue->insert_count);
456
457 wmb(); /* Ensure descriptors are written before they are fetched */
458 falcon_notify_tx_desc(tx_queue);
459 }
460
461 /* Allocate hardware resources for a TX queue */
462 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
463 {
464 struct efx_nic *efx = tx_queue->efx;
465 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
466 FALCON_TXD_RING_SIZE *
467 sizeof(efx_qword_t));
468 }
469
470 void falcon_init_tx(struct efx_tx_queue *tx_queue)
471 {
472 efx_oword_t tx_desc_ptr;
473 struct efx_nic *efx = tx_queue->efx;
474
475 tx_queue->flushed = false;
476
477 /* Pin TX descriptor ring */
478 falcon_init_special_buffer(efx, &tx_queue->txd);
479
480 /* Push TX descriptor ring to card */
481 EFX_POPULATE_OWORD_10(tx_desc_ptr,
482 FRF_AZ_TX_DESCQ_EN, 1,
483 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
484 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
485 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
486 FRF_AZ_TX_DESCQ_EVQ_ID,
487 tx_queue->channel->channel,
488 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
489 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
490 FRF_AZ_TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
491 FRF_AZ_TX_DESCQ_TYPE, 0,
492 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
493
494 if (falcon_rev(efx) >= FALCON_REV_B0) {
495 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
496 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
497 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
498 !csum);
499 }
500
501 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
502 tx_queue->queue);
503
504 if (falcon_rev(efx) < FALCON_REV_B0) {
505 efx_oword_t reg;
506
507 /* Only 128 bits in this register */
508 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
509
510 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
511 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
512 clear_bit_le(tx_queue->queue, (void *)&reg);
513 else
514 set_bit_le(tx_queue->queue, (void *)&reg);
515 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
516 }
517 }
518
519 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
520 {
521 struct efx_nic *efx = tx_queue->efx;
522 efx_oword_t tx_flush_descq;
523
524 /* Post a flush command */
525 EFX_POPULATE_OWORD_2(tx_flush_descq,
526 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
527 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
528 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
529 }
530
531 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
532 {
533 struct efx_nic *efx = tx_queue->efx;
534 efx_oword_t tx_desc_ptr;
535
536 /* The queue should have been flushed */
537 WARN_ON(!tx_queue->flushed);
538
539 /* Remove TX descriptor ring from card */
540 EFX_ZERO_OWORD(tx_desc_ptr);
541 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
542 tx_queue->queue);
543
544 /* Unpin TX descriptor ring */
545 falcon_fini_special_buffer(efx, &tx_queue->txd);
546 }
547
548 /* Free buffers backing TX queue */
549 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
550 {
551 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
552 }
553
554 /**************************************************************************
555 *
556 * Falcon RX path
557 *
558 **************************************************************************/
559
560 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
561 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
562 unsigned int index)
563 {
564 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
565 }
566
567 /* This creates an entry in the RX descriptor queue */
568 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
569 unsigned index)
570 {
571 struct efx_rx_buffer *rx_buf;
572 efx_qword_t *rxd;
573
574 rxd = falcon_rx_desc(rx_queue, index);
575 rx_buf = efx_rx_buffer(rx_queue, index);
576 EFX_POPULATE_QWORD_3(*rxd,
577 FSF_AZ_RX_KER_BUF_SIZE,
578 rx_buf->len -
579 rx_queue->efx->type->rx_buffer_padding,
580 FSF_AZ_RX_KER_BUF_REGION, 0,
581 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
582 }
583
584 /* This writes to the RX_DESC_WPTR register for the specified receive
585 * descriptor ring.
586 */
587 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
588 {
589 efx_dword_t reg;
590 unsigned write_ptr;
591
592 while (rx_queue->notified_count != rx_queue->added_count) {
593 falcon_build_rx_desc(rx_queue,
594 rx_queue->notified_count &
595 FALCON_RXD_RING_MASK);
596 ++rx_queue->notified_count;
597 }
598
599 wmb();
600 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
601 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
602 efx_writed_page(rx_queue->efx, &reg,
603 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
604 }
605
606 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
607 {
608 struct efx_nic *efx = rx_queue->efx;
609 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
610 FALCON_RXD_RING_SIZE *
611 sizeof(efx_qword_t));
612 }
613
614 void falcon_init_rx(struct efx_rx_queue *rx_queue)
615 {
616 efx_oword_t rx_desc_ptr;
617 struct efx_nic *efx = rx_queue->efx;
618 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
619 bool iscsi_digest_en = is_b0;
620
621 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
622 rx_queue->queue, rx_queue->rxd.index,
623 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
624
625 rx_queue->flushed = false;
626
627 /* Pin RX descriptor ring */
628 falcon_init_special_buffer(efx, &rx_queue->rxd);
629
630 /* Push RX descriptor ring to card */
631 EFX_POPULATE_OWORD_10(rx_desc_ptr,
632 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
633 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
634 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
635 FRF_AZ_RX_DESCQ_EVQ_ID,
636 rx_queue->channel->channel,
637 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
638 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
639 FRF_AZ_RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
640 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
641 /* For >=B0 this is scatter so disable */
642 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
643 FRF_AZ_RX_DESCQ_EN, 1);
644 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
645 rx_queue->queue);
646 }
647
648 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
649 {
650 struct efx_nic *efx = rx_queue->efx;
651 efx_oword_t rx_flush_descq;
652
653 /* Post a flush command */
654 EFX_POPULATE_OWORD_2(rx_flush_descq,
655 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
656 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
657 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
658 }
659
660 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
661 {
662 efx_oword_t rx_desc_ptr;
663 struct efx_nic *efx = rx_queue->efx;
664
665 /* The queue should already have been flushed */
666 WARN_ON(!rx_queue->flushed);
667
668 /* Remove RX descriptor ring from card */
669 EFX_ZERO_OWORD(rx_desc_ptr);
670 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
671 rx_queue->queue);
672
673 /* Unpin RX descriptor ring */
674 falcon_fini_special_buffer(efx, &rx_queue->rxd);
675 }
676
677 /* Free buffers backing RX queue */
678 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
679 {
680 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
681 }
682
683 /**************************************************************************
684 *
685 * Falcon event queue processing
686 * Event queues are processed by per-channel tasklets.
687 *
688 **************************************************************************/
689
690 /* Update a channel's event queue's read pointer (RPTR) register
691 *
692 * This writes the EVQ_RPTR_REG register for the specified channel's
693 * event queue.
694 *
695 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
696 * whereas channel->eventq_read_ptr contains the index of the "next to
697 * read" event.
698 */
699 void falcon_eventq_read_ack(struct efx_channel *channel)
700 {
701 efx_dword_t reg;
702 struct efx_nic *efx = channel->efx;
703
704 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
705 efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
706 channel->channel);
707 }
708
709 /* Use HW to insert a SW defined event */
710 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
711 {
712 efx_oword_t drv_ev_reg;
713
714 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
715 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
716 drv_ev_reg.u32[0] = event->u32[0];
717 drv_ev_reg.u32[1] = event->u32[1];
718 drv_ev_reg.u32[2] = 0;
719 drv_ev_reg.u32[3] = 0;
720 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
721 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
722 }
723
724 /* Handle a transmit completion event
725 *
726 * Falcon batches TX completion events; the message we receive is of
727 * the form "complete all TX events up to this index".
728 */
729 static void falcon_handle_tx_event(struct efx_channel *channel,
730 efx_qword_t *event)
731 {
732 unsigned int tx_ev_desc_ptr;
733 unsigned int tx_ev_q_label;
734 struct efx_tx_queue *tx_queue;
735 struct efx_nic *efx = channel->efx;
736
737 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
738 /* Transmit completion */
739 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
740 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
741 tx_queue = &efx->tx_queue[tx_ev_q_label];
742 channel->irq_mod_score +=
743 (tx_ev_desc_ptr - tx_queue->read_count) &
744 efx->type->txd_ring_mask;
745 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
746 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
747 /* Rewrite the FIFO write pointer */
748 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
749 tx_queue = &efx->tx_queue[tx_ev_q_label];
750
751 if (efx_dev_registered(efx))
752 netif_tx_lock(efx->net_dev);
753 falcon_notify_tx_desc(tx_queue);
754 if (efx_dev_registered(efx))
755 netif_tx_unlock(efx->net_dev);
756 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
757 EFX_WORKAROUND_10727(efx)) {
758 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
759 } else {
760 EFX_ERR(efx, "channel %d unexpected TX event "
761 EFX_QWORD_FMT"\n", channel->channel,
762 EFX_QWORD_VAL(*event));
763 }
764 }
765
766 /* Detect errors included in the rx_evt_pkt_ok bit. */
767 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
768 const efx_qword_t *event,
769 bool *rx_ev_pkt_ok,
770 bool *discard)
771 {
772 struct efx_nic *efx = rx_queue->efx;
773 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
774 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
775 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
776 bool rx_ev_other_err, rx_ev_pause_frm;
777 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
778 unsigned rx_ev_pkt_type;
779
780 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
781 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
782 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
783 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
784 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
785 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
786 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
787 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
788 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
789 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
790 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
791 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
792 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
793 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
794 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
795 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
796
797 /* Every error apart from tobe_disc and pause_frm */
798 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
799 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
800 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
801
802 /* Count errors that are not in MAC stats. Ignore expected
803 * checksum errors during self-test. */
804 if (rx_ev_frm_trunc)
805 ++rx_queue->channel->n_rx_frm_trunc;
806 else if (rx_ev_tobe_disc)
807 ++rx_queue->channel->n_rx_tobe_disc;
808 else if (!efx->loopback_selftest) {
809 if (rx_ev_ip_hdr_chksum_err)
810 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
811 else if (rx_ev_tcp_udp_chksum_err)
812 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
813 }
814 if (rx_ev_ip_frag_err)
815 ++rx_queue->channel->n_rx_ip_frag_err;
816
817 /* The frame must be discarded if any of these are true. */
818 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
819 rx_ev_tobe_disc | rx_ev_pause_frm);
820
821 /* TOBE_DISC is expected on unicast mismatches; don't print out an
822 * error message. FRM_TRUNC indicates RXDP dropped the packet due
823 * to a FIFO overflow.
824 */
825 #ifdef EFX_ENABLE_DEBUG
826 if (rx_ev_other_err) {
827 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
828 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
829 rx_queue->queue, EFX_QWORD_VAL(*event),
830 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
831 rx_ev_ip_hdr_chksum_err ?
832 " [IP_HDR_CHKSUM_ERR]" : "",
833 rx_ev_tcp_udp_chksum_err ?
834 " [TCP_UDP_CHKSUM_ERR]" : "",
835 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
836 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
837 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
838 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
839 rx_ev_pause_frm ? " [PAUSE]" : "");
840 }
841 #endif
842 }
843
844 /* Handle receive events that are not in-order. */
845 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
846 unsigned index)
847 {
848 struct efx_nic *efx = rx_queue->efx;
849 unsigned expected, dropped;
850
851 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
852 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
853 FALCON_RXD_RING_MASK);
854 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
855 dropped, index, expected);
856
857 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
858 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
859 }
860
861 /* Handle a packet received event
862 *
863 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
864 * wrong destination address
865 * Also "is multicast" and "matches multicast filter" flags can be used to
866 * discard non-matching multicast packets.
867 */
868 static void falcon_handle_rx_event(struct efx_channel *channel,
869 const efx_qword_t *event)
870 {
871 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
872 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
873 unsigned expected_ptr;
874 bool rx_ev_pkt_ok, discard = false, checksummed;
875 struct efx_rx_queue *rx_queue;
876 struct efx_nic *efx = channel->efx;
877
878 /* Basic packet information */
879 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
880 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
881 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
882 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
883 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
884 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
885 channel->channel);
886
887 rx_queue = &efx->rx_queue[channel->channel];
888
889 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
890 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
891 if (unlikely(rx_ev_desc_ptr != expected_ptr))
892 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
893
894 if (likely(rx_ev_pkt_ok)) {
895 /* If packet is marked as OK and packet type is TCP/IPv4 or
896 * UDP/IPv4, then we can rely on the hardware checksum.
897 */
898 checksummed =
899 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
900 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP;
901 } else {
902 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
903 &discard);
904 checksummed = false;
905 }
906
907 /* Detect multicast packets that didn't match the filter */
908 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
909 if (rx_ev_mcast_pkt) {
910 unsigned int rx_ev_mcast_hash_match =
911 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
912
913 if (unlikely(!rx_ev_mcast_hash_match))
914 discard = true;
915 }
916
917 channel->irq_mod_score += 2;
918
919 /* Handle received packet */
920 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
921 checksummed, discard);
922 }
923
924 /* Global events are basically PHY events */
925 static void falcon_handle_global_event(struct efx_channel *channel,
926 efx_qword_t *event)
927 {
928 struct efx_nic *efx = channel->efx;
929 bool handled = false;
930
931 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
932 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
933 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
934 efx->phy_op->clear_interrupt(efx);
935 queue_work(efx->workqueue, &efx->phy_work);
936 handled = true;
937 }
938
939 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
940 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
941 queue_work(efx->workqueue, &efx->mac_work);
942 handled = true;
943 }
944
945 if (falcon_rev(efx) <= FALCON_REV_A1 ?
946 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
947 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
948 EFX_ERR(efx, "channel %d seen global RX_RESET "
949 "event. Resetting.\n", channel->channel);
950
951 atomic_inc(&efx->rx_reset);
952 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
953 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
954 handled = true;
955 }
956
957 if (!handled)
958 EFX_ERR(efx, "channel %d unknown global event "
959 EFX_QWORD_FMT "\n", channel->channel,
960 EFX_QWORD_VAL(*event));
961 }
962
963 static void falcon_handle_driver_event(struct efx_channel *channel,
964 efx_qword_t *event)
965 {
966 struct efx_nic *efx = channel->efx;
967 unsigned int ev_sub_code;
968 unsigned int ev_sub_data;
969
970 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
971 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
972
973 switch (ev_sub_code) {
974 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
975 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
976 channel->channel, ev_sub_data);
977 break;
978 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
979 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
980 channel->channel, ev_sub_data);
981 break;
982 case FSE_AZ_EVQ_INIT_DONE_EV:
983 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
984 channel->channel, ev_sub_data);
985 break;
986 case FSE_AZ_SRM_UPD_DONE_EV:
987 EFX_TRACE(efx, "channel %d SRAM update done\n",
988 channel->channel);
989 break;
990 case FSE_AZ_WAKE_UP_EV:
991 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
992 channel->channel, ev_sub_data);
993 break;
994 case FSE_AZ_TIMER_EV:
995 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
996 channel->channel, ev_sub_data);
997 break;
998 case FSE_AA_RX_RECOVER_EV:
999 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1000 "Resetting.\n", channel->channel);
1001 atomic_inc(&efx->rx_reset);
1002 efx_schedule_reset(efx,
1003 EFX_WORKAROUND_6555(efx) ?
1004 RESET_TYPE_RX_RECOVERY :
1005 RESET_TYPE_DISABLE);
1006 break;
1007 case FSE_BZ_RX_DSC_ERROR_EV:
1008 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1009 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1010 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1011 break;
1012 case FSE_BZ_TX_DSC_ERROR_EV:
1013 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1014 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1015 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1016 break;
1017 default:
1018 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1019 "data %04x\n", channel->channel, ev_sub_code,
1020 ev_sub_data);
1021 break;
1022 }
1023 }
1024
1025 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1026 {
1027 unsigned int read_ptr;
1028 efx_qword_t event, *p_event;
1029 int ev_code;
1030 int rx_packets = 0;
1031
1032 read_ptr = channel->eventq_read_ptr;
1033
1034 do {
1035 p_event = falcon_event(channel, read_ptr);
1036 event = *p_event;
1037
1038 if (!falcon_event_present(&event))
1039 /* End of events */
1040 break;
1041
1042 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1043 channel->channel, EFX_QWORD_VAL(event));
1044
1045 /* Clear this event by marking it all ones */
1046 EFX_SET_QWORD(*p_event);
1047
1048 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1049
1050 switch (ev_code) {
1051 case FSE_AZ_EV_CODE_RX_EV:
1052 falcon_handle_rx_event(channel, &event);
1053 ++rx_packets;
1054 break;
1055 case FSE_AZ_EV_CODE_TX_EV:
1056 falcon_handle_tx_event(channel, &event);
1057 break;
1058 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1059 channel->eventq_magic = EFX_QWORD_FIELD(
1060 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1061 EFX_LOG(channel->efx, "channel %d received generated "
1062 "event "EFX_QWORD_FMT"\n", channel->channel,
1063 EFX_QWORD_VAL(event));
1064 break;
1065 case FSE_AZ_EV_CODE_GLOBAL_EV:
1066 falcon_handle_global_event(channel, &event);
1067 break;
1068 case FSE_AZ_EV_CODE_DRIVER_EV:
1069 falcon_handle_driver_event(channel, &event);
1070 break;
1071 default:
1072 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1073 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1074 ev_code, EFX_QWORD_VAL(event));
1075 }
1076
1077 /* Increment read pointer */
1078 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1079
1080 } while (rx_packets < rx_quota);
1081
1082 channel->eventq_read_ptr = read_ptr;
1083 return rx_packets;
1084 }
1085
1086 void falcon_set_int_moderation(struct efx_channel *channel)
1087 {
1088 efx_dword_t timer_cmd;
1089 struct efx_nic *efx = channel->efx;
1090
1091 /* Set timer register */
1092 if (channel->irq_moderation) {
1093 /* Round to resolution supported by hardware. The value we
1094 * program is based at 0. So actual interrupt moderation
1095 * achieved is ((x + 1) * res).
1096 */
1097 channel->irq_moderation -= (channel->irq_moderation %
1098 FALCON_IRQ_MOD_RESOLUTION);
1099 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION)
1100 channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION;
1101 EFX_POPULATE_DWORD_2(timer_cmd,
1102 FRF_AB_TC_TIMER_MODE,
1103 FFE_BB_TIMER_MODE_INT_HLDOFF,
1104 FRF_AB_TC_TIMER_VAL,
1105 channel->irq_moderation /
1106 FALCON_IRQ_MOD_RESOLUTION - 1);
1107 } else {
1108 EFX_POPULATE_DWORD_2(timer_cmd,
1109 FRF_AB_TC_TIMER_MODE,
1110 FFE_BB_TIMER_MODE_DIS,
1111 FRF_AB_TC_TIMER_VAL, 0);
1112 }
1113 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1114 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1115 channel->channel);
1116
1117 }
1118
1119 /* Allocate buffer table entries for event queue */
1120 int falcon_probe_eventq(struct efx_channel *channel)
1121 {
1122 struct efx_nic *efx = channel->efx;
1123 unsigned int evq_size;
1124
1125 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1126 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1127 }
1128
1129 void falcon_init_eventq(struct efx_channel *channel)
1130 {
1131 efx_oword_t evq_ptr;
1132 struct efx_nic *efx = channel->efx;
1133
1134 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1135 channel->channel, channel->eventq.index,
1136 channel->eventq.index + channel->eventq.entries - 1);
1137
1138 /* Pin event queue buffer */
1139 falcon_init_special_buffer(efx, &channel->eventq);
1140
1141 /* Fill event queue with all ones (i.e. empty events) */
1142 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1143
1144 /* Push event queue to card */
1145 EFX_POPULATE_OWORD_3(evq_ptr,
1146 FRF_AZ_EVQ_EN, 1,
1147 FRF_AZ_EVQ_SIZE, FALCON_EVQ_ORDER,
1148 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1149 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1150 channel->channel);
1151
1152 falcon_set_int_moderation(channel);
1153 }
1154
1155 void falcon_fini_eventq(struct efx_channel *channel)
1156 {
1157 efx_oword_t eventq_ptr;
1158 struct efx_nic *efx = channel->efx;
1159
1160 /* Remove event queue from card */
1161 EFX_ZERO_OWORD(eventq_ptr);
1162 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1163 channel->channel);
1164
1165 /* Unpin event queue */
1166 falcon_fini_special_buffer(efx, &channel->eventq);
1167 }
1168
1169 /* Free buffers backing event queue */
1170 void falcon_remove_eventq(struct efx_channel *channel)
1171 {
1172 falcon_free_special_buffer(channel->efx, &channel->eventq);
1173 }
1174
1175
1176 /* Generates a test event on the event queue. A subsequent call to
1177 * process_eventq() should pick up the event and place the value of
1178 * "magic" into channel->eventq_magic;
1179 */
1180 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1181 {
1182 efx_qword_t test_event;
1183
1184 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1185 FSE_AZ_EV_CODE_DRV_GEN_EV,
1186 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1187 falcon_generate_event(channel, &test_event);
1188 }
1189
1190 void falcon_sim_phy_event(struct efx_nic *efx)
1191 {
1192 efx_qword_t phy_event;
1193
1194 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1195 FSE_AZ_EV_CODE_GLOBAL_EV);
1196 if (EFX_IS10G(efx))
1197 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1198 else
1199 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1200
1201 falcon_generate_event(&efx->channel[0], &phy_event);
1202 }
1203
1204 /**************************************************************************
1205 *
1206 * Flush handling
1207 *
1208 **************************************************************************/
1209
1210
1211 static void falcon_poll_flush_events(struct efx_nic *efx)
1212 {
1213 struct efx_channel *channel = &efx->channel[0];
1214 struct efx_tx_queue *tx_queue;
1215 struct efx_rx_queue *rx_queue;
1216 unsigned int read_ptr = channel->eventq_read_ptr;
1217 unsigned int end_ptr = (read_ptr - 1) & FALCON_EVQ_MASK;
1218
1219 do {
1220 efx_qword_t *event = falcon_event(channel, read_ptr);
1221 int ev_code, ev_sub_code, ev_queue;
1222 bool ev_failed;
1223
1224 if (!falcon_event_present(event))
1225 break;
1226
1227 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1228 ev_sub_code = EFX_QWORD_FIELD(*event,
1229 FSF_AZ_DRIVER_EV_SUBCODE);
1230 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1231 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1232 ev_queue = EFX_QWORD_FIELD(*event,
1233 FSF_AZ_DRIVER_EV_SUBDATA);
1234 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1235 tx_queue = efx->tx_queue + ev_queue;
1236 tx_queue->flushed = true;
1237 }
1238 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1239 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1240 ev_queue = EFX_QWORD_FIELD(
1241 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1242 ev_failed = EFX_QWORD_FIELD(
1243 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1244 if (ev_queue < efx->n_rx_queues) {
1245 rx_queue = efx->rx_queue + ev_queue;
1246
1247 /* retry the rx flush */
1248 if (ev_failed)
1249 falcon_flush_rx_queue(rx_queue);
1250 else
1251 rx_queue->flushed = true;
1252 }
1253 }
1254
1255 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1256 } while (read_ptr != end_ptr);
1257 }
1258
1259 /* Handle tx and rx flushes at the same time, since they run in
1260 * parallel in the hardware and there's no reason for us to
1261 * serialise them */
1262 int falcon_flush_queues(struct efx_nic *efx)
1263 {
1264 struct efx_rx_queue *rx_queue;
1265 struct efx_tx_queue *tx_queue;
1266 int i;
1267 bool outstanding;
1268
1269 /* Issue flush requests */
1270 efx_for_each_tx_queue(tx_queue, efx) {
1271 tx_queue->flushed = false;
1272 falcon_flush_tx_queue(tx_queue);
1273 }
1274 efx_for_each_rx_queue(rx_queue, efx) {
1275 rx_queue->flushed = false;
1276 falcon_flush_rx_queue(rx_queue);
1277 }
1278
1279 /* Poll the evq looking for flush completions. Since we're not pushing
1280 * any more rx or tx descriptors at this point, we're in no danger of
1281 * overflowing the evq whilst we wait */
1282 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1283 msleep(FALCON_FLUSH_INTERVAL);
1284 falcon_poll_flush_events(efx);
1285
1286 /* Check if every queue has been succesfully flushed */
1287 outstanding = false;
1288 efx_for_each_tx_queue(tx_queue, efx)
1289 outstanding |= !tx_queue->flushed;
1290 efx_for_each_rx_queue(rx_queue, efx)
1291 outstanding |= !rx_queue->flushed;
1292 if (!outstanding)
1293 return 0;
1294 }
1295
1296 /* Mark the queues as all flushed. We're going to return failure
1297 * leading to a reset, or fake up success anyway. "flushed" now
1298 * indicates that we tried to flush. */
1299 efx_for_each_tx_queue(tx_queue, efx) {
1300 if (!tx_queue->flushed)
1301 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1302 tx_queue->queue);
1303 tx_queue->flushed = true;
1304 }
1305 efx_for_each_rx_queue(rx_queue, efx) {
1306 if (!rx_queue->flushed)
1307 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1308 rx_queue->queue);
1309 rx_queue->flushed = true;
1310 }
1311
1312 if (EFX_WORKAROUND_7803(efx))
1313 return 0;
1314
1315 return -ETIMEDOUT;
1316 }
1317
1318 /**************************************************************************
1319 *
1320 * Falcon hardware interrupts
1321 * The hardware interrupt handler does very little work; all the event
1322 * queue processing is carried out by per-channel tasklets.
1323 *
1324 **************************************************************************/
1325
1326 /* Enable/disable/generate Falcon interrupts */
1327 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1328 int force)
1329 {
1330 efx_oword_t int_en_reg_ker;
1331
1332 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1333 FRF_AZ_KER_INT_KER, force,
1334 FRF_AZ_DRV_INT_EN_KER, enabled);
1335 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1336 }
1337
1338 void falcon_enable_interrupts(struct efx_nic *efx)
1339 {
1340 efx_oword_t int_adr_reg_ker;
1341 struct efx_channel *channel;
1342
1343 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1344 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1345
1346 /* Program address */
1347 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1348 FRF_AZ_NORM_INT_VEC_DIS_KER,
1349 EFX_INT_MODE_USE_MSI(efx),
1350 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1351 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1352
1353 /* Enable interrupts */
1354 falcon_interrupts(efx, 1, 0);
1355
1356 /* Force processing of all the channels to get the EVQ RPTRs up to
1357 date */
1358 efx_for_each_channel(channel, efx)
1359 efx_schedule_channel(channel);
1360 }
1361
1362 void falcon_disable_interrupts(struct efx_nic *efx)
1363 {
1364 /* Disable interrupts */
1365 falcon_interrupts(efx, 0, 0);
1366 }
1367
1368 /* Generate a Falcon test interrupt
1369 * Interrupt must already have been enabled, otherwise nasty things
1370 * may happen.
1371 */
1372 void falcon_generate_interrupt(struct efx_nic *efx)
1373 {
1374 falcon_interrupts(efx, 1, 1);
1375 }
1376
1377 /* Acknowledge a legacy interrupt from Falcon
1378 *
1379 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1380 *
1381 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1382 * BIU. Interrupt acknowledge is read sensitive so must write instead
1383 * (then read to ensure the BIU collector is flushed)
1384 *
1385 * NB most hardware supports MSI interrupts
1386 */
1387 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1388 {
1389 efx_dword_t reg;
1390
1391 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1392 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1393 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1394 }
1395
1396 /* Process a fatal interrupt
1397 * Disable bus mastering ASAP and schedule a reset
1398 */
1399 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1400 {
1401 struct falcon_nic_data *nic_data = efx->nic_data;
1402 efx_oword_t *int_ker = efx->irq_status.addr;
1403 efx_oword_t fatal_intr;
1404 int error, mem_perr;
1405
1406 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1407 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1408
1409 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1410 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1411 EFX_OWORD_VAL(fatal_intr),
1412 error ? "disabling bus mastering" : "no recognised error");
1413 if (error == 0)
1414 goto out;
1415
1416 /* If this is a memory parity error dump which blocks are offending */
1417 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1418 if (mem_perr) {
1419 efx_oword_t reg;
1420 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1421 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1422 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1423 }
1424
1425 /* Disable both devices */
1426 pci_clear_master(efx->pci_dev);
1427 if (FALCON_IS_DUAL_FUNC(efx))
1428 pci_clear_master(nic_data->pci_dev2);
1429 falcon_disable_interrupts(efx);
1430
1431 /* Count errors and reset or disable the NIC accordingly */
1432 if (nic_data->int_error_count == 0 ||
1433 time_after(jiffies, nic_data->int_error_expire)) {
1434 nic_data->int_error_count = 0;
1435 nic_data->int_error_expire =
1436 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1437 }
1438 if (++nic_data->int_error_count < FALCON_MAX_INT_ERRORS) {
1439 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1440 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1441 } else {
1442 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1443 "NIC will be disabled\n");
1444 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1445 }
1446 out:
1447 return IRQ_HANDLED;
1448 }
1449
1450 /* Handle a legacy interrupt from Falcon
1451 * Acknowledges the interrupt and schedule event queue processing.
1452 */
1453 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1454 {
1455 struct efx_nic *efx = dev_id;
1456 efx_oword_t *int_ker = efx->irq_status.addr;
1457 irqreturn_t result = IRQ_NONE;
1458 struct efx_channel *channel;
1459 efx_dword_t reg;
1460 u32 queues;
1461 int syserr;
1462
1463 /* Read the ISR which also ACKs the interrupts */
1464 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1465 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1466
1467 /* Check to see if we have a serious error condition */
1468 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1469 if (unlikely(syserr))
1470 return falcon_fatal_interrupt(efx);
1471
1472 /* Schedule processing of any interrupting queues */
1473 efx_for_each_channel(channel, efx) {
1474 if ((queues & 1) ||
1475 falcon_event_present(
1476 falcon_event(channel, channel->eventq_read_ptr))) {
1477 efx_schedule_channel(channel);
1478 result = IRQ_HANDLED;
1479 }
1480 queues >>= 1;
1481 }
1482
1483 if (result == IRQ_HANDLED) {
1484 efx->last_irq_cpu = raw_smp_processor_id();
1485 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1486 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1487 }
1488
1489 return result;
1490 }
1491
1492
1493 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1494 {
1495 struct efx_nic *efx = dev_id;
1496 efx_oword_t *int_ker = efx->irq_status.addr;
1497 struct efx_channel *channel;
1498 int syserr;
1499 int queues;
1500
1501 /* Check to see if this is our interrupt. If it isn't, we
1502 * exit without having touched the hardware.
1503 */
1504 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1505 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1506 raw_smp_processor_id());
1507 return IRQ_NONE;
1508 }
1509 efx->last_irq_cpu = raw_smp_processor_id();
1510 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1511 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1512
1513 /* Check to see if we have a serious error condition */
1514 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1515 if (unlikely(syserr))
1516 return falcon_fatal_interrupt(efx);
1517
1518 /* Determine interrupting queues, clear interrupt status
1519 * register and acknowledge the device interrupt.
1520 */
1521 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1522 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1523 EFX_ZERO_OWORD(*int_ker);
1524 wmb(); /* Ensure the vector is cleared before interrupt ack */
1525 falcon_irq_ack_a1(efx);
1526
1527 /* Schedule processing of any interrupting queues */
1528 channel = &efx->channel[0];
1529 while (queues) {
1530 if (queues & 0x01)
1531 efx_schedule_channel(channel);
1532 channel++;
1533 queues >>= 1;
1534 }
1535
1536 return IRQ_HANDLED;
1537 }
1538
1539 /* Handle an MSI interrupt from Falcon
1540 *
1541 * Handle an MSI hardware interrupt. This routine schedules event
1542 * queue processing. No interrupt acknowledgement cycle is necessary.
1543 * Also, we never need to check that the interrupt is for us, since
1544 * MSI interrupts cannot be shared.
1545 */
1546 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1547 {
1548 struct efx_channel *channel = dev_id;
1549 struct efx_nic *efx = channel->efx;
1550 efx_oword_t *int_ker = efx->irq_status.addr;
1551 int syserr;
1552
1553 efx->last_irq_cpu = raw_smp_processor_id();
1554 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1555 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1556
1557 /* Check to see if we have a serious error condition */
1558 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1559 if (unlikely(syserr))
1560 return falcon_fatal_interrupt(efx);
1561
1562 /* Schedule processing of the channel */
1563 efx_schedule_channel(channel);
1564
1565 return IRQ_HANDLED;
1566 }
1567
1568
1569 /* Setup RSS indirection table.
1570 * This maps from the hash value of the packet to RXQ
1571 */
1572 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1573 {
1574 int i = 0;
1575 unsigned long offset;
1576 efx_dword_t dword;
1577
1578 if (falcon_rev(efx) < FALCON_REV_B0)
1579 return;
1580
1581 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1582 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1583 offset += 0x10) {
1584 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1585 i % efx->n_rx_queues);
1586 efx_writed(efx, &dword, offset);
1587 i++;
1588 }
1589 }
1590
1591 /* Hook interrupt handler(s)
1592 * Try MSI and then legacy interrupts.
1593 */
1594 int falcon_init_interrupt(struct efx_nic *efx)
1595 {
1596 struct efx_channel *channel;
1597 int rc;
1598
1599 if (!EFX_INT_MODE_USE_MSI(efx)) {
1600 irq_handler_t handler;
1601 if (falcon_rev(efx) >= FALCON_REV_B0)
1602 handler = falcon_legacy_interrupt_b0;
1603 else
1604 handler = falcon_legacy_interrupt_a1;
1605
1606 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1607 efx->name, efx);
1608 if (rc) {
1609 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1610 efx->pci_dev->irq);
1611 goto fail1;
1612 }
1613 return 0;
1614 }
1615
1616 /* Hook MSI or MSI-X interrupt */
1617 efx_for_each_channel(channel, efx) {
1618 rc = request_irq(channel->irq, falcon_msi_interrupt,
1619 IRQF_PROBE_SHARED, /* Not shared */
1620 channel->name, channel);
1621 if (rc) {
1622 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1623 goto fail2;
1624 }
1625 }
1626
1627 return 0;
1628
1629 fail2:
1630 efx_for_each_channel(channel, efx)
1631 free_irq(channel->irq, channel);
1632 fail1:
1633 return rc;
1634 }
1635
1636 void falcon_fini_interrupt(struct efx_nic *efx)
1637 {
1638 struct efx_channel *channel;
1639 efx_oword_t reg;
1640
1641 /* Disable MSI/MSI-X interrupts */
1642 efx_for_each_channel(channel, efx) {
1643 if (channel->irq)
1644 free_irq(channel->irq, channel);
1645 }
1646
1647 /* ACK legacy interrupt */
1648 if (falcon_rev(efx) >= FALCON_REV_B0)
1649 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1650 else
1651 falcon_irq_ack_a1(efx);
1652
1653 /* Disable legacy interrupt */
1654 if (efx->legacy_irq)
1655 free_irq(efx->legacy_irq, efx);
1656 }
1657
1658 /**************************************************************************
1659 *
1660 * EEPROM/flash
1661 *
1662 **************************************************************************
1663 */
1664
1665 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1666
1667 static int falcon_spi_poll(struct efx_nic *efx)
1668 {
1669 efx_oword_t reg;
1670 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1671 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1672 }
1673
1674 /* Wait for SPI command completion */
1675 static int falcon_spi_wait(struct efx_nic *efx)
1676 {
1677 /* Most commands will finish quickly, so we start polling at
1678 * very short intervals. Sometimes the command may have to
1679 * wait for VPD or expansion ROM access outside of our
1680 * control, so we allow up to 100 ms. */
1681 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1682 int i;
1683
1684 for (i = 0; i < 10; i++) {
1685 if (!falcon_spi_poll(efx))
1686 return 0;
1687 udelay(10);
1688 }
1689
1690 for (;;) {
1691 if (!falcon_spi_poll(efx))
1692 return 0;
1693 if (time_after_eq(jiffies, timeout)) {
1694 EFX_ERR(efx, "timed out waiting for SPI\n");
1695 return -ETIMEDOUT;
1696 }
1697 schedule_timeout_uninterruptible(1);
1698 }
1699 }
1700
1701 int falcon_spi_cmd(const struct efx_spi_device *spi,
1702 unsigned int command, int address,
1703 const void *in, void *out, size_t len)
1704 {
1705 struct efx_nic *efx = spi->efx;
1706 bool addressed = (address >= 0);
1707 bool reading = (out != NULL);
1708 efx_oword_t reg;
1709 int rc;
1710
1711 /* Input validation */
1712 if (len > FALCON_SPI_MAX_LEN)
1713 return -EINVAL;
1714 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1715
1716 /* Check that previous command is not still running */
1717 rc = falcon_spi_poll(efx);
1718 if (rc)
1719 return rc;
1720
1721 /* Program address register, if we have an address */
1722 if (addressed) {
1723 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1724 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1725 }
1726
1727 /* Program data register, if we have data */
1728 if (in != NULL) {
1729 memcpy(&reg, in, len);
1730 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1731 }
1732
1733 /* Issue read/write command */
1734 EFX_POPULATE_OWORD_7(reg,
1735 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1736 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1737 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1738 FRF_AB_EE_SPI_HCMD_READ, reading,
1739 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1740 FRF_AB_EE_SPI_HCMD_ADBCNT,
1741 (addressed ? spi->addr_len : 0),
1742 FRF_AB_EE_SPI_HCMD_ENC, command);
1743 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1744
1745 /* Wait for read/write to complete */
1746 rc = falcon_spi_wait(efx);
1747 if (rc)
1748 return rc;
1749
1750 /* Read data */
1751 if (out != NULL) {
1752 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1753 memcpy(out, &reg, len);
1754 }
1755
1756 return 0;
1757 }
1758
1759 static size_t
1760 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1761 {
1762 return min(FALCON_SPI_MAX_LEN,
1763 (spi->block_size - (start & (spi->block_size - 1))));
1764 }
1765
1766 static inline u8
1767 efx_spi_munge_command(const struct efx_spi_device *spi,
1768 const u8 command, const unsigned int address)
1769 {
1770 return command | (((address >> 8) & spi->munge_address) << 3);
1771 }
1772
1773 /* Wait up to 10 ms for buffered write completion */
1774 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1775 {
1776 struct efx_nic *efx = spi->efx;
1777 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1778 u8 status;
1779 int rc;
1780
1781 for (;;) {
1782 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1783 &status, sizeof(status));
1784 if (rc)
1785 return rc;
1786 if (!(status & SPI_STATUS_NRDY))
1787 return 0;
1788 if (time_after_eq(jiffies, timeout)) {
1789 EFX_ERR(efx, "SPI write timeout on device %d"
1790 " last status=0x%02x\n",
1791 spi->device_id, status);
1792 return -ETIMEDOUT;
1793 }
1794 schedule_timeout_uninterruptible(1);
1795 }
1796 }
1797
1798 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1799 size_t len, size_t *retlen, u8 *buffer)
1800 {
1801 size_t block_len, pos = 0;
1802 unsigned int command;
1803 int rc = 0;
1804
1805 while (pos < len) {
1806 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1807
1808 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1809 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1810 buffer + pos, block_len);
1811 if (rc)
1812 break;
1813 pos += block_len;
1814
1815 /* Avoid locking up the system */
1816 cond_resched();
1817 if (signal_pending(current)) {
1818 rc = -EINTR;
1819 break;
1820 }
1821 }
1822
1823 if (retlen)
1824 *retlen = pos;
1825 return rc;
1826 }
1827
1828 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1829 size_t len, size_t *retlen, const u8 *buffer)
1830 {
1831 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1832 size_t block_len, pos = 0;
1833 unsigned int command;
1834 int rc = 0;
1835
1836 while (pos < len) {
1837 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1838 if (rc)
1839 break;
1840
1841 block_len = min(len - pos,
1842 falcon_spi_write_limit(spi, start + pos));
1843 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1844 rc = falcon_spi_cmd(spi, command, start + pos,
1845 buffer + pos, NULL, block_len);
1846 if (rc)
1847 break;
1848
1849 rc = falcon_spi_wait_write(spi);
1850 if (rc)
1851 break;
1852
1853 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1854 rc = falcon_spi_cmd(spi, command, start + pos,
1855 NULL, verify_buffer, block_len);
1856 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1857 rc = -EIO;
1858 break;
1859 }
1860
1861 pos += block_len;
1862
1863 /* Avoid locking up the system */
1864 cond_resched();
1865 if (signal_pending(current)) {
1866 rc = -EINTR;
1867 break;
1868 }
1869 }
1870
1871 if (retlen)
1872 *retlen = pos;
1873 return rc;
1874 }
1875
1876 /**************************************************************************
1877 *
1878 * MAC wrapper
1879 *
1880 **************************************************************************
1881 */
1882
1883 static int falcon_reset_macs(struct efx_nic *efx)
1884 {
1885 efx_oword_t reg;
1886 int count;
1887
1888 if (falcon_rev(efx) < FALCON_REV_B0) {
1889 /* It's not safe to use GLB_CTL_REG to reset the
1890 * macs, so instead use the internal MAC resets
1891 */
1892 if (!EFX_IS10G(efx)) {
1893 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1894 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1895 udelay(1000);
1896
1897 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1898 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1899 udelay(1000);
1900 return 0;
1901 } else {
1902 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1903 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1904
1905 for (count = 0; count < 10000; count++) {
1906 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1907 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1908 0)
1909 return 0;
1910 udelay(10);
1911 }
1912
1913 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1914 return -ETIMEDOUT;
1915 }
1916 }
1917
1918 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1919 * the drain sequence with the statistics fetch */
1920 efx_stats_disable(efx);
1921
1922 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1923 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1924 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1925
1926 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1927 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1928 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1929 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1930 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1931
1932 count = 0;
1933 while (1) {
1934 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1935 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1936 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1937 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1938 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1939 count);
1940 break;
1941 }
1942 if (count > 20) {
1943 EFX_ERR(efx, "MAC reset failed\n");
1944 break;
1945 }
1946 count++;
1947 udelay(10);
1948 }
1949
1950 efx_stats_enable(efx);
1951
1952 /* If we've reset the EM block and the link is up, then
1953 * we'll have to kick the XAUI link so the PHY can recover */
1954 if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1955 falcon_reset_xaui(efx);
1956
1957 return 0;
1958 }
1959
1960 void falcon_drain_tx_fifo(struct efx_nic *efx)
1961 {
1962 efx_oword_t reg;
1963
1964 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1965 (efx->loopback_mode != LOOPBACK_NONE))
1966 return;
1967
1968 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1969 /* There is no point in draining more than once */
1970 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1971 return;
1972
1973 falcon_reset_macs(efx);
1974 }
1975
1976 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1977 {
1978 efx_oword_t reg;
1979
1980 if (falcon_rev(efx) < FALCON_REV_B0)
1981 return;
1982
1983 /* Isolate the MAC -> RX */
1984 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1985 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1986 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1987
1988 if (!efx->link_up)
1989 falcon_drain_tx_fifo(efx);
1990 }
1991
1992 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1993 {
1994 efx_oword_t reg;
1995 int link_speed;
1996 bool tx_fc;
1997
1998 switch (efx->link_speed) {
1999 case 10000: link_speed = 3; break;
2000 case 1000: link_speed = 2; break;
2001 case 100: link_speed = 1; break;
2002 default: link_speed = 0; break;
2003 }
2004 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
2005 * as advertised. Disable to ensure packets are not
2006 * indefinitely held and TX queue can be flushed at any point
2007 * while the link is down. */
2008 EFX_POPULATE_OWORD_5(reg,
2009 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
2010 FRF_AB_MAC_BCAD_ACPT, 1,
2011 FRF_AB_MAC_UC_PROM, efx->promiscuous,
2012 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
2013 FRF_AB_MAC_SPEED, link_speed);
2014 /* On B0, MAC backpressure can be disabled and packets get
2015 * discarded. */
2016 if (falcon_rev(efx) >= FALCON_REV_B0) {
2017 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
2018 !efx->link_up);
2019 }
2020
2021 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
2022
2023 /* Restore the multicast hash registers. */
2024 falcon_set_multicast_hash(efx);
2025
2026 /* Transmission of pause frames when RX crosses the threshold is
2027 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2028 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2029 tx_fc = !!(efx->link_fc & EFX_FC_TX);
2030 efx_reado(efx, &reg, FR_AZ_RX_CFG);
2031 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
2032
2033 /* Unisolate the MAC -> RX */
2034 if (falcon_rev(efx) >= FALCON_REV_B0)
2035 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2036 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2037 }
2038
2039 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2040 {
2041 efx_oword_t reg;
2042 u32 *dma_done;
2043 int i;
2044
2045 if (disable_dma_stats)
2046 return 0;
2047
2048 /* Statistics fetch will fail if the MAC is in TX drain */
2049 if (falcon_rev(efx) >= FALCON_REV_B0) {
2050 efx_oword_t temp;
2051 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2052 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2053 return 0;
2054 }
2055
2056 dma_done = (efx->stats_buffer.addr + done_offset);
2057 *dma_done = FALCON_STATS_NOT_DONE;
2058 wmb(); /* ensure done flag is clear */
2059
2060 /* Initiate DMA transfer of stats */
2061 EFX_POPULATE_OWORD_2(reg,
2062 FRF_AB_MAC_STAT_DMA_CMD, 1,
2063 FRF_AB_MAC_STAT_DMA_ADR,
2064 efx->stats_buffer.dma_addr);
2065 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2066
2067 /* Wait for transfer to complete */
2068 for (i = 0; i < 400; i++) {
2069 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2070 rmb(); /* Ensure the stats are valid. */
2071 return 0;
2072 }
2073 udelay(10);
2074 }
2075
2076 EFX_ERR(efx, "timed out waiting for statistics\n");
2077 return -ETIMEDOUT;
2078 }
2079
2080 /**************************************************************************
2081 *
2082 * PHY access via GMII
2083 *
2084 **************************************************************************
2085 */
2086
2087 /* Wait for GMII access to complete */
2088 static int falcon_gmii_wait(struct efx_nic *efx)
2089 {
2090 efx_dword_t md_stat;
2091 int count;
2092
2093 /* wait upto 50ms - taken max from datasheet */
2094 for (count = 0; count < 5000; count++) {
2095 efx_readd(efx, &md_stat, FR_AB_MD_STAT);
2096 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2097 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2098 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2099 EFX_ERR(efx, "error from GMII access "
2100 EFX_DWORD_FMT"\n",
2101 EFX_DWORD_VAL(md_stat));
2102 return -EIO;
2103 }
2104 return 0;
2105 }
2106 udelay(10);
2107 }
2108 EFX_ERR(efx, "timed out waiting for GMII\n");
2109 return -ETIMEDOUT;
2110 }
2111
2112 /* Write an MDIO register of a PHY connected to Falcon. */
2113 static int falcon_mdio_write(struct net_device *net_dev,
2114 int prtad, int devad, u16 addr, u16 value)
2115 {
2116 struct efx_nic *efx = netdev_priv(net_dev);
2117 efx_oword_t reg;
2118 int rc;
2119
2120 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2121 prtad, devad, addr, value);
2122
2123 spin_lock_bh(&efx->phy_lock);
2124
2125 /* Check MDIO not currently being accessed */
2126 rc = falcon_gmii_wait(efx);
2127 if (rc)
2128 goto out;
2129
2130 /* Write the address/ID register */
2131 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2132 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2133
2134 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2135 FRF_AB_MD_DEV_ADR, devad);
2136 efx_writeo(efx, &reg, FR_AB_MD_ID);
2137
2138 /* Write data */
2139 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2140 efx_writeo(efx, &reg, FR_AB_MD_TXD);
2141
2142 EFX_POPULATE_OWORD_2(reg,
2143 FRF_AB_MD_WRC, 1,
2144 FRF_AB_MD_GC, 0);
2145 efx_writeo(efx, &reg, FR_AB_MD_CS);
2146
2147 /* Wait for data to be written */
2148 rc = falcon_gmii_wait(efx);
2149 if (rc) {
2150 /* Abort the write operation */
2151 EFX_POPULATE_OWORD_2(reg,
2152 FRF_AB_MD_WRC, 0,
2153 FRF_AB_MD_GC, 1);
2154 efx_writeo(efx, &reg, FR_AB_MD_CS);
2155 udelay(10);
2156 }
2157
2158 out:
2159 spin_unlock_bh(&efx->phy_lock);
2160 return rc;
2161 }
2162
2163 /* Read an MDIO register of a PHY connected to Falcon. */
2164 static int falcon_mdio_read(struct net_device *net_dev,
2165 int prtad, int devad, u16 addr)
2166 {
2167 struct efx_nic *efx = netdev_priv(net_dev);
2168 efx_oword_t reg;
2169 int rc;
2170
2171 spin_lock_bh(&efx->phy_lock);
2172
2173 /* Check MDIO not currently being accessed */
2174 rc = falcon_gmii_wait(efx);
2175 if (rc)
2176 goto out;
2177
2178 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2179 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2180
2181 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2182 FRF_AB_MD_DEV_ADR, devad);
2183 efx_writeo(efx, &reg, FR_AB_MD_ID);
2184
2185 /* Request data to be read */
2186 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2187 efx_writeo(efx, &reg, FR_AB_MD_CS);
2188
2189 /* Wait for data to become available */
2190 rc = falcon_gmii_wait(efx);
2191 if (rc == 0) {
2192 efx_reado(efx, &reg, FR_AB_MD_RXD);
2193 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2194 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2195 prtad, devad, addr, rc);
2196 } else {
2197 /* Abort the read operation */
2198 EFX_POPULATE_OWORD_2(reg,
2199 FRF_AB_MD_RIC, 0,
2200 FRF_AB_MD_GC, 1);
2201 efx_writeo(efx, &reg, FR_AB_MD_CS);
2202
2203 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2204 prtad, devad, addr, rc);
2205 }
2206
2207 out:
2208 spin_unlock_bh(&efx->phy_lock);
2209 return rc;
2210 }
2211
2212 static int falcon_probe_phy(struct efx_nic *efx)
2213 {
2214 switch (efx->phy_type) {
2215 case PHY_TYPE_SFX7101:
2216 efx->phy_op = &falcon_sfx7101_phy_ops;
2217 break;
2218 case PHY_TYPE_SFT9001A:
2219 case PHY_TYPE_SFT9001B:
2220 efx->phy_op = &falcon_sft9001_phy_ops;
2221 break;
2222 case PHY_TYPE_QT2022C2:
2223 case PHY_TYPE_QT2025C:
2224 efx->phy_op = &falcon_xfp_phy_ops;
2225 break;
2226 default:
2227 EFX_ERR(efx, "Unknown PHY type %d\n",
2228 efx->phy_type);
2229 return -1;
2230 }
2231
2232 if (efx->phy_op->macs & EFX_XMAC)
2233 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2234 (1 << LOOPBACK_XGXS) |
2235 (1 << LOOPBACK_XAUI));
2236 if (efx->phy_op->macs & EFX_GMAC)
2237 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2238 efx->loopback_modes |= efx->phy_op->loopbacks;
2239
2240 return 0;
2241 }
2242
2243 int falcon_switch_mac(struct efx_nic *efx)
2244 {
2245 struct efx_mac_operations *old_mac_op = efx->mac_op;
2246 efx_oword_t nic_stat;
2247 unsigned strap_val;
2248 int rc = 0;
2249
2250 /* Don't try to fetch MAC stats while we're switching MACs */
2251 efx_stats_disable(efx);
2252
2253 /* Internal loopbacks override the phy speed setting */
2254 if (efx->loopback_mode == LOOPBACK_GMAC) {
2255 efx->link_speed = 1000;
2256 efx->link_fd = true;
2257 } else if (LOOPBACK_INTERNAL(efx)) {
2258 efx->link_speed = 10000;
2259 efx->link_fd = true;
2260 }
2261
2262 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2263 efx->mac_op = (EFX_IS10G(efx) ?
2264 &falcon_xmac_operations : &falcon_gmac_operations);
2265
2266 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2267 * changed, because this function is run post online reset */
2268 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2269 strap_val = EFX_IS10G(efx) ? 5 : 3;
2270 if (falcon_rev(efx) >= FALCON_REV_B0) {
2271 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2272 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2273 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2274 } else {
2275 /* Falcon A1 does not support 1G/10G speed switching
2276 * and must not be used with a PHY that does. */
2277 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2278 strap_val);
2279 }
2280
2281 if (old_mac_op == efx->mac_op)
2282 goto out;
2283
2284 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2285 /* Not all macs support a mac-level link state */
2286 efx->mac_up = true;
2287
2288 rc = falcon_reset_macs(efx);
2289 out:
2290 efx_stats_enable(efx);
2291 return rc;
2292 }
2293
2294 /* This call is responsible for hooking in the MAC and PHY operations */
2295 int falcon_probe_port(struct efx_nic *efx)
2296 {
2297 int rc;
2298
2299 /* Hook in PHY operations table */
2300 rc = falcon_probe_phy(efx);
2301 if (rc)
2302 return rc;
2303
2304 /* Set up MDIO structure for PHY */
2305 efx->mdio.mmds = efx->phy_op->mmds;
2306 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2307 efx->mdio.mdio_read = falcon_mdio_read;
2308 efx->mdio.mdio_write = falcon_mdio_write;
2309
2310 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2311 if (falcon_rev(efx) >= FALCON_REV_B0)
2312 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2313 else
2314 efx->wanted_fc = EFX_FC_RX;
2315
2316 /* Allocate buffer for stats */
2317 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2318 FALCON_MAC_STATS_SIZE);
2319 if (rc)
2320 return rc;
2321 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2322 (u64)efx->stats_buffer.dma_addr,
2323 efx->stats_buffer.addr,
2324 (u64)virt_to_phys(efx->stats_buffer.addr));
2325
2326 return 0;
2327 }
2328
2329 void falcon_remove_port(struct efx_nic *efx)
2330 {
2331 falcon_free_buffer(efx, &efx->stats_buffer);
2332 }
2333
2334 /**************************************************************************
2335 *
2336 * Multicast filtering
2337 *
2338 **************************************************************************
2339 */
2340
2341 void falcon_set_multicast_hash(struct efx_nic *efx)
2342 {
2343 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2344
2345 /* Broadcast packets go through the multicast hash filter.
2346 * ether_crc_le() of the broadcast address is 0xbe2612ff
2347 * so we always add bit 0xff to the mask.
2348 */
2349 set_bit_le(0xff, mc_hash->byte);
2350
2351 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2352 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2353 }
2354
2355
2356 /**************************************************************************
2357 *
2358 * Falcon test code
2359 *
2360 **************************************************************************/
2361
2362 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2363 {
2364 struct falcon_nvconfig *nvconfig;
2365 struct efx_spi_device *spi;
2366 void *region;
2367 int rc, magic_num, struct_ver;
2368 __le16 *word, *limit;
2369 u32 csum;
2370
2371 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2372 if (!spi)
2373 return -EINVAL;
2374
2375 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2376 if (!region)
2377 return -ENOMEM;
2378 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2379
2380 mutex_lock(&efx->spi_lock);
2381 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2382 mutex_unlock(&efx->spi_lock);
2383 if (rc) {
2384 EFX_ERR(efx, "Failed to read %s\n",
2385 efx->spi_flash ? "flash" : "EEPROM");
2386 rc = -EIO;
2387 goto out;
2388 }
2389
2390 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2391 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2392
2393 rc = -EINVAL;
2394 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2395 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2396 goto out;
2397 }
2398 if (struct_ver < 2) {
2399 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2400 goto out;
2401 } else if (struct_ver < 4) {
2402 word = &nvconfig->board_magic_num;
2403 limit = (__le16 *) (nvconfig + 1);
2404 } else {
2405 word = region;
2406 limit = region + FALCON_NVCONFIG_END;
2407 }
2408 for (csum = 0; word < limit; ++word)
2409 csum += le16_to_cpu(*word);
2410
2411 if (~csum & 0xffff) {
2412 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2413 goto out;
2414 }
2415
2416 rc = 0;
2417 if (nvconfig_out)
2418 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2419
2420 out:
2421 kfree(region);
2422 return rc;
2423 }
2424
2425 /* Registers tested in the falcon register test */
2426 static struct {
2427 unsigned address;
2428 efx_oword_t mask;
2429 } efx_test_registers[] = {
2430 { FR_AZ_ADR_REGION,
2431 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2432 { FR_AZ_RX_CFG,
2433 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2434 { FR_AZ_TX_CFG,
2435 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2436 { FR_AZ_TX_RESERVED,
2437 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2438 { FR_AB_MAC_CTRL,
2439 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2440 { FR_AZ_SRM_TX_DC_CFG,
2441 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2442 { FR_AZ_RX_DC_CFG,
2443 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2444 { FR_AZ_RX_DC_PF_WM,
2445 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2446 { FR_BZ_DP_CTRL,
2447 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2448 { FR_AB_GM_CFG2,
2449 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2450 { FR_AB_GMF_CFG0,
2451 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2452 { FR_AB_XM_GLB_CFG,
2453 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2454 { FR_AB_XM_TX_CFG,
2455 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2456 { FR_AB_XM_RX_CFG,
2457 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2458 { FR_AB_XM_RX_PARAM,
2459 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2460 { FR_AB_XM_FC,
2461 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2462 { FR_AB_XM_ADR_LO,
2463 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2464 { FR_AB_XX_SD_CTL,
2465 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2466 };
2467
2468 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2469 const efx_oword_t *mask)
2470 {
2471 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2472 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2473 }
2474
2475 int falcon_test_registers(struct efx_nic *efx)
2476 {
2477 unsigned address = 0, i, j;
2478 efx_oword_t mask, imask, original, reg, buf;
2479
2480 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2481 WARN_ON(!LOOPBACK_INTERNAL(efx));
2482
2483 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2484 address = efx_test_registers[i].address;
2485 mask = imask = efx_test_registers[i].mask;
2486 EFX_INVERT_OWORD(imask);
2487
2488 efx_reado(efx, &original, address);
2489
2490 /* bit sweep on and off */
2491 for (j = 0; j < 128; j++) {
2492 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2493 continue;
2494
2495 /* Test this testable bit can be set in isolation */
2496 EFX_AND_OWORD(reg, original, mask);
2497 EFX_SET_OWORD32(reg, j, j, 1);
2498
2499 efx_writeo(efx, &reg, address);
2500 efx_reado(efx, &buf, address);
2501
2502 if (efx_masked_compare_oword(&reg, &buf, &mask))
2503 goto fail;
2504
2505 /* Test this testable bit can be cleared in isolation */
2506 EFX_OR_OWORD(reg, original, mask);
2507 EFX_SET_OWORD32(reg, j, j, 0);
2508
2509 efx_writeo(efx, &reg, address);
2510 efx_reado(efx, &buf, address);
2511
2512 if (efx_masked_compare_oword(&reg, &buf, &mask))
2513 goto fail;
2514 }
2515
2516 efx_writeo(efx, &original, address);
2517 }
2518
2519 return 0;
2520
2521 fail:
2522 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2523 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2524 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2525 return -EIO;
2526 }
2527
2528 /**************************************************************************
2529 *
2530 * Device reset
2531 *
2532 **************************************************************************
2533 */
2534
2535 /* Resets NIC to known state. This routine must be called in process
2536 * context and is allowed to sleep. */
2537 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2538 {
2539 struct falcon_nic_data *nic_data = efx->nic_data;
2540 efx_oword_t glb_ctl_reg_ker;
2541 int rc;
2542
2543 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2544
2545 /* Initiate device reset */
2546 if (method == RESET_TYPE_WORLD) {
2547 rc = pci_save_state(efx->pci_dev);
2548 if (rc) {
2549 EFX_ERR(efx, "failed to backup PCI state of primary "
2550 "function prior to hardware reset\n");
2551 goto fail1;
2552 }
2553 if (FALCON_IS_DUAL_FUNC(efx)) {
2554 rc = pci_save_state(nic_data->pci_dev2);
2555 if (rc) {
2556 EFX_ERR(efx, "failed to backup PCI state of "
2557 "secondary function prior to "
2558 "hardware reset\n");
2559 goto fail2;
2560 }
2561 }
2562
2563 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2564 FRF_AB_EXT_PHY_RST_DUR,
2565 FFE_AB_EXT_PHY_RST_DUR_10240US,
2566 FRF_AB_SWRST, 1);
2567 } else {
2568 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2569 /* exclude PHY from "invisible" reset */
2570 FRF_AB_EXT_PHY_RST_CTL,
2571 method == RESET_TYPE_INVISIBLE,
2572 /* exclude EEPROM/flash and PCIe */
2573 FRF_AB_PCIE_CORE_RST_CTL, 1,
2574 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2575 FRF_AB_PCIE_SD_RST_CTL, 1,
2576 FRF_AB_EE_RST_CTL, 1,
2577 FRF_AB_EXT_PHY_RST_DUR,
2578 FFE_AB_EXT_PHY_RST_DUR_10240US,
2579 FRF_AB_SWRST, 1);
2580 }
2581 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2582
2583 EFX_LOG(efx, "waiting for hardware reset\n");
2584 schedule_timeout_uninterruptible(HZ / 20);
2585
2586 /* Restore PCI configuration if needed */
2587 if (method == RESET_TYPE_WORLD) {
2588 if (FALCON_IS_DUAL_FUNC(efx)) {
2589 rc = pci_restore_state(nic_data->pci_dev2);
2590 if (rc) {
2591 EFX_ERR(efx, "failed to restore PCI config for "
2592 "the secondary function\n");
2593 goto fail3;
2594 }
2595 }
2596 rc = pci_restore_state(efx->pci_dev);
2597 if (rc) {
2598 EFX_ERR(efx, "failed to restore PCI config for the "
2599 "primary function\n");
2600 goto fail4;
2601 }
2602 EFX_LOG(efx, "successfully restored PCI config\n");
2603 }
2604
2605 /* Assert that reset complete */
2606 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2607 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2608 rc = -ETIMEDOUT;
2609 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2610 goto fail5;
2611 }
2612 EFX_LOG(efx, "hardware reset complete\n");
2613
2614 return 0;
2615
2616 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2617 fail2:
2618 fail3:
2619 pci_restore_state(efx->pci_dev);
2620 fail1:
2621 fail4:
2622 fail5:
2623 return rc;
2624 }
2625
2626 /* Zeroes out the SRAM contents. This routine must be called in
2627 * process context and is allowed to sleep.
2628 */
2629 static int falcon_reset_sram(struct efx_nic *efx)
2630 {
2631 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2632 int count;
2633
2634 /* Set the SRAM wake/sleep GPIO appropriately. */
2635 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2636 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2637 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2638 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2639
2640 /* Initiate SRAM reset */
2641 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2642 FRF_AZ_SRM_INIT_EN, 1,
2643 FRF_AZ_SRM_NB_SZ, 0);
2644 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2645
2646 /* Wait for SRAM reset to complete */
2647 count = 0;
2648 do {
2649 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2650
2651 /* SRAM reset is slow; expect around 16ms */
2652 schedule_timeout_uninterruptible(HZ / 50);
2653
2654 /* Check for reset complete */
2655 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2656 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2657 EFX_LOG(efx, "SRAM reset complete\n");
2658
2659 return 0;
2660 }
2661 } while (++count < 20); /* wait upto 0.4 sec */
2662
2663 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2664 return -ETIMEDOUT;
2665 }
2666
2667 static int falcon_spi_device_init(struct efx_nic *efx,
2668 struct efx_spi_device **spi_device_ret,
2669 unsigned int device_id, u32 device_type)
2670 {
2671 struct efx_spi_device *spi_device;
2672
2673 if (device_type != 0) {
2674 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2675 if (!spi_device)
2676 return -ENOMEM;
2677 spi_device->device_id = device_id;
2678 spi_device->size =
2679 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2680 spi_device->addr_len =
2681 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2682 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2683 spi_device->addr_len == 1);
2684 spi_device->erase_command =
2685 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2686 spi_device->erase_size =
2687 1 << SPI_DEV_TYPE_FIELD(device_type,
2688 SPI_DEV_TYPE_ERASE_SIZE);
2689 spi_device->block_size =
2690 1 << SPI_DEV_TYPE_FIELD(device_type,
2691 SPI_DEV_TYPE_BLOCK_SIZE);
2692
2693 spi_device->efx = efx;
2694 } else {
2695 spi_device = NULL;
2696 }
2697
2698 kfree(*spi_device_ret);
2699 *spi_device_ret = spi_device;
2700 return 0;
2701 }
2702
2703
2704 static void falcon_remove_spi_devices(struct efx_nic *efx)
2705 {
2706 kfree(efx->spi_eeprom);
2707 efx->spi_eeprom = NULL;
2708 kfree(efx->spi_flash);
2709 efx->spi_flash = NULL;
2710 }
2711
2712 /* Extract non-volatile configuration */
2713 static int falcon_probe_nvconfig(struct efx_nic *efx)
2714 {
2715 struct falcon_nvconfig *nvconfig;
2716 int board_rev;
2717 int rc;
2718
2719 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2720 if (!nvconfig)
2721 return -ENOMEM;
2722
2723 rc = falcon_read_nvram(efx, nvconfig);
2724 if (rc == -EINVAL) {
2725 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2726 efx->phy_type = PHY_TYPE_NONE;
2727 efx->mdio.prtad = MDIO_PRTAD_NONE;
2728 board_rev = 0;
2729 rc = 0;
2730 } else if (rc) {
2731 goto fail1;
2732 } else {
2733 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2734 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2735
2736 efx->phy_type = v2->port0_phy_type;
2737 efx->mdio.prtad = v2->port0_phy_addr;
2738 board_rev = le16_to_cpu(v2->board_revision);
2739
2740 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2741 rc = falcon_spi_device_init(
2742 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2743 le32_to_cpu(v3->spi_device_type
2744 [FFE_AB_SPI_DEVICE_FLASH]));
2745 if (rc)
2746 goto fail2;
2747 rc = falcon_spi_device_init(
2748 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2749 le32_to_cpu(v3->spi_device_type
2750 [FFE_AB_SPI_DEVICE_EEPROM]));
2751 if (rc)
2752 goto fail2;
2753 }
2754 }
2755
2756 /* Read the MAC addresses */
2757 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2758
2759 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2760
2761 falcon_probe_board(efx, board_rev);
2762
2763 kfree(nvconfig);
2764 return 0;
2765
2766 fail2:
2767 falcon_remove_spi_devices(efx);
2768 fail1:
2769 kfree(nvconfig);
2770 return rc;
2771 }
2772
2773 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2774 * count, port speed). Set workaround and feature flags accordingly.
2775 */
2776 static int falcon_probe_nic_variant(struct efx_nic *efx)
2777 {
2778 efx_oword_t altera_build;
2779 efx_oword_t nic_stat;
2780
2781 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2782 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2783 EFX_ERR(efx, "Falcon FPGA not supported\n");
2784 return -ENODEV;
2785 }
2786
2787 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2788
2789 switch (falcon_rev(efx)) {
2790 case FALCON_REV_A0:
2791 case 0xff:
2792 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2793 return -ENODEV;
2794
2795 case FALCON_REV_A1:
2796 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2797 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2798 return -ENODEV;
2799 }
2800 break;
2801
2802 case FALCON_REV_B0:
2803 break;
2804
2805 default:
2806 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2807 return -ENODEV;
2808 }
2809
2810 /* Initial assumed speed */
2811 efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2812
2813 return 0;
2814 }
2815
2816 /* Probe all SPI devices on the NIC */
2817 static void falcon_probe_spi_devices(struct efx_nic *efx)
2818 {
2819 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2820 int boot_dev;
2821
2822 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2823 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2824 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2825
2826 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2827 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2828 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2829 EFX_LOG(efx, "Booted from %s\n",
2830 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2831 } else {
2832 /* Disable VPD and set clock dividers to safe
2833 * values for initial programming. */
2834 boot_dev = -1;
2835 EFX_LOG(efx, "Booted from internal ASIC settings;"
2836 " setting SPI config\n");
2837 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2838 /* 125 MHz / 7 ~= 20 MHz */
2839 FRF_AB_EE_SF_CLOCK_DIV, 7,
2840 /* 125 MHz / 63 ~= 2 MHz */
2841 FRF_AB_EE_EE_CLOCK_DIV, 63);
2842 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2843 }
2844
2845 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2846 falcon_spi_device_init(efx, &efx->spi_flash,
2847 FFE_AB_SPI_DEVICE_FLASH,
2848 default_flash_type);
2849 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2850 falcon_spi_device_init(efx, &efx->spi_eeprom,
2851 FFE_AB_SPI_DEVICE_EEPROM,
2852 large_eeprom_type);
2853 }
2854
2855 int falcon_probe_nic(struct efx_nic *efx)
2856 {
2857 struct falcon_nic_data *nic_data;
2858 int rc;
2859
2860 /* Allocate storage for hardware specific data */
2861 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2862 if (!nic_data)
2863 return -ENOMEM;
2864 efx->nic_data = nic_data;
2865
2866 /* Determine number of ports etc. */
2867 rc = falcon_probe_nic_variant(efx);
2868 if (rc)
2869 goto fail1;
2870
2871 /* Probe secondary function if expected */
2872 if (FALCON_IS_DUAL_FUNC(efx)) {
2873 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2874
2875 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2876 dev))) {
2877 if (dev->bus == efx->pci_dev->bus &&
2878 dev->devfn == efx->pci_dev->devfn + 1) {
2879 nic_data->pci_dev2 = dev;
2880 break;
2881 }
2882 }
2883 if (!nic_data->pci_dev2) {
2884 EFX_ERR(efx, "failed to find secondary function\n");
2885 rc = -ENODEV;
2886 goto fail2;
2887 }
2888 }
2889
2890 /* Now we can reset the NIC */
2891 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2892 if (rc) {
2893 EFX_ERR(efx, "failed to reset NIC\n");
2894 goto fail3;
2895 }
2896
2897 /* Allocate memory for INT_KER */
2898 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2899 if (rc)
2900 goto fail4;
2901 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2902
2903 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2904 (u64)efx->irq_status.dma_addr,
2905 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2906
2907 falcon_probe_spi_devices(efx);
2908
2909 /* Read in the non-volatile configuration */
2910 rc = falcon_probe_nvconfig(efx);
2911 if (rc)
2912 goto fail5;
2913
2914 /* Initialise I2C adapter */
2915 efx->i2c_adap.owner = THIS_MODULE;
2916 nic_data->i2c_data = falcon_i2c_bit_operations;
2917 nic_data->i2c_data.data = efx;
2918 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2919 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2920 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2921 rc = i2c_bit_add_bus(&efx->i2c_adap);
2922 if (rc)
2923 goto fail5;
2924
2925 return 0;
2926
2927 fail5:
2928 falcon_remove_spi_devices(efx);
2929 falcon_free_buffer(efx, &efx->irq_status);
2930 fail4:
2931 fail3:
2932 if (nic_data->pci_dev2) {
2933 pci_dev_put(nic_data->pci_dev2);
2934 nic_data->pci_dev2 = NULL;
2935 }
2936 fail2:
2937 fail1:
2938 kfree(efx->nic_data);
2939 return rc;
2940 }
2941
2942 static void falcon_init_rx_cfg(struct efx_nic *efx)
2943 {
2944 /* Prior to Siena the RX DMA engine will split each frame at
2945 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2946 * be so large that that never happens. */
2947 const unsigned huge_buf_size = (3 * 4096) >> 5;
2948 /* RX control FIFO thresholds (32 entries) */
2949 const unsigned ctrl_xon_thr = 20;
2950 const unsigned ctrl_xoff_thr = 25;
2951 /* RX data FIFO thresholds (256-byte units; size varies) */
2952 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2953 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2954 efx_oword_t reg;
2955
2956 efx_reado(efx, &reg, FR_AZ_RX_CFG);
2957 if (falcon_rev(efx) <= FALCON_REV_A1) {
2958 /* Data FIFO size is 5.5K */
2959 if (data_xon_thr < 0)
2960 data_xon_thr = 512 >> 8;
2961 if (data_xoff_thr < 0)
2962 data_xoff_thr = 2048 >> 8;
2963 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2964 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2965 huge_buf_size);
2966 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2967 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2968 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2969 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2970 } else {
2971 /* Data FIFO size is 80K; register fields moved */
2972 if (data_xon_thr < 0)
2973 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2974 if (data_xoff_thr < 0)
2975 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2976 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2977 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2978 huge_buf_size);
2979 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2980 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2981 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2982 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2983 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2984 }
2985 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2986 }
2987
2988 /* This call performs hardware-specific global initialisation, such as
2989 * defining the descriptor cache sizes and number of RSS channels.
2990 * It does not set up any buffers, descriptor rings or event queues.
2991 */
2992 int falcon_init_nic(struct efx_nic *efx)
2993 {
2994 efx_oword_t temp;
2995 int rc;
2996
2997 /* Use on-chip SRAM */
2998 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2999 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
3000 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
3001
3002 /* Set the source of the GMAC clock */
3003 if (falcon_rev(efx) == FALCON_REV_B0) {
3004 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
3005 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
3006 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
3007 }
3008
3009 rc = falcon_reset_sram(efx);
3010 if (rc)
3011 return rc;
3012
3013 /* Set positions of descriptor caches in SRAM. */
3014 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
3015 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3016 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
3017 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3018
3019 /* Set TX descriptor cache size. */
3020 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
3021 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3022 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
3023
3024 /* Set RX descriptor cache size. Set low watermark to size-8, as
3025 * this allows most efficient prefetching.
3026 */
3027 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
3028 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3029 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3030 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3031 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3032
3033 /* Clear the parity enables on the TX data fifos as
3034 * they produce false parity errors because of timing issues
3035 */
3036 if (EFX_WORKAROUND_5129(efx)) {
3037 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3038 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3039 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
3040 }
3041
3042 /* Enable all the genuinely fatal interrupts. (They are still
3043 * masked by the overall interrupt mask, controlled by
3044 * falcon_interrupts()).
3045 *
3046 * Note: All other fatal interrupts are enabled
3047 */
3048 EFX_POPULATE_OWORD_3(temp,
3049 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3050 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3051 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3052 EFX_INVERT_OWORD(temp);
3053 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3054
3055 if (EFX_WORKAROUND_7244(efx)) {
3056 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3057 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3058 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3059 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3060 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3061 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3062 }
3063
3064 falcon_setup_rss_indir_table(efx);
3065
3066 /* XXX This is documented only for Falcon A0/A1 */
3067 /* Setup RX. Wait for descriptor is broken and must
3068 * be disabled. RXDP recovery shouldn't be needed, but is.
3069 */
3070 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3071 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3072 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3073 if (EFX_WORKAROUND_5583(efx))
3074 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3075 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3076
3077 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3078 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3079 */
3080 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3081 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3082 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3083 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3084 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3085 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3086 /* Enable SW_EV to inherit in char driver - assume harmless here */
3087 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3088 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3089 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3090 /* Squash TX of packets of 16 bytes or less */
3091 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3092 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3093 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3094
3095 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3096 * descriptors (which is bad).
3097 */
3098 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3099 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3100 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3101
3102 falcon_init_rx_cfg(efx);
3103
3104 /* Set destination of both TX and RX Flush events */
3105 if (falcon_rev(efx) >= FALCON_REV_B0) {
3106 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3107 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3108 }
3109
3110 return 0;
3111 }
3112
3113 void falcon_remove_nic(struct efx_nic *efx)
3114 {
3115 struct falcon_nic_data *nic_data = efx->nic_data;
3116 int rc;
3117
3118 /* Remove I2C adapter and clear it in preparation for a retry */
3119 rc = i2c_del_adapter(&efx->i2c_adap);
3120 BUG_ON(rc);
3121 memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
3122
3123 falcon_remove_spi_devices(efx);
3124 falcon_free_buffer(efx, &efx->irq_status);
3125
3126 falcon_reset_hw(efx, RESET_TYPE_ALL);
3127
3128 /* Release the second function after the reset */
3129 if (nic_data->pci_dev2) {
3130 pci_dev_put(nic_data->pci_dev2);
3131 nic_data->pci_dev2 = NULL;
3132 }
3133
3134 /* Tear down the private nic state */
3135 kfree(efx->nic_data);
3136 efx->nic_data = NULL;
3137 }
3138
3139 void falcon_update_nic_stats(struct efx_nic *efx)
3140 {
3141 efx_oword_t cnt;
3142
3143 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3144 efx->n_rx_nodesc_drop_cnt +=
3145 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3146 }
3147
3148 /**************************************************************************
3149 *
3150 * Revision-dependent attributes used by efx.c
3151 *
3152 **************************************************************************
3153 */
3154
3155 struct efx_nic_type falcon_a_nic_type = {
3156 .mem_bar = 2,
3157 .mem_map_size = 0x20000,
3158 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3159 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3160 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3161 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3162 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3163 .txd_ring_mask = FALCON_TXD_RING_MASK,
3164 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3165 .evq_size = FALCON_EVQ_SIZE,
3166 .max_dma_mask = FALCON_DMA_MASK,
3167 .tx_dma_mask = FALCON_TX_DMA_MASK,
3168 .bug5391_mask = 0xf,
3169 .rx_buffer_padding = 0x24,
3170 .max_interrupt_mode = EFX_INT_MODE_MSI,
3171 .phys_addr_channels = 4,
3172 };
3173
3174 struct efx_nic_type falcon_b_nic_type = {
3175 .mem_bar = 2,
3176 /* Map everything up to and including the RSS indirection
3177 * table. Don't map MSI-X table, MSI-X PBA since Linux
3178 * requires that they not be mapped. */
3179 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3180 FR_BZ_RX_INDIRECTION_TBL_STEP *
3181 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3182 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3183 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3184 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3185 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3186 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3187 .txd_ring_mask = FALCON_TXD_RING_MASK,
3188 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3189 .evq_size = FALCON_EVQ_SIZE,
3190 .max_dma_mask = FALCON_DMA_MASK,
3191 .tx_dma_mask = FALCON_TX_DMA_MASK,
3192 .bug5391_mask = 0,
3193 .rx_buffer_padding = 0,
3194 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3195 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3196 * interrupt handler only supports 32
3197 * channels */
3198 };
3199
Linux kernel - Deliverables
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