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[deliverable/linux.git] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "falcon.h"
25 #include "regs.h"
26 #include "falcon_io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "workarounds.h"
30
31 /* Falcon hardware control.
32 * Falcon is the internal codename for the SFC4000 controller that is
33 * present in SFE400X evaluation boards
34 */
35
36 /**
37 * struct falcon_nic_data - Falcon NIC state
38 * @next_buffer_table: First available buffer table id
39 * @pci_dev2: The secondary PCI device if present
40 * @i2c_data: Operations and state for I2C bit-bashing algorithm
41 * @int_error_count: Number of internal errors seen recently
42 * @int_error_expire: Time at which error count will be expired
43 */
44 struct falcon_nic_data {
45 unsigned next_buffer_table;
46 struct pci_dev *pci_dev2;
47 struct i2c_algo_bit_data i2c_data;
48
49 unsigned int_error_count;
50 unsigned long int_error_expire;
51 };
52
53 /**************************************************************************
54 *
55 * Configurable values
56 *
57 **************************************************************************
58 */
59
60 static int disable_dma_stats;
61
62 /* This is set to 16 for a good reason. In summary, if larger than
63 * 16, the descriptor cache holds more than a default socket
64 * buffer's worth of packets (for UDP we can only have at most one
65 * socket buffer's worth outstanding). This combined with the fact
66 * that we only get 1 TX event per descriptor cache means the NIC
67 * goes idle.
68 */
69 #define TX_DC_ENTRIES 16
70 #define TX_DC_ENTRIES_ORDER 0
71 #define TX_DC_BASE 0x130000
72
73 #define RX_DC_ENTRIES 64
74 #define RX_DC_ENTRIES_ORDER 2
75 #define RX_DC_BASE 0x100000
76
77 static const unsigned int
78 /* "Large" EEPROM device: Atmel AT25640 or similar
79 * 8 KB, 16-bit address, 32 B write block */
80 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
81 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
82 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
83 /* Default flash device: Atmel AT25F1024
84 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
85 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
86 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
87 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
88 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
89 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
90
91 /* RX FIFO XOFF watermark
92 *
93 * When the amount of the RX FIFO increases used increases past this
94 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
95 * This also has an effect on RX/TX arbitration
96 */
97 static int rx_xoff_thresh_bytes = -1;
98 module_param(rx_xoff_thresh_bytes, int, 0644);
99 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
100
101 /* RX FIFO XON watermark
102 *
103 * When the amount of the RX FIFO used decreases below this
104 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
105 * This also has an effect on RX/TX arbitration
106 */
107 static int rx_xon_thresh_bytes = -1;
108 module_param(rx_xon_thresh_bytes, int, 0644);
109 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
110
111 /* TX descriptor ring size - min 512 max 4k */
112 #define FALCON_TXD_RING_ORDER FFE_AZ_TX_DESCQ_SIZE_1K
113 #define FALCON_TXD_RING_SIZE 1024
114 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
115
116 /* RX descriptor ring size - min 512 max 4k */
117 #define FALCON_RXD_RING_ORDER FFE_AZ_RX_DESCQ_SIZE_1K
118 #define FALCON_RXD_RING_SIZE 1024
119 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
120
121 /* Event queue size - max 32k */
122 #define FALCON_EVQ_ORDER FFE_AZ_EVQ_SIZE_4K
123 #define FALCON_EVQ_SIZE 4096
124 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
125
126 /* If FALCON_MAX_INT_ERRORS internal errors occur within
127 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
128 * disable it.
129 */
130 #define FALCON_INT_ERROR_EXPIRE 3600
131 #define FALCON_MAX_INT_ERRORS 5
132
133 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
134 */
135 #define FALCON_FLUSH_INTERVAL 10
136 #define FALCON_FLUSH_POLL_COUNT 100
137
138 /**************************************************************************
139 *
140 * Falcon constants
141 *
142 **************************************************************************
143 */
144
145 /* DMA address mask */
146 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
147
148 /* TX DMA length mask (13-bit) */
149 #define FALCON_TX_DMA_MASK (4096 - 1)
150
151 /* Size and alignment of special buffers (4KB) */
152 #define FALCON_BUF_SIZE 4096
153
154 /* Dummy SRAM size code */
155 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
156
157 #define FALCON_IS_DUAL_FUNC(efx) \
158 (falcon_rev(efx) < FALCON_REV_B0)
159
160 /**************************************************************************
161 *
162 * Falcon hardware access
163 *
164 **************************************************************************/
165
166 /* Read the current event from the event queue */
167 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
168 unsigned int index)
169 {
170 return (((efx_qword_t *) (channel->eventq.addr)) + index);
171 }
172
173 /* See if an event is present
174 *
175 * We check both the high and low dword of the event for all ones. We
176 * wrote all ones when we cleared the event, and no valid event can
177 * have all ones in either its high or low dwords. This approach is
178 * robust against reordering.
179 *
180 * Note that using a single 64-bit comparison is incorrect; even
181 * though the CPU read will be atomic, the DMA write may not be.
182 */
183 static inline int falcon_event_present(efx_qword_t *event)
184 {
185 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
186 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
187 }
188
189 /**************************************************************************
190 *
191 * I2C bus - this is a bit-bashing interface using GPIO pins
192 * Note that it uses the output enables to tristate the outputs
193 * SDA is the data pin and SCL is the clock
194 *
195 **************************************************************************
196 */
197 static void falcon_setsda(void *data, int state)
198 {
199 struct efx_nic *efx = (struct efx_nic *)data;
200 efx_oword_t reg;
201
202 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
203 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
204 falcon_write(efx, &reg, FR_AB_GPIO_CTL);
205 }
206
207 static void falcon_setscl(void *data, int state)
208 {
209 struct efx_nic *efx = (struct efx_nic *)data;
210 efx_oword_t reg;
211
212 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
213 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
214 falcon_write(efx, &reg, FR_AB_GPIO_CTL);
215 }
216
217 static int falcon_getsda(void *data)
218 {
219 struct efx_nic *efx = (struct efx_nic *)data;
220 efx_oword_t reg;
221
222 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
223 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
224 }
225
226 static int falcon_getscl(void *data)
227 {
228 struct efx_nic *efx = (struct efx_nic *)data;
229 efx_oword_t reg;
230
231 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
232 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
233 }
234
235 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
236 .setsda = falcon_setsda,
237 .setscl = falcon_setscl,
238 .getsda = falcon_getsda,
239 .getscl = falcon_getscl,
240 .udelay = 5,
241 /* Wait up to 50 ms for slave to let us pull SCL high */
242 .timeout = DIV_ROUND_UP(HZ, 20),
243 };
244
245 /**************************************************************************
246 *
247 * Falcon special buffer handling
248 * Special buffers are used for event queues and the TX and RX
249 * descriptor rings.
250 *
251 *************************************************************************/
252
253 /*
254 * Initialise a Falcon special buffer
255 *
256 * This will define a buffer (previously allocated via
257 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
258 * it to be used for event queues, descriptor rings etc.
259 */
260 static void
261 falcon_init_special_buffer(struct efx_nic *efx,
262 struct efx_special_buffer *buffer)
263 {
264 efx_qword_t buf_desc;
265 int index;
266 dma_addr_t dma_addr;
267 int i;
268
269 EFX_BUG_ON_PARANOID(!buffer->addr);
270
271 /* Write buffer descriptors to NIC */
272 for (i = 0; i < buffer->entries; i++) {
273 index = buffer->index + i;
274 dma_addr = buffer->dma_addr + (i * 4096);
275 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
276 index, (unsigned long long)dma_addr);
277 EFX_POPULATE_QWORD_3(buf_desc,
278 FRF_AZ_BUF_ADR_REGION, 0,
279 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
280 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
281 falcon_write_sram(efx, &buf_desc, index);
282 }
283 }
284
285 /* Unmaps a buffer from Falcon and clears the buffer table entries */
286 static void
287 falcon_fini_special_buffer(struct efx_nic *efx,
288 struct efx_special_buffer *buffer)
289 {
290 efx_oword_t buf_tbl_upd;
291 unsigned int start = buffer->index;
292 unsigned int end = (buffer->index + buffer->entries - 1);
293
294 if (!buffer->entries)
295 return;
296
297 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
298 buffer->index, buffer->index + buffer->entries - 1);
299
300 EFX_POPULATE_OWORD_4(buf_tbl_upd,
301 FRF_AZ_BUF_UPD_CMD, 0,
302 FRF_AZ_BUF_CLR_CMD, 1,
303 FRF_AZ_BUF_CLR_END_ID, end,
304 FRF_AZ_BUF_CLR_START_ID, start);
305 falcon_write(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
306 }
307
308 /*
309 * Allocate a new Falcon special buffer
310 *
311 * This allocates memory for a new buffer, clears it and allocates a
312 * new buffer ID range. It does not write into Falcon's buffer table.
313 *
314 * This call will allocate 4KB buffers, since Falcon can't use 8KB
315 * buffers for event queues and descriptor rings.
316 */
317 static int falcon_alloc_special_buffer(struct efx_nic *efx,
318 struct efx_special_buffer *buffer,
319 unsigned int len)
320 {
321 struct falcon_nic_data *nic_data = efx->nic_data;
322
323 len = ALIGN(len, FALCON_BUF_SIZE);
324
325 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
326 &buffer->dma_addr);
327 if (!buffer->addr)
328 return -ENOMEM;
329 buffer->len = len;
330 buffer->entries = len / FALCON_BUF_SIZE;
331 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
332
333 /* All zeros is a potentially valid event so memset to 0xff */
334 memset(buffer->addr, 0xff, len);
335
336 /* Select new buffer ID */
337 buffer->index = nic_data->next_buffer_table;
338 nic_data->next_buffer_table += buffer->entries;
339
340 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
341 "(virt %p phys %llx)\n", buffer->index,
342 buffer->index + buffer->entries - 1,
343 (u64)buffer->dma_addr, len,
344 buffer->addr, (u64)virt_to_phys(buffer->addr));
345
346 return 0;
347 }
348
349 static void falcon_free_special_buffer(struct efx_nic *efx,
350 struct efx_special_buffer *buffer)
351 {
352 if (!buffer->addr)
353 return;
354
355 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
356 "(virt %p phys %llx)\n", buffer->index,
357 buffer->index + buffer->entries - 1,
358 (u64)buffer->dma_addr, buffer->len,
359 buffer->addr, (u64)virt_to_phys(buffer->addr));
360
361 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
362 buffer->dma_addr);
363 buffer->addr = NULL;
364 buffer->entries = 0;
365 }
366
367 /**************************************************************************
368 *
369 * Falcon generic buffer handling
370 * These buffers are used for interrupt status and MAC stats
371 *
372 **************************************************************************/
373
374 static int falcon_alloc_buffer(struct efx_nic *efx,
375 struct efx_buffer *buffer, unsigned int len)
376 {
377 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
378 &buffer->dma_addr);
379 if (!buffer->addr)
380 return -ENOMEM;
381 buffer->len = len;
382 memset(buffer->addr, 0, len);
383 return 0;
384 }
385
386 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
387 {
388 if (buffer->addr) {
389 pci_free_consistent(efx->pci_dev, buffer->len,
390 buffer->addr, buffer->dma_addr);
391 buffer->addr = NULL;
392 }
393 }
394
395 /**************************************************************************
396 *
397 * Falcon TX path
398 *
399 **************************************************************************/
400
401 /* Returns a pointer to the specified transmit descriptor in the TX
402 * descriptor queue belonging to the specified channel.
403 */
404 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
405 unsigned int index)
406 {
407 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
408 }
409
410 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
411 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
412 {
413 unsigned write_ptr;
414 efx_dword_t reg;
415
416 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
417 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
418 falcon_writel_page(tx_queue->efx, &reg,
419 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
420 }
421
422
423 /* For each entry inserted into the software descriptor ring, create a
424 * descriptor in the hardware TX descriptor ring (in host memory), and
425 * write a doorbell.
426 */
427 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
428 {
429
430 struct efx_tx_buffer *buffer;
431 efx_qword_t *txd;
432 unsigned write_ptr;
433
434 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
435
436 do {
437 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
438 buffer = &tx_queue->buffer[write_ptr];
439 txd = falcon_tx_desc(tx_queue, write_ptr);
440 ++tx_queue->write_count;
441
442 /* Create TX descriptor ring entry */
443 EFX_POPULATE_QWORD_4(*txd,
444 FSF_AZ_TX_KER_CONT, buffer->continuation,
445 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
446 FSF_AZ_TX_KER_BUF_REGION, 0,
447 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
448 } while (tx_queue->write_count != tx_queue->insert_count);
449
450 wmb(); /* Ensure descriptors are written before they are fetched */
451 falcon_notify_tx_desc(tx_queue);
452 }
453
454 /* Allocate hardware resources for a TX queue */
455 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
456 {
457 struct efx_nic *efx = tx_queue->efx;
458 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
459 FALCON_TXD_RING_SIZE *
460 sizeof(efx_qword_t));
461 }
462
463 void falcon_init_tx(struct efx_tx_queue *tx_queue)
464 {
465 efx_oword_t tx_desc_ptr;
466 struct efx_nic *efx = tx_queue->efx;
467
468 tx_queue->flushed = false;
469
470 /* Pin TX descriptor ring */
471 falcon_init_special_buffer(efx, &tx_queue->txd);
472
473 /* Push TX descriptor ring to card */
474 EFX_POPULATE_OWORD_10(tx_desc_ptr,
475 FRF_AZ_TX_DESCQ_EN, 1,
476 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
477 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
478 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
479 FRF_AZ_TX_DESCQ_EVQ_ID,
480 tx_queue->channel->channel,
481 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
482 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
483 FRF_AZ_TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
484 FRF_AZ_TX_DESCQ_TYPE, 0,
485 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
486
487 if (falcon_rev(efx) >= FALCON_REV_B0) {
488 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
489 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
490 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
491 !csum);
492 }
493
494 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
495 tx_queue->queue);
496
497 if (falcon_rev(efx) < FALCON_REV_B0) {
498 efx_oword_t reg;
499
500 /* Only 128 bits in this register */
501 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
502
503 falcon_read(efx, &reg, FR_AA_TX_CHKSM_CFG);
504 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
505 clear_bit_le(tx_queue->queue, (void *)&reg);
506 else
507 set_bit_le(tx_queue->queue, (void *)&reg);
508 falcon_write(efx, &reg, FR_AA_TX_CHKSM_CFG);
509 }
510 }
511
512 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
513 {
514 struct efx_nic *efx = tx_queue->efx;
515 efx_oword_t tx_flush_descq;
516
517 /* Post a flush command */
518 EFX_POPULATE_OWORD_2(tx_flush_descq,
519 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
520 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
521 falcon_write(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
522 }
523
524 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
525 {
526 struct efx_nic *efx = tx_queue->efx;
527 efx_oword_t tx_desc_ptr;
528
529 /* The queue should have been flushed */
530 WARN_ON(!tx_queue->flushed);
531
532 /* Remove TX descriptor ring from card */
533 EFX_ZERO_OWORD(tx_desc_ptr);
534 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
535 tx_queue->queue);
536
537 /* Unpin TX descriptor ring */
538 falcon_fini_special_buffer(efx, &tx_queue->txd);
539 }
540
541 /* Free buffers backing TX queue */
542 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
543 {
544 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
545 }
546
547 /**************************************************************************
548 *
549 * Falcon RX path
550 *
551 **************************************************************************/
552
553 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
554 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
555 unsigned int index)
556 {
557 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
558 }
559
560 /* This creates an entry in the RX descriptor queue */
561 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
562 unsigned index)
563 {
564 struct efx_rx_buffer *rx_buf;
565 efx_qword_t *rxd;
566
567 rxd = falcon_rx_desc(rx_queue, index);
568 rx_buf = efx_rx_buffer(rx_queue, index);
569 EFX_POPULATE_QWORD_3(*rxd,
570 FSF_AZ_RX_KER_BUF_SIZE,
571 rx_buf->len -
572 rx_queue->efx->type->rx_buffer_padding,
573 FSF_AZ_RX_KER_BUF_REGION, 0,
574 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
575 }
576
577 /* This writes to the RX_DESC_WPTR register for the specified receive
578 * descriptor ring.
579 */
580 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
581 {
582 efx_dword_t reg;
583 unsigned write_ptr;
584
585 while (rx_queue->notified_count != rx_queue->added_count) {
586 falcon_build_rx_desc(rx_queue,
587 rx_queue->notified_count &
588 FALCON_RXD_RING_MASK);
589 ++rx_queue->notified_count;
590 }
591
592 wmb();
593 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
594 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
595 falcon_writel_page(rx_queue->efx, &reg,
596 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
597 }
598
599 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
600 {
601 struct efx_nic *efx = rx_queue->efx;
602 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
603 FALCON_RXD_RING_SIZE *
604 sizeof(efx_qword_t));
605 }
606
607 void falcon_init_rx(struct efx_rx_queue *rx_queue)
608 {
609 efx_oword_t rx_desc_ptr;
610 struct efx_nic *efx = rx_queue->efx;
611 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
612 bool iscsi_digest_en = is_b0;
613
614 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
615 rx_queue->queue, rx_queue->rxd.index,
616 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
617
618 rx_queue->flushed = false;
619
620 /* Pin RX descriptor ring */
621 falcon_init_special_buffer(efx, &rx_queue->rxd);
622
623 /* Push RX descriptor ring to card */
624 EFX_POPULATE_OWORD_10(rx_desc_ptr,
625 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
626 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
627 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
628 FRF_AZ_RX_DESCQ_EVQ_ID,
629 rx_queue->channel->channel,
630 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
631 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
632 FRF_AZ_RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
633 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
634 /* For >=B0 this is scatter so disable */
635 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
636 FRF_AZ_RX_DESCQ_EN, 1);
637 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
638 rx_queue->queue);
639 }
640
641 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
642 {
643 struct efx_nic *efx = rx_queue->efx;
644 efx_oword_t rx_flush_descq;
645
646 /* Post a flush command */
647 EFX_POPULATE_OWORD_2(rx_flush_descq,
648 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
649 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
650 falcon_write(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
651 }
652
653 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
654 {
655 efx_oword_t rx_desc_ptr;
656 struct efx_nic *efx = rx_queue->efx;
657
658 /* The queue should already have been flushed */
659 WARN_ON(!rx_queue->flushed);
660
661 /* Remove RX descriptor ring from card */
662 EFX_ZERO_OWORD(rx_desc_ptr);
663 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
664 rx_queue->queue);
665
666 /* Unpin RX descriptor ring */
667 falcon_fini_special_buffer(efx, &rx_queue->rxd);
668 }
669
670 /* Free buffers backing RX queue */
671 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
672 {
673 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
674 }
675
676 /**************************************************************************
677 *
678 * Falcon event queue processing
679 * Event queues are processed by per-channel tasklets.
680 *
681 **************************************************************************/
682
683 /* Update a channel's event queue's read pointer (RPTR) register
684 *
685 * This writes the EVQ_RPTR_REG register for the specified channel's
686 * event queue.
687 *
688 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
689 * whereas channel->eventq_read_ptr contains the index of the "next to
690 * read" event.
691 */
692 void falcon_eventq_read_ack(struct efx_channel *channel)
693 {
694 efx_dword_t reg;
695 struct efx_nic *efx = channel->efx;
696
697 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
698 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
699 channel->channel);
700 }
701
702 /* Use HW to insert a SW defined event */
703 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
704 {
705 efx_oword_t drv_ev_reg;
706
707 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
708 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
709 drv_ev_reg.u32[0] = event->u32[0];
710 drv_ev_reg.u32[1] = event->u32[1];
711 drv_ev_reg.u32[2] = 0;
712 drv_ev_reg.u32[3] = 0;
713 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
714 falcon_write(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
715 }
716
717 /* Handle a transmit completion event
718 *
719 * Falcon batches TX completion events; the message we receive is of
720 * the form "complete all TX events up to this index".
721 */
722 static void falcon_handle_tx_event(struct efx_channel *channel,
723 efx_qword_t *event)
724 {
725 unsigned int tx_ev_desc_ptr;
726 unsigned int tx_ev_q_label;
727 struct efx_tx_queue *tx_queue;
728 struct efx_nic *efx = channel->efx;
729
730 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
731 /* Transmit completion */
732 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
733 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
734 tx_queue = &efx->tx_queue[tx_ev_q_label];
735 channel->irq_mod_score +=
736 (tx_ev_desc_ptr - tx_queue->read_count) &
737 efx->type->txd_ring_mask;
738 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
739 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
740 /* Rewrite the FIFO write pointer */
741 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
742 tx_queue = &efx->tx_queue[tx_ev_q_label];
743
744 if (efx_dev_registered(efx))
745 netif_tx_lock(efx->net_dev);
746 falcon_notify_tx_desc(tx_queue);
747 if (efx_dev_registered(efx))
748 netif_tx_unlock(efx->net_dev);
749 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
750 EFX_WORKAROUND_10727(efx)) {
751 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
752 } else {
753 EFX_ERR(efx, "channel %d unexpected TX event "
754 EFX_QWORD_FMT"\n", channel->channel,
755 EFX_QWORD_VAL(*event));
756 }
757 }
758
759 /* Detect errors included in the rx_evt_pkt_ok bit. */
760 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
761 const efx_qword_t *event,
762 bool *rx_ev_pkt_ok,
763 bool *discard)
764 {
765 struct efx_nic *efx = rx_queue->efx;
766 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
767 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
768 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
769 bool rx_ev_other_err, rx_ev_pause_frm;
770 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
771 unsigned rx_ev_pkt_type;
772
773 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
774 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
775 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
776 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
777 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
778 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
779 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
780 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
781 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
782 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
783 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
784 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
785 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
786 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
787 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
788 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
789
790 /* Every error apart from tobe_disc and pause_frm */
791 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
792 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
793 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
794
795 /* Count errors that are not in MAC stats. Ignore expected
796 * checksum errors during self-test. */
797 if (rx_ev_frm_trunc)
798 ++rx_queue->channel->n_rx_frm_trunc;
799 else if (rx_ev_tobe_disc)
800 ++rx_queue->channel->n_rx_tobe_disc;
801 else if (!efx->loopback_selftest) {
802 if (rx_ev_ip_hdr_chksum_err)
803 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
804 else if (rx_ev_tcp_udp_chksum_err)
805 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
806 }
807 if (rx_ev_ip_frag_err)
808 ++rx_queue->channel->n_rx_ip_frag_err;
809
810 /* The frame must be discarded if any of these are true. */
811 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
812 rx_ev_tobe_disc | rx_ev_pause_frm);
813
814 /* TOBE_DISC is expected on unicast mismatches; don't print out an
815 * error message. FRM_TRUNC indicates RXDP dropped the packet due
816 * to a FIFO overflow.
817 */
818 #ifdef EFX_ENABLE_DEBUG
819 if (rx_ev_other_err) {
820 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
821 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
822 rx_queue->queue, EFX_QWORD_VAL(*event),
823 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
824 rx_ev_ip_hdr_chksum_err ?
825 " [IP_HDR_CHKSUM_ERR]" : "",
826 rx_ev_tcp_udp_chksum_err ?
827 " [TCP_UDP_CHKSUM_ERR]" : "",
828 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
829 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
830 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
831 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
832 rx_ev_pause_frm ? " [PAUSE]" : "");
833 }
834 #endif
835 }
836
837 /* Handle receive events that are not in-order. */
838 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
839 unsigned index)
840 {
841 struct efx_nic *efx = rx_queue->efx;
842 unsigned expected, dropped;
843
844 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
845 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
846 FALCON_RXD_RING_MASK);
847 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
848 dropped, index, expected);
849
850 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
851 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
852 }
853
854 /* Handle a packet received event
855 *
856 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
857 * wrong destination address
858 * Also "is multicast" and "matches multicast filter" flags can be used to
859 * discard non-matching multicast packets.
860 */
861 static void falcon_handle_rx_event(struct efx_channel *channel,
862 const efx_qword_t *event)
863 {
864 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
865 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
866 unsigned expected_ptr;
867 bool rx_ev_pkt_ok, discard = false, checksummed;
868 struct efx_rx_queue *rx_queue;
869 struct efx_nic *efx = channel->efx;
870
871 /* Basic packet information */
872 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
873 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
874 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
875 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
876 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
877 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
878 channel->channel);
879
880 rx_queue = &efx->rx_queue[channel->channel];
881
882 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
883 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
884 if (unlikely(rx_ev_desc_ptr != expected_ptr))
885 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
886
887 if (likely(rx_ev_pkt_ok)) {
888 /* If packet is marked as OK and packet type is TCP/IPv4 or
889 * UDP/IPv4, then we can rely on the hardware checksum.
890 */
891 checksummed =
892 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
893 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP;
894 } else {
895 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
896 &discard);
897 checksummed = false;
898 }
899
900 /* Detect multicast packets that didn't match the filter */
901 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
902 if (rx_ev_mcast_pkt) {
903 unsigned int rx_ev_mcast_hash_match =
904 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
905
906 if (unlikely(!rx_ev_mcast_hash_match))
907 discard = true;
908 }
909
910 channel->irq_mod_score += 2;
911
912 /* Handle received packet */
913 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
914 checksummed, discard);
915 }
916
917 /* Global events are basically PHY events */
918 static void falcon_handle_global_event(struct efx_channel *channel,
919 efx_qword_t *event)
920 {
921 struct efx_nic *efx = channel->efx;
922 bool handled = false;
923
924 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
925 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
926 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
927 efx->phy_op->clear_interrupt(efx);
928 queue_work(efx->workqueue, &efx->phy_work);
929 handled = true;
930 }
931
932 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
933 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
934 queue_work(efx->workqueue, &efx->mac_work);
935 handled = true;
936 }
937
938 if (falcon_rev(efx) <= FALCON_REV_A1 ?
939 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
940 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
941 EFX_ERR(efx, "channel %d seen global RX_RESET "
942 "event. Resetting.\n", channel->channel);
943
944 atomic_inc(&efx->rx_reset);
945 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
946 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
947 handled = true;
948 }
949
950 if (!handled)
951 EFX_ERR(efx, "channel %d unknown global event "
952 EFX_QWORD_FMT "\n", channel->channel,
953 EFX_QWORD_VAL(*event));
954 }
955
956 static void falcon_handle_driver_event(struct efx_channel *channel,
957 efx_qword_t *event)
958 {
959 struct efx_nic *efx = channel->efx;
960 unsigned int ev_sub_code;
961 unsigned int ev_sub_data;
962
963 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
964 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
965
966 switch (ev_sub_code) {
967 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
968 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
969 channel->channel, ev_sub_data);
970 break;
971 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
972 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
973 channel->channel, ev_sub_data);
974 break;
975 case FSE_AZ_EVQ_INIT_DONE_EV:
976 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
977 channel->channel, ev_sub_data);
978 break;
979 case FSE_AZ_SRM_UPD_DONE_EV:
980 EFX_TRACE(efx, "channel %d SRAM update done\n",
981 channel->channel);
982 break;
983 case FSE_AZ_WAKE_UP_EV:
984 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
985 channel->channel, ev_sub_data);
986 break;
987 case FSE_AZ_TIMER_EV:
988 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
989 channel->channel, ev_sub_data);
990 break;
991 case FSE_AA_RX_RECOVER_EV:
992 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
993 "Resetting.\n", channel->channel);
994 atomic_inc(&efx->rx_reset);
995 efx_schedule_reset(efx,
996 EFX_WORKAROUND_6555(efx) ?
997 RESET_TYPE_RX_RECOVERY :
998 RESET_TYPE_DISABLE);
999 break;
1000 case FSE_BZ_RX_DSC_ERROR_EV:
1001 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1002 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1003 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1004 break;
1005 case FSE_BZ_TX_DSC_ERROR_EV:
1006 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1007 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1008 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1009 break;
1010 default:
1011 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1012 "data %04x\n", channel->channel, ev_sub_code,
1013 ev_sub_data);
1014 break;
1015 }
1016 }
1017
1018 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1019 {
1020 unsigned int read_ptr;
1021 efx_qword_t event, *p_event;
1022 int ev_code;
1023 int rx_packets = 0;
1024
1025 read_ptr = channel->eventq_read_ptr;
1026
1027 do {
1028 p_event = falcon_event(channel, read_ptr);
1029 event = *p_event;
1030
1031 if (!falcon_event_present(&event))
1032 /* End of events */
1033 break;
1034
1035 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1036 channel->channel, EFX_QWORD_VAL(event));
1037
1038 /* Clear this event by marking it all ones */
1039 EFX_SET_QWORD(*p_event);
1040
1041 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1042
1043 switch (ev_code) {
1044 case FSE_AZ_EV_CODE_RX_EV:
1045 falcon_handle_rx_event(channel, &event);
1046 ++rx_packets;
1047 break;
1048 case FSE_AZ_EV_CODE_TX_EV:
1049 falcon_handle_tx_event(channel, &event);
1050 break;
1051 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1052 channel->eventq_magic = EFX_QWORD_FIELD(
1053 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1054 EFX_LOG(channel->efx, "channel %d received generated "
1055 "event "EFX_QWORD_FMT"\n", channel->channel,
1056 EFX_QWORD_VAL(event));
1057 break;
1058 case FSE_AZ_EV_CODE_GLOBAL_EV:
1059 falcon_handle_global_event(channel, &event);
1060 break;
1061 case FSE_AZ_EV_CODE_DRIVER_EV:
1062 falcon_handle_driver_event(channel, &event);
1063 break;
1064 default:
1065 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1066 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1067 ev_code, EFX_QWORD_VAL(event));
1068 }
1069
1070 /* Increment read pointer */
1071 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1072
1073 } while (rx_packets < rx_quota);
1074
1075 channel->eventq_read_ptr = read_ptr;
1076 return rx_packets;
1077 }
1078
1079 void falcon_set_int_moderation(struct efx_channel *channel)
1080 {
1081 efx_dword_t timer_cmd;
1082 struct efx_nic *efx = channel->efx;
1083
1084 /* Set timer register */
1085 if (channel->irq_moderation) {
1086 /* Round to resolution supported by hardware. The value we
1087 * program is based at 0. So actual interrupt moderation
1088 * achieved is ((x + 1) * res).
1089 */
1090 channel->irq_moderation -= (channel->irq_moderation %
1091 FALCON_IRQ_MOD_RESOLUTION);
1092 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION)
1093 channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION;
1094 EFX_POPULATE_DWORD_2(timer_cmd,
1095 FRF_AB_TC_TIMER_MODE,
1096 FFE_BB_TIMER_MODE_INT_HLDOFF,
1097 FRF_AB_TC_TIMER_VAL,
1098 channel->irq_moderation /
1099 FALCON_IRQ_MOD_RESOLUTION - 1);
1100 } else {
1101 EFX_POPULATE_DWORD_2(timer_cmd,
1102 FRF_AB_TC_TIMER_MODE,
1103 FFE_BB_TIMER_MODE_DIS,
1104 FRF_AB_TC_TIMER_VAL, 0);
1105 }
1106 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1107 falcon_writel_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1108 channel->channel);
1109
1110 }
1111
1112 /* Allocate buffer table entries for event queue */
1113 int falcon_probe_eventq(struct efx_channel *channel)
1114 {
1115 struct efx_nic *efx = channel->efx;
1116 unsigned int evq_size;
1117
1118 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1119 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1120 }
1121
1122 void falcon_init_eventq(struct efx_channel *channel)
1123 {
1124 efx_oword_t evq_ptr;
1125 struct efx_nic *efx = channel->efx;
1126
1127 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1128 channel->channel, channel->eventq.index,
1129 channel->eventq.index + channel->eventq.entries - 1);
1130
1131 /* Pin event queue buffer */
1132 falcon_init_special_buffer(efx, &channel->eventq);
1133
1134 /* Fill event queue with all ones (i.e. empty events) */
1135 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1136
1137 /* Push event queue to card */
1138 EFX_POPULATE_OWORD_3(evq_ptr,
1139 FRF_AZ_EVQ_EN, 1,
1140 FRF_AZ_EVQ_SIZE, FALCON_EVQ_ORDER,
1141 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1142 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1143 channel->channel);
1144
1145 falcon_set_int_moderation(channel);
1146 }
1147
1148 void falcon_fini_eventq(struct efx_channel *channel)
1149 {
1150 efx_oword_t eventq_ptr;
1151 struct efx_nic *efx = channel->efx;
1152
1153 /* Remove event queue from card */
1154 EFX_ZERO_OWORD(eventq_ptr);
1155 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1156 channel->channel);
1157
1158 /* Unpin event queue */
1159 falcon_fini_special_buffer(efx, &channel->eventq);
1160 }
1161
1162 /* Free buffers backing event queue */
1163 void falcon_remove_eventq(struct efx_channel *channel)
1164 {
1165 falcon_free_special_buffer(channel->efx, &channel->eventq);
1166 }
1167
1168
1169 /* Generates a test event on the event queue. A subsequent call to
1170 * process_eventq() should pick up the event and place the value of
1171 * "magic" into channel->eventq_magic;
1172 */
1173 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1174 {
1175 efx_qword_t test_event;
1176
1177 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1178 FSE_AZ_EV_CODE_DRV_GEN_EV,
1179 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1180 falcon_generate_event(channel, &test_event);
1181 }
1182
1183 void falcon_sim_phy_event(struct efx_nic *efx)
1184 {
1185 efx_qword_t phy_event;
1186
1187 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1188 FSE_AZ_EV_CODE_GLOBAL_EV);
1189 if (EFX_IS10G(efx))
1190 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1191 else
1192 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1193
1194 falcon_generate_event(&efx->channel[0], &phy_event);
1195 }
1196
1197 /**************************************************************************
1198 *
1199 * Flush handling
1200 *
1201 **************************************************************************/
1202
1203
1204 static void falcon_poll_flush_events(struct efx_nic *efx)
1205 {
1206 struct efx_channel *channel = &efx->channel[0];
1207 struct efx_tx_queue *tx_queue;
1208 struct efx_rx_queue *rx_queue;
1209 unsigned int read_ptr = channel->eventq_read_ptr;
1210 unsigned int end_ptr = (read_ptr - 1) & FALCON_EVQ_MASK;
1211
1212 do {
1213 efx_qword_t *event = falcon_event(channel, read_ptr);
1214 int ev_code, ev_sub_code, ev_queue;
1215 bool ev_failed;
1216
1217 if (!falcon_event_present(event))
1218 break;
1219
1220 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1221 ev_sub_code = EFX_QWORD_FIELD(*event,
1222 FSF_AZ_DRIVER_EV_SUBCODE);
1223 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1224 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1225 ev_queue = EFX_QWORD_FIELD(*event,
1226 FSF_AZ_DRIVER_EV_SUBDATA);
1227 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1228 tx_queue = efx->tx_queue + ev_queue;
1229 tx_queue->flushed = true;
1230 }
1231 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1232 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1233 ev_queue = EFX_QWORD_FIELD(
1234 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1235 ev_failed = EFX_QWORD_FIELD(
1236 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1237 if (ev_queue < efx->n_rx_queues) {
1238 rx_queue = efx->rx_queue + ev_queue;
1239
1240 /* retry the rx flush */
1241 if (ev_failed)
1242 falcon_flush_rx_queue(rx_queue);
1243 else
1244 rx_queue->flushed = true;
1245 }
1246 }
1247
1248 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1249 } while (read_ptr != end_ptr);
1250 }
1251
1252 /* Handle tx and rx flushes at the same time, since they run in
1253 * parallel in the hardware and there's no reason for us to
1254 * serialise them */
1255 int falcon_flush_queues(struct efx_nic *efx)
1256 {
1257 struct efx_rx_queue *rx_queue;
1258 struct efx_tx_queue *tx_queue;
1259 int i;
1260 bool outstanding;
1261
1262 /* Issue flush requests */
1263 efx_for_each_tx_queue(tx_queue, efx) {
1264 tx_queue->flushed = false;
1265 falcon_flush_tx_queue(tx_queue);
1266 }
1267 efx_for_each_rx_queue(rx_queue, efx) {
1268 rx_queue->flushed = false;
1269 falcon_flush_rx_queue(rx_queue);
1270 }
1271
1272 /* Poll the evq looking for flush completions. Since we're not pushing
1273 * any more rx or tx descriptors at this point, we're in no danger of
1274 * overflowing the evq whilst we wait */
1275 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1276 msleep(FALCON_FLUSH_INTERVAL);
1277 falcon_poll_flush_events(efx);
1278
1279 /* Check if every queue has been succesfully flushed */
1280 outstanding = false;
1281 efx_for_each_tx_queue(tx_queue, efx)
1282 outstanding |= !tx_queue->flushed;
1283 efx_for_each_rx_queue(rx_queue, efx)
1284 outstanding |= !rx_queue->flushed;
1285 if (!outstanding)
1286 return 0;
1287 }
1288
1289 /* Mark the queues as all flushed. We're going to return failure
1290 * leading to a reset, or fake up success anyway. "flushed" now
1291 * indicates that we tried to flush. */
1292 efx_for_each_tx_queue(tx_queue, efx) {
1293 if (!tx_queue->flushed)
1294 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1295 tx_queue->queue);
1296 tx_queue->flushed = true;
1297 }
1298 efx_for_each_rx_queue(rx_queue, efx) {
1299 if (!rx_queue->flushed)
1300 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1301 rx_queue->queue);
1302 rx_queue->flushed = true;
1303 }
1304
1305 if (EFX_WORKAROUND_7803(efx))
1306 return 0;
1307
1308 return -ETIMEDOUT;
1309 }
1310
1311 /**************************************************************************
1312 *
1313 * Falcon hardware interrupts
1314 * The hardware interrupt handler does very little work; all the event
1315 * queue processing is carried out by per-channel tasklets.
1316 *
1317 **************************************************************************/
1318
1319 /* Enable/disable/generate Falcon interrupts */
1320 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1321 int force)
1322 {
1323 efx_oword_t int_en_reg_ker;
1324
1325 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1326 FRF_AZ_KER_INT_KER, force,
1327 FRF_AZ_DRV_INT_EN_KER, enabled);
1328 falcon_write(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1329 }
1330
1331 void falcon_enable_interrupts(struct efx_nic *efx)
1332 {
1333 efx_oword_t int_adr_reg_ker;
1334 struct efx_channel *channel;
1335
1336 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1337 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1338
1339 /* Program address */
1340 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1341 FRF_AZ_NORM_INT_VEC_DIS_KER,
1342 EFX_INT_MODE_USE_MSI(efx),
1343 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1344 falcon_write(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1345
1346 /* Enable interrupts */
1347 falcon_interrupts(efx, 1, 0);
1348
1349 /* Force processing of all the channels to get the EVQ RPTRs up to
1350 date */
1351 efx_for_each_channel(channel, efx)
1352 efx_schedule_channel(channel);
1353 }
1354
1355 void falcon_disable_interrupts(struct efx_nic *efx)
1356 {
1357 /* Disable interrupts */
1358 falcon_interrupts(efx, 0, 0);
1359 }
1360
1361 /* Generate a Falcon test interrupt
1362 * Interrupt must already have been enabled, otherwise nasty things
1363 * may happen.
1364 */
1365 void falcon_generate_interrupt(struct efx_nic *efx)
1366 {
1367 falcon_interrupts(efx, 1, 1);
1368 }
1369
1370 /* Acknowledge a legacy interrupt from Falcon
1371 *
1372 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1373 *
1374 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1375 * BIU. Interrupt acknowledge is read sensitive so must write instead
1376 * (then read to ensure the BIU collector is flushed)
1377 *
1378 * NB most hardware supports MSI interrupts
1379 */
1380 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1381 {
1382 efx_dword_t reg;
1383
1384 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1385 falcon_writel(efx, &reg, FR_AA_INT_ACK_KER);
1386 falcon_readl(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1387 }
1388
1389 /* Process a fatal interrupt
1390 * Disable bus mastering ASAP and schedule a reset
1391 */
1392 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1393 {
1394 struct falcon_nic_data *nic_data = efx->nic_data;
1395 efx_oword_t *int_ker = efx->irq_status.addr;
1396 efx_oword_t fatal_intr;
1397 int error, mem_perr;
1398
1399 falcon_read(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1400 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1401
1402 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1403 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1404 EFX_OWORD_VAL(fatal_intr),
1405 error ? "disabling bus mastering" : "no recognised error");
1406 if (error == 0)
1407 goto out;
1408
1409 /* If this is a memory parity error dump which blocks are offending */
1410 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1411 if (mem_perr) {
1412 efx_oword_t reg;
1413 falcon_read(efx, &reg, FR_AZ_MEM_STAT);
1414 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1415 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1416 }
1417
1418 /* Disable both devices */
1419 pci_clear_master(efx->pci_dev);
1420 if (FALCON_IS_DUAL_FUNC(efx))
1421 pci_clear_master(nic_data->pci_dev2);
1422 falcon_disable_interrupts(efx);
1423
1424 /* Count errors and reset or disable the NIC accordingly */
1425 if (nic_data->int_error_count == 0 ||
1426 time_after(jiffies, nic_data->int_error_expire)) {
1427 nic_data->int_error_count = 0;
1428 nic_data->int_error_expire =
1429 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1430 }
1431 if (++nic_data->int_error_count < FALCON_MAX_INT_ERRORS) {
1432 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1433 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1434 } else {
1435 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1436 "NIC will be disabled\n");
1437 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1438 }
1439 out:
1440 return IRQ_HANDLED;
1441 }
1442
1443 /* Handle a legacy interrupt from Falcon
1444 * Acknowledges the interrupt and schedule event queue processing.
1445 */
1446 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1447 {
1448 struct efx_nic *efx = dev_id;
1449 efx_oword_t *int_ker = efx->irq_status.addr;
1450 irqreturn_t result = IRQ_NONE;
1451 struct efx_channel *channel;
1452 efx_dword_t reg;
1453 u32 queues;
1454 int syserr;
1455
1456 /* Read the ISR which also ACKs the interrupts */
1457 falcon_readl(efx, &reg, FR_BZ_INT_ISR0);
1458 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1459
1460 /* Check to see if we have a serious error condition */
1461 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1462 if (unlikely(syserr))
1463 return falcon_fatal_interrupt(efx);
1464
1465 /* Schedule processing of any interrupting queues */
1466 efx_for_each_channel(channel, efx) {
1467 if ((queues & 1) ||
1468 falcon_event_present(
1469 falcon_event(channel, channel->eventq_read_ptr))) {
1470 efx_schedule_channel(channel);
1471 result = IRQ_HANDLED;
1472 }
1473 queues >>= 1;
1474 }
1475
1476 if (result == IRQ_HANDLED) {
1477 efx->last_irq_cpu = raw_smp_processor_id();
1478 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1479 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1480 }
1481
1482 return result;
1483 }
1484
1485
1486 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1487 {
1488 struct efx_nic *efx = dev_id;
1489 efx_oword_t *int_ker = efx->irq_status.addr;
1490 struct efx_channel *channel;
1491 int syserr;
1492 int queues;
1493
1494 /* Check to see if this is our interrupt. If it isn't, we
1495 * exit without having touched the hardware.
1496 */
1497 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1498 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1499 raw_smp_processor_id());
1500 return IRQ_NONE;
1501 }
1502 efx->last_irq_cpu = raw_smp_processor_id();
1503 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1504 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1505
1506 /* Check to see if we have a serious error condition */
1507 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1508 if (unlikely(syserr))
1509 return falcon_fatal_interrupt(efx);
1510
1511 /* Determine interrupting queues, clear interrupt status
1512 * register and acknowledge the device interrupt.
1513 */
1514 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1515 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1516 EFX_ZERO_OWORD(*int_ker);
1517 wmb(); /* Ensure the vector is cleared before interrupt ack */
1518 falcon_irq_ack_a1(efx);
1519
1520 /* Schedule processing of any interrupting queues */
1521 channel = &efx->channel[0];
1522 while (queues) {
1523 if (queues & 0x01)
1524 efx_schedule_channel(channel);
1525 channel++;
1526 queues >>= 1;
1527 }
1528
1529 return IRQ_HANDLED;
1530 }
1531
1532 /* Handle an MSI interrupt from Falcon
1533 *
1534 * Handle an MSI hardware interrupt. This routine schedules event
1535 * queue processing. No interrupt acknowledgement cycle is necessary.
1536 * Also, we never need to check that the interrupt is for us, since
1537 * MSI interrupts cannot be shared.
1538 */
1539 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1540 {
1541 struct efx_channel *channel = dev_id;
1542 struct efx_nic *efx = channel->efx;
1543 efx_oword_t *int_ker = efx->irq_status.addr;
1544 int syserr;
1545
1546 efx->last_irq_cpu = raw_smp_processor_id();
1547 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1548 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1549
1550 /* Check to see if we have a serious error condition */
1551 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1552 if (unlikely(syserr))
1553 return falcon_fatal_interrupt(efx);
1554
1555 /* Schedule processing of the channel */
1556 efx_schedule_channel(channel);
1557
1558 return IRQ_HANDLED;
1559 }
1560
1561
1562 /* Setup RSS indirection table.
1563 * This maps from the hash value of the packet to RXQ
1564 */
1565 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1566 {
1567 int i = 0;
1568 unsigned long offset;
1569 efx_dword_t dword;
1570
1571 if (falcon_rev(efx) < FALCON_REV_B0)
1572 return;
1573
1574 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1575 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1576 offset += 0x10) {
1577 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1578 i % efx->n_rx_queues);
1579 falcon_writel(efx, &dword, offset);
1580 i++;
1581 }
1582 }
1583
1584 /* Hook interrupt handler(s)
1585 * Try MSI and then legacy interrupts.
1586 */
1587 int falcon_init_interrupt(struct efx_nic *efx)
1588 {
1589 struct efx_channel *channel;
1590 int rc;
1591
1592 if (!EFX_INT_MODE_USE_MSI(efx)) {
1593 irq_handler_t handler;
1594 if (falcon_rev(efx) >= FALCON_REV_B0)
1595 handler = falcon_legacy_interrupt_b0;
1596 else
1597 handler = falcon_legacy_interrupt_a1;
1598
1599 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1600 efx->name, efx);
1601 if (rc) {
1602 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1603 efx->pci_dev->irq);
1604 goto fail1;
1605 }
1606 return 0;
1607 }
1608
1609 /* Hook MSI or MSI-X interrupt */
1610 efx_for_each_channel(channel, efx) {
1611 rc = request_irq(channel->irq, falcon_msi_interrupt,
1612 IRQF_PROBE_SHARED, /* Not shared */
1613 channel->name, channel);
1614 if (rc) {
1615 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1616 goto fail2;
1617 }
1618 }
1619
1620 return 0;
1621
1622 fail2:
1623 efx_for_each_channel(channel, efx)
1624 free_irq(channel->irq, channel);
1625 fail1:
1626 return rc;
1627 }
1628
1629 void falcon_fini_interrupt(struct efx_nic *efx)
1630 {
1631 struct efx_channel *channel;
1632 efx_oword_t reg;
1633
1634 /* Disable MSI/MSI-X interrupts */
1635 efx_for_each_channel(channel, efx) {
1636 if (channel->irq)
1637 free_irq(channel->irq, channel);
1638 }
1639
1640 /* ACK legacy interrupt */
1641 if (falcon_rev(efx) >= FALCON_REV_B0)
1642 falcon_read(efx, &reg, FR_BZ_INT_ISR0);
1643 else
1644 falcon_irq_ack_a1(efx);
1645
1646 /* Disable legacy interrupt */
1647 if (efx->legacy_irq)
1648 free_irq(efx->legacy_irq, efx);
1649 }
1650
1651 /**************************************************************************
1652 *
1653 * EEPROM/flash
1654 *
1655 **************************************************************************
1656 */
1657
1658 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1659
1660 static int falcon_spi_poll(struct efx_nic *efx)
1661 {
1662 efx_oword_t reg;
1663 falcon_read(efx, &reg, FR_AB_EE_SPI_HCMD);
1664 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1665 }
1666
1667 /* Wait for SPI command completion */
1668 static int falcon_spi_wait(struct efx_nic *efx)
1669 {
1670 /* Most commands will finish quickly, so we start polling at
1671 * very short intervals. Sometimes the command may have to
1672 * wait for VPD or expansion ROM access outside of our
1673 * control, so we allow up to 100 ms. */
1674 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1675 int i;
1676
1677 for (i = 0; i < 10; i++) {
1678 if (!falcon_spi_poll(efx))
1679 return 0;
1680 udelay(10);
1681 }
1682
1683 for (;;) {
1684 if (!falcon_spi_poll(efx))
1685 return 0;
1686 if (time_after_eq(jiffies, timeout)) {
1687 EFX_ERR(efx, "timed out waiting for SPI\n");
1688 return -ETIMEDOUT;
1689 }
1690 schedule_timeout_uninterruptible(1);
1691 }
1692 }
1693
1694 int falcon_spi_cmd(const struct efx_spi_device *spi,
1695 unsigned int command, int address,
1696 const void *in, void *out, size_t len)
1697 {
1698 struct efx_nic *efx = spi->efx;
1699 bool addressed = (address >= 0);
1700 bool reading = (out != NULL);
1701 efx_oword_t reg;
1702 int rc;
1703
1704 /* Input validation */
1705 if (len > FALCON_SPI_MAX_LEN)
1706 return -EINVAL;
1707 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1708
1709 /* Check that previous command is not still running */
1710 rc = falcon_spi_poll(efx);
1711 if (rc)
1712 return rc;
1713
1714 /* Program address register, if we have an address */
1715 if (addressed) {
1716 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1717 falcon_write(efx, &reg, FR_AB_EE_SPI_HADR);
1718 }
1719
1720 /* Program data register, if we have data */
1721 if (in != NULL) {
1722 memcpy(&reg, in, len);
1723 falcon_write(efx, &reg, FR_AB_EE_SPI_HDATA);
1724 }
1725
1726 /* Issue read/write command */
1727 EFX_POPULATE_OWORD_7(reg,
1728 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1729 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1730 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1731 FRF_AB_EE_SPI_HCMD_READ, reading,
1732 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1733 FRF_AB_EE_SPI_HCMD_ADBCNT,
1734 (addressed ? spi->addr_len : 0),
1735 FRF_AB_EE_SPI_HCMD_ENC, command);
1736 falcon_write(efx, &reg, FR_AB_EE_SPI_HCMD);
1737
1738 /* Wait for read/write to complete */
1739 rc = falcon_spi_wait(efx);
1740 if (rc)
1741 return rc;
1742
1743 /* Read data */
1744 if (out != NULL) {
1745 falcon_read(efx, &reg, FR_AB_EE_SPI_HDATA);
1746 memcpy(out, &reg, len);
1747 }
1748
1749 return 0;
1750 }
1751
1752 static size_t
1753 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1754 {
1755 return min(FALCON_SPI_MAX_LEN,
1756 (spi->block_size - (start & (spi->block_size - 1))));
1757 }
1758
1759 static inline u8
1760 efx_spi_munge_command(const struct efx_spi_device *spi,
1761 const u8 command, const unsigned int address)
1762 {
1763 return command | (((address >> 8) & spi->munge_address) << 3);
1764 }
1765
1766 /* Wait up to 10 ms for buffered write completion */
1767 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1768 {
1769 struct efx_nic *efx = spi->efx;
1770 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1771 u8 status;
1772 int rc;
1773
1774 for (;;) {
1775 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1776 &status, sizeof(status));
1777 if (rc)
1778 return rc;
1779 if (!(status & SPI_STATUS_NRDY))
1780 return 0;
1781 if (time_after_eq(jiffies, timeout)) {
1782 EFX_ERR(efx, "SPI write timeout on device %d"
1783 " last status=0x%02x\n",
1784 spi->device_id, status);
1785 return -ETIMEDOUT;
1786 }
1787 schedule_timeout_uninterruptible(1);
1788 }
1789 }
1790
1791 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1792 size_t len, size_t *retlen, u8 *buffer)
1793 {
1794 size_t block_len, pos = 0;
1795 unsigned int command;
1796 int rc = 0;
1797
1798 while (pos < len) {
1799 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1800
1801 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1802 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1803 buffer + pos, block_len);
1804 if (rc)
1805 break;
1806 pos += block_len;
1807
1808 /* Avoid locking up the system */
1809 cond_resched();
1810 if (signal_pending(current)) {
1811 rc = -EINTR;
1812 break;
1813 }
1814 }
1815
1816 if (retlen)
1817 *retlen = pos;
1818 return rc;
1819 }
1820
1821 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1822 size_t len, size_t *retlen, const u8 *buffer)
1823 {
1824 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1825 size_t block_len, pos = 0;
1826 unsigned int command;
1827 int rc = 0;
1828
1829 while (pos < len) {
1830 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1831 if (rc)
1832 break;
1833
1834 block_len = min(len - pos,
1835 falcon_spi_write_limit(spi, start + pos));
1836 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1837 rc = falcon_spi_cmd(spi, command, start + pos,
1838 buffer + pos, NULL, block_len);
1839 if (rc)
1840 break;
1841
1842 rc = falcon_spi_wait_write(spi);
1843 if (rc)
1844 break;
1845
1846 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1847 rc = falcon_spi_cmd(spi, command, start + pos,
1848 NULL, verify_buffer, block_len);
1849 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1850 rc = -EIO;
1851 break;
1852 }
1853
1854 pos += block_len;
1855
1856 /* Avoid locking up the system */
1857 cond_resched();
1858 if (signal_pending(current)) {
1859 rc = -EINTR;
1860 break;
1861 }
1862 }
1863
1864 if (retlen)
1865 *retlen = pos;
1866 return rc;
1867 }
1868
1869 /**************************************************************************
1870 *
1871 * MAC wrapper
1872 *
1873 **************************************************************************
1874 */
1875
1876 static int falcon_reset_macs(struct efx_nic *efx)
1877 {
1878 efx_oword_t reg;
1879 int count;
1880
1881 if (falcon_rev(efx) < FALCON_REV_B0) {
1882 /* It's not safe to use GLB_CTL_REG to reset the
1883 * macs, so instead use the internal MAC resets
1884 */
1885 if (!EFX_IS10G(efx)) {
1886 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1887 falcon_write(efx, &reg, FR_AB_GM_CFG1);
1888 udelay(1000);
1889
1890 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1891 falcon_write(efx, &reg, FR_AB_GM_CFG1);
1892 udelay(1000);
1893 return 0;
1894 } else {
1895 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1896 falcon_write(efx, &reg, FR_AB_XM_GLB_CFG);
1897
1898 for (count = 0; count < 10000; count++) {
1899 falcon_read(efx, &reg, FR_AB_XM_GLB_CFG);
1900 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1901 0)
1902 return 0;
1903 udelay(10);
1904 }
1905
1906 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1907 return -ETIMEDOUT;
1908 }
1909 }
1910
1911 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1912 * the drain sequence with the statistics fetch */
1913 efx_stats_disable(efx);
1914
1915 falcon_read(efx, &reg, FR_AB_MAC_CTRL);
1916 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1917 falcon_write(efx, &reg, FR_AB_MAC_CTRL);
1918
1919 falcon_read(efx, &reg, FR_AB_GLB_CTL);
1920 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1921 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1922 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1923 falcon_write(efx, &reg, FR_AB_GLB_CTL);
1924
1925 count = 0;
1926 while (1) {
1927 falcon_read(efx, &reg, FR_AB_GLB_CTL);
1928 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1929 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1930 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1931 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1932 count);
1933 break;
1934 }
1935 if (count > 20) {
1936 EFX_ERR(efx, "MAC reset failed\n");
1937 break;
1938 }
1939 count++;
1940 udelay(10);
1941 }
1942
1943 efx_stats_enable(efx);
1944
1945 /* If we've reset the EM block and the link is up, then
1946 * we'll have to kick the XAUI link so the PHY can recover */
1947 if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1948 falcon_reset_xaui(efx);
1949
1950 return 0;
1951 }
1952
1953 void falcon_drain_tx_fifo(struct efx_nic *efx)
1954 {
1955 efx_oword_t reg;
1956
1957 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1958 (efx->loopback_mode != LOOPBACK_NONE))
1959 return;
1960
1961 falcon_read(efx, &reg, FR_AB_MAC_CTRL);
1962 /* There is no point in draining more than once */
1963 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1964 return;
1965
1966 falcon_reset_macs(efx);
1967 }
1968
1969 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1970 {
1971 efx_oword_t reg;
1972
1973 if (falcon_rev(efx) < FALCON_REV_B0)
1974 return;
1975
1976 /* Isolate the MAC -> RX */
1977 falcon_read(efx, &reg, FR_AZ_RX_CFG);
1978 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1979 falcon_write(efx, &reg, FR_AZ_RX_CFG);
1980
1981 if (!efx->link_up)
1982 falcon_drain_tx_fifo(efx);
1983 }
1984
1985 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1986 {
1987 efx_oword_t reg;
1988 int link_speed;
1989 bool tx_fc;
1990
1991 switch (efx->link_speed) {
1992 case 10000: link_speed = 3; break;
1993 case 1000: link_speed = 2; break;
1994 case 100: link_speed = 1; break;
1995 default: link_speed = 0; break;
1996 }
1997 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1998 * as advertised. Disable to ensure packets are not
1999 * indefinitely held and TX queue can be flushed at any point
2000 * while the link is down. */
2001 EFX_POPULATE_OWORD_5(reg,
2002 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
2003 FRF_AB_MAC_BCAD_ACPT, 1,
2004 FRF_AB_MAC_UC_PROM, efx->promiscuous,
2005 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
2006 FRF_AB_MAC_SPEED, link_speed);
2007 /* On B0, MAC backpressure can be disabled and packets get
2008 * discarded. */
2009 if (falcon_rev(efx) >= FALCON_REV_B0) {
2010 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
2011 !efx->link_up);
2012 }
2013
2014 falcon_write(efx, &reg, FR_AB_MAC_CTRL);
2015
2016 /* Restore the multicast hash registers. */
2017 falcon_set_multicast_hash(efx);
2018
2019 /* Transmission of pause frames when RX crosses the threshold is
2020 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2021 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2022 tx_fc = !!(efx->link_fc & EFX_FC_TX);
2023 falcon_read(efx, &reg, FR_AZ_RX_CFG);
2024 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
2025
2026 /* Unisolate the MAC -> RX */
2027 if (falcon_rev(efx) >= FALCON_REV_B0)
2028 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2029 falcon_write(efx, &reg, FR_AZ_RX_CFG);
2030 }
2031
2032 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2033 {
2034 efx_oword_t reg;
2035 u32 *dma_done;
2036 int i;
2037
2038 if (disable_dma_stats)
2039 return 0;
2040
2041 /* Statistics fetch will fail if the MAC is in TX drain */
2042 if (falcon_rev(efx) >= FALCON_REV_B0) {
2043 efx_oword_t temp;
2044 falcon_read(efx, &temp, FR_AB_MAC_CTRL);
2045 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2046 return 0;
2047 }
2048
2049 dma_done = (efx->stats_buffer.addr + done_offset);
2050 *dma_done = FALCON_STATS_NOT_DONE;
2051 wmb(); /* ensure done flag is clear */
2052
2053 /* Initiate DMA transfer of stats */
2054 EFX_POPULATE_OWORD_2(reg,
2055 FRF_AB_MAC_STAT_DMA_CMD, 1,
2056 FRF_AB_MAC_STAT_DMA_ADR,
2057 efx->stats_buffer.dma_addr);
2058 falcon_write(efx, &reg, FR_AB_MAC_STAT_DMA);
2059
2060 /* Wait for transfer to complete */
2061 for (i = 0; i < 400; i++) {
2062 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2063 rmb(); /* Ensure the stats are valid. */
2064 return 0;
2065 }
2066 udelay(10);
2067 }
2068
2069 EFX_ERR(efx, "timed out waiting for statistics\n");
2070 return -ETIMEDOUT;
2071 }
2072
2073 /**************************************************************************
2074 *
2075 * PHY access via GMII
2076 *
2077 **************************************************************************
2078 */
2079
2080 /* Wait for GMII access to complete */
2081 static int falcon_gmii_wait(struct efx_nic *efx)
2082 {
2083 efx_dword_t md_stat;
2084 int count;
2085
2086 /* wait upto 50ms - taken max from datasheet */
2087 for (count = 0; count < 5000; count++) {
2088 falcon_readl(efx, &md_stat, FR_AB_MD_STAT);
2089 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2090 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2091 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2092 EFX_ERR(efx, "error from GMII access "
2093 EFX_DWORD_FMT"\n",
2094 EFX_DWORD_VAL(md_stat));
2095 return -EIO;
2096 }
2097 return 0;
2098 }
2099 udelay(10);
2100 }
2101 EFX_ERR(efx, "timed out waiting for GMII\n");
2102 return -ETIMEDOUT;
2103 }
2104
2105 /* Write an MDIO register of a PHY connected to Falcon. */
2106 static int falcon_mdio_write(struct net_device *net_dev,
2107 int prtad, int devad, u16 addr, u16 value)
2108 {
2109 struct efx_nic *efx = netdev_priv(net_dev);
2110 efx_oword_t reg;
2111 int rc;
2112
2113 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2114 prtad, devad, addr, value);
2115
2116 spin_lock_bh(&efx->phy_lock);
2117
2118 /* Check MDIO not currently being accessed */
2119 rc = falcon_gmii_wait(efx);
2120 if (rc)
2121 goto out;
2122
2123 /* Write the address/ID register */
2124 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2125 falcon_write(efx, &reg, FR_AB_MD_PHY_ADR);
2126
2127 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2128 FRF_AB_MD_DEV_ADR, devad);
2129 falcon_write(efx, &reg, FR_AB_MD_ID);
2130
2131 /* Write data */
2132 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2133 falcon_write(efx, &reg, FR_AB_MD_TXD);
2134
2135 EFX_POPULATE_OWORD_2(reg,
2136 FRF_AB_MD_WRC, 1,
2137 FRF_AB_MD_GC, 0);
2138 falcon_write(efx, &reg, FR_AB_MD_CS);
2139
2140 /* Wait for data to be written */
2141 rc = falcon_gmii_wait(efx);
2142 if (rc) {
2143 /* Abort the write operation */
2144 EFX_POPULATE_OWORD_2(reg,
2145 FRF_AB_MD_WRC, 0,
2146 FRF_AB_MD_GC, 1);
2147 falcon_write(efx, &reg, FR_AB_MD_CS);
2148 udelay(10);
2149 }
2150
2151 out:
2152 spin_unlock_bh(&efx->phy_lock);
2153 return rc;
2154 }
2155
2156 /* Read an MDIO register of a PHY connected to Falcon. */
2157 static int falcon_mdio_read(struct net_device *net_dev,
2158 int prtad, int devad, u16 addr)
2159 {
2160 struct efx_nic *efx = netdev_priv(net_dev);
2161 efx_oword_t reg;
2162 int rc;
2163
2164 spin_lock_bh(&efx->phy_lock);
2165
2166 /* Check MDIO not currently being accessed */
2167 rc = falcon_gmii_wait(efx);
2168 if (rc)
2169 goto out;
2170
2171 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2172 falcon_write(efx, &reg, FR_AB_MD_PHY_ADR);
2173
2174 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2175 FRF_AB_MD_DEV_ADR, devad);
2176 falcon_write(efx, &reg, FR_AB_MD_ID);
2177
2178 /* Request data to be read */
2179 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2180 falcon_write(efx, &reg, FR_AB_MD_CS);
2181
2182 /* Wait for data to become available */
2183 rc = falcon_gmii_wait(efx);
2184 if (rc == 0) {
2185 falcon_read(efx, &reg, FR_AB_MD_RXD);
2186 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2187 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2188 prtad, devad, addr, rc);
2189 } else {
2190 /* Abort the read operation */
2191 EFX_POPULATE_OWORD_2(reg,
2192 FRF_AB_MD_RIC, 0,
2193 FRF_AB_MD_GC, 1);
2194 falcon_write(efx, &reg, FR_AB_MD_CS);
2195
2196 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2197 prtad, devad, addr, rc);
2198 }
2199
2200 out:
2201 spin_unlock_bh(&efx->phy_lock);
2202 return rc;
2203 }
2204
2205 static int falcon_probe_phy(struct efx_nic *efx)
2206 {
2207 switch (efx->phy_type) {
2208 case PHY_TYPE_SFX7101:
2209 efx->phy_op = &falcon_sfx7101_phy_ops;
2210 break;
2211 case PHY_TYPE_SFT9001A:
2212 case PHY_TYPE_SFT9001B:
2213 efx->phy_op = &falcon_sft9001_phy_ops;
2214 break;
2215 case PHY_TYPE_QT2022C2:
2216 case PHY_TYPE_QT2025C:
2217 efx->phy_op = &falcon_xfp_phy_ops;
2218 break;
2219 default:
2220 EFX_ERR(efx, "Unknown PHY type %d\n",
2221 efx->phy_type);
2222 return -1;
2223 }
2224
2225 if (efx->phy_op->macs & EFX_XMAC)
2226 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2227 (1 << LOOPBACK_XGXS) |
2228 (1 << LOOPBACK_XAUI));
2229 if (efx->phy_op->macs & EFX_GMAC)
2230 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2231 efx->loopback_modes |= efx->phy_op->loopbacks;
2232
2233 return 0;
2234 }
2235
2236 int falcon_switch_mac(struct efx_nic *efx)
2237 {
2238 struct efx_mac_operations *old_mac_op = efx->mac_op;
2239 efx_oword_t nic_stat;
2240 unsigned strap_val;
2241 int rc = 0;
2242
2243 /* Don't try to fetch MAC stats while we're switching MACs */
2244 efx_stats_disable(efx);
2245
2246 /* Internal loopbacks override the phy speed setting */
2247 if (efx->loopback_mode == LOOPBACK_GMAC) {
2248 efx->link_speed = 1000;
2249 efx->link_fd = true;
2250 } else if (LOOPBACK_INTERNAL(efx)) {
2251 efx->link_speed = 10000;
2252 efx->link_fd = true;
2253 }
2254
2255 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2256 efx->mac_op = (EFX_IS10G(efx) ?
2257 &falcon_xmac_operations : &falcon_gmac_operations);
2258
2259 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2260 * changed, because this function is run post online reset */
2261 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT);
2262 strap_val = EFX_IS10G(efx) ? 5 : 3;
2263 if (falcon_rev(efx) >= FALCON_REV_B0) {
2264 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2265 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2266 falcon_write(efx, &nic_stat, FR_AB_NIC_STAT);
2267 } else {
2268 /* Falcon A1 does not support 1G/10G speed switching
2269 * and must not be used with a PHY that does. */
2270 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2271 strap_val);
2272 }
2273
2274 if (old_mac_op == efx->mac_op)
2275 goto out;
2276
2277 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2278 /* Not all macs support a mac-level link state */
2279 efx->mac_up = true;
2280
2281 rc = falcon_reset_macs(efx);
2282 out:
2283 efx_stats_enable(efx);
2284 return rc;
2285 }
2286
2287 /* This call is responsible for hooking in the MAC and PHY operations */
2288 int falcon_probe_port(struct efx_nic *efx)
2289 {
2290 int rc;
2291
2292 /* Hook in PHY operations table */
2293 rc = falcon_probe_phy(efx);
2294 if (rc)
2295 return rc;
2296
2297 /* Set up MDIO structure for PHY */
2298 efx->mdio.mmds = efx->phy_op->mmds;
2299 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2300 efx->mdio.mdio_read = falcon_mdio_read;
2301 efx->mdio.mdio_write = falcon_mdio_write;
2302
2303 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2304 if (falcon_rev(efx) >= FALCON_REV_B0)
2305 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2306 else
2307 efx->wanted_fc = EFX_FC_RX;
2308
2309 /* Allocate buffer for stats */
2310 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2311 FALCON_MAC_STATS_SIZE);
2312 if (rc)
2313 return rc;
2314 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2315 (u64)efx->stats_buffer.dma_addr,
2316 efx->stats_buffer.addr,
2317 (u64)virt_to_phys(efx->stats_buffer.addr));
2318
2319 return 0;
2320 }
2321
2322 void falcon_remove_port(struct efx_nic *efx)
2323 {
2324 falcon_free_buffer(efx, &efx->stats_buffer);
2325 }
2326
2327 /**************************************************************************
2328 *
2329 * Multicast filtering
2330 *
2331 **************************************************************************
2332 */
2333
2334 void falcon_set_multicast_hash(struct efx_nic *efx)
2335 {
2336 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2337
2338 /* Broadcast packets go through the multicast hash filter.
2339 * ether_crc_le() of the broadcast address is 0xbe2612ff
2340 * so we always add bit 0xff to the mask.
2341 */
2342 set_bit_le(0xff, mc_hash->byte);
2343
2344 falcon_write(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2345 falcon_write(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2346 }
2347
2348
2349 /**************************************************************************
2350 *
2351 * Falcon test code
2352 *
2353 **************************************************************************/
2354
2355 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2356 {
2357 struct falcon_nvconfig *nvconfig;
2358 struct efx_spi_device *spi;
2359 void *region;
2360 int rc, magic_num, struct_ver;
2361 __le16 *word, *limit;
2362 u32 csum;
2363
2364 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2365 if (!spi)
2366 return -EINVAL;
2367
2368 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2369 if (!region)
2370 return -ENOMEM;
2371 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2372
2373 mutex_lock(&efx->spi_lock);
2374 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2375 mutex_unlock(&efx->spi_lock);
2376 if (rc) {
2377 EFX_ERR(efx, "Failed to read %s\n",
2378 efx->spi_flash ? "flash" : "EEPROM");
2379 rc = -EIO;
2380 goto out;
2381 }
2382
2383 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2384 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2385
2386 rc = -EINVAL;
2387 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2388 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2389 goto out;
2390 }
2391 if (struct_ver < 2) {
2392 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2393 goto out;
2394 } else if (struct_ver < 4) {
2395 word = &nvconfig->board_magic_num;
2396 limit = (__le16 *) (nvconfig + 1);
2397 } else {
2398 word = region;
2399 limit = region + FALCON_NVCONFIG_END;
2400 }
2401 for (csum = 0; word < limit; ++word)
2402 csum += le16_to_cpu(*word);
2403
2404 if (~csum & 0xffff) {
2405 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2406 goto out;
2407 }
2408
2409 rc = 0;
2410 if (nvconfig_out)
2411 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2412
2413 out:
2414 kfree(region);
2415 return rc;
2416 }
2417
2418 /* Registers tested in the falcon register test */
2419 static struct {
2420 unsigned address;
2421 efx_oword_t mask;
2422 } efx_test_registers[] = {
2423 { FR_AZ_ADR_REGION,
2424 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2425 { FR_AZ_RX_CFG,
2426 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2427 { FR_AZ_TX_CFG,
2428 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2429 { FR_AZ_TX_RESERVED,
2430 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2431 { FR_AB_MAC_CTRL,
2432 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2433 { FR_AZ_SRM_TX_DC_CFG,
2434 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2435 { FR_AZ_RX_DC_CFG,
2436 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2437 { FR_AZ_RX_DC_PF_WM,
2438 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2439 { FR_BZ_DP_CTRL,
2440 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2441 { FR_AB_GM_CFG2,
2442 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2443 { FR_AB_GMF_CFG0,
2444 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2445 { FR_AB_XM_GLB_CFG,
2446 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2447 { FR_AB_XM_TX_CFG,
2448 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2449 { FR_AB_XM_RX_CFG,
2450 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2451 { FR_AB_XM_RX_PARAM,
2452 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2453 { FR_AB_XM_FC,
2454 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2455 { FR_AB_XM_ADR_LO,
2456 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2457 { FR_AB_XX_SD_CTL,
2458 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2459 };
2460
2461 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2462 const efx_oword_t *mask)
2463 {
2464 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2465 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2466 }
2467
2468 int falcon_test_registers(struct efx_nic *efx)
2469 {
2470 unsigned address = 0, i, j;
2471 efx_oword_t mask, imask, original, reg, buf;
2472
2473 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2474 WARN_ON(!LOOPBACK_INTERNAL(efx));
2475
2476 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2477 address = efx_test_registers[i].address;
2478 mask = imask = efx_test_registers[i].mask;
2479 EFX_INVERT_OWORD(imask);
2480
2481 falcon_read(efx, &original, address);
2482
2483 /* bit sweep on and off */
2484 for (j = 0; j < 128; j++) {
2485 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2486 continue;
2487
2488 /* Test this testable bit can be set in isolation */
2489 EFX_AND_OWORD(reg, original, mask);
2490 EFX_SET_OWORD32(reg, j, j, 1);
2491
2492 falcon_write(efx, &reg, address);
2493 falcon_read(efx, &buf, address);
2494
2495 if (efx_masked_compare_oword(&reg, &buf, &mask))
2496 goto fail;
2497
2498 /* Test this testable bit can be cleared in isolation */
2499 EFX_OR_OWORD(reg, original, mask);
2500 EFX_SET_OWORD32(reg, j, j, 0);
2501
2502 falcon_write(efx, &reg, address);
2503 falcon_read(efx, &buf, address);
2504
2505 if (efx_masked_compare_oword(&reg, &buf, &mask))
2506 goto fail;
2507 }
2508
2509 falcon_write(efx, &original, address);
2510 }
2511
2512 return 0;
2513
2514 fail:
2515 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2516 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2517 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2518 return -EIO;
2519 }
2520
2521 /**************************************************************************
2522 *
2523 * Device reset
2524 *
2525 **************************************************************************
2526 */
2527
2528 /* Resets NIC to known state. This routine must be called in process
2529 * context and is allowed to sleep. */
2530 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2531 {
2532 struct falcon_nic_data *nic_data = efx->nic_data;
2533 efx_oword_t glb_ctl_reg_ker;
2534 int rc;
2535
2536 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2537
2538 /* Initiate device reset */
2539 if (method == RESET_TYPE_WORLD) {
2540 rc = pci_save_state(efx->pci_dev);
2541 if (rc) {
2542 EFX_ERR(efx, "failed to backup PCI state of primary "
2543 "function prior to hardware reset\n");
2544 goto fail1;
2545 }
2546 if (FALCON_IS_DUAL_FUNC(efx)) {
2547 rc = pci_save_state(nic_data->pci_dev2);
2548 if (rc) {
2549 EFX_ERR(efx, "failed to backup PCI state of "
2550 "secondary function prior to "
2551 "hardware reset\n");
2552 goto fail2;
2553 }
2554 }
2555
2556 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2557 FRF_AB_EXT_PHY_RST_DUR,
2558 FFE_AB_EXT_PHY_RST_DUR_10240US,
2559 FRF_AB_SWRST, 1);
2560 } else {
2561 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2562 /* exclude PHY from "invisible" reset */
2563 FRF_AB_EXT_PHY_RST_CTL,
2564 method == RESET_TYPE_INVISIBLE,
2565 /* exclude EEPROM/flash and PCIe */
2566 FRF_AB_PCIE_CORE_RST_CTL, 1,
2567 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2568 FRF_AB_PCIE_SD_RST_CTL, 1,
2569 FRF_AB_EE_RST_CTL, 1,
2570 FRF_AB_EXT_PHY_RST_DUR,
2571 FFE_AB_EXT_PHY_RST_DUR_10240US,
2572 FRF_AB_SWRST, 1);
2573 }
2574 falcon_write(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2575
2576 EFX_LOG(efx, "waiting for hardware reset\n");
2577 schedule_timeout_uninterruptible(HZ / 20);
2578
2579 /* Restore PCI configuration if needed */
2580 if (method == RESET_TYPE_WORLD) {
2581 if (FALCON_IS_DUAL_FUNC(efx)) {
2582 rc = pci_restore_state(nic_data->pci_dev2);
2583 if (rc) {
2584 EFX_ERR(efx, "failed to restore PCI config for "
2585 "the secondary function\n");
2586 goto fail3;
2587 }
2588 }
2589 rc = pci_restore_state(efx->pci_dev);
2590 if (rc) {
2591 EFX_ERR(efx, "failed to restore PCI config for the "
2592 "primary function\n");
2593 goto fail4;
2594 }
2595 EFX_LOG(efx, "successfully restored PCI config\n");
2596 }
2597
2598 /* Assert that reset complete */
2599 falcon_read(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2600 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2601 rc = -ETIMEDOUT;
2602 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2603 goto fail5;
2604 }
2605 EFX_LOG(efx, "hardware reset complete\n");
2606
2607 return 0;
2608
2609 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2610 fail2:
2611 fail3:
2612 pci_restore_state(efx->pci_dev);
2613 fail1:
2614 fail4:
2615 fail5:
2616 return rc;
2617 }
2618
2619 /* Zeroes out the SRAM contents. This routine must be called in
2620 * process context and is allowed to sleep.
2621 */
2622 static int falcon_reset_sram(struct efx_nic *efx)
2623 {
2624 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2625 int count;
2626
2627 /* Set the SRAM wake/sleep GPIO appropriately. */
2628 falcon_read(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2629 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2630 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2631 falcon_write(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2632
2633 /* Initiate SRAM reset */
2634 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2635 FRF_AZ_SRM_INIT_EN, 1,
2636 FRF_AZ_SRM_NB_SZ, 0);
2637 falcon_write(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2638
2639 /* Wait for SRAM reset to complete */
2640 count = 0;
2641 do {
2642 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2643
2644 /* SRAM reset is slow; expect around 16ms */
2645 schedule_timeout_uninterruptible(HZ / 50);
2646
2647 /* Check for reset complete */
2648 falcon_read(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2649 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2650 EFX_LOG(efx, "SRAM reset complete\n");
2651
2652 return 0;
2653 }
2654 } while (++count < 20); /* wait upto 0.4 sec */
2655
2656 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2657 return -ETIMEDOUT;
2658 }
2659
2660 static int falcon_spi_device_init(struct efx_nic *efx,
2661 struct efx_spi_device **spi_device_ret,
2662 unsigned int device_id, u32 device_type)
2663 {
2664 struct efx_spi_device *spi_device;
2665
2666 if (device_type != 0) {
2667 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2668 if (!spi_device)
2669 return -ENOMEM;
2670 spi_device->device_id = device_id;
2671 spi_device->size =
2672 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2673 spi_device->addr_len =
2674 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2675 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2676 spi_device->addr_len == 1);
2677 spi_device->erase_command =
2678 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2679 spi_device->erase_size =
2680 1 << SPI_DEV_TYPE_FIELD(device_type,
2681 SPI_DEV_TYPE_ERASE_SIZE);
2682 spi_device->block_size =
2683 1 << SPI_DEV_TYPE_FIELD(device_type,
2684 SPI_DEV_TYPE_BLOCK_SIZE);
2685
2686 spi_device->efx = efx;
2687 } else {
2688 spi_device = NULL;
2689 }
2690
2691 kfree(*spi_device_ret);
2692 *spi_device_ret = spi_device;
2693 return 0;
2694 }
2695
2696
2697 static void falcon_remove_spi_devices(struct efx_nic *efx)
2698 {
2699 kfree(efx->spi_eeprom);
2700 efx->spi_eeprom = NULL;
2701 kfree(efx->spi_flash);
2702 efx->spi_flash = NULL;
2703 }
2704
2705 /* Extract non-volatile configuration */
2706 static int falcon_probe_nvconfig(struct efx_nic *efx)
2707 {
2708 struct falcon_nvconfig *nvconfig;
2709 int board_rev;
2710 int rc;
2711
2712 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2713 if (!nvconfig)
2714 return -ENOMEM;
2715
2716 rc = falcon_read_nvram(efx, nvconfig);
2717 if (rc == -EINVAL) {
2718 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2719 efx->phy_type = PHY_TYPE_NONE;
2720 efx->mdio.prtad = MDIO_PRTAD_NONE;
2721 board_rev = 0;
2722 rc = 0;
2723 } else if (rc) {
2724 goto fail1;
2725 } else {
2726 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2727 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2728
2729 efx->phy_type = v2->port0_phy_type;
2730 efx->mdio.prtad = v2->port0_phy_addr;
2731 board_rev = le16_to_cpu(v2->board_revision);
2732
2733 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2734 rc = falcon_spi_device_init(
2735 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2736 le32_to_cpu(v3->spi_device_type
2737 [FFE_AB_SPI_DEVICE_FLASH]));
2738 if (rc)
2739 goto fail2;
2740 rc = falcon_spi_device_init(
2741 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2742 le32_to_cpu(v3->spi_device_type
2743 [FFE_AB_SPI_DEVICE_EEPROM]));
2744 if (rc)
2745 goto fail2;
2746 }
2747 }
2748
2749 /* Read the MAC addresses */
2750 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2751
2752 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2753
2754 falcon_probe_board(efx, board_rev);
2755
2756 kfree(nvconfig);
2757 return 0;
2758
2759 fail2:
2760 falcon_remove_spi_devices(efx);
2761 fail1:
2762 kfree(nvconfig);
2763 return rc;
2764 }
2765
2766 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2767 * count, port speed). Set workaround and feature flags accordingly.
2768 */
2769 static int falcon_probe_nic_variant(struct efx_nic *efx)
2770 {
2771 efx_oword_t altera_build;
2772 efx_oword_t nic_stat;
2773
2774 falcon_read(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2775 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2776 EFX_ERR(efx, "Falcon FPGA not supported\n");
2777 return -ENODEV;
2778 }
2779
2780 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT);
2781
2782 switch (falcon_rev(efx)) {
2783 case FALCON_REV_A0:
2784 case 0xff:
2785 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2786 return -ENODEV;
2787
2788 case FALCON_REV_A1:
2789 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2790 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2791 return -ENODEV;
2792 }
2793 break;
2794
2795 case FALCON_REV_B0:
2796 break;
2797
2798 default:
2799 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2800 return -ENODEV;
2801 }
2802
2803 /* Initial assumed speed */
2804 efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2805
2806 return 0;
2807 }
2808
2809 /* Probe all SPI devices on the NIC */
2810 static void falcon_probe_spi_devices(struct efx_nic *efx)
2811 {
2812 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2813 int boot_dev;
2814
2815 falcon_read(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2816 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT);
2817 falcon_read(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2818
2819 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2820 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2821 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2822 EFX_LOG(efx, "Booted from %s\n",
2823 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2824 } else {
2825 /* Disable VPD and set clock dividers to safe
2826 * values for initial programming. */
2827 boot_dev = -1;
2828 EFX_LOG(efx, "Booted from internal ASIC settings;"
2829 " setting SPI config\n");
2830 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2831 /* 125 MHz / 7 ~= 20 MHz */
2832 FRF_AB_EE_SF_CLOCK_DIV, 7,
2833 /* 125 MHz / 63 ~= 2 MHz */
2834 FRF_AB_EE_EE_CLOCK_DIV, 63);
2835 falcon_write(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2836 }
2837
2838 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2839 falcon_spi_device_init(efx, &efx->spi_flash,
2840 FFE_AB_SPI_DEVICE_FLASH,
2841 default_flash_type);
2842 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2843 falcon_spi_device_init(efx, &efx->spi_eeprom,
2844 FFE_AB_SPI_DEVICE_EEPROM,
2845 large_eeprom_type);
2846 }
2847
2848 int falcon_probe_nic(struct efx_nic *efx)
2849 {
2850 struct falcon_nic_data *nic_data;
2851 int rc;
2852
2853 /* Allocate storage for hardware specific data */
2854 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2855 if (!nic_data)
2856 return -ENOMEM;
2857 efx->nic_data = nic_data;
2858
2859 /* Determine number of ports etc. */
2860 rc = falcon_probe_nic_variant(efx);
2861 if (rc)
2862 goto fail1;
2863
2864 /* Probe secondary function if expected */
2865 if (FALCON_IS_DUAL_FUNC(efx)) {
2866 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2867
2868 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2869 dev))) {
2870 if (dev->bus == efx->pci_dev->bus &&
2871 dev->devfn == efx->pci_dev->devfn + 1) {
2872 nic_data->pci_dev2 = dev;
2873 break;
2874 }
2875 }
2876 if (!nic_data->pci_dev2) {
2877 EFX_ERR(efx, "failed to find secondary function\n");
2878 rc = -ENODEV;
2879 goto fail2;
2880 }
2881 }
2882
2883 /* Now we can reset the NIC */
2884 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2885 if (rc) {
2886 EFX_ERR(efx, "failed to reset NIC\n");
2887 goto fail3;
2888 }
2889
2890 /* Allocate memory for INT_KER */
2891 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2892 if (rc)
2893 goto fail4;
2894 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2895
2896 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2897 (u64)efx->irq_status.dma_addr,
2898 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2899
2900 falcon_probe_spi_devices(efx);
2901
2902 /* Read in the non-volatile configuration */
2903 rc = falcon_probe_nvconfig(efx);
2904 if (rc)
2905 goto fail5;
2906
2907 /* Initialise I2C adapter */
2908 efx->i2c_adap.owner = THIS_MODULE;
2909 nic_data->i2c_data = falcon_i2c_bit_operations;
2910 nic_data->i2c_data.data = efx;
2911 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2912 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2913 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2914 rc = i2c_bit_add_bus(&efx->i2c_adap);
2915 if (rc)
2916 goto fail5;
2917
2918 return 0;
2919
2920 fail5:
2921 falcon_remove_spi_devices(efx);
2922 falcon_free_buffer(efx, &efx->irq_status);
2923 fail4:
2924 fail3:
2925 if (nic_data->pci_dev2) {
2926 pci_dev_put(nic_data->pci_dev2);
2927 nic_data->pci_dev2 = NULL;
2928 }
2929 fail2:
2930 fail1:
2931 kfree(efx->nic_data);
2932 return rc;
2933 }
2934
2935 static void falcon_init_rx_cfg(struct efx_nic *efx)
2936 {
2937 /* Prior to Siena the RX DMA engine will split each frame at
2938 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2939 * be so large that that never happens. */
2940 const unsigned huge_buf_size = (3 * 4096) >> 5;
2941 /* RX control FIFO thresholds (32 entries) */
2942 const unsigned ctrl_xon_thr = 20;
2943 const unsigned ctrl_xoff_thr = 25;
2944 /* RX data FIFO thresholds (256-byte units; size varies) */
2945 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2946 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2947 efx_oword_t reg;
2948
2949 falcon_read(efx, &reg, FR_AZ_RX_CFG);
2950 if (falcon_rev(efx) <= FALCON_REV_A1) {
2951 /* Data FIFO size is 5.5K */
2952 if (data_xon_thr < 0)
2953 data_xon_thr = 512 >> 8;
2954 if (data_xoff_thr < 0)
2955 data_xoff_thr = 2048 >> 8;
2956 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2957 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2958 huge_buf_size);
2959 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2960 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2961 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2962 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2963 } else {
2964 /* Data FIFO size is 80K; register fields moved */
2965 if (data_xon_thr < 0)
2966 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2967 if (data_xoff_thr < 0)
2968 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2969 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2970 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2971 huge_buf_size);
2972 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2973 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2974 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2975 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2976 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2977 }
2978 falcon_write(efx, &reg, FR_AZ_RX_CFG);
2979 }
2980
2981 /* This call performs hardware-specific global initialisation, such as
2982 * defining the descriptor cache sizes and number of RSS channels.
2983 * It does not set up any buffers, descriptor rings or event queues.
2984 */
2985 int falcon_init_nic(struct efx_nic *efx)
2986 {
2987 efx_oword_t temp;
2988 int rc;
2989
2990 /* Use on-chip SRAM */
2991 falcon_read(efx, &temp, FR_AB_NIC_STAT);
2992 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2993 falcon_write(efx, &temp, FR_AB_NIC_STAT);
2994
2995 /* Set the source of the GMAC clock */
2996 if (falcon_rev(efx) == FALCON_REV_B0) {
2997 falcon_read(efx, &temp, FR_AB_GPIO_CTL);
2998 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2999 falcon_write(efx, &temp, FR_AB_GPIO_CTL);
3000 }
3001
3002 rc = falcon_reset_sram(efx);
3003 if (rc)
3004 return rc;
3005
3006 /* Set positions of descriptor caches in SRAM. */
3007 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
3008 falcon_write(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3009 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
3010 falcon_write(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3011
3012 /* Set TX descriptor cache size. */
3013 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
3014 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3015 falcon_write(efx, &temp, FR_AZ_TX_DC_CFG);
3016
3017 /* Set RX descriptor cache size. Set low watermark to size-8, as
3018 * this allows most efficient prefetching.
3019 */
3020 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
3021 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3022 falcon_write(efx, &temp, FR_AZ_RX_DC_CFG);
3023 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3024 falcon_write(efx, &temp, FR_AZ_RX_DC_PF_WM);
3025
3026 /* Clear the parity enables on the TX data fifos as
3027 * they produce false parity errors because of timing issues
3028 */
3029 if (EFX_WORKAROUND_5129(efx)) {
3030 falcon_read(efx, &temp, FR_AZ_CSR_SPARE);
3031 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3032 falcon_write(efx, &temp, FR_AZ_CSR_SPARE);
3033 }
3034
3035 /* Enable all the genuinely fatal interrupts. (They are still
3036 * masked by the overall interrupt mask, controlled by
3037 * falcon_interrupts()).
3038 *
3039 * Note: All other fatal interrupts are enabled
3040 */
3041 EFX_POPULATE_OWORD_3(temp,
3042 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3043 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3044 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3045 EFX_INVERT_OWORD(temp);
3046 falcon_write(efx, &temp, FR_AZ_FATAL_INTR_KER);
3047
3048 if (EFX_WORKAROUND_7244(efx)) {
3049 falcon_read(efx, &temp, FR_BZ_RX_FILTER_CTL);
3050 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3051 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3052 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3053 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3054 falcon_write(efx, &temp, FR_BZ_RX_FILTER_CTL);
3055 }
3056
3057 falcon_setup_rss_indir_table(efx);
3058
3059 /* XXX This is documented only for Falcon A0/A1 */
3060 /* Setup RX. Wait for descriptor is broken and must
3061 * be disabled. RXDP recovery shouldn't be needed, but is.
3062 */
3063 falcon_read(efx, &temp, FR_AA_RX_SELF_RST);
3064 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3065 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3066 if (EFX_WORKAROUND_5583(efx))
3067 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3068 falcon_write(efx, &temp, FR_AA_RX_SELF_RST);
3069
3070 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3071 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3072 */
3073 falcon_read(efx, &temp, FR_AZ_TX_RESERVED);
3074 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3075 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3076 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3077 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3078 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3079 /* Enable SW_EV to inherit in char driver - assume harmless here */
3080 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3081 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3082 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3083 /* Squash TX of packets of 16 bytes or less */
3084 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3085 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3086 falcon_write(efx, &temp, FR_AZ_TX_RESERVED);
3087
3088 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3089 * descriptors (which is bad).
3090 */
3091 falcon_read(efx, &temp, FR_AZ_TX_CFG);
3092 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3093 falcon_write(efx, &temp, FR_AZ_TX_CFG);
3094
3095 falcon_init_rx_cfg(efx);
3096
3097 /* Set destination of both TX and RX Flush events */
3098 if (falcon_rev(efx) >= FALCON_REV_B0) {
3099 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3100 falcon_write(efx, &temp, FR_BZ_DP_CTRL);
3101 }
3102
3103 return 0;
3104 }
3105
3106 void falcon_remove_nic(struct efx_nic *efx)
3107 {
3108 struct falcon_nic_data *nic_data = efx->nic_data;
3109 int rc;
3110
3111 /* Remove I2C adapter and clear it in preparation for a retry */
3112 rc = i2c_del_adapter(&efx->i2c_adap);
3113 BUG_ON(rc);
3114 memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
3115
3116 falcon_remove_spi_devices(efx);
3117 falcon_free_buffer(efx, &efx->irq_status);
3118
3119 falcon_reset_hw(efx, RESET_TYPE_ALL);
3120
3121 /* Release the second function after the reset */
3122 if (nic_data->pci_dev2) {
3123 pci_dev_put(nic_data->pci_dev2);
3124 nic_data->pci_dev2 = NULL;
3125 }
3126
3127 /* Tear down the private nic state */
3128 kfree(efx->nic_data);
3129 efx->nic_data = NULL;
3130 }
3131
3132 void falcon_update_nic_stats(struct efx_nic *efx)
3133 {
3134 efx_oword_t cnt;
3135
3136 falcon_read(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3137 efx->n_rx_nodesc_drop_cnt +=
3138 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3139 }
3140
3141 /**************************************************************************
3142 *
3143 * Revision-dependent attributes used by efx.c
3144 *
3145 **************************************************************************
3146 */
3147
3148 struct efx_nic_type falcon_a_nic_type = {
3149 .mem_bar = 2,
3150 .mem_map_size = 0x20000,
3151 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3152 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3153 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3154 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3155 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3156 .txd_ring_mask = FALCON_TXD_RING_MASK,
3157 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3158 .evq_size = FALCON_EVQ_SIZE,
3159 .max_dma_mask = FALCON_DMA_MASK,
3160 .tx_dma_mask = FALCON_TX_DMA_MASK,
3161 .bug5391_mask = 0xf,
3162 .rx_buffer_padding = 0x24,
3163 .max_interrupt_mode = EFX_INT_MODE_MSI,
3164 .phys_addr_channels = 4,
3165 };
3166
3167 struct efx_nic_type falcon_b_nic_type = {
3168 .mem_bar = 2,
3169 /* Map everything up to and including the RSS indirection
3170 * table. Don't map MSI-X table, MSI-X PBA since Linux
3171 * requires that they not be mapped. */
3172 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3173 FR_BZ_RX_INDIRECTION_TBL_STEP *
3174 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3175 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3176 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3177 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3178 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3179 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3180 .txd_ring_mask = FALCON_TXD_RING_MASK,
3181 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3182 .evq_size = FALCON_EVQ_SIZE,
3183 .max_dma_mask = FALCON_DMA_MASK,
3184 .tx_dma_mask = FALCON_TX_DMA_MASK,
3185 .bug5391_mask = 0,
3186 .rx_buffer_padding = 0,
3187 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3188 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3189 * interrupt handler only supports 32
3190 * channels */
3191 };
3192
Linux kernel - Deliverables
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