1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include "net_driver.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
30 #include "workarounds.h"
32 /* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
43 struct falcon_nic_data
{
44 unsigned next_buffer_table
;
45 struct pci_dev
*pci_dev2
;
46 struct i2c_algo_bit_data i2c_data
;
49 /**************************************************************************
53 **************************************************************************
56 static int disable_dma_stats
;
58 /* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
65 #define TX_DC_ENTRIES 16
66 #define TX_DC_ENTRIES_ORDER 0
67 #define TX_DC_BASE 0x130000
69 #define RX_DC_ENTRIES 64
70 #define RX_DC_ENTRIES_ORDER 2
71 #define RX_DC_BASE 0x100000
73 /* RX FIFO XOFF watermark
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
79 static int rx_xoff_thresh_bytes
= -1;
80 module_param(rx_xoff_thresh_bytes
, int, 0644);
81 MODULE_PARM_DESC(rx_xoff_thresh_bytes
, "RX fifo XOFF threshold");
83 /* RX FIFO XON watermark
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
89 static int rx_xon_thresh_bytes
= -1;
90 module_param(rx_xon_thresh_bytes
, int, 0644);
91 MODULE_PARM_DESC(rx_xon_thresh_bytes
, "RX fifo XON threshold");
93 /* TX descriptor ring size - min 512 max 4k */
94 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95 #define FALCON_TXD_RING_SIZE 1024
96 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
98 /* RX descriptor ring size - min 512 max 4k */
99 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100 #define FALCON_RXD_RING_SIZE 1024
101 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
103 /* Event queue size - max 32k */
104 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
105 #define FALCON_EVQ_SIZE 4096
106 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
108 /* Max number of internal errors. After this resets will not be performed */
109 #define FALCON_MAX_INT_ERRORS 4
111 /* Maximum period that we wait for flush events. If the flush event
112 * doesn't arrive in this period of time then we check if the queue
113 * was disabled anyway. */
114 #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
116 /**************************************************************************
120 **************************************************************************
123 /* DMA address mask */
124 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
126 /* TX DMA length mask (13-bit) */
127 #define FALCON_TX_DMA_MASK (4096 - 1)
129 /* Size and alignment of special buffers (4KB) */
130 #define FALCON_BUF_SIZE 4096
132 /* Dummy SRAM size code */
133 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
135 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
137 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
138 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
139 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
140 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
142 #define FALCON_IS_DUAL_FUNC(efx) \
143 (falcon_rev(efx) < FALCON_REV_B0)
145 /**************************************************************************
147 * Falcon hardware access
149 **************************************************************************/
151 /* Read the current event from the event queue */
152 static inline efx_qword_t
*falcon_event(struct efx_channel
*channel
,
155 return (((efx_qword_t
*) (channel
->eventq
.addr
)) + index
);
158 /* See if an event is present
160 * We check both the high and low dword of the event for all ones. We
161 * wrote all ones when we cleared the event, and no valid event can
162 * have all ones in either its high or low dwords. This approach is
163 * robust against reordering.
165 * Note that using a single 64-bit comparison is incorrect; even
166 * though the CPU read will be atomic, the DMA write may not be.
168 static inline int falcon_event_present(efx_qword_t
*event
)
170 return (!(EFX_DWORD_IS_ALL_ONES(event
->dword
[0]) |
171 EFX_DWORD_IS_ALL_ONES(event
->dword
[1])));
174 /**************************************************************************
176 * I2C bus - this is a bit-bashing interface using GPIO pins
177 * Note that it uses the output enables to tristate the outputs
178 * SDA is the data pin and SCL is the clock
180 **************************************************************************
182 static void falcon_setsda(void *data
, int state
)
184 struct efx_nic
*efx
= (struct efx_nic
*)data
;
187 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
188 EFX_SET_OWORD_FIELD(reg
, GPIO3_OEN
, !state
);
189 falcon_write(efx
, ®
, GPIO_CTL_REG_KER
);
192 static void falcon_setscl(void *data
, int state
)
194 struct efx_nic
*efx
= (struct efx_nic
*)data
;
197 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
198 EFX_SET_OWORD_FIELD(reg
, GPIO0_OEN
, !state
);
199 falcon_write(efx
, ®
, GPIO_CTL_REG_KER
);
202 static int falcon_getsda(void *data
)
204 struct efx_nic
*efx
= (struct efx_nic
*)data
;
207 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
208 return EFX_OWORD_FIELD(reg
, GPIO3_IN
);
211 static int falcon_getscl(void *data
)
213 struct efx_nic
*efx
= (struct efx_nic
*)data
;
216 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
217 return EFX_OWORD_FIELD(reg
, GPIO0_IN
);
220 static struct i2c_algo_bit_data falcon_i2c_bit_operations
= {
221 .setsda
= falcon_setsda
,
222 .setscl
= falcon_setscl
,
223 .getsda
= falcon_getsda
,
224 .getscl
= falcon_getscl
,
226 /* Wait up to 50 ms for slave to let us pull SCL high */
227 .timeout
= DIV_ROUND_UP(HZ
, 20),
230 /**************************************************************************
232 * Falcon special buffer handling
233 * Special buffers are used for event queues and the TX and RX
236 *************************************************************************/
239 * Initialise a Falcon special buffer
241 * This will define a buffer (previously allocated via
242 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243 * it to be used for event queues, descriptor rings etc.
246 falcon_init_special_buffer(struct efx_nic
*efx
,
247 struct efx_special_buffer
*buffer
)
249 efx_qword_t buf_desc
;
254 EFX_BUG_ON_PARANOID(!buffer
->addr
);
256 /* Write buffer descriptors to NIC */
257 for (i
= 0; i
< buffer
->entries
; i
++) {
258 index
= buffer
->index
+ i
;
259 dma_addr
= buffer
->dma_addr
+ (i
* 4096);
260 EFX_LOG(efx
, "mapping special buffer %d at %llx\n",
261 index
, (unsigned long long)dma_addr
);
262 EFX_POPULATE_QWORD_4(buf_desc
,
263 IP_DAT_BUF_SIZE
, IP_DAT_BUF_SIZE_4K
,
265 BUF_ADR_FBUF
, (dma_addr
>> 12),
266 BUF_OWNER_ID_FBUF
, 0);
267 falcon_write_sram(efx
, &buf_desc
, index
);
273 /* Unmaps a buffer from Falcon and clears the buffer table entries */
275 falcon_fini_special_buffer(struct efx_nic
*efx
,
276 struct efx_special_buffer
*buffer
)
278 efx_oword_t buf_tbl_upd
;
279 unsigned int start
= buffer
->index
;
280 unsigned int end
= (buffer
->index
+ buffer
->entries
- 1);
282 if (!buffer
->entries
)
285 EFX_LOG(efx
, "unmapping special buffers %d-%d\n",
286 buffer
->index
, buffer
->index
+ buffer
->entries
- 1);
288 EFX_POPULATE_OWORD_4(buf_tbl_upd
,
292 BUF_CLR_START_ID
, start
);
293 falcon_write(efx
, &buf_tbl_upd
, BUF_TBL_UPD_REG_KER
);
297 * Allocate a new Falcon special buffer
299 * This allocates memory for a new buffer, clears it and allocates a
300 * new buffer ID range. It does not write into Falcon's buffer table.
302 * This call will allocate 4KB buffers, since Falcon can't use 8KB
303 * buffers for event queues and descriptor rings.
305 static int falcon_alloc_special_buffer(struct efx_nic
*efx
,
306 struct efx_special_buffer
*buffer
,
309 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
311 len
= ALIGN(len
, FALCON_BUF_SIZE
);
313 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
318 buffer
->entries
= len
/ FALCON_BUF_SIZE
;
319 BUG_ON(buffer
->dma_addr
& (FALCON_BUF_SIZE
- 1));
321 /* All zeros is a potentially valid event so memset to 0xff */
322 memset(buffer
->addr
, 0xff, len
);
324 /* Select new buffer ID */
325 buffer
->index
= nic_data
->next_buffer_table
;
326 nic_data
->next_buffer_table
+= buffer
->entries
;
328 EFX_LOG(efx
, "allocating special buffers %d-%d at %llx+%x "
329 "(virt %p phys %lx)\n", buffer
->index
,
330 buffer
->index
+ buffer
->entries
- 1,
331 (unsigned long long)buffer
->dma_addr
, len
,
332 buffer
->addr
, virt_to_phys(buffer
->addr
));
337 static void falcon_free_special_buffer(struct efx_nic
*efx
,
338 struct efx_special_buffer
*buffer
)
343 EFX_LOG(efx
, "deallocating special buffers %d-%d at %llx+%x "
344 "(virt %p phys %lx)\n", buffer
->index
,
345 buffer
->index
+ buffer
->entries
- 1,
346 (unsigned long long)buffer
->dma_addr
, buffer
->len
,
347 buffer
->addr
, virt_to_phys(buffer
->addr
));
349 pci_free_consistent(efx
->pci_dev
, buffer
->len
, buffer
->addr
,
355 /**************************************************************************
357 * Falcon generic buffer handling
358 * These buffers are used for interrupt status and MAC stats
360 **************************************************************************/
362 static int falcon_alloc_buffer(struct efx_nic
*efx
,
363 struct efx_buffer
*buffer
, unsigned int len
)
365 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
370 memset(buffer
->addr
, 0, len
);
374 static void falcon_free_buffer(struct efx_nic
*efx
, struct efx_buffer
*buffer
)
377 pci_free_consistent(efx
->pci_dev
, buffer
->len
,
378 buffer
->addr
, buffer
->dma_addr
);
383 /**************************************************************************
387 **************************************************************************/
389 /* Returns a pointer to the specified transmit descriptor in the TX
390 * descriptor queue belonging to the specified channel.
392 static inline efx_qword_t
*falcon_tx_desc(struct efx_tx_queue
*tx_queue
,
395 return (((efx_qword_t
*) (tx_queue
->txd
.addr
)) + index
);
398 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
399 static inline void falcon_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
404 write_ptr
= tx_queue
->write_count
& FALCON_TXD_RING_MASK
;
405 EFX_POPULATE_DWORD_1(reg
, TX_DESC_WPTR_DWORD
, write_ptr
);
406 falcon_writel_page(tx_queue
->efx
, ®
,
407 TX_DESC_UPD_REG_KER_DWORD
, tx_queue
->queue
);
411 /* For each entry inserted into the software descriptor ring, create a
412 * descriptor in the hardware TX descriptor ring (in host memory), and
415 void falcon_push_buffers(struct efx_tx_queue
*tx_queue
)
418 struct efx_tx_buffer
*buffer
;
422 BUG_ON(tx_queue
->write_count
== tx_queue
->insert_count
);
425 write_ptr
= tx_queue
->write_count
& FALCON_TXD_RING_MASK
;
426 buffer
= &tx_queue
->buffer
[write_ptr
];
427 txd
= falcon_tx_desc(tx_queue
, write_ptr
);
428 ++tx_queue
->write_count
;
430 /* Create TX descriptor ring entry */
431 EFX_POPULATE_QWORD_5(*txd
,
433 TX_KER_CONT
, buffer
->continuation
,
434 TX_KER_BYTE_CNT
, buffer
->len
,
435 TX_KER_BUF_REGION
, 0,
436 TX_KER_BUF_ADR
, buffer
->dma_addr
);
437 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
439 wmb(); /* Ensure descriptors are written before they are fetched */
440 falcon_notify_tx_desc(tx_queue
);
443 /* Allocate hardware resources for a TX queue */
444 int falcon_probe_tx(struct efx_tx_queue
*tx_queue
)
446 struct efx_nic
*efx
= tx_queue
->efx
;
447 return falcon_alloc_special_buffer(efx
, &tx_queue
->txd
,
448 FALCON_TXD_RING_SIZE
*
449 sizeof(efx_qword_t
));
452 int falcon_init_tx(struct efx_tx_queue
*tx_queue
)
454 efx_oword_t tx_desc_ptr
;
455 struct efx_nic
*efx
= tx_queue
->efx
;
458 /* Pin TX descriptor ring */
459 rc
= falcon_init_special_buffer(efx
, &tx_queue
->txd
);
463 /* Push TX descriptor ring to card */
464 EFX_POPULATE_OWORD_10(tx_desc_ptr
,
468 TX_DESCQ_BUF_BASE_ID
, tx_queue
->txd
.index
,
469 TX_DESCQ_EVQ_ID
, tx_queue
->channel
->evqnum
,
470 TX_DESCQ_OWNER_ID
, 0,
471 TX_DESCQ_LABEL
, tx_queue
->queue
,
472 TX_DESCQ_SIZE
, FALCON_TXD_RING_ORDER
,
474 TX_NON_IP_DROP_DIS_B0
, 1);
476 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
477 int csum
= tx_queue
->queue
== EFX_TX_QUEUE_OFFLOAD_CSUM
;
478 EFX_SET_OWORD_FIELD(tx_desc_ptr
, TX_IP_CHKSM_DIS_B0
, !csum
);
479 EFX_SET_OWORD_FIELD(tx_desc_ptr
, TX_TCP_CHKSM_DIS_B0
, !csum
);
482 falcon_write_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
485 if (falcon_rev(efx
) < FALCON_REV_B0
) {
488 /* Only 128 bits in this register */
489 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT
>= 128);
491 falcon_read(efx
, ®
, TX_CHKSM_CFG_REG_KER_A1
);
492 if (tx_queue
->queue
== EFX_TX_QUEUE_OFFLOAD_CSUM
)
493 clear_bit_le(tx_queue
->queue
, (void *)®
);
495 set_bit_le(tx_queue
->queue
, (void *)®
);
496 falcon_write(efx
, ®
, TX_CHKSM_CFG_REG_KER_A1
);
502 static int falcon_flush_tx_queue(struct efx_tx_queue
*tx_queue
)
504 struct efx_nic
*efx
= tx_queue
->efx
;
505 struct efx_channel
*channel
= &efx
->channel
[0];
506 efx_oword_t tx_flush_descq
;
507 unsigned int read_ptr
, i
;
509 /* Post a flush command */
510 EFX_POPULATE_OWORD_2(tx_flush_descq
,
511 TX_FLUSH_DESCQ_CMD
, 1,
512 TX_FLUSH_DESCQ
, tx_queue
->queue
);
513 falcon_write(efx
, &tx_flush_descq
, TX_FLUSH_DESCQ_REG_KER
);
514 msleep(FALCON_FLUSH_TIMEOUT
);
516 if (EFX_WORKAROUND_7803(efx
))
519 /* Look for a flush completed event */
520 read_ptr
= channel
->eventq_read_ptr
;
521 for (i
= 0; i
< FALCON_EVQ_SIZE
; ++i
) {
522 efx_qword_t
*event
= falcon_event(channel
, read_ptr
);
523 int ev_code
, ev_sub_code
, ev_queue
;
524 if (!falcon_event_present(event
))
527 ev_code
= EFX_QWORD_FIELD(*event
, EV_CODE
);
528 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
529 ev_queue
= EFX_QWORD_FIELD(*event
, DRIVER_EV_TX_DESCQ_ID
);
530 if ((ev_sub_code
== TX_DESCQ_FLS_DONE_EV_DECODE
) &&
531 (ev_queue
== tx_queue
->queue
)) {
532 EFX_LOG(efx
, "tx queue %d flush command succesful\n",
537 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
540 if (EFX_WORKAROUND_11557(efx
)) {
544 falcon_read_table(efx
, ®
, efx
->type
->txd_ptr_tbl_base
,
546 enabled
= EFX_OWORD_FIELD(reg
, TX_DESCQ_EN
);
548 EFX_LOG(efx
, "tx queue %d disabled without a "
549 "flush event seen\n", tx_queue
->queue
);
554 EFX_ERR(efx
, "tx queue %d flush command timed out\n", tx_queue
->queue
);
558 void falcon_fini_tx(struct efx_tx_queue
*tx_queue
)
560 struct efx_nic
*efx
= tx_queue
->efx
;
561 efx_oword_t tx_desc_ptr
;
563 /* Stop the hardware using the queue */
564 if (falcon_flush_tx_queue(tx_queue
))
565 EFX_ERR(efx
, "failed to flush tx queue %d\n", tx_queue
->queue
);
567 /* Remove TX descriptor ring from card */
568 EFX_ZERO_OWORD(tx_desc_ptr
);
569 falcon_write_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
572 /* Unpin TX descriptor ring */
573 falcon_fini_special_buffer(efx
, &tx_queue
->txd
);
576 /* Free buffers backing TX queue */
577 void falcon_remove_tx(struct efx_tx_queue
*tx_queue
)
579 falcon_free_special_buffer(tx_queue
->efx
, &tx_queue
->txd
);
582 /**************************************************************************
586 **************************************************************************/
588 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
589 static inline efx_qword_t
*falcon_rx_desc(struct efx_rx_queue
*rx_queue
,
592 return (((efx_qword_t
*) (rx_queue
->rxd
.addr
)) + index
);
595 /* This creates an entry in the RX descriptor queue */
596 static inline void falcon_build_rx_desc(struct efx_rx_queue
*rx_queue
,
599 struct efx_rx_buffer
*rx_buf
;
602 rxd
= falcon_rx_desc(rx_queue
, index
);
603 rx_buf
= efx_rx_buffer(rx_queue
, index
);
604 EFX_POPULATE_QWORD_3(*rxd
,
607 rx_queue
->efx
->type
->rx_buffer_padding
,
608 RX_KER_BUF_REGION
, 0,
609 RX_KER_BUF_ADR
, rx_buf
->dma_addr
);
612 /* This writes to the RX_DESC_WPTR register for the specified receive
615 void falcon_notify_rx_desc(struct efx_rx_queue
*rx_queue
)
620 while (rx_queue
->notified_count
!= rx_queue
->added_count
) {
621 falcon_build_rx_desc(rx_queue
,
622 rx_queue
->notified_count
&
623 FALCON_RXD_RING_MASK
);
624 ++rx_queue
->notified_count
;
628 write_ptr
= rx_queue
->added_count
& FALCON_RXD_RING_MASK
;
629 EFX_POPULATE_DWORD_1(reg
, RX_DESC_WPTR_DWORD
, write_ptr
);
630 falcon_writel_page(rx_queue
->efx
, ®
,
631 RX_DESC_UPD_REG_KER_DWORD
, rx_queue
->queue
);
634 int falcon_probe_rx(struct efx_rx_queue
*rx_queue
)
636 struct efx_nic
*efx
= rx_queue
->efx
;
637 return falcon_alloc_special_buffer(efx
, &rx_queue
->rxd
,
638 FALCON_RXD_RING_SIZE
*
639 sizeof(efx_qword_t
));
642 int falcon_init_rx(struct efx_rx_queue
*rx_queue
)
644 efx_oword_t rx_desc_ptr
;
645 struct efx_nic
*efx
= rx_queue
->efx
;
647 int is_b0
= falcon_rev(efx
) >= FALCON_REV_B0
;
648 int iscsi_digest_en
= is_b0
;
650 EFX_LOG(efx
, "RX queue %d ring in special buffers %d-%d\n",
651 rx_queue
->queue
, rx_queue
->rxd
.index
,
652 rx_queue
->rxd
.index
+ rx_queue
->rxd
.entries
- 1);
654 /* Pin RX descriptor ring */
655 rc
= falcon_init_special_buffer(efx
, &rx_queue
->rxd
);
659 /* Push RX descriptor ring to card */
660 EFX_POPULATE_OWORD_10(rx_desc_ptr
,
661 RX_ISCSI_DDIG_EN
, iscsi_digest_en
,
662 RX_ISCSI_HDIG_EN
, iscsi_digest_en
,
663 RX_DESCQ_BUF_BASE_ID
, rx_queue
->rxd
.index
,
664 RX_DESCQ_EVQ_ID
, rx_queue
->channel
->evqnum
,
665 RX_DESCQ_OWNER_ID
, 0,
666 RX_DESCQ_LABEL
, rx_queue
->queue
,
667 RX_DESCQ_SIZE
, FALCON_RXD_RING_ORDER
,
668 RX_DESCQ_TYPE
, 0 /* kernel queue */ ,
669 /* For >=B0 this is scatter so disable */
670 RX_DESCQ_JUMBO
, !is_b0
,
672 falcon_write_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
677 static int falcon_flush_rx_queue(struct efx_rx_queue
*rx_queue
)
679 struct efx_nic
*efx
= rx_queue
->efx
;
680 struct efx_channel
*channel
= &efx
->channel
[0];
681 unsigned int read_ptr
, i
;
682 efx_oword_t rx_flush_descq
;
684 /* Post a flush command */
685 EFX_POPULATE_OWORD_2(rx_flush_descq
,
686 RX_FLUSH_DESCQ_CMD
, 1,
687 RX_FLUSH_DESCQ
, rx_queue
->queue
);
688 falcon_write(efx
, &rx_flush_descq
, RX_FLUSH_DESCQ_REG_KER
);
689 msleep(FALCON_FLUSH_TIMEOUT
);
691 if (EFX_WORKAROUND_7803(efx
))
694 /* Look for a flush completed event */
695 read_ptr
= channel
->eventq_read_ptr
;
696 for (i
= 0; i
< FALCON_EVQ_SIZE
; ++i
) {
697 efx_qword_t
*event
= falcon_event(channel
, read_ptr
);
698 int ev_code
, ev_sub_code
, ev_queue
, ev_failed
;
699 if (!falcon_event_present(event
))
702 ev_code
= EFX_QWORD_FIELD(*event
, EV_CODE
);
703 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
704 ev_queue
= EFX_QWORD_FIELD(*event
, DRIVER_EV_RX_DESCQ_ID
);
705 ev_failed
= EFX_QWORD_FIELD(*event
, DRIVER_EV_RX_FLUSH_FAIL
);
707 if ((ev_sub_code
== RX_DESCQ_FLS_DONE_EV_DECODE
) &&
708 (ev_queue
== rx_queue
->queue
)) {
710 EFX_INFO(efx
, "rx queue %d flush command "
711 "failed\n", rx_queue
->queue
);
714 EFX_LOG(efx
, "rx queue %d flush command "
715 "succesful\n", rx_queue
->queue
);
720 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
723 if (EFX_WORKAROUND_11557(efx
)) {
727 falcon_read_table(efx
, ®
, efx
->type
->rxd_ptr_tbl_base
,
729 enabled
= EFX_OWORD_FIELD(reg
, RX_DESCQ_EN
);
731 EFX_LOG(efx
, "rx queue %d disabled without a "
732 "flush event seen\n", rx_queue
->queue
);
737 EFX_ERR(efx
, "rx queue %d flush command timed out\n", rx_queue
->queue
);
741 void falcon_fini_rx(struct efx_rx_queue
*rx_queue
)
743 efx_oword_t rx_desc_ptr
;
744 struct efx_nic
*efx
= rx_queue
->efx
;
747 /* Try and flush the rx queue. This may need to be repeated */
748 for (i
= 0; i
< 5; i
++) {
749 rc
= falcon_flush_rx_queue(rx_queue
);
755 EFX_ERR(efx
, "failed to flush rx queue %d\n", rx_queue
->queue
);
756 efx_schedule_reset(efx
, RESET_TYPE_INVISIBLE
);
759 /* Remove RX descriptor ring from card */
760 EFX_ZERO_OWORD(rx_desc_ptr
);
761 falcon_write_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
764 /* Unpin RX descriptor ring */
765 falcon_fini_special_buffer(efx
, &rx_queue
->rxd
);
768 /* Free buffers backing RX queue */
769 void falcon_remove_rx(struct efx_rx_queue
*rx_queue
)
771 falcon_free_special_buffer(rx_queue
->efx
, &rx_queue
->rxd
);
774 /**************************************************************************
776 * Falcon event queue processing
777 * Event queues are processed by per-channel tasklets.
779 **************************************************************************/
781 /* Update a channel's event queue's read pointer (RPTR) register
783 * This writes the EVQ_RPTR_REG register for the specified channel's
786 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
787 * whereas channel->eventq_read_ptr contains the index of the "next to
790 void falcon_eventq_read_ack(struct efx_channel
*channel
)
793 struct efx_nic
*efx
= channel
->efx
;
795 EFX_POPULATE_DWORD_1(reg
, EVQ_RPTR_DWORD
, channel
->eventq_read_ptr
);
796 falcon_writel_table(efx
, ®
, efx
->type
->evq_rptr_tbl_base
,
800 /* Use HW to insert a SW defined event */
801 void falcon_generate_event(struct efx_channel
*channel
, efx_qword_t
*event
)
803 efx_oword_t drv_ev_reg
;
805 EFX_POPULATE_OWORD_2(drv_ev_reg
,
806 DRV_EV_QID
, channel
->evqnum
,
808 EFX_QWORD_FIELD64(*event
, WHOLE_EVENT
));
809 falcon_write(channel
->efx
, &drv_ev_reg
, DRV_EV_REG_KER
);
812 /* Handle a transmit completion event
814 * Falcon batches TX completion events; the message we receive is of
815 * the form "complete all TX events up to this index".
817 static inline void falcon_handle_tx_event(struct efx_channel
*channel
,
820 unsigned int tx_ev_desc_ptr
;
821 unsigned int tx_ev_q_label
;
822 struct efx_tx_queue
*tx_queue
;
823 struct efx_nic
*efx
= channel
->efx
;
825 if (likely(EFX_QWORD_FIELD(*event
, TX_EV_COMP
))) {
826 /* Transmit completion */
827 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, TX_EV_DESC_PTR
);
828 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, TX_EV_Q_LABEL
);
829 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
830 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
);
831 } else if (EFX_QWORD_FIELD(*event
, TX_EV_WQ_FF_FULL
)) {
832 /* Rewrite the FIFO write pointer */
833 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, TX_EV_Q_LABEL
);
834 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
836 if (efx_dev_registered(efx
))
837 netif_tx_lock(efx
->net_dev
);
838 falcon_notify_tx_desc(tx_queue
);
839 if (efx_dev_registered(efx
))
840 netif_tx_unlock(efx
->net_dev
);
841 } else if (EFX_QWORD_FIELD(*event
, TX_EV_PKT_ERR
) &&
842 EFX_WORKAROUND_10727(efx
)) {
843 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
845 EFX_ERR(efx
, "channel %d unexpected TX event "
846 EFX_QWORD_FMT
"\n", channel
->channel
,
847 EFX_QWORD_VAL(*event
));
851 /* Check received packet's destination MAC address. */
852 static int check_dest_mac(struct efx_rx_queue
*rx_queue
,
853 const efx_qword_t
*event
)
855 struct efx_rx_buffer
*rx_buf
;
856 struct efx_nic
*efx
= rx_queue
->efx
;
860 if (efx
->promiscuous
)
863 rx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, RX_EV_DESC_PTR
);
864 rx_buf
= efx_rx_buffer(rx_queue
, rx_ev_desc_ptr
);
865 eh
= (struct ethhdr
*)rx_buf
->data
;
866 if (memcmp(eh
->h_dest
, efx
->net_dev
->dev_addr
, ETH_ALEN
))
871 /* Detect errors included in the rx_evt_pkt_ok bit. */
872 static void falcon_handle_rx_not_ok(struct efx_rx_queue
*rx_queue
,
873 const efx_qword_t
*event
,
874 unsigned *rx_ev_pkt_ok
,
875 int *discard
, int byte_count
)
877 struct efx_nic
*efx
= rx_queue
->efx
;
878 unsigned rx_ev_buf_owner_id_err
, rx_ev_ip_hdr_chksum_err
;
879 unsigned rx_ev_tcp_udp_chksum_err
, rx_ev_eth_crc_err
;
880 unsigned rx_ev_frm_trunc
, rx_ev_drib_nib
, rx_ev_tobe_disc
;
881 unsigned rx_ev_pkt_type
, rx_ev_other_err
, rx_ev_pause_frm
;
882 unsigned rx_ev_ip_frag_err
, rx_ev_hdr_type
, rx_ev_mcast_pkt
;
885 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, RX_EV_HDR_TYPE
);
886 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, RX_EV_MCAST_PKT
);
887 rx_ev_tobe_disc
= EFX_QWORD_FIELD(*event
, RX_EV_TOBE_DISC
);
888 rx_ev_pkt_type
= EFX_QWORD_FIELD(*event
, RX_EV_PKT_TYPE
);
889 rx_ev_buf_owner_id_err
= EFX_QWORD_FIELD(*event
,
890 RX_EV_BUF_OWNER_ID_ERR
);
891 rx_ev_ip_frag_err
= EFX_QWORD_FIELD(*event
, RX_EV_IF_FRAG_ERR
);
892 rx_ev_ip_hdr_chksum_err
= EFX_QWORD_FIELD(*event
,
893 RX_EV_IP_HDR_CHKSUM_ERR
);
894 rx_ev_tcp_udp_chksum_err
= EFX_QWORD_FIELD(*event
,
895 RX_EV_TCP_UDP_CHKSUM_ERR
);
896 rx_ev_eth_crc_err
= EFX_QWORD_FIELD(*event
, RX_EV_ETH_CRC_ERR
);
897 rx_ev_frm_trunc
= EFX_QWORD_FIELD(*event
, RX_EV_FRM_TRUNC
);
898 rx_ev_drib_nib
= ((falcon_rev(efx
) >= FALCON_REV_B0
) ?
899 0 : EFX_QWORD_FIELD(*event
, RX_EV_DRIB_NIB
));
900 rx_ev_pause_frm
= EFX_QWORD_FIELD(*event
, RX_EV_PAUSE_FRM_ERR
);
902 /* Every error apart from tobe_disc and pause_frm */
903 rx_ev_other_err
= (rx_ev_drib_nib
| rx_ev_tcp_udp_chksum_err
|
904 rx_ev_buf_owner_id_err
| rx_ev_eth_crc_err
|
905 rx_ev_frm_trunc
| rx_ev_ip_hdr_chksum_err
);
907 snap
= (rx_ev_pkt_type
== RX_EV_PKT_TYPE_LLC_DECODE
) ||
908 (rx_ev_pkt_type
== RX_EV_PKT_TYPE_VLAN_LLC_DECODE
);
909 non_ip
= (rx_ev_hdr_type
== RX_EV_HDR_TYPE_NON_IP_DECODE
);
911 /* SFC bug 5475/8970: The Falcon XMAC incorrectly calculates the
912 * length field of an LLC frame, which sets TOBE_DISC. We could set
913 * PASS_LEN_ERR, but we want the MAC to filter out short frames (to
914 * protect the RX block).
916 * bug5475 - LLC/SNAP: Falcon identifies SNAP packets.
917 * bug8970 - LLC/noSNAP: Falcon does not provide an LLC flag.
918 * LLC can't encapsulate IP, so by definition
919 * these packets are NON_IP.
921 * Unicast mismatch will also cause TOBE_DISC, so the driver needs
924 if (EFX_WORKAROUND_5475(efx
) && rx_ev_tobe_disc
&& (snap
|| non_ip
)) {
925 /* If all the other flags are zero then we can state the
926 * entire packet is ok, which will flag to the kernel not
927 * to recalculate checksums.
929 if (!(non_ip
| rx_ev_other_err
| rx_ev_pause_frm
))
934 /* TOBE_DISC is set for unicast mismatch. But given that
935 * we can't trust TOBE_DISC here, we must validate the dest
936 * MAC address ourselves.
938 if (!rx_ev_mcast_pkt
&& !check_dest_mac(rx_queue
, event
))
942 /* Count errors that are not in MAC stats. */
944 ++rx_queue
->channel
->n_rx_frm_trunc
;
945 else if (rx_ev_tobe_disc
)
946 ++rx_queue
->channel
->n_rx_tobe_disc
;
947 else if (rx_ev_ip_hdr_chksum_err
)
948 ++rx_queue
->channel
->n_rx_ip_hdr_chksum_err
;
949 else if (rx_ev_tcp_udp_chksum_err
)
950 ++rx_queue
->channel
->n_rx_tcp_udp_chksum_err
;
951 if (rx_ev_ip_frag_err
)
952 ++rx_queue
->channel
->n_rx_ip_frag_err
;
954 /* The frame must be discarded if any of these are true. */
955 *discard
= (rx_ev_eth_crc_err
| rx_ev_frm_trunc
| rx_ev_drib_nib
|
956 rx_ev_tobe_disc
| rx_ev_pause_frm
);
958 /* TOBE_DISC is expected on unicast mismatches; don't print out an
959 * error message. FRM_TRUNC indicates RXDP dropped the packet due
960 * to a FIFO overflow.
962 #ifdef EFX_ENABLE_DEBUG
963 if (rx_ev_other_err
) {
964 EFX_INFO_RL(efx
, " RX queue %d unexpected RX event "
965 EFX_QWORD_FMT
"%s%s%s%s%s%s%s%s%s\n",
966 rx_queue
->queue
, EFX_QWORD_VAL(*event
),
967 rx_ev_buf_owner_id_err
? " [OWNER_ID_ERR]" : "",
968 rx_ev_ip_hdr_chksum_err
?
969 " [IP_HDR_CHKSUM_ERR]" : "",
970 rx_ev_tcp_udp_chksum_err
?
971 " [TCP_UDP_CHKSUM_ERR]" : "",
972 rx_ev_eth_crc_err
? " [ETH_CRC_ERR]" : "",
973 rx_ev_frm_trunc
? " [FRM_TRUNC]" : "",
974 rx_ev_drib_nib
? " [DRIB_NIB]" : "",
975 rx_ev_tobe_disc
? " [TOBE_DISC]" : "",
976 rx_ev_pause_frm
? " [PAUSE]" : "",
977 snap
? " [SNAP/LLC]" : "");
981 if (unlikely(rx_ev_eth_crc_err
&& EFX_WORKAROUND_10750(efx
) &&
982 efx
->phy_type
== PHY_TYPE_10XPRESS
))
983 tenxpress_crc_err(efx
);
986 /* Handle receive events that are not in-order. */
987 static void falcon_handle_rx_bad_index(struct efx_rx_queue
*rx_queue
,
990 struct efx_nic
*efx
= rx_queue
->efx
;
991 unsigned expected
, dropped
;
993 expected
= rx_queue
->removed_count
& FALCON_RXD_RING_MASK
;
994 dropped
= ((index
+ FALCON_RXD_RING_SIZE
- expected
) &
995 FALCON_RXD_RING_MASK
);
996 EFX_INFO(efx
, "dropped %d events (index=%d expected=%d)\n",
997 dropped
, index
, expected
);
999 efx_schedule_reset(efx
, EFX_WORKAROUND_5676(efx
) ?
1000 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
1003 /* Handle a packet received event
1005 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
1006 * wrong destination address
1007 * Also "is multicast" and "matches multicast filter" flags can be used to
1008 * discard non-matching multicast packets.
1010 static inline int falcon_handle_rx_event(struct efx_channel
*channel
,
1011 const efx_qword_t
*event
)
1013 unsigned int rx_ev_q_label
, rx_ev_desc_ptr
, rx_ev_byte_cnt
;
1014 unsigned int rx_ev_pkt_ok
, rx_ev_hdr_type
, rx_ev_mcast_pkt
;
1015 unsigned expected_ptr
;
1016 int discard
= 0, checksummed
;
1017 struct efx_rx_queue
*rx_queue
;
1018 struct efx_nic
*efx
= channel
->efx
;
1020 /* Basic packet information */
1021 rx_ev_byte_cnt
= EFX_QWORD_FIELD(*event
, RX_EV_BYTE_CNT
);
1022 rx_ev_pkt_ok
= EFX_QWORD_FIELD(*event
, RX_EV_PKT_OK
);
1023 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, RX_EV_HDR_TYPE
);
1024 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_JUMBO_CONT
));
1025 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_SOP
) != 1);
1027 rx_ev_q_label
= EFX_QWORD_FIELD(*event
, RX_EV_Q_LABEL
);
1028 rx_queue
= &efx
->rx_queue
[rx_ev_q_label
];
1030 rx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, RX_EV_DESC_PTR
);
1031 expected_ptr
= rx_queue
->removed_count
& FALCON_RXD_RING_MASK
;
1032 if (unlikely(rx_ev_desc_ptr
!= expected_ptr
)) {
1033 falcon_handle_rx_bad_index(rx_queue
, rx_ev_desc_ptr
);
1034 return rx_ev_q_label
;
1037 if (likely(rx_ev_pkt_ok
)) {
1038 /* If packet is marked as OK and packet type is TCP/IPv4 or
1039 * UDP/IPv4, then we can rely on the hardware checksum.
1041 checksummed
= RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type
);
1043 falcon_handle_rx_not_ok(rx_queue
, event
, &rx_ev_pkt_ok
,
1044 &discard
, rx_ev_byte_cnt
);
1048 /* Detect multicast packets that didn't match the filter */
1049 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, RX_EV_MCAST_PKT
);
1050 if (rx_ev_mcast_pkt
) {
1051 unsigned int rx_ev_mcast_hash_match
=
1052 EFX_QWORD_FIELD(*event
, RX_EV_MCAST_HASH_MATCH
);
1054 if (unlikely(!rx_ev_mcast_hash_match
))
1058 /* Handle received packet */
1059 efx_rx_packet(rx_queue
, rx_ev_desc_ptr
, rx_ev_byte_cnt
,
1060 checksummed
, discard
);
1062 return rx_ev_q_label
;
1065 /* Global events are basically PHY events */
1066 static void falcon_handle_global_event(struct efx_channel
*channel
,
1069 struct efx_nic
*efx
= channel
->efx
;
1070 int is_phy_event
= 0, handled
= 0;
1072 /* Check for interrupt on either port. Some boards have a
1073 * single PHY wired to the interrupt line for port 1. */
1074 if (EFX_QWORD_FIELD(*event
, G_PHY0_INTR
) ||
1075 EFX_QWORD_FIELD(*event
, G_PHY1_INTR
) ||
1076 EFX_QWORD_FIELD(*event
, XG_PHY_INTR
))
1079 if ((falcon_rev(efx
) >= FALCON_REV_B0
) &&
1080 EFX_OWORD_FIELD(*event
, XG_MNT_INTR_B0
))
1084 efx
->phy_op
->clear_interrupt(efx
);
1085 queue_work(efx
->workqueue
, &efx
->reconfigure_work
);
1089 if (EFX_QWORD_FIELD_VER(efx
, *event
, RX_RECOVERY
)) {
1090 EFX_ERR(efx
, "channel %d seen global RX_RESET "
1091 "event. Resetting.\n", channel
->channel
);
1093 atomic_inc(&efx
->rx_reset
);
1094 efx_schedule_reset(efx
, EFX_WORKAROUND_6555(efx
) ?
1095 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
1100 EFX_ERR(efx
, "channel %d unknown global event "
1101 EFX_QWORD_FMT
"\n", channel
->channel
,
1102 EFX_QWORD_VAL(*event
));
1105 static void falcon_handle_driver_event(struct efx_channel
*channel
,
1108 struct efx_nic
*efx
= channel
->efx
;
1109 unsigned int ev_sub_code
;
1110 unsigned int ev_sub_data
;
1112 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
1113 ev_sub_data
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_DATA
);
1115 switch (ev_sub_code
) {
1116 case TX_DESCQ_FLS_DONE_EV_DECODE
:
1117 EFX_TRACE(efx
, "channel %d TXQ %d flushed\n",
1118 channel
->channel
, ev_sub_data
);
1120 case RX_DESCQ_FLS_DONE_EV_DECODE
:
1121 EFX_TRACE(efx
, "channel %d RXQ %d flushed\n",
1122 channel
->channel
, ev_sub_data
);
1124 case EVQ_INIT_DONE_EV_DECODE
:
1125 EFX_LOG(efx
, "channel %d EVQ %d initialised\n",
1126 channel
->channel
, ev_sub_data
);
1128 case SRM_UPD_DONE_EV_DECODE
:
1129 EFX_TRACE(efx
, "channel %d SRAM update done\n",
1132 case WAKE_UP_EV_DECODE
:
1133 EFX_TRACE(efx
, "channel %d RXQ %d wakeup event\n",
1134 channel
->channel
, ev_sub_data
);
1136 case TIMER_EV_DECODE
:
1137 EFX_TRACE(efx
, "channel %d RX queue %d timer expired\n",
1138 channel
->channel
, ev_sub_data
);
1140 case RX_RECOVERY_EV_DECODE
:
1141 EFX_ERR(efx
, "channel %d seen DRIVER RX_RESET event. "
1142 "Resetting.\n", channel
->channel
);
1143 atomic_inc(&efx
->rx_reset
);
1144 efx_schedule_reset(efx
,
1145 EFX_WORKAROUND_6555(efx
) ?
1146 RESET_TYPE_RX_RECOVERY
:
1147 RESET_TYPE_DISABLE
);
1149 case RX_DSC_ERROR_EV_DECODE
:
1150 EFX_ERR(efx
, "RX DMA Q %d reports descriptor fetch error."
1151 " RX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
1152 efx_schedule_reset(efx
, RESET_TYPE_RX_DESC_FETCH
);
1154 case TX_DSC_ERROR_EV_DECODE
:
1155 EFX_ERR(efx
, "TX DMA Q %d reports descriptor fetch error."
1156 " TX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
1157 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
1160 EFX_TRACE(efx
, "channel %d unknown driver event code %d "
1161 "data %04x\n", channel
->channel
, ev_sub_code
,
1167 int falcon_process_eventq(struct efx_channel
*channel
, int *rx_quota
)
1169 unsigned int read_ptr
;
1170 efx_qword_t event
, *p_event
;
1175 read_ptr
= channel
->eventq_read_ptr
;
1178 p_event
= falcon_event(channel
, read_ptr
);
1181 if (!falcon_event_present(&event
))
1185 EFX_TRACE(channel
->efx
, "channel %d event is "EFX_QWORD_FMT
"\n",
1186 channel
->channel
, EFX_QWORD_VAL(event
));
1188 /* Clear this event by marking it all ones */
1189 EFX_SET_QWORD(*p_event
);
1191 ev_code
= EFX_QWORD_FIELD(event
, EV_CODE
);
1194 case RX_IP_EV_DECODE
:
1195 rxq
= falcon_handle_rx_event(channel
, &event
);
1196 rxdmaqs
|= (1 << rxq
);
1199 case TX_IP_EV_DECODE
:
1200 falcon_handle_tx_event(channel
, &event
);
1202 case DRV_GEN_EV_DECODE
:
1203 channel
->eventq_magic
1204 = EFX_QWORD_FIELD(event
, EVQ_MAGIC
);
1205 EFX_LOG(channel
->efx
, "channel %d received generated "
1206 "event "EFX_QWORD_FMT
"\n", channel
->channel
,
1207 EFX_QWORD_VAL(event
));
1209 case GLOBAL_EV_DECODE
:
1210 falcon_handle_global_event(channel
, &event
);
1212 case DRIVER_EV_DECODE
:
1213 falcon_handle_driver_event(channel
, &event
);
1216 EFX_ERR(channel
->efx
, "channel %d unknown event type %d"
1217 " (data " EFX_QWORD_FMT
")\n", channel
->channel
,
1218 ev_code
, EFX_QWORD_VAL(event
));
1221 /* Increment read pointer */
1222 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
1224 } while (*rx_quota
);
1226 channel
->eventq_read_ptr
= read_ptr
;
1230 void falcon_set_int_moderation(struct efx_channel
*channel
)
1232 efx_dword_t timer_cmd
;
1233 struct efx_nic
*efx
= channel
->efx
;
1235 /* Set timer register */
1236 if (channel
->irq_moderation
) {
1237 /* Round to resolution supported by hardware. The value we
1238 * program is based at 0. So actual interrupt moderation
1239 * achieved is ((x + 1) * res).
1241 unsigned int res
= 5;
1242 channel
->irq_moderation
-= (channel
->irq_moderation
% res
);
1243 if (channel
->irq_moderation
< res
)
1244 channel
->irq_moderation
= res
;
1245 EFX_POPULATE_DWORD_2(timer_cmd
,
1246 TIMER_MODE
, TIMER_MODE_INT_HLDOFF
,
1248 (channel
->irq_moderation
/ res
) - 1);
1250 EFX_POPULATE_DWORD_2(timer_cmd
,
1251 TIMER_MODE
, TIMER_MODE_DIS
,
1254 falcon_writel_page_locked(efx
, &timer_cmd
, TIMER_CMD_REG_KER
,
1259 /* Allocate buffer table entries for event queue */
1260 int falcon_probe_eventq(struct efx_channel
*channel
)
1262 struct efx_nic
*efx
= channel
->efx
;
1263 unsigned int evq_size
;
1265 evq_size
= FALCON_EVQ_SIZE
* sizeof(efx_qword_t
);
1266 return falcon_alloc_special_buffer(efx
, &channel
->eventq
, evq_size
);
1269 int falcon_init_eventq(struct efx_channel
*channel
)
1271 efx_oword_t evq_ptr
;
1272 struct efx_nic
*efx
= channel
->efx
;
1275 EFX_LOG(efx
, "channel %d event queue in special buffers %d-%d\n",
1276 channel
->channel
, channel
->eventq
.index
,
1277 channel
->eventq
.index
+ channel
->eventq
.entries
- 1);
1279 /* Pin event queue buffer */
1280 rc
= falcon_init_special_buffer(efx
, &channel
->eventq
);
1284 /* Fill event queue with all ones (i.e. empty events) */
1285 memset(channel
->eventq
.addr
, 0xff, channel
->eventq
.len
);
1287 /* Push event queue to card */
1288 EFX_POPULATE_OWORD_3(evq_ptr
,
1290 EVQ_SIZE
, FALCON_EVQ_ORDER
,
1291 EVQ_BUF_BASE_ID
, channel
->eventq
.index
);
1292 falcon_write_table(efx
, &evq_ptr
, efx
->type
->evq_ptr_tbl_base
,
1295 falcon_set_int_moderation(channel
);
1300 void falcon_fini_eventq(struct efx_channel
*channel
)
1302 efx_oword_t eventq_ptr
;
1303 struct efx_nic
*efx
= channel
->efx
;
1305 /* Remove event queue from card */
1306 EFX_ZERO_OWORD(eventq_ptr
);
1307 falcon_write_table(efx
, &eventq_ptr
, efx
->type
->evq_ptr_tbl_base
,
1310 /* Unpin event queue */
1311 falcon_fini_special_buffer(efx
, &channel
->eventq
);
1314 /* Free buffers backing event queue */
1315 void falcon_remove_eventq(struct efx_channel
*channel
)
1317 falcon_free_special_buffer(channel
->efx
, &channel
->eventq
);
1321 /* Generates a test event on the event queue. A subsequent call to
1322 * process_eventq() should pick up the event and place the value of
1323 * "magic" into channel->eventq_magic;
1325 void falcon_generate_test_event(struct efx_channel
*channel
, unsigned int magic
)
1327 efx_qword_t test_event
;
1329 EFX_POPULATE_QWORD_2(test_event
,
1330 EV_CODE
, DRV_GEN_EV_DECODE
,
1332 falcon_generate_event(channel
, &test_event
);
1336 /**************************************************************************
1338 * Falcon hardware interrupts
1339 * The hardware interrupt handler does very little work; all the event
1340 * queue processing is carried out by per-channel tasklets.
1342 **************************************************************************/
1344 /* Enable/disable/generate Falcon interrupts */
1345 static inline void falcon_interrupts(struct efx_nic
*efx
, int enabled
,
1348 efx_oword_t int_en_reg_ker
;
1350 EFX_POPULATE_OWORD_2(int_en_reg_ker
,
1352 DRV_INT_EN_KER
, enabled
);
1353 falcon_write(efx
, &int_en_reg_ker
, INT_EN_REG_KER
);
1356 void falcon_enable_interrupts(struct efx_nic
*efx
)
1358 efx_oword_t int_adr_reg_ker
;
1359 struct efx_channel
*channel
;
1361 EFX_ZERO_OWORD(*((efx_oword_t
*) efx
->irq_status
.addr
));
1362 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1364 /* Program address */
1365 EFX_POPULATE_OWORD_2(int_adr_reg_ker
,
1366 NORM_INT_VEC_DIS_KER
, EFX_INT_MODE_USE_MSI(efx
),
1367 INT_ADR_KER
, efx
->irq_status
.dma_addr
);
1368 falcon_write(efx
, &int_adr_reg_ker
, INT_ADR_REG_KER
);
1370 /* Enable interrupts */
1371 falcon_interrupts(efx
, 1, 0);
1373 /* Force processing of all the channels to get the EVQ RPTRs up to
1375 efx_for_each_channel_with_interrupt(channel
, efx
)
1376 efx_schedule_channel(channel
);
1379 void falcon_disable_interrupts(struct efx_nic
*efx
)
1381 /* Disable interrupts */
1382 falcon_interrupts(efx
, 0, 0);
1385 /* Generate a Falcon test interrupt
1386 * Interrupt must already have been enabled, otherwise nasty things
1389 void falcon_generate_interrupt(struct efx_nic
*efx
)
1391 falcon_interrupts(efx
, 1, 1);
1394 /* Acknowledge a legacy interrupt from Falcon
1396 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1398 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1399 * BIU. Interrupt acknowledge is read sensitive so must write instead
1400 * (then read to ensure the BIU collector is flushed)
1402 * NB most hardware supports MSI interrupts
1404 static inline void falcon_irq_ack_a1(struct efx_nic
*efx
)
1408 EFX_POPULATE_DWORD_1(reg
, INT_ACK_DUMMY_DATA
, 0xb7eb7e);
1409 falcon_writel(efx
, ®
, INT_ACK_REG_KER_A1
);
1410 falcon_readl(efx
, ®
, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1
);
1413 /* Process a fatal interrupt
1414 * Disable bus mastering ASAP and schedule a reset
1416 static irqreturn_t
falcon_fatal_interrupt(struct efx_nic
*efx
)
1418 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1419 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1420 efx_oword_t fatal_intr
;
1421 int error
, mem_perr
;
1422 static int n_int_errors
;
1424 falcon_read(efx
, &fatal_intr
, FATAL_INTR_REG_KER
);
1425 error
= EFX_OWORD_FIELD(fatal_intr
, INT_KER_ERROR
);
1427 EFX_ERR(efx
, "SYSTEM ERROR " EFX_OWORD_FMT
" status "
1428 EFX_OWORD_FMT
": %s\n", EFX_OWORD_VAL(*int_ker
),
1429 EFX_OWORD_VAL(fatal_intr
),
1430 error
? "disabling bus mastering" : "no recognised error");
1434 /* If this is a memory parity error dump which blocks are offending */
1435 mem_perr
= EFX_OWORD_FIELD(fatal_intr
, MEM_PERR_INT_KER
);
1438 falcon_read(efx
, ®
, MEM_STAT_REG_KER
);
1439 EFX_ERR(efx
, "SYSTEM ERROR: memory parity error "
1440 EFX_OWORD_FMT
"\n", EFX_OWORD_VAL(reg
));
1443 /* Disable DMA bus mastering on both devices */
1444 pci_disable_device(efx
->pci_dev
);
1445 if (FALCON_IS_DUAL_FUNC(efx
))
1446 pci_disable_device(nic_data
->pci_dev2
);
1448 if (++n_int_errors
< FALCON_MAX_INT_ERRORS
) {
1449 EFX_ERR(efx
, "SYSTEM ERROR - reset scheduled\n");
1450 efx_schedule_reset(efx
, RESET_TYPE_INT_ERROR
);
1452 EFX_ERR(efx
, "SYSTEM ERROR - max number of errors seen."
1453 "NIC will be disabled\n");
1454 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
1460 /* Handle a legacy interrupt from Falcon
1461 * Acknowledges the interrupt and schedule event queue processing.
1463 static irqreturn_t
falcon_legacy_interrupt_b0(int irq
, void *dev_id
)
1465 struct efx_nic
*efx
= dev_id
;
1466 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1467 struct efx_channel
*channel
;
1472 /* Read the ISR which also ACKs the interrupts */
1473 falcon_readl(efx
, ®
, INT_ISR0_B0
);
1474 queues
= EFX_EXTRACT_DWORD(reg
, 0, 31);
1476 /* Check to see if we have a serious error condition */
1477 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1478 if (unlikely(syserr
))
1479 return falcon_fatal_interrupt(efx
);
1484 efx
->last_irq_cpu
= raw_smp_processor_id();
1485 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1486 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1488 /* Schedule processing of any interrupting queues */
1489 channel
= &efx
->channel
[0];
1492 efx_schedule_channel(channel
);
1501 static irqreturn_t
falcon_legacy_interrupt_a1(int irq
, void *dev_id
)
1503 struct efx_nic
*efx
= dev_id
;
1504 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1505 struct efx_channel
*channel
;
1509 /* Check to see if this is our interrupt. If it isn't, we
1510 * exit without having touched the hardware.
1512 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker
))) {
1513 EFX_TRACE(efx
, "IRQ %d on CPU %d not for me\n", irq
,
1514 raw_smp_processor_id());
1517 efx
->last_irq_cpu
= raw_smp_processor_id();
1518 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1519 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1521 /* Check to see if we have a serious error condition */
1522 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1523 if (unlikely(syserr
))
1524 return falcon_fatal_interrupt(efx
);
1526 /* Determine interrupting queues, clear interrupt status
1527 * register and acknowledge the device interrupt.
1529 BUILD_BUG_ON(INT_EVQS_WIDTH
> EFX_MAX_CHANNELS
);
1530 queues
= EFX_OWORD_FIELD(*int_ker
, INT_EVQS
);
1531 EFX_ZERO_OWORD(*int_ker
);
1532 wmb(); /* Ensure the vector is cleared before interrupt ack */
1533 falcon_irq_ack_a1(efx
);
1535 /* Schedule processing of any interrupting queues */
1536 channel
= &efx
->channel
[0];
1539 efx_schedule_channel(channel
);
1547 /* Handle an MSI interrupt from Falcon
1549 * Handle an MSI hardware interrupt. This routine schedules event
1550 * queue processing. No interrupt acknowledgement cycle is necessary.
1551 * Also, we never need to check that the interrupt is for us, since
1552 * MSI interrupts cannot be shared.
1554 static irqreturn_t
falcon_msi_interrupt(int irq
, void *dev_id
)
1556 struct efx_channel
*channel
= dev_id
;
1557 struct efx_nic
*efx
= channel
->efx
;
1558 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1561 efx
->last_irq_cpu
= raw_smp_processor_id();
1562 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1563 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1565 /* Check to see if we have a serious error condition */
1566 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1567 if (unlikely(syserr
))
1568 return falcon_fatal_interrupt(efx
);
1570 /* Schedule processing of the channel */
1571 efx_schedule_channel(channel
);
1577 /* Setup RSS indirection table.
1578 * This maps from the hash value of the packet to RXQ
1580 static void falcon_setup_rss_indir_table(struct efx_nic
*efx
)
1583 unsigned long offset
;
1586 if (falcon_rev(efx
) < FALCON_REV_B0
)
1589 for (offset
= RX_RSS_INDIR_TBL_B0
;
1590 offset
< RX_RSS_INDIR_TBL_B0
+ 0x800;
1592 EFX_POPULATE_DWORD_1(dword
, RX_RSS_INDIR_ENT_B0
,
1593 i
% efx
->rss_queues
);
1594 falcon_writel(efx
, &dword
, offset
);
1599 /* Hook interrupt handler(s)
1600 * Try MSI and then legacy interrupts.
1602 int falcon_init_interrupt(struct efx_nic
*efx
)
1604 struct efx_channel
*channel
;
1607 if (!EFX_INT_MODE_USE_MSI(efx
)) {
1608 irq_handler_t handler
;
1609 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1610 handler
= falcon_legacy_interrupt_b0
;
1612 handler
= falcon_legacy_interrupt_a1
;
1614 rc
= request_irq(efx
->legacy_irq
, handler
, IRQF_SHARED
,
1617 EFX_ERR(efx
, "failed to hook legacy IRQ %d\n",
1624 /* Hook MSI or MSI-X interrupt */
1625 efx_for_each_channel_with_interrupt(channel
, efx
) {
1626 rc
= request_irq(channel
->irq
, falcon_msi_interrupt
,
1627 IRQF_PROBE_SHARED
, /* Not shared */
1628 efx
->name
, channel
);
1630 EFX_ERR(efx
, "failed to hook IRQ %d\n", channel
->irq
);
1638 efx_for_each_channel_with_interrupt(channel
, efx
)
1639 free_irq(channel
->irq
, channel
);
1644 void falcon_fini_interrupt(struct efx_nic
*efx
)
1646 struct efx_channel
*channel
;
1649 /* Disable MSI/MSI-X interrupts */
1650 efx_for_each_channel_with_interrupt(channel
, efx
) {
1652 free_irq(channel
->irq
, channel
);
1655 /* ACK legacy interrupt */
1656 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1657 falcon_read(efx
, ®
, INT_ISR0_B0
);
1659 falcon_irq_ack_a1(efx
);
1661 /* Disable legacy interrupt */
1662 if (efx
->legacy_irq
)
1663 free_irq(efx
->legacy_irq
, efx
);
1666 /**************************************************************************
1670 **************************************************************************
1673 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1675 /* Wait for SPI command completion */
1676 static int falcon_spi_wait(struct efx_nic
*efx
)
1679 int cmd_en
, timer_active
;
1684 falcon_read(efx
, ®
, EE_SPI_HCMD_REG_KER
);
1685 cmd_en
= EFX_OWORD_FIELD(reg
, EE_SPI_HCMD_CMD_EN
);
1686 timer_active
= EFX_OWORD_FIELD(reg
, EE_WR_TIMER_ACTIVE
);
1687 if (!cmd_en
&& !timer_active
)
1690 } while (++count
< 10000); /* wait upto 100msec */
1691 EFX_ERR(efx
, "timed out waiting for SPI\n");
1696 falcon_spi_read(struct efx_nic
*efx
, int device_id
, unsigned int command
,
1697 unsigned int address
, unsigned int addr_len
,
1698 void *data
, unsigned int len
)
1703 BUG_ON(len
> FALCON_SPI_MAX_LEN
);
1705 /* Check SPI not currently being accessed */
1706 rc
= falcon_spi_wait(efx
);
1710 /* Program address register */
1711 EFX_POPULATE_OWORD_1(reg
, EE_SPI_HADR_ADR
, address
);
1712 falcon_write(efx
, ®
, EE_SPI_HADR_REG_KER
);
1714 /* Issue read command */
1715 EFX_POPULATE_OWORD_7(reg
,
1716 EE_SPI_HCMD_CMD_EN
, 1,
1717 EE_SPI_HCMD_SF_SEL
, device_id
,
1718 EE_SPI_HCMD_DABCNT
, len
,
1719 EE_SPI_HCMD_READ
, EE_SPI_READ
,
1720 EE_SPI_HCMD_DUBCNT
, 0,
1721 EE_SPI_HCMD_ADBCNT
, addr_len
,
1722 EE_SPI_HCMD_ENC
, command
);
1723 falcon_write(efx
, ®
, EE_SPI_HCMD_REG_KER
);
1725 /* Wait for read to complete */
1726 rc
= falcon_spi_wait(efx
);
1731 falcon_read(efx
, ®
, EE_SPI_HDATA_REG_KER
);
1732 memcpy(data
, ®
, len
);
1736 /**************************************************************************
1740 **************************************************************************
1742 void falcon_drain_tx_fifo(struct efx_nic
*efx
)
1747 if ((falcon_rev(efx
) < FALCON_REV_B0
) ||
1748 (efx
->loopback_mode
!= LOOPBACK_NONE
))
1751 falcon_read(efx
, &temp
, MAC0_CTRL_REG_KER
);
1752 /* There is no point in draining more than once */
1753 if (EFX_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
))
1756 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1757 * the drain sequence with the statistics fetch */
1758 spin_lock(&efx
->stats_lock
);
1760 EFX_SET_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
, 1);
1761 falcon_write(efx
, &temp
, MAC0_CTRL_REG_KER
);
1763 /* Reset the MAC and EM block. */
1764 falcon_read(efx
, &temp
, GLB_CTL_REG_KER
);
1765 EFX_SET_OWORD_FIELD(temp
, RST_XGTX
, 1);
1766 EFX_SET_OWORD_FIELD(temp
, RST_XGRX
, 1);
1767 EFX_SET_OWORD_FIELD(temp
, RST_EM
, 1);
1768 falcon_write(efx
, &temp
, GLB_CTL_REG_KER
);
1772 falcon_read(efx
, &temp
, GLB_CTL_REG_KER
);
1773 if (!EFX_OWORD_FIELD(temp
, RST_XGTX
) &&
1774 !EFX_OWORD_FIELD(temp
, RST_XGRX
) &&
1775 !EFX_OWORD_FIELD(temp
, RST_EM
)) {
1776 EFX_LOG(efx
, "Completed MAC reset after %d loops\n",
1781 EFX_ERR(efx
, "MAC reset failed\n");
1788 spin_unlock(&efx
->stats_lock
);
1790 /* If we've reset the EM block and the link is up, then
1791 * we'll have to kick the XAUI link so the PHY can recover */
1792 if (efx
->link_up
&& EFX_WORKAROUND_5147(efx
))
1793 falcon_reset_xaui(efx
);
1796 void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
)
1800 if (falcon_rev(efx
) < FALCON_REV_B0
)
1803 /* Isolate the MAC -> RX */
1804 falcon_read(efx
, &temp
, RX_CFG_REG_KER
);
1805 EFX_SET_OWORD_FIELD(temp
, RX_INGR_EN_B0
, 0);
1806 falcon_write(efx
, &temp
, RX_CFG_REG_KER
);
1809 falcon_drain_tx_fifo(efx
);
1812 void falcon_reconfigure_mac_wrapper(struct efx_nic
*efx
)
1818 if (efx
->link_options
& GM_LPA_10000
)
1820 else if (efx
->link_options
& GM_LPA_1000
)
1822 else if (efx
->link_options
& GM_LPA_100
)
1826 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1827 * as advertised. Disable to ensure packets are not
1828 * indefinitely held and TX queue can be flushed at any point
1829 * while the link is down. */
1830 EFX_POPULATE_OWORD_5(reg
,
1831 MAC_XOFF_VAL
, 0xffff /* max pause time */,
1833 MAC_UC_PROM
, efx
->promiscuous
,
1834 MAC_LINK_STATUS
, 1, /* always set */
1835 MAC_SPEED
, link_speed
);
1836 /* On B0, MAC backpressure can be disabled and packets get
1838 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
1839 EFX_SET_OWORD_FIELD(reg
, TXFIFO_DRAIN_EN_B0
,
1843 falcon_write(efx
, ®
, MAC0_CTRL_REG_KER
);
1845 /* Restore the multicast hash registers. */
1846 falcon_set_multicast_hash(efx
);
1848 /* Transmission of pause frames when RX crosses the threshold is
1849 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1850 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1851 tx_fc
= (efx
->flow_control
& EFX_FC_TX
) ? 1 : 0;
1852 falcon_read(efx
, ®
, RX_CFG_REG_KER
);
1853 EFX_SET_OWORD_FIELD_VER(efx
, reg
, RX_XOFF_MAC_EN
, tx_fc
);
1855 /* Unisolate the MAC -> RX */
1856 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1857 EFX_SET_OWORD_FIELD(reg
, RX_INGR_EN_B0
, 1);
1858 falcon_write(efx
, ®
, RX_CFG_REG_KER
);
1861 int falcon_dma_stats(struct efx_nic
*efx
, unsigned int done_offset
)
1867 if (disable_dma_stats
)
1870 /* Statistics fetch will fail if the MAC is in TX drain */
1871 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
1873 falcon_read(efx
, &temp
, MAC0_CTRL_REG_KER
);
1874 if (EFX_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
))
1878 dma_done
= (efx
->stats_buffer
.addr
+ done_offset
);
1879 *dma_done
= FALCON_STATS_NOT_DONE
;
1880 wmb(); /* ensure done flag is clear */
1882 /* Initiate DMA transfer of stats */
1883 EFX_POPULATE_OWORD_2(reg
,
1884 MAC_STAT_DMA_CMD
, 1,
1886 efx
->stats_buffer
.dma_addr
);
1887 falcon_write(efx
, ®
, MAC0_STAT_DMA_REG_KER
);
1889 /* Wait for transfer to complete */
1890 for (i
= 0; i
< 400; i
++) {
1891 if (*(volatile u32
*)dma_done
== FALCON_STATS_DONE
)
1896 EFX_ERR(efx
, "timed out waiting for statistics\n");
1900 /**************************************************************************
1902 * PHY access via GMII
1904 **************************************************************************
1907 /* Use the top bit of the MII PHY id to indicate the PHY type
1908 * (1G/10G), with the remaining bits as the actual PHY id.
1910 * This allows us to avoid leaking information from the mii_if_info
1911 * structure into other data structures.
1913 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1914 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1915 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1916 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1917 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1920 /* Packing the clause 45 port and device fields into a single value */
1921 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1922 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1923 #define MD_DEV_ADR_COMP_LBN 0
1924 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1927 /* Wait for GMII access to complete */
1928 static int falcon_gmii_wait(struct efx_nic
*efx
)
1930 efx_dword_t md_stat
;
1933 for (count
= 0; count
< 1000; count
++) { /* wait upto 10ms */
1934 falcon_readl(efx
, &md_stat
, MD_STAT_REG_KER
);
1935 if (EFX_DWORD_FIELD(md_stat
, MD_BSY
) == 0) {
1936 if (EFX_DWORD_FIELD(md_stat
, MD_LNFL
) != 0 ||
1937 EFX_DWORD_FIELD(md_stat
, MD_BSERR
) != 0) {
1938 EFX_ERR(efx
, "error from GMII access "
1940 EFX_DWORD_VAL(md_stat
));
1947 EFX_ERR(efx
, "timed out waiting for GMII\n");
1951 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1952 static void falcon_mdio_write(struct net_device
*net_dev
, int phy_id
,
1953 int addr
, int value
)
1955 struct efx_nic
*efx
= netdev_priv(net_dev
);
1956 unsigned int phy_id2
= phy_id
& FALCON_PHY_ID_ID_MASK
;
1959 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1960 * chosen so that the only current user, Falcon, can take the
1961 * packed value and use them directly.
1962 * Fail to build if this assumption is broken.
1964 BUILD_BUG_ON(FALCON_PHY_ID_10G
!= MDIO45_XPRT_ID_IS10G
);
1965 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH
!= MDIO45_PRT_DEV_WIDTH
);
1966 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN
!= MDIO45_PRT_ID_COMP_LBN
);
1967 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN
!= MDIO45_DEV_ID_COMP_LBN
);
1969 if (phy_id2
== PHY_ADDR_INVALID
)
1972 /* See falcon_mdio_read for an explanation. */
1973 if (!(phy_id
& FALCON_PHY_ID_10G
)) {
1974 int mmd
= ffs(efx
->phy_op
->mmds
) - 1;
1975 EFX_TRACE(efx
, "Fixing erroneous clause22 write\n");
1976 phy_id2
= mdio_clause45_pack(phy_id2
, mmd
)
1977 & FALCON_PHY_ID_ID_MASK
;
1980 EFX_REGDUMP(efx
, "writing GMII %d register %02x with %04x\n", phy_id
,
1983 spin_lock_bh(&efx
->phy_lock
);
1985 /* Check MII not currently being accessed */
1986 if (falcon_gmii_wait(efx
) != 0)
1989 /* Write the address/ID register */
1990 EFX_POPULATE_OWORD_1(reg
, MD_PHY_ADR
, addr
);
1991 falcon_write(efx
, ®
, MD_PHY_ADR_REG_KER
);
1993 EFX_POPULATE_OWORD_1(reg
, MD_PRT_DEV_ADR
, phy_id2
);
1994 falcon_write(efx
, ®
, MD_ID_REG_KER
);
1997 EFX_POPULATE_OWORD_1(reg
, MD_TXD
, value
);
1998 falcon_write(efx
, ®
, MD_TXD_REG_KER
);
2000 EFX_POPULATE_OWORD_2(reg
,
2003 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2005 /* Wait for data to be written */
2006 if (falcon_gmii_wait(efx
) != 0) {
2007 /* Abort the write operation */
2008 EFX_POPULATE_OWORD_2(reg
,
2011 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2016 spin_unlock_bh(&efx
->phy_lock
);
2019 /* Reads a GMII register from a PHY connected to Falcon. If no value
2020 * could be read, -1 will be returned. */
2021 static int falcon_mdio_read(struct net_device
*net_dev
, int phy_id
, int addr
)
2023 struct efx_nic
*efx
= netdev_priv(net_dev
);
2024 unsigned int phy_addr
= phy_id
& FALCON_PHY_ID_ID_MASK
;
2028 if (phy_addr
== PHY_ADDR_INVALID
)
2031 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2032 * but the generic Linux code does not make any distinction or have
2033 * any state for this.
2034 * We spot the case where someone tried to talk 22 to a 45 PHY and
2035 * redirect the request to the lowest numbered MMD as a clause45
2036 * request. This is enough to allow simple queries like id and link
2037 * state to succeed. TODO: We may need to do more in future.
2039 if (!(phy_id
& FALCON_PHY_ID_10G
)) {
2040 int mmd
= ffs(efx
->phy_op
->mmds
) - 1;
2041 EFX_TRACE(efx
, "Fixing erroneous clause22 read\n");
2042 phy_addr
= mdio_clause45_pack(phy_addr
, mmd
)
2043 & FALCON_PHY_ID_ID_MASK
;
2046 spin_lock_bh(&efx
->phy_lock
);
2048 /* Check MII not currently being accessed */
2049 if (falcon_gmii_wait(efx
) != 0)
2052 EFX_POPULATE_OWORD_1(reg
, MD_PHY_ADR
, addr
);
2053 falcon_write(efx
, ®
, MD_PHY_ADR_REG_KER
);
2055 EFX_POPULATE_OWORD_1(reg
, MD_PRT_DEV_ADR
, phy_addr
);
2056 falcon_write(efx
, ®
, MD_ID_REG_KER
);
2058 /* Request data to be read */
2059 EFX_POPULATE_OWORD_2(reg
, MD_RDC
, 1, MD_GC
, 0);
2060 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2062 /* Wait for data to become available */
2063 value
= falcon_gmii_wait(efx
);
2065 falcon_read(efx
, ®
, MD_RXD_REG_KER
);
2066 value
= EFX_OWORD_FIELD(reg
, MD_RXD
);
2067 EFX_REGDUMP(efx
, "read from GMII %d register %02x, got %04x\n",
2068 phy_id
, addr
, value
);
2070 /* Abort the read operation */
2071 EFX_POPULATE_OWORD_2(reg
,
2074 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2076 EFX_LOG(efx
, "read from GMII 0x%x register %02x, got "
2077 "error %d\n", phy_id
, addr
, value
);
2081 spin_unlock_bh(&efx
->phy_lock
);
2086 static void falcon_init_mdio(struct mii_if_info
*gmii
)
2088 gmii
->mdio_read
= falcon_mdio_read
;
2089 gmii
->mdio_write
= falcon_mdio_write
;
2090 gmii
->phy_id_mask
= FALCON_PHY_ID_MASK
;
2091 gmii
->reg_num_mask
= ((1 << EFX_WIDTH(MD_PHY_ADR
)) - 1);
2094 static int falcon_probe_phy(struct efx_nic
*efx
)
2096 switch (efx
->phy_type
) {
2097 case PHY_TYPE_10XPRESS
:
2098 efx
->phy_op
= &falcon_tenxpress_phy_ops
;
2101 efx
->phy_op
= &falcon_xfp_phy_ops
;
2104 EFX_ERR(efx
, "Unknown PHY type %d\n",
2109 efx
->loopback_modes
= LOOPBACKS_10G_INTERNAL
| efx
->phy_op
->loopbacks
;
2113 /* This call is responsible for hooking in the MAC and PHY operations */
2114 int falcon_probe_port(struct efx_nic
*efx
)
2118 /* Hook in PHY operations table */
2119 rc
= falcon_probe_phy(efx
);
2123 /* Set up GMII structure for PHY */
2124 efx
->mii
.supports_gmii
= 1;
2125 falcon_init_mdio(&efx
->mii
);
2127 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2128 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2129 efx
->flow_control
= EFX_FC_RX
| EFX_FC_TX
;
2131 efx
->flow_control
= EFX_FC_RX
;
2133 /* Allocate buffer for stats */
2134 rc
= falcon_alloc_buffer(efx
, &efx
->stats_buffer
,
2135 FALCON_MAC_STATS_SIZE
);
2138 EFX_LOG(efx
, "stats buffer at %llx (virt %p phys %lx)\n",
2139 (unsigned long long)efx
->stats_buffer
.dma_addr
,
2140 efx
->stats_buffer
.addr
,
2141 virt_to_phys(efx
->stats_buffer
.addr
));
2146 void falcon_remove_port(struct efx_nic
*efx
)
2148 falcon_free_buffer(efx
, &efx
->stats_buffer
);
2151 /**************************************************************************
2153 * Multicast filtering
2155 **************************************************************************
2158 void falcon_set_multicast_hash(struct efx_nic
*efx
)
2160 union efx_multicast_hash
*mc_hash
= &efx
->multicast_hash
;
2162 /* Broadcast packets go through the multicast hash filter.
2163 * ether_crc_le() of the broadcast address is 0xbe2612ff
2164 * so we always add bit 0xff to the mask.
2166 set_bit_le(0xff, mc_hash
->byte
);
2168 falcon_write(efx
, &mc_hash
->oword
[0], MAC_MCAST_HASH_REG0_KER
);
2169 falcon_write(efx
, &mc_hash
->oword
[1], MAC_MCAST_HASH_REG1_KER
);
2172 /**************************************************************************
2176 **************************************************************************
2179 /* Resets NIC to known state. This routine must be called in process
2180 * context and is allowed to sleep. */
2181 int falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
2183 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2184 efx_oword_t glb_ctl_reg_ker
;
2187 EFX_LOG(efx
, "performing hardware reset (%d)\n", method
);
2189 /* Initiate device reset */
2190 if (method
== RESET_TYPE_WORLD
) {
2191 rc
= pci_save_state(efx
->pci_dev
);
2193 EFX_ERR(efx
, "failed to backup PCI state of primary "
2194 "function prior to hardware reset\n");
2197 if (FALCON_IS_DUAL_FUNC(efx
)) {
2198 rc
= pci_save_state(nic_data
->pci_dev2
);
2200 EFX_ERR(efx
, "failed to backup PCI state of "
2201 "secondary function prior to "
2202 "hardware reset\n");
2207 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker
,
2208 EXT_PHY_RST_DUR
, 0x7,
2211 int reset_phy
= (method
== RESET_TYPE_INVISIBLE
?
2212 EXCLUDE_FROM_RESET
: 0);
2214 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker
,
2215 EXT_PHY_RST_CTL
, reset_phy
,
2216 PCIE_CORE_RST_CTL
, EXCLUDE_FROM_RESET
,
2217 PCIE_NSTCK_RST_CTL
, EXCLUDE_FROM_RESET
,
2218 PCIE_SD_RST_CTL
, EXCLUDE_FROM_RESET
,
2219 EE_RST_CTL
, EXCLUDE_FROM_RESET
,
2220 EXT_PHY_RST_DUR
, 0x7 /* 10ms */,
2223 falcon_write(efx
, &glb_ctl_reg_ker
, GLB_CTL_REG_KER
);
2225 EFX_LOG(efx
, "waiting for hardware reset\n");
2226 schedule_timeout_uninterruptible(HZ
/ 20);
2228 /* Restore PCI configuration if needed */
2229 if (method
== RESET_TYPE_WORLD
) {
2230 if (FALCON_IS_DUAL_FUNC(efx
)) {
2231 rc
= pci_restore_state(nic_data
->pci_dev2
);
2233 EFX_ERR(efx
, "failed to restore PCI config for "
2234 "the secondary function\n");
2238 rc
= pci_restore_state(efx
->pci_dev
);
2240 EFX_ERR(efx
, "failed to restore PCI config for the "
2241 "primary function\n");
2244 EFX_LOG(efx
, "successfully restored PCI config\n");
2247 /* Assert that reset complete */
2248 falcon_read(efx
, &glb_ctl_reg_ker
, GLB_CTL_REG_KER
);
2249 if (EFX_OWORD_FIELD(glb_ctl_reg_ker
, SWRST
) != 0) {
2251 EFX_ERR(efx
, "timed out waiting for hardware reset\n");
2254 EFX_LOG(efx
, "hardware reset complete\n");
2258 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2261 pci_restore_state(efx
->pci_dev
);
2268 /* Zeroes out the SRAM contents. This routine must be called in
2269 * process context and is allowed to sleep.
2271 static int falcon_reset_sram(struct efx_nic
*efx
)
2273 efx_oword_t srm_cfg_reg_ker
, gpio_cfg_reg_ker
;
2276 /* Set the SRAM wake/sleep GPIO appropriately. */
2277 falcon_read(efx
, &gpio_cfg_reg_ker
, GPIO_CTL_REG_KER
);
2278 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, GPIO1_OEN
, 1);
2279 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, GPIO1_OUT
, 1);
2280 falcon_write(efx
, &gpio_cfg_reg_ker
, GPIO_CTL_REG_KER
);
2282 /* Initiate SRAM reset */
2283 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker
,
2284 SRAM_OOB_BT_INIT_EN
, 1,
2285 SRM_NUM_BANKS_AND_BANK_SIZE
, 0);
2286 falcon_write(efx
, &srm_cfg_reg_ker
, SRM_CFG_REG_KER
);
2288 /* Wait for SRAM reset to complete */
2291 EFX_LOG(efx
, "waiting for SRAM reset (attempt %d)...\n", count
);
2293 /* SRAM reset is slow; expect around 16ms */
2294 schedule_timeout_uninterruptible(HZ
/ 50);
2296 /* Check for reset complete */
2297 falcon_read(efx
, &srm_cfg_reg_ker
, SRM_CFG_REG_KER
);
2298 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker
, SRAM_OOB_BT_INIT_EN
)) {
2299 EFX_LOG(efx
, "SRAM reset complete\n");
2303 } while (++count
< 20); /* wait upto 0.4 sec */
2305 EFX_ERR(efx
, "timed out waiting for SRAM reset\n");
2309 /* Extract non-volatile configuration */
2310 static int falcon_probe_nvconfig(struct efx_nic
*efx
)
2312 struct falcon_nvconfig
*nvconfig
;
2313 efx_oword_t nic_stat
;
2317 int magic_num
, struct_ver
, board_rev
;
2320 /* Find the boot device. */
2321 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2322 if (EFX_OWORD_FIELD(nic_stat
, SF_PRST
)) {
2323 device_id
= EE_SPI_FLASH
;
2325 } else if (EFX_OWORD_FIELD(nic_stat
, EE_PRST
)) {
2326 device_id
= EE_SPI_EEPROM
;
2332 nvconfig
= kmalloc(sizeof(*nvconfig
), GFP_KERNEL
);
2334 /* Read the whole configuration structure into memory. */
2335 for (offset
= 0; offset
< sizeof(*nvconfig
); offset
+= len
) {
2336 len
= min(sizeof(*nvconfig
) - offset
,
2337 (size_t) FALCON_SPI_MAX_LEN
);
2338 rc
= falcon_spi_read(efx
, device_id
, SPI_READ
,
2339 NVCONFIG_BASE
+ offset
, addr_len
,
2340 (char *)nvconfig
+ offset
, len
);
2345 /* Read the MAC addresses */
2346 memcpy(efx
->mac_address
, nvconfig
->mac_address
[0], ETH_ALEN
);
2348 /* Read the board configuration. */
2349 magic_num
= le16_to_cpu(nvconfig
->board_magic_num
);
2350 struct_ver
= le16_to_cpu(nvconfig
->board_struct_ver
);
2352 if (magic_num
!= NVCONFIG_BOARD_MAGIC_NUM
|| struct_ver
< 2) {
2353 EFX_ERR(efx
, "Non volatile memory bad magic=%x ver=%x "
2354 "therefore using defaults\n", magic_num
, struct_ver
);
2355 efx
->phy_type
= PHY_TYPE_NONE
;
2356 efx
->mii
.phy_id
= PHY_ADDR_INVALID
;
2359 struct falcon_nvconfig_board_v2
*v2
= &nvconfig
->board_v2
;
2361 efx
->phy_type
= v2
->port0_phy_type
;
2362 efx
->mii
.phy_id
= v2
->port0_phy_addr
;
2363 board_rev
= le16_to_cpu(v2
->board_revision
);
2366 EFX_LOG(efx
, "PHY is %d phy_id %d\n", efx
->phy_type
, efx
->mii
.phy_id
);
2368 efx_set_board_info(efx
, board_rev
);
2375 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2376 * count, port speed). Set workaround and feature flags accordingly.
2378 static int falcon_probe_nic_variant(struct efx_nic
*efx
)
2380 efx_oword_t altera_build
;
2382 falcon_read(efx
, &altera_build
, ALTERA_BUILD_REG_KER
);
2383 if (EFX_OWORD_FIELD(altera_build
, VER_ALL
)) {
2384 EFX_ERR(efx
, "Falcon FPGA not supported\n");
2388 switch (falcon_rev(efx
)) {
2391 EFX_ERR(efx
, "Falcon rev A0 not supported\n");
2394 case FALCON_REV_A1
:{
2395 efx_oword_t nic_stat
;
2397 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2399 if (EFX_OWORD_FIELD(nic_stat
, STRAP_PCIE
) == 0) {
2400 EFX_ERR(efx
, "Falcon rev A1 PCI-X not supported\n");
2403 if (!EFX_OWORD_FIELD(nic_stat
, STRAP_10G
)) {
2404 EFX_ERR(efx
, "1G mode not supported\n");
2414 EFX_ERR(efx
, "Unknown Falcon rev %d\n", falcon_rev(efx
));
2421 int falcon_probe_nic(struct efx_nic
*efx
)
2423 struct falcon_nic_data
*nic_data
;
2426 /* Allocate storage for hardware specific data */
2427 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
2428 efx
->nic_data
= nic_data
;
2430 /* Determine number of ports etc. */
2431 rc
= falcon_probe_nic_variant(efx
);
2435 /* Probe secondary function if expected */
2436 if (FALCON_IS_DUAL_FUNC(efx
)) {
2437 struct pci_dev
*dev
= pci_dev_get(efx
->pci_dev
);
2439 while ((dev
= pci_get_device(EFX_VENDID_SFC
, FALCON_A_S_DEVID
,
2441 if (dev
->bus
== efx
->pci_dev
->bus
&&
2442 dev
->devfn
== efx
->pci_dev
->devfn
+ 1) {
2443 nic_data
->pci_dev2
= dev
;
2447 if (!nic_data
->pci_dev2
) {
2448 EFX_ERR(efx
, "failed to find secondary function\n");
2454 /* Now we can reset the NIC */
2455 rc
= falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2457 EFX_ERR(efx
, "failed to reset NIC\n");
2461 /* Allocate memory for INT_KER */
2462 rc
= falcon_alloc_buffer(efx
, &efx
->irq_status
, sizeof(efx_oword_t
));
2465 BUG_ON(efx
->irq_status
.dma_addr
& 0x0f);
2467 EFX_LOG(efx
, "INT_KER at %llx (virt %p phys %lx)\n",
2468 (unsigned long long)efx
->irq_status
.dma_addr
,
2469 efx
->irq_status
.addr
, virt_to_phys(efx
->irq_status
.addr
));
2471 /* Read in the non-volatile configuration */
2472 rc
= falcon_probe_nvconfig(efx
);
2476 /* Initialise I2C adapter */
2477 efx
->i2c_adap
.owner
= THIS_MODULE
;
2478 nic_data
->i2c_data
= falcon_i2c_bit_operations
;
2479 nic_data
->i2c_data
.data
= efx
;
2480 efx
->i2c_adap
.algo_data
= &nic_data
->i2c_data
;
2481 efx
->i2c_adap
.dev
.parent
= &efx
->pci_dev
->dev
;
2482 strlcpy(efx
->i2c_adap
.name
, "SFC4000 GPIO", sizeof(efx
->i2c_adap
.name
));
2483 rc
= i2c_bit_add_bus(&efx
->i2c_adap
);
2490 falcon_free_buffer(efx
, &efx
->irq_status
);
2493 if (nic_data
->pci_dev2
) {
2494 pci_dev_put(nic_data
->pci_dev2
);
2495 nic_data
->pci_dev2
= NULL
;
2499 kfree(efx
->nic_data
);
2503 /* This call performs hardware-specific global initialisation, such as
2504 * defining the descriptor cache sizes and number of RSS channels.
2505 * It does not set up any buffers, descriptor rings or event queues.
2507 int falcon_init_nic(struct efx_nic
*efx
)
2513 /* Set up the address region register. This is only needed
2514 * for the B0 FPGA, but since we are just pushing in the
2515 * reset defaults this may as well be unconditional. */
2516 EFX_POPULATE_OWORD_4(temp
, ADR_REGION0
, 0,
2517 ADR_REGION1
, (1 << 16),
2518 ADR_REGION2
, (2 << 16),
2519 ADR_REGION3
, (3 << 16));
2520 falcon_write(efx
, &temp
, ADR_REGION_REG_KER
);
2522 /* Use on-chip SRAM */
2523 falcon_read(efx
, &temp
, NIC_STAT_REG
);
2524 EFX_SET_OWORD_FIELD(temp
, ONCHIP_SRAM
, 1);
2525 falcon_write(efx
, &temp
, NIC_STAT_REG
);
2527 /* Set buffer table mode */
2528 EFX_POPULATE_OWORD_1(temp
, BUF_TBL_MODE
, BUF_TBL_MODE_FULL
);
2529 falcon_write(efx
, &temp
, BUF_TBL_CFG_REG_KER
);
2531 rc
= falcon_reset_sram(efx
);
2535 /* Set positions of descriptor caches in SRAM. */
2536 EFX_POPULATE_OWORD_1(temp
, SRM_TX_DC_BASE_ADR
, TX_DC_BASE
/ 8);
2537 falcon_write(efx
, &temp
, SRM_TX_DC_CFG_REG_KER
);
2538 EFX_POPULATE_OWORD_1(temp
, SRM_RX_DC_BASE_ADR
, RX_DC_BASE
/ 8);
2539 falcon_write(efx
, &temp
, SRM_RX_DC_CFG_REG_KER
);
2541 /* Set TX descriptor cache size. */
2542 BUILD_BUG_ON(TX_DC_ENTRIES
!= (16 << TX_DC_ENTRIES_ORDER
));
2543 EFX_POPULATE_OWORD_1(temp
, TX_DC_SIZE
, TX_DC_ENTRIES_ORDER
);
2544 falcon_write(efx
, &temp
, TX_DC_CFG_REG_KER
);
2546 /* Set RX descriptor cache size. Set low watermark to size-8, as
2547 * this allows most efficient prefetching.
2549 BUILD_BUG_ON(RX_DC_ENTRIES
!= (16 << RX_DC_ENTRIES_ORDER
));
2550 EFX_POPULATE_OWORD_1(temp
, RX_DC_SIZE
, RX_DC_ENTRIES_ORDER
);
2551 falcon_write(efx
, &temp
, RX_DC_CFG_REG_KER
);
2552 EFX_POPULATE_OWORD_1(temp
, RX_DC_PF_LWM
, RX_DC_ENTRIES
- 8);
2553 falcon_write(efx
, &temp
, RX_DC_PF_WM_REG_KER
);
2555 /* Clear the parity enables on the TX data fifos as
2556 * they produce false parity errors because of timing issues
2558 if (EFX_WORKAROUND_5129(efx
)) {
2559 falcon_read(efx
, &temp
, SPARE_REG_KER
);
2560 EFX_SET_OWORD_FIELD(temp
, MEM_PERR_EN_TX_DATA
, 0);
2561 falcon_write(efx
, &temp
, SPARE_REG_KER
);
2564 /* Enable all the genuinely fatal interrupts. (They are still
2565 * masked by the overall interrupt mask, controlled by
2566 * falcon_interrupts()).
2568 * Note: All other fatal interrupts are enabled
2570 EFX_POPULATE_OWORD_3(temp
,
2571 ILL_ADR_INT_KER_EN
, 1,
2572 RBUF_OWN_INT_KER_EN
, 1,
2573 TBUF_OWN_INT_KER_EN
, 1);
2574 EFX_INVERT_OWORD(temp
);
2575 falcon_write(efx
, &temp
, FATAL_INTR_REG_KER
);
2577 /* Set number of RSS queues for receive path. */
2578 falcon_read(efx
, &temp
, RX_FILTER_CTL_REG
);
2579 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2580 EFX_SET_OWORD_FIELD(temp
, NUM_KER
, 0);
2582 EFX_SET_OWORD_FIELD(temp
, NUM_KER
, efx
->rss_queues
- 1);
2583 if (EFX_WORKAROUND_7244(efx
)) {
2584 EFX_SET_OWORD_FIELD(temp
, UDP_FULL_SRCH_LIMIT
, 8);
2585 EFX_SET_OWORD_FIELD(temp
, UDP_WILD_SRCH_LIMIT
, 8);
2586 EFX_SET_OWORD_FIELD(temp
, TCP_FULL_SRCH_LIMIT
, 8);
2587 EFX_SET_OWORD_FIELD(temp
, TCP_WILD_SRCH_LIMIT
, 8);
2589 falcon_write(efx
, &temp
, RX_FILTER_CTL_REG
);
2591 falcon_setup_rss_indir_table(efx
);
2593 /* Setup RX. Wait for descriptor is broken and must
2594 * be disabled. RXDP recovery shouldn't be needed, but is.
2596 falcon_read(efx
, &temp
, RX_SELF_RST_REG_KER
);
2597 EFX_SET_OWORD_FIELD(temp
, RX_NODESC_WAIT_DIS
, 1);
2598 EFX_SET_OWORD_FIELD(temp
, RX_RECOVERY_EN
, 1);
2599 if (EFX_WORKAROUND_5583(efx
))
2600 EFX_SET_OWORD_FIELD(temp
, RX_ISCSI_DIS
, 1);
2601 falcon_write(efx
, &temp
, RX_SELF_RST_REG_KER
);
2603 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2604 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2606 falcon_read(efx
, &temp
, TX_CFG2_REG_KER
);
2607 EFX_SET_OWORD_FIELD(temp
, TX_RX_SPACER
, 0xfe);
2608 EFX_SET_OWORD_FIELD(temp
, TX_RX_SPACER_EN
, 1);
2609 EFX_SET_OWORD_FIELD(temp
, TX_ONE_PKT_PER_Q
, 1);
2610 EFX_SET_OWORD_FIELD(temp
, TX_CSR_PUSH_EN
, 0);
2611 EFX_SET_OWORD_FIELD(temp
, TX_DIS_NON_IP_EV
, 1);
2612 /* Enable SW_EV to inherit in char driver - assume harmless here */
2613 EFX_SET_OWORD_FIELD(temp
, TX_SW_EV_EN
, 1);
2614 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2615 EFX_SET_OWORD_FIELD(temp
, TX_PREF_THRESHOLD
, 2);
2616 /* Squash TX of packets of 16 bytes or less */
2617 if (falcon_rev(efx
) >= FALCON_REV_B0
&& EFX_WORKAROUND_9141(efx
))
2618 EFX_SET_OWORD_FIELD(temp
, TX_FLUSH_MIN_LEN_EN_B0
, 1);
2619 falcon_write(efx
, &temp
, TX_CFG2_REG_KER
);
2621 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2622 * descriptors (which is bad).
2624 falcon_read(efx
, &temp
, TX_CFG_REG_KER
);
2625 EFX_SET_OWORD_FIELD(temp
, TX_NO_EOP_DISC_EN
, 0);
2626 falcon_write(efx
, &temp
, TX_CFG_REG_KER
);
2629 falcon_read(efx
, &temp
, RX_CFG_REG_KER
);
2630 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_DESC_PUSH_EN
, 0);
2631 if (EFX_WORKAROUND_7575(efx
))
2632 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_USR_BUF_SIZE
,
2634 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2635 EFX_SET_OWORD_FIELD(temp
, RX_INGR_EN_B0
, 1);
2637 /* RX FIFO flow control thresholds */
2638 thresh
= ((rx_xon_thresh_bytes
>= 0) ?
2639 rx_xon_thresh_bytes
: efx
->type
->rx_xon_thresh
);
2640 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XON_MAC_TH
, thresh
/ 256);
2641 thresh
= ((rx_xoff_thresh_bytes
>= 0) ?
2642 rx_xoff_thresh_bytes
: efx
->type
->rx_xoff_thresh
);
2643 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XOFF_MAC_TH
, thresh
/ 256);
2644 /* RX control FIFO thresholds [32 entries] */
2645 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XON_TX_TH
, 25);
2646 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XOFF_TX_TH
, 20);
2647 falcon_write(efx
, &temp
, RX_CFG_REG_KER
);
2649 /* Set destination of both TX and RX Flush events */
2650 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
2651 EFX_POPULATE_OWORD_1(temp
, FLS_EVQ_ID
, 0);
2652 falcon_write(efx
, &temp
, DP_CTRL_REG
);
2658 void falcon_remove_nic(struct efx_nic
*efx
)
2660 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2663 rc
= i2c_del_adapter(&efx
->i2c_adap
);
2666 falcon_free_buffer(efx
, &efx
->irq_status
);
2668 falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2670 /* Release the second function after the reset */
2671 if (nic_data
->pci_dev2
) {
2672 pci_dev_put(nic_data
->pci_dev2
);
2673 nic_data
->pci_dev2
= NULL
;
2676 /* Tear down the private nic state */
2677 kfree(efx
->nic_data
);
2678 efx
->nic_data
= NULL
;
2681 void falcon_update_nic_stats(struct efx_nic
*efx
)
2685 falcon_read(efx
, &cnt
, RX_NODESC_DROP_REG_KER
);
2686 efx
->n_rx_nodesc_drop_cnt
+= EFX_OWORD_FIELD(cnt
, RX_NODESC_DROP_CNT
);
2689 /**************************************************************************
2691 * Revision-dependent attributes used by efx.c
2693 **************************************************************************
2696 struct efx_nic_type falcon_a_nic_type
= {
2698 .mem_map_size
= 0x20000,
2699 .txd_ptr_tbl_base
= TX_DESC_PTR_TBL_KER_A1
,
2700 .rxd_ptr_tbl_base
= RX_DESC_PTR_TBL_KER_A1
,
2701 .buf_tbl_base
= BUF_TBL_KER_A1
,
2702 .evq_ptr_tbl_base
= EVQ_PTR_TBL_KER_A1
,
2703 .evq_rptr_tbl_base
= EVQ_RPTR_REG_KER_A1
,
2704 .txd_ring_mask
= FALCON_TXD_RING_MASK
,
2705 .rxd_ring_mask
= FALCON_RXD_RING_MASK
,
2706 .evq_size
= FALCON_EVQ_SIZE
,
2707 .max_dma_mask
= FALCON_DMA_MASK
,
2708 .tx_dma_mask
= FALCON_TX_DMA_MASK
,
2709 .bug5391_mask
= 0xf,
2710 .rx_xoff_thresh
= 2048,
2711 .rx_xon_thresh
= 512,
2712 .rx_buffer_padding
= 0x24,
2713 .max_interrupt_mode
= EFX_INT_MODE_MSI
,
2714 .phys_addr_channels
= 4,
2717 struct efx_nic_type falcon_b_nic_type
= {
2719 /* Map everything up to and including the RSS indirection
2720 * table. Don't map MSI-X table, MSI-X PBA since Linux
2721 * requires that they not be mapped. */
2722 .mem_map_size
= RX_RSS_INDIR_TBL_B0
+ 0x800,
2723 .txd_ptr_tbl_base
= TX_DESC_PTR_TBL_KER_B0
,
2724 .rxd_ptr_tbl_base
= RX_DESC_PTR_TBL_KER_B0
,
2725 .buf_tbl_base
= BUF_TBL_KER_B0
,
2726 .evq_ptr_tbl_base
= EVQ_PTR_TBL_KER_B0
,
2727 .evq_rptr_tbl_base
= EVQ_RPTR_REG_KER_B0
,
2728 .txd_ring_mask
= FALCON_TXD_RING_MASK
,
2729 .rxd_ring_mask
= FALCON_RXD_RING_MASK
,
2730 .evq_size
= FALCON_EVQ_SIZE
,
2731 .max_dma_mask
= FALCON_DMA_MASK
,
2732 .tx_dma_mask
= FALCON_TX_DMA_MASK
,
2734 .rx_xoff_thresh
= 54272, /* ~80Kb - 3*max MTU */
2735 .rx_xon_thresh
= 27648, /* ~3*max MTU */
2736 .rx_buffer_padding
= 0,
2737 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
2738 .phys_addr_channels
= 32, /* Hardware limit is 64, but the legacy
2739 * interrupt handler only supports 32