1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #if defined(EFX_ENABLE_DEBUG) && !defined(DEBUG)
20 #include <linux/version.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_vlan.h>
25 #include <linux/timer.h>
26 #include <linux/mdio.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/device.h>
30 #include <linux/highmem.h>
31 #include <linux/workqueue.h>
32 #include <linux/vmalloc.h>
33 #include <linux/i2c.h>
38 /**************************************************************************
42 **************************************************************************/
44 #define EFX_DRIVER_VERSION "3.0"
46 #ifdef EFX_ENABLE_DEBUG
47 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
50 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
51 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
54 /**************************************************************************
58 **************************************************************************/
60 #define EFX_MAX_CHANNELS 32
61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
63 /* Checksum generation is a per-queue option in hardware, so each
64 * queue visible to the networking core is backed by two hardware TX
66 #define EFX_MAX_TX_TC 2
67 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
68 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
69 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
70 #define EFX_TXQ_TYPES 4
71 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
74 * struct efx_special_buffer - An Efx special buffer
75 * @addr: CPU base address of the buffer
76 * @dma_addr: DMA base address of the buffer
77 * @len: Buffer length, in bytes
78 * @index: Buffer index within controller;s buffer table
79 * @entries: Number of buffer table entries
81 * Special buffers are used for the event queues and the TX and RX
82 * descriptor queues for each channel. They are *not* used for the
83 * actual transmit and receive buffers.
85 struct efx_special_buffer
{
93 enum efx_flush_state
{
101 * struct efx_tx_buffer - An Efx TX buffer
102 * @skb: The associated socket buffer.
103 * Set only on the final fragment of a packet; %NULL for all other
104 * fragments. When this fragment completes, then we can free this
106 * @tsoh: The associated TSO header structure, or %NULL if this
107 * buffer is not a TSO header.
108 * @dma_addr: DMA address of the fragment.
109 * @len: Length of this fragment.
110 * This field is zero when the queue slot is empty.
111 * @continuation: True if this fragment is not the end of a packet.
112 * @unmap_single: True if pci_unmap_single should be used.
113 * @unmap_len: Length of this fragment to unmap
115 struct efx_tx_buffer
{
116 const struct sk_buff
*skb
;
117 struct efx_tso_header
*tsoh
;
122 unsigned short unmap_len
;
126 * struct efx_tx_queue - An Efx TX queue
128 * This is a ring buffer of TX fragments.
129 * Since the TX completion path always executes on the same
130 * CPU and the xmit path can operate on different CPUs,
131 * performance is increased by ensuring that the completion
132 * path and the xmit path operate on different cache lines.
133 * This is particularly important if the xmit path is always
134 * executing on one CPU which is different from the completion
135 * path. There is also a cache line for members which are
136 * read but not written on the fast path.
138 * @efx: The associated Efx NIC
139 * @queue: DMA queue number
140 * @channel: The associated channel
141 * @core_txq: The networking core TX queue structure
142 * @buffer: The software buffer ring
143 * @txd: The hardware descriptor ring
144 * @ptr_mask: The size of the ring minus 1.
145 * @initialised: Has hardware queue been initialised?
146 * @flushed: Used when handling queue flushing
147 * @read_count: Current read pointer.
148 * This is the number of buffers that have been removed from both rings.
149 * @old_write_count: The value of @write_count when last checked.
150 * This is here for performance reasons. The xmit path will
151 * only get the up-to-date value of @write_count if this
152 * variable indicates that the queue is empty. This is to
153 * avoid cache-line ping-pong between the xmit path and the
155 * @insert_count: Current insert pointer
156 * This is the number of buffers that have been added to the
158 * @write_count: Current write pointer
159 * This is the number of buffers that have been added to the
161 * @old_read_count: The value of read_count when last checked.
162 * This is here for performance reasons. The xmit path will
163 * only get the up-to-date value of read_count if this
164 * variable indicates that the queue is full. This is to
165 * avoid cache-line ping-pong between the xmit path and the
167 * @tso_headers_free: A list of TSO headers allocated for this TX queue
168 * that are not in use, and so available for new TSO sends. The list
169 * is protected by the TX queue lock.
170 * @tso_bursts: Number of times TSO xmit invoked by kernel
171 * @tso_long_headers: Number of packets with headers too long for standard
173 * @tso_packets: Number of packets via the TSO xmit path
174 * @pushes: Number of times the TX push feature has been used
175 * @empty_read_count: If the completion path has seen the queue as empty
176 * and the transmission path has not yet checked this, the value of
177 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
179 struct efx_tx_queue
{
180 /* Members which don't change on the fast path */
181 struct efx_nic
*efx ____cacheline_aligned_in_smp
;
183 struct efx_channel
*channel
;
184 struct netdev_queue
*core_txq
;
185 struct efx_tx_buffer
*buffer
;
186 struct efx_special_buffer txd
;
187 unsigned int ptr_mask
;
189 enum efx_flush_state flushed
;
191 /* Members used mainly on the completion path */
192 unsigned int read_count ____cacheline_aligned_in_smp
;
193 unsigned int old_write_count
;
195 /* Members used only on the xmit path */
196 unsigned int insert_count ____cacheline_aligned_in_smp
;
197 unsigned int write_count
;
198 unsigned int old_read_count
;
199 struct efx_tso_header
*tso_headers_free
;
200 unsigned int tso_bursts
;
201 unsigned int tso_long_headers
;
202 unsigned int tso_packets
;
205 /* Members shared between paths and sometimes updated */
206 unsigned int empty_read_count ____cacheline_aligned_in_smp
;
207 #define EFX_EMPTY_COUNT_VALID 0x80000000
211 * struct efx_rx_buffer - An Efx RX data buffer
212 * @dma_addr: DMA base address of the buffer
213 * @skb: The associated socket buffer, if any.
214 * If both this and page are %NULL, the buffer slot is currently free.
215 * @page: The associated page buffer, if any.
216 * If both this and skb are %NULL, the buffer slot is currently free.
217 * @data: Pointer to ethernet header
218 * @len: Buffer length, in bytes.
220 struct efx_rx_buffer
{
229 * struct efx_rx_page_state - Page-based rx buffer state
231 * Inserted at the start of every page allocated for receive buffers.
232 * Used to facilitate sharing dma mappings between recycled rx buffers
233 * and those passed up to the kernel.
235 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
236 * When refcnt falls to zero, the page is unmapped for dma
237 * @dma_addr: The dma address of this page.
239 struct efx_rx_page_state
{
243 unsigned int __pad
[0] ____cacheline_aligned
;
247 * struct efx_rx_queue - An Efx RX queue
248 * @efx: The associated Efx NIC
249 * @buffer: The software buffer ring
250 * @rxd: The hardware descriptor ring
251 * @ptr_mask: The size of the ring minus 1.
252 * @added_count: Number of buffers added to the receive queue.
253 * @notified_count: Number of buffers given to NIC (<= @added_count).
254 * @removed_count: Number of buffers removed from the receive queue.
255 * @max_fill: RX descriptor maximum fill level (<= ring size)
256 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
258 * @fast_fill_limit: The level to which a fast fill will fill
259 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
260 * @min_fill: RX descriptor minimum non-zero fill level.
261 * This records the minimum fill level observed when a ring
262 * refill was triggered.
263 * @alloc_page_count: RX allocation strategy counter.
264 * @alloc_skb_count: RX allocation strategy counter.
265 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
266 * @flushed: Use when handling queue flushing
268 struct efx_rx_queue
{
270 struct efx_rx_buffer
*buffer
;
271 struct efx_special_buffer rxd
;
272 unsigned int ptr_mask
;
277 unsigned int max_fill
;
278 unsigned int fast_fill_trigger
;
279 unsigned int fast_fill_limit
;
280 unsigned int min_fill
;
281 unsigned int min_overfill
;
282 unsigned int alloc_page_count
;
283 unsigned int alloc_skb_count
;
284 struct timer_list slow_fill
;
285 unsigned int slow_fill_count
;
287 enum efx_flush_state flushed
;
291 * struct efx_buffer - An Efx general-purpose buffer
292 * @addr: host base address of the buffer
293 * @dma_addr: DMA base address of the buffer
294 * @len: Buffer length, in bytes
296 * The NIC uses these buffers for its interrupt status registers and
306 enum efx_rx_alloc_method
{
307 RX_ALLOC_METHOD_AUTO
= 0,
308 RX_ALLOC_METHOD_SKB
= 1,
309 RX_ALLOC_METHOD_PAGE
= 2,
313 * struct efx_channel - An Efx channel
315 * A channel comprises an event queue, at least one TX queue, at least
316 * one RX queue, and an associated tasklet for processing the event
319 * @efx: Associated Efx NIC
320 * @channel: Channel instance number
321 * @enabled: Channel enabled indicator
322 * @irq: IRQ number (MSI and MSI-X only)
323 * @irq_moderation: IRQ moderation value (in hardware ticks)
324 * @napi_dev: Net device used with NAPI
325 * @napi_str: NAPI control structure
326 * @work_pending: Is work pending via NAPI?
327 * @eventq: Event queue buffer
328 * @eventq_mask: Event queue pointer mask
329 * @eventq_read_ptr: Event queue read pointer
330 * @last_eventq_read_ptr: Last event queue read pointer value.
331 * @magic_count: Event queue test event count
332 * @irq_count: Number of IRQs since last adaptive moderation decision
333 * @irq_mod_score: IRQ moderation score
334 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
335 * and diagnostic counters
336 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
338 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
339 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
340 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
341 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
342 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
343 * @n_rx_overlength: Count of RX_OVERLENGTH errors
344 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
345 * @rx_queue: RX queue for this channel
346 * @tx_queue: TX queues for this channel
353 unsigned int irq_moderation
;
354 struct net_device
*napi_dev
;
355 struct napi_struct napi_str
;
357 struct efx_special_buffer eventq
;
358 unsigned int eventq_mask
;
359 unsigned int eventq_read_ptr
;
360 unsigned int last_eventq_read_ptr
;
361 unsigned int magic_count
;
363 unsigned int irq_count
;
364 unsigned int irq_mod_score
;
367 int rx_alloc_push_pages
;
369 unsigned n_rx_tobe_disc
;
370 unsigned n_rx_ip_hdr_chksum_err
;
371 unsigned n_rx_tcp_udp_chksum_err
;
372 unsigned n_rx_mcast_mismatch
;
373 unsigned n_rx_frm_trunc
;
374 unsigned n_rx_overlength
;
375 unsigned n_skbuff_leaks
;
377 /* Used to pipeline received packets in order to optimise memory
378 * access with prefetches.
380 struct efx_rx_buffer
*rx_pkt
;
383 struct efx_rx_queue rx_queue
;
384 struct efx_tx_queue tx_queue
[EFX_TXQ_TYPES
];
393 #define STRING_TABLE_LOOKUP(val, member) \
394 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
396 extern const char *efx_loopback_mode_names
[];
397 extern const unsigned int efx_loopback_mode_max
;
398 #define LOOPBACK_MODE(efx) \
399 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
401 extern const char *efx_reset_type_names
[];
402 extern const unsigned int efx_reset_type_max
;
403 #define RESET_TYPE(type) \
404 STRING_TABLE_LOOKUP(type, efx_reset_type)
407 /* Be careful if altering to correct macro below */
408 EFX_INT_MODE_MSIX
= 0,
409 EFX_INT_MODE_MSI
= 1,
410 EFX_INT_MODE_LEGACY
= 2,
411 EFX_INT_MODE_MAX
/* Insert any new items before this */
413 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
424 * Alignment of page-allocated RX buffers
426 * Controls the number of bytes inserted at the start of an RX buffer.
427 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
428 * of the skb->head for hardware DMA].
430 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
431 #define EFX_PAGE_IP_ALIGN 0
433 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
437 * Alignment of the skb->head which wraps a page-allocated RX buffer
439 * The skb allocated to wrap an rx_buffer can have this alignment. Since
440 * the data is memcpy'd from the rx_buf, it does not need to be equal to
443 #define EFX_PAGE_SKB_ALIGN 2
445 /* Forward declaration */
448 /* Pseudo bit-mask flow control field */
450 EFX_FC_RX
= FLOW_CTRL_RX
,
451 EFX_FC_TX
= FLOW_CTRL_TX
,
456 * struct efx_link_state - Current state of the link
458 * @fd: Link is full-duplex
459 * @fc: Actual flow control flags
460 * @speed: Link speed (Mbps)
462 struct efx_link_state
{
469 static inline bool efx_link_state_equal(const struct efx_link_state
*left
,
470 const struct efx_link_state
*right
)
472 return left
->up
== right
->up
&& left
->fd
== right
->fd
&&
473 left
->fc
== right
->fc
&& left
->speed
== right
->speed
;
477 * struct efx_mac_operations - Efx MAC operations table
478 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
479 * @update_stats: Update statistics
480 * @check_fault: Check fault state. True if fault present.
482 struct efx_mac_operations
{
483 int (*reconfigure
) (struct efx_nic
*efx
);
484 void (*update_stats
) (struct efx_nic
*efx
);
485 bool (*check_fault
)(struct efx_nic
*efx
);
489 * struct efx_phy_operations - Efx PHY operations table
490 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
491 * efx->loopback_modes.
492 * @init: Initialise PHY
493 * @fini: Shut down PHY
494 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
495 * @poll: Update @link_state and report whether it changed.
496 * Serialised by the mac_lock.
497 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
498 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
499 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
500 * (only needed where AN bit is set in mmds)
501 * @test_alive: Test that PHY is 'alive' (online)
502 * @test_name: Get the name of a PHY-specific test/result
503 * @run_tests: Run tests and record results as appropriate (offline).
504 * Flags are the ethtool tests flags.
506 struct efx_phy_operations
{
507 int (*probe
) (struct efx_nic
*efx
);
508 int (*init
) (struct efx_nic
*efx
);
509 void (*fini
) (struct efx_nic
*efx
);
510 void (*remove
) (struct efx_nic
*efx
);
511 int (*reconfigure
) (struct efx_nic
*efx
);
512 bool (*poll
) (struct efx_nic
*efx
);
513 void (*get_settings
) (struct efx_nic
*efx
,
514 struct ethtool_cmd
*ecmd
);
515 int (*set_settings
) (struct efx_nic
*efx
,
516 struct ethtool_cmd
*ecmd
);
517 void (*set_npage_adv
) (struct efx_nic
*efx
, u32
);
518 int (*test_alive
) (struct efx_nic
*efx
);
519 const char *(*test_name
) (struct efx_nic
*efx
, unsigned int index
);
520 int (*run_tests
) (struct efx_nic
*efx
, int *results
, unsigned flags
);
524 * @enum efx_phy_mode - PHY operating mode flags
525 * @PHY_MODE_NORMAL: on and should pass traffic
526 * @PHY_MODE_TX_DISABLED: on with TX disabled
527 * @PHY_MODE_LOW_POWER: set to low power through MDIO
528 * @PHY_MODE_OFF: switched off through external control
529 * @PHY_MODE_SPECIAL: on but will not pass traffic
533 PHY_MODE_TX_DISABLED
= 1,
534 PHY_MODE_LOW_POWER
= 2,
536 PHY_MODE_SPECIAL
= 8,
539 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode
)
541 return !!(mode
& ~PHY_MODE_TX_DISABLED
);
545 * Efx extended statistics
547 * Not all statistics are provided by all supported MACs. The purpose
548 * is this structure is to contain the raw statistics provided by each
551 struct efx_mac_stats
{
555 unsigned long tx_packets
;
556 unsigned long tx_bad
;
557 unsigned long tx_pause
;
558 unsigned long tx_control
;
559 unsigned long tx_unicast
;
560 unsigned long tx_multicast
;
561 unsigned long tx_broadcast
;
562 unsigned long tx_lt64
;
564 unsigned long tx_65_to_127
;
565 unsigned long tx_128_to_255
;
566 unsigned long tx_256_to_511
;
567 unsigned long tx_512_to_1023
;
568 unsigned long tx_1024_to_15xx
;
569 unsigned long tx_15xx_to_jumbo
;
570 unsigned long tx_gtjumbo
;
571 unsigned long tx_collision
;
572 unsigned long tx_single_collision
;
573 unsigned long tx_multiple_collision
;
574 unsigned long tx_excessive_collision
;
575 unsigned long tx_deferred
;
576 unsigned long tx_late_collision
;
577 unsigned long tx_excessive_deferred
;
578 unsigned long tx_non_tcpudp
;
579 unsigned long tx_mac_src_error
;
580 unsigned long tx_ip_src_error
;
584 unsigned long rx_packets
;
585 unsigned long rx_good
;
586 unsigned long rx_bad
;
587 unsigned long rx_pause
;
588 unsigned long rx_control
;
589 unsigned long rx_unicast
;
590 unsigned long rx_multicast
;
591 unsigned long rx_broadcast
;
592 unsigned long rx_lt64
;
594 unsigned long rx_65_to_127
;
595 unsigned long rx_128_to_255
;
596 unsigned long rx_256_to_511
;
597 unsigned long rx_512_to_1023
;
598 unsigned long rx_1024_to_15xx
;
599 unsigned long rx_15xx_to_jumbo
;
600 unsigned long rx_gtjumbo
;
601 unsigned long rx_bad_lt64
;
602 unsigned long rx_bad_64_to_15xx
;
603 unsigned long rx_bad_15xx_to_jumbo
;
604 unsigned long rx_bad_gtjumbo
;
605 unsigned long rx_overflow
;
606 unsigned long rx_missed
;
607 unsigned long rx_false_carrier
;
608 unsigned long rx_symbol_error
;
609 unsigned long rx_align_error
;
610 unsigned long rx_length_error
;
611 unsigned long rx_internal_error
;
612 unsigned long rx_good_lt64
;
615 /* Number of bits used in a multicast filter hash address */
616 #define EFX_MCAST_HASH_BITS 8
618 /* Number of (single-bit) entries in a multicast filter hash */
619 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
621 /* An Efx multicast filter hash */
622 union efx_multicast_hash
{
623 u8 byte
[EFX_MCAST_HASH_ENTRIES
/ 8];
624 efx_oword_t oword
[EFX_MCAST_HASH_ENTRIES
/ sizeof(efx_oword_t
) / 8];
627 struct efx_filter_state
;
630 * struct efx_nic - an Efx NIC
631 * @name: Device name (net device name or bus id before net device registered)
632 * @pci_dev: The PCI device
633 * @type: Controller type attributes
634 * @legacy_irq: IRQ number
635 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)?
636 * @workqueue: Workqueue for port reconfigures and the HW monitor.
637 * Work items do not hold and must not acquire RTNL.
638 * @workqueue_name: Name of workqueue
639 * @reset_work: Scheduled reset workitem
640 * @membase_phys: Memory BAR value as physical address
641 * @membase: Memory BAR value
642 * @interrupt_mode: Interrupt mode
643 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
644 * @irq_rx_moderation: IRQ moderation time for RX event queues
645 * @msg_enable: Log message enable flags
646 * @state: Device state flag. Serialised by the rtnl_lock.
647 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
648 * @tx_queue: TX DMA queues
649 * @rx_queue: RX DMA queues
651 * @channel_name: Names for channels and their IRQs
652 * @rxq_entries: Size of receive queues requested by user.
653 * @txq_entries: Size of transmit queues requested by user.
654 * @next_buffer_table: First available buffer table id
655 * @n_channels: Number of channels in use
656 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
657 * @n_tx_channels: Number of channels used for TX
658 * @rx_buffer_len: RX buffer length
659 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
660 * @rx_hash_key: Toeplitz hash key for RSS
661 * @rx_indir_table: Indirection table for RSS
662 * @int_error_count: Number of internal errors seen recently
663 * @int_error_expire: Time at which error count will be expired
664 * @irq_status: Interrupt status buffer
665 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
666 * @fatal_irq_level: IRQ level (bit number) used for serious errors
667 * @mtd_list: List of MTDs attached to the NIC
668 * @nic_data: Hardware dependant state
669 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
670 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
671 * @port_enabled: Port enabled indicator.
672 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
673 * efx_mac_work() with kernel interfaces. Safe to read under any
674 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
675 * be held to modify it.
676 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
677 * @port_initialized: Port initialized?
678 * @net_dev: Operating system network device. Consider holding the rtnl lock
679 * @rx_checksum_enabled: RX checksumming enabled
680 * @stats_buffer: DMA buffer for statistics
681 * @mac_op: MAC interface
682 * @phy_type: PHY type
683 * @phy_op: PHY interface
684 * @phy_data: PHY private data (including PHY-specific stats)
685 * @mdio: PHY MDIO interface
686 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
687 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
688 * @link_advertising: Autonegotiation advertising flags
689 * @link_state: Current state of the link
690 * @n_link_state_changes: Number of times the link has changed state
691 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
692 * @multicast_hash: Multicast hash table
693 * @wanted_fc: Wanted flow control flags
694 * @mac_work: Work item for changing MAC promiscuity and multicast hash
695 * @loopback_mode: Loopback status
696 * @loopback_modes: Supported loopback mode bitmask
697 * @loopback_selftest: Offline self-test private state
698 * @monitor_work: Hardware monitor workitem
699 * @biu_lock: BIU (bus interface unit) lock
700 * @last_irq_cpu: Last CPU to handle interrupt.
701 * This register is written with the SMP processor ID whenever an
702 * interrupt is handled. It is used by efx_nic_test_interrupt()
703 * to verify that an interrupt has occurred.
704 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
705 * @mac_stats: MAC statistics. These include all statistics the MACs
706 * can provide. Generic code converts these into a standard
707 * &struct net_device_stats.
708 * @stats_lock: Statistics update lock. Serialises statistics fetches
710 * This is stored in the private area of the &struct net_device.
713 /* The following fields should be written very rarely */
716 struct pci_dev
*pci_dev
;
717 const struct efx_nic_type
*type
;
719 bool legacy_irq_enabled
;
720 struct workqueue_struct
*workqueue
;
721 char workqueue_name
[16];
722 struct work_struct reset_work
;
723 resource_size_t membase_phys
;
724 void __iomem
*membase
;
726 enum efx_int_mode interrupt_mode
;
727 bool irq_rx_adaptive
;
728 unsigned int irq_rx_moderation
;
731 enum nic_state state
;
732 enum reset_type reset_pending
;
734 struct efx_channel
*channel
[EFX_MAX_CHANNELS
];
735 char channel_name
[EFX_MAX_CHANNELS
][IFNAMSIZ
+ 6];
737 unsigned rxq_entries
;
738 unsigned txq_entries
;
739 unsigned next_buffer_table
;
741 unsigned n_rx_channels
;
742 unsigned tx_channel_offset
;
743 unsigned n_tx_channels
;
744 unsigned int rx_buffer_len
;
745 unsigned int rx_buffer_order
;
747 u32 rx_indir_table
[128];
749 unsigned int_error_count
;
750 unsigned long int_error_expire
;
752 struct efx_buffer irq_status
;
753 unsigned irq_zero_count
;
754 unsigned fatal_irq_level
;
756 #ifdef CONFIG_SFC_MTD
757 struct list_head mtd_list
;
762 struct mutex mac_lock
;
763 struct work_struct mac_work
;
767 bool port_initialized
;
768 struct net_device
*net_dev
;
769 bool rx_checksum_enabled
;
771 struct efx_buffer stats_buffer
;
773 struct efx_mac_operations
*mac_op
;
775 unsigned int phy_type
;
776 struct efx_phy_operations
*phy_op
;
778 struct mdio_if_info mdio
;
779 unsigned int mdio_bus
;
780 enum efx_phy_mode phy_mode
;
782 u32 link_advertising
;
783 struct efx_link_state link_state
;
784 unsigned int n_link_state_changes
;
787 union efx_multicast_hash multicast_hash
;
788 enum efx_fc_type wanted_fc
;
791 enum efx_loopback_mode loopback_mode
;
794 void *loopback_selftest
;
796 struct efx_filter_state
*filter_state
;
798 /* The following fields may be written more often */
800 struct delayed_work monitor_work ____cacheline_aligned_in_smp
;
802 volatile signed int last_irq_cpu
;
803 unsigned n_rx_nodesc_drop_cnt
;
804 struct efx_mac_stats mac_stats
;
805 spinlock_t stats_lock
;
808 static inline int efx_dev_registered(struct efx_nic
*efx
)
810 return efx
->net_dev
->reg_state
== NETREG_REGISTERED
;
813 /* Net device name, for inclusion in log messages if it has been registered.
814 * Use efx->name not efx->net_dev->name so that races with (un)registration
817 static inline const char *efx_dev_name(struct efx_nic
*efx
)
819 return efx_dev_registered(efx
) ? efx
->name
: "";
822 static inline unsigned int efx_port_num(struct efx_nic
*efx
)
824 return efx
->net_dev
->dev_id
;
828 * struct efx_nic_type - Efx device type definition
829 * @probe: Probe the controller
830 * @remove: Free resources allocated by probe()
831 * @init: Initialise the controller
832 * @fini: Shut down the controller
833 * @monitor: Periodic function for polling link state and hardware monitor
834 * @reset: Reset the controller hardware and possibly the PHY. This will
835 * be called while the controller is uninitialised.
836 * @probe_port: Probe the MAC and PHY
837 * @remove_port: Free resources allocated by probe_port()
838 * @handle_global_event: Handle a "global" event (may be %NULL)
839 * @prepare_flush: Prepare the hardware for flushing the DMA queues
840 * @update_stats: Update statistics not provided by event handling
841 * @start_stats: Start the regular fetching of statistics
842 * @stop_stats: Stop the regular fetching of statistics
843 * @set_id_led: Set state of identifying LED or revert to automatic function
844 * @push_irq_moderation: Apply interrupt moderation value
845 * @push_multicast_hash: Apply multicast hash table
846 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
847 * @get_wol: Get WoL configuration from driver state
848 * @set_wol: Push WoL configuration to the NIC
849 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
850 * @test_registers: Test read/write functionality of control registers
851 * @test_nvram: Test validity of NVRAM contents
852 * @default_mac_ops: efx_mac_operations to set at startup
853 * @revision: Hardware architecture revision
854 * @mem_map_size: Memory BAR mapped size
855 * @txd_ptr_tbl_base: TX descriptor ring base address
856 * @rxd_ptr_tbl_base: RX descriptor ring base address
857 * @buf_tbl_base: Buffer table base address
858 * @evq_ptr_tbl_base: Event queue pointer table base address
859 * @evq_rptr_tbl_base: Event queue read-pointer table base address
860 * @max_dma_mask: Maximum possible DMA mask
861 * @rx_buffer_hash_size: Size of hash at start of RX buffer
862 * @rx_buffer_padding: Size of padding at end of RX buffer
863 * @max_interrupt_mode: Highest capability interrupt mode supported
864 * from &enum efx_init_mode.
865 * @phys_addr_channels: Number of channels with physically addressed
867 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
868 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
869 * @offload_features: net_device feature flags for protocol offload
870 * features implemented in hardware
871 * @reset_world_flags: Flags for additional components covered by
872 * reset method RESET_TYPE_WORLD
874 struct efx_nic_type
{
875 int (*probe
)(struct efx_nic
*efx
);
876 void (*remove
)(struct efx_nic
*efx
);
877 int (*init
)(struct efx_nic
*efx
);
878 void (*fini
)(struct efx_nic
*efx
);
879 void (*monitor
)(struct efx_nic
*efx
);
880 int (*reset
)(struct efx_nic
*efx
, enum reset_type method
);
881 int (*probe_port
)(struct efx_nic
*efx
);
882 void (*remove_port
)(struct efx_nic
*efx
);
883 bool (*handle_global_event
)(struct efx_channel
*channel
, efx_qword_t
*);
884 void (*prepare_flush
)(struct efx_nic
*efx
);
885 void (*update_stats
)(struct efx_nic
*efx
);
886 void (*start_stats
)(struct efx_nic
*efx
);
887 void (*stop_stats
)(struct efx_nic
*efx
);
888 void (*set_id_led
)(struct efx_nic
*efx
, enum efx_led_mode mode
);
889 void (*push_irq_moderation
)(struct efx_channel
*channel
);
890 void (*push_multicast_hash
)(struct efx_nic
*efx
);
891 int (*reconfigure_port
)(struct efx_nic
*efx
);
892 void (*get_wol
)(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
);
893 int (*set_wol
)(struct efx_nic
*efx
, u32 type
);
894 void (*resume_wol
)(struct efx_nic
*efx
);
895 int (*test_registers
)(struct efx_nic
*efx
);
896 int (*test_nvram
)(struct efx_nic
*efx
);
897 struct efx_mac_operations
*default_mac_ops
;
900 unsigned int mem_map_size
;
901 unsigned int txd_ptr_tbl_base
;
902 unsigned int rxd_ptr_tbl_base
;
903 unsigned int buf_tbl_base
;
904 unsigned int evq_ptr_tbl_base
;
905 unsigned int evq_rptr_tbl_base
;
907 unsigned int rx_buffer_hash_size
;
908 unsigned int rx_buffer_padding
;
909 unsigned int max_interrupt_mode
;
910 unsigned int phys_addr_channels
;
911 unsigned int tx_dc_base
;
912 unsigned int rx_dc_base
;
913 u32 offload_features
;
914 u32 reset_world_flags
;
917 /**************************************************************************
919 * Prototypes and inline functions
921 *************************************************************************/
923 static inline struct efx_channel
*
924 efx_get_channel(struct efx_nic
*efx
, unsigned index
)
926 EFX_BUG_ON_PARANOID(index
>= efx
->n_channels
);
927 return efx
->channel
[index
];
930 /* Iterate over all used channels */
931 #define efx_for_each_channel(_channel, _efx) \
932 for (_channel = (_efx)->channel[0]; \
934 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
935 (_efx)->channel[_channel->channel + 1] : NULL)
937 static inline struct efx_tx_queue
*
938 efx_get_tx_queue(struct efx_nic
*efx
, unsigned index
, unsigned type
)
940 EFX_BUG_ON_PARANOID(index
>= efx
->n_tx_channels
||
941 type
>= EFX_TXQ_TYPES
);
942 return &efx
->channel
[efx
->tx_channel_offset
+ index
]->tx_queue
[type
];
945 static inline bool efx_channel_has_tx_queues(struct efx_channel
*channel
)
947 return channel
->channel
- channel
->efx
->tx_channel_offset
<
948 channel
->efx
->n_tx_channels
;
951 static inline struct efx_tx_queue
*
952 efx_channel_get_tx_queue(struct efx_channel
*channel
, unsigned type
)
954 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel
) ||
955 type
>= EFX_TXQ_TYPES
);
956 return &channel
->tx_queue
[type
];
959 static inline bool efx_tx_queue_used(struct efx_tx_queue
*tx_queue
)
961 return !(tx_queue
->efx
->net_dev
->num_tc
< 2 &&
962 tx_queue
->queue
& EFX_TXQ_TYPE_HIGHPRI
);
965 /* Iterate over all TX queues belonging to a channel */
966 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
967 if (!efx_channel_has_tx_queues(_channel)) \
970 for (_tx_queue = (_channel)->tx_queue; \
971 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
972 efx_tx_queue_used(_tx_queue); \
975 /* Iterate over all possible TX queues belonging to a channel */
976 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
977 for (_tx_queue = (_channel)->tx_queue; \
978 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
981 static inline struct efx_rx_queue
*
982 efx_get_rx_queue(struct efx_nic
*efx
, unsigned index
)
984 EFX_BUG_ON_PARANOID(index
>= efx
->n_rx_channels
);
985 return &efx
->channel
[index
]->rx_queue
;
988 static inline bool efx_channel_has_rx_queue(struct efx_channel
*channel
)
990 return channel
->channel
< channel
->efx
->n_rx_channels
;
993 static inline struct efx_rx_queue
*
994 efx_channel_get_rx_queue(struct efx_channel
*channel
)
996 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel
));
997 return &channel
->rx_queue
;
1000 /* Iterate over all RX queues belonging to a channel */
1001 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1002 if (!efx_channel_has_rx_queue(_channel)) \
1005 for (_rx_queue = &(_channel)->rx_queue; \
1009 static inline struct efx_channel
*
1010 efx_rx_queue_channel(struct efx_rx_queue
*rx_queue
)
1012 return container_of(rx_queue
, struct efx_channel
, rx_queue
);
1015 static inline int efx_rx_queue_index(struct efx_rx_queue
*rx_queue
)
1017 return efx_rx_queue_channel(rx_queue
)->channel
;
1020 /* Returns a pointer to the specified receive buffer in the RX
1023 static inline struct efx_rx_buffer
*efx_rx_buffer(struct efx_rx_queue
*rx_queue
,
1026 return &rx_queue
->buffer
[index
];
1029 /* Set bit in a little-endian bitfield */
1030 static inline void set_bit_le(unsigned nr
, unsigned char *addr
)
1032 addr
[nr
/ 8] |= (1 << (nr
% 8));
1035 /* Clear bit in a little-endian bitfield */
1036 static inline void clear_bit_le(unsigned nr
, unsigned char *addr
)
1038 addr
[nr
/ 8] &= ~(1 << (nr
% 8));
1043 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1045 * This calculates the maximum frame length that will be used for a
1046 * given MTU. The frame length will be equal to the MTU plus a
1047 * constant amount of header space and padding. This is the quantity
1048 * that the net driver will program into the MAC as the maximum frame
1051 * The 10G MAC requires 8-byte alignment on the frame
1052 * length, so we round up to the nearest 8.
1054 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1055 * XGMII cycle). If the frame length reaches the maximum value in the
1056 * same cycle, the XMAC can miss the IPG altogether. We work around
1057 * this by adding a further 16 bytes.
1059 #define EFX_MAX_FRAME_LEN(mtu) \
1060 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1063 #endif /* EFX_NET_DRIVER_H */