1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #if defined(EFX_ENABLE_DEBUG) && !defined(DEBUG)
20 #include <linux/version.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_vlan.h>
25 #include <linux/timer.h>
26 #include <linux/mdio.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/device.h>
30 #include <linux/highmem.h>
31 #include <linux/workqueue.h>
32 #include <linux/i2c.h>
37 /**************************************************************************
41 **************************************************************************/
43 #define EFX_DRIVER_VERSION "3.0"
45 #ifdef EFX_ENABLE_DEBUG
46 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
47 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
49 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
50 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
53 /**************************************************************************
57 **************************************************************************/
59 #define EFX_MAX_CHANNELS 32
60 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62 /* Checksum generation is a per-queue option in hardware, so each
63 * queue visible to the networking core is backed by two hardware TX
65 #define EFX_MAX_CORE_TX_QUEUES EFX_MAX_CHANNELS
66 #define EFX_TXQ_TYPE_OFFLOAD 1
67 #define EFX_TXQ_TYPES 2
68 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES)
71 * struct efx_special_buffer - An Efx special buffer
72 * @addr: CPU base address of the buffer
73 * @dma_addr: DMA base address of the buffer
74 * @len: Buffer length, in bytes
75 * @index: Buffer index within controller;s buffer table
76 * @entries: Number of buffer table entries
78 * Special buffers are used for the event queues and the TX and RX
79 * descriptor queues for each channel. They are *not* used for the
80 * actual transmit and receive buffers.
82 struct efx_special_buffer
{
90 enum efx_flush_state
{
98 * struct efx_tx_buffer - An Efx TX buffer
99 * @skb: The associated socket buffer.
100 * Set only on the final fragment of a packet; %NULL for all other
101 * fragments. When this fragment completes, then we can free this
103 * @tsoh: The associated TSO header structure, or %NULL if this
104 * buffer is not a TSO header.
105 * @dma_addr: DMA address of the fragment.
106 * @len: Length of this fragment.
107 * This field is zero when the queue slot is empty.
108 * @continuation: True if this fragment is not the end of a packet.
109 * @unmap_single: True if pci_unmap_single should be used.
110 * @unmap_len: Length of this fragment to unmap
112 struct efx_tx_buffer
{
113 const struct sk_buff
*skb
;
114 struct efx_tso_header
*tsoh
;
119 unsigned short unmap_len
;
123 * struct efx_tx_queue - An Efx TX queue
125 * This is a ring buffer of TX fragments.
126 * Since the TX completion path always executes on the same
127 * CPU and the xmit path can operate on different CPUs,
128 * performance is increased by ensuring that the completion
129 * path and the xmit path operate on different cache lines.
130 * This is particularly important if the xmit path is always
131 * executing on one CPU which is different from the completion
132 * path. There is also a cache line for members which are
133 * read but not written on the fast path.
135 * @efx: The associated Efx NIC
136 * @queue: DMA queue number
137 * @channel: The associated channel
138 * @buffer: The software buffer ring
139 * @txd: The hardware descriptor ring
140 * @ptr_mask: The size of the ring minus 1.
141 * @flushed: Used when handling queue flushing
142 * @read_count: Current read pointer.
143 * This is the number of buffers that have been removed from both rings.
144 * @stopped: Stopped count.
145 * Set if this TX queue is currently stopping its port.
146 * @insert_count: Current insert pointer
147 * This is the number of buffers that have been added to the
149 * @write_count: Current write pointer
150 * This is the number of buffers that have been added to the
152 * @old_read_count: The value of read_count when last checked.
153 * This is here for performance reasons. The xmit path will
154 * only get the up-to-date value of read_count if this
155 * variable indicates that the queue is full. This is to
156 * avoid cache-line ping-pong between the xmit path and the
158 * @tso_headers_free: A list of TSO headers allocated for this TX queue
159 * that are not in use, and so available for new TSO sends. The list
160 * is protected by the TX queue lock.
161 * @tso_bursts: Number of times TSO xmit invoked by kernel
162 * @tso_long_headers: Number of packets with headers too long for standard
164 * @tso_packets: Number of packets via the TSO xmit path
166 struct efx_tx_queue
{
167 /* Members which don't change on the fast path */
168 struct efx_nic
*efx ____cacheline_aligned_in_smp
;
170 struct efx_channel
*channel
;
172 struct efx_tx_buffer
*buffer
;
173 struct efx_special_buffer txd
;
174 unsigned int ptr_mask
;
175 enum efx_flush_state flushed
;
177 /* Members used mainly on the completion path */
178 unsigned int read_count ____cacheline_aligned_in_smp
;
181 /* Members used only on the xmit path */
182 unsigned int insert_count ____cacheline_aligned_in_smp
;
183 unsigned int write_count
;
184 unsigned int old_read_count
;
185 struct efx_tso_header
*tso_headers_free
;
186 unsigned int tso_bursts
;
187 unsigned int tso_long_headers
;
188 unsigned int tso_packets
;
192 * struct efx_rx_buffer - An Efx RX data buffer
193 * @dma_addr: DMA base address of the buffer
194 * @skb: The associated socket buffer, if any.
195 * If both this and page are %NULL, the buffer slot is currently free.
196 * @page: The associated page buffer, if any.
197 * If both this and skb are %NULL, the buffer slot is currently free.
198 * @data: Pointer to ethernet header
199 * @len: Buffer length, in bytes.
201 struct efx_rx_buffer
{
210 * struct efx_rx_page_state - Page-based rx buffer state
212 * Inserted at the start of every page allocated for receive buffers.
213 * Used to facilitate sharing dma mappings between recycled rx buffers
214 * and those passed up to the kernel.
216 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
217 * When refcnt falls to zero, the page is unmapped for dma
218 * @dma_addr: The dma address of this page.
220 struct efx_rx_page_state
{
224 unsigned int __pad
[0] ____cacheline_aligned
;
228 * struct efx_rx_queue - An Efx RX queue
229 * @efx: The associated Efx NIC
230 * @buffer: The software buffer ring
231 * @rxd: The hardware descriptor ring
232 * @ptr_mask: The size of the ring minus 1.
233 * @added_count: Number of buffers added to the receive queue.
234 * @notified_count: Number of buffers given to NIC (<= @added_count).
235 * @removed_count: Number of buffers removed from the receive queue.
236 * @max_fill: RX descriptor maximum fill level (<= ring size)
237 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
239 * @fast_fill_limit: The level to which a fast fill will fill
240 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
241 * @min_fill: RX descriptor minimum non-zero fill level.
242 * This records the minimum fill level observed when a ring
243 * refill was triggered.
244 * @alloc_page_count: RX allocation strategy counter.
245 * @alloc_skb_count: RX allocation strategy counter.
246 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
247 * @flushed: Use when handling queue flushing
249 struct efx_rx_queue
{
251 struct efx_rx_buffer
*buffer
;
252 struct efx_special_buffer rxd
;
253 unsigned int ptr_mask
;
258 unsigned int max_fill
;
259 unsigned int fast_fill_trigger
;
260 unsigned int fast_fill_limit
;
261 unsigned int min_fill
;
262 unsigned int min_overfill
;
263 unsigned int alloc_page_count
;
264 unsigned int alloc_skb_count
;
265 struct timer_list slow_fill
;
266 unsigned int slow_fill_count
;
268 enum efx_flush_state flushed
;
272 * struct efx_buffer - An Efx general-purpose buffer
273 * @addr: host base address of the buffer
274 * @dma_addr: DMA base address of the buffer
275 * @len: Buffer length, in bytes
277 * The NIC uses these buffers for its interrupt status registers and
287 enum efx_rx_alloc_method
{
288 RX_ALLOC_METHOD_AUTO
= 0,
289 RX_ALLOC_METHOD_SKB
= 1,
290 RX_ALLOC_METHOD_PAGE
= 2,
294 * struct efx_channel - An Efx channel
296 * A channel comprises an event queue, at least one TX queue, at least
297 * one RX queue, and an associated tasklet for processing the event
300 * @efx: Associated Efx NIC
301 * @channel: Channel instance number
302 * @name: Name for channel and IRQ
303 * @enabled: Channel enabled indicator
304 * @irq: IRQ number (MSI and MSI-X only)
305 * @irq_moderation: IRQ moderation value (in hardware ticks)
306 * @napi_dev: Net device used with NAPI
307 * @napi_str: NAPI control structure
308 * @reset_work: Scheduled reset work thread
309 * @work_pending: Is work pending via NAPI?
310 * @eventq: Event queue buffer
311 * @eventq_mask: Event queue pointer mask
312 * @eventq_read_ptr: Event queue read pointer
313 * @last_eventq_read_ptr: Last event queue read pointer value.
314 * @magic_count: Event queue test event count
315 * @irq_count: Number of IRQs since last adaptive moderation decision
316 * @irq_mod_score: IRQ moderation score
317 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
318 * and diagnostic counters
319 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
321 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
322 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
323 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
324 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
325 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
326 * @n_rx_overlength: Count of RX_OVERLENGTH errors
327 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
328 * @rx_queue: RX queue for this channel
329 * @tx_stop_count: Core TX queue stop count
330 * @tx_stop_lock: Core TX queue stop lock
331 * @tx_queue: TX queues for this channel
336 char name
[IFNAMSIZ
+ 6];
339 unsigned int irq_moderation
;
340 struct net_device
*napi_dev
;
341 struct napi_struct napi_str
;
343 struct efx_special_buffer eventq
;
344 unsigned int eventq_mask
;
345 unsigned int eventq_read_ptr
;
346 unsigned int last_eventq_read_ptr
;
347 unsigned int magic_count
;
349 unsigned int irq_count
;
350 unsigned int irq_mod_score
;
353 int rx_alloc_push_pages
;
355 unsigned n_rx_tobe_disc
;
356 unsigned n_rx_ip_hdr_chksum_err
;
357 unsigned n_rx_tcp_udp_chksum_err
;
358 unsigned n_rx_mcast_mismatch
;
359 unsigned n_rx_frm_trunc
;
360 unsigned n_rx_overlength
;
361 unsigned n_skbuff_leaks
;
363 /* Used to pipeline received packets in order to optimise memory
364 * access with prefetches.
366 struct efx_rx_buffer
*rx_pkt
;
369 struct efx_rx_queue rx_queue
;
371 atomic_t tx_stop_count
;
372 spinlock_t tx_stop_lock
;
374 struct efx_tx_queue tx_queue
[2];
383 #define STRING_TABLE_LOOKUP(val, member) \
384 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
386 extern const char *efx_loopback_mode_names
[];
387 extern const unsigned int efx_loopback_mode_max
;
388 #define LOOPBACK_MODE(efx) \
389 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
391 extern const char *efx_interrupt_mode_names
[];
392 extern const unsigned int efx_interrupt_mode_max
;
393 #define INT_MODE(efx) \
394 STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode)
396 extern const char *efx_reset_type_names
[];
397 extern const unsigned int efx_reset_type_max
;
398 #define RESET_TYPE(type) \
399 STRING_TABLE_LOOKUP(type, efx_reset_type)
402 /* Be careful if altering to correct macro below */
403 EFX_INT_MODE_MSIX
= 0,
404 EFX_INT_MODE_MSI
= 1,
405 EFX_INT_MODE_LEGACY
= 2,
406 EFX_INT_MODE_MAX
/* Insert any new items before this */
408 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
410 #define EFX_IS10G(efx) ((efx)->link_state.speed == 10000)
421 * Alignment of page-allocated RX buffers
423 * Controls the number of bytes inserted at the start of an RX buffer.
424 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
425 * of the skb->head for hardware DMA].
427 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
428 #define EFX_PAGE_IP_ALIGN 0
430 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
434 * Alignment of the skb->head which wraps a page-allocated RX buffer
436 * The skb allocated to wrap an rx_buffer can have this alignment. Since
437 * the data is memcpy'd from the rx_buf, it does not need to be equal to
440 #define EFX_PAGE_SKB_ALIGN 2
442 /* Forward declaration */
445 /* Pseudo bit-mask flow control field */
447 EFX_FC_RX
= FLOW_CTRL_RX
,
448 EFX_FC_TX
= FLOW_CTRL_TX
,
453 * struct efx_link_state - Current state of the link
455 * @fd: Link is full-duplex
456 * @fc: Actual flow control flags
457 * @speed: Link speed (Mbps)
459 struct efx_link_state
{
466 static inline bool efx_link_state_equal(const struct efx_link_state
*left
,
467 const struct efx_link_state
*right
)
469 return left
->up
== right
->up
&& left
->fd
== right
->fd
&&
470 left
->fc
== right
->fc
&& left
->speed
== right
->speed
;
474 * struct efx_mac_operations - Efx MAC operations table
475 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
476 * @update_stats: Update statistics
477 * @check_fault: Check fault state. True if fault present.
479 struct efx_mac_operations
{
480 int (*reconfigure
) (struct efx_nic
*efx
);
481 void (*update_stats
) (struct efx_nic
*efx
);
482 bool (*check_fault
)(struct efx_nic
*efx
);
486 * struct efx_phy_operations - Efx PHY operations table
487 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
488 * efx->loopback_modes.
489 * @init: Initialise PHY
490 * @fini: Shut down PHY
491 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
492 * @poll: Update @link_state and report whether it changed.
493 * Serialised by the mac_lock.
494 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
495 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
496 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
497 * (only needed where AN bit is set in mmds)
498 * @test_alive: Test that PHY is 'alive' (online)
499 * @test_name: Get the name of a PHY-specific test/result
500 * @run_tests: Run tests and record results as appropriate (offline).
501 * Flags are the ethtool tests flags.
503 struct efx_phy_operations
{
504 int (*probe
) (struct efx_nic
*efx
);
505 int (*init
) (struct efx_nic
*efx
);
506 void (*fini
) (struct efx_nic
*efx
);
507 void (*remove
) (struct efx_nic
*efx
);
508 int (*reconfigure
) (struct efx_nic
*efx
);
509 bool (*poll
) (struct efx_nic
*efx
);
510 void (*get_settings
) (struct efx_nic
*efx
,
511 struct ethtool_cmd
*ecmd
);
512 int (*set_settings
) (struct efx_nic
*efx
,
513 struct ethtool_cmd
*ecmd
);
514 void (*set_npage_adv
) (struct efx_nic
*efx
, u32
);
515 int (*test_alive
) (struct efx_nic
*efx
);
516 const char *(*test_name
) (struct efx_nic
*efx
, unsigned int index
);
517 int (*run_tests
) (struct efx_nic
*efx
, int *results
, unsigned flags
);
521 * @enum efx_phy_mode - PHY operating mode flags
522 * @PHY_MODE_NORMAL: on and should pass traffic
523 * @PHY_MODE_TX_DISABLED: on with TX disabled
524 * @PHY_MODE_LOW_POWER: set to low power through MDIO
525 * @PHY_MODE_OFF: switched off through external control
526 * @PHY_MODE_SPECIAL: on but will not pass traffic
530 PHY_MODE_TX_DISABLED
= 1,
531 PHY_MODE_LOW_POWER
= 2,
533 PHY_MODE_SPECIAL
= 8,
536 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode
)
538 return !!(mode
& ~PHY_MODE_TX_DISABLED
);
542 * Efx extended statistics
544 * Not all statistics are provided by all supported MACs. The purpose
545 * is this structure is to contain the raw statistics provided by each
548 struct efx_mac_stats
{
552 unsigned long tx_packets
;
553 unsigned long tx_bad
;
554 unsigned long tx_pause
;
555 unsigned long tx_control
;
556 unsigned long tx_unicast
;
557 unsigned long tx_multicast
;
558 unsigned long tx_broadcast
;
559 unsigned long tx_lt64
;
561 unsigned long tx_65_to_127
;
562 unsigned long tx_128_to_255
;
563 unsigned long tx_256_to_511
;
564 unsigned long tx_512_to_1023
;
565 unsigned long tx_1024_to_15xx
;
566 unsigned long tx_15xx_to_jumbo
;
567 unsigned long tx_gtjumbo
;
568 unsigned long tx_collision
;
569 unsigned long tx_single_collision
;
570 unsigned long tx_multiple_collision
;
571 unsigned long tx_excessive_collision
;
572 unsigned long tx_deferred
;
573 unsigned long tx_late_collision
;
574 unsigned long tx_excessive_deferred
;
575 unsigned long tx_non_tcpudp
;
576 unsigned long tx_mac_src_error
;
577 unsigned long tx_ip_src_error
;
581 unsigned long rx_packets
;
582 unsigned long rx_good
;
583 unsigned long rx_bad
;
584 unsigned long rx_pause
;
585 unsigned long rx_control
;
586 unsigned long rx_unicast
;
587 unsigned long rx_multicast
;
588 unsigned long rx_broadcast
;
589 unsigned long rx_lt64
;
591 unsigned long rx_65_to_127
;
592 unsigned long rx_128_to_255
;
593 unsigned long rx_256_to_511
;
594 unsigned long rx_512_to_1023
;
595 unsigned long rx_1024_to_15xx
;
596 unsigned long rx_15xx_to_jumbo
;
597 unsigned long rx_gtjumbo
;
598 unsigned long rx_bad_lt64
;
599 unsigned long rx_bad_64_to_15xx
;
600 unsigned long rx_bad_15xx_to_jumbo
;
601 unsigned long rx_bad_gtjumbo
;
602 unsigned long rx_overflow
;
603 unsigned long rx_missed
;
604 unsigned long rx_false_carrier
;
605 unsigned long rx_symbol_error
;
606 unsigned long rx_align_error
;
607 unsigned long rx_length_error
;
608 unsigned long rx_internal_error
;
609 unsigned long rx_good_lt64
;
612 /* Number of bits used in a multicast filter hash address */
613 #define EFX_MCAST_HASH_BITS 8
615 /* Number of (single-bit) entries in a multicast filter hash */
616 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
618 /* An Efx multicast filter hash */
619 union efx_multicast_hash
{
620 u8 byte
[EFX_MCAST_HASH_ENTRIES
/ 8];
621 efx_oword_t oword
[EFX_MCAST_HASH_ENTRIES
/ sizeof(efx_oword_t
) / 8];
625 * struct efx_nic - an Efx NIC
626 * @name: Device name (net device name or bus id before net device registered)
627 * @pci_dev: The PCI device
628 * @type: Controller type attributes
629 * @legacy_irq: IRQ number
630 * @workqueue: Workqueue for port reconfigures and the HW monitor.
631 * Work items do not hold and must not acquire RTNL.
632 * @workqueue_name: Name of workqueue
633 * @reset_work: Scheduled reset workitem
634 * @monitor_work: Hardware monitor workitem
635 * @membase_phys: Memory BAR value as physical address
636 * @membase: Memory BAR value
637 * @biu_lock: BIU (bus interface unit) lock
638 * @interrupt_mode: Interrupt mode
639 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
640 * @irq_rx_moderation: IRQ moderation time for RX event queues
641 * @msg_enable: Log message enable flags
642 * @state: Device state flag. Serialised by the rtnl_lock.
643 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
644 * @tx_queue: TX DMA queues
645 * @rx_queue: RX DMA queues
647 * @rxq_entries: Size of receive queues requested by user.
648 * @txq_entries: Size of transmit queues requested by user.
649 * @next_buffer_table: First available buffer table id
650 * @n_channels: Number of channels in use
651 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
652 * @n_tx_channels: Number of channels used for TX
653 * @rx_buffer_len: RX buffer length
654 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
655 * @rx_indir_table: Indirection table for RSS
656 * @int_error_count: Number of internal errors seen recently
657 * @int_error_expire: Time at which error count will be expired
658 * @irq_status: Interrupt status buffer
659 * @last_irq_cpu: Last CPU to handle interrupt.
660 * This register is written with the SMP processor ID whenever an
661 * interrupt is handled. It is used by efx_nic_test_interrupt()
662 * to verify that an interrupt has occurred.
663 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
664 * @fatal_irq_level: IRQ level (bit number) used for serious errors
665 * @spi_flash: SPI flash device
666 * This field will be %NULL if no flash device is present (or for Siena).
667 * @spi_eeprom: SPI EEPROM device
668 * This field will be %NULL if no EEPROM device is present (or for Siena).
669 * @spi_lock: SPI bus lock
670 * @mtd_list: List of MTDs attached to the NIC
671 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
672 * @nic_data: Hardware dependant state
673 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
674 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
675 * @port_enabled: Port enabled indicator.
676 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
677 * efx_mac_work() with kernel interfaces. Safe to read under any
678 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
679 * be held to modify it.
680 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
681 * @port_initialized: Port initialized?
682 * @net_dev: Operating system network device. Consider holding the rtnl lock
683 * @rx_checksum_enabled: RX checksumming enabled
684 * @mac_stats: MAC statistics. These include all statistics the MACs
685 * can provide. Generic code converts these into a standard
686 * &struct net_device_stats.
687 * @stats_buffer: DMA buffer for statistics
688 * @stats_lock: Statistics update lock. Serialises statistics fetches
689 * @mac_op: MAC interface
690 * @mac_address: Permanent MAC address
691 * @phy_type: PHY type
692 * @mdio_lock: MDIO lock
693 * @phy_op: PHY interface
694 * @phy_data: PHY private data (including PHY-specific stats)
695 * @mdio: PHY MDIO interface
696 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
697 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
698 * @xmac_poll_required: XMAC link state needs polling
699 * @link_advertising: Autonegotiation advertising flags
700 * @link_state: Current state of the link
701 * @n_link_state_changes: Number of times the link has changed state
702 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
703 * @multicast_hash: Multicast hash table
704 * @wanted_fc: Wanted flow control flags
705 * @mac_work: Work item for changing MAC promiscuity and multicast hash
706 * @loopback_mode: Loopback status
707 * @loopback_modes: Supported loopback mode bitmask
708 * @loopback_selftest: Offline self-test private state
710 * This is stored in the private area of the &struct net_device.
714 struct pci_dev
*pci_dev
;
715 const struct efx_nic_type
*type
;
717 struct workqueue_struct
*workqueue
;
718 char workqueue_name
[16];
719 struct work_struct reset_work
;
720 struct delayed_work monitor_work
;
721 resource_size_t membase_phys
;
722 void __iomem
*membase
;
724 enum efx_int_mode interrupt_mode
;
725 bool irq_rx_adaptive
;
726 unsigned int irq_rx_moderation
;
729 enum nic_state state
;
730 enum reset_type reset_pending
;
732 struct efx_channel
*channel
[EFX_MAX_CHANNELS
];
734 unsigned rxq_entries
;
735 unsigned txq_entries
;
736 unsigned next_buffer_table
;
738 unsigned n_rx_channels
;
739 unsigned n_tx_channels
;
740 unsigned int rx_buffer_len
;
741 unsigned int rx_buffer_order
;
743 u32 rx_indir_table
[128];
745 unsigned int_error_count
;
746 unsigned long int_error_expire
;
748 struct efx_buffer irq_status
;
749 volatile signed int last_irq_cpu
;
750 unsigned irq_zero_count
;
751 unsigned fatal_irq_level
;
753 struct efx_spi_device
*spi_flash
;
754 struct efx_spi_device
*spi_eeprom
;
755 struct mutex spi_lock
;
756 #ifdef CONFIG_SFC_MTD
757 struct list_head mtd_list
;
760 unsigned n_rx_nodesc_drop_cnt
;
764 struct mutex mac_lock
;
765 struct work_struct mac_work
;
769 bool port_initialized
;
770 struct net_device
*net_dev
;
771 bool rx_checksum_enabled
;
773 struct efx_mac_stats mac_stats
;
774 struct efx_buffer stats_buffer
;
775 spinlock_t stats_lock
;
777 struct efx_mac_operations
*mac_op
;
778 unsigned char mac_address
[ETH_ALEN
];
780 unsigned int phy_type
;
781 struct mutex mdio_lock
;
782 struct efx_phy_operations
*phy_op
;
784 struct mdio_if_info mdio
;
785 unsigned int mdio_bus
;
786 enum efx_phy_mode phy_mode
;
788 bool xmac_poll_required
;
789 u32 link_advertising
;
790 struct efx_link_state link_state
;
791 unsigned int n_link_state_changes
;
794 union efx_multicast_hash multicast_hash
;
795 enum efx_fc_type wanted_fc
;
798 enum efx_loopback_mode loopback_mode
;
801 void *loopback_selftest
;
804 static inline int efx_dev_registered(struct efx_nic
*efx
)
806 return efx
->net_dev
->reg_state
== NETREG_REGISTERED
;
809 /* Net device name, for inclusion in log messages if it has been registered.
810 * Use efx->name not efx->net_dev->name so that races with (un)registration
813 static inline const char *efx_dev_name(struct efx_nic
*efx
)
815 return efx_dev_registered(efx
) ? efx
->name
: "";
818 static inline unsigned int efx_port_num(struct efx_nic
*efx
)
820 return efx
->net_dev
->dev_id
;
824 * struct efx_nic_type - Efx device type definition
825 * @probe: Probe the controller
826 * @remove: Free resources allocated by probe()
827 * @init: Initialise the controller
828 * @fini: Shut down the controller
829 * @monitor: Periodic function for polling link state and hardware monitor
830 * @reset: Reset the controller hardware and possibly the PHY. This will
831 * be called while the controller is uninitialised.
832 * @probe_port: Probe the MAC and PHY
833 * @remove_port: Free resources allocated by probe_port()
834 * @prepare_flush: Prepare the hardware for flushing the DMA queues
835 * @update_stats: Update statistics not provided by event handling
836 * @start_stats: Start the regular fetching of statistics
837 * @stop_stats: Stop the regular fetching of statistics
838 * @set_id_led: Set state of identifying LED or revert to automatic function
839 * @push_irq_moderation: Apply interrupt moderation value
840 * @push_multicast_hash: Apply multicast hash table
841 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
842 * @get_wol: Get WoL configuration from driver state
843 * @set_wol: Push WoL configuration to the NIC
844 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
845 * @test_registers: Test read/write functionality of control registers
846 * @test_nvram: Test validity of NVRAM contents
847 * @default_mac_ops: efx_mac_operations to set at startup
848 * @revision: Hardware architecture revision
849 * @mem_map_size: Memory BAR mapped size
850 * @txd_ptr_tbl_base: TX descriptor ring base address
851 * @rxd_ptr_tbl_base: RX descriptor ring base address
852 * @buf_tbl_base: Buffer table base address
853 * @evq_ptr_tbl_base: Event queue pointer table base address
854 * @evq_rptr_tbl_base: Event queue read-pointer table base address
855 * @max_dma_mask: Maximum possible DMA mask
856 * @rx_buffer_hash_size: Size of hash at start of RX buffer
857 * @rx_buffer_padding: Size of padding at end of RX buffer
858 * @max_interrupt_mode: Highest capability interrupt mode supported
859 * from &enum efx_init_mode.
860 * @phys_addr_channels: Number of channels with physically addressed
862 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
863 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
864 * @offload_features: net_device feature flags for protocol offload
865 * features implemented in hardware
866 * @reset_world_flags: Flags for additional components covered by
867 * reset method RESET_TYPE_WORLD
869 struct efx_nic_type
{
870 int (*probe
)(struct efx_nic
*efx
);
871 void (*remove
)(struct efx_nic
*efx
);
872 int (*init
)(struct efx_nic
*efx
);
873 void (*fini
)(struct efx_nic
*efx
);
874 void (*monitor
)(struct efx_nic
*efx
);
875 int (*reset
)(struct efx_nic
*efx
, enum reset_type method
);
876 int (*probe_port
)(struct efx_nic
*efx
);
877 void (*remove_port
)(struct efx_nic
*efx
);
878 void (*prepare_flush
)(struct efx_nic
*efx
);
879 void (*update_stats
)(struct efx_nic
*efx
);
880 void (*start_stats
)(struct efx_nic
*efx
);
881 void (*stop_stats
)(struct efx_nic
*efx
);
882 void (*set_id_led
)(struct efx_nic
*efx
, enum efx_led_mode mode
);
883 void (*push_irq_moderation
)(struct efx_channel
*channel
);
884 void (*push_multicast_hash
)(struct efx_nic
*efx
);
885 int (*reconfigure_port
)(struct efx_nic
*efx
);
886 void (*get_wol
)(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
);
887 int (*set_wol
)(struct efx_nic
*efx
, u32 type
);
888 void (*resume_wol
)(struct efx_nic
*efx
);
889 int (*test_registers
)(struct efx_nic
*efx
);
890 int (*test_nvram
)(struct efx_nic
*efx
);
891 struct efx_mac_operations
*default_mac_ops
;
894 unsigned int mem_map_size
;
895 unsigned int txd_ptr_tbl_base
;
896 unsigned int rxd_ptr_tbl_base
;
897 unsigned int buf_tbl_base
;
898 unsigned int evq_ptr_tbl_base
;
899 unsigned int evq_rptr_tbl_base
;
901 unsigned int rx_buffer_hash_size
;
902 unsigned int rx_buffer_padding
;
903 unsigned int max_interrupt_mode
;
904 unsigned int phys_addr_channels
;
905 unsigned int tx_dc_base
;
906 unsigned int rx_dc_base
;
907 unsigned long offload_features
;
908 u32 reset_world_flags
;
911 /**************************************************************************
913 * Prototypes and inline functions
915 *************************************************************************/
917 static inline struct efx_channel
*
918 efx_get_channel(struct efx_nic
*efx
, unsigned index
)
920 EFX_BUG_ON_PARANOID(index
>= efx
->n_channels
);
921 return efx
->channel
[index
];
924 /* Iterate over all used channels */
925 #define efx_for_each_channel(_channel, _efx) \
926 for (_channel = (_efx)->channel[0]; \
928 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
929 (_efx)->channel[_channel->channel + 1] : NULL)
931 extern struct efx_tx_queue
*
932 efx_get_tx_queue(struct efx_nic
*efx
, unsigned index
, unsigned type
);
934 static inline struct efx_tx_queue
*
935 efx_channel_get_tx_queue(struct efx_channel
*channel
, unsigned type
)
937 struct efx_tx_queue
*tx_queue
= channel
->tx_queue
;
938 EFX_BUG_ON_PARANOID(type
>= EFX_TXQ_TYPES
);
939 return tx_queue
->channel
? tx_queue
+ type
: NULL
;
942 /* Iterate over all TX queues belonging to a channel */
943 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
944 for (_tx_queue = efx_channel_get_tx_queue(channel, 0); \
945 _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
948 static inline struct efx_rx_queue
*
949 efx_get_rx_queue(struct efx_nic
*efx
, unsigned index
)
951 EFX_BUG_ON_PARANOID(index
>= efx
->n_rx_channels
);
952 return &efx
->channel
[index
]->rx_queue
;
955 static inline struct efx_rx_queue
*
956 efx_channel_get_rx_queue(struct efx_channel
*channel
)
958 return channel
->channel
< channel
->efx
->n_rx_channels
?
959 &channel
->rx_queue
: NULL
;
962 /* Iterate over all RX queues belonging to a channel */
963 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
964 for (_rx_queue = efx_channel_get_rx_queue(channel); \
968 static inline struct efx_channel
*
969 efx_rx_queue_channel(struct efx_rx_queue
*rx_queue
)
971 return container_of(rx_queue
, struct efx_channel
, rx_queue
);
974 static inline int efx_rx_queue_index(struct efx_rx_queue
*rx_queue
)
976 return efx_rx_queue_channel(rx_queue
)->channel
;
979 /* Returns a pointer to the specified receive buffer in the RX
982 static inline struct efx_rx_buffer
*efx_rx_buffer(struct efx_rx_queue
*rx_queue
,
985 return (&rx_queue
->buffer
[index
]);
988 /* Set bit in a little-endian bitfield */
989 static inline void set_bit_le(unsigned nr
, unsigned char *addr
)
991 addr
[nr
/ 8] |= (1 << (nr
% 8));
994 /* Clear bit in a little-endian bitfield */
995 static inline void clear_bit_le(unsigned nr
, unsigned char *addr
)
997 addr
[nr
/ 8] &= ~(1 << (nr
% 8));
1002 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1004 * This calculates the maximum frame length that will be used for a
1005 * given MTU. The frame length will be equal to the MTU plus a
1006 * constant amount of header space and padding. This is the quantity
1007 * that the net driver will program into the MAC as the maximum frame
1010 * The 10G MAC requires 8-byte alignment on the frame
1011 * length, so we round up to the nearest 8.
1013 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1014 * XGMII cycle). If the frame length reaches the maximum value in the
1015 * same cycle, the XMAC can miss the IPG altogether. We work around
1016 * this by adding a further 16 bytes.
1018 #define EFX_MAX_FRAME_LEN(mtu) \
1019 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1022 #endif /* EFX_NET_DRIVER_H */