drivers/net/sfc/net_driver.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2005-2009 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 /* Common definitions for all Efx net driver code */
  12
  13 #ifndef EFX_NET_DRIVER_H
  14 #define EFX_NET_DRIVER_H
  15
  16 #if defined(EFX_ENABLE_DEBUG) && !defined(DEBUG)
  17 #define DEBUG
  18 #endif
  19
  20 #include <linux/version.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_vlan.h>
  25 #include <linux/timer.h>
  26 #include <linux/mdio.h>
  27 #include <linux/list.h>
  28 #include <linux/pci.h>
  29 #include <linux/device.h>
  30 #include <linux/highmem.h>
  31 #include <linux/workqueue.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/i2c.h>
  34
  35 #include "enum.h"
  36 #include "bitfield.h"
  37
  38 /**************************************************************************
  39  *
  40  * Build definitions
  41  *
  42  **************************************************************************/
  43
  44 #define EFX_DRIVER_VERSION      "3.0"
  45
  46 #ifdef EFX_ENABLE_DEBUG
  47 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
  48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
  49 #else
  50 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
  51 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
  52 #endif
  53
  54 /**************************************************************************
  55  *
  56  * Efx data structures
  57  *
  58  **************************************************************************/
  59
  60 #define EFX_MAX_CHANNELS 32
  61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
  62
  63 /* Checksum generation is a per-queue option in hardware, so each
  64  * queue visible to the networking core is backed by two hardware TX
  65  * queues. */
  66 #define EFX_MAX_CORE_TX_QUEUES  EFX_MAX_CHANNELS
  67 #define EFX_TXQ_TYPE_OFFLOAD    1
  68 #define EFX_TXQ_TYPES           2
  69 #define EFX_MAX_TX_QUEUES       (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES)
  70
  71 /**
  72  * struct efx_special_buffer - An Efx special buffer
  73  * @addr: CPU base address of the buffer
  74  * @dma_addr: DMA base address of the buffer
  75  * @len: Buffer length, in bytes
  76  * @index: Buffer index within controller;s buffer table
  77  * @entries: Number of buffer table entries
  78  *
  79  * Special buffers are used for the event queues and the TX and RX
  80  * descriptor queues for each channel.  They are *not* used for the
  81  * actual transmit and receive buffers.
  82  */
  83 struct efx_special_buffer {
  84         void *addr;
  85         dma_addr_t dma_addr;
  86         unsigned int len;
  87         int index;
  88         int entries;
  89 };
  90
  91 enum efx_flush_state {
  92         FLUSH_NONE,
  93         FLUSH_PENDING,
  94         FLUSH_FAILED,
  95         FLUSH_DONE,
  96 };
  97
  98 /**
  99  * struct efx_tx_buffer - An Efx TX buffer
 100  * @skb: The associated socket buffer.
 101  *      Set only on the final fragment of a packet; %NULL for all other
 102  *      fragments.  When this fragment completes, then we can free this
 103  *      skb.
 104  * @tsoh: The associated TSO header structure, or %NULL if this
 105  *      buffer is not a TSO header.
 106  * @dma_addr: DMA address of the fragment.
 107  * @len: Length of this fragment.
 108  *      This field is zero when the queue slot is empty.
 109  * @continuation: True if this fragment is not the end of a packet.
 110  * @unmap_single: True if pci_unmap_single should be used.
 111  * @unmap_len: Length of this fragment to unmap
 112  */
 113 struct efx_tx_buffer {
 114         const struct sk_buff *skb;
 115         struct efx_tso_header *tsoh;
 116         dma_addr_t dma_addr;
 117         unsigned short len;
 118         bool continuation;
 119         bool unmap_single;
 120         unsigned short unmap_len;
 121 };
 122
 123 /**
 124  * struct efx_tx_queue - An Efx TX queue
 125  *
 126  * This is a ring buffer of TX fragments.
 127  * Since the TX completion path always executes on the same
 128  * CPU and the xmit path can operate on different CPUs,
 129  * performance is increased by ensuring that the completion
 130  * path and the xmit path operate on different cache lines.
 131  * This is particularly important if the xmit path is always
 132  * executing on one CPU which is different from the completion
 133  * path.  There is also a cache line for members which are
 134  * read but not written on the fast path.
 135  *
 136  * @efx: The associated Efx NIC
 137  * @queue: DMA queue number
 138  * @channel: The associated channel
 139  * @buffer: The software buffer ring
 140  * @txd: The hardware descriptor ring
 141  * @ptr_mask: The size of the ring minus 1.
 142  * @flushed: Used when handling queue flushing
 143  * @read_count: Current read pointer.
 144  *      This is the number of buffers that have been removed from both rings.
 145  * @stopped: Stopped count.
 146  *      Set if this TX queue is currently stopping its port.
 147  * @insert_count: Current insert pointer
 148  *      This is the number of buffers that have been added to the
 149  *      software ring.
 150  * @write_count: Current write pointer
 151  *      This is the number of buffers that have been added to the
 152  *      hardware ring.
 153  * @old_read_count: The value of read_count when last checked.
 154  *      This is here for performance reasons.  The xmit path will
 155  *      only get the up-to-date value of read_count if this
 156  *      variable indicates that the queue is full.  This is to
 157  *      avoid cache-line ping-pong between the xmit path and the
 158  *      completion path.
 159  * @tso_headers_free: A list of TSO headers allocated for this TX queue
 160  *      that are not in use, and so available for new TSO sends. The list
 161  *      is protected by the TX queue lock.
 162  * @tso_bursts: Number of times TSO xmit invoked by kernel
 163  * @tso_long_headers: Number of packets with headers too long for standard
 164  *      blocks
 165  * @tso_packets: Number of packets via the TSO xmit path
 166  */
 167 struct efx_tx_queue {
 168         /* Members which don't change on the fast path */
 169         struct efx_nic *efx ____cacheline_aligned_in_smp;
 170         unsigned queue;
 171         struct efx_channel *channel;
 172         struct efx_nic *nic;
 173         struct efx_tx_buffer *buffer;
 174         struct efx_special_buffer txd;
 175         unsigned int ptr_mask;
 176         enum efx_flush_state flushed;
 177
 178         /* Members used mainly on the completion path */
 179         unsigned int read_count ____cacheline_aligned_in_smp;
 180         int stopped;
 181
 182         /* Members used only on the xmit path */
 183         unsigned int insert_count ____cacheline_aligned_in_smp;
 184         unsigned int write_count;
 185         unsigned int old_read_count;
 186         struct efx_tso_header *tso_headers_free;
 187         unsigned int tso_bursts;
 188         unsigned int tso_long_headers;
 189         unsigned int tso_packets;
 190 };
 191
 192 /**
 193  * struct efx_rx_buffer - An Efx RX data buffer
 194  * @dma_addr: DMA base address of the buffer
 195  * @skb: The associated socket buffer, if any.
 196  *      If both this and page are %NULL, the buffer slot is currently free.
 197  * @page: The associated page buffer, if any.
 198  *      If both this and skb are %NULL, the buffer slot is currently free.
 199  * @data: Pointer to ethernet header
 200  * @len: Buffer length, in bytes.
 201  */
 202 struct efx_rx_buffer {
 203         dma_addr_t dma_addr;
 204         struct sk_buff *skb;
 205         struct page *page;
 206         char *data;
 207         unsigned int len;
 208 };
 209
 210 /**
 211  * struct efx_rx_page_state - Page-based rx buffer state
 212  *
 213  * Inserted at the start of every page allocated for receive buffers.
 214  * Used to facilitate sharing dma mappings between recycled rx buffers
 215  * and those passed up to the kernel.
 216  *
 217  * @refcnt: Number of struct efx_rx_buffer's referencing this page.
 218  *      When refcnt falls to zero, the page is unmapped for dma
 219  * @dma_addr: The dma address of this page.
 220  */
 221 struct efx_rx_page_state {
 222         unsigned refcnt;
 223         dma_addr_t dma_addr;
 224
 225         unsigned int __pad[0] ____cacheline_aligned;
 226 };
 227
 228 /**
 229  * struct efx_rx_queue - An Efx RX queue
 230  * @efx: The associated Efx NIC
 231  * @buffer: The software buffer ring
 232  * @rxd: The hardware descriptor ring
 233  * @ptr_mask: The size of the ring minus 1.
 234  * @added_count: Number of buffers added to the receive queue.
 235  * @notified_count: Number of buffers given to NIC (<= @added_count).
 236  * @removed_count: Number of buffers removed from the receive queue.
 237  * @max_fill: RX descriptor maximum fill level (<= ring size)
 238  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
 239  *      (<= @max_fill)
 240  * @fast_fill_limit: The level to which a fast fill will fill
 241  *      (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
 242  * @min_fill: RX descriptor minimum non-zero fill level.
 243  *      This records the minimum fill level observed when a ring
 244  *      refill was triggered.
 245  * @alloc_page_count: RX allocation strategy counter.
 246  * @alloc_skb_count: RX allocation strategy counter.
 247  * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
 248  * @flushed: Use when handling queue flushing
 249  */
 250 struct efx_rx_queue {
 251         struct efx_nic *efx;
 252         struct efx_rx_buffer *buffer;
 253         struct efx_special_buffer rxd;
 254         unsigned int ptr_mask;
 255
 256         int added_count;
 257         int notified_count;
 258         int removed_count;
 259         unsigned int max_fill;
 260         unsigned int fast_fill_trigger;
 261         unsigned int fast_fill_limit;
 262         unsigned int min_fill;
 263         unsigned int min_overfill;
 264         unsigned int alloc_page_count;
 265         unsigned int alloc_skb_count;
 266         struct timer_list slow_fill;
 267         unsigned int slow_fill_count;
 268
 269         enum efx_flush_state flushed;
 270 };
 271
 272 /**
 273  * struct efx_buffer - An Efx general-purpose buffer
 274  * @addr: host base address of the buffer
 275  * @dma_addr: DMA base address of the buffer
 276  * @len: Buffer length, in bytes
 277  *
 278  * The NIC uses these buffers for its interrupt status registers and
 279  * MAC stats dumps.
 280  */
 281 struct efx_buffer {
 282         void *addr;
 283         dma_addr_t dma_addr;
 284         unsigned int len;
 285 };
 286
 287
 288 enum efx_rx_alloc_method {
 289         RX_ALLOC_METHOD_AUTO = 0,
 290         RX_ALLOC_METHOD_SKB = 1,
 291         RX_ALLOC_METHOD_PAGE = 2,
 292 };
 293
 294 /**
 295  * struct efx_channel - An Efx channel
 296  *
 297  * A channel comprises an event queue, at least one TX queue, at least
 298  * one RX queue, and an associated tasklet for processing the event
 299  * queue.
 300  *
 301  * @efx: Associated Efx NIC
 302  * @channel: Channel instance number
 303  * @enabled: Channel enabled indicator
 304  * @irq: IRQ number (MSI and MSI-X only)
 305  * @irq_moderation: IRQ moderation value (in hardware ticks)
 306  * @napi_dev: Net device used with NAPI
 307  * @napi_str: NAPI control structure
 308  * @reset_work: Scheduled reset work thread
 309  * @work_pending: Is work pending via NAPI?
 310  * @eventq: Event queue buffer
 311  * @eventq_mask: Event queue pointer mask
 312  * @eventq_read_ptr: Event queue read pointer
 313  * @last_eventq_read_ptr: Last event queue read pointer value.
 314  * @magic_count: Event queue test event count
 315  * @irq_count: Number of IRQs since last adaptive moderation decision
 316  * @irq_mod_score: IRQ moderation score
 317  * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
 318  *      and diagnostic counters
 319  * @rx_alloc_push_pages: RX allocation method currently in use for pushing
 320  *      descriptors
 321  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
 322  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
 323  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
 324  * @n_rx_mcast_mismatch: Count of unmatched multicast frames
 325  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
 326  * @n_rx_overlength: Count of RX_OVERLENGTH errors
 327  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
 328  * @rx_queue: RX queue for this channel
 329  * @tx_stop_count: Core TX queue stop count
 330  * @tx_stop_lock: Core TX queue stop lock
 331  * @tx_queue: TX queues for this channel
 332  */
 333 struct efx_channel {
 334         struct efx_nic *efx;
 335         int channel;
 336         bool enabled;
 337         int irq;
 338         unsigned int irq_moderation;
 339         struct net_device *napi_dev;
 340         struct napi_struct napi_str;
 341         bool work_pending;
 342         struct efx_special_buffer eventq;
 343         unsigned int eventq_mask;
 344         unsigned int eventq_read_ptr;
 345         unsigned int last_eventq_read_ptr;
 346         unsigned int magic_count;
 347
 348         unsigned int irq_count;
 349         unsigned int irq_mod_score;
 350
 351         int rx_alloc_level;
 352         int rx_alloc_push_pages;
 353
 354         unsigned n_rx_tobe_disc;
 355         unsigned n_rx_ip_hdr_chksum_err;
 356         unsigned n_rx_tcp_udp_chksum_err;
 357         unsigned n_rx_mcast_mismatch;
 358         unsigned n_rx_frm_trunc;
 359         unsigned n_rx_overlength;
 360         unsigned n_skbuff_leaks;
 361
 362         /* Used to pipeline received packets in order to optimise memory
 363          * access with prefetches.
 364          */
 365         struct efx_rx_buffer *rx_pkt;
 366         bool rx_pkt_csummed;
 367
 368         struct efx_rx_queue rx_queue;
 369
 370         atomic_t tx_stop_count;
 371         spinlock_t tx_stop_lock;
 372
 373         struct efx_tx_queue tx_queue[2];
 374 };
 375
 376 enum efx_led_mode {
 377         EFX_LED_OFF     = 0,
 378         EFX_LED_ON      = 1,
 379         EFX_LED_DEFAULT = 2
 380 };
 381
 382 #define STRING_TABLE_LOOKUP(val, member) \
 383         ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
 384
 385 extern const char *efx_loopback_mode_names[];
 386 extern const unsigned int efx_loopback_mode_max;
 387 #define LOOPBACK_MODE(efx) \
 388         STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
 389
 390 extern const char *efx_reset_type_names[];
 391 extern const unsigned int efx_reset_type_max;
 392 #define RESET_TYPE(type) \
 393         STRING_TABLE_LOOKUP(type, efx_reset_type)
 394
 395 enum efx_int_mode {
 396         /* Be careful if altering to correct macro below */
 397         EFX_INT_MODE_MSIX = 0,
 398         EFX_INT_MODE_MSI = 1,
 399         EFX_INT_MODE_LEGACY = 2,
 400         EFX_INT_MODE_MAX        /* Insert any new items before this */
 401 };
 402 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
 403
 404 enum nic_state {
 405         STATE_INIT = 0,
 406         STATE_RUNNING = 1,
 407         STATE_FINI = 2,
 408         STATE_DISABLED = 3,
 409         STATE_MAX,
 410 };
 411
 412 /*
 413  * Alignment of page-allocated RX buffers
 414  *
 415  * Controls the number of bytes inserted at the start of an RX buffer.
 416  * This is the equivalent of NET_IP_ALIGN [which controls the alignment
 417  * of the skb->head for hardware DMA].
 418  */
 419 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 420 #define EFX_PAGE_IP_ALIGN 0
 421 #else
 422 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
 423 #endif
 424
 425 /*
 426  * Alignment of the skb->head which wraps a page-allocated RX buffer
 427  *
 428  * The skb allocated to wrap an rx_buffer can have this alignment. Since
 429  * the data is memcpy'd from the rx_buf, it does not need to be equal to
 430  * EFX_PAGE_IP_ALIGN.
 431  */
 432 #define EFX_PAGE_SKB_ALIGN 2
 433
 434 /* Forward declaration */
 435 struct efx_nic;
 436
 437 /* Pseudo bit-mask flow control field */
 438 enum efx_fc_type {
 439         EFX_FC_RX = FLOW_CTRL_RX,
 440         EFX_FC_TX = FLOW_CTRL_TX,
 441         EFX_FC_AUTO = 4,
 442 };
 443
 444 /**
 445  * struct efx_link_state - Current state of the link
 446  * @up: Link is up
 447  * @fd: Link is full-duplex
 448  * @fc: Actual flow control flags
 449  * @speed: Link speed (Mbps)
 450  */
 451 struct efx_link_state {
 452         bool up;
 453         bool fd;
 454         enum efx_fc_type fc;
 455         unsigned int speed;
 456 };
 457
 458 static inline bool efx_link_state_equal(const struct efx_link_state *left,
 459                                         const struct efx_link_state *right)
 460 {
 461         return left->up == right->up && left->fd == right->fd &&
 462                 left->fc == right->fc && left->speed == right->speed;
 463 }
 464
 465 /**
 466  * struct efx_mac_operations - Efx MAC operations table
 467  * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
 468  * @update_stats: Update statistics
 469  * @check_fault: Check fault state. True if fault present.
 470  */
 471 struct efx_mac_operations {
 472         int (*reconfigure) (struct efx_nic *efx);
 473         void (*update_stats) (struct efx_nic *efx);
 474         bool (*check_fault)(struct efx_nic *efx);
 475 };
 476
 477 /**
 478  * struct efx_phy_operations - Efx PHY operations table
 479  * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
 480  *      efx->loopback_modes.
 481  * @init: Initialise PHY
 482  * @fini: Shut down PHY
 483  * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
 484  * @poll: Update @link_state and report whether it changed.
 485  *      Serialised by the mac_lock.
 486  * @get_settings: Get ethtool settings. Serialised by the mac_lock.
 487  * @set_settings: Set ethtool settings. Serialised by the mac_lock.
 488  * @set_npage_adv: Set abilities advertised in (Extended) Next Page
 489  *      (only needed where AN bit is set in mmds)
 490  * @test_alive: Test that PHY is 'alive' (online)
 491  * @test_name: Get the name of a PHY-specific test/result
 492  * @run_tests: Run tests and record results as appropriate (offline).
 493  *      Flags are the ethtool tests flags.
 494  */
 495 struct efx_phy_operations {
 496         int (*probe) (struct efx_nic *efx);
 497         int (*init) (struct efx_nic *efx);
 498         void (*fini) (struct efx_nic *efx);
 499         void (*remove) (struct efx_nic *efx);
 500         int (*reconfigure) (struct efx_nic *efx);
 501         bool (*poll) (struct efx_nic *efx);
 502         void (*get_settings) (struct efx_nic *efx,
 503                               struct ethtool_cmd *ecmd);
 504         int (*set_settings) (struct efx_nic *efx,
 505                              struct ethtool_cmd *ecmd);
 506         void (*set_npage_adv) (struct efx_nic *efx, u32);
 507         int (*test_alive) (struct efx_nic *efx);
 508         const char *(*test_name) (struct efx_nic *efx, unsigned int index);
 509         int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
 510 };
 511
 512 /**
 513  * @enum efx_phy_mode - PHY operating mode flags
 514  * @PHY_MODE_NORMAL: on and should pass traffic
 515  * @PHY_MODE_TX_DISABLED: on with TX disabled
 516  * @PHY_MODE_LOW_POWER: set to low power through MDIO
 517  * @PHY_MODE_OFF: switched off through external control
 518  * @PHY_MODE_SPECIAL: on but will not pass traffic
 519  */
 520 enum efx_phy_mode {
 521         PHY_MODE_NORMAL         = 0,
 522         PHY_MODE_TX_DISABLED    = 1,
 523         PHY_MODE_LOW_POWER      = 2,
 524         PHY_MODE_OFF            = 4,
 525         PHY_MODE_SPECIAL        = 8,
 526 };
 527
 528 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
 529 {
 530         return !!(mode & ~PHY_MODE_TX_DISABLED);
 531 }
 532
 533 /*
 534  * Efx extended statistics
 535  *
 536  * Not all statistics are provided by all supported MACs.  The purpose
 537  * is this structure is to contain the raw statistics provided by each
 538  * MAC.
 539  */
 540 struct efx_mac_stats {
 541         u64 tx_bytes;
 542         u64 tx_good_bytes;
 543         u64 tx_bad_bytes;
 544         unsigned long tx_packets;
 545         unsigned long tx_bad;
 546         unsigned long tx_pause;
 547         unsigned long tx_control;
 548         unsigned long tx_unicast;
 549         unsigned long tx_multicast;
 550         unsigned long tx_broadcast;
 551         unsigned long tx_lt64;
 552         unsigned long tx_64;
 553         unsigned long tx_65_to_127;
 554         unsigned long tx_128_to_255;
 555         unsigned long tx_256_to_511;
 556         unsigned long tx_512_to_1023;
 557         unsigned long tx_1024_to_15xx;
 558         unsigned long tx_15xx_to_jumbo;
 559         unsigned long tx_gtjumbo;
 560         unsigned long tx_collision;
 561         unsigned long tx_single_collision;
 562         unsigned long tx_multiple_collision;
 563         unsigned long tx_excessive_collision;
 564         unsigned long tx_deferred;
 565         unsigned long tx_late_collision;
 566         unsigned long tx_excessive_deferred;
 567         unsigned long tx_non_tcpudp;
 568         unsigned long tx_mac_src_error;
 569         unsigned long tx_ip_src_error;
 570         u64 rx_bytes;
 571         u64 rx_good_bytes;
 572         u64 rx_bad_bytes;
 573         unsigned long rx_packets;
 574         unsigned long rx_good;
 575         unsigned long rx_bad;
 576         unsigned long rx_pause;
 577         unsigned long rx_control;
 578         unsigned long rx_unicast;
 579         unsigned long rx_multicast;
 580         unsigned long rx_broadcast;
 581         unsigned long rx_lt64;
 582         unsigned long rx_64;
 583         unsigned long rx_65_to_127;
 584         unsigned long rx_128_to_255;
 585         unsigned long rx_256_to_511;
 586         unsigned long rx_512_to_1023;
 587         unsigned long rx_1024_to_15xx;
 588         unsigned long rx_15xx_to_jumbo;
 589         unsigned long rx_gtjumbo;
 590         unsigned long rx_bad_lt64;
 591         unsigned long rx_bad_64_to_15xx;
 592         unsigned long rx_bad_15xx_to_jumbo;
 593         unsigned long rx_bad_gtjumbo;
 594         unsigned long rx_overflow;
 595         unsigned long rx_missed;
 596         unsigned long rx_false_carrier;
 597         unsigned long rx_symbol_error;
 598         unsigned long rx_align_error;
 599         unsigned long rx_length_error;
 600         unsigned long rx_internal_error;
 601         unsigned long rx_good_lt64;
 602 };
 603
 604 /* Number of bits used in a multicast filter hash address */
 605 #define EFX_MCAST_HASH_BITS 8
 606
 607 /* Number of (single-bit) entries in a multicast filter hash */
 608 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
 609
 610 /* An Efx multicast filter hash */
 611 union efx_multicast_hash {
 612         u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
 613         efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
 614 };
 615
 616 struct efx_filter_state;
 617
 618 /**
 619  * struct efx_nic - an Efx NIC
 620  * @name: Device name (net device name or bus id before net device registered)
 621  * @pci_dev: The PCI device
 622  * @type: Controller type attributes
 623  * @legacy_irq: IRQ number
 624  * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)?
 625  * @workqueue: Workqueue for port reconfigures and the HW monitor.
 626  *      Work items do not hold and must not acquire RTNL.
 627  * @workqueue_name: Name of workqueue
 628  * @reset_work: Scheduled reset workitem
 629  * @monitor_work: Hardware monitor workitem
 630  * @membase_phys: Memory BAR value as physical address
 631  * @membase: Memory BAR value
 632  * @biu_lock: BIU (bus interface unit) lock
 633  * @interrupt_mode: Interrupt mode
 634  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
 635  * @irq_rx_moderation: IRQ moderation time for RX event queues
 636  * @msg_enable: Log message enable flags
 637  * @state: Device state flag. Serialised by the rtnl_lock.
 638  * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
 639  * @tx_queue: TX DMA queues
 640  * @rx_queue: RX DMA queues
 641  * @channel: Channels
 642  * @channel_name: Names for channels and their IRQs
 643  * @rxq_entries: Size of receive queues requested by user.
 644  * @txq_entries: Size of transmit queues requested by user.
 645  * @next_buffer_table: First available buffer table id
 646  * @n_channels: Number of channels in use
 647  * @n_rx_channels: Number of channels used for RX (= number of RX queues)
 648  * @n_tx_channels: Number of channels used for TX
 649  * @rx_buffer_len: RX buffer length
 650  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
 651  * @rx_indir_table: Indirection table for RSS
 652  * @int_error_count: Number of internal errors seen recently
 653  * @int_error_expire: Time at which error count will be expired
 654  * @irq_status: Interrupt status buffer
 655  * @last_irq_cpu: Last CPU to handle interrupt.
 656  *      This register is written with the SMP processor ID whenever an
 657  *      interrupt is handled.  It is used by efx_nic_test_interrupt()
 658  *      to verify that an interrupt has occurred.
 659  * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
 660  * @fatal_irq_level: IRQ level (bit number) used for serious errors
 661  * @spi_flash: SPI flash device
 662  *      This field will be %NULL if no flash device is present (or for Siena).
 663  * @spi_eeprom: SPI EEPROM device
 664  *      This field will be %NULL if no EEPROM device is present (or for Siena).
 665  * @spi_lock: SPI bus lock
 666  * @mtd_list: List of MTDs attached to the NIC
 667  * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
 668  * @nic_data: Hardware dependant state
 669  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
 670  *      @port_inhibited, efx_monitor() and efx_reconfigure_port()
 671  * @port_enabled: Port enabled indicator.
 672  *      Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
 673  *      efx_mac_work() with kernel interfaces. Safe to read under any
 674  *      one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
 675  *      be held to modify it.
 676  * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
 677  * @port_initialized: Port initialized?
 678  * @net_dev: Operating system network device. Consider holding the rtnl lock
 679  * @rx_checksum_enabled: RX checksumming enabled
 680  * @mac_stats: MAC statistics. These include all statistics the MACs
 681  *      can provide.  Generic code converts these into a standard
 682  *      &struct net_device_stats.
 683  * @stats_buffer: DMA buffer for statistics
 684  * @stats_lock: Statistics update lock. Serialises statistics fetches
 685  * @mac_op: MAC interface
 686  * @mac_address: Permanent MAC address
 687  * @phy_type: PHY type
 688  * @mdio_lock: MDIO lock
 689  * @phy_op: PHY interface
 690  * @phy_data: PHY private data (including PHY-specific stats)
 691  * @mdio: PHY MDIO interface
 692  * @mdio_bus: PHY MDIO bus ID (only used by Siena)
 693  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
 694  * @xmac_poll_required: XMAC link state needs polling
 695  * @link_advertising: Autonegotiation advertising flags
 696  * @link_state: Current state of the link
 697  * @n_link_state_changes: Number of times the link has changed state
 698  * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
 699  * @multicast_hash: Multicast hash table
 700  * @wanted_fc: Wanted flow control flags
 701  * @mac_work: Work item for changing MAC promiscuity and multicast hash
 702  * @loopback_mode: Loopback status
 703  * @loopback_modes: Supported loopback mode bitmask
 704  * @loopback_selftest: Offline self-test private state
 705  *
 706  * This is stored in the private area of the &struct net_device.
 707  */
 708 struct efx_nic {
 709         char name[IFNAMSIZ];
 710         struct pci_dev *pci_dev;
 711         const struct efx_nic_type *type;
 712         int legacy_irq;
 713         bool legacy_irq_enabled;
 714         struct workqueue_struct *workqueue;
 715         char workqueue_name[16];
 716         struct work_struct reset_work;
 717         struct delayed_work monitor_work;
 718         resource_size_t membase_phys;
 719         void __iomem *membase;
 720         spinlock_t biu_lock;
 721         enum efx_int_mode interrupt_mode;
 722         bool irq_rx_adaptive;
 723         unsigned int irq_rx_moderation;
 724         u32 msg_enable;
 725
 726         enum nic_state state;
 727         enum reset_type reset_pending;
 728
 729         struct efx_channel *channel[EFX_MAX_CHANNELS];
 730         char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6];
 731
 732         unsigned rxq_entries;
 733         unsigned txq_entries;
 734         unsigned next_buffer_table;
 735         unsigned n_channels;
 736         unsigned n_rx_channels;
 737         unsigned n_tx_channels;
 738         unsigned int rx_buffer_len;
 739         unsigned int rx_buffer_order;
 740         u8 rx_hash_key[40];
 741         u32 rx_indir_table[128];
 742
 743         unsigned int_error_count;
 744         unsigned long int_error_expire;
 745
 746         struct efx_buffer irq_status;
 747         volatile signed int last_irq_cpu;
 748         unsigned irq_zero_count;
 749         unsigned fatal_irq_level;
 750
 751         struct efx_spi_device *spi_flash;
 752         struct efx_spi_device *spi_eeprom;
 753         struct mutex spi_lock;
 754 #ifdef CONFIG_SFC_MTD
 755         struct list_head mtd_list;
 756 #endif
 757
 758         unsigned n_rx_nodesc_drop_cnt;
 759
 760         void *nic_data;
 761
 762         struct mutex mac_lock;
 763         struct work_struct mac_work;
 764         bool port_enabled;
 765         bool port_inhibited;
 766
 767         bool port_initialized;
 768         struct net_device *net_dev;
 769         bool rx_checksum_enabled;
 770
 771         struct efx_mac_stats mac_stats;
 772         struct efx_buffer stats_buffer;
 773         spinlock_t stats_lock;
 774
 775         struct efx_mac_operations *mac_op;
 776         unsigned char mac_address[ETH_ALEN];
 777
 778         unsigned int phy_type;
 779         struct mutex mdio_lock;
 780         struct efx_phy_operations *phy_op;
 781         void *phy_data;
 782         struct mdio_if_info mdio;
 783         unsigned int mdio_bus;
 784         enum efx_phy_mode phy_mode;
 785
 786         bool xmac_poll_required;
 787         u32 link_advertising;
 788         struct efx_link_state link_state;
 789         unsigned int n_link_state_changes;
 790
 791         bool promiscuous;
 792         union efx_multicast_hash multicast_hash;
 793         enum efx_fc_type wanted_fc;
 794
 795         atomic_t rx_reset;
 796         enum efx_loopback_mode loopback_mode;
 797         u64 loopback_modes;
 798
 799         void *loopback_selftest;
 800
 801         struct efx_filter_state *filter_state;
 802 };
 803
 804 static inline int efx_dev_registered(struct efx_nic *efx)
 805 {
 806         return efx->net_dev->reg_state == NETREG_REGISTERED;
 807 }
 808
 809 /* Net device name, for inclusion in log messages if it has been registered.
 810  * Use efx->name not efx->net_dev->name so that races with (un)registration
 811  * are harmless.
 812  */
 813 static inline const char *efx_dev_name(struct efx_nic *efx)
 814 {
 815         return efx_dev_registered(efx) ? efx->name : "";
 816 }
 817
 818 static inline unsigned int efx_port_num(struct efx_nic *efx)
 819 {
 820         return efx->net_dev->dev_id;
 821 }
 822
 823 /**
 824  * struct efx_nic_type - Efx device type definition
 825  * @probe: Probe the controller
 826  * @remove: Free resources allocated by probe()
 827  * @init: Initialise the controller
 828  * @fini: Shut down the controller
 829  * @monitor: Periodic function for polling link state and hardware monitor
 830  * @reset: Reset the controller hardware and possibly the PHY.  This will
 831  *      be called while the controller is uninitialised.
 832  * @probe_port: Probe the MAC and PHY
 833  * @remove_port: Free resources allocated by probe_port()
 834  * @prepare_flush: Prepare the hardware for flushing the DMA queues
 835  * @update_stats: Update statistics not provided by event handling
 836  * @start_stats: Start the regular fetching of statistics
 837  * @stop_stats: Stop the regular fetching of statistics
 838  * @set_id_led: Set state of identifying LED or revert to automatic function
 839  * @push_irq_moderation: Apply interrupt moderation value
 840  * @push_multicast_hash: Apply multicast hash table
 841  * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
 842  * @get_wol: Get WoL configuration from driver state
 843  * @set_wol: Push WoL configuration to the NIC
 844  * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
 845  * @test_registers: Test read/write functionality of control registers
 846  * @test_nvram: Test validity of NVRAM contents
 847  * @default_mac_ops: efx_mac_operations to set at startup
 848  * @revision: Hardware architecture revision
 849  * @mem_map_size: Memory BAR mapped size
 850  * @txd_ptr_tbl_base: TX descriptor ring base address
 851  * @rxd_ptr_tbl_base: RX descriptor ring base address
 852  * @buf_tbl_base: Buffer table base address
 853  * @evq_ptr_tbl_base: Event queue pointer table base address
 854  * @evq_rptr_tbl_base: Event queue read-pointer table base address
 855  * @max_dma_mask: Maximum possible DMA mask
 856  * @rx_buffer_hash_size: Size of hash at start of RX buffer
 857  * @rx_buffer_padding: Size of padding at end of RX buffer
 858  * @max_interrupt_mode: Highest capability interrupt mode supported
 859  *      from &enum efx_init_mode.
 860  * @phys_addr_channels: Number of channels with physically addressed
 861  *      descriptors
 862  * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
 863  * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
 864  * @offload_features: net_device feature flags for protocol offload
 865  *      features implemented in hardware
 866  * @reset_world_flags: Flags for additional components covered by
 867  *      reset method RESET_TYPE_WORLD
 868  */
 869 struct efx_nic_type {
 870         int (*probe)(struct efx_nic *efx);
 871         void (*remove)(struct efx_nic *efx);
 872         int (*init)(struct efx_nic *efx);
 873         void (*fini)(struct efx_nic *efx);
 874         void (*monitor)(struct efx_nic *efx);
 875         int (*reset)(struct efx_nic *efx, enum reset_type method);
 876         int (*probe_port)(struct efx_nic *efx);
 877         void (*remove_port)(struct efx_nic *efx);
 878         void (*prepare_flush)(struct efx_nic *efx);
 879         void (*update_stats)(struct efx_nic *efx);
 880         void (*start_stats)(struct efx_nic *efx);
 881         void (*stop_stats)(struct efx_nic *efx);
 882         void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
 883         void (*push_irq_moderation)(struct efx_channel *channel);
 884         void (*push_multicast_hash)(struct efx_nic *efx);
 885         int (*reconfigure_port)(struct efx_nic *efx);
 886         void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
 887         int (*set_wol)(struct efx_nic *efx, u32 type);
 888         void (*resume_wol)(struct efx_nic *efx);
 889         int (*test_registers)(struct efx_nic *efx);
 890         int (*test_nvram)(struct efx_nic *efx);
 891         struct efx_mac_operations *default_mac_ops;
 892
 893         int revision;
 894         unsigned int mem_map_size;
 895         unsigned int txd_ptr_tbl_base;
 896         unsigned int rxd_ptr_tbl_base;
 897         unsigned int buf_tbl_base;
 898         unsigned int evq_ptr_tbl_base;
 899         unsigned int evq_rptr_tbl_base;
 900         u64 max_dma_mask;
 901         unsigned int rx_buffer_hash_size;
 902         unsigned int rx_buffer_padding;
 903         unsigned int max_interrupt_mode;
 904         unsigned int phys_addr_channels;
 905         unsigned int tx_dc_base;
 906         unsigned int rx_dc_base;
 907         unsigned long offload_features;
 908         u32 reset_world_flags;
 909 };
 910
 911 /**************************************************************************
 912  *
 913  * Prototypes and inline functions
 914  *
 915  *************************************************************************/
 916
 917 static inline struct efx_channel *
 918 efx_get_channel(struct efx_nic *efx, unsigned index)
 919 {
 920         EFX_BUG_ON_PARANOID(index >= efx->n_channels);
 921         return efx->channel[index];
 922 }
 923
 924 /* Iterate over all used channels */
 925 #define efx_for_each_channel(_channel, _efx)                            \
 926         for (_channel = (_efx)->channel[0];                             \
 927              _channel;                                                  \
 928              _channel = (_channel->channel + 1 < (_efx)->n_channels) ?  \
 929                      (_efx)->channel[_channel->channel + 1] : NULL)
 930
 931 extern struct efx_tx_queue *
 932 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type);
 933
 934 static inline struct efx_tx_queue *
 935 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
 936 {
 937         struct efx_tx_queue *tx_queue = channel->tx_queue;
 938         EFX_BUG_ON_PARANOID(type >= EFX_TXQ_TYPES);
 939         return tx_queue->channel ? tx_queue + type : NULL;
 940 }
 941
 942 /* Iterate over all TX queues belonging to a channel */
 943 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)              \
 944         for (_tx_queue = efx_channel_get_tx_queue(channel, 0);          \
 945              _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
 946              _tx_queue++)
 947
 948 static inline struct efx_rx_queue *
 949 efx_get_rx_queue(struct efx_nic *efx, unsigned index)
 950 {
 951         EFX_BUG_ON_PARANOID(index >= efx->n_rx_channels);
 952         return &efx->channel[index]->rx_queue;
 953 }
 954
 955 static inline struct efx_rx_queue *
 956 efx_channel_get_rx_queue(struct efx_channel *channel)
 957 {
 958         return channel->channel < channel->efx->n_rx_channels ?
 959                 &channel->rx_queue : NULL;
 960 }
 961
 962 /* Iterate over all RX queues belonging to a channel */
 963 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)              \
 964         for (_rx_queue = efx_channel_get_rx_queue(channel);             \
 965              _rx_queue;                                                 \
 966              _rx_queue = NULL)
 967
 968 static inline struct efx_channel *
 969 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
 970 {
 971         return container_of(rx_queue, struct efx_channel, rx_queue);
 972 }
 973
 974 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
 975 {
 976         return efx_rx_queue_channel(rx_queue)->channel;
 977 }
 978
 979 /* Returns a pointer to the specified receive buffer in the RX
 980  * descriptor queue.
 981  */
 982 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
 983                                                   unsigned int index)
 984 {
 985         return &rx_queue->buffer[index];
 986 }
 987
 988 /* Set bit in a little-endian bitfield */
 989 static inline void set_bit_le(unsigned nr, unsigned char *addr)
 990 {
 991         addr[nr / 8] |= (1 << (nr % 8));
 992 }
 993
 994 /* Clear bit in a little-endian bitfield */
 995 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
 996 {
 997         addr[nr / 8] &= ~(1 << (nr % 8));
 998 }
 999
1000
1001 /**
1002  * EFX_MAX_FRAME_LEN - calculate maximum frame length
1003  *
1004  * This calculates the maximum frame length that will be used for a
1005  * given MTU.  The frame length will be equal to the MTU plus a
1006  * constant amount of header space and padding.  This is the quantity
1007  * that the net driver will program into the MAC as the maximum frame
1008  * length.
1009  *
1010  * The 10G MAC requires 8-byte alignment on the frame
1011  * length, so we round up to the nearest 8.
1012  *
1013  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1014  * XGMII cycle).  If the frame length reaches the maximum value in the
1015  * same cycle, the XMAC can miss the IPG altogether.  We work around
1016  * this by adding a further 16 bytes.
1017  */
1018 #define EFX_MAX_FRAME_LEN(mtu) \
1019         ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1020
1021
1022 #endif /* EFX_NET_DRIVER_H */