drivers/net/sfc/qt202x_phy.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2006-2009 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9 /*
  10  * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
  11  */
  12
  13 #include <linux/slab.h>
  14 #include <linux/timer.h>
  15 #include <linux/delay.h>
  16 #include "efx.h"
  17 #include "mdio_10g.h"
  18 #include "phy.h"
  19 #include "nic.h"
  20
  21 #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS |           \
  22                               MDIO_DEVS_PMAPMD |        \
  23                               MDIO_DEVS_PHYXS)
  24
  25 #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) |         \
  26                           (1 << LOOPBACK_PMAPMD) |      \
  27                           (1 << LOOPBACK_PHYXS_WS))
  28
  29 /****************************************************************************/
  30 /* Quake-specific MDIO registers */
  31 #define MDIO_QUAKE_LED0_REG     (0xD006)
  32
  33 /* QT2025C only */
  34 #define PCS_FW_HEARTBEAT_REG    0xd7ee
  35 #define PCS_FW_HEARTB_LBN       0
  36 #define PCS_FW_HEARTB_WIDTH     8
  37 #define PCS_FW_PRODUCT_CODE_1   0xd7f0
  38 #define PCS_FW_VERSION_1        0xd7f3
  39 #define PCS_FW_BUILD_1          0xd7f6
  40 #define PCS_UC8051_STATUS_REG   0xd7fd
  41 #define PCS_UC_STATUS_LBN       0
  42 #define PCS_UC_STATUS_WIDTH     8
  43 #define PCS_UC_STATUS_FW_SAVE   0x20
  44 #define PMA_PMD_FTX_CTRL2_REG   0xc309
  45 #define PMA_PMD_FTX_STATIC_LBN  13
  46 #define PMA_PMD_VEND1_REG       0xc001
  47 #define PMA_PMD_VEND1_LBTXD_LBN 15
  48 #define PCS_VEND1_REG           0xc000
  49 #define PCS_VEND1_LBTXD_LBN     5
  50
  51 void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
  52 {
  53         int addr = MDIO_QUAKE_LED0_REG + led;
  54         efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
  55 }
  56
  57 struct qt202x_phy_data {
  58         enum efx_phy_mode phy_mode;
  59         bool bug17190_in_bad_state;
  60         unsigned long bug17190_timer;
  61         u32 firmware_ver;
  62 };
  63
  64 #define QT2022C2_MAX_RESET_TIME 500
  65 #define QT2022C2_RESET_WAIT 10
  66
  67 #define QT2025C_MAX_HEARTB_TIME (5 * HZ)
  68 #define QT2025C_HEARTB_WAIT 100
  69 #define QT2025C_MAX_FWSTART_TIME (25 * HZ / 10)
  70 #define QT2025C_FWSTART_WAIT 100
  71
  72 #define BUG17190_INTERVAL (2 * HZ)
  73
  74 static int qt2025c_wait_heartbeat(struct efx_nic *efx)
  75 {
  76         unsigned long timeout = jiffies + QT2025C_MAX_HEARTB_TIME;
  77         int reg, old_counter = 0;
  78
  79         /* Wait for firmware heartbeat to start */
  80         for (;;) {
  81                 int counter;
  82                 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
  83                 if (reg < 0)
  84                         return reg;
  85                 counter = ((reg >> PCS_FW_HEARTB_LBN) &
  86                             ((1 << PCS_FW_HEARTB_WIDTH) - 1));
  87                 if (old_counter == 0)
  88                         old_counter = counter;
  89                 else if (counter != old_counter)
  90                         break;
  91                 if (time_after(jiffies, timeout)) {
  92                         /* Some cables have EEPROMs that conflict with the
  93                          * PHY's on-board EEPROM so it cannot load firmware */
  94                         netif_err(efx, hw, efx->net_dev,
  95                                   "If an SFP+ direct attach cable is"
  96                                   " connected, please check that it complies"
  97                                   " with the SFP+ specification\n");
  98                         return -ETIMEDOUT;
  99                 }
 100                 msleep(QT2025C_HEARTB_WAIT);
 101         }
 102
 103         return 0;
 104 }
 105
 106 static int qt2025c_wait_fw_status_good(struct efx_nic *efx)
 107 {
 108         unsigned long timeout = jiffies + QT2025C_MAX_FWSTART_TIME;
 109         int reg;
 110
 111         /* Wait for firmware status to look good */
 112         for (;;) {
 113                 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
 114                 if (reg < 0)
 115                         return reg;
 116                 if ((reg &
 117                      ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
 118                     PCS_UC_STATUS_FW_SAVE)
 119                         break;
 120                 if (time_after(jiffies, timeout))
 121                         return -ETIMEDOUT;
 122                 msleep(QT2025C_FWSTART_WAIT);
 123         }
 124
 125         return 0;
 126 }
 127
 128 static void qt2025c_restart_firmware(struct efx_nic *efx)
 129 {
 130         /* Restart microcontroller execution of firmware from RAM */
 131         efx_mdio_write(efx, 3, 0xe854, 0x00c0);
 132         efx_mdio_write(efx, 3, 0xe854, 0x0040);
 133         msleep(50);
 134 }
 135
 136 static int qt2025c_wait_reset(struct efx_nic *efx)
 137 {
 138         int rc;
 139
 140         rc = qt2025c_wait_heartbeat(efx);
 141         if (rc != 0)
 142                 return rc;
 143
 144         rc = qt2025c_wait_fw_status_good(efx);
 145         if (rc == -ETIMEDOUT) {
 146                 /* Bug 17689: occasionally heartbeat starts but firmware status
 147                  * code never progresses beyond 0x00.  Try again, once, after
 148                  * restarting execution of the firmware image. */
 149                 netif_dbg(efx, hw, efx->net_dev,
 150                           "bashing QT2025C microcontroller\n");
 151                 qt2025c_restart_firmware(efx);
 152                 rc = qt2025c_wait_heartbeat(efx);
 153                 if (rc != 0)
 154                         return rc;
 155                 rc = qt2025c_wait_fw_status_good(efx);
 156         }
 157
 158         return rc;
 159 }
 160
 161 static void qt2025c_firmware_id(struct efx_nic *efx)
 162 {
 163         struct qt202x_phy_data *phy_data = efx->phy_data;
 164         u8 firmware_id[9];
 165         size_t i;
 166
 167         for (i = 0; i < sizeof(firmware_id); i++)
 168                 firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS,
 169                                                PCS_FW_PRODUCT_CODE_1 + i);
 170         netif_info(efx, probe, efx->net_dev,
 171                    "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
 172                    (firmware_id[0] << 8) | firmware_id[1], firmware_id[2],
 173                    firmware_id[3] >> 4, firmware_id[3] & 0xf,
 174                    firmware_id[4], firmware_id[5],
 175                    firmware_id[6], firmware_id[7], firmware_id[8]);
 176         phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) |
 177                                  ((firmware_id[3] & 0x0f) << 16) |
 178                                  (firmware_id[4] << 8) | firmware_id[5];
 179 }
 180
 181 static void qt2025c_bug17190_workaround(struct efx_nic *efx)
 182 {
 183         struct qt202x_phy_data *phy_data = efx->phy_data;
 184
 185         /* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD
 186          * layers up, but PCS down (no block_lock).  If we notice this state
 187          * persisting for a couple of seconds, we switch PMA/PMD loopback
 188          * briefly on and then off again, which is normally sufficient to
 189          * recover it.
 190          */
 191         if (efx->link_state.up ||
 192             !efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) {
 193                 phy_data->bug17190_in_bad_state = false;
 194                 return;
 195         }
 196
 197         if (!phy_data->bug17190_in_bad_state) {
 198                 phy_data->bug17190_in_bad_state = true;
 199                 phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
 200                 return;
 201         }
 202
 203         if (time_after_eq(jiffies, phy_data->bug17190_timer)) {
 204                 netif_dbg(efx, hw, efx->net_dev, "bashing QT2025C PMA/PMD\n");
 205                 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
 206                                   MDIO_PMA_CTRL1_LOOPBACK, true);
 207                 msleep(100);
 208                 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
 209                                   MDIO_PMA_CTRL1_LOOPBACK, false);
 210                 phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
 211         }
 212 }
 213
 214 static int qt2025c_select_phy_mode(struct efx_nic *efx)
 215 {
 216         struct qt202x_phy_data *phy_data = efx->phy_data;
 217         struct falcon_board *board = falcon_board(efx);
 218         int reg, rc, i;
 219         uint16_t phy_op_mode;
 220
 221         /* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
 222          * Self-Configure mode.  Don't attempt any switching if we encounter
 223          * older firmware. */
 224         if (phy_data->firmware_ver < 0x02000100)
 225                 return 0;
 226
 227         /* In general we will get optimal behaviour in "SFP+ Self-Configure"
 228          * mode; however, that powers down most of the PHY when no module is
 229          * present, so we must use a different mode (any fixed mode will do)
 230          * to be sure that loopbacks will work. */
 231         phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;
 232
 233         /* Only change mode if really necessary */
 234         reg = efx_mdio_read(efx, 1, 0xc319);
 235         if ((reg & 0x0038) == phy_op_mode)
 236                 return 0;
 237         netif_dbg(efx, hw, efx->net_dev, "Switching PHY to mode 0x%04x\n",
 238                   phy_op_mode);
 239
 240         /* This sequence replicates the register writes configured in the boot
 241          * EEPROM (including the differences between board revisions), except
 242          * that the operating mode is changed, and the PHY is prevented from
 243          * unnecessarily reloading the main firmware image again. */
 244         efx_mdio_write(efx, 1, 0xc300, 0x0000);
 245         /* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
 246          * STOPs onto the firmware/module I2C bus to reset it, varies across
 247          * board revisions, as the bus is connected to different GPIO/LED
 248          * outputs on the PHY.) */
 249         if (board->major == 0 && board->minor < 2) {
 250                 efx_mdio_write(efx, 1, 0xc303, 0x4498);
 251                 for (i = 0; i < 9; i++) {
 252                         efx_mdio_write(efx, 1, 0xc303, 0x4488);
 253                         efx_mdio_write(efx, 1, 0xc303, 0x4480);
 254                         efx_mdio_write(efx, 1, 0xc303, 0x4490);
 255                         efx_mdio_write(efx, 1, 0xc303, 0x4498);
 256                 }
 257         } else {
 258                 efx_mdio_write(efx, 1, 0xc303, 0x0920);
 259                 efx_mdio_write(efx, 1, 0xd008, 0x0004);
 260                 for (i = 0; i < 9; i++) {
 261                         efx_mdio_write(efx, 1, 0xc303, 0x0900);
 262                         efx_mdio_write(efx, 1, 0xd008, 0x0005);
 263                         efx_mdio_write(efx, 1, 0xc303, 0x0920);
 264                         efx_mdio_write(efx, 1, 0xd008, 0x0004);
 265                 }
 266                 efx_mdio_write(efx, 1, 0xc303, 0x4900);
 267         }
 268         efx_mdio_write(efx, 1, 0xc303, 0x4900);
 269         efx_mdio_write(efx, 1, 0xc302, 0x0004);
 270         efx_mdio_write(efx, 1, 0xc316, 0x0013);
 271         efx_mdio_write(efx, 1, 0xc318, 0x0054);
 272         efx_mdio_write(efx, 1, 0xc319, phy_op_mode);
 273         efx_mdio_write(efx, 1, 0xc31a, 0x0098);
 274         efx_mdio_write(efx, 3, 0x0026, 0x0e00);
 275         efx_mdio_write(efx, 3, 0x0027, 0x0013);
 276         efx_mdio_write(efx, 3, 0x0028, 0xa528);
 277         efx_mdio_write(efx, 1, 0xd006, 0x000a);
 278         efx_mdio_write(efx, 1, 0xd007, 0x0009);
 279         efx_mdio_write(efx, 1, 0xd008, 0x0004);
 280         /* This additional write is not present in the boot EEPROM.  It
 281          * prevents the PHY's internal boot ROM doing another pointless (and
 282          * slow) reload of the firmware image (the microcontroller's code
 283          * memory is not affected by the microcontroller reset). */
 284         efx_mdio_write(efx, 1, 0xc317, 0x00ff);
 285         efx_mdio_write(efx, 1, 0xc300, 0x0002);
 286         msleep(20);
 287
 288         /* Restart microcontroller execution of firmware from RAM */
 289         qt2025c_restart_firmware(efx);
 290
 291         /* Wait for the microcontroller to be ready again */
 292         rc = qt2025c_wait_reset(efx);
 293         if (rc < 0) {
 294                 netif_err(efx, hw, efx->net_dev,
 295                           "PHY microcontroller reset during mode switch "
 296                           "timed out\n");
 297                 return rc;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int qt202x_reset_phy(struct efx_nic *efx)
 304 {
 305         int rc;
 306
 307         if (efx->phy_type == PHY_TYPE_QT2025C) {
 308                 /* Wait for the reset triggered by falcon_reset_hw()
 309                  * to complete */
 310                 rc = qt2025c_wait_reset(efx);
 311                 if (rc < 0)
 312                         goto fail;
 313         } else {
 314                 /* Reset the PHYXS MMD. This is documented as doing
 315                  * a complete soft reset. */
 316                 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
 317                                         QT2022C2_MAX_RESET_TIME /
 318                                         QT2022C2_RESET_WAIT,
 319                                         QT2022C2_RESET_WAIT);
 320                 if (rc < 0)
 321                         goto fail;
 322         }
 323
 324         /* Wait 250ms for the PHY to complete bootup */
 325         msleep(250);
 326
 327         falcon_board(efx)->type->init_phy(efx);
 328
 329         return 0;
 330
 331  fail:
 332         netif_err(efx, hw, efx->net_dev, "PHY reset timed out\n");
 333         return rc;
 334 }
 335
 336 static int qt202x_phy_probe(struct efx_nic *efx)
 337 {
 338         struct qt202x_phy_data *phy_data;
 339
 340         phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
 341         if (!phy_data)
 342                 return -ENOMEM;
 343         efx->phy_data = phy_data;
 344         phy_data->phy_mode = efx->phy_mode;
 345         phy_data->bug17190_in_bad_state = false;
 346         phy_data->bug17190_timer = 0;
 347
 348         efx->mdio.mmds = QT202X_REQUIRED_DEVS;
 349         efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
 350         efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
 351         return 0;
 352 }
 353
 354 static int qt202x_phy_init(struct efx_nic *efx)
 355 {
 356         u32 devid;
 357         int rc;
 358
 359         rc = qt202x_reset_phy(efx);
 360         if (rc) {
 361                 netif_err(efx, probe, efx->net_dev, "PHY init failed\n");
 362                 return rc;
 363         }
 364
 365         devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
 366         netif_info(efx, probe, efx->net_dev,
 367                    "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
 368                    devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
 369                    efx_mdio_id_rev(devid));
 370
 371         if (efx->phy_type == PHY_TYPE_QT2025C)
 372                 qt2025c_firmware_id(efx);
 373
 374         return 0;
 375 }
 376
 377 static int qt202x_link_ok(struct efx_nic *efx)
 378 {
 379         return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
 380 }
 381
 382 static bool qt202x_phy_poll(struct efx_nic *efx)
 383 {
 384         bool was_up = efx->link_state.up;
 385
 386         efx->link_state.up = qt202x_link_ok(efx);
 387         efx->link_state.speed = 10000;
 388         efx->link_state.fd = true;
 389         efx->link_state.fc = efx->wanted_fc;
 390
 391         if (efx->phy_type == PHY_TYPE_QT2025C)
 392                 qt2025c_bug17190_workaround(efx);
 393
 394         return efx->link_state.up != was_up;
 395 }
 396
 397 static int qt202x_phy_reconfigure(struct efx_nic *efx)
 398 {
 399         struct qt202x_phy_data *phy_data = efx->phy_data;
 400
 401         if (efx->phy_type == PHY_TYPE_QT2025C) {
 402                 int rc = qt2025c_select_phy_mode(efx);
 403                 if (rc)
 404                         return rc;
 405
 406                 /* There are several different register bits which can
 407                  * disable TX (and save power) on direct-attach cables
 408                  * or optical transceivers, varying somewhat between
 409                  * firmware versions.  Only 'static mode' appears to
 410                  * cover everything. */
 411                 mdio_set_flag(
 412                         &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
 413                         PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
 414                         efx->phy_mode & PHY_MODE_TX_DISABLED ||
 415                         efx->phy_mode & PHY_MODE_LOW_POWER ||
 416                         efx->loopback_mode == LOOPBACK_PCS ||
 417                         efx->loopback_mode == LOOPBACK_PMAPMD);
 418         } else {
 419                 /* Reset the PHY when moving from tx off to tx on */
 420                 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
 421                     (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
 422                         qt202x_reset_phy(efx);
 423
 424                 efx_mdio_transmit_disable(efx);
 425         }
 426
 427         efx_mdio_phy_reconfigure(efx);
 428
 429         phy_data->phy_mode = efx->phy_mode;
 430
 431         return 0;
 432 }
 433
 434 static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
 435 {
 436         mdio45_ethtool_gset(&efx->mdio, ecmd);
 437 }
 438
 439 static void qt202x_phy_remove(struct efx_nic *efx)
 440 {
 441         /* Free the context block */
 442         kfree(efx->phy_data);
 443         efx->phy_data = NULL;
 444 }
 445
 446 struct efx_phy_operations falcon_qt202x_phy_ops = {
 447         .probe           = qt202x_phy_probe,
 448         .init            = qt202x_phy_init,
 449         .reconfigure     = qt202x_phy_reconfigure,
 450         .poll            = qt202x_phy_poll,
 451         .fini            = efx_port_dummy_op_void,
 452         .remove          = qt202x_phy_remove,
 453         .get_settings    = qt202x_phy_get_settings,
 454         .set_settings    = efx_mdio_set_settings,
 455         .test_alive      = efx_mdio_test_alive,
 456 };