Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux...
[deliverable/linux.git] / drivers / net / sfc / tx.c
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/tcp.h>
13 #include <linux/ip.h>
14 #include <linux/in.h>
15 #include <linux/ipv6.h>
16 #include <linux/slab.h>
17 #include <net/ipv6.h>
18 #include <linux/if_ether.h>
19 #include <linux/highmem.h>
20 #include "net_driver.h"
21 #include "efx.h"
22 #include "nic.h"
23 #include "workarounds.h"
24
25 /*
26 * TX descriptor ring full threshold
27 *
28 * The tx_queue descriptor ring fill-level must fall below this value
29 * before we restart the netif queue
30 */
31 #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u)
32
33 /* We need to be able to nest calls to netif_tx_stop_queue(), partly
34 * because of the 2 hardware queues associated with each core queue,
35 * but also so that we can inhibit TX for reasons other than a full
36 * hardware queue. */
37 void efx_stop_queue(struct efx_channel *channel)
38 {
39 struct efx_nic *efx = channel->efx;
40 struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
41
42 if (!tx_queue)
43 return;
44
45 spin_lock_bh(&channel->tx_stop_lock);
46 netif_vdbg(efx, tx_queued, efx->net_dev, "stop TX queue\n");
47
48 atomic_inc(&channel->tx_stop_count);
49 netif_tx_stop_queue(
50 netdev_get_tx_queue(efx->net_dev,
51 tx_queue->queue / EFX_TXQ_TYPES));
52
53 spin_unlock_bh(&channel->tx_stop_lock);
54 }
55
56 /* Decrement core TX queue stop count and wake it if the count is 0 */
57 void efx_wake_queue(struct efx_channel *channel)
58 {
59 struct efx_nic *efx = channel->efx;
60 struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
61
62 if (!tx_queue)
63 return;
64
65 local_bh_disable();
66 if (atomic_dec_and_lock(&channel->tx_stop_count,
67 &channel->tx_stop_lock)) {
68 netif_vdbg(efx, tx_queued, efx->net_dev, "waking TX queue\n");
69 netif_tx_wake_queue(
70 netdev_get_tx_queue(efx->net_dev,
71 tx_queue->queue / EFX_TXQ_TYPES));
72 spin_unlock(&channel->tx_stop_lock);
73 }
74 local_bh_enable();
75 }
76
77 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
78 struct efx_tx_buffer *buffer)
79 {
80 if (buffer->unmap_len) {
81 struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
82 dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
83 buffer->unmap_len);
84 if (buffer->unmap_single)
85 pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
86 PCI_DMA_TODEVICE);
87 else
88 pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
89 PCI_DMA_TODEVICE);
90 buffer->unmap_len = 0;
91 buffer->unmap_single = false;
92 }
93
94 if (buffer->skb) {
95 dev_kfree_skb_any((struct sk_buff *) buffer->skb);
96 buffer->skb = NULL;
97 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
98 "TX queue %d transmission id %x complete\n",
99 tx_queue->queue, tx_queue->read_count);
100 }
101 }
102
103 /**
104 * struct efx_tso_header - a DMA mapped buffer for packet headers
105 * @next: Linked list of free ones.
106 * The list is protected by the TX queue lock.
107 * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
108 * @dma_addr: The DMA address of the header below.
109 *
110 * This controls the memory used for a TSO header. Use TSOH_DATA()
111 * to find the packet header data. Use TSOH_SIZE() to calculate the
112 * total size required for a given packet header length. TSO headers
113 * in the free list are exactly %TSOH_STD_SIZE bytes in size.
114 */
115 struct efx_tso_header {
116 union {
117 struct efx_tso_header *next;
118 size_t unmap_len;
119 };
120 dma_addr_t dma_addr;
121 };
122
123 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
124 struct sk_buff *skb);
125 static void efx_fini_tso(struct efx_tx_queue *tx_queue);
126 static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
127 struct efx_tso_header *tsoh);
128
129 static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
130 struct efx_tx_buffer *buffer)
131 {
132 if (buffer->tsoh) {
133 if (likely(!buffer->tsoh->unmap_len)) {
134 buffer->tsoh->next = tx_queue->tso_headers_free;
135 tx_queue->tso_headers_free = buffer->tsoh;
136 } else {
137 efx_tsoh_heap_free(tx_queue, buffer->tsoh);
138 }
139 buffer->tsoh = NULL;
140 }
141 }
142
143
144 static inline unsigned
145 efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
146 {
147 /* Depending on the NIC revision, we can use descriptor
148 * lengths up to 8K or 8K-1. However, since PCI Express
149 * devices must split read requests at 4K boundaries, there is
150 * little benefit from using descriptors that cross those
151 * boundaries and we keep things simple by not doing so.
152 */
153 unsigned len = (~dma_addr & 0xfff) + 1;
154
155 /* Work around hardware bug for unaligned buffers. */
156 if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
157 len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
158
159 return len;
160 }
161
162 /*
163 * Add a socket buffer to a TX queue
164 *
165 * This maps all fragments of a socket buffer for DMA and adds them to
166 * the TX queue. The queue's insert pointer will be incremented by
167 * the number of fragments in the socket buffer.
168 *
169 * If any DMA mapping fails, any mapped fragments will be unmapped,
170 * the queue's insert pointer will be restored to its original value.
171 *
172 * This function is split out from efx_hard_start_xmit to allow the
173 * loopback test to direct packets via specific TX queues.
174 *
175 * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
176 * You must hold netif_tx_lock() to call this function.
177 */
178 netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
179 {
180 struct efx_nic *efx = tx_queue->efx;
181 struct pci_dev *pci_dev = efx->pci_dev;
182 struct efx_tx_buffer *buffer;
183 skb_frag_t *fragment;
184 struct page *page;
185 int page_offset;
186 unsigned int len, unmap_len = 0, fill_level, insert_ptr;
187 dma_addr_t dma_addr, unmap_addr = 0;
188 unsigned int dma_len;
189 bool unmap_single;
190 int q_space, i = 0;
191 netdev_tx_t rc = NETDEV_TX_OK;
192
193 EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
194
195 if (skb_shinfo(skb)->gso_size)
196 return efx_enqueue_skb_tso(tx_queue, skb);
197
198 /* Get size of the initial fragment */
199 len = skb_headlen(skb);
200
201 /* Pad if necessary */
202 if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
203 EFX_BUG_ON_PARANOID(skb->data_len);
204 len = 32 + 1;
205 if (skb_pad(skb, len - skb->len))
206 return NETDEV_TX_OK;
207 }
208
209 fill_level = tx_queue->insert_count - tx_queue->old_read_count;
210 q_space = efx->txq_entries - 1 - fill_level;
211
212 /* Map for DMA. Use pci_map_single rather than pci_map_page
213 * since this is more efficient on machines with sparse
214 * memory.
215 */
216 unmap_single = true;
217 dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
218
219 /* Process all fragments */
220 while (1) {
221 if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
222 goto pci_err;
223
224 /* Store fields for marking in the per-fragment final
225 * descriptor */
226 unmap_len = len;
227 unmap_addr = dma_addr;
228
229 /* Add to TX queue, splitting across DMA boundaries */
230 do {
231 if (unlikely(q_space-- <= 0)) {
232 /* It might be that completions have
233 * happened since the xmit path last
234 * checked. Update the xmit path's
235 * copy of read_count.
236 */
237 ++tx_queue->stopped;
238 /* This memory barrier protects the
239 * change of stopped from the access
240 * of read_count. */
241 smp_mb();
242 tx_queue->old_read_count =
243 *(volatile unsigned *)
244 &tx_queue->read_count;
245 fill_level = (tx_queue->insert_count
246 - tx_queue->old_read_count);
247 q_space = efx->txq_entries - 1 - fill_level;
248 if (unlikely(q_space-- <= 0))
249 goto stop;
250 smp_mb();
251 --tx_queue->stopped;
252 }
253
254 insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
255 buffer = &tx_queue->buffer[insert_ptr];
256 efx_tsoh_free(tx_queue, buffer);
257 EFX_BUG_ON_PARANOID(buffer->tsoh);
258 EFX_BUG_ON_PARANOID(buffer->skb);
259 EFX_BUG_ON_PARANOID(buffer->len);
260 EFX_BUG_ON_PARANOID(!buffer->continuation);
261 EFX_BUG_ON_PARANOID(buffer->unmap_len);
262
263 dma_len = efx_max_tx_len(efx, dma_addr);
264 if (likely(dma_len >= len))
265 dma_len = len;
266
267 /* Fill out per descriptor fields */
268 buffer->len = dma_len;
269 buffer->dma_addr = dma_addr;
270 len -= dma_len;
271 dma_addr += dma_len;
272 ++tx_queue->insert_count;
273 } while (len);
274
275 /* Transfer ownership of the unmapping to the final buffer */
276 buffer->unmap_single = unmap_single;
277 buffer->unmap_len = unmap_len;
278 unmap_len = 0;
279
280 /* Get address and size of next fragment */
281 if (i >= skb_shinfo(skb)->nr_frags)
282 break;
283 fragment = &skb_shinfo(skb)->frags[i];
284 len = fragment->size;
285 page = fragment->page;
286 page_offset = fragment->page_offset;
287 i++;
288 /* Map for DMA */
289 unmap_single = false;
290 dma_addr = pci_map_page(pci_dev, page, page_offset, len,
291 PCI_DMA_TODEVICE);
292 }
293
294 /* Transfer ownership of the skb to the final buffer */
295 buffer->skb = skb;
296 buffer->continuation = false;
297
298 /* Pass off to hardware */
299 efx_nic_push_buffers(tx_queue);
300
301 return NETDEV_TX_OK;
302
303 pci_err:
304 netif_err(efx, tx_err, efx->net_dev,
305 " TX queue %d could not map skb with %d bytes %d "
306 "fragments for DMA\n", tx_queue->queue, skb->len,
307 skb_shinfo(skb)->nr_frags + 1);
308
309 /* Mark the packet as transmitted, and free the SKB ourselves */
310 dev_kfree_skb_any(skb);
311 goto unwind;
312
313 stop:
314 rc = NETDEV_TX_BUSY;
315
316 if (tx_queue->stopped == 1)
317 efx_stop_queue(tx_queue->channel);
318
319 unwind:
320 /* Work backwards until we hit the original insert pointer value */
321 while (tx_queue->insert_count != tx_queue->write_count) {
322 --tx_queue->insert_count;
323 insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
324 buffer = &tx_queue->buffer[insert_ptr];
325 efx_dequeue_buffer(tx_queue, buffer);
326 buffer->len = 0;
327 }
328
329 /* Free the fragment we were mid-way through pushing */
330 if (unmap_len) {
331 if (unmap_single)
332 pci_unmap_single(pci_dev, unmap_addr, unmap_len,
333 PCI_DMA_TODEVICE);
334 else
335 pci_unmap_page(pci_dev, unmap_addr, unmap_len,
336 PCI_DMA_TODEVICE);
337 }
338
339 return rc;
340 }
341
342 /* Remove packets from the TX queue
343 *
344 * This removes packets from the TX queue, up to and including the
345 * specified index.
346 */
347 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
348 unsigned int index)
349 {
350 struct efx_nic *efx = tx_queue->efx;
351 unsigned int stop_index, read_ptr;
352
353 stop_index = (index + 1) & tx_queue->ptr_mask;
354 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
355
356 while (read_ptr != stop_index) {
357 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
358 if (unlikely(buffer->len == 0)) {
359 netif_err(efx, tx_err, efx->net_dev,
360 "TX queue %d spurious TX completion id %x\n",
361 tx_queue->queue, read_ptr);
362 efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
363 return;
364 }
365
366 efx_dequeue_buffer(tx_queue, buffer);
367 buffer->continuation = true;
368 buffer->len = 0;
369
370 ++tx_queue->read_count;
371 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
372 }
373 }
374
375 /* Initiate a packet transmission. We use one channel per CPU
376 * (sharing when we have more CPUs than channels). On Falcon, the TX
377 * completion events will be directed back to the CPU that transmitted
378 * the packet, which should be cache-efficient.
379 *
380 * Context: non-blocking.
381 * Note that returning anything other than NETDEV_TX_OK will cause the
382 * OS to free the skb.
383 */
384 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
385 struct net_device *net_dev)
386 {
387 struct efx_nic *efx = netdev_priv(net_dev);
388 struct efx_tx_queue *tx_queue;
389
390 if (unlikely(efx->port_inhibited))
391 return NETDEV_TX_BUSY;
392
393 tx_queue = efx_get_tx_queue(efx, skb_get_queue_mapping(skb),
394 skb->ip_summed == CHECKSUM_PARTIAL ?
395 EFX_TXQ_TYPE_OFFLOAD : 0);
396
397 return efx_enqueue_skb(tx_queue, skb);
398 }
399
400 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
401 {
402 unsigned fill_level;
403 struct efx_nic *efx = tx_queue->efx;
404
405 EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
406
407 efx_dequeue_buffers(tx_queue, index);
408
409 /* See if we need to restart the netif queue. This barrier
410 * separates the update of read_count from the test of
411 * stopped. */
412 smp_mb();
413 if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
414 fill_level = tx_queue->insert_count - tx_queue->read_count;
415 if (fill_level < EFX_TXQ_THRESHOLD(efx)) {
416 EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
417
418 /* Do this under netif_tx_lock(), to avoid racing
419 * with efx_xmit(). */
420 netif_tx_lock(efx->net_dev);
421 if (tx_queue->stopped) {
422 tx_queue->stopped = 0;
423 efx_wake_queue(tx_queue->channel);
424 }
425 netif_tx_unlock(efx->net_dev);
426 }
427 }
428 }
429
430 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
431 {
432 struct efx_nic *efx = tx_queue->efx;
433 unsigned int entries;
434 int i, rc;
435
436 /* Create the smallest power-of-two aligned ring */
437 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
438 EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
439 tx_queue->ptr_mask = entries - 1;
440
441 netif_dbg(efx, probe, efx->net_dev,
442 "creating TX queue %d size %#x mask %#x\n",
443 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
444
445 /* Allocate software ring */
446 tx_queue->buffer = kzalloc(entries * sizeof(*tx_queue->buffer),
447 GFP_KERNEL);
448 if (!tx_queue->buffer)
449 return -ENOMEM;
450 for (i = 0; i <= tx_queue->ptr_mask; ++i)
451 tx_queue->buffer[i].continuation = true;
452
453 /* Allocate hardware ring */
454 rc = efx_nic_probe_tx(tx_queue);
455 if (rc)
456 goto fail;
457
458 return 0;
459
460 fail:
461 kfree(tx_queue->buffer);
462 tx_queue->buffer = NULL;
463 return rc;
464 }
465
466 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
467 {
468 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
469 "initialising TX queue %d\n", tx_queue->queue);
470
471 tx_queue->insert_count = 0;
472 tx_queue->write_count = 0;
473 tx_queue->read_count = 0;
474 tx_queue->old_read_count = 0;
475 BUG_ON(tx_queue->stopped);
476
477 /* Set up TX descriptor ring */
478 efx_nic_init_tx(tx_queue);
479 }
480
481 void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
482 {
483 struct efx_tx_buffer *buffer;
484
485 if (!tx_queue->buffer)
486 return;
487
488 /* Free any buffers left in the ring */
489 while (tx_queue->read_count != tx_queue->write_count) {
490 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
491 efx_dequeue_buffer(tx_queue, buffer);
492 buffer->continuation = true;
493 buffer->len = 0;
494
495 ++tx_queue->read_count;
496 }
497 }
498
499 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
500 {
501 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
502 "shutting down TX queue %d\n", tx_queue->queue);
503
504 /* Flush TX queue, remove descriptor ring */
505 efx_nic_fini_tx(tx_queue);
506
507 efx_release_tx_buffers(tx_queue);
508
509 /* Free up TSO header cache */
510 efx_fini_tso(tx_queue);
511
512 /* Release queue's stop on port, if any */
513 if (tx_queue->stopped) {
514 tx_queue->stopped = 0;
515 efx_wake_queue(tx_queue->channel);
516 }
517 }
518
519 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
520 {
521 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
522 "destroying TX queue %d\n", tx_queue->queue);
523 efx_nic_remove_tx(tx_queue);
524
525 kfree(tx_queue->buffer);
526 tx_queue->buffer = NULL;
527 }
528
529
530 /* Efx TCP segmentation acceleration.
531 *
532 * Why? Because by doing it here in the driver we can go significantly
533 * faster than the GSO.
534 *
535 * Requires TX checksum offload support.
536 */
537
538 /* Number of bytes inserted at the start of a TSO header buffer,
539 * similar to NET_IP_ALIGN.
540 */
541 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
542 #define TSOH_OFFSET 0
543 #else
544 #define TSOH_OFFSET NET_IP_ALIGN
545 #endif
546
547 #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
548
549 /* Total size of struct efx_tso_header, buffer and padding */
550 #define TSOH_SIZE(hdr_len) \
551 (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
552
553 /* Size of blocks on free list. Larger blocks must be allocated from
554 * the heap.
555 */
556 #define TSOH_STD_SIZE 128
557
558 #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
559 #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
560 #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
561 #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
562 #define SKB_IPV6_OFF(skb) PTR_DIFF(ipv6_hdr(skb), (skb)->data)
563
564 /**
565 * struct tso_state - TSO state for an SKB
566 * @out_len: Remaining length in current segment
567 * @seqnum: Current sequence number
568 * @ipv4_id: Current IPv4 ID, host endian
569 * @packet_space: Remaining space in current packet
570 * @dma_addr: DMA address of current position
571 * @in_len: Remaining length in current SKB fragment
572 * @unmap_len: Length of SKB fragment
573 * @unmap_addr: DMA address of SKB fragment
574 * @unmap_single: DMA single vs page mapping flag
575 * @protocol: Network protocol (after any VLAN header)
576 * @header_len: Number of bytes of header
577 * @full_packet_size: Number of bytes to put in each outgoing segment
578 *
579 * The state used during segmentation. It is put into this data structure
580 * just to make it easy to pass into inline functions.
581 */
582 struct tso_state {
583 /* Output position */
584 unsigned out_len;
585 unsigned seqnum;
586 unsigned ipv4_id;
587 unsigned packet_space;
588
589 /* Input position */
590 dma_addr_t dma_addr;
591 unsigned in_len;
592 unsigned unmap_len;
593 dma_addr_t unmap_addr;
594 bool unmap_single;
595
596 __be16 protocol;
597 unsigned header_len;
598 int full_packet_size;
599 };
600
601
602 /*
603 * Verify that our various assumptions about sk_buffs and the conditions
604 * under which TSO will be attempted hold true. Return the protocol number.
605 */
606 static __be16 efx_tso_check_protocol(struct sk_buff *skb)
607 {
608 __be16 protocol = skb->protocol;
609
610 EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
611 protocol);
612 if (protocol == htons(ETH_P_8021Q)) {
613 /* Find the encapsulated protocol; reset network header
614 * and transport header based on that. */
615 struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
616 protocol = veh->h_vlan_encapsulated_proto;
617 skb_set_network_header(skb, sizeof(*veh));
618 if (protocol == htons(ETH_P_IP))
619 skb_set_transport_header(skb, sizeof(*veh) +
620 4 * ip_hdr(skb)->ihl);
621 else if (protocol == htons(ETH_P_IPV6))
622 skb_set_transport_header(skb, sizeof(*veh) +
623 sizeof(struct ipv6hdr));
624 }
625
626 if (protocol == htons(ETH_P_IP)) {
627 EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
628 } else {
629 EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
630 EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
631 }
632 EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
633 + (tcp_hdr(skb)->doff << 2u)) >
634 skb_headlen(skb));
635
636 return protocol;
637 }
638
639
640 /*
641 * Allocate a page worth of efx_tso_header structures, and string them
642 * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
643 */
644 static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
645 {
646
647 struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
648 struct efx_tso_header *tsoh;
649 dma_addr_t dma_addr;
650 u8 *base_kva, *kva;
651
652 base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
653 if (base_kva == NULL) {
654 netif_err(tx_queue->efx, tx_err, tx_queue->efx->net_dev,
655 "Unable to allocate page for TSO headers\n");
656 return -ENOMEM;
657 }
658
659 /* pci_alloc_consistent() allocates pages. */
660 EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
661
662 for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
663 tsoh = (struct efx_tso_header *)kva;
664 tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
665 tsoh->next = tx_queue->tso_headers_free;
666 tx_queue->tso_headers_free = tsoh;
667 }
668
669 return 0;
670 }
671
672
673 /* Free up a TSO header, and all others in the same page. */
674 static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
675 struct efx_tso_header *tsoh,
676 struct pci_dev *pci_dev)
677 {
678 struct efx_tso_header **p;
679 unsigned long base_kva;
680 dma_addr_t base_dma;
681
682 base_kva = (unsigned long)tsoh & PAGE_MASK;
683 base_dma = tsoh->dma_addr & PAGE_MASK;
684
685 p = &tx_queue->tso_headers_free;
686 while (*p != NULL) {
687 if (((unsigned long)*p & PAGE_MASK) == base_kva)
688 *p = (*p)->next;
689 else
690 p = &(*p)->next;
691 }
692
693 pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
694 }
695
696 static struct efx_tso_header *
697 efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
698 {
699 struct efx_tso_header *tsoh;
700
701 tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
702 if (unlikely(!tsoh))
703 return NULL;
704
705 tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
706 TSOH_BUFFER(tsoh), header_len,
707 PCI_DMA_TODEVICE);
708 if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
709 tsoh->dma_addr))) {
710 kfree(tsoh);
711 return NULL;
712 }
713
714 tsoh->unmap_len = header_len;
715 return tsoh;
716 }
717
718 static void
719 efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
720 {
721 pci_unmap_single(tx_queue->efx->pci_dev,
722 tsoh->dma_addr, tsoh->unmap_len,
723 PCI_DMA_TODEVICE);
724 kfree(tsoh);
725 }
726
727 /**
728 * efx_tx_queue_insert - push descriptors onto the TX queue
729 * @tx_queue: Efx TX queue
730 * @dma_addr: DMA address of fragment
731 * @len: Length of fragment
732 * @final_buffer: The final buffer inserted into the queue
733 *
734 * Push descriptors onto the TX queue. Return 0 on success or 1 if
735 * @tx_queue full.
736 */
737 static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
738 dma_addr_t dma_addr, unsigned len,
739 struct efx_tx_buffer **final_buffer)
740 {
741 struct efx_tx_buffer *buffer;
742 struct efx_nic *efx = tx_queue->efx;
743 unsigned dma_len, fill_level, insert_ptr;
744 int q_space;
745
746 EFX_BUG_ON_PARANOID(len <= 0);
747
748 fill_level = tx_queue->insert_count - tx_queue->old_read_count;
749 /* -1 as there is no way to represent all descriptors used */
750 q_space = efx->txq_entries - 1 - fill_level;
751
752 while (1) {
753 if (unlikely(q_space-- <= 0)) {
754 /* It might be that completions have happened
755 * since the xmit path last checked. Update
756 * the xmit path's copy of read_count.
757 */
758 ++tx_queue->stopped;
759 /* This memory barrier protects the change of
760 * stopped from the access of read_count. */
761 smp_mb();
762 tx_queue->old_read_count =
763 *(volatile unsigned *)&tx_queue->read_count;
764 fill_level = (tx_queue->insert_count
765 - tx_queue->old_read_count);
766 q_space = efx->txq_entries - 1 - fill_level;
767 if (unlikely(q_space-- <= 0)) {
768 *final_buffer = NULL;
769 return 1;
770 }
771 smp_mb();
772 --tx_queue->stopped;
773 }
774
775 insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
776 buffer = &tx_queue->buffer[insert_ptr];
777 ++tx_queue->insert_count;
778
779 EFX_BUG_ON_PARANOID(tx_queue->insert_count -
780 tx_queue->read_count >=
781 efx->txq_entries);
782
783 efx_tsoh_free(tx_queue, buffer);
784 EFX_BUG_ON_PARANOID(buffer->len);
785 EFX_BUG_ON_PARANOID(buffer->unmap_len);
786 EFX_BUG_ON_PARANOID(buffer->skb);
787 EFX_BUG_ON_PARANOID(!buffer->continuation);
788 EFX_BUG_ON_PARANOID(buffer->tsoh);
789
790 buffer->dma_addr = dma_addr;
791
792 dma_len = efx_max_tx_len(efx, dma_addr);
793
794 /* If there is enough space to send then do so */
795 if (dma_len >= len)
796 break;
797
798 buffer->len = dma_len; /* Don't set the other members */
799 dma_addr += dma_len;
800 len -= dma_len;
801 }
802
803 EFX_BUG_ON_PARANOID(!len);
804 buffer->len = len;
805 *final_buffer = buffer;
806 return 0;
807 }
808
809
810 /*
811 * Put a TSO header into the TX queue.
812 *
813 * This is special-cased because we know that it is small enough to fit in
814 * a single fragment, and we know it doesn't cross a page boundary. It
815 * also allows us to not worry about end-of-packet etc.
816 */
817 static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
818 struct efx_tso_header *tsoh, unsigned len)
819 {
820 struct efx_tx_buffer *buffer;
821
822 buffer = &tx_queue->buffer[tx_queue->insert_count & tx_queue->ptr_mask];
823 efx_tsoh_free(tx_queue, buffer);
824 EFX_BUG_ON_PARANOID(buffer->len);
825 EFX_BUG_ON_PARANOID(buffer->unmap_len);
826 EFX_BUG_ON_PARANOID(buffer->skb);
827 EFX_BUG_ON_PARANOID(!buffer->continuation);
828 EFX_BUG_ON_PARANOID(buffer->tsoh);
829 buffer->len = len;
830 buffer->dma_addr = tsoh->dma_addr;
831 buffer->tsoh = tsoh;
832
833 ++tx_queue->insert_count;
834 }
835
836
837 /* Remove descriptors put into a tx_queue. */
838 static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
839 {
840 struct efx_tx_buffer *buffer;
841 dma_addr_t unmap_addr;
842
843 /* Work backwards until we hit the original insert pointer value */
844 while (tx_queue->insert_count != tx_queue->write_count) {
845 --tx_queue->insert_count;
846 buffer = &tx_queue->buffer[tx_queue->insert_count &
847 tx_queue->ptr_mask];
848 efx_tsoh_free(tx_queue, buffer);
849 EFX_BUG_ON_PARANOID(buffer->skb);
850 if (buffer->unmap_len) {
851 unmap_addr = (buffer->dma_addr + buffer->len -
852 buffer->unmap_len);
853 if (buffer->unmap_single)
854 pci_unmap_single(tx_queue->efx->pci_dev,
855 unmap_addr, buffer->unmap_len,
856 PCI_DMA_TODEVICE);
857 else
858 pci_unmap_page(tx_queue->efx->pci_dev,
859 unmap_addr, buffer->unmap_len,
860 PCI_DMA_TODEVICE);
861 buffer->unmap_len = 0;
862 }
863 buffer->len = 0;
864 buffer->continuation = true;
865 }
866 }
867
868
869 /* Parse the SKB header and initialise state. */
870 static void tso_start(struct tso_state *st, const struct sk_buff *skb)
871 {
872 /* All ethernet/IP/TCP headers combined size is TCP header size
873 * plus offset of TCP header relative to start of packet.
874 */
875 st->header_len = ((tcp_hdr(skb)->doff << 2u)
876 + PTR_DIFF(tcp_hdr(skb), skb->data));
877 st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
878
879 if (st->protocol == htons(ETH_P_IP))
880 st->ipv4_id = ntohs(ip_hdr(skb)->id);
881 else
882 st->ipv4_id = 0;
883 st->seqnum = ntohl(tcp_hdr(skb)->seq);
884
885 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
886 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
887 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
888
889 st->packet_space = st->full_packet_size;
890 st->out_len = skb->len - st->header_len;
891 st->unmap_len = 0;
892 st->unmap_single = false;
893 }
894
895 static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
896 skb_frag_t *frag)
897 {
898 st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
899 frag->page_offset, frag->size,
900 PCI_DMA_TODEVICE);
901 if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
902 st->unmap_single = false;
903 st->unmap_len = frag->size;
904 st->in_len = frag->size;
905 st->dma_addr = st->unmap_addr;
906 return 0;
907 }
908 return -ENOMEM;
909 }
910
911 static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
912 const struct sk_buff *skb)
913 {
914 int hl = st->header_len;
915 int len = skb_headlen(skb) - hl;
916
917 st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
918 len, PCI_DMA_TODEVICE);
919 if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
920 st->unmap_single = true;
921 st->unmap_len = len;
922 st->in_len = len;
923 st->dma_addr = st->unmap_addr;
924 return 0;
925 }
926 return -ENOMEM;
927 }
928
929
930 /**
931 * tso_fill_packet_with_fragment - form descriptors for the current fragment
932 * @tx_queue: Efx TX queue
933 * @skb: Socket buffer
934 * @st: TSO state
935 *
936 * Form descriptors for the current fragment, until we reach the end
937 * of fragment or end-of-packet. Return 0 on success, 1 if not enough
938 * space in @tx_queue.
939 */
940 static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
941 const struct sk_buff *skb,
942 struct tso_state *st)
943 {
944 struct efx_tx_buffer *buffer;
945 int n, end_of_packet, rc;
946
947 if (st->in_len == 0)
948 return 0;
949 if (st->packet_space == 0)
950 return 0;
951
952 EFX_BUG_ON_PARANOID(st->in_len <= 0);
953 EFX_BUG_ON_PARANOID(st->packet_space <= 0);
954
955 n = min(st->in_len, st->packet_space);
956
957 st->packet_space -= n;
958 st->out_len -= n;
959 st->in_len -= n;
960
961 rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
962 if (likely(rc == 0)) {
963 if (st->out_len == 0)
964 /* Transfer ownership of the skb */
965 buffer->skb = skb;
966
967 end_of_packet = st->out_len == 0 || st->packet_space == 0;
968 buffer->continuation = !end_of_packet;
969
970 if (st->in_len == 0) {
971 /* Transfer ownership of the pci mapping */
972 buffer->unmap_len = st->unmap_len;
973 buffer->unmap_single = st->unmap_single;
974 st->unmap_len = 0;
975 }
976 }
977
978 st->dma_addr += n;
979 return rc;
980 }
981
982
983 /**
984 * tso_start_new_packet - generate a new header and prepare for the new packet
985 * @tx_queue: Efx TX queue
986 * @skb: Socket buffer
987 * @st: TSO state
988 *
989 * Generate a new header and prepare for the new packet. Return 0 on
990 * success, or -1 if failed to alloc header.
991 */
992 static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
993 const struct sk_buff *skb,
994 struct tso_state *st)
995 {
996 struct efx_tso_header *tsoh;
997 struct tcphdr *tsoh_th;
998 unsigned ip_length;
999 u8 *header;
1000
1001 /* Allocate a DMA-mapped header buffer. */
1002 if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
1003 if (tx_queue->tso_headers_free == NULL) {
1004 if (efx_tsoh_block_alloc(tx_queue))
1005 return -1;
1006 }
1007 EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
1008 tsoh = tx_queue->tso_headers_free;
1009 tx_queue->tso_headers_free = tsoh->next;
1010 tsoh->unmap_len = 0;
1011 } else {
1012 tx_queue->tso_long_headers++;
1013 tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
1014 if (unlikely(!tsoh))
1015 return -1;
1016 }
1017
1018 header = TSOH_BUFFER(tsoh);
1019 tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
1020
1021 /* Copy and update the headers. */
1022 memcpy(header, skb->data, st->header_len);
1023
1024 tsoh_th->seq = htonl(st->seqnum);
1025 st->seqnum += skb_shinfo(skb)->gso_size;
1026 if (st->out_len > skb_shinfo(skb)->gso_size) {
1027 /* This packet will not finish the TSO burst. */
1028 ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
1029 tsoh_th->fin = 0;
1030 tsoh_th->psh = 0;
1031 } else {
1032 /* This packet will be the last in the TSO burst. */
1033 ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
1034 tsoh_th->fin = tcp_hdr(skb)->fin;
1035 tsoh_th->psh = tcp_hdr(skb)->psh;
1036 }
1037
1038 if (st->protocol == htons(ETH_P_IP)) {
1039 struct iphdr *tsoh_iph =
1040 (struct iphdr *)(header + SKB_IPV4_OFF(skb));
1041
1042 tsoh_iph->tot_len = htons(ip_length);
1043
1044 /* Linux leaves suitable gaps in the IP ID space for us to fill. */
1045 tsoh_iph->id = htons(st->ipv4_id);
1046 st->ipv4_id++;
1047 } else {
1048 struct ipv6hdr *tsoh_iph =
1049 (struct ipv6hdr *)(header + SKB_IPV6_OFF(skb));
1050
1051 tsoh_iph->payload_len = htons(ip_length - sizeof(*tsoh_iph));
1052 }
1053
1054 st->packet_space = skb_shinfo(skb)->gso_size;
1055 ++tx_queue->tso_packets;
1056
1057 /* Form a descriptor for this header. */
1058 efx_tso_put_header(tx_queue, tsoh, st->header_len);
1059
1060 return 0;
1061 }
1062
1063
1064 /**
1065 * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
1066 * @tx_queue: Efx TX queue
1067 * @skb: Socket buffer
1068 *
1069 * Context: You must hold netif_tx_lock() to call this function.
1070 *
1071 * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
1072 * @skb was not enqueued. In all cases @skb is consumed. Return
1073 * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
1074 */
1075 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
1076 struct sk_buff *skb)
1077 {
1078 struct efx_nic *efx = tx_queue->efx;
1079 int frag_i, rc, rc2 = NETDEV_TX_OK;
1080 struct tso_state state;
1081
1082 /* Find the packet protocol and sanity-check it */
1083 state.protocol = efx_tso_check_protocol(skb);
1084
1085 EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
1086
1087 tso_start(&state, skb);
1088
1089 /* Assume that skb header area contains exactly the headers, and
1090 * all payload is in the frag list.
1091 */
1092 if (skb_headlen(skb) == state.header_len) {
1093 /* Grab the first payload fragment. */
1094 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
1095 frag_i = 0;
1096 rc = tso_get_fragment(&state, efx,
1097 skb_shinfo(skb)->frags + frag_i);
1098 if (rc)
1099 goto mem_err;
1100 } else {
1101 rc = tso_get_head_fragment(&state, efx, skb);
1102 if (rc)
1103 goto mem_err;
1104 frag_i = -1;
1105 }
1106
1107 if (tso_start_new_packet(tx_queue, skb, &state) < 0)
1108 goto mem_err;
1109
1110 while (1) {
1111 rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
1112 if (unlikely(rc))
1113 goto stop;
1114
1115 /* Move onto the next fragment? */
1116 if (state.in_len == 0) {
1117 if (++frag_i >= skb_shinfo(skb)->nr_frags)
1118 /* End of payload reached. */
1119 break;
1120 rc = tso_get_fragment(&state, efx,
1121 skb_shinfo(skb)->frags + frag_i);
1122 if (rc)
1123 goto mem_err;
1124 }
1125
1126 /* Start at new packet? */
1127 if (state.packet_space == 0 &&
1128 tso_start_new_packet(tx_queue, skb, &state) < 0)
1129 goto mem_err;
1130 }
1131
1132 /* Pass off to hardware */
1133 efx_nic_push_buffers(tx_queue);
1134
1135 tx_queue->tso_bursts++;
1136 return NETDEV_TX_OK;
1137
1138 mem_err:
1139 netif_err(efx, tx_err, efx->net_dev,
1140 "Out of memory for TSO headers, or PCI mapping error\n");
1141 dev_kfree_skb_any(skb);
1142 goto unwind;
1143
1144 stop:
1145 rc2 = NETDEV_TX_BUSY;
1146
1147 /* Stop the queue if it wasn't stopped before. */
1148 if (tx_queue->stopped == 1)
1149 efx_stop_queue(tx_queue->channel);
1150
1151 unwind:
1152 /* Free the DMA mapping we were in the process of writing out */
1153 if (state.unmap_len) {
1154 if (state.unmap_single)
1155 pci_unmap_single(efx->pci_dev, state.unmap_addr,
1156 state.unmap_len, PCI_DMA_TODEVICE);
1157 else
1158 pci_unmap_page(efx->pci_dev, state.unmap_addr,
1159 state.unmap_len, PCI_DMA_TODEVICE);
1160 }
1161
1162 efx_enqueue_unwind(tx_queue);
1163 return rc2;
1164 }
1165
1166
1167 /*
1168 * Free up all TSO datastructures associated with tx_queue. This
1169 * routine should be called only once the tx_queue is both empty and
1170 * will no longer be used.
1171 */
1172 static void efx_fini_tso(struct efx_tx_queue *tx_queue)
1173 {
1174 unsigned i;
1175
1176 if (tx_queue->buffer) {
1177 for (i = 0; i <= tx_queue->ptr_mask; ++i)
1178 efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
1179 }
1180
1181 while (tx_queue->tso_headers_free != NULL)
1182 efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
1183 tx_queue->efx->pci_dev);
1184 }
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