drivers/net/sfc/xfp_phy.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2006-2008 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9 /*
  10  * Driver for SFP+ and XFP optical PHYs plus some support specific to the
  11  * AMCC QT20xx adapters; see www.amcc.com for details
  12  */
  13
  14 #include <linux/timer.h>
  15 #include <linux/delay.h>
  16 #include "efx.h"
  17 #include "mdio_10g.h"
  18 #include "xenpack.h"
  19 #include "phy.h"
  20 #include "falcon.h"
  21
  22 #define XFP_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PCS |       \
  23                            MDIO_MMDREG_DEVS_PMAPMD |    \
  24                            MDIO_MMDREG_DEVS_PHYXS)
  25
  26 #define XFP_LOOPBACKS ((1 << LOOPBACK_PCS) |            \
  27                        (1 << LOOPBACK_PMAPMD) |         \
  28                        (1 << LOOPBACK_NETWORK))
  29
  30 /****************************************************************************/
  31 /* Quake-specific MDIO registers */
  32 #define MDIO_QUAKE_LED0_REG     (0xD006)
  33
  34 /* QT2025C only */
  35 #define PCS_FW_HEARTBEAT_REG    0xd7ee
  36 #define PCS_FW_HEARTB_LBN       0
  37 #define PCS_FW_HEARTB_WIDTH     8
  38 #define PCS_UC8051_STATUS_REG   0xd7fd
  39 #define PCS_UC_STATUS_LBN       0
  40 #define PCS_UC_STATUS_WIDTH     8
  41 #define PCS_UC_STATUS_FW_SAVE   0x20
  42 #define PMA_PMD_FTX_CTRL2_REG   0xc309
  43 #define PMA_PMD_FTX_STATIC_LBN  13
  44 #define PMA_PMD_VEND1_REG       0xc001
  45 #define PMA_PMD_VEND1_LBTXD_LBN 15
  46 #define PCS_VEND1_REG           0xc000
  47 #define PCS_VEND1_LBTXD_LBN     5
  48
  49 void xfp_set_led(struct efx_nic *p, int led, int mode)
  50 {
  51         int addr = MDIO_QUAKE_LED0_REG + led;
  52         mdio_clause45_write(p, p->mii.phy_id, MDIO_MMD_PMAPMD, addr,
  53                             mode);
  54 }
  55
  56 struct xfp_phy_data {
  57         enum efx_phy_mode phy_mode;
  58 };
  59
  60 #define XFP_MAX_RESET_TIME 500
  61 #define XFP_RESET_WAIT 10
  62
  63 static int qt2025c_wait_reset(struct efx_nic *efx)
  64 {
  65         unsigned long timeout = jiffies + 10 * HZ;
  66         int phy_id = efx->mii.phy_id;
  67         int reg, old_counter = 0;
  68
  69         /* Wait for firmware heartbeat to start */
  70         for (;;) {
  71                 int counter;
  72                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
  73                                          PCS_FW_HEARTBEAT_REG);
  74                 if (reg < 0)
  75                         return reg;
  76                 counter = ((reg >> PCS_FW_HEARTB_LBN) &
  77                             ((1 << PCS_FW_HEARTB_WIDTH) - 1));
  78                 if (old_counter == 0)
  79                         old_counter = counter;
  80                 else if (counter != old_counter)
  81                         break;
  82                 if (time_after(jiffies, timeout))
  83                         return -ETIMEDOUT;
  84                 msleep(10);
  85         }
  86
  87         /* Wait for firmware status to look good */
  88         for (;;) {
  89                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
  90                                          PCS_UC8051_STATUS_REG);
  91                 if (reg < 0)
  92                         return reg;
  93                 if ((reg &
  94                      ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
  95                     PCS_UC_STATUS_FW_SAVE)
  96                         break;
  97                 if (time_after(jiffies, timeout))
  98                         return -ETIMEDOUT;
  99                 msleep(100);
 100         }
 101
 102         return 0;
 103 }
 104
 105 /* Reset the PHYXS MMD. This is documented (for the Quake PHYs) as doing
 106  * a complete soft reset.
 107  */
 108 static int xfp_reset_phy(struct efx_nic *efx)
 109 {
 110         int rc;
 111
 112         rc = mdio_clause45_reset_mmd(efx, MDIO_MMD_PHYXS,
 113                                      XFP_MAX_RESET_TIME / XFP_RESET_WAIT,
 114                                      XFP_RESET_WAIT);
 115         if (rc < 0)
 116                 goto fail;
 117
 118         if (efx->phy_type == PHY_TYPE_QT2025C) {
 119                 rc = qt2025c_wait_reset(efx);
 120                 if (rc < 0)
 121                         goto fail;
 122         }
 123
 124         /* Wait 250ms for the PHY to complete bootup */
 125         msleep(250);
 126
 127         /* Check that all the MMDs we expect are present and responding. We
 128          * expect faults on some if the link is down, but not on the PHY XS */
 129         rc = mdio_clause45_check_mmds(efx, XFP_REQUIRED_DEVS,
 130                                       MDIO_MMDREG_DEVS_PHYXS);
 131         if (rc < 0)
 132                 goto fail;
 133
 134         efx->board_info.init_leds(efx);
 135
 136         return rc;
 137
 138  fail:
 139         EFX_ERR(efx, "PHY reset timed out\n");
 140         return rc;
 141 }
 142
 143 static int xfp_phy_init(struct efx_nic *efx)
 144 {
 145         struct xfp_phy_data *phy_data;
 146         u32 devid = mdio_clause45_read_id(efx, MDIO_MMD_PHYXS);
 147         int rc;
 148
 149         phy_data = kzalloc(sizeof(struct xfp_phy_data), GFP_KERNEL);
 150         if (!phy_data)
 151                 return -ENOMEM;
 152         efx->phy_data = phy_data;
 153
 154         EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
 155                  devid, mdio_id_oui(devid), mdio_id_model(devid),
 156                  mdio_id_rev(devid));
 157
 158         phy_data->phy_mode = efx->phy_mode;
 159
 160         rc = xfp_reset_phy(efx);
 161
 162         EFX_INFO(efx, "PHY init %s.\n",
 163                  rc ? "failed" : "successful");
 164         if (rc < 0)
 165                 goto fail;
 166
 167         return 0;
 168
 169  fail:
 170         kfree(efx->phy_data);
 171         efx->phy_data = NULL;
 172         return rc;
 173 }
 174
 175 static void xfp_phy_clear_interrupt(struct efx_nic *efx)
 176 {
 177         xenpack_clear_lasi_irqs(efx);
 178 }
 179
 180 static int xfp_link_ok(struct efx_nic *efx)
 181 {
 182         return mdio_clause45_links_ok(efx, XFP_REQUIRED_DEVS);
 183 }
 184
 185 static void xfp_phy_poll(struct efx_nic *efx)
 186 {
 187         int link_up = xfp_link_ok(efx);
 188         /* Simulate a PHY event if link state has changed */
 189         if (link_up != efx->link_up)
 190                 falcon_sim_phy_event(efx);
 191 }
 192
 193 static void xfp_phy_reconfigure(struct efx_nic *efx)
 194 {
 195         struct xfp_phy_data *phy_data = efx->phy_data;
 196
 197         if (efx->phy_type == PHY_TYPE_QT2025C) {
 198                 /* There are several different register bits which can
 199                  * disable TX (and save power) on direct-attach cables
 200                  * or optical transceivers, varying somewhat between
 201                  * firmware versions.  Only 'static mode' appears to
 202                  * cover everything. */
 203                 mdio_clause45_set_flag(
 204                         efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 205                         PMA_PMD_FTX_CTRL2_REG, PMA_PMD_FTX_STATIC_LBN,
 206                         efx->phy_mode & PHY_MODE_TX_DISABLED ||
 207                         efx->phy_mode & PHY_MODE_LOW_POWER ||
 208                         efx->loopback_mode == LOOPBACK_PCS ||
 209                         efx->loopback_mode == LOOPBACK_PMAPMD);
 210         } else {
 211                 /* Reset the PHY when moving from tx off to tx on */
 212                 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
 213                     (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
 214                         xfp_reset_phy(efx);
 215
 216                 mdio_clause45_transmit_disable(efx);
 217         }
 218
 219         mdio_clause45_phy_reconfigure(efx);
 220
 221         phy_data->phy_mode = efx->phy_mode;
 222         efx->link_up = xfp_link_ok(efx);
 223         efx->link_speed = 10000;
 224         efx->link_fd = true;
 225         efx->link_fc = efx->wanted_fc;
 226 }
 227
 228
 229 static void xfp_phy_fini(struct efx_nic *efx)
 230 {
 231         /* Clobber the LED if it was blinking */
 232         efx->board_info.blink(efx, false);
 233
 234         /* Free the context block */
 235         kfree(efx->phy_data);
 236         efx->phy_data = NULL;
 237 }
 238
 239 struct efx_phy_operations falcon_xfp_phy_ops = {
 240         .macs            = EFX_XMAC,
 241         .init            = xfp_phy_init,
 242         .reconfigure     = xfp_phy_reconfigure,
 243         .poll            = xfp_phy_poll,
 244         .fini            = xfp_phy_fini,
 245         .clear_interrupt = xfp_phy_clear_interrupt,
 246         .get_settings    = mdio_clause45_get_settings,
 247         .set_settings    = mdio_clause45_set_settings,
 248         .mmds            = XFP_REQUIRED_DEVS,
 249         .loopbacks       = XFP_LOOPBACKS,
 250 };