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sh: sh_eth: Add support ethtool
[deliverable/linux.git] / drivers / net / sh_eth.c
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
32 #include <linux/io.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/slab.h>
35 #include <linux/ethtool.h>
36 #include <asm/cacheflush.h>
37
38 #include "sh_eth.h"
39
40 #define SH_ETH_DEF_MSG_ENABLE \
41 (NETIF_MSG_LINK | \
42 NETIF_MSG_TIMER | \
43 NETIF_MSG_RX_ERR| \
44 NETIF_MSG_TX_ERR)
45
46 /* There is CPU dependent code */
47 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
48 #define SH_ETH_RESET_DEFAULT 1
49 static void sh_eth_set_duplex(struct net_device *ndev)
50 {
51 struct sh_eth_private *mdp = netdev_priv(ndev);
52 u32 ioaddr = ndev->base_addr;
53
54 if (mdp->duplex) /* Full */
55 writel(readl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
56 else /* Half */
57 writel(readl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
58 }
59
60 static void sh_eth_set_rate(struct net_device *ndev)
61 {
62 struct sh_eth_private *mdp = netdev_priv(ndev);
63 u32 ioaddr = ndev->base_addr;
64
65 switch (mdp->speed) {
66 case 10: /* 10BASE */
67 writel(readl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
68 break;
69 case 100:/* 100BASE */
70 writel(readl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
71 break;
72 default:
73 break;
74 }
75 }
76
77 /* SH7724 */
78 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
79 .set_duplex = sh_eth_set_duplex,
80 .set_rate = sh_eth_set_rate,
81
82 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
83 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
84 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
85
86 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
87 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
88 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
89 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
90
91 .apr = 1,
92 .mpr = 1,
93 .tpauser = 1,
94 .hw_swap = 1,
95 .rpadir = 1,
96 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
97 };
98 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
99 #define SH_ETH_RESET_DEFAULT 1
100 static void sh_eth_set_duplex(struct net_device *ndev)
101 {
102 struct sh_eth_private *mdp = netdev_priv(ndev);
103 u32 ioaddr = ndev->base_addr;
104
105 if (mdp->duplex) /* Full */
106 writel(readl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
107 else /* Half */
108 writel(readl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
109 }
110
111 static void sh_eth_set_rate(struct net_device *ndev)
112 {
113 struct sh_eth_private *mdp = netdev_priv(ndev);
114 u32 ioaddr = ndev->base_addr;
115
116 switch (mdp->speed) {
117 case 10: /* 10BASE */
118 writel(0, ioaddr + RTRATE);
119 break;
120 case 100:/* 100BASE */
121 writel(1, ioaddr + RTRATE);
122 break;
123 default:
124 break;
125 }
126 }
127
128 /* SH7757 */
129 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
130 .set_duplex = sh_eth_set_duplex,
131 .set_rate = sh_eth_set_rate,
132
133 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
134 .rmcr_value = 0x00000001,
135
136 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
137 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
138 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
139 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
140
141 .apr = 1,
142 .mpr = 1,
143 .tpauser = 1,
144 .hw_swap = 1,
145 .no_ade = 1,
146 };
147
148 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
149 #define SH_ETH_HAS_TSU 1
150 static void sh_eth_chip_reset(struct net_device *ndev)
151 {
152 /* reset device */
153 writel(ARSTR_ARSTR, ARSTR);
154 mdelay(1);
155 }
156
157 static void sh_eth_reset(struct net_device *ndev)
158 {
159 u32 ioaddr = ndev->base_addr;
160 int cnt = 100;
161
162 writel(EDSR_ENALL, ioaddr + EDSR);
163 writel(readl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
164 while (cnt > 0) {
165 if (!(readl(ioaddr + EDMR) & 0x3))
166 break;
167 mdelay(1);
168 cnt--;
169 }
170 if (cnt == 0)
171 printk(KERN_ERR "Device reset fail\n");
172
173 /* Table Init */
174 writel(0x0, ioaddr + TDLAR);
175 writel(0x0, ioaddr + TDFAR);
176 writel(0x0, ioaddr + TDFXR);
177 writel(0x0, ioaddr + TDFFR);
178 writel(0x0, ioaddr + RDLAR);
179 writel(0x0, ioaddr + RDFAR);
180 writel(0x0, ioaddr + RDFXR);
181 writel(0x0, ioaddr + RDFFR);
182 }
183
184 static void sh_eth_set_duplex(struct net_device *ndev)
185 {
186 struct sh_eth_private *mdp = netdev_priv(ndev);
187 u32 ioaddr = ndev->base_addr;
188
189 if (mdp->duplex) /* Full */
190 writel(readl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
191 else /* Half */
192 writel(readl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
193 }
194
195 static void sh_eth_set_rate(struct net_device *ndev)
196 {
197 struct sh_eth_private *mdp = netdev_priv(ndev);
198 u32 ioaddr = ndev->base_addr;
199
200 switch (mdp->speed) {
201 case 10: /* 10BASE */
202 writel(GECMR_10, ioaddr + GECMR);
203 break;
204 case 100:/* 100BASE */
205 writel(GECMR_100, ioaddr + GECMR);
206 break;
207 case 1000: /* 1000BASE */
208 writel(GECMR_1000, ioaddr + GECMR);
209 break;
210 default:
211 break;
212 }
213 }
214
215 /* sh7763 */
216 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
217 .chip_reset = sh_eth_chip_reset,
218 .set_duplex = sh_eth_set_duplex,
219 .set_rate = sh_eth_set_rate,
220
221 .ecsr_value = ECSR_ICD | ECSR_MPD,
222 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
223 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
224
225 .tx_check = EESR_TC1 | EESR_FTC,
226 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
227 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
228 EESR_ECI,
229 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
230 EESR_TFE,
231
232 .apr = 1,
233 .mpr = 1,
234 .tpauser = 1,
235 .bculr = 1,
236 .hw_swap = 1,
237 .no_trimd = 1,
238 .no_ade = 1,
239 };
240
241 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
242 #define SH_ETH_RESET_DEFAULT 1
243 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
244 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
245
246 .apr = 1,
247 .mpr = 1,
248 .tpauser = 1,
249 .hw_swap = 1,
250 };
251 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
252 #define SH_ETH_RESET_DEFAULT 1
253 #define SH_ETH_HAS_TSU 1
254 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
255 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
256 };
257 #endif
258
259 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
260 {
261 if (!cd->ecsr_value)
262 cd->ecsr_value = DEFAULT_ECSR_INIT;
263
264 if (!cd->ecsipr_value)
265 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
266
267 if (!cd->fcftr_value)
268 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
269 DEFAULT_FIFO_F_D_RFD;
270
271 if (!cd->fdr_value)
272 cd->fdr_value = DEFAULT_FDR_INIT;
273
274 if (!cd->rmcr_value)
275 cd->rmcr_value = DEFAULT_RMCR_VALUE;
276
277 if (!cd->tx_check)
278 cd->tx_check = DEFAULT_TX_CHECK;
279
280 if (!cd->eesr_err_check)
281 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
282
283 if (!cd->tx_error_check)
284 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
285 }
286
287 #if defined(SH_ETH_RESET_DEFAULT)
288 /* Chip Reset */
289 static void sh_eth_reset(struct net_device *ndev)
290 {
291 u32 ioaddr = ndev->base_addr;
292
293 writel(readl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
294 mdelay(3);
295 writel(readl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
296 }
297 #endif
298
299 #if defined(CONFIG_CPU_SH4)
300 static void sh_eth_set_receive_align(struct sk_buff *skb)
301 {
302 int reserve;
303
304 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
305 if (reserve)
306 skb_reserve(skb, reserve);
307 }
308 #else
309 static void sh_eth_set_receive_align(struct sk_buff *skb)
310 {
311 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
312 }
313 #endif
314
315
316 /* CPU <-> EDMAC endian convert */
317 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
318 {
319 switch (mdp->edmac_endian) {
320 case EDMAC_LITTLE_ENDIAN:
321 return cpu_to_le32(x);
322 case EDMAC_BIG_ENDIAN:
323 return cpu_to_be32(x);
324 }
325 return x;
326 }
327
328 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
329 {
330 switch (mdp->edmac_endian) {
331 case EDMAC_LITTLE_ENDIAN:
332 return le32_to_cpu(x);
333 case EDMAC_BIG_ENDIAN:
334 return be32_to_cpu(x);
335 }
336 return x;
337 }
338
339 /*
340 * Program the hardware MAC address from dev->dev_addr.
341 */
342 static void update_mac_address(struct net_device *ndev)
343 {
344 u32 ioaddr = ndev->base_addr;
345
346 writel((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
347 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
348 ioaddr + MAHR);
349 writel((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
350 ioaddr + MALR);
351 }
352
353 /*
354 * Get MAC address from SuperH MAC address register
355 *
356 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
357 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
358 * When you want use this device, you must set MAC address in bootloader.
359 *
360 */
361 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
362 {
363 u32 ioaddr = ndev->base_addr;
364
365 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
366 memcpy(ndev->dev_addr, mac, 6);
367 } else {
368 ndev->dev_addr[0] = (readl(ioaddr + MAHR) >> 24);
369 ndev->dev_addr[1] = (readl(ioaddr + MAHR) >> 16) & 0xFF;
370 ndev->dev_addr[2] = (readl(ioaddr + MAHR) >> 8) & 0xFF;
371 ndev->dev_addr[3] = (readl(ioaddr + MAHR) & 0xFF);
372 ndev->dev_addr[4] = (readl(ioaddr + MALR) >> 8) & 0xFF;
373 ndev->dev_addr[5] = (readl(ioaddr + MALR) & 0xFF);
374 }
375 }
376
377 struct bb_info {
378 struct mdiobb_ctrl ctrl;
379 u32 addr;
380 u32 mmd_msk;/* MMD */
381 u32 mdo_msk;
382 u32 mdi_msk;
383 u32 mdc_msk;
384 };
385
386 /* PHY bit set */
387 static void bb_set(u32 addr, u32 msk)
388 {
389 writel(readl(addr) | msk, addr);
390 }
391
392 /* PHY bit clear */
393 static void bb_clr(u32 addr, u32 msk)
394 {
395 writel((readl(addr) & ~msk), addr);
396 }
397
398 /* PHY bit read */
399 static int bb_read(u32 addr, u32 msk)
400 {
401 return (readl(addr) & msk) != 0;
402 }
403
404 /* Data I/O pin control */
405 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
406 {
407 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
408 if (bit)
409 bb_set(bitbang->addr, bitbang->mmd_msk);
410 else
411 bb_clr(bitbang->addr, bitbang->mmd_msk);
412 }
413
414 /* Set bit data*/
415 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
416 {
417 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
418
419 if (bit)
420 bb_set(bitbang->addr, bitbang->mdo_msk);
421 else
422 bb_clr(bitbang->addr, bitbang->mdo_msk);
423 }
424
425 /* Get bit data*/
426 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
427 {
428 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
429 return bb_read(bitbang->addr, bitbang->mdi_msk);
430 }
431
432 /* MDC pin control */
433 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
434 {
435 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
436
437 if (bit)
438 bb_set(bitbang->addr, bitbang->mdc_msk);
439 else
440 bb_clr(bitbang->addr, bitbang->mdc_msk);
441 }
442
443 /* mdio bus control struct */
444 static struct mdiobb_ops bb_ops = {
445 .owner = THIS_MODULE,
446 .set_mdc = sh_mdc_ctrl,
447 .set_mdio_dir = sh_mmd_ctrl,
448 .set_mdio_data = sh_set_mdio,
449 .get_mdio_data = sh_get_mdio,
450 };
451
452 /* free skb and descriptor buffer */
453 static void sh_eth_ring_free(struct net_device *ndev)
454 {
455 struct sh_eth_private *mdp = netdev_priv(ndev);
456 int i;
457
458 /* Free Rx skb ringbuffer */
459 if (mdp->rx_skbuff) {
460 for (i = 0; i < RX_RING_SIZE; i++) {
461 if (mdp->rx_skbuff[i])
462 dev_kfree_skb(mdp->rx_skbuff[i]);
463 }
464 }
465 kfree(mdp->rx_skbuff);
466
467 /* Free Tx skb ringbuffer */
468 if (mdp->tx_skbuff) {
469 for (i = 0; i < TX_RING_SIZE; i++) {
470 if (mdp->tx_skbuff[i])
471 dev_kfree_skb(mdp->tx_skbuff[i]);
472 }
473 }
474 kfree(mdp->tx_skbuff);
475 }
476
477 /* format skb and descriptor buffer */
478 static void sh_eth_ring_format(struct net_device *ndev)
479 {
480 u32 ioaddr = ndev->base_addr;
481 struct sh_eth_private *mdp = netdev_priv(ndev);
482 int i;
483 struct sk_buff *skb;
484 struct sh_eth_rxdesc *rxdesc = NULL;
485 struct sh_eth_txdesc *txdesc = NULL;
486 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
487 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
488
489 mdp->cur_rx = mdp->cur_tx = 0;
490 mdp->dirty_rx = mdp->dirty_tx = 0;
491
492 memset(mdp->rx_ring, 0, rx_ringsize);
493
494 /* build Rx ring buffer */
495 for (i = 0; i < RX_RING_SIZE; i++) {
496 /* skb */
497 mdp->rx_skbuff[i] = NULL;
498 skb = dev_alloc_skb(mdp->rx_buf_sz);
499 mdp->rx_skbuff[i] = skb;
500 if (skb == NULL)
501 break;
502 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
503 DMA_FROM_DEVICE);
504 skb->dev = ndev; /* Mark as being used by this device. */
505 sh_eth_set_receive_align(skb);
506
507 /* RX descriptor */
508 rxdesc = &mdp->rx_ring[i];
509 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
510 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
511
512 /* The size of the buffer is 16 byte boundary. */
513 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
514 /* Rx descriptor address set */
515 if (i == 0) {
516 writel(mdp->rx_desc_dma, ioaddr + RDLAR);
517 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
518 writel(mdp->rx_desc_dma, ioaddr + RDFAR);
519 #endif
520 }
521 }
522
523 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
524
525 /* Mark the last entry as wrapping the ring. */
526 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
527
528 memset(mdp->tx_ring, 0, tx_ringsize);
529
530 /* build Tx ring buffer */
531 for (i = 0; i < TX_RING_SIZE; i++) {
532 mdp->tx_skbuff[i] = NULL;
533 txdesc = &mdp->tx_ring[i];
534 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
535 txdesc->buffer_length = 0;
536 if (i == 0) {
537 /* Tx descriptor address set */
538 writel(mdp->tx_desc_dma, ioaddr + TDLAR);
539 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
540 writel(mdp->tx_desc_dma, ioaddr + TDFAR);
541 #endif
542 }
543 }
544
545 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
546 }
547
548 /* Get skb and descriptor buffer */
549 static int sh_eth_ring_init(struct net_device *ndev)
550 {
551 struct sh_eth_private *mdp = netdev_priv(ndev);
552 int rx_ringsize, tx_ringsize, ret = 0;
553
554 /*
555 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
556 * card needs room to do 8 byte alignment, +2 so we can reserve
557 * the first 2 bytes, and +16 gets room for the status word from the
558 * card.
559 */
560 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
561 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
562 if (mdp->cd->rpadir)
563 mdp->rx_buf_sz += NET_IP_ALIGN;
564
565 /* Allocate RX and TX skb rings */
566 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
567 GFP_KERNEL);
568 if (!mdp->rx_skbuff) {
569 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
570 ret = -ENOMEM;
571 return ret;
572 }
573
574 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
575 GFP_KERNEL);
576 if (!mdp->tx_skbuff) {
577 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
578 ret = -ENOMEM;
579 goto skb_ring_free;
580 }
581
582 /* Allocate all Rx descriptors. */
583 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
584 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
585 GFP_KERNEL);
586
587 if (!mdp->rx_ring) {
588 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
589 rx_ringsize);
590 ret = -ENOMEM;
591 goto desc_ring_free;
592 }
593
594 mdp->dirty_rx = 0;
595
596 /* Allocate all Tx descriptors. */
597 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
598 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
599 GFP_KERNEL);
600 if (!mdp->tx_ring) {
601 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
602 tx_ringsize);
603 ret = -ENOMEM;
604 goto desc_ring_free;
605 }
606 return ret;
607
608 desc_ring_free:
609 /* free DMA buffer */
610 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
611
612 skb_ring_free:
613 /* Free Rx and Tx skb ring buffer */
614 sh_eth_ring_free(ndev);
615
616 return ret;
617 }
618
619 static int sh_eth_dev_init(struct net_device *ndev)
620 {
621 int ret = 0;
622 struct sh_eth_private *mdp = netdev_priv(ndev);
623 u32 ioaddr = ndev->base_addr;
624 u_int32_t rx_int_var, tx_int_var;
625 u32 val;
626
627 /* Soft Reset */
628 sh_eth_reset(ndev);
629
630 /* Descriptor format */
631 sh_eth_ring_format(ndev);
632 if (mdp->cd->rpadir)
633 writel(mdp->cd->rpadir_value, ioaddr + RPADIR);
634
635 /* all sh_eth int mask */
636 writel(0, ioaddr + EESIPR);
637
638 #if defined(__LITTLE_ENDIAN__)
639 if (mdp->cd->hw_swap)
640 writel(EDMR_EL, ioaddr + EDMR);
641 else
642 #endif
643 writel(0, ioaddr + EDMR);
644
645 /* FIFO size set */
646 writel(mdp->cd->fdr_value, ioaddr + FDR);
647 writel(0, ioaddr + TFTR);
648
649 /* Frame recv control */
650 writel(mdp->cd->rmcr_value, ioaddr + RMCR);
651
652 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
653 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
654 writel(rx_int_var | tx_int_var, ioaddr + TRSCER);
655
656 if (mdp->cd->bculr)
657 writel(0x800, ioaddr + BCULR); /* Burst sycle set */
658
659 writel(mdp->cd->fcftr_value, ioaddr + FCFTR);
660
661 if (!mdp->cd->no_trimd)
662 writel(0, ioaddr + TRIMD);
663
664 /* Recv frame limit set register */
665 writel(RFLR_VALUE, ioaddr + RFLR);
666
667 writel(readl(ioaddr + EESR), ioaddr + EESR);
668 writel(mdp->cd->eesipr_value, ioaddr + EESIPR);
669
670 /* PAUSE Prohibition */
671 val = (readl(ioaddr + ECMR) & ECMR_DM) |
672 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
673
674 writel(val, ioaddr + ECMR);
675
676 if (mdp->cd->set_rate)
677 mdp->cd->set_rate(ndev);
678
679 /* E-MAC Status Register clear */
680 writel(mdp->cd->ecsr_value, ioaddr + ECSR);
681
682 /* E-MAC Interrupt Enable register */
683 writel(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
684
685 /* Set MAC address */
686 update_mac_address(ndev);
687
688 /* mask reset */
689 if (mdp->cd->apr)
690 writel(APR_AP, ioaddr + APR);
691 if (mdp->cd->mpr)
692 writel(MPR_MP, ioaddr + MPR);
693 if (mdp->cd->tpauser)
694 writel(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
695
696 /* Setting the Rx mode will start the Rx process. */
697 writel(EDRRR_R, ioaddr + EDRRR);
698
699 netif_start_queue(ndev);
700
701 return ret;
702 }
703
704 /* free Tx skb function */
705 static int sh_eth_txfree(struct net_device *ndev)
706 {
707 struct sh_eth_private *mdp = netdev_priv(ndev);
708 struct sh_eth_txdesc *txdesc;
709 int freeNum = 0;
710 int entry = 0;
711
712 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
713 entry = mdp->dirty_tx % TX_RING_SIZE;
714 txdesc = &mdp->tx_ring[entry];
715 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
716 break;
717 /* Free the original skb. */
718 if (mdp->tx_skbuff[entry]) {
719 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
720 mdp->tx_skbuff[entry] = NULL;
721 freeNum++;
722 }
723 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
724 if (entry >= TX_RING_SIZE - 1)
725 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
726
727 mdp->stats.tx_packets++;
728 mdp->stats.tx_bytes += txdesc->buffer_length;
729 }
730 return freeNum;
731 }
732
733 /* Packet receive function */
734 static int sh_eth_rx(struct net_device *ndev)
735 {
736 struct sh_eth_private *mdp = netdev_priv(ndev);
737 struct sh_eth_rxdesc *rxdesc;
738
739 int entry = mdp->cur_rx % RX_RING_SIZE;
740 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
741 struct sk_buff *skb;
742 u16 pkt_len = 0;
743 u32 desc_status;
744
745 rxdesc = &mdp->rx_ring[entry];
746 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
747 desc_status = edmac_to_cpu(mdp, rxdesc->status);
748 pkt_len = rxdesc->frame_length;
749
750 if (--boguscnt < 0)
751 break;
752
753 if (!(desc_status & RDFEND))
754 mdp->stats.rx_length_errors++;
755
756 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
757 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
758 mdp->stats.rx_errors++;
759 if (desc_status & RD_RFS1)
760 mdp->stats.rx_crc_errors++;
761 if (desc_status & RD_RFS2)
762 mdp->stats.rx_frame_errors++;
763 if (desc_status & RD_RFS3)
764 mdp->stats.rx_length_errors++;
765 if (desc_status & RD_RFS4)
766 mdp->stats.rx_length_errors++;
767 if (desc_status & RD_RFS6)
768 mdp->stats.rx_missed_errors++;
769 if (desc_status & RD_RFS10)
770 mdp->stats.rx_over_errors++;
771 } else {
772 if (!mdp->cd->hw_swap)
773 sh_eth_soft_swap(
774 phys_to_virt(ALIGN(rxdesc->addr, 4)),
775 pkt_len + 2);
776 skb = mdp->rx_skbuff[entry];
777 mdp->rx_skbuff[entry] = NULL;
778 if (mdp->cd->rpadir)
779 skb_reserve(skb, NET_IP_ALIGN);
780 skb_put(skb, pkt_len);
781 skb->protocol = eth_type_trans(skb, ndev);
782 netif_rx(skb);
783 mdp->stats.rx_packets++;
784 mdp->stats.rx_bytes += pkt_len;
785 }
786 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
787 entry = (++mdp->cur_rx) % RX_RING_SIZE;
788 rxdesc = &mdp->rx_ring[entry];
789 }
790
791 /* Refill the Rx ring buffers. */
792 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
793 entry = mdp->dirty_rx % RX_RING_SIZE;
794 rxdesc = &mdp->rx_ring[entry];
795 /* The size of the buffer is 16 byte boundary. */
796 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
797
798 if (mdp->rx_skbuff[entry] == NULL) {
799 skb = dev_alloc_skb(mdp->rx_buf_sz);
800 mdp->rx_skbuff[entry] = skb;
801 if (skb == NULL)
802 break; /* Better luck next round. */
803 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
804 DMA_FROM_DEVICE);
805 skb->dev = ndev;
806 sh_eth_set_receive_align(skb);
807
808 skb_checksum_none_assert(skb);
809 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
810 }
811 if (entry >= RX_RING_SIZE - 1)
812 rxdesc->status |=
813 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
814 else
815 rxdesc->status |=
816 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
817 }
818
819 /* Restart Rx engine if stopped. */
820 /* If we don't need to check status, don't. -KDU */
821 if (!(readl(ndev->base_addr + EDRRR) & EDRRR_R))
822 writel(EDRRR_R, ndev->base_addr + EDRRR);
823
824 return 0;
825 }
826
827 static void sh_eth_rcv_snd_disable(u32 ioaddr)
828 {
829 /* disable tx and rx */
830 writel(readl(ioaddr + ECMR) &
831 ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
832 }
833
834 static void sh_eth_rcv_snd_enable(u32 ioaddr)
835 {
836 /* enable tx and rx */
837 writel(readl(ioaddr + ECMR) |
838 (ECMR_RE | ECMR_TE), ioaddr + ECMR);
839 }
840
841 /* error control function */
842 static void sh_eth_error(struct net_device *ndev, int intr_status)
843 {
844 struct sh_eth_private *mdp = netdev_priv(ndev);
845 u32 ioaddr = ndev->base_addr;
846 u32 felic_stat;
847 u32 link_stat;
848 u32 mask;
849
850 if (intr_status & EESR_ECI) {
851 felic_stat = readl(ioaddr + ECSR);
852 writel(felic_stat, ioaddr + ECSR); /* clear int */
853 if (felic_stat & ECSR_ICD)
854 mdp->stats.tx_carrier_errors++;
855 if (felic_stat & ECSR_LCHNG) {
856 /* Link Changed */
857 if (mdp->cd->no_psr || mdp->no_ether_link) {
858 if (mdp->link == PHY_DOWN)
859 link_stat = 0;
860 else
861 link_stat = PHY_ST_LINK;
862 } else {
863 link_stat = (readl(ioaddr + PSR));
864 if (mdp->ether_link_active_low)
865 link_stat = ~link_stat;
866 }
867 if (!(link_stat & PHY_ST_LINK))
868 sh_eth_rcv_snd_disable(ioaddr);
869 else {
870 /* Link Up */
871 writel(readl(ioaddr + EESIPR) &
872 ~DMAC_M_ECI, ioaddr + EESIPR);
873 /*clear int */
874 writel(readl(ioaddr + ECSR),
875 ioaddr + ECSR);
876 writel(readl(ioaddr + EESIPR) |
877 DMAC_M_ECI, ioaddr + EESIPR);
878 /* enable tx and rx */
879 sh_eth_rcv_snd_enable(ioaddr);
880 }
881 }
882 }
883
884 if (intr_status & EESR_TWB) {
885 /* Write buck end. unused write back interrupt */
886 if (intr_status & EESR_TABT) /* Transmit Abort int */
887 mdp->stats.tx_aborted_errors++;
888 if (netif_msg_tx_err(mdp))
889 dev_err(&ndev->dev, "Transmit Abort\n");
890 }
891
892 if (intr_status & EESR_RABT) {
893 /* Receive Abort int */
894 if (intr_status & EESR_RFRMER) {
895 /* Receive Frame Overflow int */
896 mdp->stats.rx_frame_errors++;
897 if (netif_msg_rx_err(mdp))
898 dev_err(&ndev->dev, "Receive Abort\n");
899 }
900 }
901
902 if (intr_status & EESR_TDE) {
903 /* Transmit Descriptor Empty int */
904 mdp->stats.tx_fifo_errors++;
905 if (netif_msg_tx_err(mdp))
906 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
907 }
908
909 if (intr_status & EESR_TFE) {
910 /* FIFO under flow */
911 mdp->stats.tx_fifo_errors++;
912 if (netif_msg_tx_err(mdp))
913 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
914 }
915
916 if (intr_status & EESR_RDE) {
917 /* Receive Descriptor Empty int */
918 mdp->stats.rx_over_errors++;
919
920 if (readl(ioaddr + EDRRR) ^ EDRRR_R)
921 writel(EDRRR_R, ioaddr + EDRRR);
922 if (netif_msg_rx_err(mdp))
923 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
924 }
925
926 if (intr_status & EESR_RFE) {
927 /* Receive FIFO Overflow int */
928 mdp->stats.rx_fifo_errors++;
929 if (netif_msg_rx_err(mdp))
930 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
931 }
932
933 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
934 /* Address Error */
935 mdp->stats.tx_fifo_errors++;
936 if (netif_msg_tx_err(mdp))
937 dev_err(&ndev->dev, "Address Error\n");
938 }
939
940 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
941 if (mdp->cd->no_ade)
942 mask &= ~EESR_ADE;
943 if (intr_status & mask) {
944 /* Tx error */
945 u32 edtrr = readl(ndev->base_addr + EDTRR);
946 /* dmesg */
947 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
948 intr_status, mdp->cur_tx);
949 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
950 mdp->dirty_tx, (u32) ndev->state, edtrr);
951 /* dirty buffer free */
952 sh_eth_txfree(ndev);
953
954 /* SH7712 BUG */
955 if (edtrr ^ EDTRR_TRNS) {
956 /* tx dma start */
957 writel(EDTRR_TRNS, ndev->base_addr + EDTRR);
958 }
959 /* wakeup */
960 netif_wake_queue(ndev);
961 }
962 }
963
964 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
965 {
966 struct net_device *ndev = netdev;
967 struct sh_eth_private *mdp = netdev_priv(ndev);
968 struct sh_eth_cpu_data *cd = mdp->cd;
969 irqreturn_t ret = IRQ_NONE;
970 u32 ioaddr, intr_status = 0;
971
972 ioaddr = ndev->base_addr;
973 spin_lock(&mdp->lock);
974
975 /* Get interrpt stat */
976 intr_status = readl(ioaddr + EESR);
977 /* Clear interrupt */
978 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
979 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
980 cd->tx_check | cd->eesr_err_check)) {
981 writel(intr_status, ioaddr + EESR);
982 ret = IRQ_HANDLED;
983 } else
984 goto other_irq;
985
986 if (intr_status & (EESR_FRC | /* Frame recv*/
987 EESR_RMAF | /* Multi cast address recv*/
988 EESR_RRF | /* Bit frame recv */
989 EESR_RTLF | /* Long frame recv*/
990 EESR_RTSF | /* short frame recv */
991 EESR_PRE | /* PHY-LSI recv error */
992 EESR_CERF)){ /* recv frame CRC error */
993 sh_eth_rx(ndev);
994 }
995
996 /* Tx Check */
997 if (intr_status & cd->tx_check) {
998 sh_eth_txfree(ndev);
999 netif_wake_queue(ndev);
1000 }
1001
1002 if (intr_status & cd->eesr_err_check)
1003 sh_eth_error(ndev, intr_status);
1004
1005 other_irq:
1006 spin_unlock(&mdp->lock);
1007
1008 return ret;
1009 }
1010
1011 static void sh_eth_timer(unsigned long data)
1012 {
1013 struct net_device *ndev = (struct net_device *)data;
1014 struct sh_eth_private *mdp = netdev_priv(ndev);
1015
1016 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1017 }
1018
1019 /* PHY state control function */
1020 static void sh_eth_adjust_link(struct net_device *ndev)
1021 {
1022 struct sh_eth_private *mdp = netdev_priv(ndev);
1023 struct phy_device *phydev = mdp->phydev;
1024 u32 ioaddr = ndev->base_addr;
1025 int new_state = 0;
1026
1027 if (phydev->link != PHY_DOWN) {
1028 if (phydev->duplex != mdp->duplex) {
1029 new_state = 1;
1030 mdp->duplex = phydev->duplex;
1031 if (mdp->cd->set_duplex)
1032 mdp->cd->set_duplex(ndev);
1033 }
1034
1035 if (phydev->speed != mdp->speed) {
1036 new_state = 1;
1037 mdp->speed = phydev->speed;
1038 if (mdp->cd->set_rate)
1039 mdp->cd->set_rate(ndev);
1040 }
1041 if (mdp->link == PHY_DOWN) {
1042 writel((readl(ioaddr + ECMR) & ~ECMR_TXF)
1043 | ECMR_DM, ioaddr + ECMR);
1044 new_state = 1;
1045 mdp->link = phydev->link;
1046 }
1047 } else if (mdp->link) {
1048 new_state = 1;
1049 mdp->link = PHY_DOWN;
1050 mdp->speed = 0;
1051 mdp->duplex = -1;
1052 }
1053
1054 if (new_state && netif_msg_link(mdp))
1055 phy_print_status(phydev);
1056 }
1057
1058 /* PHY init function */
1059 static int sh_eth_phy_init(struct net_device *ndev)
1060 {
1061 struct sh_eth_private *mdp = netdev_priv(ndev);
1062 char phy_id[MII_BUS_ID_SIZE + 3];
1063 struct phy_device *phydev = NULL;
1064
1065 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1066 mdp->mii_bus->id , mdp->phy_id);
1067
1068 mdp->link = PHY_DOWN;
1069 mdp->speed = 0;
1070 mdp->duplex = -1;
1071
1072 /* Try connect to PHY */
1073 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1074 0, PHY_INTERFACE_MODE_MII);
1075 if (IS_ERR(phydev)) {
1076 dev_err(&ndev->dev, "phy_connect failed\n");
1077 return PTR_ERR(phydev);
1078 }
1079
1080 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1081 phydev->addr, phydev->drv->name);
1082
1083 mdp->phydev = phydev;
1084
1085 return 0;
1086 }
1087
1088 /* PHY control start function */
1089 static int sh_eth_phy_start(struct net_device *ndev)
1090 {
1091 struct sh_eth_private *mdp = netdev_priv(ndev);
1092 int ret;
1093
1094 ret = sh_eth_phy_init(ndev);
1095 if (ret)
1096 return ret;
1097
1098 /* reset phy - this also wakes it from PDOWN */
1099 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1100 phy_start(mdp->phydev);
1101
1102 return 0;
1103 }
1104
1105 static int sh_eth_get_settings(struct net_device *ndev,
1106 struct ethtool_cmd *ecmd)
1107 {
1108 struct sh_eth_private *mdp = netdev_priv(ndev);
1109 unsigned long flags;
1110 int ret;
1111
1112 spin_lock_irqsave(&mdp->lock, flags);
1113 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1114 spin_unlock_irqrestore(&mdp->lock, flags);
1115
1116 return ret;
1117 }
1118
1119 static int sh_eth_set_settings(struct net_device *ndev,
1120 struct ethtool_cmd *ecmd)
1121 {
1122 struct sh_eth_private *mdp = netdev_priv(ndev);
1123 unsigned long flags;
1124 int ret;
1125 u32 ioaddr = ndev->base_addr;
1126
1127 spin_lock_irqsave(&mdp->lock, flags);
1128
1129 /* disable tx and rx */
1130 sh_eth_rcv_snd_disable(ioaddr);
1131
1132 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1133 if (ret)
1134 goto error_exit;
1135
1136 if (ecmd->duplex == DUPLEX_FULL)
1137 mdp->duplex = 1;
1138 else
1139 mdp->duplex = 0;
1140
1141 if (mdp->cd->set_duplex)
1142 mdp->cd->set_duplex(ndev);
1143
1144 error_exit:
1145 mdelay(1);
1146
1147 /* enable tx and rx */
1148 sh_eth_rcv_snd_enable(ioaddr);
1149
1150 spin_unlock_irqrestore(&mdp->lock, flags);
1151
1152 return ret;
1153 }
1154
1155 static int sh_eth_nway_reset(struct net_device *ndev)
1156 {
1157 struct sh_eth_private *mdp = netdev_priv(ndev);
1158 unsigned long flags;
1159 int ret;
1160
1161 spin_lock_irqsave(&mdp->lock, flags);
1162 ret = phy_start_aneg(mdp->phydev);
1163 spin_unlock_irqrestore(&mdp->lock, flags);
1164
1165 return ret;
1166 }
1167
1168 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1169 {
1170 struct sh_eth_private *mdp = netdev_priv(ndev);
1171 return mdp->msg_enable;
1172 }
1173
1174 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1175 {
1176 struct sh_eth_private *mdp = netdev_priv(ndev);
1177 mdp->msg_enable = value;
1178 }
1179
1180 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1181 "rx_current", "tx_current",
1182 "rx_dirty", "tx_dirty",
1183 };
1184 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1185
1186 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1187 {
1188 switch (sset) {
1189 case ETH_SS_STATS:
1190 return SH_ETH_STATS_LEN;
1191 default:
1192 return -EOPNOTSUPP;
1193 }
1194 }
1195
1196 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1197 struct ethtool_stats *stats, u64 *data)
1198 {
1199 struct sh_eth_private *mdp = netdev_priv(ndev);
1200 int i = 0;
1201
1202 /* device-specific stats */
1203 data[i++] = mdp->cur_rx;
1204 data[i++] = mdp->cur_tx;
1205 data[i++] = mdp->dirty_rx;
1206 data[i++] = mdp->dirty_tx;
1207 }
1208
1209 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1210 {
1211 switch (stringset) {
1212 case ETH_SS_STATS:
1213 memcpy(data, *sh_eth_gstrings_stats,
1214 sizeof(sh_eth_gstrings_stats));
1215 break;
1216 }
1217 }
1218
1219 static struct ethtool_ops sh_eth_ethtool_ops = {
1220 .get_settings = sh_eth_get_settings,
1221 .set_settings = sh_eth_set_settings,
1222 .nway_reset = sh_eth_nway_reset,
1223 .get_msglevel = sh_eth_get_msglevel,
1224 .set_msglevel = sh_eth_set_msglevel,
1225 .get_link = ethtool_op_get_link,
1226 .get_strings = sh_eth_get_strings,
1227 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1228 .get_sset_count = sh_eth_get_sset_count,
1229 };
1230
1231 /* network device open function */
1232 static int sh_eth_open(struct net_device *ndev)
1233 {
1234 int ret = 0;
1235 struct sh_eth_private *mdp = netdev_priv(ndev);
1236
1237 pm_runtime_get_sync(&mdp->pdev->dev);
1238
1239 ret = request_irq(ndev->irq, sh_eth_interrupt,
1240 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1241 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1242 defined(CONFIG_CPU_SUBTYPE_SH7757)
1243 IRQF_SHARED,
1244 #else
1245 0,
1246 #endif
1247 ndev->name, ndev);
1248 if (ret) {
1249 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1250 return ret;
1251 }
1252
1253 /* Descriptor set */
1254 ret = sh_eth_ring_init(ndev);
1255 if (ret)
1256 goto out_free_irq;
1257
1258 /* device init */
1259 ret = sh_eth_dev_init(ndev);
1260 if (ret)
1261 goto out_free_irq;
1262
1263 /* PHY control start*/
1264 ret = sh_eth_phy_start(ndev);
1265 if (ret)
1266 goto out_free_irq;
1267
1268 /* Set the timer to check for link beat. */
1269 init_timer(&mdp->timer);
1270 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1271 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1272
1273 return ret;
1274
1275 out_free_irq:
1276 free_irq(ndev->irq, ndev);
1277 pm_runtime_put_sync(&mdp->pdev->dev);
1278 return ret;
1279 }
1280
1281 /* Timeout function */
1282 static void sh_eth_tx_timeout(struct net_device *ndev)
1283 {
1284 struct sh_eth_private *mdp = netdev_priv(ndev);
1285 u32 ioaddr = ndev->base_addr;
1286 struct sh_eth_rxdesc *rxdesc;
1287 int i;
1288
1289 netif_stop_queue(ndev);
1290
1291 if (netif_msg_timer(mdp))
1292 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1293 " resetting...\n", ndev->name, (int)readl(ioaddr + EESR));
1294
1295 /* tx_errors count up */
1296 mdp->stats.tx_errors++;
1297
1298 /* timer off */
1299 del_timer_sync(&mdp->timer);
1300
1301 /* Free all the skbuffs in the Rx queue. */
1302 for (i = 0; i < RX_RING_SIZE; i++) {
1303 rxdesc = &mdp->rx_ring[i];
1304 rxdesc->status = 0;
1305 rxdesc->addr = 0xBADF00D0;
1306 if (mdp->rx_skbuff[i])
1307 dev_kfree_skb(mdp->rx_skbuff[i]);
1308 mdp->rx_skbuff[i] = NULL;
1309 }
1310 for (i = 0; i < TX_RING_SIZE; i++) {
1311 if (mdp->tx_skbuff[i])
1312 dev_kfree_skb(mdp->tx_skbuff[i]);
1313 mdp->tx_skbuff[i] = NULL;
1314 }
1315
1316 /* device init */
1317 sh_eth_dev_init(ndev);
1318
1319 /* timer on */
1320 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1321 add_timer(&mdp->timer);
1322 }
1323
1324 /* Packet transmit function */
1325 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1326 {
1327 struct sh_eth_private *mdp = netdev_priv(ndev);
1328 struct sh_eth_txdesc *txdesc;
1329 u32 entry;
1330 unsigned long flags;
1331
1332 spin_lock_irqsave(&mdp->lock, flags);
1333 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1334 if (!sh_eth_txfree(ndev)) {
1335 if (netif_msg_tx_queued(mdp))
1336 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1337 netif_stop_queue(ndev);
1338 spin_unlock_irqrestore(&mdp->lock, flags);
1339 return NETDEV_TX_BUSY;
1340 }
1341 }
1342 spin_unlock_irqrestore(&mdp->lock, flags);
1343
1344 entry = mdp->cur_tx % TX_RING_SIZE;
1345 mdp->tx_skbuff[entry] = skb;
1346 txdesc = &mdp->tx_ring[entry];
1347 txdesc->addr = virt_to_phys(skb->data);
1348 /* soft swap. */
1349 if (!mdp->cd->hw_swap)
1350 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1351 skb->len + 2);
1352 /* write back */
1353 __flush_purge_region(skb->data, skb->len);
1354 if (skb->len < ETHERSMALL)
1355 txdesc->buffer_length = ETHERSMALL;
1356 else
1357 txdesc->buffer_length = skb->len;
1358
1359 if (entry >= TX_RING_SIZE - 1)
1360 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1361 else
1362 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1363
1364 mdp->cur_tx++;
1365
1366 if (!(readl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
1367 writel(EDTRR_TRNS, ndev->base_addr + EDTRR);
1368
1369 return NETDEV_TX_OK;
1370 }
1371
1372 /* device close function */
1373 static int sh_eth_close(struct net_device *ndev)
1374 {
1375 struct sh_eth_private *mdp = netdev_priv(ndev);
1376 u32 ioaddr = ndev->base_addr;
1377 int ringsize;
1378
1379 netif_stop_queue(ndev);
1380
1381 /* Disable interrupts by clearing the interrupt mask. */
1382 writel(0x0000, ioaddr + EESIPR);
1383
1384 /* Stop the chip's Tx and Rx processes. */
1385 writel(0, ioaddr + EDTRR);
1386 writel(0, ioaddr + EDRRR);
1387
1388 /* PHY Disconnect */
1389 if (mdp->phydev) {
1390 phy_stop(mdp->phydev);
1391 phy_disconnect(mdp->phydev);
1392 }
1393
1394 free_irq(ndev->irq, ndev);
1395
1396 del_timer_sync(&mdp->timer);
1397
1398 /* Free all the skbuffs in the Rx queue. */
1399 sh_eth_ring_free(ndev);
1400
1401 /* free DMA buffer */
1402 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1403 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1404
1405 /* free DMA buffer */
1406 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1407 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1408
1409 pm_runtime_put_sync(&mdp->pdev->dev);
1410
1411 return 0;
1412 }
1413
1414 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1415 {
1416 struct sh_eth_private *mdp = netdev_priv(ndev);
1417 u32 ioaddr = ndev->base_addr;
1418
1419 pm_runtime_get_sync(&mdp->pdev->dev);
1420
1421 mdp->stats.tx_dropped += readl(ioaddr + TROCR);
1422 writel(0, ioaddr + TROCR); /* (write clear) */
1423 mdp->stats.collisions += readl(ioaddr + CDCR);
1424 writel(0, ioaddr + CDCR); /* (write clear) */
1425 mdp->stats.tx_carrier_errors += readl(ioaddr + LCCR);
1426 writel(0, ioaddr + LCCR); /* (write clear) */
1427 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1428 mdp->stats.tx_carrier_errors += readl(ioaddr + CERCR);/* CERCR */
1429 writel(0, ioaddr + CERCR); /* (write clear) */
1430 mdp->stats.tx_carrier_errors += readl(ioaddr + CEECR);/* CEECR */
1431 writel(0, ioaddr + CEECR); /* (write clear) */
1432 #else
1433 mdp->stats.tx_carrier_errors += readl(ioaddr + CNDCR);
1434 writel(0, ioaddr + CNDCR); /* (write clear) */
1435 #endif
1436 pm_runtime_put_sync(&mdp->pdev->dev);
1437
1438 return &mdp->stats;
1439 }
1440
1441 /* ioctl to device funciotn*/
1442 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1443 int cmd)
1444 {
1445 struct sh_eth_private *mdp = netdev_priv(ndev);
1446 struct phy_device *phydev = mdp->phydev;
1447
1448 if (!netif_running(ndev))
1449 return -EINVAL;
1450
1451 if (!phydev)
1452 return -ENODEV;
1453
1454 return phy_mii_ioctl(phydev, rq, cmd);
1455 }
1456
1457 #if defined(SH_ETH_HAS_TSU)
1458 /* Multicast reception directions set */
1459 static void sh_eth_set_multicast_list(struct net_device *ndev)
1460 {
1461 u32 ioaddr = ndev->base_addr;
1462
1463 if (ndev->flags & IFF_PROMISC) {
1464 /* Set promiscuous. */
1465 writel((readl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
1466 ioaddr + ECMR);
1467 } else {
1468 /* Normal, unicast/broadcast-only mode. */
1469 writel((readl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
1470 ioaddr + ECMR);
1471 }
1472 }
1473
1474 /* SuperH's TSU register init function */
1475 static void sh_eth_tsu_init(u32 ioaddr)
1476 {
1477 writel(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
1478 writel(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
1479 writel(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
1480 writel(0xc, ioaddr + TSU_BSYSL0);
1481 writel(0xc, ioaddr + TSU_BSYSL1);
1482 writel(0, ioaddr + TSU_PRISL0);
1483 writel(0, ioaddr + TSU_PRISL1);
1484 writel(0, ioaddr + TSU_FWSL0);
1485 writel(0, ioaddr + TSU_FWSL1);
1486 writel(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
1487 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1488 writel(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1489 writel(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1490 #else
1491 writel(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
1492 writel(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
1493 #endif
1494 writel(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
1495 writel(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
1496 writel(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
1497 writel(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
1498 writel(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
1499 writel(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1500 writel(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
1501 }
1502 #endif /* SH_ETH_HAS_TSU */
1503
1504 /* MDIO bus release function */
1505 static int sh_mdio_release(struct net_device *ndev)
1506 {
1507 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1508
1509 /* unregister mdio bus */
1510 mdiobus_unregister(bus);
1511
1512 /* remove mdio bus info from net_device */
1513 dev_set_drvdata(&ndev->dev, NULL);
1514
1515 /* free interrupts memory */
1516 kfree(bus->irq);
1517
1518 /* free bitbang info */
1519 free_mdio_bitbang(bus);
1520
1521 return 0;
1522 }
1523
1524 /* MDIO bus init function */
1525 static int sh_mdio_init(struct net_device *ndev, int id)
1526 {
1527 int ret, i;
1528 struct bb_info *bitbang;
1529 struct sh_eth_private *mdp = netdev_priv(ndev);
1530
1531 /* create bit control struct for PHY */
1532 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1533 if (!bitbang) {
1534 ret = -ENOMEM;
1535 goto out;
1536 }
1537
1538 /* bitbang init */
1539 bitbang->addr = ndev->base_addr + PIR;
1540 bitbang->mdi_msk = 0x08;
1541 bitbang->mdo_msk = 0x04;
1542 bitbang->mmd_msk = 0x02;/* MMD */
1543 bitbang->mdc_msk = 0x01;
1544 bitbang->ctrl.ops = &bb_ops;
1545
1546 /* MII controller setting */
1547 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1548 if (!mdp->mii_bus) {
1549 ret = -ENOMEM;
1550 goto out_free_bitbang;
1551 }
1552
1553 /* Hook up MII support for ethtool */
1554 mdp->mii_bus->name = "sh_mii";
1555 mdp->mii_bus->parent = &ndev->dev;
1556 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1557
1558 /* PHY IRQ */
1559 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1560 if (!mdp->mii_bus->irq) {
1561 ret = -ENOMEM;
1562 goto out_free_bus;
1563 }
1564
1565 for (i = 0; i < PHY_MAX_ADDR; i++)
1566 mdp->mii_bus->irq[i] = PHY_POLL;
1567
1568 /* regist mdio bus */
1569 ret = mdiobus_register(mdp->mii_bus);
1570 if (ret)
1571 goto out_free_irq;
1572
1573 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1574
1575 return 0;
1576
1577 out_free_irq:
1578 kfree(mdp->mii_bus->irq);
1579
1580 out_free_bus:
1581 free_mdio_bitbang(mdp->mii_bus);
1582
1583 out_free_bitbang:
1584 kfree(bitbang);
1585
1586 out:
1587 return ret;
1588 }
1589
1590 static const struct net_device_ops sh_eth_netdev_ops = {
1591 .ndo_open = sh_eth_open,
1592 .ndo_stop = sh_eth_close,
1593 .ndo_start_xmit = sh_eth_start_xmit,
1594 .ndo_get_stats = sh_eth_get_stats,
1595 #if defined(SH_ETH_HAS_TSU)
1596 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1597 #endif
1598 .ndo_tx_timeout = sh_eth_tx_timeout,
1599 .ndo_do_ioctl = sh_eth_do_ioctl,
1600 .ndo_validate_addr = eth_validate_addr,
1601 .ndo_set_mac_address = eth_mac_addr,
1602 .ndo_change_mtu = eth_change_mtu,
1603 };
1604
1605 static int sh_eth_drv_probe(struct platform_device *pdev)
1606 {
1607 int ret, devno = 0;
1608 struct resource *res;
1609 struct net_device *ndev = NULL;
1610 struct sh_eth_private *mdp;
1611 struct sh_eth_plat_data *pd;
1612
1613 /* get base addr */
1614 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1615 if (unlikely(res == NULL)) {
1616 dev_err(&pdev->dev, "invalid resource\n");
1617 ret = -EINVAL;
1618 goto out;
1619 }
1620
1621 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1622 if (!ndev) {
1623 dev_err(&pdev->dev, "Could not allocate device.\n");
1624 ret = -ENOMEM;
1625 goto out;
1626 }
1627
1628 /* The sh Ether-specific entries in the device structure. */
1629 ndev->base_addr = res->start;
1630 devno = pdev->id;
1631 if (devno < 0)
1632 devno = 0;
1633
1634 ndev->dma = -1;
1635 ret = platform_get_irq(pdev, 0);
1636 if (ret < 0) {
1637 ret = -ENODEV;
1638 goto out_release;
1639 }
1640 ndev->irq = ret;
1641
1642 SET_NETDEV_DEV(ndev, &pdev->dev);
1643
1644 /* Fill in the fields of the device structure with ethernet values. */
1645 ether_setup(ndev);
1646
1647 mdp = netdev_priv(ndev);
1648 spin_lock_init(&mdp->lock);
1649 mdp->pdev = pdev;
1650 pm_runtime_enable(&pdev->dev);
1651 pm_runtime_resume(&pdev->dev);
1652
1653 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1654 /* get PHY ID */
1655 mdp->phy_id = pd->phy;
1656 /* EDMAC endian */
1657 mdp->edmac_endian = pd->edmac_endian;
1658 mdp->no_ether_link = pd->no_ether_link;
1659 mdp->ether_link_active_low = pd->ether_link_active_low;
1660
1661 /* set cpu data */
1662 mdp->cd = &sh_eth_my_cpu_data;
1663 sh_eth_set_default_cpu_data(mdp->cd);
1664
1665 /* set function */
1666 ndev->netdev_ops = &sh_eth_netdev_ops;
1667 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
1668 ndev->watchdog_timeo = TX_TIMEOUT;
1669
1670 /* debug message level */
1671 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
1672 mdp->post_rx = POST_RX >> (devno << 1);
1673 mdp->post_fw = POST_FW >> (devno << 1);
1674
1675 /* read and set MAC address */
1676 read_mac_address(ndev, pd->mac_addr);
1677
1678 /* First device only init */
1679 if (!devno) {
1680 if (mdp->cd->chip_reset)
1681 mdp->cd->chip_reset(ndev);
1682
1683 #if defined(SH_ETH_HAS_TSU)
1684 /* TSU init (Init only)*/
1685 sh_eth_tsu_init(SH_TSU_ADDR);
1686 #endif
1687 }
1688
1689 /* network device register */
1690 ret = register_netdev(ndev);
1691 if (ret)
1692 goto out_release;
1693
1694 /* mdio bus init */
1695 ret = sh_mdio_init(ndev, pdev->id);
1696 if (ret)
1697 goto out_unregister;
1698
1699 /* print device infomation */
1700 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1701 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1702
1703 platform_set_drvdata(pdev, ndev);
1704
1705 return ret;
1706
1707 out_unregister:
1708 unregister_netdev(ndev);
1709
1710 out_release:
1711 /* net_dev free */
1712 if (ndev)
1713 free_netdev(ndev);
1714
1715 out:
1716 return ret;
1717 }
1718
1719 static int sh_eth_drv_remove(struct platform_device *pdev)
1720 {
1721 struct net_device *ndev = platform_get_drvdata(pdev);
1722
1723 sh_mdio_release(ndev);
1724 unregister_netdev(ndev);
1725 pm_runtime_disable(&pdev->dev);
1726 free_netdev(ndev);
1727 platform_set_drvdata(pdev, NULL);
1728
1729 return 0;
1730 }
1731
1732 static int sh_eth_runtime_nop(struct device *dev)
1733 {
1734 /*
1735 * Runtime PM callback shared between ->runtime_suspend()
1736 * and ->runtime_resume(). Simply returns success.
1737 *
1738 * This driver re-initializes all registers after
1739 * pm_runtime_get_sync() anyway so there is no need
1740 * to save and restore registers here.
1741 */
1742 return 0;
1743 }
1744
1745 static struct dev_pm_ops sh_eth_dev_pm_ops = {
1746 .runtime_suspend = sh_eth_runtime_nop,
1747 .runtime_resume = sh_eth_runtime_nop,
1748 };
1749
1750 static struct platform_driver sh_eth_driver = {
1751 .probe = sh_eth_drv_probe,
1752 .remove = sh_eth_drv_remove,
1753 .driver = {
1754 .name = CARDNAME,
1755 .pm = &sh_eth_dev_pm_ops,
1756 },
1757 };
1758
1759 static int __init sh_eth_init(void)
1760 {
1761 return platform_driver_register(&sh_eth_driver);
1762 }
1763
1764 static void __exit sh_eth_cleanup(void)
1765 {
1766 platform_driver_unregister(&sh_eth_driver);
1767 }
1768
1769 module_init(sh_eth_init);
1770 module_exit(sh_eth_cleanup);
1771
1772 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1773 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1774 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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