2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/version.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/platform_device.h>
29 #include <linux/mdio-bitbang.h>
30 #include <linux/netdevice.h>
31 #include <linux/phy.h>
32 #include <linux/cache.h>
37 /* CPU <-> EDMAC endian convert */
38 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
40 switch (mdp
->edmac_endian
) {
41 case EDMAC_LITTLE_ENDIAN
:
42 return cpu_to_le32(x
);
43 case EDMAC_BIG_ENDIAN
:
44 return cpu_to_be32(x
);
49 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
51 switch (mdp
->edmac_endian
) {
52 case EDMAC_LITTLE_ENDIAN
:
53 return le32_to_cpu(x
);
54 case EDMAC_BIG_ENDIAN
:
55 return be32_to_cpu(x
);
61 * Program the hardware MAC address from dev->dev_addr.
63 static void update_mac_address(struct net_device
*ndev
)
65 u32 ioaddr
= ndev
->base_addr
;
67 ctrl_outl((ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
68 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]),
70 ctrl_outl((ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]),
75 * Get MAC address from SuperH MAC address register
77 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
78 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
79 * When you want use this device, you must set MAC address in bootloader.
82 static void read_mac_address(struct net_device
*ndev
)
84 u32 ioaddr
= ndev
->base_addr
;
86 ndev
->dev_addr
[0] = (ctrl_inl(ioaddr
+ MAHR
) >> 24);
87 ndev
->dev_addr
[1] = (ctrl_inl(ioaddr
+ MAHR
) >> 16) & 0xFF;
88 ndev
->dev_addr
[2] = (ctrl_inl(ioaddr
+ MAHR
) >> 8) & 0xFF;
89 ndev
->dev_addr
[3] = (ctrl_inl(ioaddr
+ MAHR
) & 0xFF);
90 ndev
->dev_addr
[4] = (ctrl_inl(ioaddr
+ MALR
) >> 8) & 0xFF;
91 ndev
->dev_addr
[5] = (ctrl_inl(ioaddr
+ MALR
) & 0xFF);
95 struct mdiobb_ctrl ctrl
;
104 static void bb_set(u32 addr
, u32 msk
)
106 ctrl_outl(ctrl_inl(addr
) | msk
, addr
);
110 static void bb_clr(u32 addr
, u32 msk
)
112 ctrl_outl((ctrl_inl(addr
) & ~msk
), addr
);
116 static int bb_read(u32 addr
, u32 msk
)
118 return (ctrl_inl(addr
) & msk
) != 0;
121 /* Data I/O pin control */
122 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
124 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
126 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
128 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
132 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
134 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
137 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
139 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
143 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
145 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
146 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
149 /* MDC pin control */
150 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
152 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
155 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
157 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
160 /* mdio bus control struct */
161 static struct mdiobb_ops bb_ops
= {
162 .owner
= THIS_MODULE
,
163 .set_mdc
= sh_mdc_ctrl
,
164 .set_mdio_dir
= sh_mmd_ctrl
,
165 .set_mdio_data
= sh_set_mdio
,
166 .get_mdio_data
= sh_get_mdio
,
170 static void sh_eth_reset(struct net_device
*ndev
)
172 u32 ioaddr
= ndev
->base_addr
;
174 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
177 ctrl_outl(EDSR_ENALL
, ioaddr
+ EDSR
);
178 ctrl_outl(ctrl_inl(ioaddr
+ EDMR
) | EDMR_SRST
, ioaddr
+ EDMR
);
180 if (!(ctrl_inl(ioaddr
+ EDMR
) & 0x3))
186 printk(KERN_ERR
"Device reset fail\n");
189 ctrl_outl(0x0, ioaddr
+ TDLAR
);
190 ctrl_outl(0x0, ioaddr
+ TDFAR
);
191 ctrl_outl(0x0, ioaddr
+ TDFXR
);
192 ctrl_outl(0x0, ioaddr
+ TDFFR
);
193 ctrl_outl(0x0, ioaddr
+ RDLAR
);
194 ctrl_outl(0x0, ioaddr
+ RDFAR
);
195 ctrl_outl(0x0, ioaddr
+ RDFXR
);
196 ctrl_outl(0x0, ioaddr
+ RDFFR
);
198 ctrl_outl(ctrl_inl(ioaddr
+ EDMR
) | EDMR_SRST
, ioaddr
+ EDMR
);
200 ctrl_outl(ctrl_inl(ioaddr
+ EDMR
) & ~EDMR_SRST
, ioaddr
+ EDMR
);
204 /* free skb and descriptor buffer */
205 static void sh_eth_ring_free(struct net_device
*ndev
)
207 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
210 /* Free Rx skb ringbuffer */
211 if (mdp
->rx_skbuff
) {
212 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
213 if (mdp
->rx_skbuff
[i
])
214 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
217 kfree(mdp
->rx_skbuff
);
219 /* Free Tx skb ringbuffer */
220 if (mdp
->tx_skbuff
) {
221 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
222 if (mdp
->tx_skbuff
[i
])
223 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
226 kfree(mdp
->tx_skbuff
);
229 /* format skb and descriptor buffer */
230 static void sh_eth_ring_format(struct net_device
*ndev
)
232 u32 ioaddr
= ndev
->base_addr
, reserve
= 0;
233 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
236 struct sh_eth_rxdesc
*rxdesc
= NULL
;
237 struct sh_eth_txdesc
*txdesc
= NULL
;
238 int rx_ringsize
= sizeof(*rxdesc
) * RX_RING_SIZE
;
239 int tx_ringsize
= sizeof(*txdesc
) * TX_RING_SIZE
;
241 mdp
->cur_rx
= mdp
->cur_tx
= 0;
242 mdp
->dirty_rx
= mdp
->dirty_tx
= 0;
244 memset(mdp
->rx_ring
, 0, rx_ringsize
);
246 /* build Rx ring buffer */
247 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
249 mdp
->rx_skbuff
[i
] = NULL
;
250 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
251 mdp
->rx_skbuff
[i
] = skb
;
254 skb
->dev
= ndev
; /* Mark as being used by this device. */
255 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
256 reserve
= SH7763_SKB_ALIGN
257 - ((uint32_t)skb
->data
& (SH7763_SKB_ALIGN
-1));
259 skb_reserve(skb
, reserve
);
261 skb_reserve(skb
, RX_OFFSET
);
264 rxdesc
= &mdp
->rx_ring
[i
];
265 rxdesc
->addr
= (u32
)skb
->data
& ~0x3UL
;
266 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
268 /* The size of the buffer is 16 byte boundary. */
269 rxdesc
->buffer_length
= (mdp
->rx_buf_sz
+ 16) & ~0x0F;
270 /* Rx descriptor address set */
272 ctrl_outl((u32
)rxdesc
, ioaddr
+ RDLAR
);
273 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
274 ctrl_outl((u32
)rxdesc
, ioaddr
+ RDFAR
);
279 /* Rx descriptor address set */
280 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
281 ctrl_outl((u32
)rxdesc
, ioaddr
+ RDFXR
);
282 ctrl_outl(0x1, ioaddr
+ RDFFR
);
285 mdp
->dirty_rx
= (u32
) (i
- RX_RING_SIZE
);
287 /* Mark the last entry as wrapping the ring. */
288 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
290 memset(mdp
->tx_ring
, 0, tx_ringsize
);
292 /* build Tx ring buffer */
293 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
294 mdp
->tx_skbuff
[i
] = NULL
;
295 txdesc
= &mdp
->tx_ring
[i
];
296 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
297 txdesc
->buffer_length
= 0;
299 /* Tx descriptor address set */
300 ctrl_outl((u32
)txdesc
, ioaddr
+ TDLAR
);
301 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
302 ctrl_outl((u32
)txdesc
, ioaddr
+ TDFAR
);
307 /* Tx descriptor address set */
308 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
309 ctrl_outl((u32
)txdesc
, ioaddr
+ TDFXR
);
310 ctrl_outl(0x1, ioaddr
+ TDFFR
);
313 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
316 /* Get skb and descriptor buffer */
317 static int sh_eth_ring_init(struct net_device
*ndev
)
319 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
320 int rx_ringsize
, tx_ringsize
, ret
= 0;
323 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
324 * card needs room to do 8 byte alignment, +2 so we can reserve
325 * the first 2 bytes, and +16 gets room for the status word from the
328 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
329 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
331 /* Allocate RX and TX skb rings */
332 mdp
->rx_skbuff
= kmalloc(sizeof(*mdp
->rx_skbuff
) * RX_RING_SIZE
,
334 if (!mdp
->rx_skbuff
) {
335 printk(KERN_ERR
"%s: Cannot allocate Rx skb\n", ndev
->name
);
340 mdp
->tx_skbuff
= kmalloc(sizeof(*mdp
->tx_skbuff
) * TX_RING_SIZE
,
342 if (!mdp
->tx_skbuff
) {
343 printk(KERN_ERR
"%s: Cannot allocate Tx skb\n", ndev
->name
);
348 /* Allocate all Rx descriptors. */
349 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
350 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
354 printk(KERN_ERR
"%s: Cannot allocate Rx Ring (size %d bytes)\n",
355 ndev
->name
, rx_ringsize
);
362 /* Allocate all Tx descriptors. */
363 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
364 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
367 printk(KERN_ERR
"%s: Cannot allocate Tx Ring (size %d bytes)\n",
368 ndev
->name
, tx_ringsize
);
375 /* free DMA buffer */
376 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
379 /* Free Rx and Tx skb ring buffer */
380 sh_eth_ring_free(ndev
);
385 static int sh_eth_dev_init(struct net_device
*ndev
)
388 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
389 u32 ioaddr
= ndev
->base_addr
;
390 u_int32_t rx_int_var
, tx_int_var
;
396 /* Descriptor format */
397 sh_eth_ring_format(ndev
);
398 ctrl_outl(RPADIR_INIT
, ioaddr
+ RPADIR
);
400 /* all sh_eth int mask */
401 ctrl_outl(0, ioaddr
+ EESIPR
);
403 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
404 ctrl_outl(EDMR_EL
, ioaddr
+ EDMR
);
406 ctrl_outl(0, ioaddr
+ EDMR
); /* Endian change */
410 ctrl_outl((FIFO_SIZE_T
| FIFO_SIZE_R
), ioaddr
+ FDR
);
411 ctrl_outl(0, ioaddr
+ TFTR
);
413 /* Frame recv control */
414 ctrl_outl(0, ioaddr
+ RMCR
);
416 rx_int_var
= mdp
->rx_int_var
= DESC_I_RINT8
| DESC_I_RINT5
;
417 tx_int_var
= mdp
->tx_int_var
= DESC_I_TINT2
;
418 ctrl_outl(rx_int_var
| tx_int_var
, ioaddr
+ TRSCER
);
420 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
421 /* Burst sycle set */
422 ctrl_outl(0x800, ioaddr
+ BCULR
);
425 ctrl_outl((FIFO_F_D_RFF
| FIFO_F_D_RFD
), ioaddr
+ FCFTR
);
427 #if !defined(CONFIG_CPU_SUBTYPE_SH7763)
428 ctrl_outl(0, ioaddr
+ TRIMD
);
431 /* Recv frame limit set register */
432 ctrl_outl(RFLR_VALUE
, ioaddr
+ RFLR
);
434 ctrl_outl(ctrl_inl(ioaddr
+ EESR
), ioaddr
+ EESR
);
435 ctrl_outl((DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff), ioaddr
+ EESIPR
);
437 /* PAUSE Prohibition */
438 val
= (ctrl_inl(ioaddr
+ ECMR
) & ECMR_DM
) |
439 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
441 ctrl_outl(val
, ioaddr
+ ECMR
);
443 /* E-MAC Status Register clear */
444 ctrl_outl(ECSR_INIT
, ioaddr
+ ECSR
);
446 /* E-MAC Interrupt Enable register */
447 ctrl_outl(ECSIPR_INIT
, ioaddr
+ ECSIPR
);
449 /* Set MAC address */
450 update_mac_address(ndev
);
453 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7763)
454 ctrl_outl(APR_AP
, ioaddr
+ APR
);
455 ctrl_outl(MPR_MP
, ioaddr
+ MPR
);
456 ctrl_outl(TPAUSER_UNLIMITED
, ioaddr
+ TPAUSER
);
458 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
459 ctrl_outl(BCFR_UNLIMITED
, ioaddr
+ BCFR
);
462 /* Setting the Rx mode will start the Rx process. */
463 ctrl_outl(EDRRR_R
, ioaddr
+ EDRRR
);
465 netif_start_queue(ndev
);
470 /* free Tx skb function */
471 static int sh_eth_txfree(struct net_device
*ndev
)
473 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
474 struct sh_eth_txdesc
*txdesc
;
478 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
479 entry
= mdp
->dirty_tx
% TX_RING_SIZE
;
480 txdesc
= &mdp
->tx_ring
[entry
];
481 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
483 /* Free the original skb. */
484 if (mdp
->tx_skbuff
[entry
]) {
485 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
486 mdp
->tx_skbuff
[entry
] = NULL
;
489 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
490 if (entry
>= TX_RING_SIZE
- 1)
491 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
493 mdp
->stats
.tx_packets
++;
494 mdp
->stats
.tx_bytes
+= txdesc
->buffer_length
;
499 /* Packet receive function */
500 static int sh_eth_rx(struct net_device
*ndev
)
502 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
503 struct sh_eth_rxdesc
*rxdesc
;
505 int entry
= mdp
->cur_rx
% RX_RING_SIZE
;
506 int boguscnt
= (mdp
->dirty_rx
+ RX_RING_SIZE
) - mdp
->cur_rx
;
509 u32 desc_status
, reserve
= 0;
511 rxdesc
= &mdp
->rx_ring
[entry
];
512 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
513 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
514 pkt_len
= rxdesc
->frame_length
;
519 if (!(desc_status
& RDFEND
))
520 mdp
->stats
.rx_length_errors
++;
522 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
523 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
524 mdp
->stats
.rx_errors
++;
525 if (desc_status
& RD_RFS1
)
526 mdp
->stats
.rx_crc_errors
++;
527 if (desc_status
& RD_RFS2
)
528 mdp
->stats
.rx_frame_errors
++;
529 if (desc_status
& RD_RFS3
)
530 mdp
->stats
.rx_length_errors
++;
531 if (desc_status
& RD_RFS4
)
532 mdp
->stats
.rx_length_errors
++;
533 if (desc_status
& RD_RFS6
)
534 mdp
->stats
.rx_missed_errors
++;
535 if (desc_status
& RD_RFS10
)
536 mdp
->stats
.rx_over_errors
++;
538 swaps((char *)(rxdesc
->addr
& ~0x3), pkt_len
+ 2);
539 skb
= mdp
->rx_skbuff
[entry
];
540 mdp
->rx_skbuff
[entry
] = NULL
;
541 skb_put(skb
, pkt_len
);
542 skb
->protocol
= eth_type_trans(skb
, ndev
);
544 ndev
->last_rx
= jiffies
;
545 mdp
->stats
.rx_packets
++;
546 mdp
->stats
.rx_bytes
+= pkt_len
;
548 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
549 entry
= (++mdp
->cur_rx
) % RX_RING_SIZE
;
552 /* Refill the Rx ring buffers. */
553 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
554 entry
= mdp
->dirty_rx
% RX_RING_SIZE
;
555 rxdesc
= &mdp
->rx_ring
[entry
];
556 /* The size of the buffer is 16 byte boundary. */
557 rxdesc
->buffer_length
= (mdp
->rx_buf_sz
+ 16) & ~0x0F;
559 if (mdp
->rx_skbuff
[entry
] == NULL
) {
560 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
561 mdp
->rx_skbuff
[entry
] = skb
;
563 break; /* Better luck next round. */
565 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
566 reserve
= SH7763_SKB_ALIGN
567 - ((uint32_t)skb
->data
& (SH7763_SKB_ALIGN
-1));
569 skb_reserve(skb
, reserve
);
571 skb_reserve(skb
, RX_OFFSET
);
573 skb
->ip_summed
= CHECKSUM_NONE
;
574 rxdesc
->addr
= (u32
)skb
->data
& ~0x3UL
;
576 if (entry
>= RX_RING_SIZE
- 1)
578 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
581 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
584 /* Restart Rx engine if stopped. */
585 /* If we don't need to check status, don't. -KDU */
586 if (!(ctrl_inl(ndev
->base_addr
+ EDRRR
) & EDRRR_R
))
587 ctrl_outl(EDRRR_R
, ndev
->base_addr
+ EDRRR
);
592 /* error control function */
593 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
595 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
596 u32 ioaddr
= ndev
->base_addr
;
599 if (intr_status
& EESR_ECI
) {
600 felic_stat
= ctrl_inl(ioaddr
+ ECSR
);
601 ctrl_outl(felic_stat
, ioaddr
+ ECSR
); /* clear int */
602 if (felic_stat
& ECSR_ICD
)
603 mdp
->stats
.tx_carrier_errors
++;
604 if (felic_stat
& ECSR_LCHNG
) {
606 u32 link_stat
= (ctrl_inl(ioaddr
+ PSR
));
607 if (!(link_stat
& PHY_ST_LINK
)) {
608 /* Link Down : disable tx and rx */
609 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) &
610 ~(ECMR_RE
| ECMR_TE
), ioaddr
+ ECMR
);
613 ctrl_outl(ctrl_inl(ioaddr
+ EESIPR
) &
614 ~DMAC_M_ECI
, ioaddr
+ EESIPR
);
616 ctrl_outl(ctrl_inl(ioaddr
+ ECSR
),
618 ctrl_outl(ctrl_inl(ioaddr
+ EESIPR
) |
619 DMAC_M_ECI
, ioaddr
+ EESIPR
);
620 /* enable tx and rx */
621 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) |
622 (ECMR_RE
| ECMR_TE
), ioaddr
+ ECMR
);
627 if (intr_status
& EESR_TWB
) {
628 /* Write buck end. unused write back interrupt */
629 if (intr_status
& EESR_TABT
) /* Transmit Abort int */
630 mdp
->stats
.tx_aborted_errors
++;
633 if (intr_status
& EESR_RABT
) {
634 /* Receive Abort int */
635 if (intr_status
& EESR_RFRMER
) {
636 /* Receive Frame Overflow int */
637 mdp
->stats
.rx_frame_errors
++;
638 printk(KERN_ERR
"Receive Frame Overflow\n");
641 #if !defined(CONFIG_CPU_SUBTYPE_SH7763)
642 if (intr_status
& EESR_ADE
) {
643 if (intr_status
& EESR_TDE
) {
644 if (intr_status
& EESR_TFE
)
645 mdp
->stats
.tx_fifo_errors
++;
650 if (intr_status
& EESR_RDE
) {
651 /* Receive Descriptor Empty int */
652 mdp
->stats
.rx_over_errors
++;
654 if (ctrl_inl(ioaddr
+ EDRRR
) ^ EDRRR_R
)
655 ctrl_outl(EDRRR_R
, ioaddr
+ EDRRR
);
656 printk(KERN_ERR
"Receive Descriptor Empty\n");
658 if (intr_status
& EESR_RFE
) {
659 /* Receive FIFO Overflow int */
660 mdp
->stats
.rx_fifo_errors
++;
661 printk(KERN_ERR
"Receive FIFO Overflow\n");
663 if (intr_status
& (EESR_TWB
| EESR_TABT
|
664 #if !defined(CONFIG_CPU_SUBTYPE_SH7763)
667 EESR_TDE
| EESR_TFE
)) {
669 u32 edtrr
= ctrl_inl(ndev
->base_addr
+ EDTRR
);
671 printk(KERN_ERR
"%s:TX error. status=%8.8x cur_tx=%8.8x ",
672 ndev
->name
, intr_status
, mdp
->cur_tx
);
673 printk(KERN_ERR
"dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
674 mdp
->dirty_tx
, (u32
) ndev
->state
, edtrr
);
675 /* dirty buffer free */
679 if (edtrr
^ EDTRR_TRNS
) {
681 ctrl_outl(EDTRR_TRNS
, ndev
->base_addr
+ EDTRR
);
684 netif_wake_queue(ndev
);
688 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
690 struct net_device
*ndev
= netdev
;
691 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
692 u32 ioaddr
, boguscnt
= RX_RING_SIZE
;
695 ioaddr
= ndev
->base_addr
;
696 spin_lock(&mdp
->lock
);
698 /* Get interrpt stat */
699 intr_status
= ctrl_inl(ioaddr
+ EESR
);
700 /* Clear interrupt */
701 ctrl_outl(intr_status
, ioaddr
+ EESR
);
703 if (intr_status
& (EESR_FRC
| /* Frame recv*/
704 EESR_RMAF
| /* Multi cast address recv*/
705 EESR_RRF
| /* Bit frame recv */
706 EESR_RTLF
| /* Long frame recv*/
707 EESR_RTSF
| /* short frame recv */
708 EESR_PRE
| /* PHY-LSI recv error */
709 EESR_CERF
)){ /* recv frame CRC error */
714 if (intr_status
& TX_CHECK
) {
716 netif_wake_queue(ndev
);
719 if (intr_status
& EESR_ERR_CHECK
)
720 sh_eth_error(ndev
, intr_status
);
722 if (--boguscnt
< 0) {
724 "%s: Too much work at interrupt, status=0x%4.4x.\n",
725 ndev
->name
, intr_status
);
728 spin_unlock(&mdp
->lock
);
733 static void sh_eth_timer(unsigned long data
)
735 struct net_device
*ndev
= (struct net_device
*)data
;
736 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
738 mod_timer(&mdp
->timer
, jiffies
+ (10 * HZ
));
741 /* PHY state control function */
742 static void sh_eth_adjust_link(struct net_device
*ndev
)
744 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
745 struct phy_device
*phydev
= mdp
->phydev
;
746 u32 ioaddr
= ndev
->base_addr
;
749 if (phydev
->link
!= PHY_DOWN
) {
750 if (phydev
->duplex
!= mdp
->duplex
) {
752 mdp
->duplex
= phydev
->duplex
;
753 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
754 if (mdp
->duplex
) { /* FULL */
755 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) | ECMR_DM
,
758 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_DM
,
764 if (phydev
->speed
!= mdp
->speed
) {
766 mdp
->speed
= phydev
->speed
;
767 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
768 switch (mdp
->speed
) {
769 case 10: /* 10BASE */
770 ctrl_outl(GECMR_10
, ioaddr
+ GECMR
); break;
771 case 100:/* 100BASE */
772 ctrl_outl(GECMR_100
, ioaddr
+ GECMR
); break;
773 case 1000: /* 1000BASE */
774 ctrl_outl(GECMR_1000
, ioaddr
+ GECMR
); break;
780 if (mdp
->link
== PHY_DOWN
) {
781 ctrl_outl((ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_TXF
)
782 | ECMR_DM
, ioaddr
+ ECMR
);
784 mdp
->link
= phydev
->link
;
786 } else if (mdp
->link
) {
788 mdp
->link
= PHY_DOWN
;
794 phy_print_status(phydev
);
797 /* PHY init function */
798 static int sh_eth_phy_init(struct net_device
*ndev
)
800 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
801 char phy_id
[BUS_ID_SIZE
];
802 struct phy_device
*phydev
= NULL
;
804 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
,
805 mdp
->mii_bus
->id
, mdp
->phy_id
);
807 mdp
->link
= PHY_DOWN
;
811 /* Try connect to PHY */
812 phydev
= phy_connect(ndev
, phy_id
, &sh_eth_adjust_link
,
813 0, PHY_INTERFACE_MODE_MII
);
814 if (IS_ERR(phydev
)) {
815 dev_err(&ndev
->dev
, "phy_connect failed\n");
816 return PTR_ERR(phydev
);
818 dev_info(&ndev
->dev
, "attached phy %i to driver %s\n",
819 phydev
->addr
, phydev
->drv
->name
);
821 mdp
->phydev
= phydev
;
826 /* PHY control start function */
827 static int sh_eth_phy_start(struct net_device
*ndev
)
829 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
832 ret
= sh_eth_phy_init(ndev
);
836 /* reset phy - this also wakes it from PDOWN */
837 phy_write(mdp
->phydev
, MII_BMCR
, BMCR_RESET
);
838 phy_start(mdp
->phydev
);
843 /* network device open function */
844 static int sh_eth_open(struct net_device
*ndev
)
847 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
849 ret
= request_irq(ndev
->irq
, &sh_eth_interrupt
, 0, ndev
->name
, ndev
);
851 printk(KERN_ERR
"Can not assign IRQ number to %s\n", CARDNAME
);
856 ret
= sh_eth_ring_init(ndev
);
861 ret
= sh_eth_dev_init(ndev
);
865 /* PHY control start*/
866 ret
= sh_eth_phy_start(ndev
);
870 /* Set the timer to check for link beat. */
871 init_timer(&mdp
->timer
);
872 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
873 setup_timer(&mdp
->timer
, sh_eth_timer
, (unsigned long)ndev
);
878 free_irq(ndev
->irq
, ndev
);
882 /* Timeout function */
883 static void sh_eth_tx_timeout(struct net_device
*ndev
)
885 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
886 u32 ioaddr
= ndev
->base_addr
;
887 struct sh_eth_rxdesc
*rxdesc
;
890 netif_stop_queue(ndev
);
892 /* worning message out. */
893 printk(KERN_WARNING
"%s: transmit timed out, status %8.8x,"
894 " resetting...\n", ndev
->name
, (int)ctrl_inl(ioaddr
+ EESR
));
896 /* tx_errors count up */
897 mdp
->stats
.tx_errors
++;
900 del_timer_sync(&mdp
->timer
);
902 /* Free all the skbuffs in the Rx queue. */
903 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
904 rxdesc
= &mdp
->rx_ring
[i
];
906 rxdesc
->addr
= 0xBADF00D0;
907 if (mdp
->rx_skbuff
[i
])
908 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
909 mdp
->rx_skbuff
[i
] = NULL
;
911 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
912 if (mdp
->tx_skbuff
[i
])
913 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
914 mdp
->tx_skbuff
[i
] = NULL
;
918 sh_eth_dev_init(ndev
);
921 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
922 add_timer(&mdp
->timer
);
925 /* Packet transmit function */
926 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
928 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
929 struct sh_eth_txdesc
*txdesc
;
933 spin_lock_irqsave(&mdp
->lock
, flags
);
934 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (TX_RING_SIZE
- 4)) {
935 if (!sh_eth_txfree(ndev
)) {
936 netif_stop_queue(ndev
);
937 spin_unlock_irqrestore(&mdp
->lock
, flags
);
941 spin_unlock_irqrestore(&mdp
->lock
, flags
);
943 entry
= mdp
->cur_tx
% TX_RING_SIZE
;
944 mdp
->tx_skbuff
[entry
] = skb
;
945 txdesc
= &mdp
->tx_ring
[entry
];
946 txdesc
->addr
= (u32
)(skb
->data
);
948 swaps((char *)(txdesc
->addr
& ~0x3), skb
->len
+ 2);
950 __flush_purge_region(skb
->data
, skb
->len
);
951 if (skb
->len
< ETHERSMALL
)
952 txdesc
->buffer_length
= ETHERSMALL
;
954 txdesc
->buffer_length
= skb
->len
;
956 if (entry
>= TX_RING_SIZE
- 1)
957 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
959 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
963 if (!(ctrl_inl(ndev
->base_addr
+ EDTRR
) & EDTRR_TRNS
))
964 ctrl_outl(EDTRR_TRNS
, ndev
->base_addr
+ EDTRR
);
966 ndev
->trans_start
= jiffies
;
971 /* device close function */
972 static int sh_eth_close(struct net_device
*ndev
)
974 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
975 u32 ioaddr
= ndev
->base_addr
;
978 netif_stop_queue(ndev
);
980 /* Disable interrupts by clearing the interrupt mask. */
981 ctrl_outl(0x0000, ioaddr
+ EESIPR
);
983 /* Stop the chip's Tx and Rx processes. */
984 ctrl_outl(0, ioaddr
+ EDTRR
);
985 ctrl_outl(0, ioaddr
+ EDRRR
);
989 phy_stop(mdp
->phydev
);
990 phy_disconnect(mdp
->phydev
);
993 free_irq(ndev
->irq
, ndev
);
995 del_timer_sync(&mdp
->timer
);
997 /* Free all the skbuffs in the Rx queue. */
998 sh_eth_ring_free(ndev
);
1000 /* free DMA buffer */
1001 ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
1002 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1004 /* free DMA buffer */
1005 ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
1006 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
, mdp
->tx_desc_dma
);
1011 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
1013 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1014 u32 ioaddr
= ndev
->base_addr
;
1016 mdp
->stats
.tx_dropped
+= ctrl_inl(ioaddr
+ TROCR
);
1017 ctrl_outl(0, ioaddr
+ TROCR
); /* (write clear) */
1018 mdp
->stats
.collisions
+= ctrl_inl(ioaddr
+ CDCR
);
1019 ctrl_outl(0, ioaddr
+ CDCR
); /* (write clear) */
1020 mdp
->stats
.tx_carrier_errors
+= ctrl_inl(ioaddr
+ LCCR
);
1021 ctrl_outl(0, ioaddr
+ LCCR
); /* (write clear) */
1022 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1023 mdp
->stats
.tx_carrier_errors
+= ctrl_inl(ioaddr
+ CERCR
);/* CERCR */
1024 ctrl_outl(0, ioaddr
+ CERCR
); /* (write clear) */
1025 mdp
->stats
.tx_carrier_errors
+= ctrl_inl(ioaddr
+ CEECR
);/* CEECR */
1026 ctrl_outl(0, ioaddr
+ CEECR
); /* (write clear) */
1028 mdp
->stats
.tx_carrier_errors
+= ctrl_inl(ioaddr
+ CNDCR
);
1029 ctrl_outl(0, ioaddr
+ CNDCR
); /* (write clear) */
1034 /* ioctl to device funciotn*/
1035 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
,
1038 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1039 struct phy_device
*phydev
= mdp
->phydev
;
1041 if (!netif_running(ndev
))
1047 return phy_mii_ioctl(phydev
, if_mii(rq
), cmd
);
1051 /* Multicast reception directions set */
1052 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
1054 u32 ioaddr
= ndev
->base_addr
;
1056 if (ndev
->flags
& IFF_PROMISC
) {
1057 /* Set promiscuous. */
1058 ctrl_outl((ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_MCT
) | ECMR_PRM
,
1061 /* Normal, unicast/broadcast-only mode. */
1062 ctrl_outl((ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_PRM
) | ECMR_MCT
,
1067 /* SuperH's TSU register init function */
1068 static void sh_eth_tsu_init(u32 ioaddr
)
1070 ctrl_outl(0, ioaddr
+ TSU_FWEN0
); /* Disable forward(0->1) */
1071 ctrl_outl(0, ioaddr
+ TSU_FWEN1
); /* Disable forward(1->0) */
1072 ctrl_outl(0, ioaddr
+ TSU_FCM
); /* forward fifo 3k-3k */
1073 ctrl_outl(0xc, ioaddr
+ TSU_BSYSL0
);
1074 ctrl_outl(0xc, ioaddr
+ TSU_BSYSL1
);
1075 ctrl_outl(0, ioaddr
+ TSU_PRISL0
);
1076 ctrl_outl(0, ioaddr
+ TSU_PRISL1
);
1077 ctrl_outl(0, ioaddr
+ TSU_FWSL0
);
1078 ctrl_outl(0, ioaddr
+ TSU_FWSL1
);
1079 ctrl_outl(TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, ioaddr
+ TSU_FWSLC
);
1080 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1081 ctrl_outl(0, ioaddr
+ TSU_QTAG0
); /* Disable QTAG(0->1) */
1082 ctrl_outl(0, ioaddr
+ TSU_QTAG1
); /* Disable QTAG(1->0) */
1084 ctrl_outl(0, ioaddr
+ TSU_QTAGM0
); /* Disable QTAG(0->1) */
1085 ctrl_outl(0, ioaddr
+ TSU_QTAGM1
); /* Disable QTAG(1->0) */
1087 ctrl_outl(0, ioaddr
+ TSU_FWSR
); /* all interrupt status clear */
1088 ctrl_outl(0, ioaddr
+ TSU_FWINMK
); /* Disable all interrupt */
1089 ctrl_outl(0, ioaddr
+ TSU_TEN
); /* Disable all CAM entry */
1090 ctrl_outl(0, ioaddr
+ TSU_POST1
); /* Disable CAM entry [ 0- 7] */
1091 ctrl_outl(0, ioaddr
+ TSU_POST2
); /* Disable CAM entry [ 8-15] */
1092 ctrl_outl(0, ioaddr
+ TSU_POST3
); /* Disable CAM entry [16-23] */
1093 ctrl_outl(0, ioaddr
+ TSU_POST4
); /* Disable CAM entry [24-31] */
1096 /* MDIO bus release function */
1097 static int sh_mdio_release(struct net_device
*ndev
)
1099 struct mii_bus
*bus
= dev_get_drvdata(&ndev
->dev
);
1101 /* unregister mdio bus */
1102 mdiobus_unregister(bus
);
1104 /* remove mdio bus info from net_device */
1105 dev_set_drvdata(&ndev
->dev
, NULL
);
1107 /* free bitbang info */
1108 free_mdio_bitbang(bus
);
1113 /* MDIO bus init function */
1114 static int sh_mdio_init(struct net_device
*ndev
, int id
)
1117 struct bb_info
*bitbang
;
1118 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1120 /* create bit control struct for PHY */
1121 bitbang
= kzalloc(sizeof(struct bb_info
), GFP_KERNEL
);
1128 bitbang
->addr
= ndev
->base_addr
+ PIR
;
1129 bitbang
->mdi_msk
= 0x08;
1130 bitbang
->mdo_msk
= 0x04;
1131 bitbang
->mmd_msk
= 0x02;/* MMD */
1132 bitbang
->mdc_msk
= 0x01;
1133 bitbang
->ctrl
.ops
= &bb_ops
;
1135 /* MII contorller setting */
1136 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
1137 if (!mdp
->mii_bus
) {
1139 goto out_free_bitbang
;
1142 /* Hook up MII support for ethtool */
1143 mdp
->mii_bus
->name
= "sh_mii";
1144 mdp
->mii_bus
->dev
= &ndev
->dev
;
1145 mdp
->mii_bus
->id
[0] = id
;
1148 mdp
->mii_bus
->irq
= kmalloc(sizeof(int)*PHY_MAX_ADDR
, GFP_KERNEL
);
1149 if (!mdp
->mii_bus
->irq
) {
1154 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1155 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
1157 /* regist mdio bus */
1158 ret
= mdiobus_register(mdp
->mii_bus
);
1162 dev_set_drvdata(&ndev
->dev
, mdp
->mii_bus
);
1167 kfree(mdp
->mii_bus
->irq
);
1170 kfree(mdp
->mii_bus
);
1179 static int sh_eth_drv_probe(struct platform_device
*pdev
)
1181 int ret
, i
, devno
= 0;
1182 struct resource
*res
;
1183 struct net_device
*ndev
= NULL
;
1184 struct sh_eth_private
*mdp
;
1185 struct sh_eth_plat_data
*pd
;
1188 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1189 if (unlikely(res
== NULL
)) {
1190 dev_err(&pdev
->dev
, "invalid resource\n");
1195 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
1197 printk(KERN_ERR
"%s: could not allocate device.\n", CARDNAME
);
1202 /* The sh Ether-specific entries in the device structure. */
1203 ndev
->base_addr
= res
->start
;
1209 ndev
->irq
= platform_get_irq(pdev
, 0);
1210 if (ndev
->irq
< 0) {
1215 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1217 /* Fill in the fields of the device structure with ethernet values. */
1220 mdp
= netdev_priv(ndev
);
1221 spin_lock_init(&mdp
->lock
);
1223 pd
= (struct sh_eth_plat_data
*)(pdev
->dev
.platform_data
);
1225 mdp
->phy_id
= pd
->phy
;
1227 mdp
->edmac_endian
= pd
->edmac_endian
;
1230 ndev
->open
= sh_eth_open
;
1231 ndev
->hard_start_xmit
= sh_eth_start_xmit
;
1232 ndev
->stop
= sh_eth_close
;
1233 ndev
->get_stats
= sh_eth_get_stats
;
1234 ndev
->set_multicast_list
= sh_eth_set_multicast_list
;
1235 ndev
->do_ioctl
= sh_eth_do_ioctl
;
1236 ndev
->tx_timeout
= sh_eth_tx_timeout
;
1237 ndev
->watchdog_timeo
= TX_TIMEOUT
;
1239 mdp
->post_rx
= POST_RX
>> (devno
<< 1);
1240 mdp
->post_fw
= POST_FW
>> (devno
<< 1);
1242 /* read and set MAC address */
1243 read_mac_address(ndev
);
1245 /* First device only init */
1249 ctrl_outl(ARSTR_ARSTR
, ARSTR
);
1253 #if defined(SH_TSU_ADDR)
1254 /* TSU init (Init only)*/
1255 sh_eth_tsu_init(SH_TSU_ADDR
);
1259 /* network device register */
1260 ret
= register_netdev(ndev
);
1265 ret
= sh_mdio_init(ndev
, pdev
->id
);
1267 goto out_unregister
;
1269 /* pritnt device infomation */
1270 printk(KERN_INFO
"%s: %s at 0x%x, ",
1271 ndev
->name
, CARDNAME
, (u32
) ndev
->base_addr
);
1273 for (i
= 0; i
< 5; i
++)
1274 printk("%02X:", ndev
->dev_addr
[i
]);
1275 printk("%02X, IRQ %d.\n", ndev
->dev_addr
[i
], ndev
->irq
);
1277 platform_set_drvdata(pdev
, ndev
);
1282 unregister_netdev(ndev
);
1293 static int sh_eth_drv_remove(struct platform_device
*pdev
)
1295 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1297 sh_mdio_release(ndev
);
1298 unregister_netdev(ndev
);
1299 flush_scheduled_work();
1302 platform_set_drvdata(pdev
, NULL
);
1307 static struct platform_driver sh_eth_driver
= {
1308 .probe
= sh_eth_drv_probe
,
1309 .remove
= sh_eth_drv_remove
,
1315 static int __init
sh_eth_init(void)
1317 return platform_driver_register(&sh_eth_driver
);
1320 static void __exit
sh_eth_cleanup(void)
1322 platform_driver_unregister(&sh_eth_driver
);
1325 module_init(sh_eth_init
);
1326 module_exit(sh_eth_cleanup
);
1328 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1329 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1330 MODULE_LICENSE("GPL v2");