drivers/net/sh_eth.h

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2008 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008 Renesas Solutions Corp.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms and conditions of the GNU General Public License,
   9  *  version 2, as published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  *  more details.
  15  *  You should have received a copy of the GNU General Public License along with
  16  *  this program; if not, write to the Free Software Foundation, Inc.,
  17  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *  The full GNU General Public License is included in this distribution in
  20  *  the file called "COPYING".
  21  */
  22
  23 #ifndef __SH_ETH_H__
  24 #define __SH_ETH_H__
  25
  26 #include <linux/module.h>
  27 #include <linux/kernel.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/phy.h>
  32
  33 #define CARDNAME        "sh-eth"
  34 #define TX_TIMEOUT      (5*HZ)
  35 #define TX_RING_SIZE    64      /* Tx ring size */
  36 #define RX_RING_SIZE    64      /* Rx ring size */
  37 #define ETHERSMALL              60
  38 #define PKT_BUF_SZ              1538
  39
  40 #ifdef CONFIG_CPU_SUBTYPE_SH7763
  41
  42 #define SH7763_SKB_ALIGN 32
  43 /* Chip Base Address */
  44 # define SH_TSU_ADDR  0xFFE01800
  45 # define ARSTR            0xFFE01800
  46
  47 /* Chip Registers */
  48 /* E-DMAC */
  49 # define EDSR    0x000
  50 # define EDMR    0x400
  51 # define EDTRR   0x408
  52 # define EDRRR   0x410
  53 # define EESR    0x428
  54 # define EESIPR  0x430
  55 # define TDLAR   0x010
  56 # define TDFAR   0x014
  57 # define TDFXR   0x018
  58 # define TDFFR   0x01C
  59 # define RDLAR   0x030
  60 # define RDFAR   0x034
  61 # define RDFXR   0x038
  62 # define RDFFR   0x03C
  63 # define TRSCER  0x438
  64 # define RMFCR   0x440
  65 # define TFTR    0x448
  66 # define FDR     0x450
  67 # define RMCR    0x458
  68 # define RPADIR  0x460
  69 # define FCFTR   0x468
  70
  71 /* Ether Register */
  72 # define ECMR    0x500
  73 # define ECSR    0x510
  74 # define ECSIPR  0x518
  75 # define PIR     0x520
  76 # define PSR     0x528
  77 # define PIPR    0x52C
  78 # define RFLR    0x508
  79 # define APR     0x554
  80 # define MPR     0x558
  81 # define PFTCR   0x55C
  82 # define PFRCR   0x560
  83 # define TPAUSER 0x564
  84 # define GECMR   0x5B0
  85 # define BCULR   0x5B4
  86 # define MAHR    0x5C0
  87 # define MALR    0x5C8
  88 # define TROCR   0x700
  89 # define CDCR    0x708
  90 # define LCCR    0x710
  91 # define CEFCR   0x740
  92 # define FRECR   0x748
  93 # define TSFRCR  0x750
  94 # define TLFRCR  0x758
  95 # define RFCR    0x760
  96 # define CERCR   0x768
  97 # define CEECR   0x770
  98 # define MAFCR   0x778
  99
 100 /* TSU Absolute Address */
 101 # define TSU_CTRST       0x004
 102 # define TSU_FWEN0       0x010
 103 # define TSU_FWEN1       0x014
 104 # define TSU_FCM         0x18
 105 # define TSU_BSYSL0      0x20
 106 # define TSU_BSYSL1      0x24
 107 # define TSU_PRISL0      0x28
 108 # define TSU_PRISL1      0x2C
 109 # define TSU_FWSL0       0x30
 110 # define TSU_FWSL1       0x34
 111 # define TSU_FWSLC       0x38
 112 # define TSU_QTAG0       0x40
 113 # define TSU_QTAG1       0x44
 114 # define TSU_FWSR        0x50
 115 # define TSU_FWINMK      0x54
 116 # define TSU_ADQT0       0x48
 117 # define TSU_ADQT1       0x4C
 118 # define TSU_VTAG0       0x58
 119 # define TSU_VTAG1       0x5C
 120 # define TSU_ADSBSY      0x60
 121 # define TSU_TEN         0x64
 122 # define TSU_POST1       0x70
 123 # define TSU_POST2       0x74
 124 # define TSU_POST3       0x78
 125 # define TSU_POST4       0x7C
 126 # define TSU_ADRH0       0x100
 127 # define TSU_ADRL0       0x104
 128 # define TSU_ADRH31      0x1F8
 129 # define TSU_ADRL31      0x1FC
 130
 131 # define TXNLCR0         0x80
 132 # define TXALCR0         0x84
 133 # define RXNLCR0         0x88
 134 # define RXALCR0         0x8C
 135 # define FWNLCR0         0x90
 136 # define FWALCR0         0x94
 137 # define TXNLCR1         0xA0
 138 # define TXALCR1         0xA4
 139 # define RXNLCR1         0xA8
 140 # define RXALCR1         0xAC
 141 # define FWNLCR1         0xB0
 142 # define FWALCR1         0x40
 143
 144 #else /* CONFIG_CPU_SUBTYPE_SH7763 */
 145 # define RX_OFFSET 2    /* skb offset */
 146 /* Chip base address */
 147 # define SH_TSU_ADDR  0xA7000804
 148 # define ARSTR            0xA7000800
 149
 150 /* Chip Registers */
 151 /* E-DMAC */
 152 # define EDMR   0x0000
 153 # define EDTRR  0x0004
 154 # define EDRRR  0x0008
 155 # define TDLAR  0x000C
 156 # define RDLAR  0x0010
 157 # define EESR   0x0014
 158 # define EESIPR 0x0018
 159 # define TRSCER 0x001C
 160 # define RMFCR  0x0020
 161 # define TFTR   0x0024
 162 # define FDR    0x0028
 163 # define RMCR   0x002C
 164 # define EDOCR  0x0030
 165 # define FCFTR  0x0034
 166 # define RPADIR 0x0038
 167 # define TRIMD  0x003C
 168 # define RBWAR  0x0040
 169 # define RDFAR  0x0044
 170 # define TBRAR  0x004C
 171 # define TDFAR  0x0050
 172
 173 /* Ether Register */
 174 # define ECMR   0x0160
 175 # define ECSR   0x0164
 176 # define ECSIPR 0x0168
 177 # define PIR    0x016C
 178 # define MAHR   0x0170
 179 # define MALR   0x0174
 180 # define RFLR   0x0178
 181 # define PSR    0x017C
 182 # define TROCR  0x0180
 183 # define CDCR   0x0184
 184 # define LCCR   0x0188
 185 # define CNDCR  0x018C
 186 # define CEFCR  0x0194
 187 # define FRECR  0x0198
 188 # define TSFRCR 0x019C
 189 # define TLFRCR 0x01A0
 190 # define RFCR   0x01A4
 191 # define MAFCR  0x01A8
 192 # define IPGR   0x01B4
 193 # if defined(CONFIG_CPU_SUBTYPE_SH7710)
 194 # define APR    0x01B8
 195 # define MPR    0x01BC
 196 # define TPAUSER 0x1C4
 197 # define BCFR   0x1CC
 198 # endif /* CONFIG_CPU_SH7710 */
 199
 200 /* TSU */
 201 # define TSU_CTRST      0x004
 202 # define TSU_FWEN0      0x010
 203 # define TSU_FWEN1      0x014
 204 # define TSU_FCM        0x018
 205 # define TSU_BSYSL0     0x020
 206 # define TSU_BSYSL1     0x024
 207 # define TSU_PRISL0     0x028
 208 # define TSU_PRISL1     0x02C
 209 # define TSU_FWSL0      0x030
 210 # define TSU_FWSL1      0x034
 211 # define TSU_FWSLC      0x038
 212 # define TSU_QTAGM0     0x040
 213 # define TSU_QTAGM1     0x044
 214 # define TSU_ADQT0      0x048
 215 # define TSU_ADQT1      0x04C
 216 # define TSU_FWSR       0x050
 217 # define TSU_FWINMK     0x054
 218 # define TSU_ADSBSY     0x060
 219 # define TSU_TEN        0x064
 220 # define TSU_POST1      0x070
 221 # define TSU_POST2      0x074
 222 # define TSU_POST3      0x078
 223 # define TSU_POST4      0x07C
 224 # define TXNLCR0        0x080
 225 # define TXALCR0        0x084
 226 # define RXNLCR0        0x088
 227 # define RXALCR0        0x08C
 228 # define FWNLCR0        0x090
 229 # define FWALCR0        0x094
 230 # define TXNLCR1        0x0A0
 231 # define TXALCR1        0x0A4
 232 # define RXNLCR1        0x0A8
 233 # define RXALCR1        0x0AC
 234 # define FWNLCR1        0x0B0
 235 # define FWALCR1        0x0B4
 236
 237 #define TSU_ADRH0       0x0100
 238 #define TSU_ADRL0       0x0104
 239 #define TSU_ADRL31      0x01FC
 240
 241 #endif /* CONFIG_CPU_SUBTYPE_SH7763 */
 242
 243 /*
 244  * Register's bits
 245  */
 246 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 247 /* EDSR */
 248 enum EDSR_BIT {
 249         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 250 };
 251 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 252
 253 /* GECMR */
 254 enum GECMR_BIT {
 255         GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
 256 };
 257 #endif
 258
 259 /* EDMR */
 260 enum DMAC_M_BIT {
 261         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 262 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 263         EDMR_SRST       = 0x03,
 264         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 265         EDMR_EL         = 0x40, /* Litte endian */
 266 #else /* CONFIG_CPU_SUBTYPE_SH7763 */
 267         EDMR_SRST = 0x01,
 268 #endif
 269 };
 270
 271 /* EDTRR */
 272 enum DMAC_T_BIT {
 273 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 274         EDTRR_TRNS = 0x03,
 275 #else
 276         EDTRR_TRNS = 0x01,
 277 #endif
 278 };
 279
 280 /* EDRRR*/
 281 enum EDRRR_R_BIT {
 282         EDRRR_R = 0x01,
 283 };
 284
 285 /* TPAUSER */
 286 enum TPAUSER_BIT {
 287         TPAUSER_TPAUSE = 0x0000ffff,
 288         TPAUSER_UNLIMITED = 0,
 289 };
 290
 291 /* BCFR */
 292 enum BCFR_BIT {
 293         BCFR_RPAUSE = 0x0000ffff,
 294         BCFR_UNLIMITED = 0,
 295 };
 296
 297 /* PIR */
 298 enum PIR_BIT {
 299         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 300 };
 301
 302 /* PSR */
 303 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 304
 305 /* EESR */
 306 enum EESR_BIT {
 307 #ifndef CONFIG_CPU_SUBTYPE_SH7763
 308         EESR_TWB  = 0x40000000,
 309 #else
 310         EESR_TWB  = 0xC0000000,
 311         EESR_TC1  = 0x20000000,
 312         EESR_TUC  = 0x10000000,
 313         EESR_ROC  = 0x80000000,
 314 #endif
 315         EESR_TABT = 0x04000000,
 316         EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
 317 #ifndef CONFIG_CPU_SUBTYPE_SH7763
 318         EESR_ADE  = 0x00800000,
 319 #endif
 320         EESR_ECI  = 0x00400000,
 321         EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 322         EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 323         EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
 324 #ifndef CONFIG_CPU_SUBTYPE_SH7763
 325         EESR_CND  = 0x00000800,
 326 #endif
 327         EESR_DLC  = 0x00000400,
 328         EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
 329         EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
 330         EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
 331         EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
 332         EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
 333 };
 334
 335
 336 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 337 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 338 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 339                 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
 340 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
 341
 342 #else
 343 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
 344 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 345                 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
 346 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
 347 #endif
 348
 349 /* EESIPR */
 350 enum DMAC_IM_BIT {
 351         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 352         DMAC_M_RABT = 0x02000000,
 353         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 354         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 355         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 356         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 357         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 358         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 359         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 360         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 361         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 362         DMAC_M_RINT1 = 0x00000001,
 363 };
 364
 365 /* Receive descriptor bit */
 366 enum RD_STS_BIT {
 367         RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
 368         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 369         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 370         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 371         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 372         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 373         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 374         RD_RFS1 = 0x00000001,
 375 };
 376 #define RDF1ST  RD_RFP1
 377 #define RDFEND  RD_RFP0
 378 #define RD_RFP  (RD_RFP1|RD_RFP0)
 379
 380 /* FCFTR */
 381 enum FCFTR_BIT {
 382         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 383         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 384         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 385 };
 386 #define FIFO_F_D_RFF    (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
 387 #define FIFO_F_D_RFD    (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
 388
 389 /* Transfer descriptor bit */
 390 enum TD_STS_BIT {
 391         TD_TACT = 0x80000000,
 392         TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 393         TD_TFP0 = 0x10000000,
 394 };
 395 #define TDF1ST  TD_TFP1
 396 #define TDFEND  TD_TFP0
 397 #define TD_TFP  (TD_TFP1|TD_TFP0)
 398
 399 /* RMCR */
 400 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 401 /* ECMR */
 402 enum FELIC_MODE_BIT {
 403 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 404         ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 405         ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 406 #endif
 407         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 408         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 409         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 410         ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
 411         ECMR_PRM = 0x00000001,
 412 };
 413
 414 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 415 #define ECMR_CHG_DM     (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\
 416                         ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
 417 #else
 418 #define ECMR_CHG_DM     (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
 419 #endif
 420
 421 /* ECSR */
 422 enum ECSR_STATUS_BIT {
 423 #ifndef CONFIG_CPU_SUBTYPE_SH7763
 424         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 425 #endif
 426         ECSR_LCHNG = 0x04,
 427         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 428 };
 429
 430 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 431 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 432 #else
 433 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
 434                         ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
 435 #endif
 436
 437 /* ECSIPR */
 438 enum ECSIPR_STATUS_MASK_BIT {
 439 #ifndef CONFIG_CPU_SUBTYPE_SH7763
 440         ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 441 #endif
 442         ECSIPR_LCHNGIP = 0x04,
 443         ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 444 };
 445
 446 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 447 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 448 #else
 449 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
 450                                 ECSIPR_ICDIP | ECSIPR_MPDIP)
 451 #endif
 452
 453 /* APR */
 454 enum APR_BIT {
 455         APR_AP = 0x00000001,
 456 };
 457
 458 /* MPR */
 459 enum MPR_BIT {
 460         MPR_MP = 0x00000001,
 461 };
 462
 463 /* TRSCER */
 464 enum DESC_I_BIT {
 465         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 466         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 467         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 468         DESC_I_RINT1 = 0x0001,
 469 };
 470
 471 /* RPADIR */
 472 enum RPADIR_BIT {
 473         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 474         RPADIR_PADR = 0x0003f,
 475 };
 476
 477 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
 478 # define RPADIR_INIT (0x00)
 479 #else
 480 # define RPADIR_INIT (RPADIR_PADS1)
 481 #endif
 482
 483 /* RFLR */
 484 #define RFLR_VALUE 0x1000
 485
 486 /* FDR */
 487 enum FIFO_SIZE_BIT {
 488         FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 489 };
 490 enum phy_offsets {
 491         PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
 492         PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
 493         PHY_16 = 16,
 494 };
 495
 496 /* PHY_CTRL */
 497 enum PHY_CTRL_BIT {
 498         PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
 499         PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
 500         PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
 501 };
 502 #define DM9161_PHY_C_ANEGEN 0   /* auto nego special */
 503
 504 /* PHY_STAT */
 505 enum PHY_STAT_BIT {
 506         PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
 507         PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
 508         PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
 509         PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
 510 };
 511
 512 /* PHY_ANA */
 513 enum PHY_ANA_BIT {
 514         PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
 515         PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
 516         PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
 517         PHY_A_SEL = 0x001e,
 518 };
 519 /* PHY_ANL */
 520 enum PHY_ANL_BIT {
 521         PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
 522         PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
 523         PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
 524         PHY_L_SEL = 0x001f,
 525 };
 526
 527 /* PHY_ANE */
 528 enum PHY_ANE_BIT {
 529         PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
 530         PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
 531 };
 532
 533 /* DM9161 */
 534 enum PHY_16_BIT {
 535         PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
 536         PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
 537         PHY_16_TXselect = 0x0400,
 538         PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
 539         PHY_16_Force100LNK = 0x0080,
 540         PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
 541         PHY_16_RPDCTR_EN = 0x0010,
 542         PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
 543         PHY_16_Sleepmode = 0x0002,
 544         PHY_16_RemoteLoopOut = 0x0001,
 545 };
 546
 547 #define POST_RX         0x08
 548 #define POST_FW         0x04
 549 #define POST0_RX        (POST_RX)
 550 #define POST0_FW        (POST_FW)
 551 #define POST1_RX        (POST_RX >> 2)
 552 #define POST1_FW        (POST_FW >> 2)
 553 #define POST_ALL        (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
 554
 555 /* ARSTR */
 556 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
 557
 558 /* TSU_FWEN0 */
 559 enum TSU_FWEN0_BIT {
 560         TSU_FWEN0_0 = 0x00000001,
 561 };
 562
 563 /* TSU_ADSBSY */
 564 enum TSU_ADSBSY_BIT {
 565         TSU_ADSBSY_0 = 0x00000001,
 566 };
 567
 568 /* TSU_TEN */
 569 enum TSU_TEN_BIT {
 570         TSU_TEN_0 = 0x80000000,
 571 };
 572
 573 /* TSU_FWSL0 */
 574 enum TSU_FWSL0_BIT {
 575         TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
 576         TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
 577         TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
 578 };
 579
 580 /* TSU_FWSLC */
 581 enum TSU_FWSLC_BIT {
 582         TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
 583         TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
 584         TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
 585         TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
 586         TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
 587 };
 588
 589 /*
 590  * The sh ether Tx buffer descriptors.
 591  * This structure should be 20 bytes.
 592  */
 593 struct sh_eth_txdesc {
 594         u32 status;             /* TD0 */
 595 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 596         u16 pad0;               /* TD1 */
 597         u16 buffer_length;      /* TD1 */
 598 #else
 599         u16 buffer_length;      /* TD1 */
 600         u16 pad0;               /* TD1 */
 601 #endif
 602         u32 addr;               /* TD2 */
 603         u32 pad1;               /* padding data */
 604 };
 605
 606 /*
 607  * The sh ether Rx buffer descriptors.
 608  * This structure should be 20 bytes.
 609  */
 610 struct sh_eth_rxdesc {
 611         u32 status;             /* RD0 */
 612 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 613         u16 frame_length;       /* RD1 */
 614         u16 buffer_length;      /* RD1 */
 615 #else
 616         u16 buffer_length;      /* RD1 */
 617         u16 frame_length;       /* RD1 */
 618 #endif
 619         u32 addr;               /* RD2 */
 620         u32 pad0;               /* padding data */
 621 };
 622
 623 struct sh_eth_private {
 624         dma_addr_t rx_desc_dma;
 625         dma_addr_t tx_desc_dma;
 626         struct sh_eth_rxdesc *rx_ring;
 627         struct sh_eth_txdesc *tx_ring;
 628         struct sk_buff **rx_skbuff;
 629         struct sk_buff **tx_skbuff;
 630         struct net_device_stats stats;
 631         struct timer_list timer;
 632         spinlock_t lock;
 633         u32 cur_rx, dirty_rx;   /* Producer/consumer ring indices */
 634         u32 cur_tx, dirty_tx;
 635         u32 rx_buf_sz;          /* Based on MTU+slack. */
 636         /* MII transceiver section. */
 637         u32 phy_id;                                     /* PHY ID */
 638         struct mii_bus *mii_bus;        /* MDIO bus control */
 639         struct phy_device *phydev;      /* PHY device control */
 640         enum phy_state link;
 641         int msg_enable;
 642         int speed;
 643         int duplex;
 644         u32 rx_int_var, tx_int_var;     /* interrupt control variables */
 645         char post_rx;           /* POST receive */
 646         char post_fw;           /* POST forward */
 647         struct net_device_stats tsu_stats;      /* TSU forward status */
 648 };
 649
 650 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 651 /* SH7763 has endian control register */
 652 #define swaps(x, y)
 653 #else
 654 static void swaps(char *src, int len)
 655 {
 656 #ifdef __LITTLE_ENDIAN__
 657         u32 *p = (u32 *)src;
 658         u32 *maxp;
 659         maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
 660
 661         for (; p < maxp; p++)
 662                 *p = swab32(*p);
 663 #endif
 664 }
 665 #endif /* CONFIG_CPU_SUBTYPE_SH7763 */
 666 #endif