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[deliverable/linux.git] / drivers / net / skge.c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/in.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/mii.h>
42 #include <asm/irq.h>
43
44 #include "skge.h"
45
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.3"
48 #define PFX DRV_NAME " "
49
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
60 #define BLINK_MS 250
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
86 { 0 }
87 };
88 MODULE_DEVICE_TABLE(pci, skge_id_table);
89
90 static int skge_up(struct net_device *dev);
91 static int skge_down(struct net_device *dev);
92 static void skge_phy_reset(struct skge_port *skge);
93 static void skge_tx_clean(struct skge_port *skge);
94 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static void genesis_get_stats(struct skge_port *skge, u64 *data);
97 static void yukon_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_init(struct skge_hw *hw, int port);
99 static void genesis_mac_init(struct skge_hw *hw, int port);
100 static void genesis_link_up(struct skge_port *skge);
101
102 /* Avoid conditionals by using array */
103 static const int txqaddr[] = { Q_XA1, Q_XA2 };
104 static const int rxqaddr[] = { Q_R1, Q_R2 };
105 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
107 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
108
109 static int skge_get_regs_len(struct net_device *dev)
110 {
111 return 0x4000;
112 }
113
114 /*
115 * Returns copy of whole control register region
116 * Note: skip RAM address register because accessing it will
117 * cause bus hangs!
118 */
119 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121 {
122 const struct skge_port *skge = netdev_priv(dev);
123 const void __iomem *io = skge->hw->regs;
124
125 regs->version = 1;
126 memset(p, 0, regs->len);
127 memcpy_fromio(p, io, B3_RAM_ADDR);
128
129 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
130 regs->len - B3_RI_WTO_R1);
131 }
132
133 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
134 static int wol_supported(const struct skge_hw *hw)
135 {
136 return !((hw->chip_id == CHIP_ID_GENESIS ||
137 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
138 }
139
140 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141 {
142 struct skge_port *skge = netdev_priv(dev);
143
144 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
145 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
146 }
147
148 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149 {
150 struct skge_port *skge = netdev_priv(dev);
151 struct skge_hw *hw = skge->hw;
152
153 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
154 return -EOPNOTSUPP;
155
156 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
157 return -EOPNOTSUPP;
158
159 skge->wol = wol->wolopts == WAKE_MAGIC;
160
161 if (skge->wol) {
162 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163
164 skge_write16(hw, WOL_CTRL_STAT,
165 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
166 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 } else
168 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
169
170 return 0;
171 }
172
173 /* Determine supported/advertised modes based on hardware.
174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 */
176 static u32 skge_supported_modes(const struct skge_hw *hw)
177 {
178 u32 supported;
179
180 if (hw->copper) {
181 supported = SUPPORTED_10baseT_Half
182 | SUPPORTED_10baseT_Full
183 | SUPPORTED_100baseT_Half
184 | SUPPORTED_100baseT_Full
185 | SUPPORTED_1000baseT_Half
186 | SUPPORTED_1000baseT_Full
187 | SUPPORTED_Autoneg| SUPPORTED_TP;
188
189 if (hw->chip_id == CHIP_ID_GENESIS)
190 supported &= ~(SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full);
194
195 else if (hw->chip_id == CHIP_ID_YUKON)
196 supported &= ~SUPPORTED_1000baseT_Half;
197 } else
198 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
199 | SUPPORTED_Autoneg;
200
201 return supported;
202 }
203
204 static int skge_get_settings(struct net_device *dev,
205 struct ethtool_cmd *ecmd)
206 {
207 struct skge_port *skge = netdev_priv(dev);
208 struct skge_hw *hw = skge->hw;
209
210 ecmd->transceiver = XCVR_INTERNAL;
211 ecmd->supported = skge_supported_modes(hw);
212
213 if (hw->copper) {
214 ecmd->port = PORT_TP;
215 ecmd->phy_address = hw->phy_addr;
216 } else
217 ecmd->port = PORT_FIBRE;
218
219 ecmd->advertising = skge->advertising;
220 ecmd->autoneg = skge->autoneg;
221 ecmd->speed = skge->speed;
222 ecmd->duplex = skge->duplex;
223 return 0;
224 }
225
226 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 {
228 struct skge_port *skge = netdev_priv(dev);
229 const struct skge_hw *hw = skge->hw;
230 u32 supported = skge_supported_modes(hw);
231
232 if (ecmd->autoneg == AUTONEG_ENABLE) {
233 ecmd->advertising = supported;
234 skge->duplex = -1;
235 skge->speed = -1;
236 } else {
237 u32 setting;
238
239 switch (ecmd->speed) {
240 case SPEED_1000:
241 if (ecmd->duplex == DUPLEX_FULL)
242 setting = SUPPORTED_1000baseT_Full;
243 else if (ecmd->duplex == DUPLEX_HALF)
244 setting = SUPPORTED_1000baseT_Half;
245 else
246 return -EINVAL;
247 break;
248 case SPEED_100:
249 if (ecmd->duplex == DUPLEX_FULL)
250 setting = SUPPORTED_100baseT_Full;
251 else if (ecmd->duplex == DUPLEX_HALF)
252 setting = SUPPORTED_100baseT_Half;
253 else
254 return -EINVAL;
255 break;
256
257 case SPEED_10:
258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_10baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_10baseT_Half;
262 else
263 return -EINVAL;
264 break;
265 default:
266 return -EINVAL;
267 }
268
269 if ((setting & supported) == 0)
270 return -EINVAL;
271
272 skge->speed = ecmd->speed;
273 skge->duplex = ecmd->duplex;
274 }
275
276 skge->autoneg = ecmd->autoneg;
277 skge->advertising = ecmd->advertising;
278
279 if (netif_running(dev))
280 skge_phy_reset(skge);
281
282 return (0);
283 }
284
285 static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287 {
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294 }
295
296 static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300 } skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325 };
326
327 static int skge_get_stats_count(struct net_device *dev)
328 {
329 return ARRAY_SIZE(skge_stats);
330 }
331
332 static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334 {
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341 }
342
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 {
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[5] + data[7];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366 }
367
368 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369 {
370 int i;
371
372 switch (stringset) {
373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379 }
380
381 static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383 {
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395 }
396
397 static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399 {
400 struct skge_port *skge = netdev_priv(dev);
401 int err;
402
403 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
404 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
405 return -EINVAL;
406
407 skge->rx_ring.count = p->rx_pending;
408 skge->tx_ring.count = p->tx_pending;
409
410 if (netif_running(dev)) {
411 skge_down(dev);
412 err = skge_up(dev);
413 if (err)
414 dev_close(dev);
415 }
416
417 return 0;
418 }
419
420 static u32 skge_get_msglevel(struct net_device *netdev)
421 {
422 struct skge_port *skge = netdev_priv(netdev);
423 return skge->msg_enable;
424 }
425
426 static void skge_set_msglevel(struct net_device *netdev, u32 value)
427 {
428 struct skge_port *skge = netdev_priv(netdev);
429 skge->msg_enable = value;
430 }
431
432 static int skge_nway_reset(struct net_device *dev)
433 {
434 struct skge_port *skge = netdev_priv(dev);
435
436 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
437 return -EINVAL;
438
439 skge_phy_reset(skge);
440 return 0;
441 }
442
443 static int skge_set_sg(struct net_device *dev, u32 data)
444 {
445 struct skge_port *skge = netdev_priv(dev);
446 struct skge_hw *hw = skge->hw;
447
448 if (hw->chip_id == CHIP_ID_GENESIS && data)
449 return -EOPNOTSUPP;
450 return ethtool_op_set_sg(dev, data);
451 }
452
453 static int skge_set_tx_csum(struct net_device *dev, u32 data)
454 {
455 struct skge_port *skge = netdev_priv(dev);
456 struct skge_hw *hw = skge->hw;
457
458 if (hw->chip_id == CHIP_ID_GENESIS && data)
459 return -EOPNOTSUPP;
460
461 return ethtool_op_set_tx_csum(dev, data);
462 }
463
464 static u32 skge_get_rx_csum(struct net_device *dev)
465 {
466 struct skge_port *skge = netdev_priv(dev);
467
468 return skge->rx_csum;
469 }
470
471 /* Only Yukon supports checksum offload. */
472 static int skge_set_rx_csum(struct net_device *dev, u32 data)
473 {
474 struct skge_port *skge = netdev_priv(dev);
475
476 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
477 return -EOPNOTSUPP;
478
479 skge->rx_csum = data;
480 return 0;
481 }
482
483 static void skge_get_pauseparam(struct net_device *dev,
484 struct ethtool_pauseparam *ecmd)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
489 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
490 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492
493 ecmd->autoneg = skge->autoneg;
494 }
495
496 static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
498 {
499 struct skge_port *skge = netdev_priv(dev);
500
501 skge->autoneg = ecmd->autoneg;
502 if (ecmd->rx_pause && ecmd->tx_pause)
503 skge->flow_control = FLOW_MODE_SYMMETRIC;
504 else if (ecmd->rx_pause && !ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_REM_SEND;
506 else if (!ecmd->rx_pause && ecmd->tx_pause)
507 skge->flow_control = FLOW_MODE_LOC_SEND;
508 else
509 skge->flow_control = FLOW_MODE_NONE;
510
511 if (netif_running(dev))
512 skge_phy_reset(skge);
513 return 0;
514 }
515
516 /* Chip internal frequency for clock calculations */
517 static inline u32 hwkhz(const struct skge_hw *hw)
518 {
519 if (hw->chip_id == CHIP_ID_GENESIS)
520 return 53215; /* or: 53.125 MHz */
521 else
522 return 78215; /* or: 78.125 MHz */
523 }
524
525 /* Chip HZ to microseconds */
526 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
527 {
528 return (ticks * 1000) / hwkhz(hw);
529 }
530
531 /* Microseconds to chip HZ */
532 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
533 {
534 return hwkhz(hw) * usec / 1000;
535 }
536
537 static int skge_get_coalesce(struct net_device *dev,
538 struct ethtool_coalesce *ecmd)
539 {
540 struct skge_port *skge = netdev_priv(dev);
541 struct skge_hw *hw = skge->hw;
542 int port = skge->port;
543
544 ecmd->rx_coalesce_usecs = 0;
545 ecmd->tx_coalesce_usecs = 0;
546
547 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
548 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
549 u32 msk = skge_read32(hw, B2_IRQM_MSK);
550
551 if (msk & rxirqmask[port])
552 ecmd->rx_coalesce_usecs = delay;
553 if (msk & txirqmask[port])
554 ecmd->tx_coalesce_usecs = delay;
555 }
556
557 return 0;
558 }
559
560 /* Note: interrupt timer is per board, but can turn on/off per port */
561 static int skge_set_coalesce(struct net_device *dev,
562 struct ethtool_coalesce *ecmd)
563 {
564 struct skge_port *skge = netdev_priv(dev);
565 struct skge_hw *hw = skge->hw;
566 int port = skge->port;
567 u32 msk = skge_read32(hw, B2_IRQM_MSK);
568 u32 delay = 25;
569
570 if (ecmd->rx_coalesce_usecs == 0)
571 msk &= ~rxirqmask[port];
572 else if (ecmd->rx_coalesce_usecs < 25 ||
573 ecmd->rx_coalesce_usecs > 33333)
574 return -EINVAL;
575 else {
576 msk |= rxirqmask[port];
577 delay = ecmd->rx_coalesce_usecs;
578 }
579
580 if (ecmd->tx_coalesce_usecs == 0)
581 msk &= ~txirqmask[port];
582 else if (ecmd->tx_coalesce_usecs < 25 ||
583 ecmd->tx_coalesce_usecs > 33333)
584 return -EINVAL;
585 else {
586 msk |= txirqmask[port];
587 delay = min(delay, ecmd->rx_coalesce_usecs);
588 }
589
590 skge_write32(hw, B2_IRQM_MSK, msk);
591 if (msk == 0)
592 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
593 else {
594 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
595 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
596 }
597 return 0;
598 }
599
600 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
601 static void skge_led(struct skge_port *skge, enum led_mode mode)
602 {
603 struct skge_hw *hw = skge->hw;
604 int port = skge->port;
605
606 spin_lock_bh(&hw->phy_lock);
607 if (hw->chip_id == CHIP_ID_GENESIS) {
608 switch (mode) {
609 case LED_MODE_OFF:
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
611 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
612 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
614 break;
615
616 case LED_MODE_ON:
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
618 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
619
620 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
621 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
622
623 break;
624
625 case LED_MODE_TST:
626 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
627 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
628 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
629
630 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
631 break;
632 }
633 } else {
634 switch (mode) {
635 case LED_MODE_OFF:
636 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
637 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
638 PHY_M_LED_MO_DUP(MO_LED_OFF) |
639 PHY_M_LED_MO_10(MO_LED_OFF) |
640 PHY_M_LED_MO_100(MO_LED_OFF) |
641 PHY_M_LED_MO_1000(MO_LED_OFF) |
642 PHY_M_LED_MO_RX(MO_LED_OFF));
643 break;
644 case LED_MODE_ON:
645 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
646 PHY_M_LED_PULS_DUR(PULS_170MS) |
647 PHY_M_LED_BLINK_RT(BLINK_84MS) |
648 PHY_M_LEDC_TX_CTRL |
649 PHY_M_LEDC_DP_CTRL);
650
651 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
652 PHY_M_LED_MO_RX(MO_LED_OFF) |
653 (skge->speed == SPEED_100 ?
654 PHY_M_LED_MO_100(MO_LED_ON) : 0));
655 break;
656 case LED_MODE_TST:
657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
659 PHY_M_LED_MO_DUP(MO_LED_ON) |
660 PHY_M_LED_MO_10(MO_LED_ON) |
661 PHY_M_LED_MO_100(MO_LED_ON) |
662 PHY_M_LED_MO_1000(MO_LED_ON) |
663 PHY_M_LED_MO_RX(MO_LED_ON));
664 }
665 }
666 spin_unlock_bh(&hw->phy_lock);
667 }
668
669 /* blink LED's for finding board */
670 static int skge_phys_id(struct net_device *dev, u32 data)
671 {
672 struct skge_port *skge = netdev_priv(dev);
673 unsigned long ms;
674 enum led_mode mode = LED_MODE_TST;
675
676 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
677 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
678 else
679 ms = data * 1000;
680
681 while (ms > 0) {
682 skge_led(skge, mode);
683 mode ^= LED_MODE_TST;
684
685 if (msleep_interruptible(BLINK_MS))
686 break;
687 ms -= BLINK_MS;
688 }
689
690 /* back to regular LED state */
691 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
692
693 return 0;
694 }
695
696 static struct ethtool_ops skge_ethtool_ops = {
697 .get_settings = skge_get_settings,
698 .set_settings = skge_set_settings,
699 .get_drvinfo = skge_get_drvinfo,
700 .get_regs_len = skge_get_regs_len,
701 .get_regs = skge_get_regs,
702 .get_wol = skge_get_wol,
703 .set_wol = skge_set_wol,
704 .get_msglevel = skge_get_msglevel,
705 .set_msglevel = skge_set_msglevel,
706 .nway_reset = skge_nway_reset,
707 .get_link = ethtool_op_get_link,
708 .get_ringparam = skge_get_ring_param,
709 .set_ringparam = skge_set_ring_param,
710 .get_pauseparam = skge_get_pauseparam,
711 .set_pauseparam = skge_set_pauseparam,
712 .get_coalesce = skge_get_coalesce,
713 .set_coalesce = skge_set_coalesce,
714 .get_sg = ethtool_op_get_sg,
715 .set_sg = skge_set_sg,
716 .get_tx_csum = ethtool_op_get_tx_csum,
717 .set_tx_csum = skge_set_tx_csum,
718 .get_rx_csum = skge_get_rx_csum,
719 .set_rx_csum = skge_set_rx_csum,
720 .get_strings = skge_get_strings,
721 .phys_id = skge_phys_id,
722 .get_stats_count = skge_get_stats_count,
723 .get_ethtool_stats = skge_get_ethtool_stats,
724 .get_perm_addr = ethtool_op_get_perm_addr,
725 };
726
727 /*
728 * Allocate ring elements and chain them together
729 * One-to-one association of board descriptors with ring elements
730 */
731 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
732 {
733 struct skge_tx_desc *d;
734 struct skge_element *e;
735 int i;
736
737 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
738 if (!ring->start)
739 return -ENOMEM;
740
741 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
742 e->desc = d;
743 e->skb = NULL;
744 if (i == ring->count - 1) {
745 e->next = ring->start;
746 d->next_offset = base;
747 } else {
748 e->next = e + 1;
749 d->next_offset = base + (i+1) * sizeof(*d);
750 }
751 }
752 ring->to_use = ring->to_clean = ring->start;
753
754 return 0;
755 }
756
757 /* Allocate and setup a new buffer for receiving */
758 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
759 struct sk_buff *skb, unsigned int bufsize)
760 {
761 struct skge_rx_desc *rd = e->desc;
762 u64 map;
763
764 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
765 PCI_DMA_FROMDEVICE);
766
767 rd->dma_lo = map;
768 rd->dma_hi = map >> 32;
769 e->skb = skb;
770 rd->csum1_start = ETH_HLEN;
771 rd->csum2_start = ETH_HLEN;
772 rd->csum1 = 0;
773 rd->csum2 = 0;
774
775 wmb();
776
777 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
778 pci_unmap_addr_set(e, mapaddr, map);
779 pci_unmap_len_set(e, maplen, bufsize);
780 }
781
782 /* Resume receiving using existing skb,
783 * Note: DMA address is not changed by chip.
784 * MTU not changed while receiver active.
785 */
786 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
787 {
788 struct skge_rx_desc *rd = e->desc;
789
790 rd->csum2 = 0;
791 rd->csum2_start = ETH_HLEN;
792
793 wmb();
794
795 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
796 }
797
798
799 /* Free all buffers in receive ring, assumes receiver stopped */
800 static void skge_rx_clean(struct skge_port *skge)
801 {
802 struct skge_hw *hw = skge->hw;
803 struct skge_ring *ring = &skge->rx_ring;
804 struct skge_element *e;
805
806 e = ring->start;
807 do {
808 struct skge_rx_desc *rd = e->desc;
809 rd->control = 0;
810 if (e->skb) {
811 pci_unmap_single(hw->pdev,
812 pci_unmap_addr(e, mapaddr),
813 pci_unmap_len(e, maplen),
814 PCI_DMA_FROMDEVICE);
815 dev_kfree_skb(e->skb);
816 e->skb = NULL;
817 }
818 } while ((e = e->next) != ring->start);
819 }
820
821
822 /* Allocate buffers for receive ring
823 * For receive: to_clean is next received frame.
824 */
825 static int skge_rx_fill(struct skge_port *skge)
826 {
827 struct skge_ring *ring = &skge->rx_ring;
828 struct skge_element *e;
829
830 e = ring->start;
831 do {
832 struct sk_buff *skb;
833
834 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
835 if (!skb)
836 return -ENOMEM;
837
838 skb_reserve(skb, NET_IP_ALIGN);
839 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
840 } while ( (e = e->next) != ring->start);
841
842 ring->to_clean = ring->start;
843 return 0;
844 }
845
846 static void skge_link_up(struct skge_port *skge)
847 {
848 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
849 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850
851 netif_carrier_on(skge->netdev);
852 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
853 netif_wake_queue(skge->netdev);
854
855 if (netif_msg_link(skge))
856 printk(KERN_INFO PFX
857 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
858 skge->netdev->name, skge->speed,
859 skge->duplex == DUPLEX_FULL ? "full" : "half",
860 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
861 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
862 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
863 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
864 "unknown");
865 }
866
867 static void skge_link_down(struct skge_port *skge)
868 {
869 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
870 netif_carrier_off(skge->netdev);
871 netif_stop_queue(skge->netdev);
872
873 if (netif_msg_link(skge))
874 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
875 }
876
877 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
878 {
879 int i;
880
881 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
882 *val = xm_read16(hw, port, XM_PHY_DATA);
883
884 for (i = 0; i < PHY_RETRIES; i++) {
885 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
886 goto ready;
887 udelay(1);
888 }
889
890 return -ETIMEDOUT;
891 ready:
892 *val = xm_read16(hw, port, XM_PHY_DATA);
893
894 return 0;
895 }
896
897 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
898 {
899 u16 v = 0;
900 if (__xm_phy_read(hw, port, reg, &v))
901 printk(KERN_WARNING PFX "%s: phy read timed out\n",
902 hw->dev[port]->name);
903 return v;
904 }
905
906 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
907 {
908 int i;
909
910 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
911 for (i = 0; i < PHY_RETRIES; i++) {
912 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
913 goto ready;
914 udelay(1);
915 }
916 return -EIO;
917
918 ready:
919 xm_write16(hw, port, XM_PHY_DATA, val);
920 for (i = 0; i < PHY_RETRIES; i++) {
921 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
922 return 0;
923 udelay(1);
924 }
925 return -ETIMEDOUT;
926 }
927
928 static void genesis_init(struct skge_hw *hw)
929 {
930 /* set blink source counter */
931 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
932 skge_write8(hw, B2_BSC_CTRL, BSC_START);
933
934 /* configure mac arbiter */
935 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
936
937 /* configure mac arbiter timeout values */
938 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
940 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
941 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
942
943 skge_write8(hw, B3_MA_RCINI_RX1, 0);
944 skge_write8(hw, B3_MA_RCINI_RX2, 0);
945 skge_write8(hw, B3_MA_RCINI_TX1, 0);
946 skge_write8(hw, B3_MA_RCINI_TX2, 0);
947
948 /* configure packet arbiter timeout */
949 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
950 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
952 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
953 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
954 }
955
956 static void genesis_reset(struct skge_hw *hw, int port)
957 {
958 const u8 zero[8] = { 0 };
959
960 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
961
962 /* reset the statistics module */
963 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
964 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
965 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
966 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
967 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
968
969 /* disable Broadcom PHY IRQ */
970 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
971
972 xm_outhash(hw, port, XM_HSM, zero);
973 }
974
975
976 /* Convert mode to MII values */
977 static const u16 phy_pause_map[] = {
978 [FLOW_MODE_NONE] = 0,
979 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
980 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
981 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
982 };
983
984
985 /* Check status of Broadcom phy link */
986 static void bcom_check_link(struct skge_hw *hw, int port)
987 {
988 struct net_device *dev = hw->dev[port];
989 struct skge_port *skge = netdev_priv(dev);
990 u16 status;
991
992 /* read twice because of latch */
993 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
994 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
995
996 if ((status & PHY_ST_LSYNC) == 0) {
997 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
998 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
999 xm_write16(hw, port, XM_MMU_CMD, cmd);
1000 /* dummy read to ensure writing */
1001 (void) xm_read16(hw, port, XM_MMU_CMD);
1002
1003 if (netif_carrier_ok(dev))
1004 skge_link_down(skge);
1005 } else {
1006 if (skge->autoneg == AUTONEG_ENABLE &&
1007 (status & PHY_ST_AN_OVER)) {
1008 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1009 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1010
1011 if (lpa & PHY_B_AN_RF) {
1012 printk(KERN_NOTICE PFX "%s: remote fault\n",
1013 dev->name);
1014 return;
1015 }
1016
1017 /* Check Duplex mismatch */
1018 switch (aux & PHY_B_AS_AN_RES_MSK) {
1019 case PHY_B_RES_1000FD:
1020 skge->duplex = DUPLEX_FULL;
1021 break;
1022 case PHY_B_RES_1000HD:
1023 skge->duplex = DUPLEX_HALF;
1024 break;
1025 default:
1026 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1027 dev->name);
1028 return;
1029 }
1030
1031
1032 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1033 switch (aux & PHY_B_AS_PAUSE_MSK) {
1034 case PHY_B_AS_PAUSE_MSK:
1035 skge->flow_control = FLOW_MODE_SYMMETRIC;
1036 break;
1037 case PHY_B_AS_PRR:
1038 skge->flow_control = FLOW_MODE_REM_SEND;
1039 break;
1040 case PHY_B_AS_PRT:
1041 skge->flow_control = FLOW_MODE_LOC_SEND;
1042 break;
1043 default:
1044 skge->flow_control = FLOW_MODE_NONE;
1045 }
1046
1047 skge->speed = SPEED_1000;
1048 }
1049
1050 if (!netif_carrier_ok(dev))
1051 genesis_link_up(skge);
1052 }
1053 }
1054
1055 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1056 * Phy on for 100 or 10Mbit operation
1057 */
1058 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1059 {
1060 struct skge_hw *hw = skge->hw;
1061 int port = skge->port;
1062 int i;
1063 u16 id1, r, ext, ctl;
1064
1065 /* magic workaround patterns for Broadcom */
1066 static const struct {
1067 u16 reg;
1068 u16 val;
1069 } A1hack[] = {
1070 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1071 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1072 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1073 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1074 }, C0hack[] = {
1075 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1076 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1077 };
1078
1079 /* read Id from external PHY (all have the same address) */
1080 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1081
1082 /* Optimize MDIO transfer by suppressing preamble. */
1083 r = xm_read16(hw, port, XM_MMU_CMD);
1084 r |= XM_MMU_NO_PRE;
1085 xm_write16(hw, port, XM_MMU_CMD,r);
1086
1087 switch (id1) {
1088 case PHY_BCOM_ID1_C0:
1089 /*
1090 * Workaround BCOM Errata for the C0 type.
1091 * Write magic patterns to reserved registers.
1092 */
1093 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1094 xm_phy_write(hw, port,
1095 C0hack[i].reg, C0hack[i].val);
1096
1097 break;
1098 case PHY_BCOM_ID1_A1:
1099 /*
1100 * Workaround BCOM Errata for the A1 type.
1101 * Write magic patterns to reserved registers.
1102 */
1103 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1104 xm_phy_write(hw, port,
1105 A1hack[i].reg, A1hack[i].val);
1106 break;
1107 }
1108
1109 /*
1110 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1111 * Disable Power Management after reset.
1112 */
1113 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1114 r |= PHY_B_AC_DIS_PM;
1115 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1116
1117 /* Dummy read */
1118 xm_read16(hw, port, XM_ISRC);
1119
1120 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1121 ctl = PHY_CT_SP1000; /* always 1000mbit */
1122
1123 if (skge->autoneg == AUTONEG_ENABLE) {
1124 /*
1125 * Workaround BCOM Errata #1 for the C5 type.
1126 * 1000Base-T Link Acquisition Failure in Slave Mode
1127 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1128 */
1129 u16 adv = PHY_B_1000C_RD;
1130 if (skge->advertising & ADVERTISED_1000baseT_Half)
1131 adv |= PHY_B_1000C_AHD;
1132 if (skge->advertising & ADVERTISED_1000baseT_Full)
1133 adv |= PHY_B_1000C_AFD;
1134 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1135
1136 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1137 } else {
1138 if (skge->duplex == DUPLEX_FULL)
1139 ctl |= PHY_CT_DUP_MD;
1140 /* Force to slave */
1141 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1142 }
1143
1144 /* Set autonegotiation pause parameters */
1145 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1146 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1147
1148 /* Handle Jumbo frames */
1149 if (jumbo) {
1150 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1151 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1152
1153 ext |= PHY_B_PEC_HIGH_LA;
1154
1155 }
1156
1157 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1158 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1159
1160 /* Use link status change interrupt */
1161 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1162
1163 bcom_check_link(hw, port);
1164 }
1165
1166 static void genesis_mac_init(struct skge_hw *hw, int port)
1167 {
1168 struct net_device *dev = hw->dev[port];
1169 struct skge_port *skge = netdev_priv(dev);
1170 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1171 int i;
1172 u32 r;
1173 const u8 zero[6] = { 0 };
1174
1175 for (i = 0; i < 10; i++) {
1176 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1177 MFF_SET_MAC_RST);
1178 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1179 goto reset_ok;
1180 udelay(1);
1181 }
1182
1183 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1184
1185 reset_ok:
1186 /* Unreset the XMAC. */
1187 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1188
1189 /*
1190 * Perform additional initialization for external PHYs,
1191 * namely for the 1000baseTX cards that use the XMAC's
1192 * GMII mode.
1193 */
1194 /* Take external Phy out of reset */
1195 r = skge_read32(hw, B2_GP_IO);
1196 if (port == 0)
1197 r |= GP_DIR_0|GP_IO_0;
1198 else
1199 r |= GP_DIR_2|GP_IO_2;
1200
1201 skge_write32(hw, B2_GP_IO, r);
1202
1203
1204 /* Enable GMII interface */
1205 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1206
1207 bcom_phy_init(skge, jumbo);
1208
1209 /* Set Station Address */
1210 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1211
1212 /* We don't use match addresses so clear */
1213 for (i = 1; i < 16; i++)
1214 xm_outaddr(hw, port, XM_EXM(i), zero);
1215
1216 /* Clear MIB counters */
1217 xm_write16(hw, port, XM_STAT_CMD,
1218 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1219 /* Clear two times according to Errata #3 */
1220 xm_write16(hw, port, XM_STAT_CMD,
1221 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1222
1223 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1224 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1225
1226 /* We don't need the FCS appended to the packet. */
1227 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1228 if (jumbo)
1229 r |= XM_RX_BIG_PK_OK;
1230
1231 if (skge->duplex == DUPLEX_HALF) {
1232 /*
1233 * If in manual half duplex mode the other side might be in
1234 * full duplex mode, so ignore if a carrier extension is not seen
1235 * on frames received
1236 */
1237 r |= XM_RX_DIS_CEXT;
1238 }
1239 xm_write16(hw, port, XM_RX_CMD, r);
1240
1241
1242 /* We want short frames padded to 60 bytes. */
1243 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1244
1245 /*
1246 * Bump up the transmit threshold. This helps hold off transmit
1247 * underruns when we're blasting traffic from both ports at once.
1248 */
1249 xm_write16(hw, port, XM_TX_THR, 512);
1250
1251 /*
1252 * Enable the reception of all error frames. This is is
1253 * a necessary evil due to the design of the XMAC. The
1254 * XMAC's receive FIFO is only 8K in size, however jumbo
1255 * frames can be up to 9000 bytes in length. When bad
1256 * frame filtering is enabled, the XMAC's RX FIFO operates
1257 * in 'store and forward' mode. For this to work, the
1258 * entire frame has to fit into the FIFO, but that means
1259 * that jumbo frames larger than 8192 bytes will be
1260 * truncated. Disabling all bad frame filtering causes
1261 * the RX FIFO to operate in streaming mode, in which
1262 * case the XMAC will start transferring frames out of the
1263 * RX FIFO as soon as the FIFO threshold is reached.
1264 */
1265 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1266
1267
1268 /*
1269 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1270 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1271 * and 'Octets Rx OK Hi Cnt Ov'.
1272 */
1273 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1274
1275 /*
1276 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1277 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1278 * and 'Octets Tx OK Hi Cnt Ov'.
1279 */
1280 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1281
1282 /* Configure MAC arbiter */
1283 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1284
1285 /* configure timeout values */
1286 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1287 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1288 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1289 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1290
1291 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1292 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1293 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1294 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1295
1296 /* Configure Rx MAC FIFO */
1297 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1298 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1299 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1300
1301 /* Configure Tx MAC FIFO */
1302 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1303 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1304 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1305
1306 if (jumbo) {
1307 /* Enable frame flushing if jumbo frames used */
1308 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1309 } else {
1310 /* enable timeout timers if normal frames */
1311 skge_write16(hw, B3_PA_CTRL,
1312 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1313 }
1314 }
1315
1316 static void genesis_stop(struct skge_port *skge)
1317 {
1318 struct skge_hw *hw = skge->hw;
1319 int port = skge->port;
1320 u32 reg;
1321
1322 genesis_reset(hw, port);
1323
1324 /* Clear Tx packet arbiter timeout IRQ */
1325 skge_write16(hw, B3_PA_CTRL,
1326 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1327
1328 /*
1329 * If the transfer sticks at the MAC the STOP command will not
1330 * terminate if we don't flush the XMAC's transmit FIFO !
1331 */
1332 xm_write32(hw, port, XM_MODE,
1333 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1334
1335
1336 /* Reset the MAC */
1337 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1338
1339 /* For external PHYs there must be special handling */
1340 reg = skge_read32(hw, B2_GP_IO);
1341 if (port == 0) {
1342 reg |= GP_DIR_0;
1343 reg &= ~GP_IO_0;
1344 } else {
1345 reg |= GP_DIR_2;
1346 reg &= ~GP_IO_2;
1347 }
1348 skge_write32(hw, B2_GP_IO, reg);
1349 skge_read32(hw, B2_GP_IO);
1350
1351 xm_write16(hw, port, XM_MMU_CMD,
1352 xm_read16(hw, port, XM_MMU_CMD)
1353 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1354
1355 xm_read16(hw, port, XM_MMU_CMD);
1356 }
1357
1358
1359 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1360 {
1361 struct skge_hw *hw = skge->hw;
1362 int port = skge->port;
1363 int i;
1364 unsigned long timeout = jiffies + HZ;
1365
1366 xm_write16(hw, port,
1367 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1368
1369 /* wait for update to complete */
1370 while (xm_read16(hw, port, XM_STAT_CMD)
1371 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1372 if (time_after(jiffies, timeout))
1373 break;
1374 udelay(10);
1375 }
1376
1377 /* special case for 64 bit octet counter */
1378 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1379 | xm_read32(hw, port, XM_TXO_OK_LO);
1380 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1381 | xm_read32(hw, port, XM_RXO_OK_LO);
1382
1383 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1384 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1385 }
1386
1387 static void genesis_mac_intr(struct skge_hw *hw, int port)
1388 {
1389 struct skge_port *skge = netdev_priv(hw->dev[port]);
1390 u16 status = xm_read16(hw, port, XM_ISRC);
1391
1392 if (netif_msg_intr(skge))
1393 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1394 skge->netdev->name, status);
1395
1396 if (status & XM_IS_TXF_UR) {
1397 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1398 ++skge->net_stats.tx_fifo_errors;
1399 }
1400 if (status & XM_IS_RXF_OV) {
1401 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1402 ++skge->net_stats.rx_fifo_errors;
1403 }
1404 }
1405
1406 static void genesis_link_up(struct skge_port *skge)
1407 {
1408 struct skge_hw *hw = skge->hw;
1409 int port = skge->port;
1410 u16 cmd;
1411 u32 mode, msk;
1412
1413 cmd = xm_read16(hw, port, XM_MMU_CMD);
1414
1415 /*
1416 * enabling pause frame reception is required for 1000BT
1417 * because the XMAC is not reset if the link is going down
1418 */
1419 if (skge->flow_control == FLOW_MODE_NONE ||
1420 skge->flow_control == FLOW_MODE_LOC_SEND)
1421 /* Disable Pause Frame Reception */
1422 cmd |= XM_MMU_IGN_PF;
1423 else
1424 /* Enable Pause Frame Reception */
1425 cmd &= ~XM_MMU_IGN_PF;
1426
1427 xm_write16(hw, port, XM_MMU_CMD, cmd);
1428
1429 mode = xm_read32(hw, port, XM_MODE);
1430 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1431 skge->flow_control == FLOW_MODE_LOC_SEND) {
1432 /*
1433 * Configure Pause Frame Generation
1434 * Use internal and external Pause Frame Generation.
1435 * Sending pause frames is edge triggered.
1436 * Send a Pause frame with the maximum pause time if
1437 * internal oder external FIFO full condition occurs.
1438 * Send a zero pause time frame to re-start transmission.
1439 */
1440 /* XM_PAUSE_DA = '010000C28001' (default) */
1441 /* XM_MAC_PTIME = 0xffff (maximum) */
1442 /* remember this value is defined in big endian (!) */
1443 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1444
1445 mode |= XM_PAUSE_MODE;
1446 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1447 } else {
1448 /*
1449 * disable pause frame generation is required for 1000BT
1450 * because the XMAC is not reset if the link is going down
1451 */
1452 /* Disable Pause Mode in Mode Register */
1453 mode &= ~XM_PAUSE_MODE;
1454
1455 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1456 }
1457
1458 xm_write32(hw, port, XM_MODE, mode);
1459
1460 msk = XM_DEF_MSK;
1461 /* disable GP0 interrupt bit for external Phy */
1462 msk |= XM_IS_INP_ASS;
1463
1464 xm_write16(hw, port, XM_IMSK, msk);
1465 xm_read16(hw, port, XM_ISRC);
1466
1467 /* get MMU Command Reg. */
1468 cmd = xm_read16(hw, port, XM_MMU_CMD);
1469 if (skge->duplex == DUPLEX_FULL)
1470 cmd |= XM_MMU_GMII_FD;
1471
1472 /*
1473 * Workaround BCOM Errata (#10523) for all BCom Phys
1474 * Enable Power Management after link up
1475 */
1476 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1477 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1478 & ~PHY_B_AC_DIS_PM);
1479 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1480
1481 /* enable Rx/Tx */
1482 xm_write16(hw, port, XM_MMU_CMD,
1483 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1484 skge_link_up(skge);
1485 }
1486
1487
1488 static inline void bcom_phy_intr(struct skge_port *skge)
1489 {
1490 struct skge_hw *hw = skge->hw;
1491 int port = skge->port;
1492 u16 isrc;
1493
1494 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1495 if (netif_msg_intr(skge))
1496 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1497 skge->netdev->name, isrc);
1498
1499 if (isrc & PHY_B_IS_PSE)
1500 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1501 hw->dev[port]->name);
1502
1503 /* Workaround BCom Errata:
1504 * enable and disable loopback mode if "NO HCD" occurs.
1505 */
1506 if (isrc & PHY_B_IS_NO_HDCL) {
1507 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1508 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1509 ctrl | PHY_CT_LOOP);
1510 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1511 ctrl & ~PHY_CT_LOOP);
1512 }
1513
1514 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1515 bcom_check_link(hw, port);
1516
1517 }
1518
1519 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1520 {
1521 int i;
1522
1523 gma_write16(hw, port, GM_SMI_DATA, val);
1524 gma_write16(hw, port, GM_SMI_CTRL,
1525 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1526 for (i = 0; i < PHY_RETRIES; i++) {
1527 udelay(1);
1528
1529 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1530 return 0;
1531 }
1532
1533 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1534 hw->dev[port]->name);
1535 return -EIO;
1536 }
1537
1538 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1539 {
1540 int i;
1541
1542 gma_write16(hw, port, GM_SMI_CTRL,
1543 GM_SMI_CT_PHY_AD(hw->phy_addr)
1544 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1545
1546 for (i = 0; i < PHY_RETRIES; i++) {
1547 udelay(1);
1548 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1549 goto ready;
1550 }
1551
1552 return -ETIMEDOUT;
1553 ready:
1554 *val = gma_read16(hw, port, GM_SMI_DATA);
1555 return 0;
1556 }
1557
1558 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1559 {
1560 u16 v = 0;
1561 if (__gm_phy_read(hw, port, reg, &v))
1562 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1563 hw->dev[port]->name);
1564 return v;
1565 }
1566
1567 /* Marvell Phy Initialization */
1568 static void yukon_init(struct skge_hw *hw, int port)
1569 {
1570 struct skge_port *skge = netdev_priv(hw->dev[port]);
1571 u16 ctrl, ct1000, adv;
1572
1573 if (skge->autoneg == AUTONEG_ENABLE) {
1574 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1575
1576 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1577 PHY_M_EC_MAC_S_MSK);
1578 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1579
1580 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1581
1582 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1583 }
1584
1585 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1586 if (skge->autoneg == AUTONEG_DISABLE)
1587 ctrl &= ~PHY_CT_ANE;
1588
1589 ctrl |= PHY_CT_RESET;
1590 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1591
1592 ctrl = 0;
1593 ct1000 = 0;
1594 adv = PHY_AN_CSMA;
1595
1596 if (skge->autoneg == AUTONEG_ENABLE) {
1597 if (hw->copper) {
1598 if (skge->advertising & ADVERTISED_1000baseT_Full)
1599 ct1000 |= PHY_M_1000C_AFD;
1600 if (skge->advertising & ADVERTISED_1000baseT_Half)
1601 ct1000 |= PHY_M_1000C_AHD;
1602 if (skge->advertising & ADVERTISED_100baseT_Full)
1603 adv |= PHY_M_AN_100_FD;
1604 if (skge->advertising & ADVERTISED_100baseT_Half)
1605 adv |= PHY_M_AN_100_HD;
1606 if (skge->advertising & ADVERTISED_10baseT_Full)
1607 adv |= PHY_M_AN_10_FD;
1608 if (skge->advertising & ADVERTISED_10baseT_Half)
1609 adv |= PHY_M_AN_10_HD;
1610 } else /* special defines for FIBER (88E1011S only) */
1611 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1612
1613 /* Set Flow-control capabilities */
1614 adv |= phy_pause_map[skge->flow_control];
1615
1616 /* Restart Auto-negotiation */
1617 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1618 } else {
1619 /* forced speed/duplex settings */
1620 ct1000 = PHY_M_1000C_MSE;
1621
1622 if (skge->duplex == DUPLEX_FULL)
1623 ctrl |= PHY_CT_DUP_MD;
1624
1625 switch (skge->speed) {
1626 case SPEED_1000:
1627 ctrl |= PHY_CT_SP1000;
1628 break;
1629 case SPEED_100:
1630 ctrl |= PHY_CT_SP100;
1631 break;
1632 }
1633
1634 ctrl |= PHY_CT_RESET;
1635 }
1636
1637 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1638
1639 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1640 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1641
1642 /* Enable phy interrupt on autonegotiation complete (or link up) */
1643 if (skge->autoneg == AUTONEG_ENABLE)
1644 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1645 else
1646 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1647 }
1648
1649 static void yukon_reset(struct skge_hw *hw, int port)
1650 {
1651 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1652 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1653 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1654 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1655 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1656
1657 gma_write16(hw, port, GM_RX_CTRL,
1658 gma_read16(hw, port, GM_RX_CTRL)
1659 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1660 }
1661
1662 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1663 static int is_yukon_lite_a0(struct skge_hw *hw)
1664 {
1665 u32 reg;
1666 int ret;
1667
1668 if (hw->chip_id != CHIP_ID_YUKON)
1669 return 0;
1670
1671 reg = skge_read32(hw, B2_FAR);
1672 skge_write8(hw, B2_FAR + 3, 0xff);
1673 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1674 skge_write32(hw, B2_FAR, reg);
1675 return ret;
1676 }
1677
1678 static void yukon_mac_init(struct skge_hw *hw, int port)
1679 {
1680 struct skge_port *skge = netdev_priv(hw->dev[port]);
1681 int i;
1682 u32 reg;
1683 const u8 *addr = hw->dev[port]->dev_addr;
1684
1685 /* WA code for COMA mode -- set PHY reset */
1686 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1687 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1688 reg = skge_read32(hw, B2_GP_IO);
1689 reg |= GP_DIR_9 | GP_IO_9;
1690 skge_write32(hw, B2_GP_IO, reg);
1691 }
1692
1693 /* hard reset */
1694 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1695 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1696
1697 /* WA code for COMA mode -- clear PHY reset */
1698 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1699 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1700 reg = skge_read32(hw, B2_GP_IO);
1701 reg |= GP_DIR_9;
1702 reg &= ~GP_IO_9;
1703 skge_write32(hw, B2_GP_IO, reg);
1704 }
1705
1706 /* Set hardware config mode */
1707 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1708 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1709 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1710
1711 /* Clear GMC reset */
1712 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1713 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1714 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1715
1716 if (skge->autoneg == AUTONEG_DISABLE) {
1717 reg = GM_GPCR_AU_ALL_DIS;
1718 gma_write16(hw, port, GM_GP_CTRL,
1719 gma_read16(hw, port, GM_GP_CTRL) | reg);
1720
1721 switch (skge->speed) {
1722 case SPEED_1000:
1723 reg &= ~GM_GPCR_SPEED_100;
1724 reg |= GM_GPCR_SPEED_1000;
1725 break;
1726 case SPEED_100:
1727 reg &= ~GM_GPCR_SPEED_1000;
1728 reg |= GM_GPCR_SPEED_100;
1729 break;
1730 case SPEED_10:
1731 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1732 break;
1733 }
1734
1735 if (skge->duplex == DUPLEX_FULL)
1736 reg |= GM_GPCR_DUP_FULL;
1737 } else
1738 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1739
1740 switch (skge->flow_control) {
1741 case FLOW_MODE_NONE:
1742 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1743 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1744 break;
1745 case FLOW_MODE_LOC_SEND:
1746 /* disable Rx flow-control */
1747 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1748 }
1749
1750 gma_write16(hw, port, GM_GP_CTRL, reg);
1751 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1752
1753 yukon_init(hw, port);
1754
1755 /* MIB clear */
1756 reg = gma_read16(hw, port, GM_PHY_ADDR);
1757 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1758
1759 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1760 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1761 gma_write16(hw, port, GM_PHY_ADDR, reg);
1762
1763 /* transmit control */
1764 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1765
1766 /* receive control reg: unicast + multicast + no FCS */
1767 gma_write16(hw, port, GM_RX_CTRL,
1768 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1769
1770 /* transmit flow control */
1771 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1772
1773 /* transmit parameter */
1774 gma_write16(hw, port, GM_TX_PARAM,
1775 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1776 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1777 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1778
1779 /* serial mode register */
1780 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1781 if (hw->dev[port]->mtu > 1500)
1782 reg |= GM_SMOD_JUMBO_ENA;
1783
1784 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1785
1786 /* physical address: used for pause frames */
1787 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1788 /* virtual address for data */
1789 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1790
1791 /* enable interrupt mask for counter overflows */
1792 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1793 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1794 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1795
1796 /* Initialize Mac Fifo */
1797
1798 /* Configure Rx MAC FIFO */
1799 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1800 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1801
1802 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1803 if (is_yukon_lite_a0(hw))
1804 reg &= ~GMF_RX_F_FL_ON;
1805
1806 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1807 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1808 /*
1809 * because Pause Packet Truncation in GMAC is not working
1810 * we have to increase the Flush Threshold to 64 bytes
1811 * in order to flush pause packets in Rx FIFO on Yukon-1
1812 */
1813 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1814
1815 /* Configure Tx MAC FIFO */
1816 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1817 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1818 }
1819
1820 /* Go into power down mode */
1821 static void yukon_suspend(struct skge_hw *hw, int port)
1822 {
1823 u16 ctrl;
1824
1825 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1826 ctrl |= PHY_M_PC_POL_R_DIS;
1827 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1828
1829 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1830 ctrl |= PHY_CT_RESET;
1831 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1832
1833 /* switch IEEE compatible power down mode on */
1834 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1835 ctrl |= PHY_CT_PDOWN;
1836 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1837 }
1838
1839 static void yukon_stop(struct skge_port *skge)
1840 {
1841 struct skge_hw *hw = skge->hw;
1842 int port = skge->port;
1843
1844 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1845 yukon_reset(hw, port);
1846
1847 gma_write16(hw, port, GM_GP_CTRL,
1848 gma_read16(hw, port, GM_GP_CTRL)
1849 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1850 gma_read16(hw, port, GM_GP_CTRL);
1851
1852 yukon_suspend(hw, port);
1853
1854 /* set GPHY Control reset */
1855 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1856 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1857 }
1858
1859 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1860 {
1861 struct skge_hw *hw = skge->hw;
1862 int port = skge->port;
1863 int i;
1864
1865 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1866 | gma_read32(hw, port, GM_TXO_OK_LO);
1867 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1868 | gma_read32(hw, port, GM_RXO_OK_LO);
1869
1870 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1871 data[i] = gma_read32(hw, port,
1872 skge_stats[i].gma_offset);
1873 }
1874
1875 static void yukon_mac_intr(struct skge_hw *hw, int port)
1876 {
1877 struct net_device *dev = hw->dev[port];
1878 struct skge_port *skge = netdev_priv(dev);
1879 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1880
1881 if (netif_msg_intr(skge))
1882 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1883 dev->name, status);
1884
1885 if (status & GM_IS_RX_FF_OR) {
1886 ++skge->net_stats.rx_fifo_errors;
1887 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1888 }
1889
1890 if (status & GM_IS_TX_FF_UR) {
1891 ++skge->net_stats.tx_fifo_errors;
1892 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1893 }
1894
1895 }
1896
1897 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1898 {
1899 switch (aux & PHY_M_PS_SPEED_MSK) {
1900 case PHY_M_PS_SPEED_1000:
1901 return SPEED_1000;
1902 case PHY_M_PS_SPEED_100:
1903 return SPEED_100;
1904 default:
1905 return SPEED_10;
1906 }
1907 }
1908
1909 static void yukon_link_up(struct skge_port *skge)
1910 {
1911 struct skge_hw *hw = skge->hw;
1912 int port = skge->port;
1913 u16 reg;
1914
1915 /* Enable Transmit FIFO Underrun */
1916 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1917
1918 reg = gma_read16(hw, port, GM_GP_CTRL);
1919 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1920 reg |= GM_GPCR_DUP_FULL;
1921
1922 /* enable Rx/Tx */
1923 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1924 gma_write16(hw, port, GM_GP_CTRL, reg);
1925
1926 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1927 skge_link_up(skge);
1928 }
1929
1930 static void yukon_link_down(struct skge_port *skge)
1931 {
1932 struct skge_hw *hw = skge->hw;
1933 int port = skge->port;
1934 u16 ctrl;
1935
1936 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1937
1938 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1939 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1940 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1941
1942 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1943 /* restore Asymmetric Pause bit */
1944 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1945 gm_phy_read(hw, port,
1946 PHY_MARV_AUNE_ADV)
1947 | PHY_M_AN_ASP);
1948
1949 }
1950
1951 yukon_reset(hw, port);
1952 skge_link_down(skge);
1953
1954 yukon_init(hw, port);
1955 }
1956
1957 static void yukon_phy_intr(struct skge_port *skge)
1958 {
1959 struct skge_hw *hw = skge->hw;
1960 int port = skge->port;
1961 const char *reason = NULL;
1962 u16 istatus, phystat;
1963
1964 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1965 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1966
1967 if (netif_msg_intr(skge))
1968 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1969 skge->netdev->name, istatus, phystat);
1970
1971 if (istatus & PHY_M_IS_AN_COMPL) {
1972 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1973 & PHY_M_AN_RF) {
1974 reason = "remote fault";
1975 goto failed;
1976 }
1977
1978 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1979 reason = "master/slave fault";
1980 goto failed;
1981 }
1982
1983 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1984 reason = "speed/duplex";
1985 goto failed;
1986 }
1987
1988 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1989 ? DUPLEX_FULL : DUPLEX_HALF;
1990 skge->speed = yukon_speed(hw, phystat);
1991
1992 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1993 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1994 case PHY_M_PS_PAUSE_MSK:
1995 skge->flow_control = FLOW_MODE_SYMMETRIC;
1996 break;
1997 case PHY_M_PS_RX_P_EN:
1998 skge->flow_control = FLOW_MODE_REM_SEND;
1999 break;
2000 case PHY_M_PS_TX_P_EN:
2001 skge->flow_control = FLOW_MODE_LOC_SEND;
2002 break;
2003 default:
2004 skge->flow_control = FLOW_MODE_NONE;
2005 }
2006
2007 if (skge->flow_control == FLOW_MODE_NONE ||
2008 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2009 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2010 else
2011 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2012 yukon_link_up(skge);
2013 return;
2014 }
2015
2016 if (istatus & PHY_M_IS_LSP_CHANGE)
2017 skge->speed = yukon_speed(hw, phystat);
2018
2019 if (istatus & PHY_M_IS_DUP_CHANGE)
2020 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2021 if (istatus & PHY_M_IS_LST_CHANGE) {
2022 if (phystat & PHY_M_PS_LINK_UP)
2023 yukon_link_up(skge);
2024 else
2025 yukon_link_down(skge);
2026 }
2027 return;
2028 failed:
2029 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2030 skge->netdev->name, reason);
2031
2032 /* XXX restart autonegotiation? */
2033 }
2034
2035 static void skge_phy_reset(struct skge_port *skge)
2036 {
2037 struct skge_hw *hw = skge->hw;
2038 int port = skge->port;
2039
2040 netif_stop_queue(skge->netdev);
2041 netif_carrier_off(skge->netdev);
2042
2043 spin_lock_bh(&hw->phy_lock);
2044 if (hw->chip_id == CHIP_ID_GENESIS) {
2045 genesis_reset(hw, port);
2046 genesis_mac_init(hw, port);
2047 } else {
2048 yukon_reset(hw, port);
2049 yukon_init(hw, port);
2050 }
2051 spin_unlock_bh(&hw->phy_lock);
2052 }
2053
2054 /* Basic MII support */
2055 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2056 {
2057 struct mii_ioctl_data *data = if_mii(ifr);
2058 struct skge_port *skge = netdev_priv(dev);
2059 struct skge_hw *hw = skge->hw;
2060 int err = -EOPNOTSUPP;
2061
2062 if (!netif_running(dev))
2063 return -ENODEV; /* Phy still in reset */
2064
2065 switch(cmd) {
2066 case SIOCGMIIPHY:
2067 data->phy_id = hw->phy_addr;
2068
2069 /* fallthru */
2070 case SIOCGMIIREG: {
2071 u16 val = 0;
2072 spin_lock_bh(&hw->phy_lock);
2073 if (hw->chip_id == CHIP_ID_GENESIS)
2074 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2075 else
2076 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2077 spin_unlock_bh(&hw->phy_lock);
2078 data->val_out = val;
2079 break;
2080 }
2081
2082 case SIOCSMIIREG:
2083 if (!capable(CAP_NET_ADMIN))
2084 return -EPERM;
2085
2086 spin_lock_bh(&hw->phy_lock);
2087 if (hw->chip_id == CHIP_ID_GENESIS)
2088 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2089 data->val_in);
2090 else
2091 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2092 data->val_in);
2093 spin_unlock_bh(&hw->phy_lock);
2094 break;
2095 }
2096 return err;
2097 }
2098
2099 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2100 {
2101 u32 end;
2102
2103 start /= 8;
2104 len /= 8;
2105 end = start + len - 1;
2106
2107 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2108 skge_write32(hw, RB_ADDR(q, RB_START), start);
2109 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2110 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2111 skge_write32(hw, RB_ADDR(q, RB_END), end);
2112
2113 if (q == Q_R1 || q == Q_R2) {
2114 /* Set thresholds on receive queue's */
2115 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2116 start + (2*len)/3);
2117 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2118 start + (len/3));
2119 } else {
2120 /* Enable store & forward on Tx queue's because
2121 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2122 */
2123 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2124 }
2125
2126 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2127 }
2128
2129 /* Setup Bus Memory Interface */
2130 static void skge_qset(struct skge_port *skge, u16 q,
2131 const struct skge_element *e)
2132 {
2133 struct skge_hw *hw = skge->hw;
2134 u32 watermark = 0x600;
2135 u64 base = skge->dma + (e->desc - skge->mem);
2136
2137 /* optimization to reduce window on 32bit/33mhz */
2138 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2139 watermark /= 2;
2140
2141 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2142 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2143 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2144 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2145 }
2146
2147 static int skge_up(struct net_device *dev)
2148 {
2149 struct skge_port *skge = netdev_priv(dev);
2150 struct skge_hw *hw = skge->hw;
2151 int port = skge->port;
2152 u32 chunk, ram_addr;
2153 size_t rx_size, tx_size;
2154 int err;
2155
2156 if (netif_msg_ifup(skge))
2157 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2158
2159 if (dev->mtu > RX_BUF_SIZE)
2160 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2161 else
2162 skge->rx_buf_size = RX_BUF_SIZE;
2163
2164
2165 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2166 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2167 skge->mem_size = tx_size + rx_size;
2168 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2169 if (!skge->mem)
2170 return -ENOMEM;
2171
2172 memset(skge->mem, 0, skge->mem_size);
2173
2174 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2175 goto free_pci_mem;
2176
2177 err = skge_rx_fill(skge);
2178 if (err)
2179 goto free_rx_ring;
2180
2181 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2182 skge->dma + rx_size)))
2183 goto free_rx_ring;
2184
2185 skge->tx_avail = skge->tx_ring.count - 1;
2186
2187 /* Enable IRQ from port */
2188 spin_lock_irq(&hw->hw_lock);
2189 hw->intr_mask |= portirqmask[port];
2190 skge_write32(hw, B0_IMSK, hw->intr_mask);
2191 spin_unlock_irq(&hw->hw_lock);
2192
2193 /* Initialize MAC */
2194 spin_lock_bh(&hw->phy_lock);
2195 if (hw->chip_id == CHIP_ID_GENESIS)
2196 genesis_mac_init(hw, port);
2197 else
2198 yukon_mac_init(hw, port);
2199 spin_unlock_bh(&hw->phy_lock);
2200
2201 /* Configure RAMbuffers */
2202 chunk = hw->ram_size / ((hw->ports + 1)*2);
2203 ram_addr = hw->ram_offset + 2 * chunk * port;
2204
2205 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2206 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2207
2208 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2209 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2210 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2211
2212 /* Start receiver BMU */
2213 wmb();
2214 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2215 skge_led(skge, LED_MODE_ON);
2216
2217 return 0;
2218
2219 free_rx_ring:
2220 skge_rx_clean(skge);
2221 kfree(skge->rx_ring.start);
2222 free_pci_mem:
2223 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2224 skge->mem = NULL;
2225
2226 return err;
2227 }
2228
2229 static int skge_down(struct net_device *dev)
2230 {
2231 struct skge_port *skge = netdev_priv(dev);
2232 struct skge_hw *hw = skge->hw;
2233 int port = skge->port;
2234
2235 if (skge->mem == NULL)
2236 return 0;
2237
2238 if (netif_msg_ifdown(skge))
2239 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2240
2241 netif_stop_queue(dev);
2242
2243 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2244 if (hw->chip_id == CHIP_ID_GENESIS)
2245 genesis_stop(skge);
2246 else
2247 yukon_stop(skge);
2248
2249 spin_lock_irq(&hw->hw_lock);
2250 hw->intr_mask &= ~portirqmask[skge->port];
2251 skge_write32(hw, B0_IMSK, hw->intr_mask);
2252 spin_unlock_irq(&hw->hw_lock);
2253
2254 /* Stop transmitter */
2255 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2256 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2257 RB_RST_SET|RB_DIS_OP_MD);
2258
2259
2260 /* Disable Force Sync bit and Enable Alloc bit */
2261 skge_write8(hw, SK_REG(port, TXA_CTRL),
2262 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2263
2264 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2265 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2266 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2267
2268 /* Reset PCI FIFO */
2269 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2270 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2271
2272 /* Reset the RAM Buffer async Tx queue */
2273 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2274 /* stop receiver */
2275 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2276 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2277 RB_RST_SET|RB_DIS_OP_MD);
2278 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2279
2280 if (hw->chip_id == CHIP_ID_GENESIS) {
2281 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2282 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2283 } else {
2284 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2285 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2286 }
2287
2288 skge_led(skge, LED_MODE_OFF);
2289
2290 skge_tx_clean(skge);
2291 skge_rx_clean(skge);
2292
2293 kfree(skge->rx_ring.start);
2294 kfree(skge->tx_ring.start);
2295 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2296 skge->mem = NULL;
2297 return 0;
2298 }
2299
2300 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2301 {
2302 struct skge_port *skge = netdev_priv(dev);
2303 struct skge_hw *hw = skge->hw;
2304 struct skge_ring *ring = &skge->tx_ring;
2305 struct skge_element *e;
2306 struct skge_tx_desc *td;
2307 int i;
2308 u32 control, len;
2309 u64 map;
2310
2311 skb = skb_padto(skb, ETH_ZLEN);
2312 if (!skb)
2313 return NETDEV_TX_OK;
2314
2315 if (!spin_trylock(&skge->tx_lock)) {
2316 /* Collision - tell upper layer to requeue */
2317 return NETDEV_TX_LOCKED;
2318 }
2319
2320 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2321 if (!netif_queue_stopped(dev)) {
2322 netif_stop_queue(dev);
2323
2324 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2325 dev->name);
2326 }
2327 spin_unlock(&skge->tx_lock);
2328 return NETDEV_TX_BUSY;
2329 }
2330
2331 e = ring->to_use;
2332 td = e->desc;
2333 e->skb = skb;
2334 len = skb_headlen(skb);
2335 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2336 pci_unmap_addr_set(e, mapaddr, map);
2337 pci_unmap_len_set(e, maplen, len);
2338
2339 td->dma_lo = map;
2340 td->dma_hi = map >> 32;
2341
2342 if (skb->ip_summed == CHECKSUM_HW) {
2343 int offset = skb->h.raw - skb->data;
2344
2345 /* This seems backwards, but it is what the sk98lin
2346 * does. Looks like hardware is wrong?
2347 */
2348 if (skb->h.ipiph->protocol == IPPROTO_UDP
2349 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2350 control = BMU_TCP_CHECK;
2351 else
2352 control = BMU_UDP_CHECK;
2353
2354 td->csum_offs = 0;
2355 td->csum_start = offset;
2356 td->csum_write = offset + skb->csum;
2357 } else
2358 control = BMU_CHECK;
2359
2360 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2361 control |= BMU_EOF| BMU_IRQ_EOF;
2362 else {
2363 struct skge_tx_desc *tf = td;
2364
2365 control |= BMU_STFWD;
2366 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2367 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2368
2369 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2370 frag->size, PCI_DMA_TODEVICE);
2371
2372 e = e->next;
2373 e->skb = NULL;
2374 tf = e->desc;
2375 tf->dma_lo = map;
2376 tf->dma_hi = (u64) map >> 32;
2377 pci_unmap_addr_set(e, mapaddr, map);
2378 pci_unmap_len_set(e, maplen, frag->size);
2379
2380 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2381 }
2382 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2383 }
2384 /* Make sure all the descriptors written */
2385 wmb();
2386 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2387 wmb();
2388
2389 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2390
2391 if (netif_msg_tx_queued(skge))
2392 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2393 dev->name, e - ring->start, skb->len);
2394
2395 ring->to_use = e->next;
2396 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2397 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2398 pr_debug("%s: transmit queue full\n", dev->name);
2399 netif_stop_queue(dev);
2400 }
2401
2402 dev->trans_start = jiffies;
2403 spin_unlock(&skge->tx_lock);
2404
2405 return NETDEV_TX_OK;
2406 }
2407
2408 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2409 {
2410 /* This ring element can be skb or fragment */
2411 if (e->skb) {
2412 pci_unmap_single(hw->pdev,
2413 pci_unmap_addr(e, mapaddr),
2414 pci_unmap_len(e, maplen),
2415 PCI_DMA_TODEVICE);
2416 dev_kfree_skb(e->skb);
2417 e->skb = NULL;
2418 } else {
2419 pci_unmap_page(hw->pdev,
2420 pci_unmap_addr(e, mapaddr),
2421 pci_unmap_len(e, maplen),
2422 PCI_DMA_TODEVICE);
2423 }
2424 }
2425
2426 static void skge_tx_clean(struct skge_port *skge)
2427 {
2428 struct skge_ring *ring = &skge->tx_ring;
2429 struct skge_element *e;
2430
2431 spin_lock_bh(&skge->tx_lock);
2432 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2433 ++skge->tx_avail;
2434 skge_tx_free(skge->hw, e);
2435 }
2436 ring->to_clean = e;
2437 spin_unlock_bh(&skge->tx_lock);
2438 }
2439
2440 static void skge_tx_timeout(struct net_device *dev)
2441 {
2442 struct skge_port *skge = netdev_priv(dev);
2443
2444 if (netif_msg_timer(skge))
2445 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2446
2447 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2448 skge_tx_clean(skge);
2449 }
2450
2451 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2452 {
2453 int err;
2454
2455 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2456 return -EINVAL;
2457
2458 if (!netif_running(dev)) {
2459 dev->mtu = new_mtu;
2460 return 0;
2461 }
2462
2463 skge_down(dev);
2464
2465 dev->mtu = new_mtu;
2466
2467 err = skge_up(dev);
2468 if (err)
2469 dev_close(dev);
2470
2471 return err;
2472 }
2473
2474 static void genesis_set_multicast(struct net_device *dev)
2475 {
2476 struct skge_port *skge = netdev_priv(dev);
2477 struct skge_hw *hw = skge->hw;
2478 int port = skge->port;
2479 int i, count = dev->mc_count;
2480 struct dev_mc_list *list = dev->mc_list;
2481 u32 mode;
2482 u8 filter[8];
2483
2484 mode = xm_read32(hw, port, XM_MODE);
2485 mode |= XM_MD_ENA_HASH;
2486 if (dev->flags & IFF_PROMISC)
2487 mode |= XM_MD_ENA_PROM;
2488 else
2489 mode &= ~XM_MD_ENA_PROM;
2490
2491 if (dev->flags & IFF_ALLMULTI)
2492 memset(filter, 0xff, sizeof(filter));
2493 else {
2494 memset(filter, 0, sizeof(filter));
2495 for (i = 0; list && i < count; i++, list = list->next) {
2496 u32 crc, bit;
2497 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2498 bit = ~crc & 0x3f;
2499 filter[bit/8] |= 1 << (bit%8);
2500 }
2501 }
2502
2503 xm_write32(hw, port, XM_MODE, mode);
2504 xm_outhash(hw, port, XM_HSM, filter);
2505 }
2506
2507 static void yukon_set_multicast(struct net_device *dev)
2508 {
2509 struct skge_port *skge = netdev_priv(dev);
2510 struct skge_hw *hw = skge->hw;
2511 int port = skge->port;
2512 struct dev_mc_list *list = dev->mc_list;
2513 u16 reg;
2514 u8 filter[8];
2515
2516 memset(filter, 0, sizeof(filter));
2517
2518 reg = gma_read16(hw, port, GM_RX_CTRL);
2519 reg |= GM_RXCR_UCF_ENA;
2520
2521 if (dev->flags & IFF_PROMISC) /* promiscuous */
2522 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2523 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2524 memset(filter, 0xff, sizeof(filter));
2525 else if (dev->mc_count == 0) /* no multicast */
2526 reg &= ~GM_RXCR_MCF_ENA;
2527 else {
2528 int i;
2529 reg |= GM_RXCR_MCF_ENA;
2530
2531 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2532 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2533 filter[bit/8] |= 1 << (bit%8);
2534 }
2535 }
2536
2537
2538 gma_write16(hw, port, GM_MC_ADDR_H1,
2539 (u16)filter[0] | ((u16)filter[1] << 8));
2540 gma_write16(hw, port, GM_MC_ADDR_H2,
2541 (u16)filter[2] | ((u16)filter[3] << 8));
2542 gma_write16(hw, port, GM_MC_ADDR_H3,
2543 (u16)filter[4] | ((u16)filter[5] << 8));
2544 gma_write16(hw, port, GM_MC_ADDR_H4,
2545 (u16)filter[6] | ((u16)filter[7] << 8));
2546
2547 gma_write16(hw, port, GM_RX_CTRL, reg);
2548 }
2549
2550 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2551 {
2552 if (hw->chip_id == CHIP_ID_GENESIS)
2553 return status >> XMR_FS_LEN_SHIFT;
2554 else
2555 return status >> GMR_FS_LEN_SHIFT;
2556 }
2557
2558 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2559 {
2560 if (hw->chip_id == CHIP_ID_GENESIS)
2561 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2562 else
2563 return (status & GMR_FS_ANY_ERR) ||
2564 (status & GMR_FS_RX_OK) == 0;
2565 }
2566
2567
2568 /* Get receive buffer from descriptor.
2569 * Handles copy of small buffers and reallocation failures
2570 */
2571 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2572 struct skge_element *e,
2573 u32 control, u32 status, u16 csum)
2574 {
2575 struct sk_buff *skb;
2576 u16 len = control & BMU_BBC;
2577
2578 if (unlikely(netif_msg_rx_status(skge)))
2579 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2580 skge->netdev->name, e - skge->rx_ring.start,
2581 status, len);
2582
2583 if (len > skge->rx_buf_size)
2584 goto error;
2585
2586 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2587 goto error;
2588
2589 if (bad_phy_status(skge->hw, status))
2590 goto error;
2591
2592 if (phy_length(skge->hw, status) != len)
2593 goto error;
2594
2595 if (len < RX_COPY_THRESHOLD) {
2596 skb = dev_alloc_skb(len + 2);
2597 if (!skb)
2598 goto resubmit;
2599
2600 skb_reserve(skb, 2);
2601 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2602 pci_unmap_addr(e, mapaddr),
2603 len, PCI_DMA_FROMDEVICE);
2604 memcpy(skb->data, e->skb->data, len);
2605 pci_dma_sync_single_for_device(skge->hw->pdev,
2606 pci_unmap_addr(e, mapaddr),
2607 len, PCI_DMA_FROMDEVICE);
2608 skge_rx_reuse(e, skge->rx_buf_size);
2609 } else {
2610 struct sk_buff *nskb;
2611 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2612 if (!nskb)
2613 goto resubmit;
2614
2615 pci_unmap_single(skge->hw->pdev,
2616 pci_unmap_addr(e, mapaddr),
2617 pci_unmap_len(e, maplen),
2618 PCI_DMA_FROMDEVICE);
2619 skb = e->skb;
2620 prefetch(skb->data);
2621 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2622 }
2623
2624 skb_put(skb, len);
2625 skb->dev = skge->netdev;
2626 if (skge->rx_csum) {
2627 skb->csum = csum;
2628 skb->ip_summed = CHECKSUM_HW;
2629 }
2630
2631 skb->protocol = eth_type_trans(skb, skge->netdev);
2632
2633 return skb;
2634 error:
2635
2636 if (netif_msg_rx_err(skge))
2637 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2638 skge->netdev->name, e - skge->rx_ring.start,
2639 control, status);
2640
2641 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2642 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2643 skge->net_stats.rx_length_errors++;
2644 if (status & XMR_FS_FRA_ERR)
2645 skge->net_stats.rx_frame_errors++;
2646 if (status & XMR_FS_FCS_ERR)
2647 skge->net_stats.rx_crc_errors++;
2648 } else {
2649 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2650 skge->net_stats.rx_length_errors++;
2651 if (status & GMR_FS_FRAGMENT)
2652 skge->net_stats.rx_frame_errors++;
2653 if (status & GMR_FS_CRC_ERR)
2654 skge->net_stats.rx_crc_errors++;
2655 }
2656
2657 resubmit:
2658 skge_rx_reuse(e, skge->rx_buf_size);
2659 return NULL;
2660 }
2661
2662 static void skge_tx_done(struct skge_port *skge)
2663 {
2664 struct skge_ring *ring = &skge->tx_ring;
2665 struct skge_element *e;
2666
2667 spin_lock(&skge->tx_lock);
2668 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2669 struct skge_tx_desc *td = e->desc;
2670 u32 control;
2671
2672 rmb();
2673 control = td->control;
2674 if (control & BMU_OWN)
2675 break;
2676
2677 if (unlikely(netif_msg_tx_done(skge)))
2678 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2679 skge->netdev->name, e - ring->start, td->status);
2680
2681 skge_tx_free(skge->hw, e);
2682 e->skb = NULL;
2683 ++skge->tx_avail;
2684 }
2685 ring->to_clean = e;
2686 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2687
2688 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2689 netif_wake_queue(skge->netdev);
2690
2691 spin_unlock(&skge->tx_lock);
2692 }
2693
2694 static int skge_poll(struct net_device *dev, int *budget)
2695 {
2696 struct skge_port *skge = netdev_priv(dev);
2697 struct skge_hw *hw = skge->hw;
2698 struct skge_ring *ring = &skge->rx_ring;
2699 struct skge_element *e;
2700 int to_do = min(dev->quota, *budget);
2701 int work_done = 0;
2702
2703 skge_tx_done(skge);
2704
2705 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2706 struct skge_rx_desc *rd = e->desc;
2707 struct sk_buff *skb;
2708 u32 control;
2709
2710 rmb();
2711 control = rd->control;
2712 if (control & BMU_OWN)
2713 break;
2714
2715 skb = skge_rx_get(skge, e, control, rd->status,
2716 le16_to_cpu(rd->csum2));
2717 if (likely(skb)) {
2718 dev->last_rx = jiffies;
2719 netif_receive_skb(skb);
2720
2721 ++work_done;
2722 } else
2723 skge_rx_reuse(e, skge->rx_buf_size);
2724 }
2725 ring->to_clean = e;
2726
2727 /* restart receiver */
2728 wmb();
2729 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2730
2731 *budget -= work_done;
2732 dev->quota -= work_done;
2733
2734 if (work_done >= to_do)
2735 return 1; /* not done */
2736
2737 spin_lock_irq(&hw->hw_lock);
2738 __netif_rx_complete(dev);
2739 hw->intr_mask |= portirqmask[skge->port];
2740 skge_write32(hw, B0_IMSK, hw->intr_mask);
2741 spin_unlock_irq(&hw->hw_lock);
2742
2743 return 0;
2744 }
2745
2746 /* Parity errors seem to happen when Genesis is connected to a switch
2747 * with no other ports present. Heartbeat error??
2748 */
2749 static void skge_mac_parity(struct skge_hw *hw, int port)
2750 {
2751 struct net_device *dev = hw->dev[port];
2752
2753 if (dev) {
2754 struct skge_port *skge = netdev_priv(dev);
2755 ++skge->net_stats.tx_heartbeat_errors;
2756 }
2757
2758 if (hw->chip_id == CHIP_ID_GENESIS)
2759 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2760 MFF_CLR_PERR);
2761 else
2762 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2763 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2764 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2765 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2766 }
2767
2768 static void skge_pci_clear(struct skge_hw *hw)
2769 {
2770 u16 status;
2771
2772 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2773 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2774 pci_write_config_word(hw->pdev, PCI_STATUS,
2775 status | PCI_STATUS_ERROR_BITS);
2776 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2777 }
2778
2779 static void skge_mac_intr(struct skge_hw *hw, int port)
2780 {
2781 if (hw->chip_id == CHIP_ID_GENESIS)
2782 genesis_mac_intr(hw, port);
2783 else
2784 yukon_mac_intr(hw, port);
2785 }
2786
2787 /* Handle device specific framing and timeout interrupts */
2788 static void skge_error_irq(struct skge_hw *hw)
2789 {
2790 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2791
2792 if (hw->chip_id == CHIP_ID_GENESIS) {
2793 /* clear xmac errors */
2794 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2795 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2796 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2797 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2798 } else {
2799 /* Timestamp (unused) overflow */
2800 if (hwstatus & IS_IRQ_TIST_OV)
2801 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2802 }
2803
2804 if (hwstatus & IS_RAM_RD_PAR) {
2805 printk(KERN_ERR PFX "Ram read data parity error\n");
2806 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2807 }
2808
2809 if (hwstatus & IS_RAM_WR_PAR) {
2810 printk(KERN_ERR PFX "Ram write data parity error\n");
2811 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2812 }
2813
2814 if (hwstatus & IS_M1_PAR_ERR)
2815 skge_mac_parity(hw, 0);
2816
2817 if (hwstatus & IS_M2_PAR_ERR)
2818 skge_mac_parity(hw, 1);
2819
2820 if (hwstatus & IS_R1_PAR_ERR)
2821 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2822
2823 if (hwstatus & IS_R2_PAR_ERR)
2824 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2825
2826 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2827 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2828 hwstatus);
2829
2830 skge_pci_clear(hw);
2831
2832 /* if error still set then just ignore it */
2833 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2834 if (hwstatus & IS_IRQ_STAT) {
2835 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2836 hwstatus);
2837 hw->intr_mask &= ~IS_HW_ERR;
2838 }
2839 }
2840 }
2841
2842 /*
2843 * Interrupt from PHY are handled in tasklet (soft irq)
2844 * because accessing phy registers requires spin wait which might
2845 * cause excess interrupt latency.
2846 */
2847 static void skge_extirq(unsigned long data)
2848 {
2849 struct skge_hw *hw = (struct skge_hw *) data;
2850 int port;
2851
2852 spin_lock(&hw->phy_lock);
2853 for (port = 0; port < 2; port++) {
2854 struct net_device *dev = hw->dev[port];
2855
2856 if (dev && netif_running(dev)) {
2857 struct skge_port *skge = netdev_priv(dev);
2858
2859 if (hw->chip_id != CHIP_ID_GENESIS)
2860 yukon_phy_intr(skge);
2861 else
2862 bcom_phy_intr(skge);
2863 }
2864 }
2865 spin_unlock(&hw->phy_lock);
2866
2867 spin_lock_irq(&hw->hw_lock);
2868 hw->intr_mask |= IS_EXT_REG;
2869 skge_write32(hw, B0_IMSK, hw->intr_mask);
2870 spin_unlock_irq(&hw->hw_lock);
2871 }
2872
2873 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2874 {
2875 struct skge_hw *hw = dev_id;
2876 u32 status = skge_read32(hw, B0_SP_ISRC);
2877
2878 if (status == 0 || status == ~0) /* hotplug or shared irq */
2879 return IRQ_NONE;
2880
2881 spin_lock(&hw->hw_lock);
2882 if (status & (IS_R1_F|IS_XA1_F)) {
2883 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2884 hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);
2885 netif_rx_schedule(hw->dev[0]);
2886 }
2887
2888 if (status & (IS_R2_F|IS_XA2_F)) {
2889 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2890 hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);
2891 netif_rx_schedule(hw->dev[1]);
2892 }
2893
2894 if (status & IS_PA_TO_RX1) {
2895 struct skge_port *skge = netdev_priv(hw->dev[0]);
2896 ++skge->net_stats.rx_over_errors;
2897 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2898 }
2899
2900 if (status & IS_PA_TO_RX2) {
2901 struct skge_port *skge = netdev_priv(hw->dev[1]);
2902 ++skge->net_stats.rx_over_errors;
2903 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2904 }
2905
2906 if (status & IS_PA_TO_TX1)
2907 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2908
2909 if (status & IS_PA_TO_TX2)
2910 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2911
2912 if (status & IS_MAC1)
2913 skge_mac_intr(hw, 0);
2914
2915 if (status & IS_MAC2)
2916 skge_mac_intr(hw, 1);
2917
2918 if (status & IS_HW_ERR)
2919 skge_error_irq(hw);
2920
2921 if (status & IS_EXT_REG) {
2922 hw->intr_mask &= ~IS_EXT_REG;
2923 tasklet_schedule(&hw->ext_tasklet);
2924 }
2925
2926 skge_write32(hw, B0_IMSK, hw->intr_mask);
2927 spin_unlock(&hw->hw_lock);
2928
2929 return IRQ_HANDLED;
2930 }
2931
2932 #ifdef CONFIG_NET_POLL_CONTROLLER
2933 static void skge_netpoll(struct net_device *dev)
2934 {
2935 struct skge_port *skge = netdev_priv(dev);
2936
2937 disable_irq(dev->irq);
2938 skge_intr(dev->irq, skge->hw, NULL);
2939 enable_irq(dev->irq);
2940 }
2941 #endif
2942
2943 static int skge_set_mac_address(struct net_device *dev, void *p)
2944 {
2945 struct skge_port *skge = netdev_priv(dev);
2946 struct skge_hw *hw = skge->hw;
2947 unsigned port = skge->port;
2948 const struct sockaddr *addr = p;
2949
2950 if (!is_valid_ether_addr(addr->sa_data))
2951 return -EADDRNOTAVAIL;
2952
2953 spin_lock_bh(&hw->phy_lock);
2954 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2955 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2956 dev->dev_addr, ETH_ALEN);
2957 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2958 dev->dev_addr, ETH_ALEN);
2959
2960 if (hw->chip_id == CHIP_ID_GENESIS)
2961 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2962 else {
2963 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2964 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2965 }
2966 spin_unlock_bh(&hw->phy_lock);
2967
2968 return 0;
2969 }
2970
2971 static const struct {
2972 u8 id;
2973 const char *name;
2974 } skge_chips[] = {
2975 { CHIP_ID_GENESIS, "Genesis" },
2976 { CHIP_ID_YUKON, "Yukon" },
2977 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2978 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2979 };
2980
2981 static const char *skge_board_name(const struct skge_hw *hw)
2982 {
2983 int i;
2984 static char buf[16];
2985
2986 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2987 if (skge_chips[i].id == hw->chip_id)
2988 return skge_chips[i].name;
2989
2990 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2991 return buf;
2992 }
2993
2994
2995 /*
2996 * Setup the board data structure, but don't bring up
2997 * the port(s)
2998 */
2999 static int skge_reset(struct skge_hw *hw)
3000 {
3001 u32 reg;
3002 u16 ctst;
3003 u8 t8, mac_cfg, pmd_type, phy_type;
3004 int i;
3005
3006 ctst = skge_read16(hw, B0_CTST);
3007
3008 /* do a SW reset */
3009 skge_write8(hw, B0_CTST, CS_RST_SET);
3010 skge_write8(hw, B0_CTST, CS_RST_CLR);
3011
3012 /* clear PCI errors, if any */
3013 skge_pci_clear(hw);
3014
3015 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3016
3017 /* restore CLK_RUN bits (for Yukon-Lite) */
3018 skge_write16(hw, B0_CTST,
3019 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3020
3021 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3022 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3023 pmd_type = skge_read8(hw, B2_PMD_TYP);
3024 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3025
3026 switch (hw->chip_id) {
3027 case CHIP_ID_GENESIS:
3028 switch (phy_type) {
3029 case SK_PHY_BCOM:
3030 hw->phy_addr = PHY_ADDR_BCOM;
3031 break;
3032 default:
3033 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3034 pci_name(hw->pdev), phy_type);
3035 return -EOPNOTSUPP;
3036 }
3037 break;
3038
3039 case CHIP_ID_YUKON:
3040 case CHIP_ID_YUKON_LITE:
3041 case CHIP_ID_YUKON_LP:
3042 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3043 hw->copper = 1;
3044
3045 hw->phy_addr = PHY_ADDR_MARV;
3046 break;
3047
3048 default:
3049 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3050 pci_name(hw->pdev), hw->chip_id);
3051 return -EOPNOTSUPP;
3052 }
3053
3054 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3055 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3056 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3057
3058 /* read the adapters RAM size */
3059 t8 = skge_read8(hw, B2_E_0);
3060 if (hw->chip_id == CHIP_ID_GENESIS) {
3061 if (t8 == 3) {
3062 /* special case: 4 x 64k x 36, offset = 0x80000 */
3063 hw->ram_size = 0x100000;
3064 hw->ram_offset = 0x80000;
3065 } else
3066 hw->ram_size = t8 * 512;
3067 }
3068 else if (t8 == 0)
3069 hw->ram_size = 0x20000;
3070 else
3071 hw->ram_size = t8 * 4096;
3072
3073 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
3074 if (hw->chip_id == CHIP_ID_GENESIS)
3075 genesis_init(hw);
3076 else {
3077 /* switch power to VCC (WA for VAUX problem) */
3078 skge_write8(hw, B0_POWER_CTRL,
3079 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3080
3081 /* avoid boards with stuck Hardware error bits */
3082 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3083 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3084 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3085 hw->intr_mask &= ~IS_HW_ERR;
3086 }
3087
3088 /* Clear PHY COMA */
3089 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3090 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3091 reg &= ~PCI_PHY_COMA;
3092 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3093 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3094
3095
3096 for (i = 0; i < hw->ports; i++) {
3097 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3098 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3099 }
3100 }
3101
3102 /* turn off hardware timer (unused) */
3103 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3104 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3105 skge_write8(hw, B0_LED, LED_STAT_ON);
3106
3107 /* enable the Tx Arbiters */
3108 for (i = 0; i < hw->ports; i++)
3109 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3110
3111 /* Initialize ram interface */
3112 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3113
3114 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3115 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3116 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3117 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3118 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3119 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3120 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3121 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3122 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3123 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3124 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3125 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3126
3127 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3128
3129 /* Set interrupt moderation for Transmit only
3130 * Receive interrupts avoided by NAPI
3131 */
3132 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3133 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3134 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3135
3136 skge_write32(hw, B0_IMSK, hw->intr_mask);
3137
3138 spin_lock_bh(&hw->phy_lock);
3139 for (i = 0; i < hw->ports; i++) {
3140 if (hw->chip_id == CHIP_ID_GENESIS)
3141 genesis_reset(hw, i);
3142 else
3143 yukon_reset(hw, i);
3144 }
3145 spin_unlock_bh(&hw->phy_lock);
3146
3147 return 0;
3148 }
3149
3150 /* Initialize network device */
3151 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3152 int highmem)
3153 {
3154 struct skge_port *skge;
3155 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3156
3157 if (!dev) {
3158 printk(KERN_ERR "skge etherdev alloc failed");
3159 return NULL;
3160 }
3161
3162 SET_MODULE_OWNER(dev);
3163 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3164 dev->open = skge_up;
3165 dev->stop = skge_down;
3166 dev->do_ioctl = skge_ioctl;
3167 dev->hard_start_xmit = skge_xmit_frame;
3168 dev->get_stats = skge_get_stats;
3169 if (hw->chip_id == CHIP_ID_GENESIS)
3170 dev->set_multicast_list = genesis_set_multicast;
3171 else
3172 dev->set_multicast_list = yukon_set_multicast;
3173
3174 dev->set_mac_address = skge_set_mac_address;
3175 dev->change_mtu = skge_change_mtu;
3176 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3177 dev->tx_timeout = skge_tx_timeout;
3178 dev->watchdog_timeo = TX_WATCHDOG;
3179 dev->poll = skge_poll;
3180 dev->weight = NAPI_WEIGHT;
3181 #ifdef CONFIG_NET_POLL_CONTROLLER
3182 dev->poll_controller = skge_netpoll;
3183 #endif
3184 dev->irq = hw->pdev->irq;
3185 dev->features = NETIF_F_LLTX;
3186 if (highmem)
3187 dev->features |= NETIF_F_HIGHDMA;
3188
3189 skge = netdev_priv(dev);
3190 skge->netdev = dev;
3191 skge->hw = hw;
3192 skge->msg_enable = netif_msg_init(debug, default_msg);
3193 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3194 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3195
3196 /* Auto speed and flow control */
3197 skge->autoneg = AUTONEG_ENABLE;
3198 skge->flow_control = FLOW_MODE_SYMMETRIC;
3199 skge->duplex = -1;
3200 skge->speed = -1;
3201 skge->advertising = skge_supported_modes(hw);
3202
3203 hw->dev[port] = dev;
3204
3205 skge->port = port;
3206
3207 spin_lock_init(&skge->tx_lock);
3208
3209 if (hw->chip_id != CHIP_ID_GENESIS) {
3210 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3211 skge->rx_csum = 1;
3212 }
3213
3214 /* read the mac address */
3215 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3216 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3217
3218 /* device is off until link detection */
3219 netif_carrier_off(dev);
3220 netif_stop_queue(dev);
3221
3222 return dev;
3223 }
3224
3225 static void __devinit skge_show_addr(struct net_device *dev)
3226 {
3227 const struct skge_port *skge = netdev_priv(dev);
3228
3229 if (netif_msg_probe(skge))
3230 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3231 dev->name,
3232 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3233 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3234 }
3235
3236 static int __devinit skge_probe(struct pci_dev *pdev,
3237 const struct pci_device_id *ent)
3238 {
3239 struct net_device *dev, *dev1;
3240 struct skge_hw *hw;
3241 int err, using_dac = 0;
3242
3243 if ((err = pci_enable_device(pdev))) {
3244 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3245 pci_name(pdev));
3246 goto err_out;
3247 }
3248
3249 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3250 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3251 pci_name(pdev));
3252 goto err_out_disable_pdev;
3253 }
3254
3255 pci_set_master(pdev);
3256
3257 if (sizeof(dma_addr_t) > sizeof(u32) &&
3258 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3259 using_dac = 1;
3260 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3261 if (err < 0) {
3262 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3263 "for consistent allocations\n", pci_name(pdev));
3264 goto err_out_free_regions;
3265 }
3266 } else {
3267 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3268 if (err) {
3269 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3270 pci_name(pdev));
3271 goto err_out_free_regions;
3272 }
3273 }
3274
3275 #ifdef __BIG_ENDIAN
3276 /* byte swap descriptors in hardware */
3277 {
3278 u32 reg;
3279
3280 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3281 reg |= PCI_REV_DESC;
3282 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3283 }
3284 #endif
3285
3286 err = -ENOMEM;
3287 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3288 if (!hw) {
3289 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3290 pci_name(pdev));
3291 goto err_out_free_regions;
3292 }
3293
3294 hw->pdev = pdev;
3295 spin_lock_init(&hw->phy_lock);
3296 spin_lock_init(&hw->hw_lock);
3297 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3298
3299 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3300 if (!hw->regs) {
3301 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3302 pci_name(pdev));
3303 goto err_out_free_hw;
3304 }
3305
3306 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3307 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3308 pci_name(pdev), pdev->irq);
3309 goto err_out_iounmap;
3310 }
3311 pci_set_drvdata(pdev, hw);
3312
3313 err = skge_reset(hw);
3314 if (err)
3315 goto err_out_free_irq;
3316
3317 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3318 pci_resource_start(pdev, 0), pdev->irq,
3319 skge_board_name(hw), hw->chip_rev);
3320
3321 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3322 goto err_out_led_off;
3323
3324 if ((err = register_netdev(dev))) {
3325 printk(KERN_ERR PFX "%s: cannot register net device\n",
3326 pci_name(pdev));
3327 goto err_out_free_netdev;
3328 }
3329
3330 skge_show_addr(dev);
3331
3332 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3333 if (register_netdev(dev1) == 0)
3334 skge_show_addr(dev1);
3335 else {
3336 /* Failure to register second port need not be fatal */
3337 printk(KERN_WARNING PFX "register of second port failed\n");
3338 hw->dev[1] = NULL;
3339 free_netdev(dev1);
3340 }
3341 }
3342
3343 return 0;
3344
3345 err_out_free_netdev:
3346 free_netdev(dev);
3347 err_out_led_off:
3348 skge_write16(hw, B0_LED, LED_STAT_OFF);
3349 err_out_free_irq:
3350 free_irq(pdev->irq, hw);
3351 err_out_iounmap:
3352 iounmap(hw->regs);
3353 err_out_free_hw:
3354 kfree(hw);
3355 err_out_free_regions:
3356 pci_release_regions(pdev);
3357 err_out_disable_pdev:
3358 pci_disable_device(pdev);
3359 pci_set_drvdata(pdev, NULL);
3360 err_out:
3361 return err;
3362 }
3363
3364 static void __devexit skge_remove(struct pci_dev *pdev)
3365 {
3366 struct skge_hw *hw = pci_get_drvdata(pdev);
3367 struct net_device *dev0, *dev1;
3368
3369 if (!hw)
3370 return;
3371
3372 if ((dev1 = hw->dev[1]))
3373 unregister_netdev(dev1);
3374 dev0 = hw->dev[0];
3375 unregister_netdev(dev0);
3376
3377 skge_write32(hw, B0_IMSK, 0);
3378 skge_write16(hw, B0_LED, LED_STAT_OFF);
3379 skge_pci_clear(hw);
3380 skge_write8(hw, B0_CTST, CS_RST_SET);
3381
3382 tasklet_kill(&hw->ext_tasklet);
3383
3384 free_irq(pdev->irq, hw);
3385 pci_release_regions(pdev);
3386 pci_disable_device(pdev);
3387 if (dev1)
3388 free_netdev(dev1);
3389 free_netdev(dev0);
3390
3391 iounmap(hw->regs);
3392 kfree(hw);
3393 pci_set_drvdata(pdev, NULL);
3394 }
3395
3396 #ifdef CONFIG_PM
3397 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3398 {
3399 struct skge_hw *hw = pci_get_drvdata(pdev);
3400 int i, wol = 0;
3401
3402 for (i = 0; i < 2; i++) {
3403 struct net_device *dev = hw->dev[i];
3404
3405 if (dev) {
3406 struct skge_port *skge = netdev_priv(dev);
3407 if (netif_running(dev)) {
3408 netif_carrier_off(dev);
3409 if (skge->wol)
3410 netif_stop_queue(dev);
3411 else
3412 skge_down(dev);
3413 }
3414 netif_device_detach(dev);
3415 wol |= skge->wol;
3416 }
3417 }
3418
3419 pci_save_state(pdev);
3420 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3421 pci_disable_device(pdev);
3422 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3423
3424 return 0;
3425 }
3426
3427 static int skge_resume(struct pci_dev *pdev)
3428 {
3429 struct skge_hw *hw = pci_get_drvdata(pdev);
3430 int i;
3431
3432 pci_set_power_state(pdev, PCI_D0);
3433 pci_restore_state(pdev);
3434 pci_enable_wake(pdev, PCI_D0, 0);
3435
3436 skge_reset(hw);
3437
3438 for (i = 0; i < 2; i++) {
3439 struct net_device *dev = hw->dev[i];
3440 if (dev) {
3441 netif_device_attach(dev);
3442 if (netif_running(dev) && skge_up(dev))
3443 dev_close(dev);
3444 }
3445 }
3446 return 0;
3447 }
3448 #endif
3449
3450 static struct pci_driver skge_driver = {
3451 .name = DRV_NAME,
3452 .id_table = skge_id_table,
3453 .probe = skge_probe,
3454 .remove = __devexit_p(skge_remove),
3455 #ifdef CONFIG_PM
3456 .suspend = skge_suspend,
3457 .resume = skge_resume,
3458 #endif
3459 };
3460
3461 static int __init skge_init_module(void)
3462 {
3463 return pci_module_init(&skge_driver);
3464 }
3465
3466 static void __exit skge_cleanup_module(void)
3467 {
3468 pci_unregister_driver(&skge_driver);
3469 }
3470
3471 module_init(skge_init_module);
3472 module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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