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Merge branch 'master'
[deliverable/linux.git] / drivers / net / skge.c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.1"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define RX_COPY_THRESHOLD 128
53 #define RX_BUF_SIZE 1536
54 #define PHY_RETRIES 1000
55 #define ETH_JUMBO_MTU 9000
56 #define TX_WATCHDOG (5 * HZ)
57 #define NAPI_WEIGHT 64
58 #define BLINK_MS 250
59
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
64
65 static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
83 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
84 { 0 }
85 };
86 MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88 static int skge_up(struct net_device *dev);
89 static int skge_down(struct net_device *dev);
90 static void skge_tx_clean(struct skge_port *skge);
91 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static void genesis_get_stats(struct skge_port *skge, u64 *data);
94 static void yukon_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_init(struct skge_hw *hw, int port);
96 static void yukon_reset(struct skge_hw *hw, int port);
97 static void genesis_mac_init(struct skge_hw *hw, int port);
98 static void genesis_reset(struct skge_hw *hw, int port);
99 static void genesis_link_up(struct skge_port *skge);
100
101 /* Avoid conditionals by using array */
102 static const int txqaddr[] = { Q_XA1, Q_XA2 };
103 static const int rxqaddr[] = { Q_R1, Q_R2 };
104 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
106 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
107
108 static int skge_get_regs_len(struct net_device *dev)
109 {
110 return 0x4000;
111 }
112
113 /*
114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
116 * cause bus hangs!
117 */
118 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
119 void *p)
120 {
121 const struct skge_port *skge = netdev_priv(dev);
122 const void __iomem *io = skge->hw->regs;
123
124 regs->version = 1;
125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
127
128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
130 }
131
132 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
133 static int wol_supported(const struct skge_hw *hw)
134 {
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
137 }
138
139 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
140 {
141 struct skge_port *skge = netdev_priv(dev);
142
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
145 }
146
147 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
148 {
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
151
152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
153 return -EOPNOTSUPP;
154
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
156 return -EOPNOTSUPP;
157
158 skge->wol = wol->wolopts == WAKE_MAGIC;
159
160 if (skge->wol) {
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
162
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
166 } else
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
168
169 return 0;
170 }
171
172 /* Determine supported/adverised modes based on hardware.
173 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
174 */
175 static u32 skge_supported_modes(const struct skge_hw *hw)
176 {
177 u32 supported;
178
179 if (hw->copper) {
180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
187
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
193
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
196 } else
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
198 | SUPPORTED_Autoneg;
199
200 return supported;
201 }
202
203 static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
205 {
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
208
209 ecmd->transceiver = XCVR_INTERNAL;
210 ecmd->supported = skge_supported_modes(hw);
211
212 if (hw->copper) {
213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
215 } else
216 ecmd->port = PORT_FIBRE;
217
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
222 return 0;
223 }
224
225 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
226 {
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
229 u32 supported = skge_supported_modes(hw);
230
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
232 ecmd->advertising = supported;
233 skge->duplex = -1;
234 skge->speed = -1;
235 } else {
236 u32 setting;
237
238 switch (ecmd->speed) {
239 case SPEED_1000:
240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
244 else
245 return -EINVAL;
246 break;
247 case SPEED_100:
248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
252 else
253 return -EINVAL;
254 break;
255
256 case SPEED_10:
257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
261 else
262 return -EINVAL;
263 break;
264 default:
265 return -EINVAL;
266 }
267
268 if ((setting & supported) == 0)
269 return -EINVAL;
270
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
273 }
274
275 skge->autoneg = ecmd->autoneg;
276 skge->advertising = ecmd->advertising;
277
278 if (netif_running(dev)) {
279 skge_down(dev);
280 skge_up(dev);
281 }
282 return (0);
283 }
284
285 static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287 {
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294 }
295
296 static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300 } skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325 };
326
327 static int skge_get_stats_count(struct net_device *dev)
328 {
329 return ARRAY_SIZE(skge_stats);
330 }
331
332 static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334 {
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341 }
342
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 {
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[5] + data[7];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366 }
367
368 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369 {
370 int i;
371
372 switch (stringset) {
373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379 }
380
381 static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383 {
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395 }
396
397 static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399 {
400 struct skge_port *skge = netdev_priv(dev);
401
402 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
403 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
404 return -EINVAL;
405
406 skge->rx_ring.count = p->rx_pending;
407 skge->tx_ring.count = p->tx_pending;
408
409 if (netif_running(dev)) {
410 skge_down(dev);
411 skge_up(dev);
412 }
413
414 return 0;
415 }
416
417 static u32 skge_get_msglevel(struct net_device *netdev)
418 {
419 struct skge_port *skge = netdev_priv(netdev);
420 return skge->msg_enable;
421 }
422
423 static void skge_set_msglevel(struct net_device *netdev, u32 value)
424 {
425 struct skge_port *skge = netdev_priv(netdev);
426 skge->msg_enable = value;
427 }
428
429 static int skge_nway_reset(struct net_device *dev)
430 {
431 struct skge_port *skge = netdev_priv(dev);
432 struct skge_hw *hw = skge->hw;
433 int port = skge->port;
434
435 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
436 return -EINVAL;
437
438 spin_lock_bh(&hw->phy_lock);
439 if (hw->chip_id == CHIP_ID_GENESIS) {
440 genesis_reset(hw, port);
441 genesis_mac_init(hw, port);
442 } else {
443 yukon_reset(hw, port);
444 yukon_init(hw, port);
445 }
446 spin_unlock_bh(&hw->phy_lock);
447 return 0;
448 }
449
450 static int skge_set_sg(struct net_device *dev, u32 data)
451 {
452 struct skge_port *skge = netdev_priv(dev);
453 struct skge_hw *hw = skge->hw;
454
455 if (hw->chip_id == CHIP_ID_GENESIS && data)
456 return -EOPNOTSUPP;
457 return ethtool_op_set_sg(dev, data);
458 }
459
460 static int skge_set_tx_csum(struct net_device *dev, u32 data)
461 {
462 struct skge_port *skge = netdev_priv(dev);
463 struct skge_hw *hw = skge->hw;
464
465 if (hw->chip_id == CHIP_ID_GENESIS && data)
466 return -EOPNOTSUPP;
467
468 return ethtool_op_set_tx_csum(dev, data);
469 }
470
471 static u32 skge_get_rx_csum(struct net_device *dev)
472 {
473 struct skge_port *skge = netdev_priv(dev);
474
475 return skge->rx_csum;
476 }
477
478 /* Only Yukon supports checksum offload. */
479 static int skge_set_rx_csum(struct net_device *dev, u32 data)
480 {
481 struct skge_port *skge = netdev_priv(dev);
482
483 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
484 return -EOPNOTSUPP;
485
486 skge->rx_csum = data;
487 return 0;
488 }
489
490 static void skge_get_pauseparam(struct net_device *dev,
491 struct ethtool_pauseparam *ecmd)
492 {
493 struct skge_port *skge = netdev_priv(dev);
494
495 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
496 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
497 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
498 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
499
500 ecmd->autoneg = skge->autoneg;
501 }
502
503 static int skge_set_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505 {
506 struct skge_port *skge = netdev_priv(dev);
507
508 skge->autoneg = ecmd->autoneg;
509 if (ecmd->rx_pause && ecmd->tx_pause)
510 skge->flow_control = FLOW_MODE_SYMMETRIC;
511 else if (ecmd->rx_pause && !ecmd->tx_pause)
512 skge->flow_control = FLOW_MODE_REM_SEND;
513 else if (!ecmd->rx_pause && ecmd->tx_pause)
514 skge->flow_control = FLOW_MODE_LOC_SEND;
515 else
516 skge->flow_control = FLOW_MODE_NONE;
517
518 if (netif_running(dev)) {
519 skge_down(dev);
520 skge_up(dev);
521 }
522 return 0;
523 }
524
525 /* Chip internal frequency for clock calculations */
526 static inline u32 hwkhz(const struct skge_hw *hw)
527 {
528 if (hw->chip_id == CHIP_ID_GENESIS)
529 return 53215; /* or: 53.125 MHz */
530 else
531 return 78215; /* or: 78.125 MHz */
532 }
533
534 /* Chip hz to microseconds */
535 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
536 {
537 return (ticks * 1000) / hwkhz(hw);
538 }
539
540 /* Microseconds to chip hz */
541 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
542 {
543 return hwkhz(hw) * usec / 1000;
544 }
545
546 static int skge_get_coalesce(struct net_device *dev,
547 struct ethtool_coalesce *ecmd)
548 {
549 struct skge_port *skge = netdev_priv(dev);
550 struct skge_hw *hw = skge->hw;
551 int port = skge->port;
552
553 ecmd->rx_coalesce_usecs = 0;
554 ecmd->tx_coalesce_usecs = 0;
555
556 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
557 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
558 u32 msk = skge_read32(hw, B2_IRQM_MSK);
559
560 if (msk & rxirqmask[port])
561 ecmd->rx_coalesce_usecs = delay;
562 if (msk & txirqmask[port])
563 ecmd->tx_coalesce_usecs = delay;
564 }
565
566 return 0;
567 }
568
569 /* Note: interrupt timer is per board, but can turn on/off per port */
570 static int skge_set_coalesce(struct net_device *dev,
571 struct ethtool_coalesce *ecmd)
572 {
573 struct skge_port *skge = netdev_priv(dev);
574 struct skge_hw *hw = skge->hw;
575 int port = skge->port;
576 u32 msk = skge_read32(hw, B2_IRQM_MSK);
577 u32 delay = 25;
578
579 if (ecmd->rx_coalesce_usecs == 0)
580 msk &= ~rxirqmask[port];
581 else if (ecmd->rx_coalesce_usecs < 25 ||
582 ecmd->rx_coalesce_usecs > 33333)
583 return -EINVAL;
584 else {
585 msk |= rxirqmask[port];
586 delay = ecmd->rx_coalesce_usecs;
587 }
588
589 if (ecmd->tx_coalesce_usecs == 0)
590 msk &= ~txirqmask[port];
591 else if (ecmd->tx_coalesce_usecs < 25 ||
592 ecmd->tx_coalesce_usecs > 33333)
593 return -EINVAL;
594 else {
595 msk |= txirqmask[port];
596 delay = min(delay, ecmd->rx_coalesce_usecs);
597 }
598
599 skge_write32(hw, B2_IRQM_MSK, msk);
600 if (msk == 0)
601 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
602 else {
603 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
604 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
605 }
606 return 0;
607 }
608
609 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
610 static void skge_led(struct skge_port *skge, enum led_mode mode)
611 {
612 struct skge_hw *hw = skge->hw;
613 int port = skge->port;
614
615 spin_lock_bh(&hw->phy_lock);
616 if (hw->chip_id == CHIP_ID_GENESIS) {
617 switch (mode) {
618 case LED_MODE_OFF:
619 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
620 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
621 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
622 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
623 break;
624
625 case LED_MODE_ON:
626 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
627 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
628
629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
630 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
631
632 break;
633
634 case LED_MODE_TST:
635 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
636 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
637 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
638
639 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
640 break;
641 }
642 } else {
643 switch (mode) {
644 case LED_MODE_OFF:
645 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
646 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
647 PHY_M_LED_MO_DUP(MO_LED_OFF) |
648 PHY_M_LED_MO_10(MO_LED_OFF) |
649 PHY_M_LED_MO_100(MO_LED_OFF) |
650 PHY_M_LED_MO_1000(MO_LED_OFF) |
651 PHY_M_LED_MO_RX(MO_LED_OFF));
652 break;
653 case LED_MODE_ON:
654 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
655 PHY_M_LED_PULS_DUR(PULS_170MS) |
656 PHY_M_LED_BLINK_RT(BLINK_84MS) |
657 PHY_M_LEDC_TX_CTRL |
658 PHY_M_LEDC_DP_CTRL);
659
660 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
661 PHY_M_LED_MO_RX(MO_LED_OFF) |
662 (skge->speed == SPEED_100 ?
663 PHY_M_LED_MO_100(MO_LED_ON) : 0));
664 break;
665 case LED_MODE_TST:
666 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
667 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
668 PHY_M_LED_MO_DUP(MO_LED_ON) |
669 PHY_M_LED_MO_10(MO_LED_ON) |
670 PHY_M_LED_MO_100(MO_LED_ON) |
671 PHY_M_LED_MO_1000(MO_LED_ON) |
672 PHY_M_LED_MO_RX(MO_LED_ON));
673 }
674 }
675 spin_unlock_bh(&hw->phy_lock);
676 }
677
678 /* blink LED's for finding board */
679 static int skge_phys_id(struct net_device *dev, u32 data)
680 {
681 struct skge_port *skge = netdev_priv(dev);
682 unsigned long ms;
683 enum led_mode mode = LED_MODE_TST;
684
685 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
686 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
687 else
688 ms = data * 1000;
689
690 while (ms > 0) {
691 skge_led(skge, mode);
692 mode ^= LED_MODE_TST;
693
694 if (msleep_interruptible(BLINK_MS))
695 break;
696 ms -= BLINK_MS;
697 }
698
699 /* back to regular LED state */
700 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
701
702 return 0;
703 }
704
705 static struct ethtool_ops skge_ethtool_ops = {
706 .get_settings = skge_get_settings,
707 .set_settings = skge_set_settings,
708 .get_drvinfo = skge_get_drvinfo,
709 .get_regs_len = skge_get_regs_len,
710 .get_regs = skge_get_regs,
711 .get_wol = skge_get_wol,
712 .set_wol = skge_set_wol,
713 .get_msglevel = skge_get_msglevel,
714 .set_msglevel = skge_set_msglevel,
715 .nway_reset = skge_nway_reset,
716 .get_link = ethtool_op_get_link,
717 .get_ringparam = skge_get_ring_param,
718 .set_ringparam = skge_set_ring_param,
719 .get_pauseparam = skge_get_pauseparam,
720 .set_pauseparam = skge_set_pauseparam,
721 .get_coalesce = skge_get_coalesce,
722 .set_coalesce = skge_set_coalesce,
723 .get_sg = ethtool_op_get_sg,
724 .set_sg = skge_set_sg,
725 .get_tx_csum = ethtool_op_get_tx_csum,
726 .set_tx_csum = skge_set_tx_csum,
727 .get_rx_csum = skge_get_rx_csum,
728 .set_rx_csum = skge_set_rx_csum,
729 .get_strings = skge_get_strings,
730 .phys_id = skge_phys_id,
731 .get_stats_count = skge_get_stats_count,
732 .get_ethtool_stats = skge_get_ethtool_stats,
733 .get_perm_addr = ethtool_op_get_perm_addr,
734 };
735
736 /*
737 * Allocate ring elements and chain them together
738 * One-to-one association of board descriptors with ring elements
739 */
740 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
741 {
742 struct skge_tx_desc *d;
743 struct skge_element *e;
744 int i;
745
746 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
747 if (!ring->start)
748 return -ENOMEM;
749
750 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
751 e->desc = d;
752 e->skb = NULL;
753 if (i == ring->count - 1) {
754 e->next = ring->start;
755 d->next_offset = base;
756 } else {
757 e->next = e + 1;
758 d->next_offset = base + (i+1) * sizeof(*d);
759 }
760 }
761 ring->to_use = ring->to_clean = ring->start;
762
763 return 0;
764 }
765
766 /* Allocate and setup a new buffer for receiving */
767 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
768 struct sk_buff *skb, unsigned int bufsize)
769 {
770 struct skge_rx_desc *rd = e->desc;
771 u64 map;
772
773 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
774 PCI_DMA_FROMDEVICE);
775
776 rd->dma_lo = map;
777 rd->dma_hi = map >> 32;
778 e->skb = skb;
779 rd->csum1_start = ETH_HLEN;
780 rd->csum2_start = ETH_HLEN;
781 rd->csum1 = 0;
782 rd->csum2 = 0;
783
784 wmb();
785
786 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
787 pci_unmap_addr_set(e, mapaddr, map);
788 pci_unmap_len_set(e, maplen, bufsize);
789 }
790
791 /* Resume receiving using existing skb,
792 * Note: DMA address is not changed by chip.
793 * MTU not changed while receiver active.
794 */
795 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
796 {
797 struct skge_rx_desc *rd = e->desc;
798
799 rd->csum2 = 0;
800 rd->csum2_start = ETH_HLEN;
801
802 wmb();
803
804 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
805 }
806
807
808 /* Free all buffers in receive ring, assumes receiver stopped */
809 static void skge_rx_clean(struct skge_port *skge)
810 {
811 struct skge_hw *hw = skge->hw;
812 struct skge_ring *ring = &skge->rx_ring;
813 struct skge_element *e;
814
815 e = ring->start;
816 do {
817 struct skge_rx_desc *rd = e->desc;
818 rd->control = 0;
819 if (e->skb) {
820 pci_unmap_single(hw->pdev,
821 pci_unmap_addr(e, mapaddr),
822 pci_unmap_len(e, maplen),
823 PCI_DMA_FROMDEVICE);
824 dev_kfree_skb(e->skb);
825 e->skb = NULL;
826 }
827 } while ((e = e->next) != ring->start);
828 }
829
830
831 /* Allocate buffers for receive ring
832 * For receive: to_clean is next received frame.
833 */
834 static int skge_rx_fill(struct skge_port *skge)
835 {
836 struct skge_ring *ring = &skge->rx_ring;
837 struct skge_element *e;
838
839 e = ring->start;
840 do {
841 struct sk_buff *skb;
842
843 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
844 if (!skb)
845 return -ENOMEM;
846
847 skb_reserve(skb, NET_IP_ALIGN);
848 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
849 } while ( (e = e->next) != ring->start);
850
851 ring->to_clean = ring->start;
852 return 0;
853 }
854
855 static void skge_link_up(struct skge_port *skge)
856 {
857 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
858 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
859
860 netif_carrier_on(skge->netdev);
861 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
862 netif_wake_queue(skge->netdev);
863
864 if (netif_msg_link(skge))
865 printk(KERN_INFO PFX
866 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
867 skge->netdev->name, skge->speed,
868 skge->duplex == DUPLEX_FULL ? "full" : "half",
869 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
870 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
871 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
872 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
873 "unknown");
874 }
875
876 static void skge_link_down(struct skge_port *skge)
877 {
878 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
879 netif_carrier_off(skge->netdev);
880 netif_stop_queue(skge->netdev);
881
882 if (netif_msg_link(skge))
883 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
884 }
885
886 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
887 {
888 int i;
889 u16 v;
890
891 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
892 v = xm_read16(hw, port, XM_PHY_DATA);
893
894 /* Need to wait for external PHY */
895 for (i = 0; i < PHY_RETRIES; i++) {
896 udelay(1);
897 if (xm_read16(hw, port, XM_MMU_CMD)
898 & XM_MMU_PHY_RDY)
899 goto ready;
900 }
901
902 printk(KERN_WARNING PFX "%s: phy read timed out\n",
903 hw->dev[port]->name);
904 return 0;
905 ready:
906 v = xm_read16(hw, port, XM_PHY_DATA);
907
908 return v;
909 }
910
911 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
912 {
913 int i;
914
915 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
916 for (i = 0; i < PHY_RETRIES; i++) {
917 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
918 goto ready;
919 udelay(1);
920 }
921 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
922 hw->dev[port]->name);
923
924
925 ready:
926 xm_write16(hw, port, XM_PHY_DATA, val);
927 for (i = 0; i < PHY_RETRIES; i++) {
928 udelay(1);
929 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
930 return;
931 }
932 printk(KERN_WARNING PFX "%s: phy write timed out\n",
933 hw->dev[port]->name);
934 }
935
936 static void genesis_init(struct skge_hw *hw)
937 {
938 /* set blink source counter */
939 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
940 skge_write8(hw, B2_BSC_CTRL, BSC_START);
941
942 /* configure mac arbiter */
943 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
944
945 /* configure mac arbiter timeout values */
946 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
947 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
948 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
949 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
950
951 skge_write8(hw, B3_MA_RCINI_RX1, 0);
952 skge_write8(hw, B3_MA_RCINI_RX2, 0);
953 skge_write8(hw, B3_MA_RCINI_TX1, 0);
954 skge_write8(hw, B3_MA_RCINI_TX2, 0);
955
956 /* configure packet arbiter timeout */
957 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
958 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
959 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
960 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
961 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
962 }
963
964 static void genesis_reset(struct skge_hw *hw, int port)
965 {
966 const u8 zero[8] = { 0 };
967
968 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
969
970 /* reset the statistics module */
971 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
972 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
973 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
974 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
975 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
976
977 /* disable Broadcom PHY IRQ */
978 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
979
980 xm_outhash(hw, port, XM_HSM, zero);
981 }
982
983
984 /* Convert mode to MII values */
985 static const u16 phy_pause_map[] = {
986 [FLOW_MODE_NONE] = 0,
987 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
988 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
989 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
990 };
991
992
993 /* Check status of Broadcom phy link */
994 static void bcom_check_link(struct skge_hw *hw, int port)
995 {
996 struct net_device *dev = hw->dev[port];
997 struct skge_port *skge = netdev_priv(dev);
998 u16 status;
999
1000 /* read twice because of latch */
1001 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1002 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1003
1004 if ((status & PHY_ST_LSYNC) == 0) {
1005 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1006 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1007 xm_write16(hw, port, XM_MMU_CMD, cmd);
1008 /* dummy read to ensure writing */
1009 (void) xm_read16(hw, port, XM_MMU_CMD);
1010
1011 if (netif_carrier_ok(dev))
1012 skge_link_down(skge);
1013 } else {
1014 if (skge->autoneg == AUTONEG_ENABLE &&
1015 (status & PHY_ST_AN_OVER)) {
1016 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1017 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1018
1019 if (lpa & PHY_B_AN_RF) {
1020 printk(KERN_NOTICE PFX "%s: remote fault\n",
1021 dev->name);
1022 return;
1023 }
1024
1025 /* Check Duplex mismatch */
1026 switch (aux & PHY_B_AS_AN_RES_MSK) {
1027 case PHY_B_RES_1000FD:
1028 skge->duplex = DUPLEX_FULL;
1029 break;
1030 case PHY_B_RES_1000HD:
1031 skge->duplex = DUPLEX_HALF;
1032 break;
1033 default:
1034 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1035 dev->name);
1036 return;
1037 }
1038
1039
1040 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1041 switch (aux & PHY_B_AS_PAUSE_MSK) {
1042 case PHY_B_AS_PAUSE_MSK:
1043 skge->flow_control = FLOW_MODE_SYMMETRIC;
1044 break;
1045 case PHY_B_AS_PRR:
1046 skge->flow_control = FLOW_MODE_REM_SEND;
1047 break;
1048 case PHY_B_AS_PRT:
1049 skge->flow_control = FLOW_MODE_LOC_SEND;
1050 break;
1051 default:
1052 skge->flow_control = FLOW_MODE_NONE;
1053 }
1054
1055 skge->speed = SPEED_1000;
1056 }
1057
1058 if (!netif_carrier_ok(dev))
1059 genesis_link_up(skge);
1060 }
1061 }
1062
1063 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1064 * Phy on for 100 or 10Mbit operation
1065 */
1066 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1067 {
1068 struct skge_hw *hw = skge->hw;
1069 int port = skge->port;
1070 int i;
1071 u16 id1, r, ext, ctl;
1072
1073 /* magic workaround patterns for Broadcom */
1074 static const struct {
1075 u16 reg;
1076 u16 val;
1077 } A1hack[] = {
1078 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1079 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1080 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1081 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1082 }, C0hack[] = {
1083 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1084 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1085 };
1086
1087 /* read Id from external PHY (all have the same address) */
1088 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1089
1090 /* Optimize MDIO transfer by suppressing preamble. */
1091 r = xm_read16(hw, port, XM_MMU_CMD);
1092 r |= XM_MMU_NO_PRE;
1093 xm_write16(hw, port, XM_MMU_CMD,r);
1094
1095 switch (id1) {
1096 case PHY_BCOM_ID1_C0:
1097 /*
1098 * Workaround BCOM Errata for the C0 type.
1099 * Write magic patterns to reserved registers.
1100 */
1101 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1102 xm_phy_write(hw, port,
1103 C0hack[i].reg, C0hack[i].val);
1104
1105 break;
1106 case PHY_BCOM_ID1_A1:
1107 /*
1108 * Workaround BCOM Errata for the A1 type.
1109 * Write magic patterns to reserved registers.
1110 */
1111 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1112 xm_phy_write(hw, port,
1113 A1hack[i].reg, A1hack[i].val);
1114 break;
1115 }
1116
1117 /*
1118 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1119 * Disable Power Management after reset.
1120 */
1121 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1122 r |= PHY_B_AC_DIS_PM;
1123 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1124
1125 /* Dummy read */
1126 xm_read16(hw, port, XM_ISRC);
1127
1128 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1129 ctl = PHY_CT_SP1000; /* always 1000mbit */
1130
1131 if (skge->autoneg == AUTONEG_ENABLE) {
1132 /*
1133 * Workaround BCOM Errata #1 for the C5 type.
1134 * 1000Base-T Link Acquisition Failure in Slave Mode
1135 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1136 */
1137 u16 adv = PHY_B_1000C_RD;
1138 if (skge->advertising & ADVERTISED_1000baseT_Half)
1139 adv |= PHY_B_1000C_AHD;
1140 if (skge->advertising & ADVERTISED_1000baseT_Full)
1141 adv |= PHY_B_1000C_AFD;
1142 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1143
1144 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1145 } else {
1146 if (skge->duplex == DUPLEX_FULL)
1147 ctl |= PHY_CT_DUP_MD;
1148 /* Force to slave */
1149 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1150 }
1151
1152 /* Set autonegotiation pause parameters */
1153 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1154 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1155
1156 /* Handle Jumbo frames */
1157 if (jumbo) {
1158 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1159 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1160
1161 ext |= PHY_B_PEC_HIGH_LA;
1162
1163 }
1164
1165 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1166 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1167
1168 /* Use link status change interrrupt */
1169 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1170
1171 bcom_check_link(hw, port);
1172 }
1173
1174 static void genesis_mac_init(struct skge_hw *hw, int port)
1175 {
1176 struct net_device *dev = hw->dev[port];
1177 struct skge_port *skge = netdev_priv(dev);
1178 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1179 int i;
1180 u32 r;
1181 const u8 zero[6] = { 0 };
1182
1183 /* Clear MIB counters */
1184 xm_write16(hw, port, XM_STAT_CMD,
1185 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1186 /* Clear two times according to Errata #3 */
1187 xm_write16(hw, port, XM_STAT_CMD,
1188 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1189
1190 /* Unreset the XMAC. */
1191 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1192
1193 /*
1194 * Perform additional initialization for external PHYs,
1195 * namely for the 1000baseTX cards that use the XMAC's
1196 * GMII mode.
1197 */
1198 /* Take external Phy out of reset */
1199 r = skge_read32(hw, B2_GP_IO);
1200 if (port == 0)
1201 r |= GP_DIR_0|GP_IO_0;
1202 else
1203 r |= GP_DIR_2|GP_IO_2;
1204
1205 skge_write32(hw, B2_GP_IO, r);
1206 skge_read32(hw, B2_GP_IO);
1207
1208 /* Enable GMII interfac */
1209 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1210
1211 bcom_phy_init(skge, jumbo);
1212
1213 /* Set Station Address */
1214 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1215
1216 /* We don't use match addresses so clear */
1217 for (i = 1; i < 16; i++)
1218 xm_outaddr(hw, port, XM_EXM(i), zero);
1219
1220 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1221 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1222
1223 /* We don't need the FCS appended to the packet. */
1224 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1225 if (jumbo)
1226 r |= XM_RX_BIG_PK_OK;
1227
1228 if (skge->duplex == DUPLEX_HALF) {
1229 /*
1230 * If in manual half duplex mode the other side might be in
1231 * full duplex mode, so ignore if a carrier extension is not seen
1232 * on frames received
1233 */
1234 r |= XM_RX_DIS_CEXT;
1235 }
1236 xm_write16(hw, port, XM_RX_CMD, r);
1237
1238
1239 /* We want short frames padded to 60 bytes. */
1240 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1241
1242 /*
1243 * Bump up the transmit threshold. This helps hold off transmit
1244 * underruns when we're blasting traffic from both ports at once.
1245 */
1246 xm_write16(hw, port, XM_TX_THR, 512);
1247
1248 /*
1249 * Enable the reception of all error frames. This is is
1250 * a necessary evil due to the design of the XMAC. The
1251 * XMAC's receive FIFO is only 8K in size, however jumbo
1252 * frames can be up to 9000 bytes in length. When bad
1253 * frame filtering is enabled, the XMAC's RX FIFO operates
1254 * in 'store and forward' mode. For this to work, the
1255 * entire frame has to fit into the FIFO, but that means
1256 * that jumbo frames larger than 8192 bytes will be
1257 * truncated. Disabling all bad frame filtering causes
1258 * the RX FIFO to operate in streaming mode, in which
1259 * case the XMAC will start transfering frames out of the
1260 * RX FIFO as soon as the FIFO threshold is reached.
1261 */
1262 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1263
1264
1265 /*
1266 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1267 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1268 * and 'Octets Rx OK Hi Cnt Ov'.
1269 */
1270 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1271
1272 /*
1273 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1274 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1275 * and 'Octets Tx OK Hi Cnt Ov'.
1276 */
1277 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1278
1279 /* Configure MAC arbiter */
1280 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1281
1282 /* configure timeout values */
1283 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1284 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1285 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1286 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1287
1288 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1289 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1290 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1291 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1292
1293 /* Configure Rx MAC FIFO */
1294 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1295 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1296 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1297
1298 /* Configure Tx MAC FIFO */
1299 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1300 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1301 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1302
1303 if (jumbo) {
1304 /* Enable frame flushing if jumbo frames used */
1305 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1306 } else {
1307 /* enable timeout timers if normal frames */
1308 skge_write16(hw, B3_PA_CTRL,
1309 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1310 }
1311 }
1312
1313 static void genesis_stop(struct skge_port *skge)
1314 {
1315 struct skge_hw *hw = skge->hw;
1316 int port = skge->port;
1317 u32 reg;
1318
1319 genesis_reset(hw, port);
1320
1321 /* Clear Tx packet arbiter timeout IRQ */
1322 skge_write16(hw, B3_PA_CTRL,
1323 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1324
1325 /*
1326 * If the transfer stucks at the MAC the STOP command will not
1327 * terminate if we don't flush the XMAC's transmit FIFO !
1328 */
1329 xm_write32(hw, port, XM_MODE,
1330 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1331
1332
1333 /* Reset the MAC */
1334 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1335
1336 /* For external PHYs there must be special handling */
1337 reg = skge_read32(hw, B2_GP_IO);
1338 if (port == 0) {
1339 reg |= GP_DIR_0;
1340 reg &= ~GP_IO_0;
1341 } else {
1342 reg |= GP_DIR_2;
1343 reg &= ~GP_IO_2;
1344 }
1345 skge_write32(hw, B2_GP_IO, reg);
1346 skge_read32(hw, B2_GP_IO);
1347
1348 xm_write16(hw, port, XM_MMU_CMD,
1349 xm_read16(hw, port, XM_MMU_CMD)
1350 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1351
1352 xm_read16(hw, port, XM_MMU_CMD);
1353 }
1354
1355
1356 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1357 {
1358 struct skge_hw *hw = skge->hw;
1359 int port = skge->port;
1360 int i;
1361 unsigned long timeout = jiffies + HZ;
1362
1363 xm_write16(hw, port,
1364 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1365
1366 /* wait for update to complete */
1367 while (xm_read16(hw, port, XM_STAT_CMD)
1368 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1369 if (time_after(jiffies, timeout))
1370 break;
1371 udelay(10);
1372 }
1373
1374 /* special case for 64 bit octet counter */
1375 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1376 | xm_read32(hw, port, XM_TXO_OK_LO);
1377 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1378 | xm_read32(hw, port, XM_RXO_OK_LO);
1379
1380 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1381 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1382 }
1383
1384 static void genesis_mac_intr(struct skge_hw *hw, int port)
1385 {
1386 struct skge_port *skge = netdev_priv(hw->dev[port]);
1387 u16 status = xm_read16(hw, port, XM_ISRC);
1388
1389 if (netif_msg_intr(skge))
1390 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1391 skge->netdev->name, status);
1392
1393 if (status & XM_IS_TXF_UR) {
1394 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1395 ++skge->net_stats.tx_fifo_errors;
1396 }
1397 if (status & XM_IS_RXF_OV) {
1398 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1399 ++skge->net_stats.rx_fifo_errors;
1400 }
1401 }
1402
1403 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1404 {
1405 int i;
1406
1407 gma_write16(hw, port, GM_SMI_DATA, val);
1408 gma_write16(hw, port, GM_SMI_CTRL,
1409 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1410 for (i = 0; i < PHY_RETRIES; i++) {
1411 udelay(1);
1412
1413 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1414 break;
1415 }
1416 }
1417
1418 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1419 {
1420 int i;
1421
1422 gma_write16(hw, port, GM_SMI_CTRL,
1423 GM_SMI_CT_PHY_AD(hw->phy_addr)
1424 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1425
1426 for (i = 0; i < PHY_RETRIES; i++) {
1427 udelay(1);
1428 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1429 goto ready;
1430 }
1431
1432 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1433 hw->dev[port]->name);
1434 return 0;
1435 ready:
1436 return gma_read16(hw, port, GM_SMI_DATA);
1437 }
1438
1439 static void genesis_link_up(struct skge_port *skge)
1440 {
1441 struct skge_hw *hw = skge->hw;
1442 int port = skge->port;
1443 u16 cmd;
1444 u32 mode, msk;
1445
1446 cmd = xm_read16(hw, port, XM_MMU_CMD);
1447
1448 /*
1449 * enabling pause frame reception is required for 1000BT
1450 * because the XMAC is not reset if the link is going down
1451 */
1452 if (skge->flow_control == FLOW_MODE_NONE ||
1453 skge->flow_control == FLOW_MODE_LOC_SEND)
1454 /* Disable Pause Frame Reception */
1455 cmd |= XM_MMU_IGN_PF;
1456 else
1457 /* Enable Pause Frame Reception */
1458 cmd &= ~XM_MMU_IGN_PF;
1459
1460 xm_write16(hw, port, XM_MMU_CMD, cmd);
1461
1462 mode = xm_read32(hw, port, XM_MODE);
1463 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1464 skge->flow_control == FLOW_MODE_LOC_SEND) {
1465 /*
1466 * Configure Pause Frame Generation
1467 * Use internal and external Pause Frame Generation.
1468 * Sending pause frames is edge triggered.
1469 * Send a Pause frame with the maximum pause time if
1470 * internal oder external FIFO full condition occurs.
1471 * Send a zero pause time frame to re-start transmission.
1472 */
1473 /* XM_PAUSE_DA = '010000C28001' (default) */
1474 /* XM_MAC_PTIME = 0xffff (maximum) */
1475 /* remember this value is defined in big endian (!) */
1476 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1477
1478 mode |= XM_PAUSE_MODE;
1479 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1480 } else {
1481 /*
1482 * disable pause frame generation is required for 1000BT
1483 * because the XMAC is not reset if the link is going down
1484 */
1485 /* Disable Pause Mode in Mode Register */
1486 mode &= ~XM_PAUSE_MODE;
1487
1488 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1489 }
1490
1491 xm_write32(hw, port, XM_MODE, mode);
1492
1493 msk = XM_DEF_MSK;
1494 /* disable GP0 interrupt bit for external Phy */
1495 msk |= XM_IS_INP_ASS;
1496
1497 xm_write16(hw, port, XM_IMSK, msk);
1498 xm_read16(hw, port, XM_ISRC);
1499
1500 /* get MMU Command Reg. */
1501 cmd = xm_read16(hw, port, XM_MMU_CMD);
1502 if (skge->duplex == DUPLEX_FULL)
1503 cmd |= XM_MMU_GMII_FD;
1504
1505 /*
1506 * Workaround BCOM Errata (#10523) for all BCom Phys
1507 * Enable Power Management after link up
1508 */
1509 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1510 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1511 & ~PHY_B_AC_DIS_PM);
1512 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1513
1514 /* enable Rx/Tx */
1515 xm_write16(hw, port, XM_MMU_CMD,
1516 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1517 skge_link_up(skge);
1518 }
1519
1520
1521 static inline void bcom_phy_intr(struct skge_port *skge)
1522 {
1523 struct skge_hw *hw = skge->hw;
1524 int port = skge->port;
1525 u16 isrc;
1526
1527 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1528 if (netif_msg_intr(skge))
1529 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1530 skge->netdev->name, isrc);
1531
1532 if (isrc & PHY_B_IS_PSE)
1533 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1534 hw->dev[port]->name);
1535
1536 /* Workaround BCom Errata:
1537 * enable and disable loopback mode if "NO HCD" occurs.
1538 */
1539 if (isrc & PHY_B_IS_NO_HDCL) {
1540 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1541 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1542 ctrl | PHY_CT_LOOP);
1543 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1544 ctrl & ~PHY_CT_LOOP);
1545 }
1546
1547 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1548 bcom_check_link(hw, port);
1549
1550 }
1551
1552 /* Marvell Phy Initailization */
1553 static void yukon_init(struct skge_hw *hw, int port)
1554 {
1555 struct skge_port *skge = netdev_priv(hw->dev[port]);
1556 u16 ctrl, ct1000, adv;
1557
1558 if (skge->autoneg == AUTONEG_ENABLE) {
1559 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1560
1561 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1562 PHY_M_EC_MAC_S_MSK);
1563 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1564
1565 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1566
1567 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1568 }
1569
1570 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1571 if (skge->autoneg == AUTONEG_DISABLE)
1572 ctrl &= ~PHY_CT_ANE;
1573
1574 ctrl |= PHY_CT_RESET;
1575 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1576
1577 ctrl = 0;
1578 ct1000 = 0;
1579 adv = PHY_AN_CSMA;
1580
1581 if (skge->autoneg == AUTONEG_ENABLE) {
1582 if (hw->copper) {
1583 if (skge->advertising & ADVERTISED_1000baseT_Full)
1584 ct1000 |= PHY_M_1000C_AFD;
1585 if (skge->advertising & ADVERTISED_1000baseT_Half)
1586 ct1000 |= PHY_M_1000C_AHD;
1587 if (skge->advertising & ADVERTISED_100baseT_Full)
1588 adv |= PHY_M_AN_100_FD;
1589 if (skge->advertising & ADVERTISED_100baseT_Half)
1590 adv |= PHY_M_AN_100_HD;
1591 if (skge->advertising & ADVERTISED_10baseT_Full)
1592 adv |= PHY_M_AN_10_FD;
1593 if (skge->advertising & ADVERTISED_10baseT_Half)
1594 adv |= PHY_M_AN_10_HD;
1595 } else /* special defines for FIBER (88E1011S only) */
1596 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1597
1598 /* Set Flow-control capabilities */
1599 adv |= phy_pause_map[skge->flow_control];
1600
1601 /* Restart Auto-negotiation */
1602 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1603 } else {
1604 /* forced speed/duplex settings */
1605 ct1000 = PHY_M_1000C_MSE;
1606
1607 if (skge->duplex == DUPLEX_FULL)
1608 ctrl |= PHY_CT_DUP_MD;
1609
1610 switch (skge->speed) {
1611 case SPEED_1000:
1612 ctrl |= PHY_CT_SP1000;
1613 break;
1614 case SPEED_100:
1615 ctrl |= PHY_CT_SP100;
1616 break;
1617 }
1618
1619 ctrl |= PHY_CT_RESET;
1620 }
1621
1622 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1623
1624 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1625 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1626
1627 /* Enable phy interrupt on autonegotiation complete (or link up) */
1628 if (skge->autoneg == AUTONEG_ENABLE)
1629 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1630 else
1631 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1632 }
1633
1634 static void yukon_reset(struct skge_hw *hw, int port)
1635 {
1636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1637 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1638 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1639 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1640 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1641
1642 gma_write16(hw, port, GM_RX_CTRL,
1643 gma_read16(hw, port, GM_RX_CTRL)
1644 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1645 }
1646
1647 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1648 static int is_yukon_lite_a0(struct skge_hw *hw)
1649 {
1650 u32 reg;
1651 int ret;
1652
1653 if (hw->chip_id != CHIP_ID_YUKON)
1654 return 0;
1655
1656 reg = skge_read32(hw, B2_FAR);
1657 skge_write8(hw, B2_FAR + 3, 0xff);
1658 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1659 skge_write32(hw, B2_FAR, reg);
1660 return ret;
1661 }
1662
1663 static void yukon_mac_init(struct skge_hw *hw, int port)
1664 {
1665 struct skge_port *skge = netdev_priv(hw->dev[port]);
1666 int i;
1667 u32 reg;
1668 const u8 *addr = hw->dev[port]->dev_addr;
1669
1670 /* WA code for COMA mode -- set PHY reset */
1671 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1672 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1673 reg = skge_read32(hw, B2_GP_IO);
1674 reg |= GP_DIR_9 | GP_IO_9;
1675 skge_write32(hw, B2_GP_IO, reg);
1676 }
1677
1678 /* hard reset */
1679 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1680 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1681
1682 /* WA code for COMA mode -- clear PHY reset */
1683 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1684 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1685 reg = skge_read32(hw, B2_GP_IO);
1686 reg |= GP_DIR_9;
1687 reg &= ~GP_IO_9;
1688 skge_write32(hw, B2_GP_IO, reg);
1689 }
1690
1691 /* Set hardware config mode */
1692 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1693 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1694 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1695
1696 /* Clear GMC reset */
1697 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1698 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1699 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1700 if (skge->autoneg == AUTONEG_DISABLE) {
1701 reg = GM_GPCR_AU_ALL_DIS;
1702 gma_write16(hw, port, GM_GP_CTRL,
1703 gma_read16(hw, port, GM_GP_CTRL) | reg);
1704
1705 switch (skge->speed) {
1706 case SPEED_1000:
1707 reg |= GM_GPCR_SPEED_1000;
1708 /* fallthru */
1709 case SPEED_100:
1710 reg |= GM_GPCR_SPEED_100;
1711 }
1712
1713 if (skge->duplex == DUPLEX_FULL)
1714 reg |= GM_GPCR_DUP_FULL;
1715 } else
1716 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1717 switch (skge->flow_control) {
1718 case FLOW_MODE_NONE:
1719 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1720 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1721 break;
1722 case FLOW_MODE_LOC_SEND:
1723 /* disable Rx flow-control */
1724 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1725 }
1726
1727 gma_write16(hw, port, GM_GP_CTRL, reg);
1728 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1729
1730 yukon_init(hw, port);
1731
1732 /* MIB clear */
1733 reg = gma_read16(hw, port, GM_PHY_ADDR);
1734 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1735
1736 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1737 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1738 gma_write16(hw, port, GM_PHY_ADDR, reg);
1739
1740 /* transmit control */
1741 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1742
1743 /* receive control reg: unicast + multicast + no FCS */
1744 gma_write16(hw, port, GM_RX_CTRL,
1745 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1746
1747 /* transmit flow control */
1748 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1749
1750 /* transmit parameter */
1751 gma_write16(hw, port, GM_TX_PARAM,
1752 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1753 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1754 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1755
1756 /* serial mode register */
1757 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1758 if (hw->dev[port]->mtu > 1500)
1759 reg |= GM_SMOD_JUMBO_ENA;
1760
1761 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1762
1763 /* physical address: used for pause frames */
1764 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1765 /* virtual address for data */
1766 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1767
1768 /* enable interrupt mask for counter overflows */
1769 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1770 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1771 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1772
1773 /* Initialize Mac Fifo */
1774
1775 /* Configure Rx MAC FIFO */
1776 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1777 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1778
1779 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1780 if (is_yukon_lite_a0(hw))
1781 reg &= ~GMF_RX_F_FL_ON;
1782
1783 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1784 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1785 /*
1786 * because Pause Packet Truncation in GMAC is not working
1787 * we have to increase the Flush Threshold to 64 bytes
1788 * in order to flush pause packets in Rx FIFO on Yukon-1
1789 */
1790 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1791
1792 /* Configure Tx MAC FIFO */
1793 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1794 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1795 }
1796
1797 static void yukon_stop(struct skge_port *skge)
1798 {
1799 struct skge_hw *hw = skge->hw;
1800 int port = skge->port;
1801
1802 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1803 yukon_reset(hw, port);
1804
1805 gma_write16(hw, port, GM_GP_CTRL,
1806 gma_read16(hw, port, GM_GP_CTRL)
1807 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1808 gma_read16(hw, port, GM_GP_CTRL);
1809
1810 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1811 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1812 u32 io = skge_read32(hw, B2_GP_IO);
1813
1814 io |= GP_DIR_9 | GP_IO_9;
1815 skge_write32(hw, B2_GP_IO, io);
1816 skge_read32(hw, B2_GP_IO);
1817 }
1818
1819 /* set GPHY Control reset */
1820 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1821 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1822 }
1823
1824 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1825 {
1826 struct skge_hw *hw = skge->hw;
1827 int port = skge->port;
1828 int i;
1829
1830 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1831 | gma_read32(hw, port, GM_TXO_OK_LO);
1832 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1833 | gma_read32(hw, port, GM_RXO_OK_LO);
1834
1835 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1836 data[i] = gma_read32(hw, port,
1837 skge_stats[i].gma_offset);
1838 }
1839
1840 static void yukon_mac_intr(struct skge_hw *hw, int port)
1841 {
1842 struct net_device *dev = hw->dev[port];
1843 struct skge_port *skge = netdev_priv(dev);
1844 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1845
1846 if (netif_msg_intr(skge))
1847 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1848 dev->name, status);
1849
1850 if (status & GM_IS_RX_FF_OR) {
1851 ++skge->net_stats.rx_fifo_errors;
1852 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1853 }
1854
1855 if (status & GM_IS_TX_FF_UR) {
1856 ++skge->net_stats.tx_fifo_errors;
1857 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1858 }
1859
1860 }
1861
1862 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1863 {
1864 switch (aux & PHY_M_PS_SPEED_MSK) {
1865 case PHY_M_PS_SPEED_1000:
1866 return SPEED_1000;
1867 case PHY_M_PS_SPEED_100:
1868 return SPEED_100;
1869 default:
1870 return SPEED_10;
1871 }
1872 }
1873
1874 static void yukon_link_up(struct skge_port *skge)
1875 {
1876 struct skge_hw *hw = skge->hw;
1877 int port = skge->port;
1878 u16 reg;
1879
1880 /* Enable Transmit FIFO Underrun */
1881 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1882
1883 reg = gma_read16(hw, port, GM_GP_CTRL);
1884 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1885 reg |= GM_GPCR_DUP_FULL;
1886
1887 /* enable Rx/Tx */
1888 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1889 gma_write16(hw, port, GM_GP_CTRL, reg);
1890
1891 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1892 skge_link_up(skge);
1893 }
1894
1895 static void yukon_link_down(struct skge_port *skge)
1896 {
1897 struct skge_hw *hw = skge->hw;
1898 int port = skge->port;
1899 u16 ctrl;
1900
1901 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1902
1903 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1904 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1905 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1906
1907 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1908 /* restore Asymmetric Pause bit */
1909 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1910 gm_phy_read(hw, port,
1911 PHY_MARV_AUNE_ADV)
1912 | PHY_M_AN_ASP);
1913
1914 }
1915
1916 yukon_reset(hw, port);
1917 skge_link_down(skge);
1918
1919 yukon_init(hw, port);
1920 }
1921
1922 static void yukon_phy_intr(struct skge_port *skge)
1923 {
1924 struct skge_hw *hw = skge->hw;
1925 int port = skge->port;
1926 const char *reason = NULL;
1927 u16 istatus, phystat;
1928
1929 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1930 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1931
1932 if (netif_msg_intr(skge))
1933 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1934 skge->netdev->name, istatus, phystat);
1935
1936 if (istatus & PHY_M_IS_AN_COMPL) {
1937 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1938 & PHY_M_AN_RF) {
1939 reason = "remote fault";
1940 goto failed;
1941 }
1942
1943 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1944 reason = "master/slave fault";
1945 goto failed;
1946 }
1947
1948 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1949 reason = "speed/duplex";
1950 goto failed;
1951 }
1952
1953 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1954 ? DUPLEX_FULL : DUPLEX_HALF;
1955 skge->speed = yukon_speed(hw, phystat);
1956
1957 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1958 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1959 case PHY_M_PS_PAUSE_MSK:
1960 skge->flow_control = FLOW_MODE_SYMMETRIC;
1961 break;
1962 case PHY_M_PS_RX_P_EN:
1963 skge->flow_control = FLOW_MODE_REM_SEND;
1964 break;
1965 case PHY_M_PS_TX_P_EN:
1966 skge->flow_control = FLOW_MODE_LOC_SEND;
1967 break;
1968 default:
1969 skge->flow_control = FLOW_MODE_NONE;
1970 }
1971
1972 if (skge->flow_control == FLOW_MODE_NONE ||
1973 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1974 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1975 else
1976 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1977 yukon_link_up(skge);
1978 return;
1979 }
1980
1981 if (istatus & PHY_M_IS_LSP_CHANGE)
1982 skge->speed = yukon_speed(hw, phystat);
1983
1984 if (istatus & PHY_M_IS_DUP_CHANGE)
1985 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1986 if (istatus & PHY_M_IS_LST_CHANGE) {
1987 if (phystat & PHY_M_PS_LINK_UP)
1988 yukon_link_up(skge);
1989 else
1990 yukon_link_down(skge);
1991 }
1992 return;
1993 failed:
1994 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1995 skge->netdev->name, reason);
1996
1997 /* XXX restart autonegotiation? */
1998 }
1999
2000 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2001 {
2002 u32 end;
2003
2004 start /= 8;
2005 len /= 8;
2006 end = start + len - 1;
2007
2008 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2009 skge_write32(hw, RB_ADDR(q, RB_START), start);
2010 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2011 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2012 skge_write32(hw, RB_ADDR(q, RB_END), end);
2013
2014 if (q == Q_R1 || q == Q_R2) {
2015 /* Set thresholds on receive queue's */
2016 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2017 start + (2*len)/3);
2018 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2019 start + (len/3));
2020 } else {
2021 /* Enable store & forward on Tx queue's because
2022 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2023 */
2024 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2025 }
2026
2027 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2028 }
2029
2030 /* Setup Bus Memory Interface */
2031 static void skge_qset(struct skge_port *skge, u16 q,
2032 const struct skge_element *e)
2033 {
2034 struct skge_hw *hw = skge->hw;
2035 u32 watermark = 0x600;
2036 u64 base = skge->dma + (e->desc - skge->mem);
2037
2038 /* optimization to reduce window on 32bit/33mhz */
2039 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2040 watermark /= 2;
2041
2042 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2043 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2044 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2045 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2046 }
2047
2048 static int skge_up(struct net_device *dev)
2049 {
2050 struct skge_port *skge = netdev_priv(dev);
2051 struct skge_hw *hw = skge->hw;
2052 int port = skge->port;
2053 u32 chunk, ram_addr;
2054 size_t rx_size, tx_size;
2055 int err;
2056
2057 if (netif_msg_ifup(skge))
2058 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2059
2060 if (dev->mtu > RX_BUF_SIZE)
2061 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2062 else
2063 skge->rx_buf_size = RX_BUF_SIZE;
2064
2065
2066 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2067 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2068 skge->mem_size = tx_size + rx_size;
2069 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2070 if (!skge->mem)
2071 return -ENOMEM;
2072
2073 memset(skge->mem, 0, skge->mem_size);
2074
2075 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2076 goto free_pci_mem;
2077
2078 err = skge_rx_fill(skge);
2079 if (err)
2080 goto free_rx_ring;
2081
2082 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2083 skge->dma + rx_size)))
2084 goto free_rx_ring;
2085
2086 skge->tx_avail = skge->tx_ring.count - 1;
2087
2088 /* Enable IRQ from port */
2089 hw->intr_mask |= portirqmask[port];
2090 skge_write32(hw, B0_IMSK, hw->intr_mask);
2091
2092 /* Initialze MAC */
2093 spin_lock_bh(&hw->phy_lock);
2094 if (hw->chip_id == CHIP_ID_GENESIS)
2095 genesis_mac_init(hw, port);
2096 else
2097 yukon_mac_init(hw, port);
2098 spin_unlock_bh(&hw->phy_lock);
2099
2100 /* Configure RAMbuffers */
2101 chunk = hw->ram_size / ((hw->ports + 1)*2);
2102 ram_addr = hw->ram_offset + 2 * chunk * port;
2103
2104 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2105 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2106
2107 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2108 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2109 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2110
2111 /* Start receiver BMU */
2112 wmb();
2113 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2114 skge_led(skge, LED_MODE_ON);
2115
2116 return 0;
2117
2118 free_rx_ring:
2119 skge_rx_clean(skge);
2120 kfree(skge->rx_ring.start);
2121 free_pci_mem:
2122 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2123
2124 return err;
2125 }
2126
2127 static int skge_down(struct net_device *dev)
2128 {
2129 struct skge_port *skge = netdev_priv(dev);
2130 struct skge_hw *hw = skge->hw;
2131 int port = skge->port;
2132
2133 if (netif_msg_ifdown(skge))
2134 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2135
2136 netif_stop_queue(dev);
2137
2138 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2139 if (hw->chip_id == CHIP_ID_GENESIS)
2140 genesis_stop(skge);
2141 else
2142 yukon_stop(skge);
2143
2144 hw->intr_mask &= ~portirqmask[skge->port];
2145 skge_write32(hw, B0_IMSK, hw->intr_mask);
2146
2147 /* Stop transmitter */
2148 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2149 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2150 RB_RST_SET|RB_DIS_OP_MD);
2151
2152
2153 /* Disable Force Sync bit and Enable Alloc bit */
2154 skge_write8(hw, SK_REG(port, TXA_CTRL),
2155 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2156
2157 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2158 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2159 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2160
2161 /* Reset PCI FIFO */
2162 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2163 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2164
2165 /* Reset the RAM Buffer async Tx queue */
2166 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2167 /* stop receiver */
2168 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2169 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2170 RB_RST_SET|RB_DIS_OP_MD);
2171 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2172
2173 if (hw->chip_id == CHIP_ID_GENESIS) {
2174 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2175 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2176 } else {
2177 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2178 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2179 }
2180
2181 skge_led(skge, LED_MODE_OFF);
2182
2183 skge_tx_clean(skge);
2184 skge_rx_clean(skge);
2185
2186 kfree(skge->rx_ring.start);
2187 kfree(skge->tx_ring.start);
2188 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2189 return 0;
2190 }
2191
2192 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2193 {
2194 struct skge_port *skge = netdev_priv(dev);
2195 struct skge_hw *hw = skge->hw;
2196 struct skge_ring *ring = &skge->tx_ring;
2197 struct skge_element *e;
2198 struct skge_tx_desc *td;
2199 int i;
2200 u32 control, len;
2201 u64 map;
2202 unsigned long flags;
2203
2204 skb = skb_padto(skb, ETH_ZLEN);
2205 if (!skb)
2206 return NETDEV_TX_OK;
2207
2208 local_irq_save(flags);
2209 if (!spin_trylock(&skge->tx_lock)) {
2210 /* Collision - tell upper layer to requeue */
2211 local_irq_restore(flags);
2212 return NETDEV_TX_LOCKED;
2213 }
2214
2215 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2216 netif_stop_queue(dev);
2217 spin_unlock_irqrestore(&skge->tx_lock, flags);
2218
2219 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2220 dev->name);
2221 return NETDEV_TX_BUSY;
2222 }
2223
2224 e = ring->to_use;
2225 td = e->desc;
2226 e->skb = skb;
2227 len = skb_headlen(skb);
2228 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2229 pci_unmap_addr_set(e, mapaddr, map);
2230 pci_unmap_len_set(e, maplen, len);
2231
2232 td->dma_lo = map;
2233 td->dma_hi = map >> 32;
2234
2235 if (skb->ip_summed == CHECKSUM_HW) {
2236 const struct iphdr *ip
2237 = (const struct iphdr *) (skb->data + ETH_HLEN);
2238 int offset = skb->h.raw - skb->data;
2239
2240 /* This seems backwards, but it is what the sk98lin
2241 * does. Looks like hardware is wrong?
2242 */
2243 if (ip->protocol == IPPROTO_UDP
2244 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2245 control = BMU_TCP_CHECK;
2246 else
2247 control = BMU_UDP_CHECK;
2248
2249 td->csum_offs = 0;
2250 td->csum_start = offset;
2251 td->csum_write = offset + skb->csum;
2252 } else
2253 control = BMU_CHECK;
2254
2255 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2256 control |= BMU_EOF| BMU_IRQ_EOF;
2257 else {
2258 struct skge_tx_desc *tf = td;
2259
2260 control |= BMU_STFWD;
2261 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2262 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2263
2264 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2265 frag->size, PCI_DMA_TODEVICE);
2266
2267 e = e->next;
2268 e->skb = NULL;
2269 tf = e->desc;
2270 tf->dma_lo = map;
2271 tf->dma_hi = (u64) map >> 32;
2272 pci_unmap_addr_set(e, mapaddr, map);
2273 pci_unmap_len_set(e, maplen, frag->size);
2274
2275 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2276 }
2277 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2278 }
2279 /* Make sure all the descriptors written */
2280 wmb();
2281 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2282 wmb();
2283
2284 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2285
2286 if (netif_msg_tx_queued(skge))
2287 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2288 dev->name, e - ring->start, skb->len);
2289
2290 ring->to_use = e->next;
2291 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2292 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2293 pr_debug("%s: transmit queue full\n", dev->name);
2294 netif_stop_queue(dev);
2295 }
2296
2297 dev->trans_start = jiffies;
2298 spin_unlock_irqrestore(&skge->tx_lock, flags);
2299
2300 return NETDEV_TX_OK;
2301 }
2302
2303 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2304 {
2305 /* This ring element can be skb or fragment */
2306 if (e->skb) {
2307 pci_unmap_single(hw->pdev,
2308 pci_unmap_addr(e, mapaddr),
2309 pci_unmap_len(e, maplen),
2310 PCI_DMA_TODEVICE);
2311 dev_kfree_skb_any(e->skb);
2312 e->skb = NULL;
2313 } else {
2314 pci_unmap_page(hw->pdev,
2315 pci_unmap_addr(e, mapaddr),
2316 pci_unmap_len(e, maplen),
2317 PCI_DMA_TODEVICE);
2318 }
2319 }
2320
2321 static void skge_tx_clean(struct skge_port *skge)
2322 {
2323 struct skge_ring *ring = &skge->tx_ring;
2324 struct skge_element *e;
2325 unsigned long flags;
2326
2327 spin_lock_irqsave(&skge->tx_lock, flags);
2328 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2329 ++skge->tx_avail;
2330 skge_tx_free(skge->hw, e);
2331 }
2332 ring->to_clean = e;
2333 spin_unlock_irqrestore(&skge->tx_lock, flags);
2334 }
2335
2336 static void skge_tx_timeout(struct net_device *dev)
2337 {
2338 struct skge_port *skge = netdev_priv(dev);
2339
2340 if (netif_msg_timer(skge))
2341 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2342
2343 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2344 skge_tx_clean(skge);
2345 }
2346
2347 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2348 {
2349 int err = 0;
2350 int running = netif_running(dev);
2351
2352 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2353 return -EINVAL;
2354
2355
2356 if (running)
2357 skge_down(dev);
2358 dev->mtu = new_mtu;
2359 if (running)
2360 skge_up(dev);
2361
2362 return err;
2363 }
2364
2365 static void genesis_set_multicast(struct net_device *dev)
2366 {
2367 struct skge_port *skge = netdev_priv(dev);
2368 struct skge_hw *hw = skge->hw;
2369 int port = skge->port;
2370 int i, count = dev->mc_count;
2371 struct dev_mc_list *list = dev->mc_list;
2372 u32 mode;
2373 u8 filter[8];
2374
2375 mode = xm_read32(hw, port, XM_MODE);
2376 mode |= XM_MD_ENA_HASH;
2377 if (dev->flags & IFF_PROMISC)
2378 mode |= XM_MD_ENA_PROM;
2379 else
2380 mode &= ~XM_MD_ENA_PROM;
2381
2382 if (dev->flags & IFF_ALLMULTI)
2383 memset(filter, 0xff, sizeof(filter));
2384 else {
2385 memset(filter, 0, sizeof(filter));
2386 for (i = 0; list && i < count; i++, list = list->next) {
2387 u32 crc, bit;
2388 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2389 bit = ~crc & 0x3f;
2390 filter[bit/8] |= 1 << (bit%8);
2391 }
2392 }
2393
2394 xm_write32(hw, port, XM_MODE, mode);
2395 xm_outhash(hw, port, XM_HSM, filter);
2396 }
2397
2398 static void yukon_set_multicast(struct net_device *dev)
2399 {
2400 struct skge_port *skge = netdev_priv(dev);
2401 struct skge_hw *hw = skge->hw;
2402 int port = skge->port;
2403 struct dev_mc_list *list = dev->mc_list;
2404 u16 reg;
2405 u8 filter[8];
2406
2407 memset(filter, 0, sizeof(filter));
2408
2409 reg = gma_read16(hw, port, GM_RX_CTRL);
2410 reg |= GM_RXCR_UCF_ENA;
2411
2412 if (dev->flags & IFF_PROMISC) /* promiscious */
2413 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2414 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2415 memset(filter, 0xff, sizeof(filter));
2416 else if (dev->mc_count == 0) /* no multicast */
2417 reg &= ~GM_RXCR_MCF_ENA;
2418 else {
2419 int i;
2420 reg |= GM_RXCR_MCF_ENA;
2421
2422 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2423 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2424 filter[bit/8] |= 1 << (bit%8);
2425 }
2426 }
2427
2428
2429 gma_write16(hw, port, GM_MC_ADDR_H1,
2430 (u16)filter[0] | ((u16)filter[1] << 8));
2431 gma_write16(hw, port, GM_MC_ADDR_H2,
2432 (u16)filter[2] | ((u16)filter[3] << 8));
2433 gma_write16(hw, port, GM_MC_ADDR_H3,
2434 (u16)filter[4] | ((u16)filter[5] << 8));
2435 gma_write16(hw, port, GM_MC_ADDR_H4,
2436 (u16)filter[6] | ((u16)filter[7] << 8));
2437
2438 gma_write16(hw, port, GM_RX_CTRL, reg);
2439 }
2440
2441 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2442 {
2443 if (hw->chip_id == CHIP_ID_GENESIS)
2444 return status >> XMR_FS_LEN_SHIFT;
2445 else
2446 return status >> GMR_FS_LEN_SHIFT;
2447 }
2448
2449 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2450 {
2451 if (hw->chip_id == CHIP_ID_GENESIS)
2452 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2453 else
2454 return (status & GMR_FS_ANY_ERR) ||
2455 (status & GMR_FS_RX_OK) == 0;
2456 }
2457
2458
2459 /* Get receive buffer from descriptor.
2460 * Handles copy of small buffers and reallocation failures
2461 */
2462 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2463 struct skge_element *e,
2464 u32 control, u32 status, u16 csum)
2465 {
2466 struct sk_buff *skb;
2467 u16 len = control & BMU_BBC;
2468
2469 if (unlikely(netif_msg_rx_status(skge)))
2470 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2471 skge->netdev->name, e - skge->rx_ring.start,
2472 status, len);
2473
2474 if (len > skge->rx_buf_size)
2475 goto error;
2476
2477 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2478 goto error;
2479
2480 if (bad_phy_status(skge->hw, status))
2481 goto error;
2482
2483 if (phy_length(skge->hw, status) != len)
2484 goto error;
2485
2486 if (len < RX_COPY_THRESHOLD) {
2487 skb = dev_alloc_skb(len + 2);
2488 if (!skb)
2489 goto resubmit;
2490
2491 skb_reserve(skb, 2);
2492 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2493 pci_unmap_addr(e, mapaddr),
2494 len, PCI_DMA_FROMDEVICE);
2495 memcpy(skb->data, e->skb->data, len);
2496 pci_dma_sync_single_for_device(skge->hw->pdev,
2497 pci_unmap_addr(e, mapaddr),
2498 len, PCI_DMA_FROMDEVICE);
2499 skge_rx_reuse(e, skge->rx_buf_size);
2500 } else {
2501 struct sk_buff *nskb;
2502 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2503 if (!nskb)
2504 goto resubmit;
2505
2506 pci_unmap_single(skge->hw->pdev,
2507 pci_unmap_addr(e, mapaddr),
2508 pci_unmap_len(e, maplen),
2509 PCI_DMA_FROMDEVICE);
2510 skb = e->skb;
2511 prefetch(skb->data);
2512 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2513 }
2514
2515 skb_put(skb, len);
2516 skb->dev = skge->netdev;
2517 if (skge->rx_csum) {
2518 skb->csum = csum;
2519 skb->ip_summed = CHECKSUM_HW;
2520 }
2521
2522 skb->protocol = eth_type_trans(skb, skge->netdev);
2523
2524 return skb;
2525 error:
2526
2527 if (netif_msg_rx_err(skge))
2528 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2529 skge->netdev->name, e - skge->rx_ring.start,
2530 control, status);
2531
2532 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2533 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2534 skge->net_stats.rx_length_errors++;
2535 if (status & XMR_FS_FRA_ERR)
2536 skge->net_stats.rx_frame_errors++;
2537 if (status & XMR_FS_FCS_ERR)
2538 skge->net_stats.rx_crc_errors++;
2539 } else {
2540 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2541 skge->net_stats.rx_length_errors++;
2542 if (status & GMR_FS_FRAGMENT)
2543 skge->net_stats.rx_frame_errors++;
2544 if (status & GMR_FS_CRC_ERR)
2545 skge->net_stats.rx_crc_errors++;
2546 }
2547
2548 resubmit:
2549 skge_rx_reuse(e, skge->rx_buf_size);
2550 return NULL;
2551 }
2552
2553
2554 static int skge_poll(struct net_device *dev, int *budget)
2555 {
2556 struct skge_port *skge = netdev_priv(dev);
2557 struct skge_hw *hw = skge->hw;
2558 struct skge_ring *ring = &skge->rx_ring;
2559 struct skge_element *e;
2560 unsigned int to_do = min(dev->quota, *budget);
2561 unsigned int work_done = 0;
2562
2563 for (e = ring->to_clean; work_done < to_do; e = e->next) {
2564 struct skge_rx_desc *rd = e->desc;
2565 struct sk_buff *skb;
2566 u32 control;
2567
2568 rmb();
2569 control = rd->control;
2570 if (control & BMU_OWN)
2571 break;
2572
2573 skb = skge_rx_get(skge, e, control, rd->status,
2574 le16_to_cpu(rd->csum2));
2575 if (likely(skb)) {
2576 dev->last_rx = jiffies;
2577 netif_receive_skb(skb);
2578
2579 ++work_done;
2580 } else
2581 skge_rx_reuse(e, skge->rx_buf_size);
2582 }
2583 ring->to_clean = e;
2584
2585 /* restart receiver */
2586 wmb();
2587 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2588 CSR_START | CSR_IRQ_CL_F);
2589
2590 *budget -= work_done;
2591 dev->quota -= work_done;
2592
2593 if (work_done >= to_do)
2594 return 1; /* not done */
2595
2596 local_irq_disable();
2597 __netif_rx_complete(dev);
2598 hw->intr_mask |= portirqmask[skge->port];
2599 skge_write32(hw, B0_IMSK, hw->intr_mask);
2600 local_irq_enable();
2601 return 0;
2602 }
2603
2604 static inline void skge_tx_intr(struct net_device *dev)
2605 {
2606 struct skge_port *skge = netdev_priv(dev);
2607 struct skge_hw *hw = skge->hw;
2608 struct skge_ring *ring = &skge->tx_ring;
2609 struct skge_element *e;
2610
2611 spin_lock(&skge->tx_lock);
2612 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2613 struct skge_tx_desc *td = e->desc;
2614 u32 control;
2615
2616 rmb();
2617 control = td->control;
2618 if (control & BMU_OWN)
2619 break;
2620
2621 if (unlikely(netif_msg_tx_done(skge)))
2622 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2623 dev->name, e - ring->start, td->status);
2624
2625 skge_tx_free(hw, e);
2626 e->skb = NULL;
2627 ++skge->tx_avail;
2628 }
2629 ring->to_clean = e;
2630 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2631
2632 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2633 netif_wake_queue(dev);
2634
2635 spin_unlock(&skge->tx_lock);
2636 }
2637
2638 /* Parity errors seem to happen when Genesis is connected to a switch
2639 * with no other ports present. Heartbeat error??
2640 */
2641 static void skge_mac_parity(struct skge_hw *hw, int port)
2642 {
2643 struct net_device *dev = hw->dev[port];
2644
2645 if (dev) {
2646 struct skge_port *skge = netdev_priv(dev);
2647 ++skge->net_stats.tx_heartbeat_errors;
2648 }
2649
2650 if (hw->chip_id == CHIP_ID_GENESIS)
2651 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2652 MFF_CLR_PERR);
2653 else
2654 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2655 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2656 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2657 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2658 }
2659
2660 static void skge_pci_clear(struct skge_hw *hw)
2661 {
2662 u16 status;
2663
2664 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2665 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2666 pci_write_config_word(hw->pdev, PCI_STATUS,
2667 status | PCI_STATUS_ERROR_BITS);
2668 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2669 }
2670
2671 static void skge_mac_intr(struct skge_hw *hw, int port)
2672 {
2673 if (hw->chip_id == CHIP_ID_GENESIS)
2674 genesis_mac_intr(hw, port);
2675 else
2676 yukon_mac_intr(hw, port);
2677 }
2678
2679 /* Handle device specific framing and timeout interrupts */
2680 static void skge_error_irq(struct skge_hw *hw)
2681 {
2682 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2683
2684 if (hw->chip_id == CHIP_ID_GENESIS) {
2685 /* clear xmac errors */
2686 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2687 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2688 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2689 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2690 } else {
2691 /* Timestamp (unused) overflow */
2692 if (hwstatus & IS_IRQ_TIST_OV)
2693 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2694 }
2695
2696 if (hwstatus & IS_RAM_RD_PAR) {
2697 printk(KERN_ERR PFX "Ram read data parity error\n");
2698 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2699 }
2700
2701 if (hwstatus & IS_RAM_WR_PAR) {
2702 printk(KERN_ERR PFX "Ram write data parity error\n");
2703 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2704 }
2705
2706 if (hwstatus & IS_M1_PAR_ERR)
2707 skge_mac_parity(hw, 0);
2708
2709 if (hwstatus & IS_M2_PAR_ERR)
2710 skge_mac_parity(hw, 1);
2711
2712 if (hwstatus & IS_R1_PAR_ERR)
2713 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2714
2715 if (hwstatus & IS_R2_PAR_ERR)
2716 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2717
2718 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2719 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2720 hwstatus);
2721
2722 skge_pci_clear(hw);
2723
2724 /* if error still set then just ignore it */
2725 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2726 if (hwstatus & IS_IRQ_STAT) {
2727 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2728 hwstatus);
2729 hw->intr_mask &= ~IS_HW_ERR;
2730 }
2731 }
2732 }
2733
2734 /*
2735 * Interrrupt from PHY are handled in tasklet (soft irq)
2736 * because accessing phy registers requires spin wait which might
2737 * cause excess interrupt latency.
2738 */
2739 static void skge_extirq(unsigned long data)
2740 {
2741 struct skge_hw *hw = (struct skge_hw *) data;
2742 int port;
2743
2744 spin_lock(&hw->phy_lock);
2745 for (port = 0; port < 2; port++) {
2746 struct net_device *dev = hw->dev[port];
2747
2748 if (dev && netif_running(dev)) {
2749 struct skge_port *skge = netdev_priv(dev);
2750
2751 if (hw->chip_id != CHIP_ID_GENESIS)
2752 yukon_phy_intr(skge);
2753 else
2754 bcom_phy_intr(skge);
2755 }
2756 }
2757 spin_unlock(&hw->phy_lock);
2758
2759 local_irq_disable();
2760 hw->intr_mask |= IS_EXT_REG;
2761 skge_write32(hw, B0_IMSK, hw->intr_mask);
2762 local_irq_enable();
2763 }
2764
2765 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2766 {
2767 struct skge_hw *hw = dev_id;
2768 u32 status = skge_read32(hw, B0_SP_ISRC);
2769
2770 if (status == 0 || status == ~0) /* hotplug or shared irq */
2771 return IRQ_NONE;
2772
2773 status &= hw->intr_mask;
2774 if (status & IS_R1_F) {
2775 hw->intr_mask &= ~IS_R1_F;
2776 netif_rx_schedule(hw->dev[0]);
2777 }
2778
2779 if (status & IS_R2_F) {
2780 hw->intr_mask &= ~IS_R2_F;
2781 netif_rx_schedule(hw->dev[1]);
2782 }
2783
2784 if (status & IS_XA1_F)
2785 skge_tx_intr(hw->dev[0]);
2786
2787 if (status & IS_XA2_F)
2788 skge_tx_intr(hw->dev[1]);
2789
2790 if (status & IS_PA_TO_RX1) {
2791 struct skge_port *skge = netdev_priv(hw->dev[0]);
2792 ++skge->net_stats.rx_over_errors;
2793 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2794 }
2795
2796 if (status & IS_PA_TO_RX2) {
2797 struct skge_port *skge = netdev_priv(hw->dev[1]);
2798 ++skge->net_stats.rx_over_errors;
2799 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2800 }
2801
2802 if (status & IS_PA_TO_TX1)
2803 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2804
2805 if (status & IS_PA_TO_TX2)
2806 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2807
2808 if (status & IS_MAC1)
2809 skge_mac_intr(hw, 0);
2810
2811 if (status & IS_MAC2)
2812 skge_mac_intr(hw, 1);
2813
2814 if (status & IS_HW_ERR)
2815 skge_error_irq(hw);
2816
2817 if (status & IS_EXT_REG) {
2818 hw->intr_mask &= ~IS_EXT_REG;
2819 tasklet_schedule(&hw->ext_tasklet);
2820 }
2821
2822 skge_write32(hw, B0_IMSK, hw->intr_mask);
2823
2824 return IRQ_HANDLED;
2825 }
2826
2827 #ifdef CONFIG_NET_POLL_CONTROLLER
2828 static void skge_netpoll(struct net_device *dev)
2829 {
2830 struct skge_port *skge = netdev_priv(dev);
2831
2832 disable_irq(dev->irq);
2833 skge_intr(dev->irq, skge->hw, NULL);
2834 enable_irq(dev->irq);
2835 }
2836 #endif
2837
2838 static int skge_set_mac_address(struct net_device *dev, void *p)
2839 {
2840 struct skge_port *skge = netdev_priv(dev);
2841 struct skge_hw *hw = skge->hw;
2842 unsigned port = skge->port;
2843 const struct sockaddr *addr = p;
2844
2845 if (!is_valid_ether_addr(addr->sa_data))
2846 return -EADDRNOTAVAIL;
2847
2848 spin_lock_bh(&hw->phy_lock);
2849 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2850 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2851 dev->dev_addr, ETH_ALEN);
2852 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2853 dev->dev_addr, ETH_ALEN);
2854
2855 if (hw->chip_id == CHIP_ID_GENESIS)
2856 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2857 else {
2858 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2859 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2860 }
2861 spin_unlock_bh(&hw->phy_lock);
2862
2863 return 0;
2864 }
2865
2866 static const struct {
2867 u8 id;
2868 const char *name;
2869 } skge_chips[] = {
2870 { CHIP_ID_GENESIS, "Genesis" },
2871 { CHIP_ID_YUKON, "Yukon" },
2872 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2873 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2874 };
2875
2876 static const char *skge_board_name(const struct skge_hw *hw)
2877 {
2878 int i;
2879 static char buf[16];
2880
2881 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2882 if (skge_chips[i].id == hw->chip_id)
2883 return skge_chips[i].name;
2884
2885 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2886 return buf;
2887 }
2888
2889
2890 /*
2891 * Setup the board data structure, but don't bring up
2892 * the port(s)
2893 */
2894 static int skge_reset(struct skge_hw *hw)
2895 {
2896 u16 ctst;
2897 u8 t8, mac_cfg, pmd_type, phy_type;
2898 int i;
2899
2900 ctst = skge_read16(hw, B0_CTST);
2901
2902 /* do a SW reset */
2903 skge_write8(hw, B0_CTST, CS_RST_SET);
2904 skge_write8(hw, B0_CTST, CS_RST_CLR);
2905
2906 /* clear PCI errors, if any */
2907 skge_pci_clear(hw);
2908
2909 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2910
2911 /* restore CLK_RUN bits (for Yukon-Lite) */
2912 skge_write16(hw, B0_CTST,
2913 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2914
2915 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2916 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2917 pmd_type = skge_read8(hw, B2_PMD_TYP);
2918 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2919
2920 switch (hw->chip_id) {
2921 case CHIP_ID_GENESIS:
2922 switch (phy_type) {
2923 case SK_PHY_BCOM:
2924 hw->phy_addr = PHY_ADDR_BCOM;
2925 break;
2926 default:
2927 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2928 pci_name(hw->pdev), phy_type);
2929 return -EOPNOTSUPP;
2930 }
2931 break;
2932
2933 case CHIP_ID_YUKON:
2934 case CHIP_ID_YUKON_LITE:
2935 case CHIP_ID_YUKON_LP:
2936 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2937 hw->copper = 1;
2938
2939 hw->phy_addr = PHY_ADDR_MARV;
2940 break;
2941
2942 default:
2943 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2944 pci_name(hw->pdev), hw->chip_id);
2945 return -EOPNOTSUPP;
2946 }
2947
2948 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2949 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2950 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2951
2952 /* read the adapters RAM size */
2953 t8 = skge_read8(hw, B2_E_0);
2954 if (hw->chip_id == CHIP_ID_GENESIS) {
2955 if (t8 == 3) {
2956 /* special case: 4 x 64k x 36, offset = 0x80000 */
2957 hw->ram_size = 0x100000;
2958 hw->ram_offset = 0x80000;
2959 } else
2960 hw->ram_size = t8 * 512;
2961 }
2962 else if (t8 == 0)
2963 hw->ram_size = 0x20000;
2964 else
2965 hw->ram_size = t8 * 4096;
2966
2967 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
2968 if (hw->chip_id == CHIP_ID_GENESIS)
2969 genesis_init(hw);
2970 else {
2971 /* switch power to VCC (WA for VAUX problem) */
2972 skge_write8(hw, B0_POWER_CTRL,
2973 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2974 /* avoid boards with stuck Hardware error bits */
2975 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2976 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2977 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
2978 hw->intr_mask &= ~IS_HW_ERR;
2979 }
2980
2981 for (i = 0; i < hw->ports; i++) {
2982 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2983 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2984 }
2985 }
2986
2987 /* turn off hardware timer (unused) */
2988 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2989 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2990 skge_write8(hw, B0_LED, LED_STAT_ON);
2991
2992 /* enable the Tx Arbiters */
2993 for (i = 0; i < hw->ports; i++)
2994 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2995
2996 /* Initialize ram interface */
2997 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2998
2999 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3000 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3001 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3002 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3003 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3004 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3005 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3006 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3007 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3008 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3009 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3010 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3011
3012 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3013
3014 /* Set interrupt moderation for Transmit only
3015 * Receive interrupts avoided by NAPI
3016 */
3017 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3018 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3019 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3020
3021 skge_write32(hw, B0_IMSK, hw->intr_mask);
3022
3023 spin_lock_bh(&hw->phy_lock);
3024 for (i = 0; i < hw->ports; i++) {
3025 if (hw->chip_id == CHIP_ID_GENESIS)
3026 genesis_reset(hw, i);
3027 else
3028 yukon_reset(hw, i);
3029 }
3030 spin_unlock_bh(&hw->phy_lock);
3031
3032 return 0;
3033 }
3034
3035 /* Initialize network device */
3036 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3037 int highmem)
3038 {
3039 struct skge_port *skge;
3040 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3041
3042 if (!dev) {
3043 printk(KERN_ERR "skge etherdev alloc failed");
3044 return NULL;
3045 }
3046
3047 SET_MODULE_OWNER(dev);
3048 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3049 dev->open = skge_up;
3050 dev->stop = skge_down;
3051 dev->hard_start_xmit = skge_xmit_frame;
3052 dev->get_stats = skge_get_stats;
3053 if (hw->chip_id == CHIP_ID_GENESIS)
3054 dev->set_multicast_list = genesis_set_multicast;
3055 else
3056 dev->set_multicast_list = yukon_set_multicast;
3057
3058 dev->set_mac_address = skge_set_mac_address;
3059 dev->change_mtu = skge_change_mtu;
3060 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3061 dev->tx_timeout = skge_tx_timeout;
3062 dev->watchdog_timeo = TX_WATCHDOG;
3063 dev->poll = skge_poll;
3064 dev->weight = NAPI_WEIGHT;
3065 #ifdef CONFIG_NET_POLL_CONTROLLER
3066 dev->poll_controller = skge_netpoll;
3067 #endif
3068 dev->irq = hw->pdev->irq;
3069 dev->features = NETIF_F_LLTX;
3070 if (highmem)
3071 dev->features |= NETIF_F_HIGHDMA;
3072
3073 skge = netdev_priv(dev);
3074 skge->netdev = dev;
3075 skge->hw = hw;
3076 skge->msg_enable = netif_msg_init(debug, default_msg);
3077 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3078 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3079
3080 /* Auto speed and flow control */
3081 skge->autoneg = AUTONEG_ENABLE;
3082 skge->flow_control = FLOW_MODE_SYMMETRIC;
3083 skge->duplex = -1;
3084 skge->speed = -1;
3085 skge->advertising = skge_supported_modes(hw);
3086
3087 hw->dev[port] = dev;
3088
3089 skge->port = port;
3090
3091 spin_lock_init(&skge->tx_lock);
3092
3093 if (hw->chip_id != CHIP_ID_GENESIS) {
3094 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3095 skge->rx_csum = 1;
3096 }
3097
3098 /* read the mac address */
3099 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3100 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3101
3102 /* device is off until link detection */
3103 netif_carrier_off(dev);
3104 netif_stop_queue(dev);
3105
3106 return dev;
3107 }
3108
3109 static void __devinit skge_show_addr(struct net_device *dev)
3110 {
3111 const struct skge_port *skge = netdev_priv(dev);
3112
3113 if (netif_msg_probe(skge))
3114 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3115 dev->name,
3116 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3117 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3118 }
3119
3120 static int __devinit skge_probe(struct pci_dev *pdev,
3121 const struct pci_device_id *ent)
3122 {
3123 struct net_device *dev, *dev1;
3124 struct skge_hw *hw;
3125 int err, using_dac = 0;
3126
3127 if ((err = pci_enable_device(pdev))) {
3128 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3129 pci_name(pdev));
3130 goto err_out;
3131 }
3132
3133 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3134 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3135 pci_name(pdev));
3136 goto err_out_disable_pdev;
3137 }
3138
3139 pci_set_master(pdev);
3140
3141 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3142 using_dac = 1;
3143 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3144 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3145 pci_name(pdev));
3146 goto err_out_free_regions;
3147 }
3148
3149 #ifdef __BIG_ENDIAN
3150 /* byte swap decriptors in hardware */
3151 {
3152 u32 reg;
3153
3154 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3155 reg |= PCI_REV_DESC;
3156 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3157 }
3158 #endif
3159
3160 err = -ENOMEM;
3161 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3162 if (!hw) {
3163 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3164 pci_name(pdev));
3165 goto err_out_free_regions;
3166 }
3167
3168 memset(hw, 0, sizeof(*hw));
3169 hw->pdev = pdev;
3170 spin_lock_init(&hw->phy_lock);
3171 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3172
3173 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3174 if (!hw->regs) {
3175 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3176 pci_name(pdev));
3177 goto err_out_free_hw;
3178 }
3179
3180 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3181 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3182 pci_name(pdev), pdev->irq);
3183 goto err_out_iounmap;
3184 }
3185 pci_set_drvdata(pdev, hw);
3186
3187 err = skge_reset(hw);
3188 if (err)
3189 goto err_out_free_irq;
3190
3191 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3192 pci_resource_start(pdev, 0), pdev->irq,
3193 skge_board_name(hw), hw->chip_rev);
3194
3195 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3196 goto err_out_led_off;
3197
3198 if ((err = register_netdev(dev))) {
3199 printk(KERN_ERR PFX "%s: cannot register net device\n",
3200 pci_name(pdev));
3201 goto err_out_free_netdev;
3202 }
3203
3204 skge_show_addr(dev);
3205
3206 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3207 if (register_netdev(dev1) == 0)
3208 skge_show_addr(dev1);
3209 else {
3210 /* Failure to register second port need not be fatal */
3211 printk(KERN_WARNING PFX "register of second port failed\n");
3212 hw->dev[1] = NULL;
3213 free_netdev(dev1);
3214 }
3215 }
3216
3217 return 0;
3218
3219 err_out_free_netdev:
3220 free_netdev(dev);
3221 err_out_led_off:
3222 skge_write16(hw, B0_LED, LED_STAT_OFF);
3223 err_out_free_irq:
3224 free_irq(pdev->irq, hw);
3225 err_out_iounmap:
3226 iounmap(hw->regs);
3227 err_out_free_hw:
3228 kfree(hw);
3229 err_out_free_regions:
3230 pci_release_regions(pdev);
3231 err_out_disable_pdev:
3232 pci_disable_device(pdev);
3233 pci_set_drvdata(pdev, NULL);
3234 err_out:
3235 return err;
3236 }
3237
3238 static void __devexit skge_remove(struct pci_dev *pdev)
3239 {
3240 struct skge_hw *hw = pci_get_drvdata(pdev);
3241 struct net_device *dev0, *dev1;
3242
3243 if (!hw)
3244 return;
3245
3246 if ((dev1 = hw->dev[1]))
3247 unregister_netdev(dev1);
3248 dev0 = hw->dev[0];
3249 unregister_netdev(dev0);
3250
3251 skge_write32(hw, B0_IMSK, 0);
3252 skge_write16(hw, B0_LED, LED_STAT_OFF);
3253 skge_pci_clear(hw);
3254 skge_write8(hw, B0_CTST, CS_RST_SET);
3255
3256 tasklet_kill(&hw->ext_tasklet);
3257
3258 free_irq(pdev->irq, hw);
3259 pci_release_regions(pdev);
3260 pci_disable_device(pdev);
3261 if (dev1)
3262 free_netdev(dev1);
3263 free_netdev(dev0);
3264
3265 iounmap(hw->regs);
3266 kfree(hw);
3267 pci_set_drvdata(pdev, NULL);
3268 }
3269
3270 #ifdef CONFIG_PM
3271 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3272 {
3273 struct skge_hw *hw = pci_get_drvdata(pdev);
3274 int i, wol = 0;
3275
3276 for (i = 0; i < 2; i++) {
3277 struct net_device *dev = hw->dev[i];
3278
3279 if (dev) {
3280 struct skge_port *skge = netdev_priv(dev);
3281 if (netif_running(dev)) {
3282 netif_carrier_off(dev);
3283 if (skge->wol)
3284 netif_stop_queue(dev);
3285 else
3286 skge_down(dev);
3287 }
3288 netif_device_detach(dev);
3289 wol |= skge->wol;
3290 }
3291 }
3292
3293 pci_save_state(pdev);
3294 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3295 pci_disable_device(pdev);
3296 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3297
3298 return 0;
3299 }
3300
3301 static int skge_resume(struct pci_dev *pdev)
3302 {
3303 struct skge_hw *hw = pci_get_drvdata(pdev);
3304 int i;
3305
3306 pci_set_power_state(pdev, PCI_D0);
3307 pci_restore_state(pdev);
3308 pci_enable_wake(pdev, PCI_D0, 0);
3309
3310 skge_reset(hw);
3311
3312 for (i = 0; i < 2; i++) {
3313 struct net_device *dev = hw->dev[i];
3314 if (dev) {
3315 netif_device_attach(dev);
3316 if (netif_running(dev))
3317 skge_up(dev);
3318 }
3319 }
3320 return 0;
3321 }
3322 #endif
3323
3324 static struct pci_driver skge_driver = {
3325 .name = DRV_NAME,
3326 .id_table = skge_id_table,
3327 .probe = skge_probe,
3328 .remove = __devexit_p(skge_remove),
3329 #ifdef CONFIG_PM
3330 .suspend = skge_suspend,
3331 .resume = skge_resume,
3332 #endif
3333 };
3334
3335 static int __init skge_init_module(void)
3336 {
3337 return pci_module_init(&skge_driver);
3338 }
3339
3340 static void __exit skge_cleanup_module(void)
3341 {
3342 pci_unregister_driver(&skge_driver);
3343 }
3344
3345 module_init(skge_init_module);
3346 module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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