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skge: fiber link up/down fix
[deliverable/linux.git] / drivers / net / skge.c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/in.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ip.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/debugfs.h>
40 #include <linux/seq_file.h>
41 #include <linux/mii.h>
42 #include <asm/irq.h>
43
44 #include "skge.h"
45
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.12"
48 #define PFX DRV_NAME " "
49
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
54 #define MAX_RX_RING_SIZE 4096
55 #define RX_COPY_THRESHOLD 128
56 #define RX_BUF_SIZE 1536
57 #define PHY_RETRIES 1000
58 #define ETH_JUMBO_MTU 9000
59 #define TX_WATCHDOG (5 * HZ)
60 #define NAPI_WEIGHT 64
61 #define BLINK_MS 250
62 #define LINK_HZ HZ
63
64 #define SKGE_EEPROM_MAGIC 0x9933aabb
65
66
67 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
68 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
69 MODULE_LICENSE("GPL");
70 MODULE_VERSION(DRV_VERSION);
71
72 static const u32 default_msg
73 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
74 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
75
76 static int debug = -1; /* defaults above */
77 module_param(debug, int, 0);
78 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
79
80 static const struct pci_device_id skge_id_table[] = {
81 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
82 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
83 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
84 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
85 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
86 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
87 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
88 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
89 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
90 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
91 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
92 { 0 }
93 };
94 MODULE_DEVICE_TABLE(pci, skge_id_table);
95
96 static int skge_up(struct net_device *dev);
97 static int skge_down(struct net_device *dev);
98 static void skge_phy_reset(struct skge_port *skge);
99 static void skge_tx_clean(struct net_device *dev);
100 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
101 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
102 static void genesis_get_stats(struct skge_port *skge, u64 *data);
103 static void yukon_get_stats(struct skge_port *skge, u64 *data);
104 static void yukon_init(struct skge_hw *hw, int port);
105 static void genesis_mac_init(struct skge_hw *hw, int port);
106 static void genesis_link_up(struct skge_port *skge);
107
108 /* Avoid conditionals by using array */
109 static const int txqaddr[] = { Q_XA1, Q_XA2 };
110 static const int rxqaddr[] = { Q_R1, Q_R2 };
111 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
112 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
113 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
114 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
115
116 static int skge_get_regs_len(struct net_device *dev)
117 {
118 return 0x4000;
119 }
120
121 /*
122 * Returns copy of whole control register region
123 * Note: skip RAM address register because accessing it will
124 * cause bus hangs!
125 */
126 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
127 void *p)
128 {
129 const struct skge_port *skge = netdev_priv(dev);
130 const void __iomem *io = skge->hw->regs;
131
132 regs->version = 1;
133 memset(p, 0, regs->len);
134 memcpy_fromio(p, io, B3_RAM_ADDR);
135
136 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
137 regs->len - B3_RI_WTO_R1);
138 }
139
140 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
141 static u32 wol_supported(const struct skge_hw *hw)
142 {
143 if (hw->chip_id == CHIP_ID_GENESIS)
144 return 0;
145
146 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
147 return 0;
148
149 return WAKE_MAGIC | WAKE_PHY;
150 }
151
152 static u32 pci_wake_enabled(struct pci_dev *dev)
153 {
154 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
155 u16 value;
156
157 /* If device doesn't support PM Capabilities, but request is to disable
158 * wake events, it's a nop; otherwise fail */
159 if (!pm)
160 return 0;
161
162 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
163
164 value &= PCI_PM_CAP_PME_MASK;
165 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
166
167 return value != 0;
168 }
169
170 static void skge_wol_init(struct skge_port *skge)
171 {
172 struct skge_hw *hw = skge->hw;
173 int port = skge->port;
174 u16 ctrl;
175
176 skge_write16(hw, B0_CTST, CS_RST_CLR);
177 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
178
179 /* Turn on Vaux */
180 skge_write8(hw, B0_POWER_CTRL,
181 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
182
183 /* WA code for COMA mode -- clear PHY reset */
184 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
185 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
186 u32 reg = skge_read32(hw, B2_GP_IO);
187 reg |= GP_DIR_9;
188 reg &= ~GP_IO_9;
189 skge_write32(hw, B2_GP_IO, reg);
190 }
191
192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_SET);
196
197 skge_write32(hw, SK_REG(port, GPHY_CTRL),
198 GPC_DIS_SLEEP |
199 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
200 GPC_ANEG_1 | GPC_RST_CLR);
201
202 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
203
204 /* Force to 10/100 skge_reset will re-enable on resume */
205 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
206 PHY_AN_100FULL | PHY_AN_100HALF |
207 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
208 /* no 1000 HD/FD */
209 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
210 gm_phy_write(hw, port, PHY_MARV_CTRL,
211 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
212 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
213
214
215 /* Set GMAC to no flow control and auto update for speed/duplex */
216 gma_write16(hw, port, GM_GP_CTRL,
217 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
218 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
219
220 /* Set WOL address */
221 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
222 skge->netdev->dev_addr, ETH_ALEN);
223
224 /* Turn on appropriate WOL control bits */
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
226 ctrl = 0;
227 if (skge->wol & WAKE_PHY)
228 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
231
232 if (skge->wol & WAKE_MAGIC)
233 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
234 else
235 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
236
237 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
238 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
239
240 /* block receiver */
241 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
242 }
243
244 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
245 {
246 struct skge_port *skge = netdev_priv(dev);
247
248 wol->supported = wol_supported(skge->hw);
249 wol->wolopts = skge->wol;
250 }
251
252 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
253 {
254 struct skge_port *skge = netdev_priv(dev);
255 struct skge_hw *hw = skge->hw;
256
257 if (wol->wolopts & ~wol_supported(hw))
258 return -EOPNOTSUPP;
259
260 skge->wol = wol->wolopts;
261 return 0;
262 }
263
264 /* Determine supported/advertised modes based on hardware.
265 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
266 */
267 static u32 skge_supported_modes(const struct skge_hw *hw)
268 {
269 u32 supported;
270
271 if (hw->copper) {
272 supported = SUPPORTED_10baseT_Half
273 | SUPPORTED_10baseT_Full
274 | SUPPORTED_100baseT_Half
275 | SUPPORTED_100baseT_Full
276 | SUPPORTED_1000baseT_Half
277 | SUPPORTED_1000baseT_Full
278 | SUPPORTED_Autoneg| SUPPORTED_TP;
279
280 if (hw->chip_id == CHIP_ID_GENESIS)
281 supported &= ~(SUPPORTED_10baseT_Half
282 | SUPPORTED_10baseT_Full
283 | SUPPORTED_100baseT_Half
284 | SUPPORTED_100baseT_Full);
285
286 else if (hw->chip_id == CHIP_ID_YUKON)
287 supported &= ~SUPPORTED_1000baseT_Half;
288 } else
289 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
290 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
291
292 return supported;
293 }
294
295 static int skge_get_settings(struct net_device *dev,
296 struct ethtool_cmd *ecmd)
297 {
298 struct skge_port *skge = netdev_priv(dev);
299 struct skge_hw *hw = skge->hw;
300
301 ecmd->transceiver = XCVR_INTERNAL;
302 ecmd->supported = skge_supported_modes(hw);
303
304 if (hw->copper) {
305 ecmd->port = PORT_TP;
306 ecmd->phy_address = hw->phy_addr;
307 } else
308 ecmd->port = PORT_FIBRE;
309
310 ecmd->advertising = skge->advertising;
311 ecmd->autoneg = skge->autoneg;
312 ecmd->speed = skge->speed;
313 ecmd->duplex = skge->duplex;
314 return 0;
315 }
316
317 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
318 {
319 struct skge_port *skge = netdev_priv(dev);
320 const struct skge_hw *hw = skge->hw;
321 u32 supported = skge_supported_modes(hw);
322
323 if (ecmd->autoneg == AUTONEG_ENABLE) {
324 ecmd->advertising = supported;
325 skge->duplex = -1;
326 skge->speed = -1;
327 } else {
328 u32 setting;
329
330 switch (ecmd->speed) {
331 case SPEED_1000:
332 if (ecmd->duplex == DUPLEX_FULL)
333 setting = SUPPORTED_1000baseT_Full;
334 else if (ecmd->duplex == DUPLEX_HALF)
335 setting = SUPPORTED_1000baseT_Half;
336 else
337 return -EINVAL;
338 break;
339 case SPEED_100:
340 if (ecmd->duplex == DUPLEX_FULL)
341 setting = SUPPORTED_100baseT_Full;
342 else if (ecmd->duplex == DUPLEX_HALF)
343 setting = SUPPORTED_100baseT_Half;
344 else
345 return -EINVAL;
346 break;
347
348 case SPEED_10:
349 if (ecmd->duplex == DUPLEX_FULL)
350 setting = SUPPORTED_10baseT_Full;
351 else if (ecmd->duplex == DUPLEX_HALF)
352 setting = SUPPORTED_10baseT_Half;
353 else
354 return -EINVAL;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 if ((setting & supported) == 0)
361 return -EINVAL;
362
363 skge->speed = ecmd->speed;
364 skge->duplex = ecmd->duplex;
365 }
366
367 skge->autoneg = ecmd->autoneg;
368 skge->advertising = ecmd->advertising;
369
370 if (netif_running(dev))
371 skge_phy_reset(skge);
372
373 return (0);
374 }
375
376 static void skge_get_drvinfo(struct net_device *dev,
377 struct ethtool_drvinfo *info)
378 {
379 struct skge_port *skge = netdev_priv(dev);
380
381 strcpy(info->driver, DRV_NAME);
382 strcpy(info->version, DRV_VERSION);
383 strcpy(info->fw_version, "N/A");
384 strcpy(info->bus_info, pci_name(skge->hw->pdev));
385 }
386
387 static const struct skge_stat {
388 char name[ETH_GSTRING_LEN];
389 u16 xmac_offset;
390 u16 gma_offset;
391 } skge_stats[] = {
392 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
393 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
394
395 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
396 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
397 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
398 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
399 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
400 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
401 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
402 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
403
404 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
405 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
406 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
407 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
408 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
409 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
410
411 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
412 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
413 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
414 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
415 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
416 };
417
418 static int skge_get_sset_count(struct net_device *dev, int sset)
419 {
420 switch (sset) {
421 case ETH_SS_STATS:
422 return ARRAY_SIZE(skge_stats);
423 default:
424 return -EOPNOTSUPP;
425 }
426 }
427
428 static void skge_get_ethtool_stats(struct net_device *dev,
429 struct ethtool_stats *stats, u64 *data)
430 {
431 struct skge_port *skge = netdev_priv(dev);
432
433 if (skge->hw->chip_id == CHIP_ID_GENESIS)
434 genesis_get_stats(skge, data);
435 else
436 yukon_get_stats(skge, data);
437 }
438
439 /* Use hardware MIB variables for critical path statistics and
440 * transmit feedback not reported at interrupt.
441 * Other errors are accounted for in interrupt handler.
442 */
443 static struct net_device_stats *skge_get_stats(struct net_device *dev)
444 {
445 struct skge_port *skge = netdev_priv(dev);
446 u64 data[ARRAY_SIZE(skge_stats)];
447
448 if (skge->hw->chip_id == CHIP_ID_GENESIS)
449 genesis_get_stats(skge, data);
450 else
451 yukon_get_stats(skge, data);
452
453 dev->stats.tx_bytes = data[0];
454 dev->stats.rx_bytes = data[1];
455 dev->stats.tx_packets = data[2] + data[4] + data[6];
456 dev->stats.rx_packets = data[3] + data[5] + data[7];
457 dev->stats.multicast = data[3] + data[5];
458 dev->stats.collisions = data[10];
459 dev->stats.tx_aborted_errors = data[12];
460
461 return &dev->stats;
462 }
463
464 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
465 {
466 int i;
467
468 switch (stringset) {
469 case ETH_SS_STATS:
470 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
471 memcpy(data + i * ETH_GSTRING_LEN,
472 skge_stats[i].name, ETH_GSTRING_LEN);
473 break;
474 }
475 }
476
477 static void skge_get_ring_param(struct net_device *dev,
478 struct ethtool_ringparam *p)
479 {
480 struct skge_port *skge = netdev_priv(dev);
481
482 p->rx_max_pending = MAX_RX_RING_SIZE;
483 p->tx_max_pending = MAX_TX_RING_SIZE;
484 p->rx_mini_max_pending = 0;
485 p->rx_jumbo_max_pending = 0;
486
487 p->rx_pending = skge->rx_ring.count;
488 p->tx_pending = skge->tx_ring.count;
489 p->rx_mini_pending = 0;
490 p->rx_jumbo_pending = 0;
491 }
492
493 static int skge_set_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
495 {
496 struct skge_port *skge = netdev_priv(dev);
497 int err;
498
499 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
500 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
501 return -EINVAL;
502
503 skge->rx_ring.count = p->rx_pending;
504 skge->tx_ring.count = p->tx_pending;
505
506 if (netif_running(dev)) {
507 skge_down(dev);
508 err = skge_up(dev);
509 if (err)
510 dev_close(dev);
511 }
512
513 return 0;
514 }
515
516 static u32 skge_get_msglevel(struct net_device *netdev)
517 {
518 struct skge_port *skge = netdev_priv(netdev);
519 return skge->msg_enable;
520 }
521
522 static void skge_set_msglevel(struct net_device *netdev, u32 value)
523 {
524 struct skge_port *skge = netdev_priv(netdev);
525 skge->msg_enable = value;
526 }
527
528 static int skge_nway_reset(struct net_device *dev)
529 {
530 struct skge_port *skge = netdev_priv(dev);
531
532 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
533 return -EINVAL;
534
535 skge_phy_reset(skge);
536 return 0;
537 }
538
539 static int skge_set_sg(struct net_device *dev, u32 data)
540 {
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543
544 if (hw->chip_id == CHIP_ID_GENESIS && data)
545 return -EOPNOTSUPP;
546 return ethtool_op_set_sg(dev, data);
547 }
548
549 static int skge_set_tx_csum(struct net_device *dev, u32 data)
550 {
551 struct skge_port *skge = netdev_priv(dev);
552 struct skge_hw *hw = skge->hw;
553
554 if (hw->chip_id == CHIP_ID_GENESIS && data)
555 return -EOPNOTSUPP;
556
557 return ethtool_op_set_tx_csum(dev, data);
558 }
559
560 static u32 skge_get_rx_csum(struct net_device *dev)
561 {
562 struct skge_port *skge = netdev_priv(dev);
563
564 return skge->rx_csum;
565 }
566
567 /* Only Yukon supports checksum offload. */
568 static int skge_set_rx_csum(struct net_device *dev, u32 data)
569 {
570 struct skge_port *skge = netdev_priv(dev);
571
572 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
573 return -EOPNOTSUPP;
574
575 skge->rx_csum = data;
576 return 0;
577 }
578
579 static void skge_get_pauseparam(struct net_device *dev,
580 struct ethtool_pauseparam *ecmd)
581 {
582 struct skge_port *skge = netdev_priv(dev);
583
584 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
585 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
586 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
587
588 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
589 }
590
591 static int skge_set_pauseparam(struct net_device *dev,
592 struct ethtool_pauseparam *ecmd)
593 {
594 struct skge_port *skge = netdev_priv(dev);
595 struct ethtool_pauseparam old;
596
597 skge_get_pauseparam(dev, &old);
598
599 if (ecmd->autoneg != old.autoneg)
600 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
601 else {
602 if (ecmd->rx_pause && ecmd->tx_pause)
603 skge->flow_control = FLOW_MODE_SYMMETRIC;
604 else if (ecmd->rx_pause && !ecmd->tx_pause)
605 skge->flow_control = FLOW_MODE_SYM_OR_REM;
606 else if (!ecmd->rx_pause && ecmd->tx_pause)
607 skge->flow_control = FLOW_MODE_LOC_SEND;
608 else
609 skge->flow_control = FLOW_MODE_NONE;
610 }
611
612 if (netif_running(dev))
613 skge_phy_reset(skge);
614
615 return 0;
616 }
617
618 /* Chip internal frequency for clock calculations */
619 static inline u32 hwkhz(const struct skge_hw *hw)
620 {
621 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
622 }
623
624 /* Chip HZ to microseconds */
625 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
626 {
627 return (ticks * 1000) / hwkhz(hw);
628 }
629
630 /* Microseconds to chip HZ */
631 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
632 {
633 return hwkhz(hw) * usec / 1000;
634 }
635
636 static int skge_get_coalesce(struct net_device *dev,
637 struct ethtool_coalesce *ecmd)
638 {
639 struct skge_port *skge = netdev_priv(dev);
640 struct skge_hw *hw = skge->hw;
641 int port = skge->port;
642
643 ecmd->rx_coalesce_usecs = 0;
644 ecmd->tx_coalesce_usecs = 0;
645
646 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
647 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
648 u32 msk = skge_read32(hw, B2_IRQM_MSK);
649
650 if (msk & rxirqmask[port])
651 ecmd->rx_coalesce_usecs = delay;
652 if (msk & txirqmask[port])
653 ecmd->tx_coalesce_usecs = delay;
654 }
655
656 return 0;
657 }
658
659 /* Note: interrupt timer is per board, but can turn on/off per port */
660 static int skge_set_coalesce(struct net_device *dev,
661 struct ethtool_coalesce *ecmd)
662 {
663 struct skge_port *skge = netdev_priv(dev);
664 struct skge_hw *hw = skge->hw;
665 int port = skge->port;
666 u32 msk = skge_read32(hw, B2_IRQM_MSK);
667 u32 delay = 25;
668
669 if (ecmd->rx_coalesce_usecs == 0)
670 msk &= ~rxirqmask[port];
671 else if (ecmd->rx_coalesce_usecs < 25 ||
672 ecmd->rx_coalesce_usecs > 33333)
673 return -EINVAL;
674 else {
675 msk |= rxirqmask[port];
676 delay = ecmd->rx_coalesce_usecs;
677 }
678
679 if (ecmd->tx_coalesce_usecs == 0)
680 msk &= ~txirqmask[port];
681 else if (ecmd->tx_coalesce_usecs < 25 ||
682 ecmd->tx_coalesce_usecs > 33333)
683 return -EINVAL;
684 else {
685 msk |= txirqmask[port];
686 delay = min(delay, ecmd->rx_coalesce_usecs);
687 }
688
689 skge_write32(hw, B2_IRQM_MSK, msk);
690 if (msk == 0)
691 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
692 else {
693 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
694 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
695 }
696 return 0;
697 }
698
699 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
700 static void skge_led(struct skge_port *skge, enum led_mode mode)
701 {
702 struct skge_hw *hw = skge->hw;
703 int port = skge->port;
704
705 spin_lock_bh(&hw->phy_lock);
706 if (hw->chip_id == CHIP_ID_GENESIS) {
707 switch (mode) {
708 case LED_MODE_OFF:
709 if (hw->phy_type == SK_PHY_BCOM)
710 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
711 else {
712 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
713 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
714 }
715 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
716 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
717 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
718 break;
719
720 case LED_MODE_ON:
721 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
722 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
723
724 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
725 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
726
727 break;
728
729 case LED_MODE_TST:
730 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
731 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
732 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
733
734 if (hw->phy_type == SK_PHY_BCOM)
735 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
736 else {
737 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
738 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
739 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
740 }
741
742 }
743 } else {
744 switch (mode) {
745 case LED_MODE_OFF:
746 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
747 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
748 PHY_M_LED_MO_DUP(MO_LED_OFF) |
749 PHY_M_LED_MO_10(MO_LED_OFF) |
750 PHY_M_LED_MO_100(MO_LED_OFF) |
751 PHY_M_LED_MO_1000(MO_LED_OFF) |
752 PHY_M_LED_MO_RX(MO_LED_OFF));
753 break;
754 case LED_MODE_ON:
755 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
756 PHY_M_LED_PULS_DUR(PULS_170MS) |
757 PHY_M_LED_BLINK_RT(BLINK_84MS) |
758 PHY_M_LEDC_TX_CTRL |
759 PHY_M_LEDC_DP_CTRL);
760
761 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
762 PHY_M_LED_MO_RX(MO_LED_OFF) |
763 (skge->speed == SPEED_100 ?
764 PHY_M_LED_MO_100(MO_LED_ON) : 0));
765 break;
766 case LED_MODE_TST:
767 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
768 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
769 PHY_M_LED_MO_DUP(MO_LED_ON) |
770 PHY_M_LED_MO_10(MO_LED_ON) |
771 PHY_M_LED_MO_100(MO_LED_ON) |
772 PHY_M_LED_MO_1000(MO_LED_ON) |
773 PHY_M_LED_MO_RX(MO_LED_ON));
774 }
775 }
776 spin_unlock_bh(&hw->phy_lock);
777 }
778
779 /* blink LED's for finding board */
780 static int skge_phys_id(struct net_device *dev, u32 data)
781 {
782 struct skge_port *skge = netdev_priv(dev);
783 unsigned long ms;
784 enum led_mode mode = LED_MODE_TST;
785
786 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
787 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
788 else
789 ms = data * 1000;
790
791 while (ms > 0) {
792 skge_led(skge, mode);
793 mode ^= LED_MODE_TST;
794
795 if (msleep_interruptible(BLINK_MS))
796 break;
797 ms -= BLINK_MS;
798 }
799
800 /* back to regular LED state */
801 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
802
803 return 0;
804 }
805
806 static int skge_get_eeprom_len(struct net_device *dev)
807 {
808 struct skge_port *skge = netdev_priv(dev);
809 u32 reg2;
810
811 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
812 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
813 }
814
815 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
816 {
817 u32 val;
818
819 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
820
821 do {
822 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
823 } while (!(offset & PCI_VPD_ADDR_F));
824
825 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
826 return val;
827 }
828
829 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
830 {
831 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
832 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
833 offset | PCI_VPD_ADDR_F);
834
835 do {
836 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
837 } while (offset & PCI_VPD_ADDR_F);
838 }
839
840 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
841 u8 *data)
842 {
843 struct skge_port *skge = netdev_priv(dev);
844 struct pci_dev *pdev = skge->hw->pdev;
845 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
846 int length = eeprom->len;
847 u16 offset = eeprom->offset;
848
849 if (!cap)
850 return -EINVAL;
851
852 eeprom->magic = SKGE_EEPROM_MAGIC;
853
854 while (length > 0) {
855 u32 val = skge_vpd_read(pdev, cap, offset);
856 int n = min_t(int, length, sizeof(val));
857
858 memcpy(data, &val, n);
859 length -= n;
860 data += n;
861 offset += n;
862 }
863 return 0;
864 }
865
866 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
867 u8 *data)
868 {
869 struct skge_port *skge = netdev_priv(dev);
870 struct pci_dev *pdev = skge->hw->pdev;
871 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
872 int length = eeprom->len;
873 u16 offset = eeprom->offset;
874
875 if (!cap)
876 return -EINVAL;
877
878 if (eeprom->magic != SKGE_EEPROM_MAGIC)
879 return -EINVAL;
880
881 while (length > 0) {
882 u32 val;
883 int n = min_t(int, length, sizeof(val));
884
885 if (n < sizeof(val))
886 val = skge_vpd_read(pdev, cap, offset);
887 memcpy(&val, data, n);
888
889 skge_vpd_write(pdev, cap, offset, val);
890
891 length -= n;
892 data += n;
893 offset += n;
894 }
895 return 0;
896 }
897
898 static const struct ethtool_ops skge_ethtool_ops = {
899 .get_settings = skge_get_settings,
900 .set_settings = skge_set_settings,
901 .get_drvinfo = skge_get_drvinfo,
902 .get_regs_len = skge_get_regs_len,
903 .get_regs = skge_get_regs,
904 .get_wol = skge_get_wol,
905 .set_wol = skge_set_wol,
906 .get_msglevel = skge_get_msglevel,
907 .set_msglevel = skge_set_msglevel,
908 .nway_reset = skge_nway_reset,
909 .get_link = ethtool_op_get_link,
910 .get_eeprom_len = skge_get_eeprom_len,
911 .get_eeprom = skge_get_eeprom,
912 .set_eeprom = skge_set_eeprom,
913 .get_ringparam = skge_get_ring_param,
914 .set_ringparam = skge_set_ring_param,
915 .get_pauseparam = skge_get_pauseparam,
916 .set_pauseparam = skge_set_pauseparam,
917 .get_coalesce = skge_get_coalesce,
918 .set_coalesce = skge_set_coalesce,
919 .set_sg = skge_set_sg,
920 .set_tx_csum = skge_set_tx_csum,
921 .get_rx_csum = skge_get_rx_csum,
922 .set_rx_csum = skge_set_rx_csum,
923 .get_strings = skge_get_strings,
924 .phys_id = skge_phys_id,
925 .get_sset_count = skge_get_sset_count,
926 .get_ethtool_stats = skge_get_ethtool_stats,
927 };
928
929 /*
930 * Allocate ring elements and chain them together
931 * One-to-one association of board descriptors with ring elements
932 */
933 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
934 {
935 struct skge_tx_desc *d;
936 struct skge_element *e;
937 int i;
938
939 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
940 if (!ring->start)
941 return -ENOMEM;
942
943 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
944 e->desc = d;
945 if (i == ring->count - 1) {
946 e->next = ring->start;
947 d->next_offset = base;
948 } else {
949 e->next = e + 1;
950 d->next_offset = base + (i+1) * sizeof(*d);
951 }
952 }
953 ring->to_use = ring->to_clean = ring->start;
954
955 return 0;
956 }
957
958 /* Allocate and setup a new buffer for receiving */
959 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
960 struct sk_buff *skb, unsigned int bufsize)
961 {
962 struct skge_rx_desc *rd = e->desc;
963 u64 map;
964
965 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
966 PCI_DMA_FROMDEVICE);
967
968 rd->dma_lo = map;
969 rd->dma_hi = map >> 32;
970 e->skb = skb;
971 rd->csum1_start = ETH_HLEN;
972 rd->csum2_start = ETH_HLEN;
973 rd->csum1 = 0;
974 rd->csum2 = 0;
975
976 wmb();
977
978 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
979 pci_unmap_addr_set(e, mapaddr, map);
980 pci_unmap_len_set(e, maplen, bufsize);
981 }
982
983 /* Resume receiving using existing skb,
984 * Note: DMA address is not changed by chip.
985 * MTU not changed while receiver active.
986 */
987 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
988 {
989 struct skge_rx_desc *rd = e->desc;
990
991 rd->csum2 = 0;
992 rd->csum2_start = ETH_HLEN;
993
994 wmb();
995
996 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
997 }
998
999
1000 /* Free all buffers in receive ring, assumes receiver stopped */
1001 static void skge_rx_clean(struct skge_port *skge)
1002 {
1003 struct skge_hw *hw = skge->hw;
1004 struct skge_ring *ring = &skge->rx_ring;
1005 struct skge_element *e;
1006
1007 e = ring->start;
1008 do {
1009 struct skge_rx_desc *rd = e->desc;
1010 rd->control = 0;
1011 if (e->skb) {
1012 pci_unmap_single(hw->pdev,
1013 pci_unmap_addr(e, mapaddr),
1014 pci_unmap_len(e, maplen),
1015 PCI_DMA_FROMDEVICE);
1016 dev_kfree_skb(e->skb);
1017 e->skb = NULL;
1018 }
1019 } while ((e = e->next) != ring->start);
1020 }
1021
1022
1023 /* Allocate buffers for receive ring
1024 * For receive: to_clean is next received frame.
1025 */
1026 static int skge_rx_fill(struct net_device *dev)
1027 {
1028 struct skge_port *skge = netdev_priv(dev);
1029 struct skge_ring *ring = &skge->rx_ring;
1030 struct skge_element *e;
1031
1032 e = ring->start;
1033 do {
1034 struct sk_buff *skb;
1035
1036 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1037 GFP_KERNEL);
1038 if (!skb)
1039 return -ENOMEM;
1040
1041 skb_reserve(skb, NET_IP_ALIGN);
1042 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1043 } while ( (e = e->next) != ring->start);
1044
1045 ring->to_clean = ring->start;
1046 return 0;
1047 }
1048
1049 static const char *skge_pause(enum pause_status status)
1050 {
1051 switch(status) {
1052 case FLOW_STAT_NONE:
1053 return "none";
1054 case FLOW_STAT_REM_SEND:
1055 return "rx only";
1056 case FLOW_STAT_LOC_SEND:
1057 return "tx_only";
1058 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1059 return "both";
1060 default:
1061 return "indeterminated";
1062 }
1063 }
1064
1065
1066 static void skge_link_up(struct skge_port *skge)
1067 {
1068 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1069 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1070
1071 netif_carrier_on(skge->netdev);
1072 netif_wake_queue(skge->netdev);
1073
1074 if (netif_msg_link(skge)) {
1075 printk(KERN_INFO PFX
1076 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1077 skge->netdev->name, skge->speed,
1078 skge->duplex == DUPLEX_FULL ? "full" : "half",
1079 skge_pause(skge->flow_status));
1080 }
1081 }
1082
1083 static void skge_link_down(struct skge_port *skge)
1084 {
1085 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1086 netif_carrier_off(skge->netdev);
1087 netif_stop_queue(skge->netdev);
1088
1089 if (netif_msg_link(skge))
1090 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1091 }
1092
1093
1094 static void xm_link_down(struct skge_hw *hw, int port)
1095 {
1096 struct net_device *dev = hw->dev[port];
1097 struct skge_port *skge = netdev_priv(dev);
1098
1099 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1100
1101 if (netif_carrier_ok(dev))
1102 skge_link_down(skge);
1103 }
1104
1105 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1106 {
1107 int i;
1108
1109 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1110 *val = xm_read16(hw, port, XM_PHY_DATA);
1111
1112 if (hw->phy_type == SK_PHY_XMAC)
1113 goto ready;
1114
1115 for (i = 0; i < PHY_RETRIES; i++) {
1116 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1117 goto ready;
1118 udelay(1);
1119 }
1120
1121 return -ETIMEDOUT;
1122 ready:
1123 *val = xm_read16(hw, port, XM_PHY_DATA);
1124
1125 return 0;
1126 }
1127
1128 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1129 {
1130 u16 v = 0;
1131 if (__xm_phy_read(hw, port, reg, &v))
1132 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1133 hw->dev[port]->name);
1134 return v;
1135 }
1136
1137 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1138 {
1139 int i;
1140
1141 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1142 for (i = 0; i < PHY_RETRIES; i++) {
1143 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1144 goto ready;
1145 udelay(1);
1146 }
1147 return -EIO;
1148
1149 ready:
1150 xm_write16(hw, port, XM_PHY_DATA, val);
1151 for (i = 0; i < PHY_RETRIES; i++) {
1152 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1153 return 0;
1154 udelay(1);
1155 }
1156 return -ETIMEDOUT;
1157 }
1158
1159 static void genesis_init(struct skge_hw *hw)
1160 {
1161 /* set blink source counter */
1162 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1163 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1164
1165 /* configure mac arbiter */
1166 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1167
1168 /* configure mac arbiter timeout values */
1169 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1170 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1171 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1172 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1173
1174 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1175 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1176 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1177 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1178
1179 /* configure packet arbiter timeout */
1180 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1181 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1182 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1183 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1184 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1185 }
1186
1187 static void genesis_reset(struct skge_hw *hw, int port)
1188 {
1189 const u8 zero[8] = { 0 };
1190 u32 reg;
1191
1192 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1193
1194 /* reset the statistics module */
1195 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1196 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1197 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1198 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1199 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1200
1201 /* disable Broadcom PHY IRQ */
1202 if (hw->phy_type == SK_PHY_BCOM)
1203 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1204
1205 xm_outhash(hw, port, XM_HSM, zero);
1206
1207 /* Flush TX and RX fifo */
1208 reg = xm_read32(hw, port, XM_MODE);
1209 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1210 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1211 }
1212
1213
1214 /* Convert mode to MII values */
1215 static const u16 phy_pause_map[] = {
1216 [FLOW_MODE_NONE] = 0,
1217 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1218 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1219 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1220 };
1221
1222 /* special defines for FIBER (88E1011S only) */
1223 static const u16 fiber_pause_map[] = {
1224 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1225 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1226 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1227 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1228 };
1229
1230
1231 /* Check status of Broadcom phy link */
1232 static void bcom_check_link(struct skge_hw *hw, int port)
1233 {
1234 struct net_device *dev = hw->dev[port];
1235 struct skge_port *skge = netdev_priv(dev);
1236 u16 status;
1237
1238 /* read twice because of latch */
1239 xm_phy_read(hw, port, PHY_BCOM_STAT);
1240 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1241
1242 if ((status & PHY_ST_LSYNC) == 0) {
1243 xm_link_down(hw, port);
1244 return;
1245 }
1246
1247 if (skge->autoneg == AUTONEG_ENABLE) {
1248 u16 lpa, aux;
1249
1250 if (!(status & PHY_ST_AN_OVER))
1251 return;
1252
1253 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1254 if (lpa & PHY_B_AN_RF) {
1255 printk(KERN_NOTICE PFX "%s: remote fault\n",
1256 dev->name);
1257 return;
1258 }
1259
1260 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1261
1262 /* Check Duplex mismatch */
1263 switch (aux & PHY_B_AS_AN_RES_MSK) {
1264 case PHY_B_RES_1000FD:
1265 skge->duplex = DUPLEX_FULL;
1266 break;
1267 case PHY_B_RES_1000HD:
1268 skge->duplex = DUPLEX_HALF;
1269 break;
1270 default:
1271 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1272 dev->name);
1273 return;
1274 }
1275
1276 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1277 switch (aux & PHY_B_AS_PAUSE_MSK) {
1278 case PHY_B_AS_PAUSE_MSK:
1279 skge->flow_status = FLOW_STAT_SYMMETRIC;
1280 break;
1281 case PHY_B_AS_PRR:
1282 skge->flow_status = FLOW_STAT_REM_SEND;
1283 break;
1284 case PHY_B_AS_PRT:
1285 skge->flow_status = FLOW_STAT_LOC_SEND;
1286 break;
1287 default:
1288 skge->flow_status = FLOW_STAT_NONE;
1289 }
1290 skge->speed = SPEED_1000;
1291 }
1292
1293 if (!netif_carrier_ok(dev))
1294 genesis_link_up(skge);
1295 }
1296
1297 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1298 * Phy on for 100 or 10Mbit operation
1299 */
1300 static void bcom_phy_init(struct skge_port *skge)
1301 {
1302 struct skge_hw *hw = skge->hw;
1303 int port = skge->port;
1304 int i;
1305 u16 id1, r, ext, ctl;
1306
1307 /* magic workaround patterns for Broadcom */
1308 static const struct {
1309 u16 reg;
1310 u16 val;
1311 } A1hack[] = {
1312 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1313 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1314 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1315 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1316 }, C0hack[] = {
1317 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1318 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1319 };
1320
1321 /* read Id from external PHY (all have the same address) */
1322 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1323
1324 /* Optimize MDIO transfer by suppressing preamble. */
1325 r = xm_read16(hw, port, XM_MMU_CMD);
1326 r |= XM_MMU_NO_PRE;
1327 xm_write16(hw, port, XM_MMU_CMD,r);
1328
1329 switch (id1) {
1330 case PHY_BCOM_ID1_C0:
1331 /*
1332 * Workaround BCOM Errata for the C0 type.
1333 * Write magic patterns to reserved registers.
1334 */
1335 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1336 xm_phy_write(hw, port,
1337 C0hack[i].reg, C0hack[i].val);
1338
1339 break;
1340 case PHY_BCOM_ID1_A1:
1341 /*
1342 * Workaround BCOM Errata for the A1 type.
1343 * Write magic patterns to reserved registers.
1344 */
1345 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1346 xm_phy_write(hw, port,
1347 A1hack[i].reg, A1hack[i].val);
1348 break;
1349 }
1350
1351 /*
1352 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1353 * Disable Power Management after reset.
1354 */
1355 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1356 r |= PHY_B_AC_DIS_PM;
1357 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1358
1359 /* Dummy read */
1360 xm_read16(hw, port, XM_ISRC);
1361
1362 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1363 ctl = PHY_CT_SP1000; /* always 1000mbit */
1364
1365 if (skge->autoneg == AUTONEG_ENABLE) {
1366 /*
1367 * Workaround BCOM Errata #1 for the C5 type.
1368 * 1000Base-T Link Acquisition Failure in Slave Mode
1369 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1370 */
1371 u16 adv = PHY_B_1000C_RD;
1372 if (skge->advertising & ADVERTISED_1000baseT_Half)
1373 adv |= PHY_B_1000C_AHD;
1374 if (skge->advertising & ADVERTISED_1000baseT_Full)
1375 adv |= PHY_B_1000C_AFD;
1376 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1377
1378 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1379 } else {
1380 if (skge->duplex == DUPLEX_FULL)
1381 ctl |= PHY_CT_DUP_MD;
1382 /* Force to slave */
1383 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1384 }
1385
1386 /* Set autonegotiation pause parameters */
1387 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1388 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1389
1390 /* Handle Jumbo frames */
1391 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1392 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1393 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1394
1395 ext |= PHY_B_PEC_HIGH_LA;
1396
1397 }
1398
1399 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1400 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1401
1402 /* Use link status change interrupt */
1403 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1404 }
1405
1406 static void xm_phy_init(struct skge_port *skge)
1407 {
1408 struct skge_hw *hw = skge->hw;
1409 int port = skge->port;
1410 u16 ctrl = 0;
1411
1412 if (skge->autoneg == AUTONEG_ENABLE) {
1413 if (skge->advertising & ADVERTISED_1000baseT_Half)
1414 ctrl |= PHY_X_AN_HD;
1415 if (skge->advertising & ADVERTISED_1000baseT_Full)
1416 ctrl |= PHY_X_AN_FD;
1417
1418 ctrl |= fiber_pause_map[skge->flow_control];
1419
1420 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1421
1422 /* Restart Auto-negotiation */
1423 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1424 } else {
1425 /* Set DuplexMode in Config register */
1426 if (skge->duplex == DUPLEX_FULL)
1427 ctrl |= PHY_CT_DUP_MD;
1428 /*
1429 * Do NOT enable Auto-negotiation here. This would hold
1430 * the link down because no IDLEs are transmitted
1431 */
1432 }
1433
1434 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1435
1436 /* Poll PHY for status changes */
1437 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1438 }
1439
1440 static int xm_check_link(struct net_device *dev)
1441 {
1442 struct skge_port *skge = netdev_priv(dev);
1443 struct skge_hw *hw = skge->hw;
1444 int port = skge->port;
1445 u16 status;
1446
1447 /* read twice because of latch */
1448 xm_phy_read(hw, port, PHY_XMAC_STAT);
1449 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1450
1451 if ((status & PHY_ST_LSYNC) == 0) {
1452 xm_link_down(hw, port);
1453 return 0;
1454 }
1455
1456 if (skge->autoneg == AUTONEG_ENABLE) {
1457 u16 lpa, res;
1458
1459 if (!(status & PHY_ST_AN_OVER))
1460 return 0;
1461
1462 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1463 if (lpa & PHY_B_AN_RF) {
1464 printk(KERN_NOTICE PFX "%s: remote fault\n",
1465 dev->name);
1466 return 0;
1467 }
1468
1469 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1470
1471 /* Check Duplex mismatch */
1472 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1473 case PHY_X_RS_FD:
1474 skge->duplex = DUPLEX_FULL;
1475 break;
1476 case PHY_X_RS_HD:
1477 skge->duplex = DUPLEX_HALF;
1478 break;
1479 default:
1480 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1481 dev->name);
1482 return 0;
1483 }
1484
1485 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1486 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1487 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1488 (lpa & PHY_X_P_SYM_MD))
1489 skge->flow_status = FLOW_STAT_SYMMETRIC;
1490 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1491 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1492 /* Enable PAUSE receive, disable PAUSE transmit */
1493 skge->flow_status = FLOW_STAT_REM_SEND;
1494 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1495 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1496 /* Disable PAUSE receive, enable PAUSE transmit */
1497 skge->flow_status = FLOW_STAT_LOC_SEND;
1498 else
1499 skge->flow_status = FLOW_STAT_NONE;
1500
1501 skge->speed = SPEED_1000;
1502 }
1503
1504 if (!netif_carrier_ok(dev))
1505 genesis_link_up(skge);
1506 return 1;
1507 }
1508
1509 /* Poll to check for link coming up.
1510 *
1511 * Since internal PHY is wired to a level triggered pin, can't
1512 * get an interrupt when carrier is detected, need to poll for
1513 * link coming up.
1514 */
1515 static void xm_link_timer(unsigned long arg)
1516 {
1517 struct skge_port *skge = (struct skge_port *) arg;
1518 struct net_device *dev = skge->netdev;
1519 struct skge_hw *hw = skge->hw;
1520 int port = skge->port;
1521 int i;
1522 unsigned long flags;
1523
1524 if (!netif_running(dev))
1525 return;
1526
1527 spin_lock_irqsave(&hw->phy_lock, flags);
1528
1529 /*
1530 * Verify that the link by checking GPIO register three times.
1531 * This pin has the signal from the link_sync pin connected to it.
1532 */
1533 for (i = 0; i < 3; i++) {
1534 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1535 goto link_down;
1536 }
1537
1538 /* Re-enable interrupt to detect link down */
1539 if (xm_check_link(dev)) {
1540 u16 msk = xm_read16(hw, port, XM_IMSK);
1541 msk &= ~XM_IS_INP_ASS;
1542 xm_write16(hw, port, XM_IMSK, msk);
1543 xm_read16(hw, port, XM_ISRC);
1544 } else {
1545 link_down:
1546 mod_timer(&skge->link_timer,
1547 round_jiffies(jiffies + LINK_HZ));
1548 }
1549 spin_unlock_irqrestore(&hw->phy_lock, flags);
1550 }
1551
1552 static void genesis_mac_init(struct skge_hw *hw, int port)
1553 {
1554 struct net_device *dev = hw->dev[port];
1555 struct skge_port *skge = netdev_priv(dev);
1556 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1557 int i;
1558 u32 r;
1559 const u8 zero[6] = { 0 };
1560
1561 for (i = 0; i < 10; i++) {
1562 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1563 MFF_SET_MAC_RST);
1564 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1565 goto reset_ok;
1566 udelay(1);
1567 }
1568
1569 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1570
1571 reset_ok:
1572 /* Unreset the XMAC. */
1573 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1574
1575 /*
1576 * Perform additional initialization for external PHYs,
1577 * namely for the 1000baseTX cards that use the XMAC's
1578 * GMII mode.
1579 */
1580 if (hw->phy_type != SK_PHY_XMAC) {
1581 /* Take external Phy out of reset */
1582 r = skge_read32(hw, B2_GP_IO);
1583 if (port == 0)
1584 r |= GP_DIR_0|GP_IO_0;
1585 else
1586 r |= GP_DIR_2|GP_IO_2;
1587
1588 skge_write32(hw, B2_GP_IO, r);
1589
1590 /* Enable GMII interface */
1591 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1592 }
1593
1594
1595 switch(hw->phy_type) {
1596 case SK_PHY_XMAC:
1597 xm_phy_init(skge);
1598 break;
1599 case SK_PHY_BCOM:
1600 bcom_phy_init(skge);
1601 bcom_check_link(hw, port);
1602 }
1603
1604 /* Set Station Address */
1605 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1606
1607 /* We don't use match addresses so clear */
1608 for (i = 1; i < 16; i++)
1609 xm_outaddr(hw, port, XM_EXM(i), zero);
1610
1611 /* Clear MIB counters */
1612 xm_write16(hw, port, XM_STAT_CMD,
1613 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1614 /* Clear two times according to Errata #3 */
1615 xm_write16(hw, port, XM_STAT_CMD,
1616 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1617
1618 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1619 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1620
1621 /* We don't need the FCS appended to the packet. */
1622 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1623 if (jumbo)
1624 r |= XM_RX_BIG_PK_OK;
1625
1626 if (skge->duplex == DUPLEX_HALF) {
1627 /*
1628 * If in manual half duplex mode the other side might be in
1629 * full duplex mode, so ignore if a carrier extension is not seen
1630 * on frames received
1631 */
1632 r |= XM_RX_DIS_CEXT;
1633 }
1634 xm_write16(hw, port, XM_RX_CMD, r);
1635
1636
1637 /* We want short frames padded to 60 bytes. */
1638 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1639
1640 /*
1641 * Bump up the transmit threshold. This helps hold off transmit
1642 * underruns when we're blasting traffic from both ports at once.
1643 */
1644 xm_write16(hw, port, XM_TX_THR, 512);
1645
1646 /*
1647 * Enable the reception of all error frames. This is is
1648 * a necessary evil due to the design of the XMAC. The
1649 * XMAC's receive FIFO is only 8K in size, however jumbo
1650 * frames can be up to 9000 bytes in length. When bad
1651 * frame filtering is enabled, the XMAC's RX FIFO operates
1652 * in 'store and forward' mode. For this to work, the
1653 * entire frame has to fit into the FIFO, but that means
1654 * that jumbo frames larger than 8192 bytes will be
1655 * truncated. Disabling all bad frame filtering causes
1656 * the RX FIFO to operate in streaming mode, in which
1657 * case the XMAC will start transferring frames out of the
1658 * RX FIFO as soon as the FIFO threshold is reached.
1659 */
1660 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1661
1662
1663 /*
1664 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1665 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1666 * and 'Octets Rx OK Hi Cnt Ov'.
1667 */
1668 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1669
1670 /*
1671 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1672 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1673 * and 'Octets Tx OK Hi Cnt Ov'.
1674 */
1675 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1676
1677 /* Configure MAC arbiter */
1678 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1679
1680 /* configure timeout values */
1681 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1682 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1683 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1684 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1685
1686 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1687 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1688 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1689 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1690
1691 /* Configure Rx MAC FIFO */
1692 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1693 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1694 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1695
1696 /* Configure Tx MAC FIFO */
1697 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1698 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1699 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1700
1701 if (jumbo) {
1702 /* Enable frame flushing if jumbo frames used */
1703 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1704 } else {
1705 /* enable timeout timers if normal frames */
1706 skge_write16(hw, B3_PA_CTRL,
1707 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1708 }
1709 }
1710
1711 static void genesis_stop(struct skge_port *skge)
1712 {
1713 struct skge_hw *hw = skge->hw;
1714 int port = skge->port;
1715 unsigned retries = 1000;
1716 u16 cmd;
1717
1718 /* Disable Tx and Rx */
1719 cmd = xm_read16(hw, port, XM_MMU_CMD);
1720 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1721 xm_write16(hw, port, XM_MMU_CMD, cmd);
1722
1723 genesis_reset(hw, port);
1724
1725 /* Clear Tx packet arbiter timeout IRQ */
1726 skge_write16(hw, B3_PA_CTRL,
1727 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1728
1729 /* Reset the MAC */
1730 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1731 do {
1732 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1733 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1734 break;
1735 } while (--retries > 0);
1736
1737 /* For external PHYs there must be special handling */
1738 if (hw->phy_type != SK_PHY_XMAC) {
1739 u32 reg = skge_read32(hw, B2_GP_IO);
1740 if (port == 0) {
1741 reg |= GP_DIR_0;
1742 reg &= ~GP_IO_0;
1743 } else {
1744 reg |= GP_DIR_2;
1745 reg &= ~GP_IO_2;
1746 }
1747 skge_write32(hw, B2_GP_IO, reg);
1748 skge_read32(hw, B2_GP_IO);
1749 }
1750
1751 xm_write16(hw, port, XM_MMU_CMD,
1752 xm_read16(hw, port, XM_MMU_CMD)
1753 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1754
1755 xm_read16(hw, port, XM_MMU_CMD);
1756 }
1757
1758
1759 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1760 {
1761 struct skge_hw *hw = skge->hw;
1762 int port = skge->port;
1763 int i;
1764 unsigned long timeout = jiffies + HZ;
1765
1766 xm_write16(hw, port,
1767 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1768
1769 /* wait for update to complete */
1770 while (xm_read16(hw, port, XM_STAT_CMD)
1771 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1772 if (time_after(jiffies, timeout))
1773 break;
1774 udelay(10);
1775 }
1776
1777 /* special case for 64 bit octet counter */
1778 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1779 | xm_read32(hw, port, XM_TXO_OK_LO);
1780 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1781 | xm_read32(hw, port, XM_RXO_OK_LO);
1782
1783 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1784 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1785 }
1786
1787 static void genesis_mac_intr(struct skge_hw *hw, int port)
1788 {
1789 struct net_device *dev = hw->dev[port];
1790 struct skge_port *skge = netdev_priv(dev);
1791 u16 status = xm_read16(hw, port, XM_ISRC);
1792
1793 if (netif_msg_intr(skge))
1794 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1795 dev->name, status);
1796
1797 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1798 xm_link_down(hw, port);
1799 mod_timer(&skge->link_timer, jiffies + 1);
1800 }
1801
1802 if (status & XM_IS_TXF_UR) {
1803 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1804 ++dev->stats.tx_fifo_errors;
1805 }
1806 }
1807
1808 static void genesis_link_up(struct skge_port *skge)
1809 {
1810 struct skge_hw *hw = skge->hw;
1811 int port = skge->port;
1812 u16 cmd, msk;
1813 u32 mode;
1814
1815 cmd = xm_read16(hw, port, XM_MMU_CMD);
1816
1817 /*
1818 * enabling pause frame reception is required for 1000BT
1819 * because the XMAC is not reset if the link is going down
1820 */
1821 if (skge->flow_status == FLOW_STAT_NONE ||
1822 skge->flow_status == FLOW_STAT_LOC_SEND)
1823 /* Disable Pause Frame Reception */
1824 cmd |= XM_MMU_IGN_PF;
1825 else
1826 /* Enable Pause Frame Reception */
1827 cmd &= ~XM_MMU_IGN_PF;
1828
1829 xm_write16(hw, port, XM_MMU_CMD, cmd);
1830
1831 mode = xm_read32(hw, port, XM_MODE);
1832 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1833 skge->flow_status == FLOW_STAT_LOC_SEND) {
1834 /*
1835 * Configure Pause Frame Generation
1836 * Use internal and external Pause Frame Generation.
1837 * Sending pause frames is edge triggered.
1838 * Send a Pause frame with the maximum pause time if
1839 * internal oder external FIFO full condition occurs.
1840 * Send a zero pause time frame to re-start transmission.
1841 */
1842 /* XM_PAUSE_DA = '010000C28001' (default) */
1843 /* XM_MAC_PTIME = 0xffff (maximum) */
1844 /* remember this value is defined in big endian (!) */
1845 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1846
1847 mode |= XM_PAUSE_MODE;
1848 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1849 } else {
1850 /*
1851 * disable pause frame generation is required for 1000BT
1852 * because the XMAC is not reset if the link is going down
1853 */
1854 /* Disable Pause Mode in Mode Register */
1855 mode &= ~XM_PAUSE_MODE;
1856
1857 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1858 }
1859
1860 xm_write32(hw, port, XM_MODE, mode);
1861
1862 /* Turn on detection of Tx underrun */
1863 msk = xm_read16(hw, port, XM_IMSK);
1864 msk &= ~XM_IS_TXF_UR;
1865 xm_write16(hw, port, XM_IMSK, msk);
1866
1867 xm_read16(hw, port, XM_ISRC);
1868
1869 /* get MMU Command Reg. */
1870 cmd = xm_read16(hw, port, XM_MMU_CMD);
1871 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1872 cmd |= XM_MMU_GMII_FD;
1873
1874 /*
1875 * Workaround BCOM Errata (#10523) for all BCom Phys
1876 * Enable Power Management after link up
1877 */
1878 if (hw->phy_type == SK_PHY_BCOM) {
1879 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1880 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1881 & ~PHY_B_AC_DIS_PM);
1882 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1883 }
1884
1885 /* enable Rx/Tx */
1886 xm_write16(hw, port, XM_MMU_CMD,
1887 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1888 skge_link_up(skge);
1889 }
1890
1891
1892 static inline void bcom_phy_intr(struct skge_port *skge)
1893 {
1894 struct skge_hw *hw = skge->hw;
1895 int port = skge->port;
1896 u16 isrc;
1897
1898 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1899 if (netif_msg_intr(skge))
1900 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1901 skge->netdev->name, isrc);
1902
1903 if (isrc & PHY_B_IS_PSE)
1904 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1905 hw->dev[port]->name);
1906
1907 /* Workaround BCom Errata:
1908 * enable and disable loopback mode if "NO HCD" occurs.
1909 */
1910 if (isrc & PHY_B_IS_NO_HDCL) {
1911 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1912 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1913 ctrl | PHY_CT_LOOP);
1914 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1915 ctrl & ~PHY_CT_LOOP);
1916 }
1917
1918 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1919 bcom_check_link(hw, port);
1920
1921 }
1922
1923 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1924 {
1925 int i;
1926
1927 gma_write16(hw, port, GM_SMI_DATA, val);
1928 gma_write16(hw, port, GM_SMI_CTRL,
1929 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1930 for (i = 0; i < PHY_RETRIES; i++) {
1931 udelay(1);
1932
1933 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1934 return 0;
1935 }
1936
1937 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1938 hw->dev[port]->name);
1939 return -EIO;
1940 }
1941
1942 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1943 {
1944 int i;
1945
1946 gma_write16(hw, port, GM_SMI_CTRL,
1947 GM_SMI_CT_PHY_AD(hw->phy_addr)
1948 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1949
1950 for (i = 0; i < PHY_RETRIES; i++) {
1951 udelay(1);
1952 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1953 goto ready;
1954 }
1955
1956 return -ETIMEDOUT;
1957 ready:
1958 *val = gma_read16(hw, port, GM_SMI_DATA);
1959 return 0;
1960 }
1961
1962 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1963 {
1964 u16 v = 0;
1965 if (__gm_phy_read(hw, port, reg, &v))
1966 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1967 hw->dev[port]->name);
1968 return v;
1969 }
1970
1971 /* Marvell Phy Initialization */
1972 static void yukon_init(struct skge_hw *hw, int port)
1973 {
1974 struct skge_port *skge = netdev_priv(hw->dev[port]);
1975 u16 ctrl, ct1000, adv;
1976
1977 if (skge->autoneg == AUTONEG_ENABLE) {
1978 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1979
1980 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1981 PHY_M_EC_MAC_S_MSK);
1982 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1983
1984 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1985
1986 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1987 }
1988
1989 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1990 if (skge->autoneg == AUTONEG_DISABLE)
1991 ctrl &= ~PHY_CT_ANE;
1992
1993 ctrl |= PHY_CT_RESET;
1994 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1995
1996 ctrl = 0;
1997 ct1000 = 0;
1998 adv = PHY_AN_CSMA;
1999
2000 if (skge->autoneg == AUTONEG_ENABLE) {
2001 if (hw->copper) {
2002 if (skge->advertising & ADVERTISED_1000baseT_Full)
2003 ct1000 |= PHY_M_1000C_AFD;
2004 if (skge->advertising & ADVERTISED_1000baseT_Half)
2005 ct1000 |= PHY_M_1000C_AHD;
2006 if (skge->advertising & ADVERTISED_100baseT_Full)
2007 adv |= PHY_M_AN_100_FD;
2008 if (skge->advertising & ADVERTISED_100baseT_Half)
2009 adv |= PHY_M_AN_100_HD;
2010 if (skge->advertising & ADVERTISED_10baseT_Full)
2011 adv |= PHY_M_AN_10_FD;
2012 if (skge->advertising & ADVERTISED_10baseT_Half)
2013 adv |= PHY_M_AN_10_HD;
2014
2015 /* Set Flow-control capabilities */
2016 adv |= phy_pause_map[skge->flow_control];
2017 } else {
2018 if (skge->advertising & ADVERTISED_1000baseT_Full)
2019 adv |= PHY_M_AN_1000X_AFD;
2020 if (skge->advertising & ADVERTISED_1000baseT_Half)
2021 adv |= PHY_M_AN_1000X_AHD;
2022
2023 adv |= fiber_pause_map[skge->flow_control];
2024 }
2025
2026 /* Restart Auto-negotiation */
2027 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2028 } else {
2029 /* forced speed/duplex settings */
2030 ct1000 = PHY_M_1000C_MSE;
2031
2032 if (skge->duplex == DUPLEX_FULL)
2033 ctrl |= PHY_CT_DUP_MD;
2034
2035 switch (skge->speed) {
2036 case SPEED_1000:
2037 ctrl |= PHY_CT_SP1000;
2038 break;
2039 case SPEED_100:
2040 ctrl |= PHY_CT_SP100;
2041 break;
2042 }
2043
2044 ctrl |= PHY_CT_RESET;
2045 }
2046
2047 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2048
2049 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2050 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2051
2052 /* Enable phy interrupt on autonegotiation complete (or link up) */
2053 if (skge->autoneg == AUTONEG_ENABLE)
2054 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2055 else
2056 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2057 }
2058
2059 static void yukon_reset(struct skge_hw *hw, int port)
2060 {
2061 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2062 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2063 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2064 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2065 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2066
2067 gma_write16(hw, port, GM_RX_CTRL,
2068 gma_read16(hw, port, GM_RX_CTRL)
2069 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2070 }
2071
2072 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2073 static int is_yukon_lite_a0(struct skge_hw *hw)
2074 {
2075 u32 reg;
2076 int ret;
2077
2078 if (hw->chip_id != CHIP_ID_YUKON)
2079 return 0;
2080
2081 reg = skge_read32(hw, B2_FAR);
2082 skge_write8(hw, B2_FAR + 3, 0xff);
2083 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2084 skge_write32(hw, B2_FAR, reg);
2085 return ret;
2086 }
2087
2088 static void yukon_mac_init(struct skge_hw *hw, int port)
2089 {
2090 struct skge_port *skge = netdev_priv(hw->dev[port]);
2091 int i;
2092 u32 reg;
2093 const u8 *addr = hw->dev[port]->dev_addr;
2094
2095 /* WA code for COMA mode -- set PHY reset */
2096 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2097 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2098 reg = skge_read32(hw, B2_GP_IO);
2099 reg |= GP_DIR_9 | GP_IO_9;
2100 skge_write32(hw, B2_GP_IO, reg);
2101 }
2102
2103 /* hard reset */
2104 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2105 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2106
2107 /* WA code for COMA mode -- clear PHY reset */
2108 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2109 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2110 reg = skge_read32(hw, B2_GP_IO);
2111 reg |= GP_DIR_9;
2112 reg &= ~GP_IO_9;
2113 skge_write32(hw, B2_GP_IO, reg);
2114 }
2115
2116 /* Set hardware config mode */
2117 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2118 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2119 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2120
2121 /* Clear GMC reset */
2122 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2123 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2124 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2125
2126 if (skge->autoneg == AUTONEG_DISABLE) {
2127 reg = GM_GPCR_AU_ALL_DIS;
2128 gma_write16(hw, port, GM_GP_CTRL,
2129 gma_read16(hw, port, GM_GP_CTRL) | reg);
2130
2131 switch (skge->speed) {
2132 case SPEED_1000:
2133 reg &= ~GM_GPCR_SPEED_100;
2134 reg |= GM_GPCR_SPEED_1000;
2135 break;
2136 case SPEED_100:
2137 reg &= ~GM_GPCR_SPEED_1000;
2138 reg |= GM_GPCR_SPEED_100;
2139 break;
2140 case SPEED_10:
2141 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2142 break;
2143 }
2144
2145 if (skge->duplex == DUPLEX_FULL)
2146 reg |= GM_GPCR_DUP_FULL;
2147 } else
2148 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2149
2150 switch (skge->flow_control) {
2151 case FLOW_MODE_NONE:
2152 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2153 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2154 break;
2155 case FLOW_MODE_LOC_SEND:
2156 /* disable Rx flow-control */
2157 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2158 break;
2159 case FLOW_MODE_SYMMETRIC:
2160 case FLOW_MODE_SYM_OR_REM:
2161 /* enable Tx & Rx flow-control */
2162 break;
2163 }
2164
2165 gma_write16(hw, port, GM_GP_CTRL, reg);
2166 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2167
2168 yukon_init(hw, port);
2169
2170 /* MIB clear */
2171 reg = gma_read16(hw, port, GM_PHY_ADDR);
2172 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2173
2174 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2175 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2176 gma_write16(hw, port, GM_PHY_ADDR, reg);
2177
2178 /* transmit control */
2179 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2180
2181 /* receive control reg: unicast + multicast + no FCS */
2182 gma_write16(hw, port, GM_RX_CTRL,
2183 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2184
2185 /* transmit flow control */
2186 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2187
2188 /* transmit parameter */
2189 gma_write16(hw, port, GM_TX_PARAM,
2190 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2191 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2192 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2193
2194 /* serial mode register */
2195 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2196 if (hw->dev[port]->mtu > 1500)
2197 reg |= GM_SMOD_JUMBO_ENA;
2198
2199 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2200
2201 /* physical address: used for pause frames */
2202 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2203 /* virtual address for data */
2204 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2205
2206 /* enable interrupt mask for counter overflows */
2207 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2208 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2209 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2210
2211 /* Initialize Mac Fifo */
2212
2213 /* Configure Rx MAC FIFO */
2214 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2215 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2216
2217 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2218 if (is_yukon_lite_a0(hw))
2219 reg &= ~GMF_RX_F_FL_ON;
2220
2221 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2222 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2223 /*
2224 * because Pause Packet Truncation in GMAC is not working
2225 * we have to increase the Flush Threshold to 64 bytes
2226 * in order to flush pause packets in Rx FIFO on Yukon-1
2227 */
2228 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2229
2230 /* Configure Tx MAC FIFO */
2231 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2232 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2233 }
2234
2235 /* Go into power down mode */
2236 static void yukon_suspend(struct skge_hw *hw, int port)
2237 {
2238 u16 ctrl;
2239
2240 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2241 ctrl |= PHY_M_PC_POL_R_DIS;
2242 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2243
2244 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2245 ctrl |= PHY_CT_RESET;
2246 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2247
2248 /* switch IEEE compatible power down mode on */
2249 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2250 ctrl |= PHY_CT_PDOWN;
2251 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2252 }
2253
2254 static void yukon_stop(struct skge_port *skge)
2255 {
2256 struct skge_hw *hw = skge->hw;
2257 int port = skge->port;
2258
2259 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2260 yukon_reset(hw, port);
2261
2262 gma_write16(hw, port, GM_GP_CTRL,
2263 gma_read16(hw, port, GM_GP_CTRL)
2264 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2265 gma_read16(hw, port, GM_GP_CTRL);
2266
2267 yukon_suspend(hw, port);
2268
2269 /* set GPHY Control reset */
2270 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2271 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2272 }
2273
2274 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2275 {
2276 struct skge_hw *hw = skge->hw;
2277 int port = skge->port;
2278 int i;
2279
2280 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2281 | gma_read32(hw, port, GM_TXO_OK_LO);
2282 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2283 | gma_read32(hw, port, GM_RXO_OK_LO);
2284
2285 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2286 data[i] = gma_read32(hw, port,
2287 skge_stats[i].gma_offset);
2288 }
2289
2290 static void yukon_mac_intr(struct skge_hw *hw, int port)
2291 {
2292 struct net_device *dev = hw->dev[port];
2293 struct skge_port *skge = netdev_priv(dev);
2294 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2295
2296 if (netif_msg_intr(skge))
2297 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2298 dev->name, status);
2299
2300 if (status & GM_IS_RX_FF_OR) {
2301 ++dev->stats.rx_fifo_errors;
2302 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2303 }
2304
2305 if (status & GM_IS_TX_FF_UR) {
2306 ++dev->stats.tx_fifo_errors;
2307 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2308 }
2309
2310 }
2311
2312 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2313 {
2314 switch (aux & PHY_M_PS_SPEED_MSK) {
2315 case PHY_M_PS_SPEED_1000:
2316 return SPEED_1000;
2317 case PHY_M_PS_SPEED_100:
2318 return SPEED_100;
2319 default:
2320 return SPEED_10;
2321 }
2322 }
2323
2324 static void yukon_link_up(struct skge_port *skge)
2325 {
2326 struct skge_hw *hw = skge->hw;
2327 int port = skge->port;
2328 u16 reg;
2329
2330 /* Enable Transmit FIFO Underrun */
2331 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2332
2333 reg = gma_read16(hw, port, GM_GP_CTRL);
2334 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2335 reg |= GM_GPCR_DUP_FULL;
2336
2337 /* enable Rx/Tx */
2338 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2339 gma_write16(hw, port, GM_GP_CTRL, reg);
2340
2341 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2342 skge_link_up(skge);
2343 }
2344
2345 static void yukon_link_down(struct skge_port *skge)
2346 {
2347 struct skge_hw *hw = skge->hw;
2348 int port = skge->port;
2349 u16 ctrl;
2350
2351 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2352 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2353 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2354
2355 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2356 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2357 ctrl |= PHY_M_AN_ASP;
2358 /* restore Asymmetric Pause bit */
2359 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2360 }
2361
2362 skge_link_down(skge);
2363
2364 yukon_init(hw, port);
2365 }
2366
2367 static void yukon_phy_intr(struct skge_port *skge)
2368 {
2369 struct skge_hw *hw = skge->hw;
2370 int port = skge->port;
2371 const char *reason = NULL;
2372 u16 istatus, phystat;
2373
2374 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2375 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2376
2377 if (netif_msg_intr(skge))
2378 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2379 skge->netdev->name, istatus, phystat);
2380
2381 if (istatus & PHY_M_IS_AN_COMPL) {
2382 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2383 & PHY_M_AN_RF) {
2384 reason = "remote fault";
2385 goto failed;
2386 }
2387
2388 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2389 reason = "master/slave fault";
2390 goto failed;
2391 }
2392
2393 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2394 reason = "speed/duplex";
2395 goto failed;
2396 }
2397
2398 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2399 ? DUPLEX_FULL : DUPLEX_HALF;
2400 skge->speed = yukon_speed(hw, phystat);
2401
2402 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2403 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2404 case PHY_M_PS_PAUSE_MSK:
2405 skge->flow_status = FLOW_STAT_SYMMETRIC;
2406 break;
2407 case PHY_M_PS_RX_P_EN:
2408 skge->flow_status = FLOW_STAT_REM_SEND;
2409 break;
2410 case PHY_M_PS_TX_P_EN:
2411 skge->flow_status = FLOW_STAT_LOC_SEND;
2412 break;
2413 default:
2414 skge->flow_status = FLOW_STAT_NONE;
2415 }
2416
2417 if (skge->flow_status == FLOW_STAT_NONE ||
2418 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2419 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2420 else
2421 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2422 yukon_link_up(skge);
2423 return;
2424 }
2425
2426 if (istatus & PHY_M_IS_LSP_CHANGE)
2427 skge->speed = yukon_speed(hw, phystat);
2428
2429 if (istatus & PHY_M_IS_DUP_CHANGE)
2430 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2431 if (istatus & PHY_M_IS_LST_CHANGE) {
2432 if (phystat & PHY_M_PS_LINK_UP)
2433 yukon_link_up(skge);
2434 else
2435 yukon_link_down(skge);
2436 }
2437 return;
2438 failed:
2439 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2440 skge->netdev->name, reason);
2441
2442 /* XXX restart autonegotiation? */
2443 }
2444
2445 static void skge_phy_reset(struct skge_port *skge)
2446 {
2447 struct skge_hw *hw = skge->hw;
2448 int port = skge->port;
2449 struct net_device *dev = hw->dev[port];
2450
2451 netif_stop_queue(skge->netdev);
2452 netif_carrier_off(skge->netdev);
2453
2454 spin_lock_bh(&hw->phy_lock);
2455 if (hw->chip_id == CHIP_ID_GENESIS) {
2456 genesis_reset(hw, port);
2457 genesis_mac_init(hw, port);
2458 } else {
2459 yukon_reset(hw, port);
2460 yukon_init(hw, port);
2461 }
2462 spin_unlock_bh(&hw->phy_lock);
2463
2464 dev->set_multicast_list(dev);
2465 }
2466
2467 /* Basic MII support */
2468 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2469 {
2470 struct mii_ioctl_data *data = if_mii(ifr);
2471 struct skge_port *skge = netdev_priv(dev);
2472 struct skge_hw *hw = skge->hw;
2473 int err = -EOPNOTSUPP;
2474
2475 if (!netif_running(dev))
2476 return -ENODEV; /* Phy still in reset */
2477
2478 switch(cmd) {
2479 case SIOCGMIIPHY:
2480 data->phy_id = hw->phy_addr;
2481
2482 /* fallthru */
2483 case SIOCGMIIREG: {
2484 u16 val = 0;
2485 spin_lock_bh(&hw->phy_lock);
2486 if (hw->chip_id == CHIP_ID_GENESIS)
2487 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2488 else
2489 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2490 spin_unlock_bh(&hw->phy_lock);
2491 data->val_out = val;
2492 break;
2493 }
2494
2495 case SIOCSMIIREG:
2496 if (!capable(CAP_NET_ADMIN))
2497 return -EPERM;
2498
2499 spin_lock_bh(&hw->phy_lock);
2500 if (hw->chip_id == CHIP_ID_GENESIS)
2501 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2502 data->val_in);
2503 else
2504 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2505 data->val_in);
2506 spin_unlock_bh(&hw->phy_lock);
2507 break;
2508 }
2509 return err;
2510 }
2511
2512 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2513 {
2514 u32 end;
2515
2516 start /= 8;
2517 len /= 8;
2518 end = start + len - 1;
2519
2520 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2521 skge_write32(hw, RB_ADDR(q, RB_START), start);
2522 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2523 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2524 skge_write32(hw, RB_ADDR(q, RB_END), end);
2525
2526 if (q == Q_R1 || q == Q_R2) {
2527 /* Set thresholds on receive queue's */
2528 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2529 start + (2*len)/3);
2530 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2531 start + (len/3));
2532 } else {
2533 /* Enable store & forward on Tx queue's because
2534 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2535 */
2536 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2537 }
2538
2539 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2540 }
2541
2542 /* Setup Bus Memory Interface */
2543 static void skge_qset(struct skge_port *skge, u16 q,
2544 const struct skge_element *e)
2545 {
2546 struct skge_hw *hw = skge->hw;
2547 u32 watermark = 0x600;
2548 u64 base = skge->dma + (e->desc - skge->mem);
2549
2550 /* optimization to reduce window on 32bit/33mhz */
2551 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2552 watermark /= 2;
2553
2554 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2555 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2556 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2557 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2558 }
2559
2560 static int skge_up(struct net_device *dev)
2561 {
2562 struct skge_port *skge = netdev_priv(dev);
2563 struct skge_hw *hw = skge->hw;
2564 int port = skge->port;
2565 u32 chunk, ram_addr;
2566 size_t rx_size, tx_size;
2567 int err;
2568
2569 if (!is_valid_ether_addr(dev->dev_addr))
2570 return -EINVAL;
2571
2572 if (netif_msg_ifup(skge))
2573 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2574
2575 if (dev->mtu > RX_BUF_SIZE)
2576 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2577 else
2578 skge->rx_buf_size = RX_BUF_SIZE;
2579
2580
2581 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2582 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2583 skge->mem_size = tx_size + rx_size;
2584 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2585 if (!skge->mem)
2586 return -ENOMEM;
2587
2588 BUG_ON(skge->dma & 7);
2589
2590 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2591 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2592 err = -EINVAL;
2593 goto free_pci_mem;
2594 }
2595
2596 memset(skge->mem, 0, skge->mem_size);
2597
2598 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2599 if (err)
2600 goto free_pci_mem;
2601
2602 err = skge_rx_fill(dev);
2603 if (err)
2604 goto free_rx_ring;
2605
2606 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2607 skge->dma + rx_size);
2608 if (err)
2609 goto free_rx_ring;
2610
2611 /* Initialize MAC */
2612 spin_lock_bh(&hw->phy_lock);
2613 if (hw->chip_id == CHIP_ID_GENESIS)
2614 genesis_mac_init(hw, port);
2615 else
2616 yukon_mac_init(hw, port);
2617 spin_unlock_bh(&hw->phy_lock);
2618
2619 /* Configure RAMbuffers - equally between ports and tx/rx */
2620 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2621 ram_addr = hw->ram_offset + 2 * chunk * port;
2622
2623 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2624 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2625
2626 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2627 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2628 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2629
2630 /* Start receiver BMU */
2631 wmb();
2632 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2633 skge_led(skge, LED_MODE_ON);
2634
2635 spin_lock_irq(&hw->hw_lock);
2636 hw->intr_mask |= portmask[port];
2637 skge_write32(hw, B0_IMSK, hw->intr_mask);
2638 spin_unlock_irq(&hw->hw_lock);
2639
2640 napi_enable(&skge->napi);
2641 return 0;
2642
2643 free_rx_ring:
2644 skge_rx_clean(skge);
2645 kfree(skge->rx_ring.start);
2646 free_pci_mem:
2647 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2648 skge->mem = NULL;
2649
2650 return err;
2651 }
2652
2653 /* stop receiver */
2654 static void skge_rx_stop(struct skge_hw *hw, int port)
2655 {
2656 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2657 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2658 RB_RST_SET|RB_DIS_OP_MD);
2659 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2660 }
2661
2662 static int skge_down(struct net_device *dev)
2663 {
2664 struct skge_port *skge = netdev_priv(dev);
2665 struct skge_hw *hw = skge->hw;
2666 int port = skge->port;
2667
2668 if (skge->mem == NULL)
2669 return 0;
2670
2671 if (netif_msg_ifdown(skge))
2672 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2673
2674 netif_stop_queue(dev);
2675
2676 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2677 del_timer_sync(&skge->link_timer);
2678
2679 napi_disable(&skge->napi);
2680 netif_carrier_off(dev);
2681
2682 spin_lock_irq(&hw->hw_lock);
2683 hw->intr_mask &= ~portmask[port];
2684 skge_write32(hw, B0_IMSK, hw->intr_mask);
2685 spin_unlock_irq(&hw->hw_lock);
2686
2687 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2688 if (hw->chip_id == CHIP_ID_GENESIS)
2689 genesis_stop(skge);
2690 else
2691 yukon_stop(skge);
2692
2693 /* Stop transmitter */
2694 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2695 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2696 RB_RST_SET|RB_DIS_OP_MD);
2697
2698
2699 /* Disable Force Sync bit and Enable Alloc bit */
2700 skge_write8(hw, SK_REG(port, TXA_CTRL),
2701 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2702
2703 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2704 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2705 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2706
2707 /* Reset PCI FIFO */
2708 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2709 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2710
2711 /* Reset the RAM Buffer async Tx queue */
2712 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2713
2714 skge_rx_stop(hw, port);
2715
2716 if (hw->chip_id == CHIP_ID_GENESIS) {
2717 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2718 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2719 } else {
2720 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2721 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2722 }
2723
2724 skge_led(skge, LED_MODE_OFF);
2725
2726 netif_tx_lock_bh(dev);
2727 skge_tx_clean(dev);
2728 netif_tx_unlock_bh(dev);
2729
2730 skge_rx_clean(skge);
2731
2732 kfree(skge->rx_ring.start);
2733 kfree(skge->tx_ring.start);
2734 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2735 skge->mem = NULL;
2736 return 0;
2737 }
2738
2739 static inline int skge_avail(const struct skge_ring *ring)
2740 {
2741 smp_mb();
2742 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2743 + (ring->to_clean - ring->to_use) - 1;
2744 }
2745
2746 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2747 {
2748 struct skge_port *skge = netdev_priv(dev);
2749 struct skge_hw *hw = skge->hw;
2750 struct skge_element *e;
2751 struct skge_tx_desc *td;
2752 int i;
2753 u32 control, len;
2754 u64 map;
2755
2756 if (skb_padto(skb, ETH_ZLEN))
2757 return NETDEV_TX_OK;
2758
2759 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2760 return NETDEV_TX_BUSY;
2761
2762 e = skge->tx_ring.to_use;
2763 td = e->desc;
2764 BUG_ON(td->control & BMU_OWN);
2765 e->skb = skb;
2766 len = skb_headlen(skb);
2767 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2768 pci_unmap_addr_set(e, mapaddr, map);
2769 pci_unmap_len_set(e, maplen, len);
2770
2771 td->dma_lo = map;
2772 td->dma_hi = map >> 32;
2773
2774 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2775 const int offset = skb_transport_offset(skb);
2776
2777 /* This seems backwards, but it is what the sk98lin
2778 * does. Looks like hardware is wrong?
2779 */
2780 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2781 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2782 control = BMU_TCP_CHECK;
2783 else
2784 control = BMU_UDP_CHECK;
2785
2786 td->csum_offs = 0;
2787 td->csum_start = offset;
2788 td->csum_write = offset + skb->csum_offset;
2789 } else
2790 control = BMU_CHECK;
2791
2792 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2793 control |= BMU_EOF| BMU_IRQ_EOF;
2794 else {
2795 struct skge_tx_desc *tf = td;
2796
2797 control |= BMU_STFWD;
2798 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2799 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2800
2801 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2802 frag->size, PCI_DMA_TODEVICE);
2803
2804 e = e->next;
2805 e->skb = skb;
2806 tf = e->desc;
2807 BUG_ON(tf->control & BMU_OWN);
2808
2809 tf->dma_lo = map;
2810 tf->dma_hi = (u64) map >> 32;
2811 pci_unmap_addr_set(e, mapaddr, map);
2812 pci_unmap_len_set(e, maplen, frag->size);
2813
2814 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2815 }
2816 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2817 }
2818 /* Make sure all the descriptors written */
2819 wmb();
2820 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2821 wmb();
2822
2823 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2824
2825 if (unlikely(netif_msg_tx_queued(skge)))
2826 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2827 dev->name, e - skge->tx_ring.start, skb->len);
2828
2829 skge->tx_ring.to_use = e->next;
2830 smp_wmb();
2831
2832 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2833 pr_debug("%s: transmit queue full\n", dev->name);
2834 netif_stop_queue(dev);
2835 }
2836
2837 dev->trans_start = jiffies;
2838
2839 return NETDEV_TX_OK;
2840 }
2841
2842
2843 /* Free resources associated with this reing element */
2844 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2845 u32 control)
2846 {
2847 struct pci_dev *pdev = skge->hw->pdev;
2848
2849 /* skb header vs. fragment */
2850 if (control & BMU_STF)
2851 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2852 pci_unmap_len(e, maplen),
2853 PCI_DMA_TODEVICE);
2854 else
2855 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2856 pci_unmap_len(e, maplen),
2857 PCI_DMA_TODEVICE);
2858
2859 if (control & BMU_EOF) {
2860 if (unlikely(netif_msg_tx_done(skge)))
2861 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2862 skge->netdev->name, e - skge->tx_ring.start);
2863
2864 dev_kfree_skb(e->skb);
2865 }
2866 }
2867
2868 /* Free all buffers in transmit ring */
2869 static void skge_tx_clean(struct net_device *dev)
2870 {
2871 struct skge_port *skge = netdev_priv(dev);
2872 struct skge_element *e;
2873
2874 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2875 struct skge_tx_desc *td = e->desc;
2876 skge_tx_free(skge, e, td->control);
2877 td->control = 0;
2878 }
2879
2880 skge->tx_ring.to_clean = e;
2881 netif_wake_queue(dev);
2882 }
2883
2884 static void skge_tx_timeout(struct net_device *dev)
2885 {
2886 struct skge_port *skge = netdev_priv(dev);
2887
2888 if (netif_msg_timer(skge))
2889 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2890
2891 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2892 skge_tx_clean(dev);
2893 }
2894
2895 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2896 {
2897 struct skge_port *skge = netdev_priv(dev);
2898 struct skge_hw *hw = skge->hw;
2899 int port = skge->port;
2900 int err;
2901 u16 ctl, reg;
2902
2903 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2904 return -EINVAL;
2905
2906 if (!netif_running(dev)) {
2907 dev->mtu = new_mtu;
2908 return 0;
2909 }
2910
2911 skge_write32(hw, B0_IMSK, 0);
2912 dev->trans_start = jiffies; /* prevent tx timeout */
2913 netif_stop_queue(dev);
2914 napi_disable(&skge->napi);
2915
2916 ctl = gma_read16(hw, port, GM_GP_CTRL);
2917 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2918
2919 skge_rx_clean(skge);
2920 skge_rx_stop(hw, port);
2921
2922 dev->mtu = new_mtu;
2923
2924 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2925 if (new_mtu > 1500)
2926 reg |= GM_SMOD_JUMBO_ENA;
2927 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2928
2929 skge_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2930
2931 err = skge_rx_fill(dev);
2932 wmb();
2933 if (!err)
2934 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2935 skge_write32(hw, B0_IMSK, hw->intr_mask);
2936
2937 if (err)
2938 dev_close(dev);
2939 else {
2940 gma_write16(hw, port, GM_GP_CTRL, ctl);
2941
2942 napi_enable(&skge->napi);
2943 netif_wake_queue(dev);
2944 }
2945
2946 return err;
2947 }
2948
2949 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2950
2951 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2952 {
2953 u32 crc, bit;
2954
2955 crc = ether_crc_le(ETH_ALEN, addr);
2956 bit = ~crc & 0x3f;
2957 filter[bit/8] |= 1 << (bit%8);
2958 }
2959
2960 static void genesis_set_multicast(struct net_device *dev)
2961 {
2962 struct skge_port *skge = netdev_priv(dev);
2963 struct skge_hw *hw = skge->hw;
2964 int port = skge->port;
2965 int i, count = dev->mc_count;
2966 struct dev_mc_list *list = dev->mc_list;
2967 u32 mode;
2968 u8 filter[8];
2969
2970 mode = xm_read32(hw, port, XM_MODE);
2971 mode |= XM_MD_ENA_HASH;
2972 if (dev->flags & IFF_PROMISC)
2973 mode |= XM_MD_ENA_PROM;
2974 else
2975 mode &= ~XM_MD_ENA_PROM;
2976
2977 if (dev->flags & IFF_ALLMULTI)
2978 memset(filter, 0xff, sizeof(filter));
2979 else {
2980 memset(filter, 0, sizeof(filter));
2981
2982 if (skge->flow_status == FLOW_STAT_REM_SEND
2983 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2984 genesis_add_filter(filter, pause_mc_addr);
2985
2986 for (i = 0; list && i < count; i++, list = list->next)
2987 genesis_add_filter(filter, list->dmi_addr);
2988 }
2989
2990 xm_write32(hw, port, XM_MODE, mode);
2991 xm_outhash(hw, port, XM_HSM, filter);
2992 }
2993
2994 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2995 {
2996 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2997 filter[bit/8] |= 1 << (bit%8);
2998 }
2999
3000 static void yukon_set_multicast(struct net_device *dev)
3001 {
3002 struct skge_port *skge = netdev_priv(dev);
3003 struct skge_hw *hw = skge->hw;
3004 int port = skge->port;
3005 struct dev_mc_list *list = dev->mc_list;
3006 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
3007 || skge->flow_status == FLOW_STAT_SYMMETRIC);
3008 u16 reg;
3009 u8 filter[8];
3010
3011 memset(filter, 0, sizeof(filter));
3012
3013 reg = gma_read16(hw, port, GM_RX_CTRL);
3014 reg |= GM_RXCR_UCF_ENA;
3015
3016 if (dev->flags & IFF_PROMISC) /* promiscuous */
3017 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3018 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
3019 memset(filter, 0xff, sizeof(filter));
3020 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
3021 reg &= ~GM_RXCR_MCF_ENA;
3022 else {
3023 int i;
3024 reg |= GM_RXCR_MCF_ENA;
3025
3026 if (rx_pause)
3027 yukon_add_filter(filter, pause_mc_addr);
3028
3029 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3030 yukon_add_filter(filter, list->dmi_addr);
3031 }
3032
3033
3034 gma_write16(hw, port, GM_MC_ADDR_H1,
3035 (u16)filter[0] | ((u16)filter[1] << 8));
3036 gma_write16(hw, port, GM_MC_ADDR_H2,
3037 (u16)filter[2] | ((u16)filter[3] << 8));
3038 gma_write16(hw, port, GM_MC_ADDR_H3,
3039 (u16)filter[4] | ((u16)filter[5] << 8));
3040 gma_write16(hw, port, GM_MC_ADDR_H4,
3041 (u16)filter[6] | ((u16)filter[7] << 8));
3042
3043 gma_write16(hw, port, GM_RX_CTRL, reg);
3044 }
3045
3046 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3047 {
3048 if (hw->chip_id == CHIP_ID_GENESIS)
3049 return status >> XMR_FS_LEN_SHIFT;
3050 else
3051 return status >> GMR_FS_LEN_SHIFT;
3052 }
3053
3054 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3055 {
3056 if (hw->chip_id == CHIP_ID_GENESIS)
3057 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3058 else
3059 return (status & GMR_FS_ANY_ERR) ||
3060 (status & GMR_FS_RX_OK) == 0;
3061 }
3062
3063
3064 /* Get receive buffer from descriptor.
3065 * Handles copy of small buffers and reallocation failures
3066 */
3067 static struct sk_buff *skge_rx_get(struct net_device *dev,
3068 struct skge_element *e,
3069 u32 control, u32 status, u16 csum)
3070 {
3071 struct skge_port *skge = netdev_priv(dev);
3072 struct sk_buff *skb;
3073 u16 len = control & BMU_BBC;
3074
3075 if (unlikely(netif_msg_rx_status(skge)))
3076 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
3077 dev->name, e - skge->rx_ring.start,
3078 status, len);
3079
3080 if (len > skge->rx_buf_size)
3081 goto error;
3082
3083 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3084 goto error;
3085
3086 if (bad_phy_status(skge->hw, status))
3087 goto error;
3088
3089 if (phy_length(skge->hw, status) != len)
3090 goto error;
3091
3092 if (len < RX_COPY_THRESHOLD) {
3093 skb = netdev_alloc_skb(dev, len + 2);
3094 if (!skb)
3095 goto resubmit;
3096
3097 skb_reserve(skb, 2);
3098 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3099 pci_unmap_addr(e, mapaddr),
3100 len, PCI_DMA_FROMDEVICE);
3101 skb_copy_from_linear_data(e->skb, skb->data, len);
3102 pci_dma_sync_single_for_device(skge->hw->pdev,
3103 pci_unmap_addr(e, mapaddr),
3104 len, PCI_DMA_FROMDEVICE);
3105 skge_rx_reuse(e, skge->rx_buf_size);
3106 } else {
3107 struct sk_buff *nskb;
3108 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
3109 if (!nskb)
3110 goto resubmit;
3111
3112 skb_reserve(nskb, NET_IP_ALIGN);
3113 pci_unmap_single(skge->hw->pdev,
3114 pci_unmap_addr(e, mapaddr),
3115 pci_unmap_len(e, maplen),
3116 PCI_DMA_FROMDEVICE);
3117 skb = e->skb;
3118 prefetch(skb->data);
3119 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3120 }
3121
3122 skb_put(skb, len);
3123 if (skge->rx_csum) {
3124 skb->csum = csum;
3125 skb->ip_summed = CHECKSUM_COMPLETE;
3126 }
3127
3128 skb->protocol = eth_type_trans(skb, dev);
3129
3130 return skb;
3131 error:
3132
3133 if (netif_msg_rx_err(skge))
3134 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
3135 dev->name, e - skge->rx_ring.start,
3136 control, status);
3137
3138 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3139 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3140 dev->stats.rx_length_errors++;
3141 if (status & XMR_FS_FRA_ERR)
3142 dev->stats.rx_frame_errors++;
3143 if (status & XMR_FS_FCS_ERR)
3144 dev->stats.rx_crc_errors++;
3145 } else {
3146 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3147 dev->stats.rx_length_errors++;
3148 if (status & GMR_FS_FRAGMENT)
3149 dev->stats.rx_frame_errors++;
3150 if (status & GMR_FS_CRC_ERR)
3151 dev->stats.rx_crc_errors++;
3152 }
3153
3154 resubmit:
3155 skge_rx_reuse(e, skge->rx_buf_size);
3156 return NULL;
3157 }
3158
3159 /* Free all buffers in Tx ring which are no longer owned by device */
3160 static void skge_tx_done(struct net_device *dev)
3161 {
3162 struct skge_port *skge = netdev_priv(dev);
3163 struct skge_ring *ring = &skge->tx_ring;
3164 struct skge_element *e;
3165
3166 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3167
3168 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3169 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3170
3171 if (control & BMU_OWN)
3172 break;
3173
3174 skge_tx_free(skge, e, control);
3175 }
3176 skge->tx_ring.to_clean = e;
3177
3178 /* Can run lockless until we need to synchronize to restart queue. */
3179 smp_mb();
3180
3181 if (unlikely(netif_queue_stopped(dev) &&
3182 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3183 netif_tx_lock(dev);
3184 if (unlikely(netif_queue_stopped(dev) &&
3185 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3186 netif_wake_queue(dev);
3187
3188 }
3189 netif_tx_unlock(dev);
3190 }
3191 }
3192
3193 static int skge_poll(struct napi_struct *napi, int to_do)
3194 {
3195 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3196 struct net_device *dev = skge->netdev;
3197 struct skge_hw *hw = skge->hw;
3198 struct skge_ring *ring = &skge->rx_ring;
3199 struct skge_element *e;
3200 int work_done = 0;
3201
3202 skge_tx_done(dev);
3203
3204 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3205
3206 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3207 struct skge_rx_desc *rd = e->desc;
3208 struct sk_buff *skb;
3209 u32 control;
3210
3211 rmb();
3212 control = rd->control;
3213 if (control & BMU_OWN)
3214 break;
3215
3216 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3217 if (likely(skb)) {
3218 dev->last_rx = jiffies;
3219 netif_receive_skb(skb);
3220
3221 ++work_done;
3222 }
3223 }
3224 ring->to_clean = e;
3225
3226 /* restart receiver */
3227 wmb();
3228 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3229
3230 if (work_done < to_do) {
3231 spin_lock_irq(&hw->hw_lock);
3232 __netif_rx_complete(dev, napi);
3233 hw->intr_mask |= napimask[skge->port];
3234 skge_write32(hw, B0_IMSK, hw->intr_mask);
3235 skge_read32(hw, B0_IMSK);
3236 spin_unlock_irq(&hw->hw_lock);
3237 }
3238
3239 return work_done;
3240 }
3241
3242 /* Parity errors seem to happen when Genesis is connected to a switch
3243 * with no other ports present. Heartbeat error??
3244 */
3245 static void skge_mac_parity(struct skge_hw *hw, int port)
3246 {
3247 struct net_device *dev = hw->dev[port];
3248
3249 ++dev->stats.tx_heartbeat_errors;
3250
3251 if (hw->chip_id == CHIP_ID_GENESIS)
3252 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3253 MFF_CLR_PERR);
3254 else
3255 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3256 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3257 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3258 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3259 }
3260
3261 static void skge_mac_intr(struct skge_hw *hw, int port)
3262 {
3263 if (hw->chip_id == CHIP_ID_GENESIS)
3264 genesis_mac_intr(hw, port);
3265 else
3266 yukon_mac_intr(hw, port);
3267 }
3268
3269 /* Handle device specific framing and timeout interrupts */
3270 static void skge_error_irq(struct skge_hw *hw)
3271 {
3272 struct pci_dev *pdev = hw->pdev;
3273 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3274
3275 if (hw->chip_id == CHIP_ID_GENESIS) {
3276 /* clear xmac errors */
3277 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3278 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3279 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3280 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3281 } else {
3282 /* Timestamp (unused) overflow */
3283 if (hwstatus & IS_IRQ_TIST_OV)
3284 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3285 }
3286
3287 if (hwstatus & IS_RAM_RD_PAR) {
3288 dev_err(&pdev->dev, "Ram read data parity error\n");
3289 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3290 }
3291
3292 if (hwstatus & IS_RAM_WR_PAR) {
3293 dev_err(&pdev->dev, "Ram write data parity error\n");
3294 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3295 }
3296
3297 if (hwstatus & IS_M1_PAR_ERR)
3298 skge_mac_parity(hw, 0);
3299
3300 if (hwstatus & IS_M2_PAR_ERR)
3301 skge_mac_parity(hw, 1);
3302
3303 if (hwstatus & IS_R1_PAR_ERR) {
3304 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3305 hw->dev[0]->name);
3306 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3307 }
3308
3309 if (hwstatus & IS_R2_PAR_ERR) {
3310 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3311 hw->dev[1]->name);
3312 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3313 }
3314
3315 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3316 u16 pci_status, pci_cmd;
3317
3318 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3319 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3320
3321 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3322 pci_cmd, pci_status);
3323
3324 /* Write the error bits back to clear them. */
3325 pci_status &= PCI_STATUS_ERROR_BITS;
3326 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3327 pci_write_config_word(pdev, PCI_COMMAND,
3328 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3329 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3330 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3331
3332 /* if error still set then just ignore it */
3333 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3334 if (hwstatus & IS_IRQ_STAT) {
3335 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3336 hw->intr_mask &= ~IS_HW_ERR;
3337 }
3338 }
3339 }
3340
3341 /*
3342 * Interrupt from PHY are handled in tasklet (softirq)
3343 * because accessing phy registers requires spin wait which might
3344 * cause excess interrupt latency.
3345 */
3346 static void skge_extirq(unsigned long arg)
3347 {
3348 struct skge_hw *hw = (struct skge_hw *) arg;
3349 int port;
3350
3351 for (port = 0; port < hw->ports; port++) {
3352 struct net_device *dev = hw->dev[port];
3353
3354 if (netif_running(dev)) {
3355 struct skge_port *skge = netdev_priv(dev);
3356
3357 spin_lock(&hw->phy_lock);
3358 if (hw->chip_id != CHIP_ID_GENESIS)
3359 yukon_phy_intr(skge);
3360 else if (hw->phy_type == SK_PHY_BCOM)
3361 bcom_phy_intr(skge);
3362 spin_unlock(&hw->phy_lock);
3363 }
3364 }
3365
3366 spin_lock_irq(&hw->hw_lock);
3367 hw->intr_mask |= IS_EXT_REG;
3368 skge_write32(hw, B0_IMSK, hw->intr_mask);
3369 skge_read32(hw, B0_IMSK);
3370 spin_unlock_irq(&hw->hw_lock);
3371 }
3372
3373 static irqreturn_t skge_intr(int irq, void *dev_id)
3374 {
3375 struct skge_hw *hw = dev_id;
3376 u32 status;
3377 int handled = 0;
3378
3379 spin_lock(&hw->hw_lock);
3380 /* Reading this register masks IRQ */
3381 status = skge_read32(hw, B0_SP_ISRC);
3382 if (status == 0 || status == ~0)
3383 goto out;
3384
3385 handled = 1;
3386 status &= hw->intr_mask;
3387 if (status & IS_EXT_REG) {
3388 hw->intr_mask &= ~IS_EXT_REG;
3389 tasklet_schedule(&hw->phy_task);
3390 }
3391
3392 if (status & (IS_XA1_F|IS_R1_F)) {
3393 struct skge_port *skge = netdev_priv(hw->dev[0]);
3394 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3395 netif_rx_schedule(hw->dev[0], &skge->napi);
3396 }
3397
3398 if (status & IS_PA_TO_TX1)
3399 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3400
3401 if (status & IS_PA_TO_RX1) {
3402 ++hw->dev[0]->stats.rx_over_errors;
3403 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3404 }
3405
3406
3407 if (status & IS_MAC1)
3408 skge_mac_intr(hw, 0);
3409
3410 if (hw->dev[1]) {
3411 struct skge_port *skge = netdev_priv(hw->dev[1]);
3412
3413 if (status & (IS_XA2_F|IS_R2_F)) {
3414 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3415 netif_rx_schedule(hw->dev[1], &skge->napi);
3416 }
3417
3418 if (status & IS_PA_TO_RX2) {
3419 ++hw->dev[1]->stats.rx_over_errors;
3420 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3421 }
3422
3423 if (status & IS_PA_TO_TX2)
3424 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3425
3426 if (status & IS_MAC2)
3427 skge_mac_intr(hw, 1);
3428 }
3429
3430 if (status & IS_HW_ERR)
3431 skge_error_irq(hw);
3432
3433 skge_write32(hw, B0_IMSK, hw->intr_mask);
3434 skge_read32(hw, B0_IMSK);
3435 out:
3436 spin_unlock(&hw->hw_lock);
3437
3438 return IRQ_RETVAL(handled);
3439 }
3440
3441 #ifdef CONFIG_NET_POLL_CONTROLLER
3442 static void skge_netpoll(struct net_device *dev)
3443 {
3444 struct skge_port *skge = netdev_priv(dev);
3445
3446 disable_irq(dev->irq);
3447 skge_intr(dev->irq, skge->hw);
3448 enable_irq(dev->irq);
3449 }
3450 #endif
3451
3452 static int skge_set_mac_address(struct net_device *dev, void *p)
3453 {
3454 struct skge_port *skge = netdev_priv(dev);
3455 struct skge_hw *hw = skge->hw;
3456 unsigned port = skge->port;
3457 const struct sockaddr *addr = p;
3458 u16 ctrl;
3459
3460 if (!is_valid_ether_addr(addr->sa_data))
3461 return -EADDRNOTAVAIL;
3462
3463 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3464
3465 if (!netif_running(dev)) {
3466 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3467 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3468 } else {
3469 /* disable Rx */
3470 spin_lock_bh(&hw->phy_lock);
3471 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3472 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3473
3474 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3475 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3476
3477 if (hw->chip_id == CHIP_ID_GENESIS)
3478 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3479 else {
3480 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3481 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3482 }
3483
3484 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3485 spin_unlock_bh(&hw->phy_lock);
3486 }
3487
3488 return 0;
3489 }
3490
3491 static const struct {
3492 u8 id;
3493 const char *name;
3494 } skge_chips[] = {
3495 { CHIP_ID_GENESIS, "Genesis" },
3496 { CHIP_ID_YUKON, "Yukon" },
3497 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3498 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3499 };
3500
3501 static const char *skge_board_name(const struct skge_hw *hw)
3502 {
3503 int i;
3504 static char buf[16];
3505
3506 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3507 if (skge_chips[i].id == hw->chip_id)
3508 return skge_chips[i].name;
3509
3510 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3511 return buf;
3512 }
3513
3514
3515 /*
3516 * Setup the board data structure, but don't bring up
3517 * the port(s)
3518 */
3519 static int skge_reset(struct skge_hw *hw)
3520 {
3521 u32 reg;
3522 u16 ctst, pci_status;
3523 u8 t8, mac_cfg, pmd_type;
3524 int i;
3525
3526 ctst = skge_read16(hw, B0_CTST);
3527
3528 /* do a SW reset */
3529 skge_write8(hw, B0_CTST, CS_RST_SET);
3530 skge_write8(hw, B0_CTST, CS_RST_CLR);
3531
3532 /* clear PCI errors, if any */
3533 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3534 skge_write8(hw, B2_TST_CTRL2, 0);
3535
3536 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3537 pci_write_config_word(hw->pdev, PCI_STATUS,
3538 pci_status | PCI_STATUS_ERROR_BITS);
3539 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3540 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3541
3542 /* restore CLK_RUN bits (for Yukon-Lite) */
3543 skge_write16(hw, B0_CTST,
3544 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3545
3546 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3547 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3548 pmd_type = skge_read8(hw, B2_PMD_TYP);
3549 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3550
3551 switch (hw->chip_id) {
3552 case CHIP_ID_GENESIS:
3553 switch (hw->phy_type) {
3554 case SK_PHY_XMAC:
3555 hw->phy_addr = PHY_ADDR_XMAC;
3556 break;
3557 case SK_PHY_BCOM:
3558 hw->phy_addr = PHY_ADDR_BCOM;
3559 break;
3560 default:
3561 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3562 hw->phy_type);
3563 return -EOPNOTSUPP;
3564 }
3565 break;
3566
3567 case CHIP_ID_YUKON:
3568 case CHIP_ID_YUKON_LITE:
3569 case CHIP_ID_YUKON_LP:
3570 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3571 hw->copper = 1;
3572
3573 hw->phy_addr = PHY_ADDR_MARV;
3574 break;
3575
3576 default:
3577 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3578 hw->chip_id);
3579 return -EOPNOTSUPP;
3580 }
3581
3582 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3583 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3584 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3585
3586 /* read the adapters RAM size */
3587 t8 = skge_read8(hw, B2_E_0);
3588 if (hw->chip_id == CHIP_ID_GENESIS) {
3589 if (t8 == 3) {
3590 /* special case: 4 x 64k x 36, offset = 0x80000 */
3591 hw->ram_size = 0x100000;
3592 hw->ram_offset = 0x80000;
3593 } else
3594 hw->ram_size = t8 * 512;
3595 }
3596 else if (t8 == 0)
3597 hw->ram_size = 0x20000;
3598 else
3599 hw->ram_size = t8 * 4096;
3600
3601 hw->intr_mask = IS_HW_ERR;
3602
3603 /* Use PHY IRQ for all but fiber based Genesis board */
3604 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3605 hw->intr_mask |= IS_EXT_REG;
3606
3607 if (hw->chip_id == CHIP_ID_GENESIS)
3608 genesis_init(hw);
3609 else {
3610 /* switch power to VCC (WA for VAUX problem) */
3611 skge_write8(hw, B0_POWER_CTRL,
3612 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3613
3614 /* avoid boards with stuck Hardware error bits */
3615 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3616 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3617 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3618 hw->intr_mask &= ~IS_HW_ERR;
3619 }
3620
3621 /* Clear PHY COMA */
3622 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3623 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3624 reg &= ~PCI_PHY_COMA;
3625 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3626 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3627
3628
3629 for (i = 0; i < hw->ports; i++) {
3630 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3631 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3632 }
3633 }
3634
3635 /* turn off hardware timer (unused) */
3636 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3637 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3638 skge_write8(hw, B0_LED, LED_STAT_ON);
3639
3640 /* enable the Tx Arbiters */
3641 for (i = 0; i < hw->ports; i++)
3642 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3643
3644 /* Initialize ram interface */
3645 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3646
3647 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3648 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3649 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3650 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3659
3660 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3661
3662 /* Set interrupt moderation for Transmit only
3663 * Receive interrupts avoided by NAPI
3664 */
3665 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3666 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3667 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3668
3669 skge_write32(hw, B0_IMSK, hw->intr_mask);
3670
3671 for (i = 0; i < hw->ports; i++) {
3672 if (hw->chip_id == CHIP_ID_GENESIS)
3673 genesis_reset(hw, i);
3674 else
3675 yukon_reset(hw, i);
3676 }
3677
3678 return 0;
3679 }
3680
3681
3682 #ifdef CONFIG_SKGE_DEBUG
3683
3684 static struct dentry *skge_debug;
3685
3686 static int skge_debug_show(struct seq_file *seq, void *v)
3687 {
3688 struct net_device *dev = seq->private;
3689 const struct skge_port *skge = netdev_priv(dev);
3690 const struct skge_hw *hw = skge->hw;
3691 const struct skge_element *e;
3692
3693 if (!netif_running(dev))
3694 return -ENETDOWN;
3695
3696 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3697 skge_read32(hw, B0_IMSK));
3698
3699 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3700 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3701 const struct skge_tx_desc *t = e->desc;
3702 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3703 t->control, t->dma_hi, t->dma_lo, t->status,
3704 t->csum_offs, t->csum_write, t->csum_start);
3705 }
3706
3707 seq_printf(seq, "\nRx Ring: \n");
3708 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3709 const struct skge_rx_desc *r = e->desc;
3710
3711 if (r->control & BMU_OWN)
3712 break;
3713
3714 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3715 r->control, r->dma_hi, r->dma_lo, r->status,
3716 r->timestamp, r->csum1, r->csum1_start);
3717 }
3718
3719 return 0;
3720 }
3721
3722 static int skge_debug_open(struct inode *inode, struct file *file)
3723 {
3724 return single_open(file, skge_debug_show, inode->i_private);
3725 }
3726
3727 static const struct file_operations skge_debug_fops = {
3728 .owner = THIS_MODULE,
3729 .open = skge_debug_open,
3730 .read = seq_read,
3731 .llseek = seq_lseek,
3732 .release = single_release,
3733 };
3734
3735 /*
3736 * Use network device events to create/remove/rename
3737 * debugfs file entries
3738 */
3739 static int skge_device_event(struct notifier_block *unused,
3740 unsigned long event, void *ptr)
3741 {
3742 struct net_device *dev = ptr;
3743 struct skge_port *skge;
3744 struct dentry *d;
3745
3746 if (dev->open != &skge_up || !skge_debug)
3747 goto done;
3748
3749 skge = netdev_priv(dev);
3750 switch(event) {
3751 case NETDEV_CHANGENAME:
3752 if (skge->debugfs) {
3753 d = debugfs_rename(skge_debug, skge->debugfs,
3754 skge_debug, dev->name);
3755 if (d)
3756 skge->debugfs = d;
3757 else {
3758 pr_info(PFX "%s: rename failed\n", dev->name);
3759 debugfs_remove(skge->debugfs);
3760 }
3761 }
3762 break;
3763
3764 case NETDEV_GOING_DOWN:
3765 if (skge->debugfs) {
3766 debugfs_remove(skge->debugfs);
3767 skge->debugfs = NULL;
3768 }
3769 break;
3770
3771 case NETDEV_UP:
3772 d = debugfs_create_file(dev->name, S_IRUGO,
3773 skge_debug, dev,
3774 &skge_debug_fops);
3775 if (!d || IS_ERR(d))
3776 pr_info(PFX "%s: debugfs create failed\n",
3777 dev->name);
3778 else
3779 skge->debugfs = d;
3780 break;
3781 }
3782
3783 done:
3784 return NOTIFY_DONE;
3785 }
3786
3787 static struct notifier_block skge_notifier = {
3788 .notifier_call = skge_device_event,
3789 };
3790
3791
3792 static __init void skge_debug_init(void)
3793 {
3794 struct dentry *ent;
3795
3796 ent = debugfs_create_dir("skge", NULL);
3797 if (!ent || IS_ERR(ent)) {
3798 pr_info(PFX "debugfs create directory failed\n");
3799 return;
3800 }
3801
3802 skge_debug = ent;
3803 register_netdevice_notifier(&skge_notifier);
3804 }
3805
3806 static __exit void skge_debug_cleanup(void)
3807 {
3808 if (skge_debug) {
3809 unregister_netdevice_notifier(&skge_notifier);
3810 debugfs_remove(skge_debug);
3811 skge_debug = NULL;
3812 }
3813 }
3814
3815 #else
3816 #define skge_debug_init()
3817 #define skge_debug_cleanup()
3818 #endif
3819
3820 /* Initialize network device */
3821 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3822 int highmem)
3823 {
3824 struct skge_port *skge;
3825 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3826
3827 if (!dev) {
3828 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3829 return NULL;
3830 }
3831
3832 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3833 dev->open = skge_up;
3834 dev->stop = skge_down;
3835 dev->do_ioctl = skge_ioctl;
3836 dev->hard_start_xmit = skge_xmit_frame;
3837 dev->get_stats = skge_get_stats;
3838 if (hw->chip_id == CHIP_ID_GENESIS)
3839 dev->set_multicast_list = genesis_set_multicast;
3840 else
3841 dev->set_multicast_list = yukon_set_multicast;
3842
3843 dev->set_mac_address = skge_set_mac_address;
3844 dev->change_mtu = skge_change_mtu;
3845 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3846 dev->tx_timeout = skge_tx_timeout;
3847 dev->watchdog_timeo = TX_WATCHDOG;
3848 #ifdef CONFIG_NET_POLL_CONTROLLER
3849 dev->poll_controller = skge_netpoll;
3850 #endif
3851 dev->irq = hw->pdev->irq;
3852
3853 if (highmem)
3854 dev->features |= NETIF_F_HIGHDMA;
3855
3856 skge = netdev_priv(dev);
3857 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3858 skge->netdev = dev;
3859 skge->hw = hw;
3860 skge->msg_enable = netif_msg_init(debug, default_msg);
3861
3862 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3863 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3864
3865 /* Auto speed and flow control */
3866 skge->autoneg = AUTONEG_ENABLE;
3867 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3868 skge->duplex = -1;
3869 skge->speed = -1;
3870 skge->advertising = skge_supported_modes(hw);
3871
3872 if (pci_wake_enabled(hw->pdev))
3873 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3874
3875 hw->dev[port] = dev;
3876
3877 skge->port = port;
3878
3879 /* Only used for Genesis XMAC */
3880 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3881
3882 if (hw->chip_id != CHIP_ID_GENESIS) {
3883 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3884 skge->rx_csum = 1;
3885 }
3886
3887 /* read the mac address */
3888 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3889 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3890
3891 /* device is off until link detection */
3892 netif_carrier_off(dev);
3893 netif_stop_queue(dev);
3894
3895 return dev;
3896 }
3897
3898 static void __devinit skge_show_addr(struct net_device *dev)
3899 {
3900 const struct skge_port *skge = netdev_priv(dev);
3901 DECLARE_MAC_BUF(mac);
3902
3903 if (netif_msg_probe(skge))
3904 printk(KERN_INFO PFX "%s: addr %s\n",
3905 dev->name, print_mac(mac, dev->dev_addr));
3906 }
3907
3908 static int __devinit skge_probe(struct pci_dev *pdev,
3909 const struct pci_device_id *ent)
3910 {
3911 struct net_device *dev, *dev1;
3912 struct skge_hw *hw;
3913 int err, using_dac = 0;
3914
3915 err = pci_enable_device(pdev);
3916 if (err) {
3917 dev_err(&pdev->dev, "cannot enable PCI device\n");
3918 goto err_out;
3919 }
3920
3921 err = pci_request_regions(pdev, DRV_NAME);
3922 if (err) {
3923 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3924 goto err_out_disable_pdev;
3925 }
3926
3927 pci_set_master(pdev);
3928
3929 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3930 using_dac = 1;
3931 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3932 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3933 using_dac = 0;
3934 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3935 }
3936
3937 if (err) {
3938 dev_err(&pdev->dev, "no usable DMA configuration\n");
3939 goto err_out_free_regions;
3940 }
3941
3942 #ifdef __BIG_ENDIAN
3943 /* byte swap descriptors in hardware */
3944 {
3945 u32 reg;
3946
3947 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3948 reg |= PCI_REV_DESC;
3949 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3950 }
3951 #endif
3952
3953 err = -ENOMEM;
3954 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3955 if (!hw) {
3956 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3957 goto err_out_free_regions;
3958 }
3959
3960 hw->pdev = pdev;
3961 spin_lock_init(&hw->hw_lock);
3962 spin_lock_init(&hw->phy_lock);
3963 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3964
3965 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3966 if (!hw->regs) {
3967 dev_err(&pdev->dev, "cannot map device registers\n");
3968 goto err_out_free_hw;
3969 }
3970
3971 err = skge_reset(hw);
3972 if (err)
3973 goto err_out_iounmap;
3974
3975 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3976 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3977 skge_board_name(hw), hw->chip_rev);
3978
3979 dev = skge_devinit(hw, 0, using_dac);
3980 if (!dev)
3981 goto err_out_led_off;
3982
3983 /* Some motherboards are broken and has zero in ROM. */
3984 if (!is_valid_ether_addr(dev->dev_addr))
3985 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3986
3987 err = register_netdev(dev);
3988 if (err) {
3989 dev_err(&pdev->dev, "cannot register net device\n");
3990 goto err_out_free_netdev;
3991 }
3992
3993 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3994 if (err) {
3995 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3996 dev->name, pdev->irq);
3997 goto err_out_unregister;
3998 }
3999 skge_show_addr(dev);
4000
4001 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
4002 if (register_netdev(dev1) == 0)
4003 skge_show_addr(dev1);
4004 else {
4005 /* Failure to register second port need not be fatal */
4006 dev_warn(&pdev->dev, "register of second port failed\n");
4007 hw->dev[1] = NULL;
4008 free_netdev(dev1);
4009 }
4010 }
4011 pci_set_drvdata(pdev, hw);
4012
4013 return 0;
4014
4015 err_out_unregister:
4016 unregister_netdev(dev);
4017 err_out_free_netdev:
4018 free_netdev(dev);
4019 err_out_led_off:
4020 skge_write16(hw, B0_LED, LED_STAT_OFF);
4021 err_out_iounmap:
4022 iounmap(hw->regs);
4023 err_out_free_hw:
4024 kfree(hw);
4025 err_out_free_regions:
4026 pci_release_regions(pdev);
4027 err_out_disable_pdev:
4028 pci_disable_device(pdev);
4029 pci_set_drvdata(pdev, NULL);
4030 err_out:
4031 return err;
4032 }
4033
4034 static void __devexit skge_remove(struct pci_dev *pdev)
4035 {
4036 struct skge_hw *hw = pci_get_drvdata(pdev);
4037 struct net_device *dev0, *dev1;
4038
4039 if (!hw)
4040 return;
4041
4042 flush_scheduled_work();
4043
4044 if ((dev1 = hw->dev[1]))
4045 unregister_netdev(dev1);
4046 dev0 = hw->dev[0];
4047 unregister_netdev(dev0);
4048
4049 tasklet_disable(&hw->phy_task);
4050
4051 spin_lock_irq(&hw->hw_lock);
4052 hw->intr_mask = 0;
4053 skge_write32(hw, B0_IMSK, 0);
4054 skge_read32(hw, B0_IMSK);
4055 spin_unlock_irq(&hw->hw_lock);
4056
4057 skge_write16(hw, B0_LED, LED_STAT_OFF);
4058 skge_write8(hw, B0_CTST, CS_RST_SET);
4059
4060 free_irq(pdev->irq, hw);
4061 pci_release_regions(pdev);
4062 pci_disable_device(pdev);
4063 if (dev1)
4064 free_netdev(dev1);
4065 free_netdev(dev0);
4066
4067 iounmap(hw->regs);
4068 kfree(hw);
4069 pci_set_drvdata(pdev, NULL);
4070 }
4071
4072 #ifdef CONFIG_PM
4073 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
4074 {
4075 struct skge_hw *hw = pci_get_drvdata(pdev);
4076 int i, err, wol = 0;
4077
4078 if (!hw)
4079 return 0;
4080
4081 err = pci_save_state(pdev);
4082 if (err)
4083 return err;
4084
4085 for (i = 0; i < hw->ports; i++) {
4086 struct net_device *dev = hw->dev[i];
4087 struct skge_port *skge = netdev_priv(dev);
4088
4089 if (netif_running(dev))
4090 skge_down(dev);
4091 if (skge->wol)
4092 skge_wol_init(skge);
4093
4094 wol |= skge->wol;
4095 }
4096
4097 skge_write32(hw, B0_IMSK, 0);
4098 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4099 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4100
4101 return 0;
4102 }
4103
4104 static int skge_resume(struct pci_dev *pdev)
4105 {
4106 struct skge_hw *hw = pci_get_drvdata(pdev);
4107 int i, err;
4108
4109 if (!hw)
4110 return 0;
4111
4112 err = pci_set_power_state(pdev, PCI_D0);
4113 if (err)
4114 goto out;
4115
4116 err = pci_restore_state(pdev);
4117 if (err)
4118 goto out;
4119
4120 pci_enable_wake(pdev, PCI_D0, 0);
4121
4122 err = skge_reset(hw);
4123 if (err)
4124 goto out;
4125
4126 for (i = 0; i < hw->ports; i++) {
4127 struct net_device *dev = hw->dev[i];
4128
4129 if (netif_running(dev)) {
4130 err = skge_up(dev);
4131
4132 if (err) {
4133 printk(KERN_ERR PFX "%s: could not up: %d\n",
4134 dev->name, err);
4135 dev_close(dev);
4136 goto out;
4137 }
4138 }
4139 }
4140 out:
4141 return err;
4142 }
4143 #endif
4144
4145 static void skge_shutdown(struct pci_dev *pdev)
4146 {
4147 struct skge_hw *hw = pci_get_drvdata(pdev);
4148 int i, wol = 0;
4149
4150 if (!hw)
4151 return;
4152
4153 for (i = 0; i < hw->ports; i++) {
4154 struct net_device *dev = hw->dev[i];
4155 struct skge_port *skge = netdev_priv(dev);
4156
4157 if (skge->wol)
4158 skge_wol_init(skge);
4159 wol |= skge->wol;
4160 }
4161
4162 pci_enable_wake(pdev, PCI_D3hot, wol);
4163 pci_enable_wake(pdev, PCI_D3cold, wol);
4164
4165 pci_disable_device(pdev);
4166 pci_set_power_state(pdev, PCI_D3hot);
4167
4168 }
4169
4170 static struct pci_driver skge_driver = {
4171 .name = DRV_NAME,
4172 .id_table = skge_id_table,
4173 .probe = skge_probe,
4174 .remove = __devexit_p(skge_remove),
4175 #ifdef CONFIG_PM
4176 .suspend = skge_suspend,
4177 .resume = skge_resume,
4178 #endif
4179 .shutdown = skge_shutdown,
4180 };
4181
4182 static int __init skge_init_module(void)
4183 {
4184 skge_debug_init();
4185 return pci_register_driver(&skge_driver);
4186 }
4187
4188 static void __exit skge_cleanup_module(void)
4189 {
4190 pci_unregister_driver(&skge_driver);
4191 skge_debug_cleanup();
4192 }
4193
4194 module_init(skge_init_module);
4195 module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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