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[PATCH] skge: use kcalloc
[deliverable/linux.git] / drivers / net / skge.c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/in.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/mii.h>
42 #include <asm/irq.h>
43
44 #include "skge.h"
45
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.3"
48 #define PFX DRV_NAME " "
49
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
60 #define BLINK_MS 250
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
86 { 0 }
87 };
88 MODULE_DEVICE_TABLE(pci, skge_id_table);
89
90 static int skge_up(struct net_device *dev);
91 static int skge_down(struct net_device *dev);
92 static void skge_phy_reset(struct skge_port *skge);
93 static void skge_tx_clean(struct skge_port *skge);
94 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static void genesis_get_stats(struct skge_port *skge, u64 *data);
97 static void yukon_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_init(struct skge_hw *hw, int port);
99 static void genesis_mac_init(struct skge_hw *hw, int port);
100 static void genesis_link_up(struct skge_port *skge);
101
102 /* Avoid conditionals by using array */
103 static const int txqaddr[] = { Q_XA1, Q_XA2 };
104 static const int rxqaddr[] = { Q_R1, Q_R2 };
105 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
107
108 static int skge_get_regs_len(struct net_device *dev)
109 {
110 return 0x4000;
111 }
112
113 /*
114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
116 * cause bus hangs!
117 */
118 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
119 void *p)
120 {
121 const struct skge_port *skge = netdev_priv(dev);
122 const void __iomem *io = skge->hw->regs;
123
124 regs->version = 1;
125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
127
128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
130 }
131
132 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
133 static int wol_supported(const struct skge_hw *hw)
134 {
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
137 }
138
139 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
140 {
141 struct skge_port *skge = netdev_priv(dev);
142
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
145 }
146
147 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
148 {
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
151
152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
153 return -EOPNOTSUPP;
154
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
156 return -EOPNOTSUPP;
157
158 skge->wol = wol->wolopts == WAKE_MAGIC;
159
160 if (skge->wol) {
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
162
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
166 } else
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
168
169 return 0;
170 }
171
172 /* Determine supported/advertised modes based on hardware.
173 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
174 */
175 static u32 skge_supported_modes(const struct skge_hw *hw)
176 {
177 u32 supported;
178
179 if (hw->copper) {
180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
187
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
193
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
196 } else
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
198 | SUPPORTED_Autoneg;
199
200 return supported;
201 }
202
203 static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
205 {
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
208
209 ecmd->transceiver = XCVR_INTERNAL;
210 ecmd->supported = skge_supported_modes(hw);
211
212 if (hw->copper) {
213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
215 } else
216 ecmd->port = PORT_FIBRE;
217
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
222 return 0;
223 }
224
225 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
226 {
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
229 u32 supported = skge_supported_modes(hw);
230
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
232 ecmd->advertising = supported;
233 skge->duplex = -1;
234 skge->speed = -1;
235 } else {
236 u32 setting;
237
238 switch (ecmd->speed) {
239 case SPEED_1000:
240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
244 else
245 return -EINVAL;
246 break;
247 case SPEED_100:
248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
252 else
253 return -EINVAL;
254 break;
255
256 case SPEED_10:
257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
261 else
262 return -EINVAL;
263 break;
264 default:
265 return -EINVAL;
266 }
267
268 if ((setting & supported) == 0)
269 return -EINVAL;
270
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
273 }
274
275 skge->autoneg = ecmd->autoneg;
276 skge->advertising = ecmd->advertising;
277
278 if (netif_running(dev))
279 skge_phy_reset(skge);
280
281 return (0);
282 }
283
284 static void skge_get_drvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
286 {
287 struct skge_port *skge = netdev_priv(dev);
288
289 strcpy(info->driver, DRV_NAME);
290 strcpy(info->version, DRV_VERSION);
291 strcpy(info->fw_version, "N/A");
292 strcpy(info->bus_info, pci_name(skge->hw->pdev));
293 }
294
295 static const struct skge_stat {
296 char name[ETH_GSTRING_LEN];
297 u16 xmac_offset;
298 u16 gma_offset;
299 } skge_stats[] = {
300 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
301 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
302
303 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
304 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
305 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
306 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
307 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
308 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
309 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
310 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
311
312 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
313 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
314 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
315 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
316 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
317 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
318
319 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
320 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
321 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
322 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
324 };
325
326 static int skge_get_stats_count(struct net_device *dev)
327 {
328 return ARRAY_SIZE(skge_stats);
329 }
330
331 static void skge_get_ethtool_stats(struct net_device *dev,
332 struct ethtool_stats *stats, u64 *data)
333 {
334 struct skge_port *skge = netdev_priv(dev);
335
336 if (skge->hw->chip_id == CHIP_ID_GENESIS)
337 genesis_get_stats(skge, data);
338 else
339 yukon_get_stats(skge, data);
340 }
341
342 /* Use hardware MIB variables for critical path statistics and
343 * transmit feedback not reported at interrupt.
344 * Other errors are accounted for in interrupt handler.
345 */
346 static struct net_device_stats *skge_get_stats(struct net_device *dev)
347 {
348 struct skge_port *skge = netdev_priv(dev);
349 u64 data[ARRAY_SIZE(skge_stats)];
350
351 if (skge->hw->chip_id == CHIP_ID_GENESIS)
352 genesis_get_stats(skge, data);
353 else
354 yukon_get_stats(skge, data);
355
356 skge->net_stats.tx_bytes = data[0];
357 skge->net_stats.rx_bytes = data[1];
358 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
359 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
360 skge->net_stats.multicast = data[5] + data[7];
361 skge->net_stats.collisions = data[10];
362 skge->net_stats.tx_aborted_errors = data[12];
363
364 return &skge->net_stats;
365 }
366
367 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
368 {
369 int i;
370
371 switch (stringset) {
372 case ETH_SS_STATS:
373 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
374 memcpy(data + i * ETH_GSTRING_LEN,
375 skge_stats[i].name, ETH_GSTRING_LEN);
376 break;
377 }
378 }
379
380 static void skge_get_ring_param(struct net_device *dev,
381 struct ethtool_ringparam *p)
382 {
383 struct skge_port *skge = netdev_priv(dev);
384
385 p->rx_max_pending = MAX_RX_RING_SIZE;
386 p->tx_max_pending = MAX_TX_RING_SIZE;
387 p->rx_mini_max_pending = 0;
388 p->rx_jumbo_max_pending = 0;
389
390 p->rx_pending = skge->rx_ring.count;
391 p->tx_pending = skge->tx_ring.count;
392 p->rx_mini_pending = 0;
393 p->rx_jumbo_pending = 0;
394 }
395
396 static int skge_set_ring_param(struct net_device *dev,
397 struct ethtool_ringparam *p)
398 {
399 struct skge_port *skge = netdev_priv(dev);
400 int err;
401
402 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
403 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
404 return -EINVAL;
405
406 skge->rx_ring.count = p->rx_pending;
407 skge->tx_ring.count = p->tx_pending;
408
409 if (netif_running(dev)) {
410 skge_down(dev);
411 err = skge_up(dev);
412 if (err)
413 dev_close(dev);
414 }
415
416 return 0;
417 }
418
419 static u32 skge_get_msglevel(struct net_device *netdev)
420 {
421 struct skge_port *skge = netdev_priv(netdev);
422 return skge->msg_enable;
423 }
424
425 static void skge_set_msglevel(struct net_device *netdev, u32 value)
426 {
427 struct skge_port *skge = netdev_priv(netdev);
428 skge->msg_enable = value;
429 }
430
431 static int skge_nway_reset(struct net_device *dev)
432 {
433 struct skge_port *skge = netdev_priv(dev);
434
435 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
436 return -EINVAL;
437
438 skge_phy_reset(skge);
439 return 0;
440 }
441
442 static int skge_set_sg(struct net_device *dev, u32 data)
443 {
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446
447 if (hw->chip_id == CHIP_ID_GENESIS && data)
448 return -EOPNOTSUPP;
449 return ethtool_op_set_sg(dev, data);
450 }
451
452 static int skge_set_tx_csum(struct net_device *dev, u32 data)
453 {
454 struct skge_port *skge = netdev_priv(dev);
455 struct skge_hw *hw = skge->hw;
456
457 if (hw->chip_id == CHIP_ID_GENESIS && data)
458 return -EOPNOTSUPP;
459
460 return ethtool_op_set_tx_csum(dev, data);
461 }
462
463 static u32 skge_get_rx_csum(struct net_device *dev)
464 {
465 struct skge_port *skge = netdev_priv(dev);
466
467 return skge->rx_csum;
468 }
469
470 /* Only Yukon supports checksum offload. */
471 static int skge_set_rx_csum(struct net_device *dev, u32 data)
472 {
473 struct skge_port *skge = netdev_priv(dev);
474
475 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
476 return -EOPNOTSUPP;
477
478 skge->rx_csum = data;
479 return 0;
480 }
481
482 static void skge_get_pauseparam(struct net_device *dev,
483 struct ethtool_pauseparam *ecmd)
484 {
485 struct skge_port *skge = netdev_priv(dev);
486
487 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
488 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
489 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
490 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
491
492 ecmd->autoneg = skge->autoneg;
493 }
494
495 static int skge_set_pauseparam(struct net_device *dev,
496 struct ethtool_pauseparam *ecmd)
497 {
498 struct skge_port *skge = netdev_priv(dev);
499
500 skge->autoneg = ecmd->autoneg;
501 if (ecmd->rx_pause && ecmd->tx_pause)
502 skge->flow_control = FLOW_MODE_SYMMETRIC;
503 else if (ecmd->rx_pause && !ecmd->tx_pause)
504 skge->flow_control = FLOW_MODE_REM_SEND;
505 else if (!ecmd->rx_pause && ecmd->tx_pause)
506 skge->flow_control = FLOW_MODE_LOC_SEND;
507 else
508 skge->flow_control = FLOW_MODE_NONE;
509
510 if (netif_running(dev))
511 skge_phy_reset(skge);
512 return 0;
513 }
514
515 /* Chip internal frequency for clock calculations */
516 static inline u32 hwkhz(const struct skge_hw *hw)
517 {
518 if (hw->chip_id == CHIP_ID_GENESIS)
519 return 53215; /* or: 53.125 MHz */
520 else
521 return 78215; /* or: 78.125 MHz */
522 }
523
524 /* Chip HZ to microseconds */
525 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
526 {
527 return (ticks * 1000) / hwkhz(hw);
528 }
529
530 /* Microseconds to chip HZ */
531 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
532 {
533 return hwkhz(hw) * usec / 1000;
534 }
535
536 static int skge_get_coalesce(struct net_device *dev,
537 struct ethtool_coalesce *ecmd)
538 {
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
541 int port = skge->port;
542
543 ecmd->rx_coalesce_usecs = 0;
544 ecmd->tx_coalesce_usecs = 0;
545
546 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
547 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
548 u32 msk = skge_read32(hw, B2_IRQM_MSK);
549
550 if (msk & rxirqmask[port])
551 ecmd->rx_coalesce_usecs = delay;
552 if (msk & txirqmask[port])
553 ecmd->tx_coalesce_usecs = delay;
554 }
555
556 return 0;
557 }
558
559 /* Note: interrupt timer is per board, but can turn on/off per port */
560 static int skge_set_coalesce(struct net_device *dev,
561 struct ethtool_coalesce *ecmd)
562 {
563 struct skge_port *skge = netdev_priv(dev);
564 struct skge_hw *hw = skge->hw;
565 int port = skge->port;
566 u32 msk = skge_read32(hw, B2_IRQM_MSK);
567 u32 delay = 25;
568
569 if (ecmd->rx_coalesce_usecs == 0)
570 msk &= ~rxirqmask[port];
571 else if (ecmd->rx_coalesce_usecs < 25 ||
572 ecmd->rx_coalesce_usecs > 33333)
573 return -EINVAL;
574 else {
575 msk |= rxirqmask[port];
576 delay = ecmd->rx_coalesce_usecs;
577 }
578
579 if (ecmd->tx_coalesce_usecs == 0)
580 msk &= ~txirqmask[port];
581 else if (ecmd->tx_coalesce_usecs < 25 ||
582 ecmd->tx_coalesce_usecs > 33333)
583 return -EINVAL;
584 else {
585 msk |= txirqmask[port];
586 delay = min(delay, ecmd->rx_coalesce_usecs);
587 }
588
589 skge_write32(hw, B2_IRQM_MSK, msk);
590 if (msk == 0)
591 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
592 else {
593 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
594 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
595 }
596 return 0;
597 }
598
599 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
600 static void skge_led(struct skge_port *skge, enum led_mode mode)
601 {
602 struct skge_hw *hw = skge->hw;
603 int port = skge->port;
604
605 spin_lock_bh(&hw->phy_lock);
606 if (hw->chip_id == CHIP_ID_GENESIS) {
607 switch (mode) {
608 case LED_MODE_OFF:
609 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
610 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
611 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
612 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
613 break;
614
615 case LED_MODE_ON:
616 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
618
619 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
620 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
621
622 break;
623
624 case LED_MODE_TST:
625 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
626 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
627 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
628
629 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
630 break;
631 }
632 } else {
633 switch (mode) {
634 case LED_MODE_OFF:
635 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
636 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
637 PHY_M_LED_MO_DUP(MO_LED_OFF) |
638 PHY_M_LED_MO_10(MO_LED_OFF) |
639 PHY_M_LED_MO_100(MO_LED_OFF) |
640 PHY_M_LED_MO_1000(MO_LED_OFF) |
641 PHY_M_LED_MO_RX(MO_LED_OFF));
642 break;
643 case LED_MODE_ON:
644 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
645 PHY_M_LED_PULS_DUR(PULS_170MS) |
646 PHY_M_LED_BLINK_RT(BLINK_84MS) |
647 PHY_M_LEDC_TX_CTRL |
648 PHY_M_LEDC_DP_CTRL);
649
650 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
651 PHY_M_LED_MO_RX(MO_LED_OFF) |
652 (skge->speed == SPEED_100 ?
653 PHY_M_LED_MO_100(MO_LED_ON) : 0));
654 break;
655 case LED_MODE_TST:
656 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
657 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
658 PHY_M_LED_MO_DUP(MO_LED_ON) |
659 PHY_M_LED_MO_10(MO_LED_ON) |
660 PHY_M_LED_MO_100(MO_LED_ON) |
661 PHY_M_LED_MO_1000(MO_LED_ON) |
662 PHY_M_LED_MO_RX(MO_LED_ON));
663 }
664 }
665 spin_unlock_bh(&hw->phy_lock);
666 }
667
668 /* blink LED's for finding board */
669 static int skge_phys_id(struct net_device *dev, u32 data)
670 {
671 struct skge_port *skge = netdev_priv(dev);
672 unsigned long ms;
673 enum led_mode mode = LED_MODE_TST;
674
675 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
676 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
677 else
678 ms = data * 1000;
679
680 while (ms > 0) {
681 skge_led(skge, mode);
682 mode ^= LED_MODE_TST;
683
684 if (msleep_interruptible(BLINK_MS))
685 break;
686 ms -= BLINK_MS;
687 }
688
689 /* back to regular LED state */
690 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
691
692 return 0;
693 }
694
695 static struct ethtool_ops skge_ethtool_ops = {
696 .get_settings = skge_get_settings,
697 .set_settings = skge_set_settings,
698 .get_drvinfo = skge_get_drvinfo,
699 .get_regs_len = skge_get_regs_len,
700 .get_regs = skge_get_regs,
701 .get_wol = skge_get_wol,
702 .set_wol = skge_set_wol,
703 .get_msglevel = skge_get_msglevel,
704 .set_msglevel = skge_set_msglevel,
705 .nway_reset = skge_nway_reset,
706 .get_link = ethtool_op_get_link,
707 .get_ringparam = skge_get_ring_param,
708 .set_ringparam = skge_set_ring_param,
709 .get_pauseparam = skge_get_pauseparam,
710 .set_pauseparam = skge_set_pauseparam,
711 .get_coalesce = skge_get_coalesce,
712 .set_coalesce = skge_set_coalesce,
713 .get_sg = ethtool_op_get_sg,
714 .set_sg = skge_set_sg,
715 .get_tx_csum = ethtool_op_get_tx_csum,
716 .set_tx_csum = skge_set_tx_csum,
717 .get_rx_csum = skge_get_rx_csum,
718 .set_rx_csum = skge_set_rx_csum,
719 .get_strings = skge_get_strings,
720 .phys_id = skge_phys_id,
721 .get_stats_count = skge_get_stats_count,
722 .get_ethtool_stats = skge_get_ethtool_stats,
723 .get_perm_addr = ethtool_op_get_perm_addr,
724 };
725
726 /*
727 * Allocate ring elements and chain them together
728 * One-to-one association of board descriptors with ring elements
729 */
730 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
731 {
732 struct skge_tx_desc *d;
733 struct skge_element *e;
734 int i;
735
736 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
737 if (!ring->start)
738 return -ENOMEM;
739
740 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
741 e->desc = d;
742 if (i == ring->count - 1) {
743 e->next = ring->start;
744 d->next_offset = base;
745 } else {
746 e->next = e + 1;
747 d->next_offset = base + (i+1) * sizeof(*d);
748 }
749 }
750 ring->to_use = ring->to_clean = ring->start;
751
752 return 0;
753 }
754
755 /* Allocate and setup a new buffer for receiving */
756 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
757 struct sk_buff *skb, unsigned int bufsize)
758 {
759 struct skge_rx_desc *rd = e->desc;
760 u64 map;
761
762 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
763 PCI_DMA_FROMDEVICE);
764
765 rd->dma_lo = map;
766 rd->dma_hi = map >> 32;
767 e->skb = skb;
768 rd->csum1_start = ETH_HLEN;
769 rd->csum2_start = ETH_HLEN;
770 rd->csum1 = 0;
771 rd->csum2 = 0;
772
773 wmb();
774
775 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
776 pci_unmap_addr_set(e, mapaddr, map);
777 pci_unmap_len_set(e, maplen, bufsize);
778 }
779
780 /* Resume receiving using existing skb,
781 * Note: DMA address is not changed by chip.
782 * MTU not changed while receiver active.
783 */
784 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
785 {
786 struct skge_rx_desc *rd = e->desc;
787
788 rd->csum2 = 0;
789 rd->csum2_start = ETH_HLEN;
790
791 wmb();
792
793 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
794 }
795
796
797 /* Free all buffers in receive ring, assumes receiver stopped */
798 static void skge_rx_clean(struct skge_port *skge)
799 {
800 struct skge_hw *hw = skge->hw;
801 struct skge_ring *ring = &skge->rx_ring;
802 struct skge_element *e;
803
804 e = ring->start;
805 do {
806 struct skge_rx_desc *rd = e->desc;
807 rd->control = 0;
808 if (e->skb) {
809 pci_unmap_single(hw->pdev,
810 pci_unmap_addr(e, mapaddr),
811 pci_unmap_len(e, maplen),
812 PCI_DMA_FROMDEVICE);
813 dev_kfree_skb(e->skb);
814 e->skb = NULL;
815 }
816 } while ((e = e->next) != ring->start);
817 }
818
819
820 /* Allocate buffers for receive ring
821 * For receive: to_clean is next received frame.
822 */
823 static int skge_rx_fill(struct skge_port *skge)
824 {
825 struct skge_ring *ring = &skge->rx_ring;
826 struct skge_element *e;
827
828 e = ring->start;
829 do {
830 struct sk_buff *skb;
831
832 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
833 if (!skb)
834 return -ENOMEM;
835
836 skb_reserve(skb, NET_IP_ALIGN);
837 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
838 } while ( (e = e->next) != ring->start);
839
840 ring->to_clean = ring->start;
841 return 0;
842 }
843
844 static void skge_link_up(struct skge_port *skge)
845 {
846 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
847 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
848
849 netif_carrier_on(skge->netdev);
850 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
851 netif_wake_queue(skge->netdev);
852
853 if (netif_msg_link(skge))
854 printk(KERN_INFO PFX
855 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
856 skge->netdev->name, skge->speed,
857 skge->duplex == DUPLEX_FULL ? "full" : "half",
858 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
859 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
860 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
861 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
862 "unknown");
863 }
864
865 static void skge_link_down(struct skge_port *skge)
866 {
867 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
868 netif_carrier_off(skge->netdev);
869 netif_stop_queue(skge->netdev);
870
871 if (netif_msg_link(skge))
872 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
873 }
874
875 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
876 {
877 int i;
878
879 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
880 *val = xm_read16(hw, port, XM_PHY_DATA);
881
882 for (i = 0; i < PHY_RETRIES; i++) {
883 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
884 goto ready;
885 udelay(1);
886 }
887
888 return -ETIMEDOUT;
889 ready:
890 *val = xm_read16(hw, port, XM_PHY_DATA);
891
892 return 0;
893 }
894
895 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
896 {
897 u16 v = 0;
898 if (__xm_phy_read(hw, port, reg, &v))
899 printk(KERN_WARNING PFX "%s: phy read timed out\n",
900 hw->dev[port]->name);
901 return v;
902 }
903
904 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
905 {
906 int i;
907
908 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
909 for (i = 0; i < PHY_RETRIES; i++) {
910 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
911 goto ready;
912 udelay(1);
913 }
914 return -EIO;
915
916 ready:
917 xm_write16(hw, port, XM_PHY_DATA, val);
918 for (i = 0; i < PHY_RETRIES; i++) {
919 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
920 return 0;
921 udelay(1);
922 }
923 return -ETIMEDOUT;
924 }
925
926 static void genesis_init(struct skge_hw *hw)
927 {
928 /* set blink source counter */
929 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
930 skge_write8(hw, B2_BSC_CTRL, BSC_START);
931
932 /* configure mac arbiter */
933 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
934
935 /* configure mac arbiter timeout values */
936 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
937 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
940
941 skge_write8(hw, B3_MA_RCINI_RX1, 0);
942 skge_write8(hw, B3_MA_RCINI_RX2, 0);
943 skge_write8(hw, B3_MA_RCINI_TX1, 0);
944 skge_write8(hw, B3_MA_RCINI_TX2, 0);
945
946 /* configure packet arbiter timeout */
947 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
948 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
949 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
952 }
953
954 static void genesis_reset(struct skge_hw *hw, int port)
955 {
956 const u8 zero[8] = { 0 };
957
958 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
959
960 /* reset the statistics module */
961 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
962 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
963 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
964 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
965 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
966
967 /* disable Broadcom PHY IRQ */
968 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
969
970 xm_outhash(hw, port, XM_HSM, zero);
971 }
972
973
974 /* Convert mode to MII values */
975 static const u16 phy_pause_map[] = {
976 [FLOW_MODE_NONE] = 0,
977 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
978 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
979 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
980 };
981
982
983 /* Check status of Broadcom phy link */
984 static void bcom_check_link(struct skge_hw *hw, int port)
985 {
986 struct net_device *dev = hw->dev[port];
987 struct skge_port *skge = netdev_priv(dev);
988 u16 status;
989
990 /* read twice because of latch */
991 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
992 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
993
994 if ((status & PHY_ST_LSYNC) == 0) {
995 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
996 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
997 xm_write16(hw, port, XM_MMU_CMD, cmd);
998 /* dummy read to ensure writing */
999 (void) xm_read16(hw, port, XM_MMU_CMD);
1000
1001 if (netif_carrier_ok(dev))
1002 skge_link_down(skge);
1003 } else {
1004 if (skge->autoneg == AUTONEG_ENABLE &&
1005 (status & PHY_ST_AN_OVER)) {
1006 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1007 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1008
1009 if (lpa & PHY_B_AN_RF) {
1010 printk(KERN_NOTICE PFX "%s: remote fault\n",
1011 dev->name);
1012 return;
1013 }
1014
1015 /* Check Duplex mismatch */
1016 switch (aux & PHY_B_AS_AN_RES_MSK) {
1017 case PHY_B_RES_1000FD:
1018 skge->duplex = DUPLEX_FULL;
1019 break;
1020 case PHY_B_RES_1000HD:
1021 skge->duplex = DUPLEX_HALF;
1022 break;
1023 default:
1024 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1025 dev->name);
1026 return;
1027 }
1028
1029
1030 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1031 switch (aux & PHY_B_AS_PAUSE_MSK) {
1032 case PHY_B_AS_PAUSE_MSK:
1033 skge->flow_control = FLOW_MODE_SYMMETRIC;
1034 break;
1035 case PHY_B_AS_PRR:
1036 skge->flow_control = FLOW_MODE_REM_SEND;
1037 break;
1038 case PHY_B_AS_PRT:
1039 skge->flow_control = FLOW_MODE_LOC_SEND;
1040 break;
1041 default:
1042 skge->flow_control = FLOW_MODE_NONE;
1043 }
1044
1045 skge->speed = SPEED_1000;
1046 }
1047
1048 if (!netif_carrier_ok(dev))
1049 genesis_link_up(skge);
1050 }
1051 }
1052
1053 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1054 * Phy on for 100 or 10Mbit operation
1055 */
1056 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1057 {
1058 struct skge_hw *hw = skge->hw;
1059 int port = skge->port;
1060 int i;
1061 u16 id1, r, ext, ctl;
1062
1063 /* magic workaround patterns for Broadcom */
1064 static const struct {
1065 u16 reg;
1066 u16 val;
1067 } A1hack[] = {
1068 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1069 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1070 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1071 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1072 }, C0hack[] = {
1073 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1074 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1075 };
1076
1077 /* read Id from external PHY (all have the same address) */
1078 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1079
1080 /* Optimize MDIO transfer by suppressing preamble. */
1081 r = xm_read16(hw, port, XM_MMU_CMD);
1082 r |= XM_MMU_NO_PRE;
1083 xm_write16(hw, port, XM_MMU_CMD,r);
1084
1085 switch (id1) {
1086 case PHY_BCOM_ID1_C0:
1087 /*
1088 * Workaround BCOM Errata for the C0 type.
1089 * Write magic patterns to reserved registers.
1090 */
1091 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1092 xm_phy_write(hw, port,
1093 C0hack[i].reg, C0hack[i].val);
1094
1095 break;
1096 case PHY_BCOM_ID1_A1:
1097 /*
1098 * Workaround BCOM Errata for the A1 type.
1099 * Write magic patterns to reserved registers.
1100 */
1101 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1102 xm_phy_write(hw, port,
1103 A1hack[i].reg, A1hack[i].val);
1104 break;
1105 }
1106
1107 /*
1108 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1109 * Disable Power Management after reset.
1110 */
1111 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1112 r |= PHY_B_AC_DIS_PM;
1113 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1114
1115 /* Dummy read */
1116 xm_read16(hw, port, XM_ISRC);
1117
1118 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1119 ctl = PHY_CT_SP1000; /* always 1000mbit */
1120
1121 if (skge->autoneg == AUTONEG_ENABLE) {
1122 /*
1123 * Workaround BCOM Errata #1 for the C5 type.
1124 * 1000Base-T Link Acquisition Failure in Slave Mode
1125 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1126 */
1127 u16 adv = PHY_B_1000C_RD;
1128 if (skge->advertising & ADVERTISED_1000baseT_Half)
1129 adv |= PHY_B_1000C_AHD;
1130 if (skge->advertising & ADVERTISED_1000baseT_Full)
1131 adv |= PHY_B_1000C_AFD;
1132 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1133
1134 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1135 } else {
1136 if (skge->duplex == DUPLEX_FULL)
1137 ctl |= PHY_CT_DUP_MD;
1138 /* Force to slave */
1139 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1140 }
1141
1142 /* Set autonegotiation pause parameters */
1143 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1144 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1145
1146 /* Handle Jumbo frames */
1147 if (jumbo) {
1148 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1149 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1150
1151 ext |= PHY_B_PEC_HIGH_LA;
1152
1153 }
1154
1155 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1156 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1157
1158 /* Use link status change interrupt */
1159 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1160
1161 bcom_check_link(hw, port);
1162 }
1163
1164 static void genesis_mac_init(struct skge_hw *hw, int port)
1165 {
1166 struct net_device *dev = hw->dev[port];
1167 struct skge_port *skge = netdev_priv(dev);
1168 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1169 int i;
1170 u32 r;
1171 const u8 zero[6] = { 0 };
1172
1173 for (i = 0; i < 10; i++) {
1174 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1175 MFF_SET_MAC_RST);
1176 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1177 goto reset_ok;
1178 udelay(1);
1179 }
1180
1181 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1182
1183 reset_ok:
1184 /* Unreset the XMAC. */
1185 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1186
1187 /*
1188 * Perform additional initialization for external PHYs,
1189 * namely for the 1000baseTX cards that use the XMAC's
1190 * GMII mode.
1191 */
1192 /* Take external Phy out of reset */
1193 r = skge_read32(hw, B2_GP_IO);
1194 if (port == 0)
1195 r |= GP_DIR_0|GP_IO_0;
1196 else
1197 r |= GP_DIR_2|GP_IO_2;
1198
1199 skge_write32(hw, B2_GP_IO, r);
1200
1201
1202 /* Enable GMII interface */
1203 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1204
1205 bcom_phy_init(skge, jumbo);
1206
1207 /* Set Station Address */
1208 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1209
1210 /* We don't use match addresses so clear */
1211 for (i = 1; i < 16; i++)
1212 xm_outaddr(hw, port, XM_EXM(i), zero);
1213
1214 /* Clear MIB counters */
1215 xm_write16(hw, port, XM_STAT_CMD,
1216 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1217 /* Clear two times according to Errata #3 */
1218 xm_write16(hw, port, XM_STAT_CMD,
1219 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1220
1221 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1222 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1223
1224 /* We don't need the FCS appended to the packet. */
1225 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1226 if (jumbo)
1227 r |= XM_RX_BIG_PK_OK;
1228
1229 if (skge->duplex == DUPLEX_HALF) {
1230 /*
1231 * If in manual half duplex mode the other side might be in
1232 * full duplex mode, so ignore if a carrier extension is not seen
1233 * on frames received
1234 */
1235 r |= XM_RX_DIS_CEXT;
1236 }
1237 xm_write16(hw, port, XM_RX_CMD, r);
1238
1239
1240 /* We want short frames padded to 60 bytes. */
1241 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1242
1243 /*
1244 * Bump up the transmit threshold. This helps hold off transmit
1245 * underruns when we're blasting traffic from both ports at once.
1246 */
1247 xm_write16(hw, port, XM_TX_THR, 512);
1248
1249 /*
1250 * Enable the reception of all error frames. This is is
1251 * a necessary evil due to the design of the XMAC. The
1252 * XMAC's receive FIFO is only 8K in size, however jumbo
1253 * frames can be up to 9000 bytes in length. When bad
1254 * frame filtering is enabled, the XMAC's RX FIFO operates
1255 * in 'store and forward' mode. For this to work, the
1256 * entire frame has to fit into the FIFO, but that means
1257 * that jumbo frames larger than 8192 bytes will be
1258 * truncated. Disabling all bad frame filtering causes
1259 * the RX FIFO to operate in streaming mode, in which
1260 * case the XMAC will start transferring frames out of the
1261 * RX FIFO as soon as the FIFO threshold is reached.
1262 */
1263 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1264
1265
1266 /*
1267 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1268 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1269 * and 'Octets Rx OK Hi Cnt Ov'.
1270 */
1271 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1272
1273 /*
1274 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1275 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1276 * and 'Octets Tx OK Hi Cnt Ov'.
1277 */
1278 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1279
1280 /* Configure MAC arbiter */
1281 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1282
1283 /* configure timeout values */
1284 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1285 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1286 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1287 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1288
1289 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1290 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1291 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1292 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1293
1294 /* Configure Rx MAC FIFO */
1295 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1296 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1297 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1298
1299 /* Configure Tx MAC FIFO */
1300 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1301 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1302 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1303
1304 if (jumbo) {
1305 /* Enable frame flushing if jumbo frames used */
1306 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1307 } else {
1308 /* enable timeout timers if normal frames */
1309 skge_write16(hw, B3_PA_CTRL,
1310 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1311 }
1312 }
1313
1314 static void genesis_stop(struct skge_port *skge)
1315 {
1316 struct skge_hw *hw = skge->hw;
1317 int port = skge->port;
1318 u32 reg;
1319
1320 genesis_reset(hw, port);
1321
1322 /* Clear Tx packet arbiter timeout IRQ */
1323 skge_write16(hw, B3_PA_CTRL,
1324 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1325
1326 /*
1327 * If the transfer sticks at the MAC the STOP command will not
1328 * terminate if we don't flush the XMAC's transmit FIFO !
1329 */
1330 xm_write32(hw, port, XM_MODE,
1331 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1332
1333
1334 /* Reset the MAC */
1335 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1336
1337 /* For external PHYs there must be special handling */
1338 reg = skge_read32(hw, B2_GP_IO);
1339 if (port == 0) {
1340 reg |= GP_DIR_0;
1341 reg &= ~GP_IO_0;
1342 } else {
1343 reg |= GP_DIR_2;
1344 reg &= ~GP_IO_2;
1345 }
1346 skge_write32(hw, B2_GP_IO, reg);
1347 skge_read32(hw, B2_GP_IO);
1348
1349 xm_write16(hw, port, XM_MMU_CMD,
1350 xm_read16(hw, port, XM_MMU_CMD)
1351 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1352
1353 xm_read16(hw, port, XM_MMU_CMD);
1354 }
1355
1356
1357 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1358 {
1359 struct skge_hw *hw = skge->hw;
1360 int port = skge->port;
1361 int i;
1362 unsigned long timeout = jiffies + HZ;
1363
1364 xm_write16(hw, port,
1365 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1366
1367 /* wait for update to complete */
1368 while (xm_read16(hw, port, XM_STAT_CMD)
1369 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1370 if (time_after(jiffies, timeout))
1371 break;
1372 udelay(10);
1373 }
1374
1375 /* special case for 64 bit octet counter */
1376 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1377 | xm_read32(hw, port, XM_TXO_OK_LO);
1378 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1379 | xm_read32(hw, port, XM_RXO_OK_LO);
1380
1381 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1382 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1383 }
1384
1385 static void genesis_mac_intr(struct skge_hw *hw, int port)
1386 {
1387 struct skge_port *skge = netdev_priv(hw->dev[port]);
1388 u16 status = xm_read16(hw, port, XM_ISRC);
1389
1390 if (netif_msg_intr(skge))
1391 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1392 skge->netdev->name, status);
1393
1394 if (status & XM_IS_TXF_UR) {
1395 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1396 ++skge->net_stats.tx_fifo_errors;
1397 }
1398 if (status & XM_IS_RXF_OV) {
1399 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1400 ++skge->net_stats.rx_fifo_errors;
1401 }
1402 }
1403
1404 static void genesis_link_up(struct skge_port *skge)
1405 {
1406 struct skge_hw *hw = skge->hw;
1407 int port = skge->port;
1408 u16 cmd;
1409 u32 mode, msk;
1410
1411 cmd = xm_read16(hw, port, XM_MMU_CMD);
1412
1413 /*
1414 * enabling pause frame reception is required for 1000BT
1415 * because the XMAC is not reset if the link is going down
1416 */
1417 if (skge->flow_control == FLOW_MODE_NONE ||
1418 skge->flow_control == FLOW_MODE_LOC_SEND)
1419 /* Disable Pause Frame Reception */
1420 cmd |= XM_MMU_IGN_PF;
1421 else
1422 /* Enable Pause Frame Reception */
1423 cmd &= ~XM_MMU_IGN_PF;
1424
1425 xm_write16(hw, port, XM_MMU_CMD, cmd);
1426
1427 mode = xm_read32(hw, port, XM_MODE);
1428 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1429 skge->flow_control == FLOW_MODE_LOC_SEND) {
1430 /*
1431 * Configure Pause Frame Generation
1432 * Use internal and external Pause Frame Generation.
1433 * Sending pause frames is edge triggered.
1434 * Send a Pause frame with the maximum pause time if
1435 * internal oder external FIFO full condition occurs.
1436 * Send a zero pause time frame to re-start transmission.
1437 */
1438 /* XM_PAUSE_DA = '010000C28001' (default) */
1439 /* XM_MAC_PTIME = 0xffff (maximum) */
1440 /* remember this value is defined in big endian (!) */
1441 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1442
1443 mode |= XM_PAUSE_MODE;
1444 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1445 } else {
1446 /*
1447 * disable pause frame generation is required for 1000BT
1448 * because the XMAC is not reset if the link is going down
1449 */
1450 /* Disable Pause Mode in Mode Register */
1451 mode &= ~XM_PAUSE_MODE;
1452
1453 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1454 }
1455
1456 xm_write32(hw, port, XM_MODE, mode);
1457
1458 msk = XM_DEF_MSK;
1459 /* disable GP0 interrupt bit for external Phy */
1460 msk |= XM_IS_INP_ASS;
1461
1462 xm_write16(hw, port, XM_IMSK, msk);
1463 xm_read16(hw, port, XM_ISRC);
1464
1465 /* get MMU Command Reg. */
1466 cmd = xm_read16(hw, port, XM_MMU_CMD);
1467 if (skge->duplex == DUPLEX_FULL)
1468 cmd |= XM_MMU_GMII_FD;
1469
1470 /*
1471 * Workaround BCOM Errata (#10523) for all BCom Phys
1472 * Enable Power Management after link up
1473 */
1474 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1475 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1476 & ~PHY_B_AC_DIS_PM);
1477 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1478
1479 /* enable Rx/Tx */
1480 xm_write16(hw, port, XM_MMU_CMD,
1481 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1482 skge_link_up(skge);
1483 }
1484
1485
1486 static inline void bcom_phy_intr(struct skge_port *skge)
1487 {
1488 struct skge_hw *hw = skge->hw;
1489 int port = skge->port;
1490 u16 isrc;
1491
1492 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1493 if (netif_msg_intr(skge))
1494 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1495 skge->netdev->name, isrc);
1496
1497 if (isrc & PHY_B_IS_PSE)
1498 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1499 hw->dev[port]->name);
1500
1501 /* Workaround BCom Errata:
1502 * enable and disable loopback mode if "NO HCD" occurs.
1503 */
1504 if (isrc & PHY_B_IS_NO_HDCL) {
1505 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1506 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1507 ctrl | PHY_CT_LOOP);
1508 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1509 ctrl & ~PHY_CT_LOOP);
1510 }
1511
1512 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1513 bcom_check_link(hw, port);
1514
1515 }
1516
1517 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1518 {
1519 int i;
1520
1521 gma_write16(hw, port, GM_SMI_DATA, val);
1522 gma_write16(hw, port, GM_SMI_CTRL,
1523 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1524 for (i = 0; i < PHY_RETRIES; i++) {
1525 udelay(1);
1526
1527 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1528 return 0;
1529 }
1530
1531 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1532 hw->dev[port]->name);
1533 return -EIO;
1534 }
1535
1536 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1537 {
1538 int i;
1539
1540 gma_write16(hw, port, GM_SMI_CTRL,
1541 GM_SMI_CT_PHY_AD(hw->phy_addr)
1542 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1543
1544 for (i = 0; i < PHY_RETRIES; i++) {
1545 udelay(1);
1546 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1547 goto ready;
1548 }
1549
1550 return -ETIMEDOUT;
1551 ready:
1552 *val = gma_read16(hw, port, GM_SMI_DATA);
1553 return 0;
1554 }
1555
1556 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1557 {
1558 u16 v = 0;
1559 if (__gm_phy_read(hw, port, reg, &v))
1560 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1561 hw->dev[port]->name);
1562 return v;
1563 }
1564
1565 /* Marvell Phy Initialization */
1566 static void yukon_init(struct skge_hw *hw, int port)
1567 {
1568 struct skge_port *skge = netdev_priv(hw->dev[port]);
1569 u16 ctrl, ct1000, adv;
1570
1571 if (skge->autoneg == AUTONEG_ENABLE) {
1572 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1573
1574 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1575 PHY_M_EC_MAC_S_MSK);
1576 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1577
1578 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1579
1580 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1581 }
1582
1583 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1584 if (skge->autoneg == AUTONEG_DISABLE)
1585 ctrl &= ~PHY_CT_ANE;
1586
1587 ctrl |= PHY_CT_RESET;
1588 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1589
1590 ctrl = 0;
1591 ct1000 = 0;
1592 adv = PHY_AN_CSMA;
1593
1594 if (skge->autoneg == AUTONEG_ENABLE) {
1595 if (hw->copper) {
1596 if (skge->advertising & ADVERTISED_1000baseT_Full)
1597 ct1000 |= PHY_M_1000C_AFD;
1598 if (skge->advertising & ADVERTISED_1000baseT_Half)
1599 ct1000 |= PHY_M_1000C_AHD;
1600 if (skge->advertising & ADVERTISED_100baseT_Full)
1601 adv |= PHY_M_AN_100_FD;
1602 if (skge->advertising & ADVERTISED_100baseT_Half)
1603 adv |= PHY_M_AN_100_HD;
1604 if (skge->advertising & ADVERTISED_10baseT_Full)
1605 adv |= PHY_M_AN_10_FD;
1606 if (skge->advertising & ADVERTISED_10baseT_Half)
1607 adv |= PHY_M_AN_10_HD;
1608 } else /* special defines for FIBER (88E1011S only) */
1609 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1610
1611 /* Set Flow-control capabilities */
1612 adv |= phy_pause_map[skge->flow_control];
1613
1614 /* Restart Auto-negotiation */
1615 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1616 } else {
1617 /* forced speed/duplex settings */
1618 ct1000 = PHY_M_1000C_MSE;
1619
1620 if (skge->duplex == DUPLEX_FULL)
1621 ctrl |= PHY_CT_DUP_MD;
1622
1623 switch (skge->speed) {
1624 case SPEED_1000:
1625 ctrl |= PHY_CT_SP1000;
1626 break;
1627 case SPEED_100:
1628 ctrl |= PHY_CT_SP100;
1629 break;
1630 }
1631
1632 ctrl |= PHY_CT_RESET;
1633 }
1634
1635 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1636
1637 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1638 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1639
1640 /* Enable phy interrupt on autonegotiation complete (or link up) */
1641 if (skge->autoneg == AUTONEG_ENABLE)
1642 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1643 else
1644 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1645 }
1646
1647 static void yukon_reset(struct skge_hw *hw, int port)
1648 {
1649 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1650 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1651 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1652 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1653 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1654
1655 gma_write16(hw, port, GM_RX_CTRL,
1656 gma_read16(hw, port, GM_RX_CTRL)
1657 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1658 }
1659
1660 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1661 static int is_yukon_lite_a0(struct skge_hw *hw)
1662 {
1663 u32 reg;
1664 int ret;
1665
1666 if (hw->chip_id != CHIP_ID_YUKON)
1667 return 0;
1668
1669 reg = skge_read32(hw, B2_FAR);
1670 skge_write8(hw, B2_FAR + 3, 0xff);
1671 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1672 skge_write32(hw, B2_FAR, reg);
1673 return ret;
1674 }
1675
1676 static void yukon_mac_init(struct skge_hw *hw, int port)
1677 {
1678 struct skge_port *skge = netdev_priv(hw->dev[port]);
1679 int i;
1680 u32 reg;
1681 const u8 *addr = hw->dev[port]->dev_addr;
1682
1683 /* WA code for COMA mode -- set PHY reset */
1684 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1685 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1686 reg = skge_read32(hw, B2_GP_IO);
1687 reg |= GP_DIR_9 | GP_IO_9;
1688 skge_write32(hw, B2_GP_IO, reg);
1689 }
1690
1691 /* hard reset */
1692 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1693 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1694
1695 /* WA code for COMA mode -- clear PHY reset */
1696 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1697 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1698 reg = skge_read32(hw, B2_GP_IO);
1699 reg |= GP_DIR_9;
1700 reg &= ~GP_IO_9;
1701 skge_write32(hw, B2_GP_IO, reg);
1702 }
1703
1704 /* Set hardware config mode */
1705 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1706 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1707 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1708
1709 /* Clear GMC reset */
1710 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1711 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1712 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1713
1714 if (skge->autoneg == AUTONEG_DISABLE) {
1715 reg = GM_GPCR_AU_ALL_DIS;
1716 gma_write16(hw, port, GM_GP_CTRL,
1717 gma_read16(hw, port, GM_GP_CTRL) | reg);
1718
1719 switch (skge->speed) {
1720 case SPEED_1000:
1721 reg &= ~GM_GPCR_SPEED_100;
1722 reg |= GM_GPCR_SPEED_1000;
1723 break;
1724 case SPEED_100:
1725 reg &= ~GM_GPCR_SPEED_1000;
1726 reg |= GM_GPCR_SPEED_100;
1727 break;
1728 case SPEED_10:
1729 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1730 break;
1731 }
1732
1733 if (skge->duplex == DUPLEX_FULL)
1734 reg |= GM_GPCR_DUP_FULL;
1735 } else
1736 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1737
1738 switch (skge->flow_control) {
1739 case FLOW_MODE_NONE:
1740 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1741 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1742 break;
1743 case FLOW_MODE_LOC_SEND:
1744 /* disable Rx flow-control */
1745 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1746 }
1747
1748 gma_write16(hw, port, GM_GP_CTRL, reg);
1749 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1750
1751 yukon_init(hw, port);
1752
1753 /* MIB clear */
1754 reg = gma_read16(hw, port, GM_PHY_ADDR);
1755 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1756
1757 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1758 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1759 gma_write16(hw, port, GM_PHY_ADDR, reg);
1760
1761 /* transmit control */
1762 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1763
1764 /* receive control reg: unicast + multicast + no FCS */
1765 gma_write16(hw, port, GM_RX_CTRL,
1766 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1767
1768 /* transmit flow control */
1769 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1770
1771 /* transmit parameter */
1772 gma_write16(hw, port, GM_TX_PARAM,
1773 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1774 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1775 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1776
1777 /* serial mode register */
1778 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1779 if (hw->dev[port]->mtu > 1500)
1780 reg |= GM_SMOD_JUMBO_ENA;
1781
1782 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1783
1784 /* physical address: used for pause frames */
1785 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1786 /* virtual address for data */
1787 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1788
1789 /* enable interrupt mask for counter overflows */
1790 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1791 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1792 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1793
1794 /* Initialize Mac Fifo */
1795
1796 /* Configure Rx MAC FIFO */
1797 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1798 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1799
1800 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1801 if (is_yukon_lite_a0(hw))
1802 reg &= ~GMF_RX_F_FL_ON;
1803
1804 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1805 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1806 /*
1807 * because Pause Packet Truncation in GMAC is not working
1808 * we have to increase the Flush Threshold to 64 bytes
1809 * in order to flush pause packets in Rx FIFO on Yukon-1
1810 */
1811 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1812
1813 /* Configure Tx MAC FIFO */
1814 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1815 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1816 }
1817
1818 /* Go into power down mode */
1819 static void yukon_suspend(struct skge_hw *hw, int port)
1820 {
1821 u16 ctrl;
1822
1823 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1824 ctrl |= PHY_M_PC_POL_R_DIS;
1825 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1826
1827 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1828 ctrl |= PHY_CT_RESET;
1829 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1830
1831 /* switch IEEE compatible power down mode on */
1832 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1833 ctrl |= PHY_CT_PDOWN;
1834 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1835 }
1836
1837 static void yukon_stop(struct skge_port *skge)
1838 {
1839 struct skge_hw *hw = skge->hw;
1840 int port = skge->port;
1841
1842 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1843 yukon_reset(hw, port);
1844
1845 gma_write16(hw, port, GM_GP_CTRL,
1846 gma_read16(hw, port, GM_GP_CTRL)
1847 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1848 gma_read16(hw, port, GM_GP_CTRL);
1849
1850 yukon_suspend(hw, port);
1851
1852 /* set GPHY Control reset */
1853 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1854 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1855 }
1856
1857 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1858 {
1859 struct skge_hw *hw = skge->hw;
1860 int port = skge->port;
1861 int i;
1862
1863 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1864 | gma_read32(hw, port, GM_TXO_OK_LO);
1865 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1866 | gma_read32(hw, port, GM_RXO_OK_LO);
1867
1868 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1869 data[i] = gma_read32(hw, port,
1870 skge_stats[i].gma_offset);
1871 }
1872
1873 static void yukon_mac_intr(struct skge_hw *hw, int port)
1874 {
1875 struct net_device *dev = hw->dev[port];
1876 struct skge_port *skge = netdev_priv(dev);
1877 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1878
1879 if (netif_msg_intr(skge))
1880 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1881 dev->name, status);
1882
1883 if (status & GM_IS_RX_FF_OR) {
1884 ++skge->net_stats.rx_fifo_errors;
1885 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1886 }
1887
1888 if (status & GM_IS_TX_FF_UR) {
1889 ++skge->net_stats.tx_fifo_errors;
1890 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1891 }
1892
1893 }
1894
1895 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1896 {
1897 switch (aux & PHY_M_PS_SPEED_MSK) {
1898 case PHY_M_PS_SPEED_1000:
1899 return SPEED_1000;
1900 case PHY_M_PS_SPEED_100:
1901 return SPEED_100;
1902 default:
1903 return SPEED_10;
1904 }
1905 }
1906
1907 static void yukon_link_up(struct skge_port *skge)
1908 {
1909 struct skge_hw *hw = skge->hw;
1910 int port = skge->port;
1911 u16 reg;
1912
1913 /* Enable Transmit FIFO Underrun */
1914 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1915
1916 reg = gma_read16(hw, port, GM_GP_CTRL);
1917 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1918 reg |= GM_GPCR_DUP_FULL;
1919
1920 /* enable Rx/Tx */
1921 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1922 gma_write16(hw, port, GM_GP_CTRL, reg);
1923
1924 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1925 skge_link_up(skge);
1926 }
1927
1928 static void yukon_link_down(struct skge_port *skge)
1929 {
1930 struct skge_hw *hw = skge->hw;
1931 int port = skge->port;
1932 u16 ctrl;
1933
1934 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1935
1936 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1937 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1938 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1939
1940 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1941 /* restore Asymmetric Pause bit */
1942 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1943 gm_phy_read(hw, port,
1944 PHY_MARV_AUNE_ADV)
1945 | PHY_M_AN_ASP);
1946
1947 }
1948
1949 yukon_reset(hw, port);
1950 skge_link_down(skge);
1951
1952 yukon_init(hw, port);
1953 }
1954
1955 static void yukon_phy_intr(struct skge_port *skge)
1956 {
1957 struct skge_hw *hw = skge->hw;
1958 int port = skge->port;
1959 const char *reason = NULL;
1960 u16 istatus, phystat;
1961
1962 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1963 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1964
1965 if (netif_msg_intr(skge))
1966 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1967 skge->netdev->name, istatus, phystat);
1968
1969 if (istatus & PHY_M_IS_AN_COMPL) {
1970 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1971 & PHY_M_AN_RF) {
1972 reason = "remote fault";
1973 goto failed;
1974 }
1975
1976 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1977 reason = "master/slave fault";
1978 goto failed;
1979 }
1980
1981 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1982 reason = "speed/duplex";
1983 goto failed;
1984 }
1985
1986 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1987 ? DUPLEX_FULL : DUPLEX_HALF;
1988 skge->speed = yukon_speed(hw, phystat);
1989
1990 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1991 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1992 case PHY_M_PS_PAUSE_MSK:
1993 skge->flow_control = FLOW_MODE_SYMMETRIC;
1994 break;
1995 case PHY_M_PS_RX_P_EN:
1996 skge->flow_control = FLOW_MODE_REM_SEND;
1997 break;
1998 case PHY_M_PS_TX_P_EN:
1999 skge->flow_control = FLOW_MODE_LOC_SEND;
2000 break;
2001 default:
2002 skge->flow_control = FLOW_MODE_NONE;
2003 }
2004
2005 if (skge->flow_control == FLOW_MODE_NONE ||
2006 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2007 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2008 else
2009 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2010 yukon_link_up(skge);
2011 return;
2012 }
2013
2014 if (istatus & PHY_M_IS_LSP_CHANGE)
2015 skge->speed = yukon_speed(hw, phystat);
2016
2017 if (istatus & PHY_M_IS_DUP_CHANGE)
2018 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2019 if (istatus & PHY_M_IS_LST_CHANGE) {
2020 if (phystat & PHY_M_PS_LINK_UP)
2021 yukon_link_up(skge);
2022 else
2023 yukon_link_down(skge);
2024 }
2025 return;
2026 failed:
2027 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2028 skge->netdev->name, reason);
2029
2030 /* XXX restart autonegotiation? */
2031 }
2032
2033 static void skge_phy_reset(struct skge_port *skge)
2034 {
2035 struct skge_hw *hw = skge->hw;
2036 int port = skge->port;
2037
2038 netif_stop_queue(skge->netdev);
2039 netif_carrier_off(skge->netdev);
2040
2041 spin_lock_bh(&hw->phy_lock);
2042 if (hw->chip_id == CHIP_ID_GENESIS) {
2043 genesis_reset(hw, port);
2044 genesis_mac_init(hw, port);
2045 } else {
2046 yukon_reset(hw, port);
2047 yukon_init(hw, port);
2048 }
2049 spin_unlock_bh(&hw->phy_lock);
2050 }
2051
2052 /* Basic MII support */
2053 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2054 {
2055 struct mii_ioctl_data *data = if_mii(ifr);
2056 struct skge_port *skge = netdev_priv(dev);
2057 struct skge_hw *hw = skge->hw;
2058 int err = -EOPNOTSUPP;
2059
2060 if (!netif_running(dev))
2061 return -ENODEV; /* Phy still in reset */
2062
2063 switch(cmd) {
2064 case SIOCGMIIPHY:
2065 data->phy_id = hw->phy_addr;
2066
2067 /* fallthru */
2068 case SIOCGMIIREG: {
2069 u16 val = 0;
2070 spin_lock_bh(&hw->phy_lock);
2071 if (hw->chip_id == CHIP_ID_GENESIS)
2072 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2073 else
2074 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2075 spin_unlock_bh(&hw->phy_lock);
2076 data->val_out = val;
2077 break;
2078 }
2079
2080 case SIOCSMIIREG:
2081 if (!capable(CAP_NET_ADMIN))
2082 return -EPERM;
2083
2084 spin_lock_bh(&hw->phy_lock);
2085 if (hw->chip_id == CHIP_ID_GENESIS)
2086 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2087 data->val_in);
2088 else
2089 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2090 data->val_in);
2091 spin_unlock_bh(&hw->phy_lock);
2092 break;
2093 }
2094 return err;
2095 }
2096
2097 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2098 {
2099 u32 end;
2100
2101 start /= 8;
2102 len /= 8;
2103 end = start + len - 1;
2104
2105 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2106 skge_write32(hw, RB_ADDR(q, RB_START), start);
2107 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2108 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2109 skge_write32(hw, RB_ADDR(q, RB_END), end);
2110
2111 if (q == Q_R1 || q == Q_R2) {
2112 /* Set thresholds on receive queue's */
2113 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2114 start + (2*len)/3);
2115 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2116 start + (len/3));
2117 } else {
2118 /* Enable store & forward on Tx queue's because
2119 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2120 */
2121 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2122 }
2123
2124 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2125 }
2126
2127 /* Setup Bus Memory Interface */
2128 static void skge_qset(struct skge_port *skge, u16 q,
2129 const struct skge_element *e)
2130 {
2131 struct skge_hw *hw = skge->hw;
2132 u32 watermark = 0x600;
2133 u64 base = skge->dma + (e->desc - skge->mem);
2134
2135 /* optimization to reduce window on 32bit/33mhz */
2136 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2137 watermark /= 2;
2138
2139 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2140 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2141 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2142 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2143 }
2144
2145 static int skge_up(struct net_device *dev)
2146 {
2147 struct skge_port *skge = netdev_priv(dev);
2148 struct skge_hw *hw = skge->hw;
2149 int port = skge->port;
2150 u32 chunk, ram_addr;
2151 size_t rx_size, tx_size;
2152 int err;
2153
2154 if (netif_msg_ifup(skge))
2155 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2156
2157 if (dev->mtu > RX_BUF_SIZE)
2158 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2159 else
2160 skge->rx_buf_size = RX_BUF_SIZE;
2161
2162
2163 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2164 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2165 skge->mem_size = tx_size + rx_size;
2166 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2167 if (!skge->mem)
2168 return -ENOMEM;
2169
2170 BUG_ON(skge->dma & 7);
2171
2172 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2173 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2174 err = -EINVAL;
2175 goto free_pci_mem;
2176 }
2177
2178 memset(skge->mem, 0, skge->mem_size);
2179
2180 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2181 goto free_pci_mem;
2182
2183 err = skge_rx_fill(skge);
2184 if (err)
2185 goto free_rx_ring;
2186
2187 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2188 skge->dma + rx_size)))
2189 goto free_rx_ring;
2190
2191 skge->tx_avail = skge->tx_ring.count - 1;
2192
2193 /* Initialize MAC */
2194 spin_lock_bh(&hw->phy_lock);
2195 if (hw->chip_id == CHIP_ID_GENESIS)
2196 genesis_mac_init(hw, port);
2197 else
2198 yukon_mac_init(hw, port);
2199 spin_unlock_bh(&hw->phy_lock);
2200
2201 /* Configure RAMbuffers */
2202 chunk = hw->ram_size / ((hw->ports + 1)*2);
2203 ram_addr = hw->ram_offset + 2 * chunk * port;
2204
2205 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2206 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2207
2208 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2209 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2210 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2211
2212 /* Start receiver BMU */
2213 wmb();
2214 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2215 skge_led(skge, LED_MODE_ON);
2216
2217 return 0;
2218
2219 free_rx_ring:
2220 skge_rx_clean(skge);
2221 kfree(skge->rx_ring.start);
2222 free_pci_mem:
2223 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2224 skge->mem = NULL;
2225
2226 return err;
2227 }
2228
2229 static int skge_down(struct net_device *dev)
2230 {
2231 struct skge_port *skge = netdev_priv(dev);
2232 struct skge_hw *hw = skge->hw;
2233 int port = skge->port;
2234
2235 if (skge->mem == NULL)
2236 return 0;
2237
2238 if (netif_msg_ifdown(skge))
2239 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2240
2241 netif_stop_queue(dev);
2242
2243 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2244 if (hw->chip_id == CHIP_ID_GENESIS)
2245 genesis_stop(skge);
2246 else
2247 yukon_stop(skge);
2248
2249 /* Stop transmitter */
2250 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2251 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2252 RB_RST_SET|RB_DIS_OP_MD);
2253
2254
2255 /* Disable Force Sync bit and Enable Alloc bit */
2256 skge_write8(hw, SK_REG(port, TXA_CTRL),
2257 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2258
2259 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2260 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2261 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2262
2263 /* Reset PCI FIFO */
2264 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2265 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2266
2267 /* Reset the RAM Buffer async Tx queue */
2268 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2269 /* stop receiver */
2270 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2271 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2272 RB_RST_SET|RB_DIS_OP_MD);
2273 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2274
2275 if (hw->chip_id == CHIP_ID_GENESIS) {
2276 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2277 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2278 } else {
2279 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2280 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2281 }
2282
2283 skge_led(skge, LED_MODE_OFF);
2284
2285 skge_tx_clean(skge);
2286 skge_rx_clean(skge);
2287
2288 kfree(skge->rx_ring.start);
2289 kfree(skge->tx_ring.start);
2290 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2291 skge->mem = NULL;
2292 return 0;
2293 }
2294
2295 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2296 {
2297 struct skge_port *skge = netdev_priv(dev);
2298 struct skge_hw *hw = skge->hw;
2299 struct skge_ring *ring = &skge->tx_ring;
2300 struct skge_element *e;
2301 struct skge_tx_desc *td;
2302 int i;
2303 u32 control, len;
2304 u64 map;
2305
2306 skb = skb_padto(skb, ETH_ZLEN);
2307 if (!skb)
2308 return NETDEV_TX_OK;
2309
2310 if (!spin_trylock(&skge->tx_lock)) {
2311 /* Collision - tell upper layer to requeue */
2312 return NETDEV_TX_LOCKED;
2313 }
2314
2315 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2316 if (!netif_queue_stopped(dev)) {
2317 netif_stop_queue(dev);
2318
2319 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2320 dev->name);
2321 }
2322 spin_unlock(&skge->tx_lock);
2323 return NETDEV_TX_BUSY;
2324 }
2325
2326 e = ring->to_use;
2327 td = e->desc;
2328 e->skb = skb;
2329 len = skb_headlen(skb);
2330 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2331 pci_unmap_addr_set(e, mapaddr, map);
2332 pci_unmap_len_set(e, maplen, len);
2333
2334 td->dma_lo = map;
2335 td->dma_hi = map >> 32;
2336
2337 if (skb->ip_summed == CHECKSUM_HW) {
2338 int offset = skb->h.raw - skb->data;
2339
2340 /* This seems backwards, but it is what the sk98lin
2341 * does. Looks like hardware is wrong?
2342 */
2343 if (skb->h.ipiph->protocol == IPPROTO_UDP
2344 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2345 control = BMU_TCP_CHECK;
2346 else
2347 control = BMU_UDP_CHECK;
2348
2349 td->csum_offs = 0;
2350 td->csum_start = offset;
2351 td->csum_write = offset + skb->csum;
2352 } else
2353 control = BMU_CHECK;
2354
2355 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2356 control |= BMU_EOF| BMU_IRQ_EOF;
2357 else {
2358 struct skge_tx_desc *tf = td;
2359
2360 control |= BMU_STFWD;
2361 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2362 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2363
2364 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2365 frag->size, PCI_DMA_TODEVICE);
2366
2367 e = e->next;
2368 e->skb = NULL;
2369 tf = e->desc;
2370 tf->dma_lo = map;
2371 tf->dma_hi = (u64) map >> 32;
2372 pci_unmap_addr_set(e, mapaddr, map);
2373 pci_unmap_len_set(e, maplen, frag->size);
2374
2375 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2376 }
2377 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2378 }
2379 /* Make sure all the descriptors written */
2380 wmb();
2381 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2382 wmb();
2383
2384 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2385
2386 if (netif_msg_tx_queued(skge))
2387 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2388 dev->name, e - ring->start, skb->len);
2389
2390 ring->to_use = e->next;
2391 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2392 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2393 pr_debug("%s: transmit queue full\n", dev->name);
2394 netif_stop_queue(dev);
2395 }
2396
2397 dev->trans_start = jiffies;
2398 spin_unlock(&skge->tx_lock);
2399
2400 return NETDEV_TX_OK;
2401 }
2402
2403 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2404 {
2405 /* This ring element can be skb or fragment */
2406 if (e->skb) {
2407 pci_unmap_single(hw->pdev,
2408 pci_unmap_addr(e, mapaddr),
2409 pci_unmap_len(e, maplen),
2410 PCI_DMA_TODEVICE);
2411 dev_kfree_skb(e->skb);
2412 e->skb = NULL;
2413 } else {
2414 pci_unmap_page(hw->pdev,
2415 pci_unmap_addr(e, mapaddr),
2416 pci_unmap_len(e, maplen),
2417 PCI_DMA_TODEVICE);
2418 }
2419 }
2420
2421 static void skge_tx_clean(struct skge_port *skge)
2422 {
2423 struct skge_ring *ring = &skge->tx_ring;
2424 struct skge_element *e;
2425
2426 spin_lock_bh(&skge->tx_lock);
2427 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2428 ++skge->tx_avail;
2429 skge_tx_free(skge->hw, e);
2430 }
2431 ring->to_clean = e;
2432 spin_unlock_bh(&skge->tx_lock);
2433 }
2434
2435 static void skge_tx_timeout(struct net_device *dev)
2436 {
2437 struct skge_port *skge = netdev_priv(dev);
2438
2439 if (netif_msg_timer(skge))
2440 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2441
2442 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2443 skge_tx_clean(skge);
2444 }
2445
2446 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2447 {
2448 int err;
2449
2450 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2451 return -EINVAL;
2452
2453 if (!netif_running(dev)) {
2454 dev->mtu = new_mtu;
2455 return 0;
2456 }
2457
2458 skge_down(dev);
2459
2460 dev->mtu = new_mtu;
2461
2462 err = skge_up(dev);
2463 if (err)
2464 dev_close(dev);
2465
2466 return err;
2467 }
2468
2469 static void genesis_set_multicast(struct net_device *dev)
2470 {
2471 struct skge_port *skge = netdev_priv(dev);
2472 struct skge_hw *hw = skge->hw;
2473 int port = skge->port;
2474 int i, count = dev->mc_count;
2475 struct dev_mc_list *list = dev->mc_list;
2476 u32 mode;
2477 u8 filter[8];
2478
2479 mode = xm_read32(hw, port, XM_MODE);
2480 mode |= XM_MD_ENA_HASH;
2481 if (dev->flags & IFF_PROMISC)
2482 mode |= XM_MD_ENA_PROM;
2483 else
2484 mode &= ~XM_MD_ENA_PROM;
2485
2486 if (dev->flags & IFF_ALLMULTI)
2487 memset(filter, 0xff, sizeof(filter));
2488 else {
2489 memset(filter, 0, sizeof(filter));
2490 for (i = 0; list && i < count; i++, list = list->next) {
2491 u32 crc, bit;
2492 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2493 bit = ~crc & 0x3f;
2494 filter[bit/8] |= 1 << (bit%8);
2495 }
2496 }
2497
2498 xm_write32(hw, port, XM_MODE, mode);
2499 xm_outhash(hw, port, XM_HSM, filter);
2500 }
2501
2502 static void yukon_set_multicast(struct net_device *dev)
2503 {
2504 struct skge_port *skge = netdev_priv(dev);
2505 struct skge_hw *hw = skge->hw;
2506 int port = skge->port;
2507 struct dev_mc_list *list = dev->mc_list;
2508 u16 reg;
2509 u8 filter[8];
2510
2511 memset(filter, 0, sizeof(filter));
2512
2513 reg = gma_read16(hw, port, GM_RX_CTRL);
2514 reg |= GM_RXCR_UCF_ENA;
2515
2516 if (dev->flags & IFF_PROMISC) /* promiscuous */
2517 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2518 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2519 memset(filter, 0xff, sizeof(filter));
2520 else if (dev->mc_count == 0) /* no multicast */
2521 reg &= ~GM_RXCR_MCF_ENA;
2522 else {
2523 int i;
2524 reg |= GM_RXCR_MCF_ENA;
2525
2526 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2527 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2528 filter[bit/8] |= 1 << (bit%8);
2529 }
2530 }
2531
2532
2533 gma_write16(hw, port, GM_MC_ADDR_H1,
2534 (u16)filter[0] | ((u16)filter[1] << 8));
2535 gma_write16(hw, port, GM_MC_ADDR_H2,
2536 (u16)filter[2] | ((u16)filter[3] << 8));
2537 gma_write16(hw, port, GM_MC_ADDR_H3,
2538 (u16)filter[4] | ((u16)filter[5] << 8));
2539 gma_write16(hw, port, GM_MC_ADDR_H4,
2540 (u16)filter[6] | ((u16)filter[7] << 8));
2541
2542 gma_write16(hw, port, GM_RX_CTRL, reg);
2543 }
2544
2545 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2546 {
2547 if (hw->chip_id == CHIP_ID_GENESIS)
2548 return status >> XMR_FS_LEN_SHIFT;
2549 else
2550 return status >> GMR_FS_LEN_SHIFT;
2551 }
2552
2553 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2554 {
2555 if (hw->chip_id == CHIP_ID_GENESIS)
2556 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2557 else
2558 return (status & GMR_FS_ANY_ERR) ||
2559 (status & GMR_FS_RX_OK) == 0;
2560 }
2561
2562
2563 /* Get receive buffer from descriptor.
2564 * Handles copy of small buffers and reallocation failures
2565 */
2566 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2567 struct skge_element *e,
2568 u32 control, u32 status, u16 csum)
2569 {
2570 struct sk_buff *skb;
2571 u16 len = control & BMU_BBC;
2572
2573 if (unlikely(netif_msg_rx_status(skge)))
2574 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2575 skge->netdev->name, e - skge->rx_ring.start,
2576 status, len);
2577
2578 if (len > skge->rx_buf_size)
2579 goto error;
2580
2581 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2582 goto error;
2583
2584 if (bad_phy_status(skge->hw, status))
2585 goto error;
2586
2587 if (phy_length(skge->hw, status) != len)
2588 goto error;
2589
2590 if (len < RX_COPY_THRESHOLD) {
2591 skb = dev_alloc_skb(len + 2);
2592 if (!skb)
2593 goto resubmit;
2594
2595 skb_reserve(skb, 2);
2596 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2597 pci_unmap_addr(e, mapaddr),
2598 len, PCI_DMA_FROMDEVICE);
2599 memcpy(skb->data, e->skb->data, len);
2600 pci_dma_sync_single_for_device(skge->hw->pdev,
2601 pci_unmap_addr(e, mapaddr),
2602 len, PCI_DMA_FROMDEVICE);
2603 skge_rx_reuse(e, skge->rx_buf_size);
2604 } else {
2605 struct sk_buff *nskb;
2606 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2607 if (!nskb)
2608 goto resubmit;
2609
2610 pci_unmap_single(skge->hw->pdev,
2611 pci_unmap_addr(e, mapaddr),
2612 pci_unmap_len(e, maplen),
2613 PCI_DMA_FROMDEVICE);
2614 skb = e->skb;
2615 prefetch(skb->data);
2616 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2617 }
2618
2619 skb_put(skb, len);
2620 skb->dev = skge->netdev;
2621 if (skge->rx_csum) {
2622 skb->csum = csum;
2623 skb->ip_summed = CHECKSUM_HW;
2624 }
2625
2626 skb->protocol = eth_type_trans(skb, skge->netdev);
2627
2628 return skb;
2629 error:
2630
2631 if (netif_msg_rx_err(skge))
2632 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2633 skge->netdev->name, e - skge->rx_ring.start,
2634 control, status);
2635
2636 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2637 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2638 skge->net_stats.rx_length_errors++;
2639 if (status & XMR_FS_FRA_ERR)
2640 skge->net_stats.rx_frame_errors++;
2641 if (status & XMR_FS_FCS_ERR)
2642 skge->net_stats.rx_crc_errors++;
2643 } else {
2644 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2645 skge->net_stats.rx_length_errors++;
2646 if (status & GMR_FS_FRAGMENT)
2647 skge->net_stats.rx_frame_errors++;
2648 if (status & GMR_FS_CRC_ERR)
2649 skge->net_stats.rx_crc_errors++;
2650 }
2651
2652 resubmit:
2653 skge_rx_reuse(e, skge->rx_buf_size);
2654 return NULL;
2655 }
2656
2657 static void skge_tx_done(struct skge_port *skge)
2658 {
2659 struct skge_ring *ring = &skge->tx_ring;
2660 struct skge_element *e;
2661
2662 spin_lock(&skge->tx_lock);
2663 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2664 struct skge_tx_desc *td = e->desc;
2665 u32 control;
2666
2667 rmb();
2668 control = td->control;
2669 if (control & BMU_OWN)
2670 break;
2671
2672 if (unlikely(netif_msg_tx_done(skge)))
2673 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2674 skge->netdev->name, e - ring->start, td->status);
2675
2676 skge_tx_free(skge->hw, e);
2677 e->skb = NULL;
2678 ++skge->tx_avail;
2679 }
2680 ring->to_clean = e;
2681 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2682
2683 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2684 netif_wake_queue(skge->netdev);
2685
2686 spin_unlock(&skge->tx_lock);
2687 }
2688
2689 static int skge_poll(struct net_device *dev, int *budget)
2690 {
2691 struct skge_port *skge = netdev_priv(dev);
2692 struct skge_hw *hw = skge->hw;
2693 struct skge_ring *ring = &skge->rx_ring;
2694 struct skge_element *e;
2695 int to_do = min(dev->quota, *budget);
2696 int work_done = 0;
2697
2698 skge_tx_done(skge);
2699
2700 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2701 struct skge_rx_desc *rd = e->desc;
2702 struct sk_buff *skb;
2703 u32 control;
2704
2705 rmb();
2706 control = rd->control;
2707 if (control & BMU_OWN)
2708 break;
2709
2710 skb = skge_rx_get(skge, e, control, rd->status,
2711 le16_to_cpu(rd->csum2));
2712 if (likely(skb)) {
2713 dev->last_rx = jiffies;
2714 netif_receive_skb(skb);
2715
2716 ++work_done;
2717 } else
2718 skge_rx_reuse(e, skge->rx_buf_size);
2719 }
2720 ring->to_clean = e;
2721
2722 /* restart receiver */
2723 wmb();
2724 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2725
2726 *budget -= work_done;
2727 dev->quota -= work_done;
2728
2729 if (work_done >= to_do)
2730 return 1; /* not done */
2731
2732 netif_rx_complete(dev);
2733 hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);
2734 skge_write32(hw, B0_IMSK, hw->intr_mask);
2735
2736 return 0;
2737 }
2738
2739 /* Parity errors seem to happen when Genesis is connected to a switch
2740 * with no other ports present. Heartbeat error??
2741 */
2742 static void skge_mac_parity(struct skge_hw *hw, int port)
2743 {
2744 struct net_device *dev = hw->dev[port];
2745
2746 if (dev) {
2747 struct skge_port *skge = netdev_priv(dev);
2748 ++skge->net_stats.tx_heartbeat_errors;
2749 }
2750
2751 if (hw->chip_id == CHIP_ID_GENESIS)
2752 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2753 MFF_CLR_PERR);
2754 else
2755 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2756 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2757 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2758 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2759 }
2760
2761 static void skge_pci_clear(struct skge_hw *hw)
2762 {
2763 u16 status;
2764
2765 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2766 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2767 pci_write_config_word(hw->pdev, PCI_STATUS,
2768 status | PCI_STATUS_ERROR_BITS);
2769 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2770 }
2771
2772 static void skge_mac_intr(struct skge_hw *hw, int port)
2773 {
2774 if (hw->chip_id == CHIP_ID_GENESIS)
2775 genesis_mac_intr(hw, port);
2776 else
2777 yukon_mac_intr(hw, port);
2778 }
2779
2780 /* Handle device specific framing and timeout interrupts */
2781 static void skge_error_irq(struct skge_hw *hw)
2782 {
2783 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2784
2785 if (hw->chip_id == CHIP_ID_GENESIS) {
2786 /* clear xmac errors */
2787 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2788 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2789 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2790 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2791 } else {
2792 /* Timestamp (unused) overflow */
2793 if (hwstatus & IS_IRQ_TIST_OV)
2794 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2795 }
2796
2797 if (hwstatus & IS_RAM_RD_PAR) {
2798 printk(KERN_ERR PFX "Ram read data parity error\n");
2799 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2800 }
2801
2802 if (hwstatus & IS_RAM_WR_PAR) {
2803 printk(KERN_ERR PFX "Ram write data parity error\n");
2804 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2805 }
2806
2807 if (hwstatus & IS_M1_PAR_ERR)
2808 skge_mac_parity(hw, 0);
2809
2810 if (hwstatus & IS_M2_PAR_ERR)
2811 skge_mac_parity(hw, 1);
2812
2813 if (hwstatus & IS_R1_PAR_ERR)
2814 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2815
2816 if (hwstatus & IS_R2_PAR_ERR)
2817 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2818
2819 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2820 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2821 hwstatus);
2822
2823 skge_pci_clear(hw);
2824
2825 /* if error still set then just ignore it */
2826 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2827 if (hwstatus & IS_IRQ_STAT) {
2828 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2829 hwstatus);
2830 hw->intr_mask &= ~IS_HW_ERR;
2831 }
2832 }
2833 }
2834
2835 /*
2836 * Interrupt from PHY are handled in tasklet (soft irq)
2837 * because accessing phy registers requires spin wait which might
2838 * cause excess interrupt latency.
2839 */
2840 static void skge_extirq(unsigned long data)
2841 {
2842 struct skge_hw *hw = (struct skge_hw *) data;
2843 int port;
2844
2845 spin_lock(&hw->phy_lock);
2846 for (port = 0; port < hw->ports; port++) {
2847 struct net_device *dev = hw->dev[port];
2848 struct skge_port *skge = netdev_priv(dev);
2849
2850 if (netif_running(dev)) {
2851 if (hw->chip_id != CHIP_ID_GENESIS)
2852 yukon_phy_intr(skge);
2853 else
2854 bcom_phy_intr(skge);
2855 }
2856 }
2857 spin_unlock(&hw->phy_lock);
2858
2859 hw->intr_mask |= IS_EXT_REG;
2860 skge_write32(hw, B0_IMSK, hw->intr_mask);
2861 }
2862
2863 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2864 {
2865 struct skge_hw *hw = dev_id;
2866 u32 status;
2867
2868 /* Reading this register masks IRQ */
2869 status = skge_read32(hw, B0_SP_ISRC);
2870 if (status == 0)
2871 return IRQ_NONE;
2872
2873 if (status & IS_EXT_REG) {
2874 hw->intr_mask &= ~IS_EXT_REG;
2875 tasklet_schedule(&hw->ext_tasklet);
2876 }
2877
2878 if (status & (IS_R1_F|IS_XA1_F)) {
2879 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2880 hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);
2881 netif_rx_schedule(hw->dev[0]);
2882 }
2883
2884 if (status & (IS_R2_F|IS_XA2_F)) {
2885 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2886 hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);
2887 netif_rx_schedule(hw->dev[1]);
2888 }
2889
2890 if (likely((status & hw->intr_mask) == 0))
2891 return IRQ_HANDLED;
2892
2893 if (status & IS_PA_TO_RX1) {
2894 struct skge_port *skge = netdev_priv(hw->dev[0]);
2895 ++skge->net_stats.rx_over_errors;
2896 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2897 }
2898
2899 if (status & IS_PA_TO_RX2) {
2900 struct skge_port *skge = netdev_priv(hw->dev[1]);
2901 ++skge->net_stats.rx_over_errors;
2902 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2903 }
2904
2905 if (status & IS_PA_TO_TX1)
2906 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2907
2908 if (status & IS_PA_TO_TX2)
2909 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2910
2911 if (status & IS_MAC1)
2912 skge_mac_intr(hw, 0);
2913
2914 if (status & IS_MAC2)
2915 skge_mac_intr(hw, 1);
2916
2917 if (status & IS_HW_ERR)
2918 skge_error_irq(hw);
2919
2920 skge_write32(hw, B0_IMSK, hw->intr_mask);
2921
2922 return IRQ_HANDLED;
2923 }
2924
2925 #ifdef CONFIG_NET_POLL_CONTROLLER
2926 static void skge_netpoll(struct net_device *dev)
2927 {
2928 struct skge_port *skge = netdev_priv(dev);
2929
2930 disable_irq(dev->irq);
2931 skge_intr(dev->irq, skge->hw, NULL);
2932 enable_irq(dev->irq);
2933 }
2934 #endif
2935
2936 static int skge_set_mac_address(struct net_device *dev, void *p)
2937 {
2938 struct skge_port *skge = netdev_priv(dev);
2939 struct skge_hw *hw = skge->hw;
2940 unsigned port = skge->port;
2941 const struct sockaddr *addr = p;
2942
2943 if (!is_valid_ether_addr(addr->sa_data))
2944 return -EADDRNOTAVAIL;
2945
2946 spin_lock_bh(&hw->phy_lock);
2947 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2948 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2949 dev->dev_addr, ETH_ALEN);
2950 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2951 dev->dev_addr, ETH_ALEN);
2952
2953 if (hw->chip_id == CHIP_ID_GENESIS)
2954 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2955 else {
2956 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2957 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2958 }
2959 spin_unlock_bh(&hw->phy_lock);
2960
2961 return 0;
2962 }
2963
2964 static const struct {
2965 u8 id;
2966 const char *name;
2967 } skge_chips[] = {
2968 { CHIP_ID_GENESIS, "Genesis" },
2969 { CHIP_ID_YUKON, "Yukon" },
2970 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2971 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2972 };
2973
2974 static const char *skge_board_name(const struct skge_hw *hw)
2975 {
2976 int i;
2977 static char buf[16];
2978
2979 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2980 if (skge_chips[i].id == hw->chip_id)
2981 return skge_chips[i].name;
2982
2983 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2984 return buf;
2985 }
2986
2987
2988 /*
2989 * Setup the board data structure, but don't bring up
2990 * the port(s)
2991 */
2992 static int skge_reset(struct skge_hw *hw)
2993 {
2994 u32 reg;
2995 u16 ctst;
2996 u8 t8, mac_cfg, pmd_type, phy_type;
2997 int i;
2998
2999 ctst = skge_read16(hw, B0_CTST);
3000
3001 /* do a SW reset */
3002 skge_write8(hw, B0_CTST, CS_RST_SET);
3003 skge_write8(hw, B0_CTST, CS_RST_CLR);
3004
3005 /* clear PCI errors, if any */
3006 skge_pci_clear(hw);
3007
3008 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3009
3010 /* restore CLK_RUN bits (for Yukon-Lite) */
3011 skge_write16(hw, B0_CTST,
3012 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3013
3014 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3015 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3016 pmd_type = skge_read8(hw, B2_PMD_TYP);
3017 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3018
3019 switch (hw->chip_id) {
3020 case CHIP_ID_GENESIS:
3021 switch (phy_type) {
3022 case SK_PHY_BCOM:
3023 hw->phy_addr = PHY_ADDR_BCOM;
3024 break;
3025 default:
3026 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3027 pci_name(hw->pdev), phy_type);
3028 return -EOPNOTSUPP;
3029 }
3030 break;
3031
3032 case CHIP_ID_YUKON:
3033 case CHIP_ID_YUKON_LITE:
3034 case CHIP_ID_YUKON_LP:
3035 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3036 hw->copper = 1;
3037
3038 hw->phy_addr = PHY_ADDR_MARV;
3039 break;
3040
3041 default:
3042 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3043 pci_name(hw->pdev), hw->chip_id);
3044 return -EOPNOTSUPP;
3045 }
3046
3047 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3048 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3049 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3050
3051 /* read the adapters RAM size */
3052 t8 = skge_read8(hw, B2_E_0);
3053 if (hw->chip_id == CHIP_ID_GENESIS) {
3054 if (t8 == 3) {
3055 /* special case: 4 x 64k x 36, offset = 0x80000 */
3056 hw->ram_size = 0x100000;
3057 hw->ram_offset = 0x80000;
3058 } else
3059 hw->ram_size = t8 * 512;
3060 }
3061 else if (t8 == 0)
3062 hw->ram_size = 0x20000;
3063 else
3064 hw->ram_size = t8 * 4096;
3065
3066 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3067 if (hw->ports > 1)
3068 hw->intr_mask |= IS_PORT_2;
3069
3070 if (hw->chip_id == CHIP_ID_GENESIS)
3071 genesis_init(hw);
3072 else {
3073 /* switch power to VCC (WA for VAUX problem) */
3074 skge_write8(hw, B0_POWER_CTRL,
3075 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3076
3077 /* avoid boards with stuck Hardware error bits */
3078 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3079 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3080 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3081 hw->intr_mask &= ~IS_HW_ERR;
3082 }
3083
3084 /* Clear PHY COMA */
3085 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3086 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3087 reg &= ~PCI_PHY_COMA;
3088 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3089 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3090
3091
3092 for (i = 0; i < hw->ports; i++) {
3093 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3094 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3095 }
3096 }
3097
3098 /* turn off hardware timer (unused) */
3099 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3100 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3101 skge_write8(hw, B0_LED, LED_STAT_ON);
3102
3103 /* enable the Tx Arbiters */
3104 for (i = 0; i < hw->ports; i++)
3105 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3106
3107 /* Initialize ram interface */
3108 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3109
3110 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3111 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3112 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3113 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3114 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3115 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3116 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3117 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3118 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3119 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3120 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3121 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3122
3123 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3124
3125 /* Set interrupt moderation for Transmit only
3126 * Receive interrupts avoided by NAPI
3127 */
3128 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3129 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3130 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3131
3132 skge_write32(hw, B0_IMSK, hw->intr_mask);
3133
3134 spin_lock_bh(&hw->phy_lock);
3135 for (i = 0; i < hw->ports; i++) {
3136 if (hw->chip_id == CHIP_ID_GENESIS)
3137 genesis_reset(hw, i);
3138 else
3139 yukon_reset(hw, i);
3140 }
3141 spin_unlock_bh(&hw->phy_lock);
3142
3143 return 0;
3144 }
3145
3146 /* Initialize network device */
3147 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3148 int highmem)
3149 {
3150 struct skge_port *skge;
3151 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3152
3153 if (!dev) {
3154 printk(KERN_ERR "skge etherdev alloc failed");
3155 return NULL;
3156 }
3157
3158 SET_MODULE_OWNER(dev);
3159 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3160 dev->open = skge_up;
3161 dev->stop = skge_down;
3162 dev->do_ioctl = skge_ioctl;
3163 dev->hard_start_xmit = skge_xmit_frame;
3164 dev->get_stats = skge_get_stats;
3165 if (hw->chip_id == CHIP_ID_GENESIS)
3166 dev->set_multicast_list = genesis_set_multicast;
3167 else
3168 dev->set_multicast_list = yukon_set_multicast;
3169
3170 dev->set_mac_address = skge_set_mac_address;
3171 dev->change_mtu = skge_change_mtu;
3172 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3173 dev->tx_timeout = skge_tx_timeout;
3174 dev->watchdog_timeo = TX_WATCHDOG;
3175 dev->poll = skge_poll;
3176 dev->weight = NAPI_WEIGHT;
3177 #ifdef CONFIG_NET_POLL_CONTROLLER
3178 dev->poll_controller = skge_netpoll;
3179 #endif
3180 dev->irq = hw->pdev->irq;
3181 dev->features = NETIF_F_LLTX;
3182 if (highmem)
3183 dev->features |= NETIF_F_HIGHDMA;
3184
3185 skge = netdev_priv(dev);
3186 skge->netdev = dev;
3187 skge->hw = hw;
3188 skge->msg_enable = netif_msg_init(debug, default_msg);
3189 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3190 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3191
3192 /* Auto speed and flow control */
3193 skge->autoneg = AUTONEG_ENABLE;
3194 skge->flow_control = FLOW_MODE_SYMMETRIC;
3195 skge->duplex = -1;
3196 skge->speed = -1;
3197 skge->advertising = skge_supported_modes(hw);
3198
3199 hw->dev[port] = dev;
3200
3201 skge->port = port;
3202
3203 spin_lock_init(&skge->tx_lock);
3204
3205 if (hw->chip_id != CHIP_ID_GENESIS) {
3206 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3207 skge->rx_csum = 1;
3208 }
3209
3210 /* read the mac address */
3211 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3212 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3213
3214 /* device is off until link detection */
3215 netif_carrier_off(dev);
3216 netif_stop_queue(dev);
3217
3218 return dev;
3219 }
3220
3221 static void __devinit skge_show_addr(struct net_device *dev)
3222 {
3223 const struct skge_port *skge = netdev_priv(dev);
3224
3225 if (netif_msg_probe(skge))
3226 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3227 dev->name,
3228 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3229 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3230 }
3231
3232 static int __devinit skge_probe(struct pci_dev *pdev,
3233 const struct pci_device_id *ent)
3234 {
3235 struct net_device *dev, *dev1;
3236 struct skge_hw *hw;
3237 int err, using_dac = 0;
3238
3239 if ((err = pci_enable_device(pdev))) {
3240 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3241 pci_name(pdev));
3242 goto err_out;
3243 }
3244
3245 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3246 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3247 pci_name(pdev));
3248 goto err_out_disable_pdev;
3249 }
3250
3251 pci_set_master(pdev);
3252
3253 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3254 using_dac = 1;
3255 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3256 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3257 using_dac = 0;
3258 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3259 }
3260
3261 if (err) {
3262 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3263 pci_name(pdev));
3264 goto err_out_free_regions;
3265 }
3266
3267 #ifdef __BIG_ENDIAN
3268 /* byte swap descriptors in hardware */
3269 {
3270 u32 reg;
3271
3272 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3273 reg |= PCI_REV_DESC;
3274 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3275 }
3276 #endif
3277
3278 err = -ENOMEM;
3279 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3280 if (!hw) {
3281 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3282 pci_name(pdev));
3283 goto err_out_free_regions;
3284 }
3285
3286 hw->pdev = pdev;
3287 spin_lock_init(&hw->phy_lock);
3288 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3289
3290 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3291 if (!hw->regs) {
3292 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3293 pci_name(pdev));
3294 goto err_out_free_hw;
3295 }
3296
3297 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3298 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3299 pci_name(pdev), pdev->irq);
3300 goto err_out_iounmap;
3301 }
3302 pci_set_drvdata(pdev, hw);
3303
3304 err = skge_reset(hw);
3305 if (err)
3306 goto err_out_free_irq;
3307
3308 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3309 pci_resource_start(pdev, 0), pdev->irq,
3310 skge_board_name(hw), hw->chip_rev);
3311
3312 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3313 goto err_out_led_off;
3314
3315 if ((err = register_netdev(dev))) {
3316 printk(KERN_ERR PFX "%s: cannot register net device\n",
3317 pci_name(pdev));
3318 goto err_out_free_netdev;
3319 }
3320
3321 skge_show_addr(dev);
3322
3323 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3324 if (register_netdev(dev1) == 0)
3325 skge_show_addr(dev1);
3326 else {
3327 /* Failure to register second port need not be fatal */
3328 printk(KERN_WARNING PFX "register of second port failed\n");
3329 hw->dev[1] = NULL;
3330 free_netdev(dev1);
3331 }
3332 }
3333
3334 return 0;
3335
3336 err_out_free_netdev:
3337 free_netdev(dev);
3338 err_out_led_off:
3339 skge_write16(hw, B0_LED, LED_STAT_OFF);
3340 err_out_free_irq:
3341 free_irq(pdev->irq, hw);
3342 err_out_iounmap:
3343 iounmap(hw->regs);
3344 err_out_free_hw:
3345 kfree(hw);
3346 err_out_free_regions:
3347 pci_release_regions(pdev);
3348 err_out_disable_pdev:
3349 pci_disable_device(pdev);
3350 pci_set_drvdata(pdev, NULL);
3351 err_out:
3352 return err;
3353 }
3354
3355 static void __devexit skge_remove(struct pci_dev *pdev)
3356 {
3357 struct skge_hw *hw = pci_get_drvdata(pdev);
3358 struct net_device *dev0, *dev1;
3359
3360 if (!hw)
3361 return;
3362
3363 if ((dev1 = hw->dev[1]))
3364 unregister_netdev(dev1);
3365 dev0 = hw->dev[0];
3366 unregister_netdev(dev0);
3367
3368 skge_write32(hw, B0_IMSK, 0);
3369 skge_write16(hw, B0_LED, LED_STAT_OFF);
3370 skge_pci_clear(hw);
3371 skge_write8(hw, B0_CTST, CS_RST_SET);
3372
3373 tasklet_kill(&hw->ext_tasklet);
3374
3375 free_irq(pdev->irq, hw);
3376 pci_release_regions(pdev);
3377 pci_disable_device(pdev);
3378 if (dev1)
3379 free_netdev(dev1);
3380 free_netdev(dev0);
3381
3382 iounmap(hw->regs);
3383 kfree(hw);
3384 pci_set_drvdata(pdev, NULL);
3385 }
3386
3387 #ifdef CONFIG_PM
3388 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3389 {
3390 struct skge_hw *hw = pci_get_drvdata(pdev);
3391 int i, wol = 0;
3392
3393 for (i = 0; i < 2; i++) {
3394 struct net_device *dev = hw->dev[i];
3395
3396 if (dev) {
3397 struct skge_port *skge = netdev_priv(dev);
3398 if (netif_running(dev)) {
3399 netif_carrier_off(dev);
3400 if (skge->wol)
3401 netif_stop_queue(dev);
3402 else
3403 skge_down(dev);
3404 }
3405 netif_device_detach(dev);
3406 wol |= skge->wol;
3407 }
3408 }
3409
3410 pci_save_state(pdev);
3411 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3412 pci_disable_device(pdev);
3413 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3414
3415 return 0;
3416 }
3417
3418 static int skge_resume(struct pci_dev *pdev)
3419 {
3420 struct skge_hw *hw = pci_get_drvdata(pdev);
3421 int i;
3422
3423 pci_set_power_state(pdev, PCI_D0);
3424 pci_restore_state(pdev);
3425 pci_enable_wake(pdev, PCI_D0, 0);
3426
3427 skge_reset(hw);
3428
3429 for (i = 0; i < 2; i++) {
3430 struct net_device *dev = hw->dev[i];
3431 if (dev) {
3432 netif_device_attach(dev);
3433 if (netif_running(dev) && skge_up(dev))
3434 dev_close(dev);
3435 }
3436 }
3437 return 0;
3438 }
3439 #endif
3440
3441 static struct pci_driver skge_driver = {
3442 .name = DRV_NAME,
3443 .id_table = skge_id_table,
3444 .probe = skge_probe,
3445 .remove = __devexit_p(skge_remove),
3446 #ifdef CONFIG_PM
3447 .suspend = skge_suspend,
3448 .resume = skge_resume,
3449 #endif
3450 };
3451
3452 static int __init skge_init_module(void)
3453 {
3454 return pci_module_init(&skge_driver);
3455 }
3456
3457 static void __exit skge_cleanup_module(void)
3458 {
3459 pci_unregister_driver(&skge_driver);
3460 }
3461
3462 module_init(skge_init_module);
3463 module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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