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Pull memoryless-node-allocation into release branch
[deliverable/linux.git] / drivers / net / skge.h
1 /*
2 * Definitions for the new Marvell Yukon / SysKonenct driver.
3 */
4 #ifndef _SKGE_H
5 #define _SKGE_H
6
7 /* PCI config registers */
8 #define PCI_DEV_REG1 0x40
9 #define PCI_PHY_COMA 0x8000000
10 #define PCI_VIO 0x2000000
11 #define PCI_DEV_REG2 0x44
12 #define PCI_REV_DESC 0x4
13
14 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
15 PCI_STATUS_SIG_SYSTEM_ERROR | \
16 PCI_STATUS_REC_MASTER_ABORT | \
17 PCI_STATUS_REC_TARGET_ABORT | \
18 PCI_STATUS_PARITY)
19
20 enum csr_regs {
21 B0_RAP = 0x0000,
22 B0_CTST = 0x0004,
23 B0_LED = 0x0006,
24 B0_POWER_CTRL = 0x0007,
25 B0_ISRC = 0x0008,
26 B0_IMSK = 0x000c,
27 B0_HWE_ISRC = 0x0010,
28 B0_HWE_IMSK = 0x0014,
29 B0_SP_ISRC = 0x0018,
30 B0_XM1_IMSK = 0x0020,
31 B0_XM1_ISRC = 0x0028,
32 B0_XM1_PHY_ADDR = 0x0030,
33 B0_XM1_PHY_DATA = 0x0034,
34 B0_XM2_IMSK = 0x0040,
35 B0_XM2_ISRC = 0x0048,
36 B0_XM2_PHY_ADDR = 0x0050,
37 B0_XM2_PHY_DATA = 0x0054,
38 B0_R1_CSR = 0x0060,
39 B0_R2_CSR = 0x0064,
40 B0_XS1_CSR = 0x0068,
41 B0_XA1_CSR = 0x006c,
42 B0_XS2_CSR = 0x0070,
43 B0_XA2_CSR = 0x0074,
44
45 B2_MAC_1 = 0x0100,
46 B2_MAC_2 = 0x0108,
47 B2_MAC_3 = 0x0110,
48 B2_CONN_TYP = 0x0118,
49 B2_PMD_TYP = 0x0119,
50 B2_MAC_CFG = 0x011a,
51 B2_CHIP_ID = 0x011b,
52 B2_E_0 = 0x011c,
53 B2_E_1 = 0x011d,
54 B2_E_2 = 0x011e,
55 B2_E_3 = 0x011f,
56 B2_FAR = 0x0120,
57 B2_FDP = 0x0124,
58 B2_LD_CTRL = 0x0128,
59 B2_LD_TEST = 0x0129,
60 B2_TI_INI = 0x0130,
61 B2_TI_VAL = 0x0134,
62 B2_TI_CTRL = 0x0138,
63 B2_TI_TEST = 0x0139,
64 B2_IRQM_INI = 0x0140,
65 B2_IRQM_VAL = 0x0144,
66 B2_IRQM_CTRL = 0x0148,
67 B2_IRQM_TEST = 0x0149,
68 B2_IRQM_MSK = 0x014c,
69 B2_IRQM_HWE_MSK = 0x0150,
70 B2_TST_CTRL1 = 0x0158,
71 B2_TST_CTRL2 = 0x0159,
72 B2_GP_IO = 0x015c,
73 B2_I2C_CTRL = 0x0160,
74 B2_I2C_DATA = 0x0164,
75 B2_I2C_IRQ = 0x0168,
76 B2_I2C_SW = 0x016c,
77 B2_BSC_INI = 0x0170,
78 B2_BSC_VAL = 0x0174,
79 B2_BSC_CTRL = 0x0178,
80 B2_BSC_STAT = 0x0179,
81 B2_BSC_TST = 0x017a,
82
83 B3_RAM_ADDR = 0x0180,
84 B3_RAM_DATA_LO = 0x0184,
85 B3_RAM_DATA_HI = 0x0188,
86 B3_RI_WTO_R1 = 0x0190,
87 B3_RI_WTO_XA1 = 0x0191,
88 B3_RI_WTO_XS1 = 0x0192,
89 B3_RI_RTO_R1 = 0x0193,
90 B3_RI_RTO_XA1 = 0x0194,
91 B3_RI_RTO_XS1 = 0x0195,
92 B3_RI_WTO_R2 = 0x0196,
93 B3_RI_WTO_XA2 = 0x0197,
94 B3_RI_WTO_XS2 = 0x0198,
95 B3_RI_RTO_R2 = 0x0199,
96 B3_RI_RTO_XA2 = 0x019a,
97 B3_RI_RTO_XS2 = 0x019b,
98 B3_RI_TO_VAL = 0x019c,
99 B3_RI_CTRL = 0x01a0,
100 B3_RI_TEST = 0x01a2,
101 B3_MA_TOINI_RX1 = 0x01b0,
102 B3_MA_TOINI_RX2 = 0x01b1,
103 B3_MA_TOINI_TX1 = 0x01b2,
104 B3_MA_TOINI_TX2 = 0x01b3,
105 B3_MA_TOVAL_RX1 = 0x01b4,
106 B3_MA_TOVAL_RX2 = 0x01b5,
107 B3_MA_TOVAL_TX1 = 0x01b6,
108 B3_MA_TOVAL_TX2 = 0x01b7,
109 B3_MA_TO_CTRL = 0x01b8,
110 B3_MA_TO_TEST = 0x01ba,
111 B3_MA_RCINI_RX1 = 0x01c0,
112 B3_MA_RCINI_RX2 = 0x01c1,
113 B3_MA_RCINI_TX1 = 0x01c2,
114 B3_MA_RCINI_TX2 = 0x01c3,
115 B3_MA_RCVAL_RX1 = 0x01c4,
116 B3_MA_RCVAL_RX2 = 0x01c5,
117 B3_MA_RCVAL_TX1 = 0x01c6,
118 B3_MA_RCVAL_TX2 = 0x01c7,
119 B3_MA_RC_CTRL = 0x01c8,
120 B3_MA_RC_TEST = 0x01ca,
121 B3_PA_TOINI_RX1 = 0x01d0,
122 B3_PA_TOINI_RX2 = 0x01d4,
123 B3_PA_TOINI_TX1 = 0x01d8,
124 B3_PA_TOINI_TX2 = 0x01dc,
125 B3_PA_TOVAL_RX1 = 0x01e0,
126 B3_PA_TOVAL_RX2 = 0x01e4,
127 B3_PA_TOVAL_TX1 = 0x01e8,
128 B3_PA_TOVAL_TX2 = 0x01ec,
129 B3_PA_CTRL = 0x01f0,
130 B3_PA_TEST = 0x01f2,
131 };
132
133 /* B0_CTST 16 bit Control/Status register */
134 enum {
135 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
136 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
137 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
139 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
140 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
141 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
142 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
143 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
144 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
145 CS_MRST_CLR = 1<<3, /* Clear Master reset */
146 CS_MRST_SET = 1<<2, /* Set Master reset */
147 CS_RST_CLR = 1<<1, /* Clear Software reset */
148 CS_RST_SET = 1, /* Set Software reset */
149
150 /* B0_LED 8 Bit LED register */
151 /* Bit 7.. 2: reserved */
152 LED_STAT_ON = 1<<1, /* Status LED on */
153 LED_STAT_OFF = 1, /* Status LED off */
154
155 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
156 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
157 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
158 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
159 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
160 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
161 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
162 PC_VCC_ON = 1<<1, /* Switch VCC On */
163 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
164 };
165
166 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
167 enum {
168 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
169 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
170 /* Bit 30: reserved */
171 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
172 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
173 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
174 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
175 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
176 IS_IRQ_SW = 1<<24, /* SW forced IRQ */
177 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
178 /* IRQ from PHY (YUKON only) */
179 IS_TIMINT = 1<<22, /* IRQ from Timer */
180 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
181 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
182 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
183 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
184 /* Receive Queue 1 */
185 IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
186 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
187 IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
188 /* Receive Queue 2 */
189 IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
190 IS_R2_F = 1<<13, /* Q_R2 End of Frame */
191 IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
192 /* Synchronous Transmit Queue 1 */
193 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
194 IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
195 IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
196 /* Asynchronous Transmit Queue 1 */
197 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
198 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
199 IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
200 /* Synchronous Transmit Queue 2 */
201 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
202 IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
203 IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
204 /* Asynchronous Transmit Queue 2 */
205 IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
206 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
207 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
208
209 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
210 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
211
212 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
213 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
214 };
215
216
217 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
218 enum {
219 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
220 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
221 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
222 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
223 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
224 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
225 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
226 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
227 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
228 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
229 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
230 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
231 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
232 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
233
234 IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
235 | IS_NO_STAT_M1 | IS_NO_STAT_M2
236 | IS_RAM_RD_PAR | IS_RAM_WR_PAR
237 | IS_M1_PAR_ERR | IS_M2_PAR_ERR
238 | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
239 };
240
241 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
242 enum {
243 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
244 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
245 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
246 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
247 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
248 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
249 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
250 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
251 };
252
253 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
254 enum {
255 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
256 /* Bit 3.. 2: reserved */
257 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
258 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
259 };
260
261 /* B2_CHIP_ID 8 bit Chip Identification Number */
262 enum {
263 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
264 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
265 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
266 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
267 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
268 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
269 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
270
271 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
272 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
273 };
274
275 /* B2_TI_CTRL 8 bit Timer control */
276 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
277 enum {
278 TIM_START = 1<<2, /* Start Timer */
279 TIM_STOP = 1<<1, /* Stop Timer */
280 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
281 };
282
283 /* B2_TI_TEST 8 Bit Timer Test */
284 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
285 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
286 enum {
287 TIM_T_ON = 1<<2, /* Test mode on */
288 TIM_T_OFF = 1<<1, /* Test mode off */
289 TIM_T_STEP = 1<<0, /* Test step */
290 };
291
292 /* B2_GP_IO 32 bit General Purpose I/O Register */
293 enum {
294 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
295 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
296 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
297 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
298 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
299 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
300 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
301 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
302 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
303 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
304
305 GP_IO_9 = 1<<9, /* IO_9 pin */
306 GP_IO_8 = 1<<8, /* IO_8 pin */
307 GP_IO_7 = 1<<7, /* IO_7 pin */
308 GP_IO_6 = 1<<6, /* IO_6 pin */
309 GP_IO_5 = 1<<5, /* IO_5 pin */
310 GP_IO_4 = 1<<4, /* IO_4 pin */
311 GP_IO_3 = 1<<3, /* IO_3 pin */
312 GP_IO_2 = 1<<2, /* IO_2 pin */
313 GP_IO_1 = 1<<1, /* IO_1 pin */
314 GP_IO_0 = 1<<0, /* IO_0 pin */
315 };
316
317 /* Descriptor Bit Definition */
318 /* TxCtrl Transmit Buffer Control Field */
319 /* RxCtrl Receive Buffer Control Field */
320 enum {
321 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
322 BMU_STF = 1<<30, /* Start of Frame */
323 BMU_EOF = 1<<29, /* End of Frame */
324 BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
325 BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
326 /* TxCtrl specific bits */
327 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
328 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
329 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
330 /* RxCtrl specific bits */
331 BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
332 BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
333 BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
334 /* Bit 23..16: BMU Check Opcodes */
335 BMU_CHECK = 0x55<<16, /* Default BMU check */
336 BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
337 BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
338 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
339 };
340
341 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
342 enum {
343 BSC_START = 1<<1, /* Start Blink Source Counter */
344 BSC_STOP = 1<<0, /* Stop Blink Source Counter */
345 };
346
347 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
348 enum {
349 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
350 };
351
352 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
353 enum {
354 BSC_T_ON = 1<<2, /* Test mode on */
355 BSC_T_OFF = 1<<1, /* Test mode off */
356 BSC_T_STEP = 1<<0, /* Test step */
357 };
358
359 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
360 /* Bit 31..19: reserved */
361 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
362 /* RAM Interface Registers */
363
364 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
365 enum {
366 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
367 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
368
369 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
370 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
371 };
372
373 /* MAC Arbiter Registers */
374 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
375 enum {
376 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
377 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
378 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
379 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
380
381 };
382
383 /* Timeout values */
384 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
385 #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
386 #define SK_PKT_TO_MAX 0xffff /* Maximum value */
387 #define SK_RI_TO_53 36 /* RAM interface timeout */
388
389 /* Packet Arbiter Registers */
390 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
391 enum {
392 PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */
393 PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */
394 PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */
395 PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */
396 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
397 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
398 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
399 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
400 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
401 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
402 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
403 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
404 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
405 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
406 };
407
408 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
409 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
410
411
412 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
413 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
414 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
415 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
416 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
417
418 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
419
420 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
421 enum {
422 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
423 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
424 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
425 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
426 TXA_START_RC = 1<<3, /* Start sync Rate Control */
427 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
428 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
429 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
430 };
431
432 /*
433 * Bank 4 - 5
434 */
435 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
436 enum {
437 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
438 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
439 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
440 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
441 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
442 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
443 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
444 };
445
446
447 enum {
448 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
449 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
450 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
451 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
452 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
453 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
454 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
455 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
456 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
457 };
458
459 /* Queue Register Offsets, use Q_ADDR() to access */
460 enum {
461 B8_Q_REGS = 0x0400, /* base of Queue registers */
462 Q_D = 0x00, /* 8*32 bit Current Descriptor */
463 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
464 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
465 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
466 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
467 Q_BC = 0x30, /* 32 bit Current Byte Counter */
468 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
469 Q_F = 0x38, /* 32 bit Flag Register */
470 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
471 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
472 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
473 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
474 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
475 Q_T2 = 0x40, /* 32 bit Test Register 2 */
476 Q_T3 = 0x44, /* 32 bit Test Register 3 */
477
478 /* Yukon-2 */
479 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
480 Q_WM = 0x40, /* 16 bit FIFO Watermark */
481 Q_AL = 0x42, /* 8 bit FIFO Alignment */
482 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
483 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
484 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
485 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
486 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
487 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
488 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
489 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
490 };
491 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
492
493 /* RAM Buffer Register Offsets */
494 enum {
495
496 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
497 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
498 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
499 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
500 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
501 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
502 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
503 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
504 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
505 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
506 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
507 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
508 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
509 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
510 };
511
512 /* Receive and Transmit Queues */
513 enum {
514 Q_R1 = 0x0000, /* Receive Queue 1 */
515 Q_R2 = 0x0080, /* Receive Queue 2 */
516 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
517 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
518 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
519 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
520 };
521
522 /* Different MAC Types */
523 enum {
524 SK_MAC_XMAC = 0, /* Xaqti XMAC II */
525 SK_MAC_GMAC = 1, /* Marvell GMAC */
526 };
527
528 /* Different PHY Types */
529 enum {
530 SK_PHY_XMAC = 0,/* integrated in XMAC II */
531 SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
532 SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
533 SK_PHY_NAT = 3,/* National DP83891 [not supported] */
534 SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
535 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
536 };
537
538 /* PHY addresses (bits 12..8 of PHY address reg) */
539 enum {
540 PHY_ADDR_XMAC = 0<<8,
541 PHY_ADDR_BCOM = 1<<8,
542
543 /* GPHY address (bits 15..11 of SMI control reg) */
544 PHY_ADDR_MARV = 0,
545 };
546
547 #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
548
549 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
550 enum {
551 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
552 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
553
554 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
555 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
556 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
557 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
558 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
559 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
560 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
561 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
562 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
563
564 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
565 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
566 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
567 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
568
569 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
570 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
571 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
572 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
573 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
574 };
575
576 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
577 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
578 enum {
579 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
580 MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
581 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
582 MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
583 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
584 MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
585 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
586 MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
587 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
588 MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
589 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
590 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
591 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
592 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
593 #define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
594 };
595
596 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
597 enum {
598 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
599 /* Bit 14: reserved */
600 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
601 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
602
603 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
604 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
605
606 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
607 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
608 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
609 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
610 };
611
612 #define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
613
614 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
615 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
616 enum {
617 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
618 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
619 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
620 MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
621 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
622 MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
623 MFF_PC_INC = 1<<0, /* Packet Counter Increment */
624 };
625
626 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
627 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
628 enum {
629 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
630 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
631 MFF_WP_INC = 1<<4, /* Write Pointer Increm */
632
633 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
634 MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
635 MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
636 };
637
638 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
639 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
640 enum {
641 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
642 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
643 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
644 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
645 };
646
647
648 /* Link LED Counter Registers (GENESIS only) */
649
650 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
651 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
652 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
653 enum {
654 LED_START = 1<<2, /* Start Timer */
655 LED_STOP = 1<<1, /* Stop Timer */
656 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
657 };
658
659 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
660 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
661 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
662 enum {
663 LED_T_ON = 1<<2, /* LED Counter Test mode On */
664 LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
665 LED_T_STEP = 1<<0, /* LED Counter Step */
666 };
667
668 /* LNK_LED_REG 8 bit Link LED Register */
669 enum {
670 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
671 LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
672 LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
673 LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
674 LED_ON = 1<<1, /* switch LED on */
675 LED_OFF = 1<<0, /* switch LED off */
676 };
677
678 /* Receive GMAC FIFO (YUKON and Yukon-2) */
679 enum {
680 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
681 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
682 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
683 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
684 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
685 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
686
687 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
688 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
689
690 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
691
692 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
693
694 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
695 };
696
697
698 /* TXA_TEST 8 bit Tx Arbiter Test Register */
699 enum {
700 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
701 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
702 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
703 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
704 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
705 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
706 };
707
708 /* TXA_STAT 8 bit Tx Arbiter Status Register */
709 enum {
710 TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
711 };
712
713
714 /* Q_BC 32 bit Current Byte Counter */
715
716 /* BMU Control Status Registers */
717 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
718 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
719 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
720 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
721 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
722 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
723 /* Q_CSR 32 bit BMU Control/Status Register */
724
725 enum {
726 CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
727
728 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
729 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
730 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
731 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
732 CSR_HPI_RUN = 1<<17, /* Release HPI SM */
733 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
734 CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
735 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
736 CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
737 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
738 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
739 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
740 CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
741 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
742 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
743 CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
744 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
745 CSR_START = 1<<4, /* Start Rx/Tx Queue */
746 CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
747 CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
748 CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
749 CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
750 };
751
752 #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
753 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
754 CSR_TRANS_RST)
755 #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
756 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
757 CSR_TRANS_RUN)
758
759 /* Q_F 32 bit Flag Register */
760 enum {
761 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
762 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
763 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
764 F_WM_REACHED = 1<<25, /* Watermark reached */
765
766 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
767 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
768 };
769
770 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
771 /* RB_START 32 bit RAM Buffer Start Address */
772 /* RB_END 32 bit RAM Buffer End Address */
773 /* RB_WP 32 bit RAM Buffer Write Pointer */
774 /* RB_RP 32 bit RAM Buffer Read Pointer */
775 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
776 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
777 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
778 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
779 /* RB_PC 32 bit RAM Buffer Packet Counter */
780 /* RB_LEV 32 bit RAM Buffer Level Register */
781
782 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
783 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
784 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
785
786 /* RB_CTRL 8 bit RAM Buffer Control Register */
787 enum {
788 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
789 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
790 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
791 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
792 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
793 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
794 };
795
796 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
797 enum {
798 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
799 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
800 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
801 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
802 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
803 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
804 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
805 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
806
807 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
808 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
809 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
810
811 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
812 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
813 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
814 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
815 };
816
817 /* Counter and Timer constants, for a host clock of 62.5 MHz */
818 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
819 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
820
821 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
822
823 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
824 /* 215 ms at 78.12 MHz */
825
826 #define SK_FACT_62 100 /* is given in percent */
827 #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
828 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
829
830
831 /* Transmit GMAC FIFO (YUKON only) */
832 enum {
833 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
834 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
835 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
836
837 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
838 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
839 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
840
841 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
842 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
843 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
844
845 /* Descriptor Poll Timer Registers */
846 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
847 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
848 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
849
850 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
851
852 /* Time Stamp Timer Registers (YUKON only) */
853 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
854 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
855 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
856 };
857
858 /* Status BMU Registers (Yukon-2 only)*/
859 enum {
860 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
861 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
862 /* 0x0e85 - 0x0e86: reserved */
863 STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */
864 STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */
865 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
866 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
867 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
868 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
869 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
870 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
871
872 /* FIFO Control/Status Registers (Yukon-2 only)*/
873 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
874 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
875 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
876 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
877 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
878 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
879 STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
880
881 /* Level and ISR Timer Registers (Yukon-2 only)*/
882 STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
883 STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */
884 STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */
885 STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */
886 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
887 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
888 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
889 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
890 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
891 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
892 STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */
893 STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */
894
895 ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
896 ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
897 ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
898 ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
899 };
900
901 enum {
902 LINKLED_OFF = 0x01,
903 LINKLED_ON = 0x02,
904 LINKLED_LINKSYNC_OFF = 0x04,
905 LINKLED_LINKSYNC_ON = 0x08,
906 LINKLED_BLINK_OFF = 0x10,
907 LINKLED_BLINK_ON = 0x20,
908 };
909
910 /* GMAC and GPHY Control Registers (YUKON only) */
911 enum {
912 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
913 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
914 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
915 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
916 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
917
918 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
919
920 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
921
922 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
923 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
924 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
925 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
926 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
927 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
928 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
929
930 /* WOL Pattern Length Registers (YUKON only) */
931
932 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
933 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
934
935 /* WOL Pattern Counter Registers (YUKON only) */
936
937 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
938 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
939 };
940
941 enum {
942 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
943 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
944 };
945
946 enum {
947 BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
948 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
949 BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
950 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
951 };
952
953 /*
954 * Receive Frame Status Encoding
955 */
956 enum {
957 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
958 XMR_FS_LEN_SHIFT = 18,
959 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
960 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
961 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
962 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
963 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
964
965 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
966 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
967 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
968 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
969 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
970 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
971 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
972 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
973 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
974 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
975 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
976 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
977
978 /*
979 * XMR_FS_ERR will be set if
980 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
981 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
982 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
983 * XMR_FS_ERR unless the corresponding bit in the Receive Command
984 * Register is set.
985 */
986 };
987
988 /*
989 ,* XMAC-PHY Registers, indirect addressed over the XMAC
990 */
991 enum {
992 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
993 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
994 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
995 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
996 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
997 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
998 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
999 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1000 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1001
1002 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
1003 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
1004 };
1005 /*
1006 * Broadcom-PHY Registers, indirect addressed over XMAC
1007 */
1008 enum {
1009 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1010 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1011 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1012 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1013 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1014 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1015 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1016 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1017 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1018 /* Broadcom-specific registers */
1019 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1020 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1021 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1022 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
1023 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
1024 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
1025 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
1026 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
1027
1028 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
1029 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
1030 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
1031 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
1032 };
1033
1034 /*
1035 * Marvel-PHY Registers, indirect addressed over GMAC
1036 */
1037 enum {
1038 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1039 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1040 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1041 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1042 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1043 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1044 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1045 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1046 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1047 /* Marvel-specific registers */
1048 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1049 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1050 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1051 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1052 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1053 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1054 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1055 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1056 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1057 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1058 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1059 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1060 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1061 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1062 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1063 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1064 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1065 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1066
1067 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1068 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1069 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1070 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1071 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1072 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1073 };
1074
1075 enum {
1076 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1077 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1078 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1079 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1080 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1081 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1082 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1083 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1084 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1085 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1086 };
1087
1088 enum {
1089 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1090 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1091 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1092 };
1093
1094 enum {
1095 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1096
1097 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1098 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1099 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1100 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1101 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1102 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1103 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1104 };
1105
1106 enum {
1107 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1108 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1109 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1110 };
1111
1112 /* different Broadcom PHY Ids */
1113 enum {
1114 PHY_BCOM_ID1_A1 = 0x6041,
1115 PHY_BCOM_ID1_B2 = 0x6043,
1116 PHY_BCOM_ID1_C0 = 0x6044,
1117 PHY_BCOM_ID1_C5 = 0x6047,
1118 };
1119
1120 /* different Marvell PHY Ids */
1121 enum {
1122 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1123 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1124 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1125 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1126 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1127 };
1128
1129 /* Advertisement register bits */
1130 enum {
1131 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1132 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1133 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1134
1135 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1136 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1137 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1138 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1139 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1140 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1141 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1142 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1143 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1144 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1145 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1146 PHY_AN_100HALF | PHY_AN_100FULL,
1147 };
1148
1149 /* Xmac Specific */
1150 enum {
1151 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1152 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1153 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1154
1155 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1156 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1157 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1158 };
1159
1160 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1161 enum {
1162 PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */
1163 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1164 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1165 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1166 };
1167
1168
1169 /* Broadcom-Specific */
1170 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1171 enum {
1172 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1173 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1174 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1175 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1176 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1177 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1178 };
1179
1180 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1181 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1182 enum {
1183 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1184 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1185 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1186 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1187 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1188 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1189 /* Bit 9..8: reserved */
1190 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1191 };
1192
1193 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1194 enum {
1195 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1196 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1197 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1198 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1199 };
1200
1201 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1202 enum {
1203 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1204 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1205 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1206 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1207 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1208 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1209 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1210 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1211 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1212 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1213 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1214 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1215 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1216 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1217 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1218 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1219 };
1220
1221 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1222 enum {
1223 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1224 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1225 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1226 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1227 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1228 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1229 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1230 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1231 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1232 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1233 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1234 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1235 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1236 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1237 };
1238
1239 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1240 /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1241 enum {
1242 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1243
1244 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1245 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1246 };
1247
1248
1249 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1250 enum {
1251 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1252
1253 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1254 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1255 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1256
1257 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1258 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1259 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1260 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1261 /* Bit 11: reserved */
1262 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1263 /* Bit 9.. 8: reserved */
1264 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1265 /* Bit 6: reserved */
1266 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1267 /* Bit 4: reserved */
1268 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1269 };
1270
1271 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1272 enum {
1273 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1274 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1275 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1276 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1277 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1278 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1279 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1280 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1281 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1282 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1283 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1284 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1285 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1286 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1287 };
1288 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1289
1290 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1291 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1292 enum {
1293 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1294 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1295 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1296 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1297 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1298 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1299 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1300 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1301 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1302 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1303 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1304 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1305 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1306 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1307 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1308 };
1309 #define PHY_B_DEF_MSK \
1310 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1311 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1312
1313 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1314 enum {
1315 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1316 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1317 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1318 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1319 };
1320 /*
1321 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1322 */
1323 enum {
1324 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1325 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1326 };
1327
1328 /** Marvell-Specific */
1329 enum {
1330 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1331 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1332 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1333
1334 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1335 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1336 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1337 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1338 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1339 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1340 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1341 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1342 };
1343
1344 /* special defines for FIBER (88E1011S only) */
1345 enum {
1346 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1347 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1348 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1349 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1350 };
1351
1352 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1353 enum {
1354 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1355 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1356 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1357 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1358 };
1359
1360 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1361 enum {
1362 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1363 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1364 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1365 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1366 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1367 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1368 };
1369
1370 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1371 enum {
1372 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1373 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1374 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1375 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1376 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1377 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1378 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1379 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1380 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1381 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1382 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1383 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1384 };
1385
1386 enum {
1387 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1388 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1389 };
1390
1391 #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1392
1393 enum {
1394 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1395 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1396 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1397 };
1398
1399 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1400 enum {
1401 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1402 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1403 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1404 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1405 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1406
1407 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1408 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1409
1410 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1411 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1412 };
1413
1414 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1415 enum {
1416 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1417 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1418 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1419 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1420 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1421 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1422 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1423 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1424 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1425 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1426 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1427 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1428 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1429 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1430 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1431 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1432 };
1433
1434 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1435
1436 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1437 enum {
1438 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1439 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1440 };
1441
1442 enum {
1443 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1444 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1445 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1446 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1447 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1448 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1449 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1450 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1451 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1452 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1453 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1454 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1455
1456 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1457 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1458 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1459
1460 PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1461 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1462
1463 PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1464 };
1465
1466 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1467 enum {
1468 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1469 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1470
1471 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1472 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1473 /* (88E1011 only) */
1474 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1475 /* (88E1011 only) */
1476 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1477 /* (88E1111 only) */
1478 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1479 /* !!! Errata in spec. (1 = disable) */
1480 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1481 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1482 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1483 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1484 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1485 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1486
1487 #define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1488 #define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1489 #define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1490
1491 #define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1492 /* 100=5x; 101=6x; 110=7x; 111=8x */
1493 enum {
1494 MAC_TX_CLK_0_MHZ = 2,
1495 MAC_TX_CLK_2_5_MHZ = 6,
1496 MAC_TX_CLK_25_MHZ = 7,
1497 };
1498
1499 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1500 enum {
1501 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1502 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1503 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1504 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1505 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1506 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1507 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1508 /* (88E1111 only) */
1509 };
1510
1511 enum {
1512 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1513 /* (88E1011 only) */
1514 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1515 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1516 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1517 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1518 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1519 };
1520
1521 #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1522
1523 enum {
1524 PULS_NO_STR = 0,/* no pulse stretching */
1525 PULS_21MS = 1,/* 21 ms to 42 ms */
1526 PULS_42MS = 2,/* 42 ms to 84 ms */
1527 PULS_84MS = 3,/* 84 ms to 170 ms */
1528 PULS_170MS = 4,/* 170 ms to 340 ms */
1529 PULS_340MS = 5,/* 340 ms to 670 ms */
1530 PULS_670MS = 6,/* 670 ms to 1.3 s */
1531 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1532 };
1533
1534 #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1535
1536 enum {
1537 BLINK_42MS = 0,/* 42 ms */
1538 BLINK_84MS = 1,/* 84 ms */
1539 BLINK_170MS = 2,/* 170 ms */
1540 BLINK_340MS = 3,/* 340 ms */
1541 BLINK_670MS = 4,/* 670 ms */
1542 };
1543
1544 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1545 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1546 /* Bit 13..12: reserved */
1547 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1548 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1549 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1550 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1551 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1552 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1553
1554 enum {
1555 MO_LED_NORM = 0,
1556 MO_LED_BLINK = 1,
1557 MO_LED_OFF = 2,
1558 MO_LED_ON = 3,
1559 };
1560
1561 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1562 enum {
1563 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1564 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1565 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1566 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1567 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1568 };
1569
1570 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1571 enum {
1572 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1573 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1574 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1575 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1576 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1577 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1578 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1579 /* (88E1111 only) */
1580 /* Bit 9.. 4: reserved (88E1011 only) */
1581 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1582 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1583 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1584 };
1585
1586 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1587 enum {
1588 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1589 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1590 /* (88E1111 only) */
1591 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1592 PHY_M_CABD_AMPL_MSK = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */
1593 /* (88E1111 only) */
1594 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1595 };
1596
1597 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1598 enum {
1599 CABD_STAT_NORMAL= 0,
1600 CABD_STAT_SHORT = 1,
1601 CABD_STAT_OPEN = 2,
1602 CABD_STAT_FAIL = 3,
1603 };
1604
1605 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1606 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1607 /* Bit 15..12: reserved (used internally) */
1608 enum {
1609 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1610 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1611 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1612 };
1613
1614 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1615 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1616 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1617
1618 enum {
1619 LED_PAR_CTRL_COLX = 0x00,
1620 LED_PAR_CTRL_ERROR = 0x01,
1621 LED_PAR_CTRL_DUPLEX = 0x02,
1622 LED_PAR_CTRL_DP_COL = 0x03,
1623 LED_PAR_CTRL_SPEED = 0x04,
1624 LED_PAR_CTRL_LINK = 0x05,
1625 LED_PAR_CTRL_TX = 0x06,
1626 LED_PAR_CTRL_RX = 0x07,
1627 LED_PAR_CTRL_ACT = 0x08,
1628 LED_PAR_CTRL_LNK_RX = 0x09,
1629 LED_PAR_CTRL_LNK_AC = 0x0a,
1630 LED_PAR_CTRL_ACT_BL = 0x0b,
1631 LED_PAR_CTRL_TX_BL = 0x0c,
1632 LED_PAR_CTRL_RX_BL = 0x0d,
1633 LED_PAR_CTRL_COL_BL = 0x0e,
1634 LED_PAR_CTRL_INACT = 0x0f
1635 };
1636
1637 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1638 enum {
1639 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1640 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1641 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1642 };
1643
1644 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1645 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1646 enum {
1647 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1648 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1649 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1650 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1651 };
1652 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1653
1654 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1655 enum {
1656 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1657 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1658 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1659 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1660 };
1661
1662 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1663 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1664 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1665 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1666
1667 /* GMAC registers */
1668 /* Port Registers */
1669 enum {
1670 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1671 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1672 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1673 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1674 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1675 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1676 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1677 /* Source Address Registers */
1678 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1679 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1680 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1681 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1682 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1683 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1684
1685 /* Multicast Address Hash Registers */
1686 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1687 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1688 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1689 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1690
1691 /* Interrupt Source Registers */
1692 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1693 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1694 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1695
1696 /* Interrupt Mask Registers */
1697 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1698 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1699 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1700
1701 /* Serial Management Interface (SMI) Registers */
1702 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1703 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1704 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1705 };
1706
1707 /* MIB Counters */
1708 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1709 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1710
1711 /*
1712 * MIB Counters base address definitions (low word) -
1713 * use offset 4 for access to high word (32 bit r/o)
1714 */
1715 enum {
1716 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1717 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1718 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1719 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1720 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1721 /* GM_MIB_CNT_BASE + 40: reserved */
1722 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1723 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1724 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1725 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1726 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1727 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1728 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1729 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1730 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1731 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1732 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1733 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1734 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1735 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1736 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1737 /* GM_MIB_CNT_BASE + 168: reserved */
1738 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1739 /* GM_MIB_CNT_BASE + 184: reserved */
1740 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1741 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1742 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1743 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1744 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1745 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1746 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1747 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1748 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1749 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1750 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1751 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1752 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1753
1754 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1755 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1756 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1757 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1758 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1759 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1760 };
1761
1762 /* GMAC Bit Definitions */
1763 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1764 enum {
1765 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1766 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1767 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1768 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1769 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1770 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1771 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1772 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1773
1774 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1775 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1776 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1777 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1778 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1779 };
1780
1781 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1782 enum {
1783 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1784 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1785 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1786 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1787 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1788 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1789 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1790 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1791 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1792 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1793 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1794 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1795 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1796 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1797 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1798 };
1799
1800 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1801 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1802
1803 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1804 enum {
1805 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1806 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1807 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1808 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
1809 };
1810
1811 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1812 #define TX_COL_DEF 0x04
1813
1814 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1815 enum {
1816 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1817 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1818 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1819 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1820 };
1821
1822 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1823 enum {
1824 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1825 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1826 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1827
1828 TX_JAM_LEN_DEF = 0x03,
1829 TX_JAM_IPG_DEF = 0x0b,
1830 TX_IPG_JAM_DEF = 0x1c,
1831 };
1832
1833 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1834 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1835 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1836
1837
1838 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1839 enum {
1840 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1841 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1842 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1843 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1844 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1845 };
1846
1847 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1848 #define DATA_BLIND_DEF 0x04
1849
1850 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1851 #define IPG_DATA_DEF 0x1e
1852
1853 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1854 enum {
1855 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1856 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1857 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1858 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1859 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1860 };
1861
1862 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1863 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1864
1865 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1866 enum {
1867 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1868 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1869 };
1870
1871 /* Receive Frame Status Encoding */
1872 enum {
1873 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1874 GMR_FS_LEN_SHIFT = 16,
1875 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
1876 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
1877 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1878 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
1879 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
1880 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
1881 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1882 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1883 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1884 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
1885 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
1886
1887 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
1888 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
1889
1890 /*
1891 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1892 */
1893 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1894 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1895 GMR_FS_JABBER,
1896 /* Rx GMAC FIFO Flush Mask (default) */
1897 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1898 GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
1899 GMR_FS_JABBER,
1900 };
1901
1902 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1903 enum {
1904 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1905 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1906 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1907
1908 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1909 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1910 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1911 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1912 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1913 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1914 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
1915 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1916 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1917 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1918 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1919
1920 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1921 };
1922
1923
1924 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1925 enum {
1926 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1927 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1928 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1929
1930 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1931 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1932 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1933 };
1934
1935 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1936 enum {
1937 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1938 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1939 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1940 };
1941
1942 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1943 enum {
1944 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1945 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1946 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1947 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1948 GMC_PAUSE_ON = 1<<3, /* Pause On */
1949 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1950 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1951 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1952 };
1953
1954 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1955 enum {
1956 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1957 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1958 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1959 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1960 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1961 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1962 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1963 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1964 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1965 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1966 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1967 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1968 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1969 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1970 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1971 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1972 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1973 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1974 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1975 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1976 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1977 /* Bits 7..2: reserved */
1978 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1979 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1980 };
1981
1982 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1983 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1984 #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1985
1986 /* forced speed and duplex mode (don't mix with other ANEG bits) */
1987 #define GPC_FRC10MBIT_HALF 0
1988 #define GPC_FRC10MBIT_FULL GPC_ANEG_0
1989 #define GPC_FRC100MBIT_HALF GPC_ANEG_1
1990 #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
1991
1992 /* auto-negotiation with limited advertised speeds */
1993 /* mix only with master/slave settings (for copper) */
1994 #define GPC_ADV_1000_HALF GPC_ANEG_2
1995 #define GPC_ADV_1000_FULL GPC_ANEG_3
1996 #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
1997
1998 /* master/slave settings */
1999 /* only for copper with 1000 Mbps */
2000 #define GPC_FORCE_MASTER 0
2001 #define GPC_FORCE_SLAVE GPC_ANEG_0
2002 #define GPC_PREF_MASTER GPC_ANEG_1
2003 #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
2004
2005 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2006 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2007 enum {
2008 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
2009 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
2010 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
2011 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
2012 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
2013 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
2014
2015 #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
2016
2017 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2018 /* Bits 15.. 2: reserved */
2019 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
2020 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
2021
2022
2023 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2024 WOL_CTL_LINK_CHG_OCC = 1<<15,
2025 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
2026 WOL_CTL_PATTERN_OCC = 1<<13,
2027 WOL_CTL_CLEAR_RESULT = 1<<12,
2028 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
2029 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
2030 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
2031 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
2032 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
2033 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
2034 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
2035 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
2036 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
2037 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
2038 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
2039 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
2040 };
2041
2042 #define WOL_CTL_DEFAULT \
2043 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
2044 WOL_CTL_DIS_PME_ON_PATTERN | \
2045 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
2046 WOL_CTL_DIS_LINK_CHG_UNIT | \
2047 WOL_CTL_DIS_PATTERN_UNIT | \
2048 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2049
2050 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2051 #define WOL_CTL_PATT_ENA(x) (1 << (x))
2052
2053
2054 /* XMAC II registers */
2055 enum {
2056 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2057 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2058 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2059 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2060 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2061 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2062 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2063 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2064 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2065 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2066 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2067 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2068 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2069 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2070 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2071 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2072 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2073 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2074 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2075 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2076 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2077 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2078 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2079 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2080 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2081
2082 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2083 #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2084 };
2085
2086 enum {
2087 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2088 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2089 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2090 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2091 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2092 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2093 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2094 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2095 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2096 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2097 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2098 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2099 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2100 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2101 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2102 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2103 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2104 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2105 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2106 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2107 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2108 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2109 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2110 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2111 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2112 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2113 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2114 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2115 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2116 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2117 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2118 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2119 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2120 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2121 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2122 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2123 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2124 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2125 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2126 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2127 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2128 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2129 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2130 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2131 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2132 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2133 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2134 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2135 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2136 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2137 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2138 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2139 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2140 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2141 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2142 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2143 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2144 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2145 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2146 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2147 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2148 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2149 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2150 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2151 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2152 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2153 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2154 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2155 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2156 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2157 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2158 };
2159
2160 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2161 enum {
2162 XM_MMU_PHY_RDY = 1<<12,/* Bit 12: PHY Read Ready */
2163 XM_MMU_PHY_BUSY = 1<<11,/* Bit 11: PHY Busy */
2164 XM_MMU_IGN_PF = 1<<10,/* Bit 10: Ignore Pause Frame */
2165 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2166 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2167 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2168 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2169 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2170 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2171 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2172 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2173 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2174 };
2175
2176
2177 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2178 enum {
2179 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2180 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2181 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2182 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2183 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2184 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2185 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2186 };
2187
2188 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2189 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2190
2191
2192 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2193 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2194
2195
2196 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2197 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2198
2199
2200 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2201 enum {
2202 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2203 /* inrange error packets */
2204 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2205 /* jumbo packets */
2206 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2207 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2208 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2209 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2210 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2211 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2212 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2213 };
2214
2215
2216 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2217 enum {
2218 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2219 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2220 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2221 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2222 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2223 };
2224
2225
2226 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2227 /* XM_ISRC 16 bit r/o Interrupt Status Register */
2228 enum {
2229 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2230 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2231 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2232 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2233 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2234 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2235 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2236 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2237 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2238 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2239 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2240 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2241 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2242 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2243 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2244 };
2245
2246 #define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | \
2247 XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | \
2248 XM_IS_RXF_OV | XM_IS_TXF_UR))
2249
2250
2251 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2252 enum {
2253 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2254 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2255 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2256 };
2257
2258
2259 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2260 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2261 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2262
2263 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2264 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2265 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2266 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2267
2268
2269 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2270 enum {
2271 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2272 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2273 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2274 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2275 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2276 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2277 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2278 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2279 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2280 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2281 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occured */
2282 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2283 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2284 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2285 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2286 };
2287
2288 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2289 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2290 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2291
2292
2293 /* XM_DEV_ID 32 bit r/o Device ID Register */
2294 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2295 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2296
2297
2298 /* XM_MODE 32 bit r/w Mode Register */
2299 enum {
2300 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2301 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2302 /* extern generated */
2303 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2304 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2305 /* intern generated */
2306 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2307 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2308 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2309 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2310 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2311 /* intern generated */
2312 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2313 /* intern generated */
2314 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2315 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2316 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2317 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2318 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2319 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2320 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2321 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2322 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2323 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2324 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2325 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2326 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2327 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2328 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2329 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2330 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2331 };
2332
2333 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2334 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2335 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2336
2337 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2338 enum {
2339 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2340 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2341 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2342 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2343 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2344 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2345 };
2346
2347
2348 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2349 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2350 enum {
2351 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2352 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2353 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2354 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2355 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2356 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2357 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2358 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2359 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2360 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2361 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2362 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2363 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2364 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2365 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2366 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2367 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2368 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2369 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2370 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2371 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2372 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2373 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2374 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2375 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2376 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2377 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2378 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2379 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2380 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2381 };
2382
2383 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2384
2385 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2386 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2387 enum {
2388 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2389 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2390 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2391 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2392 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2393 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2394 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2395 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2396 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2397 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2398 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2399 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2400 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2401 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2402 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2403 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2404 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2405 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2406 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2407 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2408 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2409 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2410 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2411 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2412 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2413 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2414 };
2415
2416 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2417
2418 struct skge_rx_desc {
2419 u32 control;
2420 u32 next_offset;
2421 u32 dma_lo;
2422 u32 dma_hi;
2423 u32 status;
2424 u32 timestamp;
2425 u16 csum2;
2426 u16 csum1;
2427 u16 csum2_start;
2428 u16 csum1_start;
2429 };
2430
2431 struct skge_tx_desc {
2432 u32 control;
2433 u32 next_offset;
2434 u32 dma_lo;
2435 u32 dma_hi;
2436 u32 status;
2437 u32 csum_offs;
2438 u16 csum_write;
2439 u16 csum_start;
2440 u32 rsvd;
2441 };
2442
2443 struct skge_element {
2444 struct skge_element *next;
2445 void *desc;
2446 struct sk_buff *skb;
2447 DECLARE_PCI_UNMAP_ADDR(mapaddr);
2448 DECLARE_PCI_UNMAP_LEN(maplen);
2449 };
2450
2451 struct skge_ring {
2452 struct skge_element *to_clean;
2453 struct skge_element *to_use;
2454 struct skge_element *start;
2455 unsigned long count;
2456 };
2457
2458
2459 struct skge_hw {
2460 void __iomem *regs;
2461 struct pci_dev *pdev;
2462 u32 intr_mask;
2463 struct net_device *dev[2];
2464
2465 u8 chip_id;
2466 u8 chip_rev;
2467 u8 copper;
2468 u8 ports;
2469
2470 u32 ram_size;
2471 u32 ram_offset;
2472 u16 phy_addr;
2473
2474 struct tasklet_struct ext_tasklet;
2475 spinlock_t phy_lock;
2476 };
2477
2478 enum {
2479 FLOW_MODE_NONE = 0, /* No Flow-Control */
2480 FLOW_MODE_LOC_SEND = 1, /* Local station sends PAUSE */
2481 FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */
2482 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2483 };
2484
2485 struct skge_port {
2486 u32 msg_enable;
2487 struct skge_hw *hw;
2488 struct net_device *netdev;
2489 int port;
2490
2491 spinlock_t tx_lock;
2492 u32 tx_avail;
2493 struct skge_ring tx_ring;
2494 struct skge_ring rx_ring;
2495
2496 struct net_device_stats net_stats;
2497
2498 u8 rx_csum;
2499 u8 blink_on;
2500 u8 flow_control;
2501 u8 wol;
2502 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2503 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2504 u16 speed; /* SPEED_1000, SPEED_100, ... */
2505 u32 advertising;
2506
2507 void *mem; /* PCI memory for rings */
2508 dma_addr_t dma;
2509 unsigned long mem_size;
2510 unsigned int rx_buf_size;
2511 };
2512
2513
2514 /* Register accessor for memory mapped device */
2515 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2516 {
2517 return readl(hw->regs + reg);
2518 }
2519
2520 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2521 {
2522 return readw(hw->regs + reg);
2523 }
2524
2525 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2526 {
2527 return readb(hw->regs + reg);
2528 }
2529
2530 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2531 {
2532 writel(val, hw->regs + reg);
2533 }
2534
2535 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2536 {
2537 writew(val, hw->regs + reg);
2538 }
2539
2540 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2541 {
2542 writeb(val, hw->regs + reg);
2543 }
2544
2545 /* MAC Related Registers inside the device. */
2546 #define SK_REG(port,reg) (((port)<<7)+(reg))
2547 #define SK_XMAC_REG(port, reg) \
2548 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2549
2550 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2551 {
2552 u32 v;
2553 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2554 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2555 return v;
2556 }
2557
2558 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2559 {
2560 return skge_read16(hw, SK_XMAC_REG(port,reg));
2561 }
2562
2563 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2564 {
2565 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2566 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2567 }
2568
2569 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2570 {
2571 skge_write16(hw, SK_XMAC_REG(port,r), v);
2572 }
2573
2574 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2575 const u8 *hash)
2576 {
2577 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2578 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2579 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2580 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2581 }
2582
2583 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2584 const u8 *addr)
2585 {
2586 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2587 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2588 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2589 }
2590
2591 #define SK_GMAC_REG(port,reg) \
2592 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2593
2594 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2595 {
2596 return skge_read16(hw, SK_GMAC_REG(port,reg));
2597 }
2598
2599 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2600 {
2601 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2602 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2603 }
2604
2605 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2606 {
2607 skge_write16(hw, SK_GMAC_REG(port,r), v);
2608 }
2609
2610 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2611 const u8 *addr)
2612 {
2613 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2614 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2615 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2616 }
2617
2618 #endif
Linux kernel - Deliverables
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