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8250.c: port.lock is irq-safe
[deliverable/linux.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.22"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
141 { 0 }
142 };
143
144 MODULE_DEVICE_TABLE(pci, sky2_id_table);
145
146 /* Avoid conditionals by using array */
147 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
148 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
149 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
150
151 static void sky2_set_multicast(struct net_device *dev);
152
153 /* Access to PHY via serial interconnect */
154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
155 {
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
164 if (ctrl == 0xffff)
165 goto io_error;
166
167 if (!(ctrl & GM_SMI_CT_BUSY))
168 return 0;
169
170 udelay(10);
171 }
172
173 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
174 return -ETIMEDOUT;
175
176 io_error:
177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
178 return -EIO;
179 }
180
181 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
182 {
183 int i;
184
185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187
188 for (i = 0; i < PHY_RETRIES; i++) {
189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
190 if (ctrl == 0xffff)
191 goto io_error;
192
193 if (ctrl & GM_SMI_CT_RD_VAL) {
194 *val = gma_read16(hw, port, GM_SMI_DATA);
195 return 0;
196 }
197
198 udelay(10);
199 }
200
201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
202 return -ETIMEDOUT;
203 io_error:
204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
205 return -EIO;
206 }
207
208 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
209 {
210 u16 v;
211 __gm_phy_read(hw, port, reg, &v);
212 return v;
213 }
214
215
216 static void sky2_power_on(struct sky2_hw *hw)
217 {
218 /* switch power to VCC (WA for VAUX problem) */
219 sky2_write8(hw, B0_POWER_CTRL,
220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221
222 /* disable Core Clock Division, */
223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224
225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
226 /* enable bits are inverted */
227 sky2_write8(hw, B2_Y2_CLK_GATE,
228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 else
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233
234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
235 u32 reg;
236
237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238
239 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
240 /* set all bits to 0 except bits 15..12 and 8 */
241 reg &= P_ASPM_CONTROL_MSK;
242 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
243
244 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
245 /* set all bits to 0 except bits 28 & 27 */
246 reg &= P_CTL_TIM_VMAIN_AV_MSK;
247 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
248
249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
250
251 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
252 reg = sky2_read32(hw, B2_GP_IO);
253 reg |= GLB_GPIO_STAT_RACE_DIS;
254 sky2_write32(hw, B2_GP_IO, reg);
255
256 sky2_read32(hw, B2_GP_IO);
257 }
258 }
259
260 static void sky2_power_aux(struct sky2_hw *hw)
261 {
262 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
263 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
264 else
265 /* enable bits are inverted */
266 sky2_write8(hw, B2_Y2_CLK_GATE,
267 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
268 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
269 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
270
271 /* switch power to VAUX */
272 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
273 sky2_write8(hw, B0_POWER_CTRL,
274 (PC_VAUX_ENA | PC_VCC_ENA |
275 PC_VAUX_ON | PC_VCC_OFF));
276 }
277
278 static void sky2_power_state(struct sky2_hw *hw, pci_power_t state)
279 {
280 u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
281 int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
282 u32 reg;
283
284 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
285
286 switch (state) {
287 case PCI_D0:
288 break;
289
290 case PCI_D1:
291 power_control |= 1;
292 break;
293
294 case PCI_D2:
295 power_control |= 2;
296 break;
297
298 case PCI_D3hot:
299 case PCI_D3cold:
300 power_control |= 3;
301 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
302 /* additional power saving measurements */
303 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
304
305 /* set gating core clock for LTSSM in L1 state */
306 reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
307 /* auto clock gated scheme controlled by CLKREQ */
308 P_ASPM_A1_MODE_SELECT |
309 /* enable Gate Root Core Clock */
310 P_CLK_GATE_ROOT_COR_ENA;
311
312 if (pex && (hw->flags & SKY2_HW_CLK_POWER)) {
313 /* enable Clock Power Management (CLKREQ) */
314 u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL);
315
316 ctrl |= PCI_EXP_DEVCTL_AUX_PME;
317 sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl);
318 } else
319 /* force CLKREQ Enable in Our4 (A1b only) */
320 reg |= P_ASPM_FORCE_CLKREQ_ENA;
321
322 /* set Mask Register for Release/Gate Clock */
323 sky2_pci_write32(hw, PCI_DEV_REG5,
324 P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
325 P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
326 P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
327 } else
328 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT);
329
330 /* put CPU into reset state */
331 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET);
332 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0)
333 /* put CPU into halt state */
334 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED);
335
336 if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) {
337 reg = sky2_pci_read32(hw, PCI_DEV_REG1);
338 /* force to PCIe L1 */
339 reg |= PCI_FORCE_PEX_L1;
340 sky2_pci_write32(hw, PCI_DEV_REG1, reg);
341 }
342 break;
343
344 default:
345 dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ",
346 state);
347 return;
348 }
349
350 power_control |= PCI_PM_CTRL_PME_ENABLE;
351 /* Finally, set the new power state. */
352 sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
353
354 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
355 sky2_pci_read32(hw, B0_CTST);
356 }
357
358 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
359 {
360 u16 reg;
361
362 /* disable all GMAC IRQ's */
363 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
364
365 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
366 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
367 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
368 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
369
370 reg = gma_read16(hw, port, GM_RX_CTRL);
371 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
372 gma_write16(hw, port, GM_RX_CTRL, reg);
373 }
374
375 /* flow control to advertise bits */
376 static const u16 copper_fc_adv[] = {
377 [FC_NONE] = 0,
378 [FC_TX] = PHY_M_AN_ASP,
379 [FC_RX] = PHY_M_AN_PC,
380 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
381 };
382
383 /* flow control to advertise bits when using 1000BaseX */
384 static const u16 fiber_fc_adv[] = {
385 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
386 [FC_TX] = PHY_M_P_ASYM_MD_X,
387 [FC_RX] = PHY_M_P_SYM_MD_X,
388 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
389 };
390
391 /* flow control to GMA disable bits */
392 static const u16 gm_fc_disable[] = {
393 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
394 [FC_TX] = GM_GPCR_FC_RX_DIS,
395 [FC_RX] = GM_GPCR_FC_TX_DIS,
396 [FC_BOTH] = 0,
397 };
398
399
400 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
401 {
402 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
403 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
404
405 if (sky2->autoneg == AUTONEG_ENABLE &&
406 !(hw->flags & SKY2_HW_NEWER_PHY)) {
407 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
408
409 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
410 PHY_M_EC_MAC_S_MSK);
411 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
412
413 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
414 if (hw->chip_id == CHIP_ID_YUKON_EC)
415 /* set downshift counter to 3x and enable downshift */
416 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
417 else
418 /* set master & slave downshift counter to 1x */
419 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
420
421 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
422 }
423
424 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
425 if (sky2_is_copper(hw)) {
426 if (!(hw->flags & SKY2_HW_GIGABIT)) {
427 /* enable automatic crossover */
428 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
429
430 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
431 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
432 u16 spec;
433
434 /* Enable Class A driver for FE+ A0 */
435 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
436 spec |= PHY_M_FESC_SEL_CL_A;
437 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
438 }
439 } else {
440 /* disable energy detect */
441 ctrl &= ~PHY_M_PC_EN_DET_MSK;
442
443 /* enable automatic crossover */
444 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
445
446 /* downshift on PHY 88E1112 and 88E1149 is changed */
447 if (sky2->autoneg == AUTONEG_ENABLE
448 && (hw->flags & SKY2_HW_NEWER_PHY)) {
449 /* set downshift counter to 3x and enable downshift */
450 ctrl &= ~PHY_M_PC_DSC_MSK;
451 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
452 }
453 }
454 } else {
455 /* workaround for deviation #4.88 (CRC errors) */
456 /* disable Automatic Crossover */
457
458 ctrl &= ~PHY_M_PC_MDIX_MSK;
459 }
460
461 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
462
463 /* special setup for PHY 88E1112 Fiber */
464 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
465 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
466
467 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
468 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
469 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
470 ctrl &= ~PHY_M_MAC_MD_MSK;
471 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
472 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
473
474 if (hw->pmd_type == 'P') {
475 /* select page 1 to access Fiber registers */
476 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
477
478 /* for SFP-module set SIGDET polarity to low */
479 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
480 ctrl |= PHY_M_FIB_SIGD_POL;
481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
482 }
483
484 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
485 }
486
487 ctrl = PHY_CT_RESET;
488 ct1000 = 0;
489 adv = PHY_AN_CSMA;
490 reg = 0;
491
492 if (sky2->autoneg == AUTONEG_ENABLE) {
493 if (sky2_is_copper(hw)) {
494 if (sky2->advertising & ADVERTISED_1000baseT_Full)
495 ct1000 |= PHY_M_1000C_AFD;
496 if (sky2->advertising & ADVERTISED_1000baseT_Half)
497 ct1000 |= PHY_M_1000C_AHD;
498 if (sky2->advertising & ADVERTISED_100baseT_Full)
499 adv |= PHY_M_AN_100_FD;
500 if (sky2->advertising & ADVERTISED_100baseT_Half)
501 adv |= PHY_M_AN_100_HD;
502 if (sky2->advertising & ADVERTISED_10baseT_Full)
503 adv |= PHY_M_AN_10_FD;
504 if (sky2->advertising & ADVERTISED_10baseT_Half)
505 adv |= PHY_M_AN_10_HD;
506
507 adv |= copper_fc_adv[sky2->flow_mode];
508 } else { /* special defines for FIBER (88E1040S only) */
509 if (sky2->advertising & ADVERTISED_1000baseT_Full)
510 adv |= PHY_M_AN_1000X_AFD;
511 if (sky2->advertising & ADVERTISED_1000baseT_Half)
512 adv |= PHY_M_AN_1000X_AHD;
513
514 adv |= fiber_fc_adv[sky2->flow_mode];
515 }
516
517 /* Restart Auto-negotiation */
518 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
519 } else {
520 /* forced speed/duplex settings */
521 ct1000 = PHY_M_1000C_MSE;
522
523 /* Disable auto update for duplex flow control and speed */
524 reg |= GM_GPCR_AU_ALL_DIS;
525
526 switch (sky2->speed) {
527 case SPEED_1000:
528 ctrl |= PHY_CT_SP1000;
529 reg |= GM_GPCR_SPEED_1000;
530 break;
531 case SPEED_100:
532 ctrl |= PHY_CT_SP100;
533 reg |= GM_GPCR_SPEED_100;
534 break;
535 }
536
537 if (sky2->duplex == DUPLEX_FULL) {
538 reg |= GM_GPCR_DUP_FULL;
539 ctrl |= PHY_CT_DUP_MD;
540 } else if (sky2->speed < SPEED_1000)
541 sky2->flow_mode = FC_NONE;
542
543
544 reg |= gm_fc_disable[sky2->flow_mode];
545
546 /* Forward pause packets to GMAC? */
547 if (sky2->flow_mode & FC_RX)
548 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
549 else
550 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
551 }
552
553 gma_write16(hw, port, GM_GP_CTRL, reg);
554
555 if (hw->flags & SKY2_HW_GIGABIT)
556 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
557
558 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
559 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
560
561 /* Setup Phy LED's */
562 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
563 ledover = 0;
564
565 switch (hw->chip_id) {
566 case CHIP_ID_YUKON_FE:
567 /* on 88E3082 these bits are at 11..9 (shifted left) */
568 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
569
570 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
571
572 /* delete ACT LED control bits */
573 ctrl &= ~PHY_M_FELP_LED1_MSK;
574 /* change ACT LED control to blink mode */
575 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
576 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
577 break;
578
579 case CHIP_ID_YUKON_FE_P:
580 /* Enable Link Partner Next Page */
581 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
582 ctrl |= PHY_M_PC_ENA_LIP_NP;
583
584 /* disable Energy Detect and enable scrambler */
585 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
586 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
587
588 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
589 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
590 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
591 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
592
593 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
594 break;
595
596 case CHIP_ID_YUKON_XL:
597 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
598
599 /* select page 3 to access LED control register */
600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
601
602 /* set LED Function Control register */
603 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
604 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
605 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
606 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
607 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
608
609 /* set Polarity Control register */
610 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
611 (PHY_M_POLC_LS1_P_MIX(4) |
612 PHY_M_POLC_IS0_P_MIX(4) |
613 PHY_M_POLC_LOS_CTRL(2) |
614 PHY_M_POLC_INIT_CTRL(2) |
615 PHY_M_POLC_STA1_CTRL(2) |
616 PHY_M_POLC_STA0_CTRL(2)));
617
618 /* restore page register */
619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
620 break;
621
622 case CHIP_ID_YUKON_EC_U:
623 case CHIP_ID_YUKON_EX:
624 case CHIP_ID_YUKON_SUPR:
625 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
626
627 /* select page 3 to access LED control register */
628 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
629
630 /* set LED Function Control register */
631 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
632 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
633 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
634 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
635 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
636
637 /* set Blink Rate in LED Timer Control Register */
638 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
639 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
640 /* restore page register */
641 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
642 break;
643
644 default:
645 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
646 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
647
648 /* turn off the Rx LED (LED_RX) */
649 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
650 }
651
652 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
653 /* apply fixes in PHY AFE */
654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
655
656 /* increase differential signal amplitude in 10BASE-T */
657 gm_phy_write(hw, port, 0x18, 0xaa99);
658 gm_phy_write(hw, port, 0x17, 0x2011);
659
660 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
661 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
662 gm_phy_write(hw, port, 0x18, 0xa204);
663 gm_phy_write(hw, port, 0x17, 0x2002);
664 }
665
666 /* set page register to 0 */
667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
668 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
669 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
670 /* apply workaround for integrated resistors calibration */
671 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
672 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
673 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
674 hw->chip_id < CHIP_ID_YUKON_SUPR) {
675 /* no effect on Yukon-XL */
676 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
677
678 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
679 /* turn on 100 Mbps LED (LED_LINK100) */
680 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
681 }
682
683 if (ledover)
684 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
685
686 }
687
688 /* Enable phy interrupt on auto-negotiation complete (or link up) */
689 if (sky2->autoneg == AUTONEG_ENABLE)
690 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
691 else
692 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
693 }
694
695 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
696 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
697
698 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
699 {
700 u32 reg1;
701
702 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
703 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
704 reg1 &= ~phy_power[port];
705
706 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
707 reg1 |= coma_mode[port];
708
709 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
711 sky2_pci_read32(hw, PCI_DEV_REG1);
712 }
713
714 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
715 {
716 u32 reg1;
717 u16 ctrl;
718
719 /* release GPHY Control reset */
720 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
721
722 /* release GMAC reset */
723 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
724
725 if (hw->flags & SKY2_HW_NEWER_PHY) {
726 /* select page 2 to access MAC control register */
727 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
728
729 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
730 /* allow GMII Power Down */
731 ctrl &= ~PHY_M_MAC_GMIF_PUP;
732 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
733
734 /* set page register back to 0 */
735 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
736 }
737
738 /* setup General Purpose Control Register */
739 gma_write16(hw, port, GM_GP_CTRL,
740 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
741
742 if (hw->chip_id != CHIP_ID_YUKON_EC) {
743 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
744 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
745
746 /* enable Power Down */
747 ctrl |= PHY_M_PC_POW_D_ENA;
748 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
749 }
750
751 /* set IEEE compatible Power Down Mode (dev. #4.99) */
752 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
753 }
754
755 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
756 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
757 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
758 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
759 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
760 }
761
762 /* Force a renegotiation */
763 static void sky2_phy_reinit(struct sky2_port *sky2)
764 {
765 spin_lock_bh(&sky2->phy_lock);
766 sky2_phy_init(sky2->hw, sky2->port);
767 spin_unlock_bh(&sky2->phy_lock);
768 }
769
770 /* Put device in state to listen for Wake On Lan */
771 static void sky2_wol_init(struct sky2_port *sky2)
772 {
773 struct sky2_hw *hw = sky2->hw;
774 unsigned port = sky2->port;
775 enum flow_control save_mode;
776 u16 ctrl;
777 u32 reg1;
778
779 /* Bring hardware out of reset */
780 sky2_write16(hw, B0_CTST, CS_RST_CLR);
781 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
782
783 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
784 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
785
786 /* Force to 10/100
787 * sky2_reset will re-enable on resume
788 */
789 save_mode = sky2->flow_mode;
790 ctrl = sky2->advertising;
791
792 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
793 sky2->flow_mode = FC_NONE;
794
795 spin_lock_bh(&sky2->phy_lock);
796 sky2_phy_power_up(hw, port);
797 sky2_phy_init(hw, port);
798 spin_unlock_bh(&sky2->phy_lock);
799
800 sky2->flow_mode = save_mode;
801 sky2->advertising = ctrl;
802
803 /* Set GMAC to no flow control and auto update for speed/duplex */
804 gma_write16(hw, port, GM_GP_CTRL,
805 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
806 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
807
808 /* Set WOL address */
809 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
810 sky2->netdev->dev_addr, ETH_ALEN);
811
812 /* Turn on appropriate WOL control bits */
813 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
814 ctrl = 0;
815 if (sky2->wol & WAKE_PHY)
816 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
817 else
818 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
819
820 if (sky2->wol & WAKE_MAGIC)
821 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
822 else
823 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
824
825 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
826 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
827
828 /* Turn on legacy PCI-Express PME mode */
829 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
830 reg1 |= PCI_Y2_PME_LEGACY;
831 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
832
833 /* block receiver */
834 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
835
836 }
837
838 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
839 {
840 struct net_device *dev = hw->dev[port];
841
842 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
843 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
844 hw->chip_id == CHIP_ID_YUKON_FE_P ||
845 hw->chip_id == CHIP_ID_YUKON_SUPR) {
846 /* Yukon-Extreme B0 and further Extreme devices */
847 /* enable Store & Forward mode for TX */
848
849 if (dev->mtu <= ETH_DATA_LEN)
850 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
851 TX_JUMBO_DIS | TX_STFW_ENA);
852
853 else
854 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
855 TX_JUMBO_ENA| TX_STFW_ENA);
856 } else {
857 if (dev->mtu <= ETH_DATA_LEN)
858 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
859 else {
860 /* set Tx GMAC FIFO Almost Empty Threshold */
861 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
862 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
863
864 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
865
866 /* Can't do offload because of lack of store/forward */
867 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
868 }
869 }
870 }
871
872 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
873 {
874 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
875 u16 reg;
876 u32 rx_reg;
877 int i;
878 const u8 *addr = hw->dev[port]->dev_addr;
879
880 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
881 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
882
883 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
884
885 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
886 /* WA DEV_472 -- looks like crossed wires on port 2 */
887 /* clear GMAC 1 Control reset */
888 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
889 do {
890 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
891 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
892 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
893 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
894 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
895 }
896
897 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
898
899 /* Enable Transmit FIFO Underrun */
900 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
901
902 spin_lock_bh(&sky2->phy_lock);
903 sky2_phy_power_up(hw, port);
904 sky2_phy_init(hw, port);
905 spin_unlock_bh(&sky2->phy_lock);
906
907 /* MIB clear */
908 reg = gma_read16(hw, port, GM_PHY_ADDR);
909 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
910
911 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
912 gma_read16(hw, port, i);
913 gma_write16(hw, port, GM_PHY_ADDR, reg);
914
915 /* transmit control */
916 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
917
918 /* receive control reg: unicast + multicast + no FCS */
919 gma_write16(hw, port, GM_RX_CTRL,
920 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
921
922 /* transmit flow control */
923 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
924
925 /* transmit parameter */
926 gma_write16(hw, port, GM_TX_PARAM,
927 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
928 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
929 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
930 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
931
932 /* serial mode register */
933 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
934 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
935
936 if (hw->dev[port]->mtu > ETH_DATA_LEN)
937 reg |= GM_SMOD_JUMBO_ENA;
938
939 gma_write16(hw, port, GM_SERIAL_MODE, reg);
940
941 /* virtual address for data */
942 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
943
944 /* physical address: used for pause frames */
945 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
946
947 /* ignore counter overflows */
948 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
949 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
950 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
951
952 /* Configure Rx MAC FIFO */
953 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
954 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
955 if (hw->chip_id == CHIP_ID_YUKON_EX ||
956 hw->chip_id == CHIP_ID_YUKON_FE_P)
957 rx_reg |= GMF_RX_OVER_ON;
958
959 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
960
961 if (hw->chip_id == CHIP_ID_YUKON_XL) {
962 /* Hardware errata - clear flush mask */
963 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
964 } else {
965 /* Flush Rx MAC FIFO on any flow control or error */
966 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
967 }
968
969 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
970 reg = RX_GMF_FL_THR_DEF + 1;
971 /* Another magic mystery workaround from sk98lin */
972 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
973 hw->chip_rev == CHIP_REV_YU_FE2_A0)
974 reg = 0x178;
975 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
976
977 /* Configure Tx MAC FIFO */
978 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
979 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
980
981 /* On chips without ram buffer, pause is controled by MAC level */
982 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
983 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
984 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
985
986 sky2_set_tx_stfwd(hw, port);
987 }
988
989 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
990 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
991 /* disable dynamic watermark */
992 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
993 reg &= ~TX_DYN_WM_ENA;
994 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
995 }
996 }
997
998 /* Assign Ram Buffer allocation to queue */
999 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1000 {
1001 u32 end;
1002
1003 /* convert from K bytes to qwords used for hw register */
1004 start *= 1024/8;
1005 space *= 1024/8;
1006 end = start + space - 1;
1007
1008 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1009 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1010 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1011 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1012 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1013
1014 if (q == Q_R1 || q == Q_R2) {
1015 u32 tp = space - space/4;
1016
1017 /* On receive queue's set the thresholds
1018 * give receiver priority when > 3/4 full
1019 * send pause when down to 2K
1020 */
1021 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1022 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1023
1024 tp = space - 2048/8;
1025 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1026 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1027 } else {
1028 /* Enable store & forward on Tx queue's because
1029 * Tx FIFO is only 1K on Yukon
1030 */
1031 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1032 }
1033
1034 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1035 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1036 }
1037
1038 /* Setup Bus Memory Interface */
1039 static void sky2_qset(struct sky2_hw *hw, u16 q)
1040 {
1041 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1042 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1043 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1044 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1045 }
1046
1047 /* Setup prefetch unit registers. This is the interface between
1048 * hardware and driver list elements
1049 */
1050 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1051 u64 addr, u32 last)
1052 {
1053 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1054 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1055 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
1056 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
1057 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1058 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1059
1060 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1061 }
1062
1063 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
1064 {
1065 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
1066
1067 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
1068 le->ctrl = 0;
1069 return le;
1070 }
1071
1072 static void tx_init(struct sky2_port *sky2)
1073 {
1074 struct sky2_tx_le *le;
1075
1076 sky2->tx_prod = sky2->tx_cons = 0;
1077 sky2->tx_tcpsum = 0;
1078 sky2->tx_last_mss = 0;
1079
1080 le = get_tx_le(sky2);
1081 le->addr = 0;
1082 le->opcode = OP_ADDR64 | HW_OWNER;
1083 }
1084
1085 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1086 struct sky2_tx_le *le)
1087 {
1088 return sky2->tx_ring + (le - sky2->tx_le);
1089 }
1090
1091 /* Update chip's next pointer */
1092 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1093 {
1094 /* Make sure write' to descriptors are complete before we tell hardware */
1095 wmb();
1096 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1097
1098 /* Synchronize I/O on since next processor may write to tail */
1099 mmiowb();
1100 }
1101
1102
1103 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1104 {
1105 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1106 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1107 le->ctrl = 0;
1108 return le;
1109 }
1110
1111 /* Build description to hardware for one receive segment */
1112 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1113 dma_addr_t map, unsigned len)
1114 {
1115 struct sky2_rx_le *le;
1116
1117 if (sizeof(dma_addr_t) > sizeof(u32)) {
1118 le = sky2_next_rx(sky2);
1119 le->addr = cpu_to_le32(upper_32_bits(map));
1120 le->opcode = OP_ADDR64 | HW_OWNER;
1121 }
1122
1123 le = sky2_next_rx(sky2);
1124 le->addr = cpu_to_le32((u32) map);
1125 le->length = cpu_to_le16(len);
1126 le->opcode = op | HW_OWNER;
1127 }
1128
1129 /* Build description to hardware for one possibly fragmented skb */
1130 static void sky2_rx_submit(struct sky2_port *sky2,
1131 const struct rx_ring_info *re)
1132 {
1133 int i;
1134
1135 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1136
1137 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1138 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1139 }
1140
1141
1142 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1143 unsigned size)
1144 {
1145 struct sk_buff *skb = re->skb;
1146 int i;
1147
1148 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1149 pci_unmap_len_set(re, data_size, size);
1150
1151 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1152 re->frag_addr[i] = pci_map_page(pdev,
1153 skb_shinfo(skb)->frags[i].page,
1154 skb_shinfo(skb)->frags[i].page_offset,
1155 skb_shinfo(skb)->frags[i].size,
1156 PCI_DMA_FROMDEVICE);
1157 }
1158
1159 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1160 {
1161 struct sk_buff *skb = re->skb;
1162 int i;
1163
1164 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1165 PCI_DMA_FROMDEVICE);
1166
1167 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1168 pci_unmap_page(pdev, re->frag_addr[i],
1169 skb_shinfo(skb)->frags[i].size,
1170 PCI_DMA_FROMDEVICE);
1171 }
1172
1173 /* Tell chip where to start receive checksum.
1174 * Actually has two checksums, but set both same to avoid possible byte
1175 * order problems.
1176 */
1177 static void rx_set_checksum(struct sky2_port *sky2)
1178 {
1179 struct sky2_rx_le *le = sky2_next_rx(sky2);
1180
1181 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1182 le->ctrl = 0;
1183 le->opcode = OP_TCPSTART | HW_OWNER;
1184
1185 sky2_write32(sky2->hw,
1186 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1187 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1188 }
1189
1190 /*
1191 * The RX Stop command will not work for Yukon-2 if the BMU does not
1192 * reach the end of packet and since we can't make sure that we have
1193 * incoming data, we must reset the BMU while it is not doing a DMA
1194 * transfer. Since it is possible that the RX path is still active,
1195 * the RX RAM buffer will be stopped first, so any possible incoming
1196 * data will not trigger a DMA. After the RAM buffer is stopped, the
1197 * BMU is polled until any DMA in progress is ended and only then it
1198 * will be reset.
1199 */
1200 static void sky2_rx_stop(struct sky2_port *sky2)
1201 {
1202 struct sky2_hw *hw = sky2->hw;
1203 unsigned rxq = rxqaddr[sky2->port];
1204 int i;
1205
1206 /* disable the RAM Buffer receive queue */
1207 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1208
1209 for (i = 0; i < 0xffff; i++)
1210 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1211 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1212 goto stopped;
1213
1214 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1215 sky2->netdev->name);
1216 stopped:
1217 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1218
1219 /* reset the Rx prefetch unit */
1220 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1221 mmiowb();
1222 }
1223
1224 /* Clean out receive buffer area, assumes receiver hardware stopped */
1225 static void sky2_rx_clean(struct sky2_port *sky2)
1226 {
1227 unsigned i;
1228
1229 memset(sky2->rx_le, 0, RX_LE_BYTES);
1230 for (i = 0; i < sky2->rx_pending; i++) {
1231 struct rx_ring_info *re = sky2->rx_ring + i;
1232
1233 if (re->skb) {
1234 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1235 kfree_skb(re->skb);
1236 re->skb = NULL;
1237 }
1238 }
1239 }
1240
1241 /* Basic MII support */
1242 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1243 {
1244 struct mii_ioctl_data *data = if_mii(ifr);
1245 struct sky2_port *sky2 = netdev_priv(dev);
1246 struct sky2_hw *hw = sky2->hw;
1247 int err = -EOPNOTSUPP;
1248
1249 if (!netif_running(dev))
1250 return -ENODEV; /* Phy still in reset */
1251
1252 switch (cmd) {
1253 case SIOCGMIIPHY:
1254 data->phy_id = PHY_ADDR_MARV;
1255
1256 /* fallthru */
1257 case SIOCGMIIREG: {
1258 u16 val = 0;
1259
1260 spin_lock_bh(&sky2->phy_lock);
1261 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1262 spin_unlock_bh(&sky2->phy_lock);
1263
1264 data->val_out = val;
1265 break;
1266 }
1267
1268 case SIOCSMIIREG:
1269 if (!capable(CAP_NET_ADMIN))
1270 return -EPERM;
1271
1272 spin_lock_bh(&sky2->phy_lock);
1273 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1274 data->val_in);
1275 spin_unlock_bh(&sky2->phy_lock);
1276 break;
1277 }
1278 return err;
1279 }
1280
1281 #ifdef SKY2_VLAN_TAG_USED
1282 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1283 {
1284 if (onoff) {
1285 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1286 RX_VLAN_STRIP_ON);
1287 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1288 TX_VLAN_TAG_ON);
1289 } else {
1290 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1291 RX_VLAN_STRIP_OFF);
1292 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1293 TX_VLAN_TAG_OFF);
1294 }
1295 }
1296
1297 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1298 {
1299 struct sky2_port *sky2 = netdev_priv(dev);
1300 struct sky2_hw *hw = sky2->hw;
1301 u16 port = sky2->port;
1302
1303 netif_tx_lock_bh(dev);
1304 napi_disable(&hw->napi);
1305
1306 sky2->vlgrp = grp;
1307 sky2_set_vlan_mode(hw, port, grp != NULL);
1308
1309 sky2_read32(hw, B0_Y2_SP_LISR);
1310 napi_enable(&hw->napi);
1311 netif_tx_unlock_bh(dev);
1312 }
1313 #endif
1314
1315 /*
1316 * Allocate an skb for receiving. If the MTU is large enough
1317 * make the skb non-linear with a fragment list of pages.
1318 */
1319 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1320 {
1321 struct sk_buff *skb;
1322 int i;
1323
1324 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1325 unsigned char *start;
1326 /*
1327 * Workaround for a bug in FIFO that cause hang
1328 * if the FIFO if the receive buffer is not 64 byte aligned.
1329 * The buffer returned from netdev_alloc_skb is
1330 * aligned except if slab debugging is enabled.
1331 */
1332 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1333 if (!skb)
1334 goto nomem;
1335 start = PTR_ALIGN(skb->data, 8);
1336 skb_reserve(skb, start - skb->data);
1337 } else {
1338 skb = netdev_alloc_skb(sky2->netdev,
1339 sky2->rx_data_size + NET_IP_ALIGN);
1340 if (!skb)
1341 goto nomem;
1342 skb_reserve(skb, NET_IP_ALIGN);
1343 }
1344
1345 for (i = 0; i < sky2->rx_nfrags; i++) {
1346 struct page *page = alloc_page(GFP_ATOMIC);
1347
1348 if (!page)
1349 goto free_partial;
1350 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1351 }
1352
1353 return skb;
1354 free_partial:
1355 kfree_skb(skb);
1356 nomem:
1357 return NULL;
1358 }
1359
1360 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1361 {
1362 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1363 }
1364
1365 /*
1366 * Allocate and setup receiver buffer pool.
1367 * Normal case this ends up creating one list element for skb
1368 * in the receive ring. Worst case if using large MTU and each
1369 * allocation falls on a different 64 bit region, that results
1370 * in 6 list elements per ring entry.
1371 * One element is used for checksum enable/disable, and one
1372 * extra to avoid wrap.
1373 */
1374 static int sky2_rx_start(struct sky2_port *sky2)
1375 {
1376 struct sky2_hw *hw = sky2->hw;
1377 struct rx_ring_info *re;
1378 unsigned rxq = rxqaddr[sky2->port];
1379 unsigned i, size, thresh;
1380
1381 sky2->rx_put = sky2->rx_next = 0;
1382 sky2_qset(hw, rxq);
1383
1384 /* On PCI express lowering the watermark gives better performance */
1385 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1386 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1387
1388 /* These chips have no ram buffer?
1389 * MAC Rx RAM Read is controlled by hardware */
1390 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1391 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1392 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1393 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1394
1395 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1396
1397 if (!(hw->flags & SKY2_HW_NEW_LE))
1398 rx_set_checksum(sky2);
1399
1400 /* Space needed for frame data + headers rounded up */
1401 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1402
1403 /* Stopping point for hardware truncation */
1404 thresh = (size - 8) / sizeof(u32);
1405
1406 sky2->rx_nfrags = size >> PAGE_SHIFT;
1407 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1408
1409 /* Compute residue after pages */
1410 size -= sky2->rx_nfrags << PAGE_SHIFT;
1411
1412 /* Optimize to handle small packets and headers */
1413 if (size < copybreak)
1414 size = copybreak;
1415 if (size < ETH_HLEN)
1416 size = ETH_HLEN;
1417
1418 sky2->rx_data_size = size;
1419
1420 /* Fill Rx ring */
1421 for (i = 0; i < sky2->rx_pending; i++) {
1422 re = sky2->rx_ring + i;
1423
1424 re->skb = sky2_rx_alloc(sky2);
1425 if (!re->skb)
1426 goto nomem;
1427
1428 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1429 sky2_rx_submit(sky2, re);
1430 }
1431
1432 /*
1433 * The receiver hangs if it receives frames larger than the
1434 * packet buffer. As a workaround, truncate oversize frames, but
1435 * the register is limited to 9 bits, so if you do frames > 2052
1436 * you better get the MTU right!
1437 */
1438 if (thresh > 0x1ff)
1439 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1440 else {
1441 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1442 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1443 }
1444
1445 /* Tell chip about available buffers */
1446 sky2_rx_update(sky2, rxq);
1447 return 0;
1448 nomem:
1449 sky2_rx_clean(sky2);
1450 return -ENOMEM;
1451 }
1452
1453 /* Bring up network interface. */
1454 static int sky2_up(struct net_device *dev)
1455 {
1456 struct sky2_port *sky2 = netdev_priv(dev);
1457 struct sky2_hw *hw = sky2->hw;
1458 unsigned port = sky2->port;
1459 u32 imask, ramsize;
1460 int cap, err = -ENOMEM;
1461 struct net_device *otherdev = hw->dev[sky2->port^1];
1462
1463 /*
1464 * On dual port PCI-X card, there is an problem where status
1465 * can be received out of order due to split transactions
1466 */
1467 if (otherdev && netif_running(otherdev) &&
1468 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1469 u16 cmd;
1470
1471 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1472 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1473 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1474
1475 }
1476
1477 if (netif_msg_ifup(sky2))
1478 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1479
1480 netif_carrier_off(dev);
1481
1482 /* must be power of 2 */
1483 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1484 TX_RING_SIZE *
1485 sizeof(struct sky2_tx_le),
1486 &sky2->tx_le_map);
1487 if (!sky2->tx_le)
1488 goto err_out;
1489
1490 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1491 GFP_KERNEL);
1492 if (!sky2->tx_ring)
1493 goto err_out;
1494
1495 tx_init(sky2);
1496
1497 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1498 &sky2->rx_le_map);
1499 if (!sky2->rx_le)
1500 goto err_out;
1501 memset(sky2->rx_le, 0, RX_LE_BYTES);
1502
1503 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1504 GFP_KERNEL);
1505 if (!sky2->rx_ring)
1506 goto err_out;
1507
1508 sky2_mac_init(hw, port);
1509
1510 /* Register is number of 4K blocks on internal RAM buffer. */
1511 ramsize = sky2_read8(hw, B2_E_0) * 4;
1512 if (ramsize > 0) {
1513 u32 rxspace;
1514
1515 hw->flags |= SKY2_HW_RAM_BUFFER;
1516 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1517 if (ramsize < 16)
1518 rxspace = ramsize / 2;
1519 else
1520 rxspace = 8 + (2*(ramsize - 16))/3;
1521
1522 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1523 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1524
1525 /* Make sure SyncQ is disabled */
1526 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1527 RB_RST_SET);
1528 }
1529
1530 sky2_qset(hw, txqaddr[port]);
1531
1532 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1533 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1534 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1535
1536 /* Set almost empty threshold */
1537 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1538 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1539 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1540
1541 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1542 TX_RING_SIZE - 1);
1543
1544 #ifdef SKY2_VLAN_TAG_USED
1545 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1546 #endif
1547
1548 err = sky2_rx_start(sky2);
1549 if (err)
1550 goto err_out;
1551
1552 /* Enable interrupts from phy/mac for port */
1553 imask = sky2_read32(hw, B0_IMSK);
1554 imask |= portirq_msk[port];
1555 sky2_write32(hw, B0_IMSK, imask);
1556
1557 sky2_set_multicast(dev);
1558 return 0;
1559
1560 err_out:
1561 if (sky2->rx_le) {
1562 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1563 sky2->rx_le, sky2->rx_le_map);
1564 sky2->rx_le = NULL;
1565 }
1566 if (sky2->tx_le) {
1567 pci_free_consistent(hw->pdev,
1568 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1569 sky2->tx_le, sky2->tx_le_map);
1570 sky2->tx_le = NULL;
1571 }
1572 kfree(sky2->tx_ring);
1573 kfree(sky2->rx_ring);
1574
1575 sky2->tx_ring = NULL;
1576 sky2->rx_ring = NULL;
1577 return err;
1578 }
1579
1580 /* Modular subtraction in ring */
1581 static inline int tx_dist(unsigned tail, unsigned head)
1582 {
1583 return (head - tail) & (TX_RING_SIZE - 1);
1584 }
1585
1586 /* Number of list elements available for next tx */
1587 static inline int tx_avail(const struct sky2_port *sky2)
1588 {
1589 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1590 }
1591
1592 /* Estimate of number of transmit list elements required */
1593 static unsigned tx_le_req(const struct sk_buff *skb)
1594 {
1595 unsigned count;
1596
1597 count = sizeof(dma_addr_t) / sizeof(u32);
1598 count += skb_shinfo(skb)->nr_frags * count;
1599
1600 if (skb_is_gso(skb))
1601 ++count;
1602
1603 if (skb->ip_summed == CHECKSUM_PARTIAL)
1604 ++count;
1605
1606 return count;
1607 }
1608
1609 /*
1610 * Put one packet in ring for transmit.
1611 * A single packet can generate multiple list elements, and
1612 * the number of ring elements will probably be less than the number
1613 * of list elements used.
1614 */
1615 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1616 {
1617 struct sky2_port *sky2 = netdev_priv(dev);
1618 struct sky2_hw *hw = sky2->hw;
1619 struct sky2_tx_le *le = NULL;
1620 struct tx_ring_info *re;
1621 unsigned i, len;
1622 dma_addr_t mapping;
1623 u16 mss;
1624 u8 ctrl;
1625
1626 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1627 return NETDEV_TX_BUSY;
1628
1629 if (unlikely(netif_msg_tx_queued(sky2)))
1630 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1631 dev->name, sky2->tx_prod, skb->len);
1632
1633 len = skb_headlen(skb);
1634 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1635
1636 /* Send high bits if needed */
1637 if (sizeof(dma_addr_t) > sizeof(u32)) {
1638 le = get_tx_le(sky2);
1639 le->addr = cpu_to_le32(upper_32_bits(mapping));
1640 le->opcode = OP_ADDR64 | HW_OWNER;
1641 }
1642
1643 /* Check for TCP Segmentation Offload */
1644 mss = skb_shinfo(skb)->gso_size;
1645 if (mss != 0) {
1646
1647 if (!(hw->flags & SKY2_HW_NEW_LE))
1648 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1649
1650 if (mss != sky2->tx_last_mss) {
1651 le = get_tx_le(sky2);
1652 le->addr = cpu_to_le32(mss);
1653
1654 if (hw->flags & SKY2_HW_NEW_LE)
1655 le->opcode = OP_MSS | HW_OWNER;
1656 else
1657 le->opcode = OP_LRGLEN | HW_OWNER;
1658 sky2->tx_last_mss = mss;
1659 }
1660 }
1661
1662 ctrl = 0;
1663 #ifdef SKY2_VLAN_TAG_USED
1664 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1665 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1666 if (!le) {
1667 le = get_tx_le(sky2);
1668 le->addr = 0;
1669 le->opcode = OP_VLAN|HW_OWNER;
1670 } else
1671 le->opcode |= OP_VLAN;
1672 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1673 ctrl |= INS_VLAN;
1674 }
1675 #endif
1676
1677 /* Handle TCP checksum offload */
1678 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1679 /* On Yukon EX (some versions) encoding change. */
1680 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1681 ctrl |= CALSUM; /* auto checksum */
1682 else {
1683 const unsigned offset = skb_transport_offset(skb);
1684 u32 tcpsum;
1685
1686 tcpsum = offset << 16; /* sum start */
1687 tcpsum |= offset + skb->csum_offset; /* sum write */
1688
1689 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1690 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1691 ctrl |= UDPTCP;
1692
1693 if (tcpsum != sky2->tx_tcpsum) {
1694 sky2->tx_tcpsum = tcpsum;
1695
1696 le = get_tx_le(sky2);
1697 le->addr = cpu_to_le32(tcpsum);
1698 le->length = 0; /* initial checksum value */
1699 le->ctrl = 1; /* one packet */
1700 le->opcode = OP_TCPLISW | HW_OWNER;
1701 }
1702 }
1703 }
1704
1705 le = get_tx_le(sky2);
1706 le->addr = cpu_to_le32((u32) mapping);
1707 le->length = cpu_to_le16(len);
1708 le->ctrl = ctrl;
1709 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1710
1711 re = tx_le_re(sky2, le);
1712 re->skb = skb;
1713 pci_unmap_addr_set(re, mapaddr, mapping);
1714 pci_unmap_len_set(re, maplen, len);
1715
1716 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1717 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1718
1719 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1720 frag->size, PCI_DMA_TODEVICE);
1721
1722 if (sizeof(dma_addr_t) > sizeof(u32)) {
1723 le = get_tx_le(sky2);
1724 le->addr = cpu_to_le32(upper_32_bits(mapping));
1725 le->ctrl = 0;
1726 le->opcode = OP_ADDR64 | HW_OWNER;
1727 }
1728
1729 le = get_tx_le(sky2);
1730 le->addr = cpu_to_le32((u32) mapping);
1731 le->length = cpu_to_le16(frag->size);
1732 le->ctrl = ctrl;
1733 le->opcode = OP_BUFFER | HW_OWNER;
1734
1735 re = tx_le_re(sky2, le);
1736 re->skb = skb;
1737 pci_unmap_addr_set(re, mapaddr, mapping);
1738 pci_unmap_len_set(re, maplen, frag->size);
1739 }
1740
1741 le->ctrl |= EOP;
1742
1743 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1744 netif_stop_queue(dev);
1745
1746 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1747
1748 dev->trans_start = jiffies;
1749 return NETDEV_TX_OK;
1750 }
1751
1752 /*
1753 * Free ring elements from starting at tx_cons until "done"
1754 *
1755 * NB: the hardware will tell us about partial completion of multi-part
1756 * buffers so make sure not to free skb to early.
1757 */
1758 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1759 {
1760 struct net_device *dev = sky2->netdev;
1761 struct pci_dev *pdev = sky2->hw->pdev;
1762 unsigned idx;
1763
1764 BUG_ON(done >= TX_RING_SIZE);
1765
1766 for (idx = sky2->tx_cons; idx != done;
1767 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1768 struct sky2_tx_le *le = sky2->tx_le + idx;
1769 struct tx_ring_info *re = sky2->tx_ring + idx;
1770
1771 switch(le->opcode & ~HW_OWNER) {
1772 case OP_LARGESEND:
1773 case OP_PACKET:
1774 pci_unmap_single(pdev,
1775 pci_unmap_addr(re, mapaddr),
1776 pci_unmap_len(re, maplen),
1777 PCI_DMA_TODEVICE);
1778 break;
1779 case OP_BUFFER:
1780 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1781 pci_unmap_len(re, maplen),
1782 PCI_DMA_TODEVICE);
1783 break;
1784 }
1785
1786 if (le->ctrl & EOP) {
1787 if (unlikely(netif_msg_tx_done(sky2)))
1788 printk(KERN_DEBUG "%s: tx done %u\n",
1789 dev->name, idx);
1790
1791 dev->stats.tx_packets++;
1792 dev->stats.tx_bytes += re->skb->len;
1793
1794 dev_kfree_skb_any(re->skb);
1795 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1796 }
1797 }
1798
1799 sky2->tx_cons = idx;
1800 smp_mb();
1801
1802 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1803 netif_wake_queue(dev);
1804 }
1805
1806 /* Cleanup all untransmitted buffers, assume transmitter not running */
1807 static void sky2_tx_clean(struct net_device *dev)
1808 {
1809 struct sky2_port *sky2 = netdev_priv(dev);
1810
1811 netif_tx_lock_bh(dev);
1812 sky2_tx_complete(sky2, sky2->tx_prod);
1813 netif_tx_unlock_bh(dev);
1814 }
1815
1816 /* Network shutdown */
1817 static int sky2_down(struct net_device *dev)
1818 {
1819 struct sky2_port *sky2 = netdev_priv(dev);
1820 struct sky2_hw *hw = sky2->hw;
1821 unsigned port = sky2->port;
1822 u16 ctrl;
1823 u32 imask;
1824
1825 /* Never really got started! */
1826 if (!sky2->tx_le)
1827 return 0;
1828
1829 if (netif_msg_ifdown(sky2))
1830 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1831
1832 /* Disable port IRQ */
1833 imask = sky2_read32(hw, B0_IMSK);
1834 imask &= ~portirq_msk[port];
1835 sky2_write32(hw, B0_IMSK, imask);
1836
1837 synchronize_irq(hw->pdev->irq);
1838
1839 sky2_gmac_reset(hw, port);
1840
1841 /* Stop transmitter */
1842 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1843 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1844
1845 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1846 RB_RST_SET | RB_DIS_OP_MD);
1847
1848 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1849 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1850 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1851
1852 /* Make sure no packets are pending */
1853 napi_synchronize(&hw->napi);
1854
1855 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1856
1857 /* Workaround shared GMAC reset */
1858 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1859 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1860 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1861
1862 /* Disable Force Sync bit and Enable Alloc bit */
1863 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1864 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1865
1866 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1867 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1868 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1869
1870 /* Reset the PCI FIFO of the async Tx queue */
1871 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1872 BMU_RST_SET | BMU_FIFO_RST);
1873
1874 /* Reset the Tx prefetch units */
1875 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1876 PREF_UNIT_RST_SET);
1877
1878 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1879
1880 sky2_rx_stop(sky2);
1881
1882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1883 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1884
1885 sky2_phy_power_down(hw, port);
1886
1887 /* turn off LED's */
1888 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1889
1890 sky2_tx_clean(dev);
1891 sky2_rx_clean(sky2);
1892
1893 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1894 sky2->rx_le, sky2->rx_le_map);
1895 kfree(sky2->rx_ring);
1896
1897 pci_free_consistent(hw->pdev,
1898 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1899 sky2->tx_le, sky2->tx_le_map);
1900 kfree(sky2->tx_ring);
1901
1902 sky2->tx_le = NULL;
1903 sky2->rx_le = NULL;
1904
1905 sky2->rx_ring = NULL;
1906 sky2->tx_ring = NULL;
1907
1908 return 0;
1909 }
1910
1911 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1912 {
1913 if (hw->flags & SKY2_HW_FIBRE_PHY)
1914 return SPEED_1000;
1915
1916 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1917 if (aux & PHY_M_PS_SPEED_100)
1918 return SPEED_100;
1919 else
1920 return SPEED_10;
1921 }
1922
1923 switch (aux & PHY_M_PS_SPEED_MSK) {
1924 case PHY_M_PS_SPEED_1000:
1925 return SPEED_1000;
1926 case PHY_M_PS_SPEED_100:
1927 return SPEED_100;
1928 default:
1929 return SPEED_10;
1930 }
1931 }
1932
1933 static void sky2_link_up(struct sky2_port *sky2)
1934 {
1935 struct sky2_hw *hw = sky2->hw;
1936 unsigned port = sky2->port;
1937 u16 reg;
1938 static const char *fc_name[] = {
1939 [FC_NONE] = "none",
1940 [FC_TX] = "tx",
1941 [FC_RX] = "rx",
1942 [FC_BOTH] = "both",
1943 };
1944
1945 /* enable Rx/Tx */
1946 reg = gma_read16(hw, port, GM_GP_CTRL);
1947 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1948 gma_write16(hw, port, GM_GP_CTRL, reg);
1949
1950 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1951
1952 netif_carrier_on(sky2->netdev);
1953
1954 mod_timer(&hw->watchdog_timer, jiffies + 1);
1955
1956 /* Turn on link LED */
1957 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1958 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1959
1960 if (netif_msg_link(sky2))
1961 printk(KERN_INFO PFX
1962 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1963 sky2->netdev->name, sky2->speed,
1964 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1965 fc_name[sky2->flow_status]);
1966 }
1967
1968 static void sky2_link_down(struct sky2_port *sky2)
1969 {
1970 struct sky2_hw *hw = sky2->hw;
1971 unsigned port = sky2->port;
1972 u16 reg;
1973
1974 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1975
1976 reg = gma_read16(hw, port, GM_GP_CTRL);
1977 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1978 gma_write16(hw, port, GM_GP_CTRL, reg);
1979
1980 netif_carrier_off(sky2->netdev);
1981
1982 /* Turn on link LED */
1983 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1984
1985 if (netif_msg_link(sky2))
1986 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1987
1988 sky2_phy_init(hw, port);
1989 }
1990
1991 static enum flow_control sky2_flow(int rx, int tx)
1992 {
1993 if (rx)
1994 return tx ? FC_BOTH : FC_RX;
1995 else
1996 return tx ? FC_TX : FC_NONE;
1997 }
1998
1999 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2000 {
2001 struct sky2_hw *hw = sky2->hw;
2002 unsigned port = sky2->port;
2003 u16 advert, lpa;
2004
2005 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2006 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2007 if (lpa & PHY_M_AN_RF) {
2008 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2009 return -1;
2010 }
2011
2012 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2013 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2014 sky2->netdev->name);
2015 return -1;
2016 }
2017
2018 sky2->speed = sky2_phy_speed(hw, aux);
2019 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2020
2021 /* Since the pause result bits seem to in different positions on
2022 * different chips. look at registers.
2023 */
2024 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2025 /* Shift for bits in fiber PHY */
2026 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2027 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2028
2029 if (advert & ADVERTISE_1000XPAUSE)
2030 advert |= ADVERTISE_PAUSE_CAP;
2031 if (advert & ADVERTISE_1000XPSE_ASYM)
2032 advert |= ADVERTISE_PAUSE_ASYM;
2033 if (lpa & LPA_1000XPAUSE)
2034 lpa |= LPA_PAUSE_CAP;
2035 if (lpa & LPA_1000XPAUSE_ASYM)
2036 lpa |= LPA_PAUSE_ASYM;
2037 }
2038
2039 sky2->flow_status = FC_NONE;
2040 if (advert & ADVERTISE_PAUSE_CAP) {
2041 if (lpa & LPA_PAUSE_CAP)
2042 sky2->flow_status = FC_BOTH;
2043 else if (advert & ADVERTISE_PAUSE_ASYM)
2044 sky2->flow_status = FC_RX;
2045 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2046 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2047 sky2->flow_status = FC_TX;
2048 }
2049
2050 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2051 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2052 sky2->flow_status = FC_NONE;
2053
2054 if (sky2->flow_status & FC_TX)
2055 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2056 else
2057 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2058
2059 return 0;
2060 }
2061
2062 /* Interrupt from PHY */
2063 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2064 {
2065 struct net_device *dev = hw->dev[port];
2066 struct sky2_port *sky2 = netdev_priv(dev);
2067 u16 istatus, phystat;
2068
2069 if (!netif_running(dev))
2070 return;
2071
2072 spin_lock(&sky2->phy_lock);
2073 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2074 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2075
2076 if (netif_msg_intr(sky2))
2077 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2078 sky2->netdev->name, istatus, phystat);
2079
2080 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2081 if (sky2_autoneg_done(sky2, phystat) == 0)
2082 sky2_link_up(sky2);
2083 goto out;
2084 }
2085
2086 if (istatus & PHY_M_IS_LSP_CHANGE)
2087 sky2->speed = sky2_phy_speed(hw, phystat);
2088
2089 if (istatus & PHY_M_IS_DUP_CHANGE)
2090 sky2->duplex =
2091 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2092
2093 if (istatus & PHY_M_IS_LST_CHANGE) {
2094 if (phystat & PHY_M_PS_LINK_UP)
2095 sky2_link_up(sky2);
2096 else
2097 sky2_link_down(sky2);
2098 }
2099 out:
2100 spin_unlock(&sky2->phy_lock);
2101 }
2102
2103 /* Transmit timeout is only called if we are running, carrier is up
2104 * and tx queue is full (stopped).
2105 */
2106 static void sky2_tx_timeout(struct net_device *dev)
2107 {
2108 struct sky2_port *sky2 = netdev_priv(dev);
2109 struct sky2_hw *hw = sky2->hw;
2110
2111 if (netif_msg_timer(sky2))
2112 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2113
2114 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2115 dev->name, sky2->tx_cons, sky2->tx_prod,
2116 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2117 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2118
2119 /* can't restart safely under softirq */
2120 schedule_work(&hw->restart_work);
2121 }
2122
2123 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2124 {
2125 struct sky2_port *sky2 = netdev_priv(dev);
2126 struct sky2_hw *hw = sky2->hw;
2127 unsigned port = sky2->port;
2128 int err;
2129 u16 ctl, mode;
2130 u32 imask;
2131
2132 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2133 return -EINVAL;
2134
2135 if (new_mtu > ETH_DATA_LEN &&
2136 (hw->chip_id == CHIP_ID_YUKON_FE ||
2137 hw->chip_id == CHIP_ID_YUKON_FE_P))
2138 return -EINVAL;
2139
2140 if (!netif_running(dev)) {
2141 dev->mtu = new_mtu;
2142 return 0;
2143 }
2144
2145 imask = sky2_read32(hw, B0_IMSK);
2146 sky2_write32(hw, B0_IMSK, 0);
2147
2148 dev->trans_start = jiffies; /* prevent tx timeout */
2149 netif_stop_queue(dev);
2150 napi_disable(&hw->napi);
2151
2152 synchronize_irq(hw->pdev->irq);
2153
2154 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2155 sky2_set_tx_stfwd(hw, port);
2156
2157 ctl = gma_read16(hw, port, GM_GP_CTRL);
2158 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2159 sky2_rx_stop(sky2);
2160 sky2_rx_clean(sky2);
2161
2162 dev->mtu = new_mtu;
2163
2164 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2165 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2166
2167 if (dev->mtu > ETH_DATA_LEN)
2168 mode |= GM_SMOD_JUMBO_ENA;
2169
2170 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2171
2172 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2173
2174 err = sky2_rx_start(sky2);
2175 sky2_write32(hw, B0_IMSK, imask);
2176
2177 sky2_read32(hw, B0_Y2_SP_LISR);
2178 napi_enable(&hw->napi);
2179
2180 if (err)
2181 dev_close(dev);
2182 else {
2183 gma_write16(hw, port, GM_GP_CTRL, ctl);
2184
2185 netif_wake_queue(dev);
2186 }
2187
2188 return err;
2189 }
2190
2191 /* For small just reuse existing skb for next receive */
2192 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2193 const struct rx_ring_info *re,
2194 unsigned length)
2195 {
2196 struct sk_buff *skb;
2197
2198 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2199 if (likely(skb)) {
2200 skb_reserve(skb, 2);
2201 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2202 length, PCI_DMA_FROMDEVICE);
2203 skb_copy_from_linear_data(re->skb, skb->data, length);
2204 skb->ip_summed = re->skb->ip_summed;
2205 skb->csum = re->skb->csum;
2206 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2207 length, PCI_DMA_FROMDEVICE);
2208 re->skb->ip_summed = CHECKSUM_NONE;
2209 skb_put(skb, length);
2210 }
2211 return skb;
2212 }
2213
2214 /* Adjust length of skb with fragments to match received data */
2215 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2216 unsigned int length)
2217 {
2218 int i, num_frags;
2219 unsigned int size;
2220
2221 /* put header into skb */
2222 size = min(length, hdr_space);
2223 skb->tail += size;
2224 skb->len += size;
2225 length -= size;
2226
2227 num_frags = skb_shinfo(skb)->nr_frags;
2228 for (i = 0; i < num_frags; i++) {
2229 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2230
2231 if (length == 0) {
2232 /* don't need this page */
2233 __free_page(frag->page);
2234 --skb_shinfo(skb)->nr_frags;
2235 } else {
2236 size = min(length, (unsigned) PAGE_SIZE);
2237
2238 frag->size = size;
2239 skb->data_len += size;
2240 skb->truesize += size;
2241 skb->len += size;
2242 length -= size;
2243 }
2244 }
2245 }
2246
2247 /* Normal packet - take skb from ring element and put in a new one */
2248 static struct sk_buff *receive_new(struct sky2_port *sky2,
2249 struct rx_ring_info *re,
2250 unsigned int length)
2251 {
2252 struct sk_buff *skb, *nskb;
2253 unsigned hdr_space = sky2->rx_data_size;
2254
2255 /* Don't be tricky about reusing pages (yet) */
2256 nskb = sky2_rx_alloc(sky2);
2257 if (unlikely(!nskb))
2258 return NULL;
2259
2260 skb = re->skb;
2261 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2262
2263 prefetch(skb->data);
2264 re->skb = nskb;
2265 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2266
2267 if (skb_shinfo(skb)->nr_frags)
2268 skb_put_frags(skb, hdr_space, length);
2269 else
2270 skb_put(skb, length);
2271 return skb;
2272 }
2273
2274 /*
2275 * Receive one packet.
2276 * For larger packets, get new buffer.
2277 */
2278 static struct sk_buff *sky2_receive(struct net_device *dev,
2279 u16 length, u32 status)
2280 {
2281 struct sky2_port *sky2 = netdev_priv(dev);
2282 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2283 struct sk_buff *skb = NULL;
2284 u16 count = (status & GMR_FS_LEN) >> 16;
2285
2286 #ifdef SKY2_VLAN_TAG_USED
2287 /* Account for vlan tag */
2288 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2289 count -= VLAN_HLEN;
2290 #endif
2291
2292 if (unlikely(netif_msg_rx_status(sky2)))
2293 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2294 dev->name, sky2->rx_next, status, length);
2295
2296 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2297 prefetch(sky2->rx_ring + sky2->rx_next);
2298
2299 /* This chip has hardware problems that generates bogus status.
2300 * So do only marginal checking and expect higher level protocols
2301 * to handle crap frames.
2302 */
2303 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2304 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2305 length != count)
2306 goto okay;
2307
2308 if (status & GMR_FS_ANY_ERR)
2309 goto error;
2310
2311 if (!(status & GMR_FS_RX_OK))
2312 goto resubmit;
2313
2314 /* if length reported by DMA does not match PHY, packet was truncated */
2315 if (length != count)
2316 goto len_error;
2317
2318 okay:
2319 if (length < copybreak)
2320 skb = receive_copy(sky2, re, length);
2321 else
2322 skb = receive_new(sky2, re, length);
2323 resubmit:
2324 sky2_rx_submit(sky2, re);
2325
2326 return skb;
2327
2328 len_error:
2329 /* Truncation of overlength packets
2330 causes PHY length to not match MAC length */
2331 ++dev->stats.rx_length_errors;
2332 if (netif_msg_rx_err(sky2) && net_ratelimit())
2333 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2334 dev->name, status, length);
2335 goto resubmit;
2336
2337 error:
2338 ++dev->stats.rx_errors;
2339 if (status & GMR_FS_RX_FF_OV) {
2340 dev->stats.rx_over_errors++;
2341 goto resubmit;
2342 }
2343
2344 if (netif_msg_rx_err(sky2) && net_ratelimit())
2345 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2346 dev->name, status, length);
2347
2348 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2349 dev->stats.rx_length_errors++;
2350 if (status & GMR_FS_FRAGMENT)
2351 dev->stats.rx_frame_errors++;
2352 if (status & GMR_FS_CRC_ERR)
2353 dev->stats.rx_crc_errors++;
2354
2355 goto resubmit;
2356 }
2357
2358 /* Transmit complete */
2359 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2360 {
2361 struct sky2_port *sky2 = netdev_priv(dev);
2362
2363 if (netif_running(dev)) {
2364 netif_tx_lock(dev);
2365 sky2_tx_complete(sky2, last);
2366 netif_tx_unlock(dev);
2367 }
2368 }
2369
2370 /* Process status response ring */
2371 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2372 {
2373 int work_done = 0;
2374 unsigned rx[2] = { 0, 0 };
2375
2376 rmb();
2377 do {
2378 struct sky2_port *sky2;
2379 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2380 unsigned port;
2381 struct net_device *dev;
2382 struct sk_buff *skb;
2383 u32 status;
2384 u16 length;
2385 u8 opcode = le->opcode;
2386
2387 if (!(opcode & HW_OWNER))
2388 break;
2389
2390 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2391
2392 port = le->css & CSS_LINK_BIT;
2393 dev = hw->dev[port];
2394 sky2 = netdev_priv(dev);
2395 length = le16_to_cpu(le->length);
2396 status = le32_to_cpu(le->status);
2397
2398 le->opcode = 0;
2399 switch (opcode & ~HW_OWNER) {
2400 case OP_RXSTAT:
2401 ++rx[port];
2402 skb = sky2_receive(dev, length, status);
2403 if (unlikely(!skb)) {
2404 dev->stats.rx_dropped++;
2405 break;
2406 }
2407
2408 /* This chip reports checksum status differently */
2409 if (hw->flags & SKY2_HW_NEW_LE) {
2410 if (sky2->rx_csum &&
2411 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2412 (le->css & CSS_TCPUDPCSOK))
2413 skb->ip_summed = CHECKSUM_UNNECESSARY;
2414 else
2415 skb->ip_summed = CHECKSUM_NONE;
2416 }
2417
2418 skb->protocol = eth_type_trans(skb, dev);
2419 dev->stats.rx_packets++;
2420 dev->stats.rx_bytes += skb->len;
2421 dev->last_rx = jiffies;
2422
2423 #ifdef SKY2_VLAN_TAG_USED
2424 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2425 vlan_hwaccel_receive_skb(skb,
2426 sky2->vlgrp,
2427 be16_to_cpu(sky2->rx_tag));
2428 } else
2429 #endif
2430 netif_receive_skb(skb);
2431
2432 /* Stop after net poll weight */
2433 if (++work_done >= to_do)
2434 goto exit_loop;
2435 break;
2436
2437 #ifdef SKY2_VLAN_TAG_USED
2438 case OP_RXVLAN:
2439 sky2->rx_tag = length;
2440 break;
2441
2442 case OP_RXCHKSVLAN:
2443 sky2->rx_tag = length;
2444 /* fall through */
2445 #endif
2446 case OP_RXCHKS:
2447 if (!sky2->rx_csum)
2448 break;
2449
2450 /* If this happens then driver assuming wrong format */
2451 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2452 if (net_ratelimit())
2453 printk(KERN_NOTICE "%s: unexpected"
2454 " checksum status\n",
2455 dev->name);
2456 break;
2457 }
2458
2459 /* Both checksum counters are programmed to start at
2460 * the same offset, so unless there is a problem they
2461 * should match. This failure is an early indication that
2462 * hardware receive checksumming won't work.
2463 */
2464 if (likely(status >> 16 == (status & 0xffff))) {
2465 skb = sky2->rx_ring[sky2->rx_next].skb;
2466 skb->ip_summed = CHECKSUM_COMPLETE;
2467 skb->csum = status & 0xffff;
2468 } else {
2469 printk(KERN_NOTICE PFX "%s: hardware receive "
2470 "checksum problem (status = %#x)\n",
2471 dev->name, status);
2472 sky2->rx_csum = 0;
2473 sky2_write32(sky2->hw,
2474 Q_ADDR(rxqaddr[port], Q_CSR),
2475 BMU_DIS_RX_CHKSUM);
2476 }
2477 break;
2478
2479 case OP_TXINDEXLE:
2480 /* TX index reports status for both ports */
2481 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2482 sky2_tx_done(hw->dev[0], status & 0xfff);
2483 if (hw->dev[1])
2484 sky2_tx_done(hw->dev[1],
2485 ((status >> 24) & 0xff)
2486 | (u16)(length & 0xf) << 8);
2487 break;
2488
2489 default:
2490 if (net_ratelimit())
2491 printk(KERN_WARNING PFX
2492 "unknown status opcode 0x%x\n", opcode);
2493 }
2494 } while (hw->st_idx != idx);
2495
2496 /* Fully processed status ring so clear irq */
2497 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2498
2499 exit_loop:
2500 if (rx[0])
2501 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2502
2503 if (rx[1])
2504 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2505
2506 return work_done;
2507 }
2508
2509 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2510 {
2511 struct net_device *dev = hw->dev[port];
2512
2513 if (net_ratelimit())
2514 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2515 dev->name, status);
2516
2517 if (status & Y2_IS_PAR_RD1) {
2518 if (net_ratelimit())
2519 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2520 dev->name);
2521 /* Clear IRQ */
2522 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2523 }
2524
2525 if (status & Y2_IS_PAR_WR1) {
2526 if (net_ratelimit())
2527 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2528 dev->name);
2529
2530 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2531 }
2532
2533 if (status & Y2_IS_PAR_MAC1) {
2534 if (net_ratelimit())
2535 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2536 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2537 }
2538
2539 if (status & Y2_IS_PAR_RX1) {
2540 if (net_ratelimit())
2541 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2542 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2543 }
2544
2545 if (status & Y2_IS_TCP_TXA1) {
2546 if (net_ratelimit())
2547 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2548 dev->name);
2549 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2550 }
2551 }
2552
2553 static void sky2_hw_intr(struct sky2_hw *hw)
2554 {
2555 struct pci_dev *pdev = hw->pdev;
2556 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2557 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2558
2559 status &= hwmsk;
2560
2561 if (status & Y2_IS_TIST_OV)
2562 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2563
2564 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2565 u16 pci_err;
2566
2567 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2568 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2569 if (net_ratelimit())
2570 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2571 pci_err);
2572
2573 sky2_pci_write16(hw, PCI_STATUS,
2574 pci_err | PCI_STATUS_ERROR_BITS);
2575 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2576 }
2577
2578 if (status & Y2_IS_PCI_EXP) {
2579 /* PCI-Express uncorrectable Error occurred */
2580 u32 err;
2581
2582 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2583 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2584 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2585 0xfffffffful);
2586 if (net_ratelimit())
2587 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2588
2589 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2590 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2591 }
2592
2593 if (status & Y2_HWE_L1_MASK)
2594 sky2_hw_error(hw, 0, status);
2595 status >>= 8;
2596 if (status & Y2_HWE_L1_MASK)
2597 sky2_hw_error(hw, 1, status);
2598 }
2599
2600 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2601 {
2602 struct net_device *dev = hw->dev[port];
2603 struct sky2_port *sky2 = netdev_priv(dev);
2604 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2605
2606 if (netif_msg_intr(sky2))
2607 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2608 dev->name, status);
2609
2610 if (status & GM_IS_RX_CO_OV)
2611 gma_read16(hw, port, GM_RX_IRQ_SRC);
2612
2613 if (status & GM_IS_TX_CO_OV)
2614 gma_read16(hw, port, GM_TX_IRQ_SRC);
2615
2616 if (status & GM_IS_RX_FF_OR) {
2617 ++dev->stats.rx_fifo_errors;
2618 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2619 }
2620
2621 if (status & GM_IS_TX_FF_UR) {
2622 ++dev->stats.tx_fifo_errors;
2623 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2624 }
2625 }
2626
2627 /* This should never happen it is a bug. */
2628 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2629 u16 q, unsigned ring_size)
2630 {
2631 struct net_device *dev = hw->dev[port];
2632 struct sky2_port *sky2 = netdev_priv(dev);
2633 unsigned idx;
2634 const u64 *le = (q == Q_R1 || q == Q_R2)
2635 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2636
2637 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2638 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2639 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2640 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2641
2642 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2643 }
2644
2645 static int sky2_rx_hung(struct net_device *dev)
2646 {
2647 struct sky2_port *sky2 = netdev_priv(dev);
2648 struct sky2_hw *hw = sky2->hw;
2649 unsigned port = sky2->port;
2650 unsigned rxq = rxqaddr[port];
2651 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2652 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2653 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2654 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2655
2656 /* If idle and MAC or PCI is stuck */
2657 if (sky2->check.last == dev->last_rx &&
2658 ((mac_rp == sky2->check.mac_rp &&
2659 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2660 /* Check if the PCI RX hang */
2661 (fifo_rp == sky2->check.fifo_rp &&
2662 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2663 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2664 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2665 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2666 return 1;
2667 } else {
2668 sky2->check.last = dev->last_rx;
2669 sky2->check.mac_rp = mac_rp;
2670 sky2->check.mac_lev = mac_lev;
2671 sky2->check.fifo_rp = fifo_rp;
2672 sky2->check.fifo_lev = fifo_lev;
2673 return 0;
2674 }
2675 }
2676
2677 static void sky2_watchdog(unsigned long arg)
2678 {
2679 struct sky2_hw *hw = (struct sky2_hw *) arg;
2680
2681 /* Check for lost IRQ once a second */
2682 if (sky2_read32(hw, B0_ISRC)) {
2683 napi_schedule(&hw->napi);
2684 } else {
2685 int i, active = 0;
2686
2687 for (i = 0; i < hw->ports; i++) {
2688 struct net_device *dev = hw->dev[i];
2689 if (!netif_running(dev))
2690 continue;
2691 ++active;
2692
2693 /* For chips with Rx FIFO, check if stuck */
2694 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2695 sky2_rx_hung(dev)) {
2696 pr_info(PFX "%s: receiver hang detected\n",
2697 dev->name);
2698 schedule_work(&hw->restart_work);
2699 return;
2700 }
2701 }
2702
2703 if (active == 0)
2704 return;
2705 }
2706
2707 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2708 }
2709
2710 /* Hardware/software error handling */
2711 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2712 {
2713 if (net_ratelimit())
2714 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2715
2716 if (status & Y2_IS_HW_ERR)
2717 sky2_hw_intr(hw);
2718
2719 if (status & Y2_IS_IRQ_MAC1)
2720 sky2_mac_intr(hw, 0);
2721
2722 if (status & Y2_IS_IRQ_MAC2)
2723 sky2_mac_intr(hw, 1);
2724
2725 if (status & Y2_IS_CHK_RX1)
2726 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2727
2728 if (status & Y2_IS_CHK_RX2)
2729 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2730
2731 if (status & Y2_IS_CHK_TXA1)
2732 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2733
2734 if (status & Y2_IS_CHK_TXA2)
2735 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2736 }
2737
2738 static int sky2_poll(struct napi_struct *napi, int work_limit)
2739 {
2740 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2741 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2742 int work_done = 0;
2743 u16 idx;
2744
2745 if (unlikely(status & Y2_IS_ERROR))
2746 sky2_err_intr(hw, status);
2747
2748 if (status & Y2_IS_IRQ_PHY1)
2749 sky2_phy_intr(hw, 0);
2750
2751 if (status & Y2_IS_IRQ_PHY2)
2752 sky2_phy_intr(hw, 1);
2753
2754 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2755 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2756
2757 if (work_done >= work_limit)
2758 goto done;
2759 }
2760
2761 /* Bug/Errata workaround?
2762 * Need to kick the TX irq moderation timer.
2763 */
2764 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2765 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2766 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2767 }
2768 napi_complete(napi);
2769 sky2_read32(hw, B0_Y2_SP_LISR);
2770 done:
2771
2772 return work_done;
2773 }
2774
2775 static irqreturn_t sky2_intr(int irq, void *dev_id)
2776 {
2777 struct sky2_hw *hw = dev_id;
2778 u32 status;
2779
2780 /* Reading this mask interrupts as side effect */
2781 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2782 if (status == 0 || status == ~0)
2783 return IRQ_NONE;
2784
2785 prefetch(&hw->st_le[hw->st_idx]);
2786
2787 napi_schedule(&hw->napi);
2788
2789 return IRQ_HANDLED;
2790 }
2791
2792 #ifdef CONFIG_NET_POLL_CONTROLLER
2793 static void sky2_netpoll(struct net_device *dev)
2794 {
2795 struct sky2_port *sky2 = netdev_priv(dev);
2796
2797 napi_schedule(&sky2->hw->napi);
2798 }
2799 #endif
2800
2801 /* Chip internal frequency for clock calculations */
2802 static u32 sky2_mhz(const struct sky2_hw *hw)
2803 {
2804 switch (hw->chip_id) {
2805 case CHIP_ID_YUKON_EC:
2806 case CHIP_ID_YUKON_EC_U:
2807 case CHIP_ID_YUKON_EX:
2808 case CHIP_ID_YUKON_SUPR:
2809 case CHIP_ID_YUKON_UL_2:
2810 return 125;
2811
2812 case CHIP_ID_YUKON_FE:
2813 return 100;
2814
2815 case CHIP_ID_YUKON_FE_P:
2816 return 50;
2817
2818 case CHIP_ID_YUKON_XL:
2819 return 156;
2820
2821 default:
2822 BUG();
2823 }
2824 }
2825
2826 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2827 {
2828 return sky2_mhz(hw) * us;
2829 }
2830
2831 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2832 {
2833 return clk / sky2_mhz(hw);
2834 }
2835
2836
2837 static int __devinit sky2_init(struct sky2_hw *hw)
2838 {
2839 u8 t8;
2840
2841 /* Enable all clocks and check for bad PCI access */
2842 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2843
2844 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2845
2846 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2847 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2848
2849 switch(hw->chip_id) {
2850 case CHIP_ID_YUKON_XL:
2851 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2852 break;
2853
2854 case CHIP_ID_YUKON_EC_U:
2855 hw->flags = SKY2_HW_GIGABIT
2856 | SKY2_HW_NEWER_PHY
2857 | SKY2_HW_ADV_POWER_CTL;
2858
2859 /* check for Rev. A1 dev 4200 */
2860 if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0)
2861 hw->flags |= SKY2_HW_CLK_POWER;
2862 break;
2863
2864 case CHIP_ID_YUKON_EX:
2865 hw->flags = SKY2_HW_GIGABIT
2866 | SKY2_HW_NEWER_PHY
2867 | SKY2_HW_NEW_LE
2868 | SKY2_HW_ADV_POWER_CTL;
2869
2870 /* New transmit checksum */
2871 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2872 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2873 break;
2874
2875 case CHIP_ID_YUKON_EC:
2876 /* This rev is really old, and requires untested workarounds */
2877 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2878 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2879 return -EOPNOTSUPP;
2880 }
2881 hw->flags = SKY2_HW_GIGABIT;
2882 break;
2883
2884 case CHIP_ID_YUKON_FE:
2885 break;
2886
2887 case CHIP_ID_YUKON_FE_P:
2888 hw->flags = SKY2_HW_NEWER_PHY
2889 | SKY2_HW_NEW_LE
2890 | SKY2_HW_AUTO_TX_SUM
2891 | SKY2_HW_ADV_POWER_CTL;
2892 break;
2893
2894 case CHIP_ID_YUKON_SUPR:
2895 hw->flags = SKY2_HW_GIGABIT
2896 | SKY2_HW_NEWER_PHY
2897 | SKY2_HW_NEW_LE
2898 | SKY2_HW_AUTO_TX_SUM
2899 | SKY2_HW_ADV_POWER_CTL;
2900 break;
2901
2902 case CHIP_ID_YUKON_UL_2:
2903 hw->flags = SKY2_HW_GIGABIT
2904 | SKY2_HW_ADV_POWER_CTL;
2905 break;
2906
2907 default:
2908 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2909 hw->chip_id);
2910 return -EOPNOTSUPP;
2911 }
2912
2913 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2914 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2915 hw->flags |= SKY2_HW_FIBRE_PHY;
2916
2917 hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM);
2918 if (hw->pm_cap == 0) {
2919 dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n");
2920 return -EIO;
2921 }
2922
2923 hw->ports = 1;
2924 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2925 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2926 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2927 ++hw->ports;
2928 }
2929
2930 return 0;
2931 }
2932
2933 static void sky2_reset(struct sky2_hw *hw)
2934 {
2935 struct pci_dev *pdev = hw->pdev;
2936 u16 status;
2937 int i, cap;
2938 u32 hwe_mask = Y2_HWE_ALL_MASK;
2939
2940 /* disable ASF */
2941 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2942 status = sky2_read16(hw, HCU_CCSR);
2943 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2944 HCU_CCSR_UC_STATE_MSK);
2945 sky2_write16(hw, HCU_CCSR, status);
2946 } else
2947 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2948 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2949
2950 /* do a SW reset */
2951 sky2_write8(hw, B0_CTST, CS_RST_SET);
2952 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2953
2954 /* allow writes to PCI config */
2955 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2956
2957 /* clear PCI errors, if any */
2958 status = sky2_pci_read16(hw, PCI_STATUS);
2959 status |= PCI_STATUS_ERROR_BITS;
2960 sky2_pci_write16(hw, PCI_STATUS, status);
2961
2962 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2963
2964 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2965 if (cap) {
2966 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2967 0xfffffffful);
2968
2969 /* If error bit is stuck on ignore it */
2970 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2971 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2972 else
2973 hwe_mask |= Y2_IS_PCI_EXP;
2974 }
2975
2976 sky2_power_on(hw);
2977 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2978
2979 for (i = 0; i < hw->ports; i++) {
2980 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2981 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2982
2983 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2984 hw->chip_id == CHIP_ID_YUKON_SUPR)
2985 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2986 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2987 | GMC_BYP_RETR_ON);
2988 }
2989
2990 /* Clear I2C IRQ noise */
2991 sky2_write32(hw, B2_I2C_IRQ, 1);
2992
2993 /* turn off hardware timer (unused) */
2994 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2995 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2996
2997 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2998
2999 /* Turn off descriptor polling */
3000 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3001
3002 /* Turn off receive timestamp */
3003 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3004 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3005
3006 /* enable the Tx Arbiters */
3007 for (i = 0; i < hw->ports; i++)
3008 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3009
3010 /* Initialize ram interface */
3011 for (i = 0; i < hw->ports; i++) {
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3013
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3015 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3016 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3017 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3019 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3021 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3022 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3023 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3024 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3025 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3026 }
3027
3028 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3029
3030 for (i = 0; i < hw->ports; i++)
3031 sky2_gmac_reset(hw, i);
3032
3033 memset(hw->st_le, 0, STATUS_LE_BYTES);
3034 hw->st_idx = 0;
3035
3036 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3037 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3038
3039 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3040 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3041
3042 /* Set the list last index */
3043 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3044
3045 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3046 sky2_write8(hw, STAT_FIFO_WM, 16);
3047
3048 /* set Status-FIFO ISR watermark */
3049 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3050 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3051 else
3052 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3053
3054 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3055 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3056 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3057
3058 /* enable status unit */
3059 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3060
3061 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3062 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3063 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3064 }
3065
3066 static void sky2_restart(struct work_struct *work)
3067 {
3068 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3069 struct net_device *dev;
3070 int i, err;
3071
3072 rtnl_lock();
3073 for (i = 0; i < hw->ports; i++) {
3074 dev = hw->dev[i];
3075 if (netif_running(dev))
3076 sky2_down(dev);
3077 }
3078
3079 napi_disable(&hw->napi);
3080 sky2_write32(hw, B0_IMSK, 0);
3081 sky2_reset(hw);
3082 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3083 napi_enable(&hw->napi);
3084
3085 for (i = 0; i < hw->ports; i++) {
3086 dev = hw->dev[i];
3087 if (netif_running(dev)) {
3088 err = sky2_up(dev);
3089 if (err) {
3090 printk(KERN_INFO PFX "%s: could not restart %d\n",
3091 dev->name, err);
3092 dev_close(dev);
3093 }
3094 }
3095 }
3096
3097 rtnl_unlock();
3098 }
3099
3100 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3101 {
3102 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3103 }
3104
3105 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3106 {
3107 const struct sky2_port *sky2 = netdev_priv(dev);
3108
3109 wol->supported = sky2_wol_supported(sky2->hw);
3110 wol->wolopts = sky2->wol;
3111 }
3112
3113 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3114 {
3115 struct sky2_port *sky2 = netdev_priv(dev);
3116 struct sky2_hw *hw = sky2->hw;
3117
3118 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3119 return -EOPNOTSUPP;
3120
3121 sky2->wol = wol->wolopts;
3122
3123 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3124 hw->chip_id == CHIP_ID_YUKON_EX ||
3125 hw->chip_id == CHIP_ID_YUKON_FE_P)
3126 sky2_write32(hw, B0_CTST, sky2->wol
3127 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3128
3129 if (!netif_running(dev))
3130 sky2_wol_init(sky2);
3131 return 0;
3132 }
3133
3134 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3135 {
3136 if (sky2_is_copper(hw)) {
3137 u32 modes = SUPPORTED_10baseT_Half
3138 | SUPPORTED_10baseT_Full
3139 | SUPPORTED_100baseT_Half
3140 | SUPPORTED_100baseT_Full
3141 | SUPPORTED_Autoneg | SUPPORTED_TP;
3142
3143 if (hw->flags & SKY2_HW_GIGABIT)
3144 modes |= SUPPORTED_1000baseT_Half
3145 | SUPPORTED_1000baseT_Full;
3146 return modes;
3147 } else
3148 return SUPPORTED_1000baseT_Half
3149 | SUPPORTED_1000baseT_Full
3150 | SUPPORTED_Autoneg
3151 | SUPPORTED_FIBRE;
3152 }
3153
3154 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3155 {
3156 struct sky2_port *sky2 = netdev_priv(dev);
3157 struct sky2_hw *hw = sky2->hw;
3158
3159 ecmd->transceiver = XCVR_INTERNAL;
3160 ecmd->supported = sky2_supported_modes(hw);
3161 ecmd->phy_address = PHY_ADDR_MARV;
3162 if (sky2_is_copper(hw)) {
3163 ecmd->port = PORT_TP;
3164 ecmd->speed = sky2->speed;
3165 } else {
3166 ecmd->speed = SPEED_1000;
3167 ecmd->port = PORT_FIBRE;
3168 }
3169
3170 ecmd->advertising = sky2->advertising;
3171 ecmd->autoneg = sky2->autoneg;
3172 ecmd->duplex = sky2->duplex;
3173 return 0;
3174 }
3175
3176 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3177 {
3178 struct sky2_port *sky2 = netdev_priv(dev);
3179 const struct sky2_hw *hw = sky2->hw;
3180 u32 supported = sky2_supported_modes(hw);
3181
3182 if (ecmd->autoneg == AUTONEG_ENABLE) {
3183 ecmd->advertising = supported;
3184 sky2->duplex = -1;
3185 sky2->speed = -1;
3186 } else {
3187 u32 setting;
3188
3189 switch (ecmd->speed) {
3190 case SPEED_1000:
3191 if (ecmd->duplex == DUPLEX_FULL)
3192 setting = SUPPORTED_1000baseT_Full;
3193 else if (ecmd->duplex == DUPLEX_HALF)
3194 setting = SUPPORTED_1000baseT_Half;
3195 else
3196 return -EINVAL;
3197 break;
3198 case SPEED_100:
3199 if (ecmd->duplex == DUPLEX_FULL)
3200 setting = SUPPORTED_100baseT_Full;
3201 else if (ecmd->duplex == DUPLEX_HALF)
3202 setting = SUPPORTED_100baseT_Half;
3203 else
3204 return -EINVAL;
3205 break;
3206
3207 case SPEED_10:
3208 if (ecmd->duplex == DUPLEX_FULL)
3209 setting = SUPPORTED_10baseT_Full;
3210 else if (ecmd->duplex == DUPLEX_HALF)
3211 setting = SUPPORTED_10baseT_Half;
3212 else
3213 return -EINVAL;
3214 break;
3215 default:
3216 return -EINVAL;
3217 }
3218
3219 if ((setting & supported) == 0)
3220 return -EINVAL;
3221
3222 sky2->speed = ecmd->speed;
3223 sky2->duplex = ecmd->duplex;
3224 }
3225
3226 sky2->autoneg = ecmd->autoneg;
3227 sky2->advertising = ecmd->advertising;
3228
3229 if (netif_running(dev)) {
3230 sky2_phy_reinit(sky2);
3231 sky2_set_multicast(dev);
3232 }
3233
3234 return 0;
3235 }
3236
3237 static void sky2_get_drvinfo(struct net_device *dev,
3238 struct ethtool_drvinfo *info)
3239 {
3240 struct sky2_port *sky2 = netdev_priv(dev);
3241
3242 strcpy(info->driver, DRV_NAME);
3243 strcpy(info->version, DRV_VERSION);
3244 strcpy(info->fw_version, "N/A");
3245 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3246 }
3247
3248 static const struct sky2_stat {
3249 char name[ETH_GSTRING_LEN];
3250 u16 offset;
3251 } sky2_stats[] = {
3252 { "tx_bytes", GM_TXO_OK_HI },
3253 { "rx_bytes", GM_RXO_OK_HI },
3254 { "tx_broadcast", GM_TXF_BC_OK },
3255 { "rx_broadcast", GM_RXF_BC_OK },
3256 { "tx_multicast", GM_TXF_MC_OK },
3257 { "rx_multicast", GM_RXF_MC_OK },
3258 { "tx_unicast", GM_TXF_UC_OK },
3259 { "rx_unicast", GM_RXF_UC_OK },
3260 { "tx_mac_pause", GM_TXF_MPAUSE },
3261 { "rx_mac_pause", GM_RXF_MPAUSE },
3262 { "collisions", GM_TXF_COL },
3263 { "late_collision",GM_TXF_LAT_COL },
3264 { "aborted", GM_TXF_ABO_COL },
3265 { "single_collisions", GM_TXF_SNG_COL },
3266 { "multi_collisions", GM_TXF_MUL_COL },
3267
3268 { "rx_short", GM_RXF_SHT },
3269 { "rx_runt", GM_RXE_FRAG },
3270 { "rx_64_byte_packets", GM_RXF_64B },
3271 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3272 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3273 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3274 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3275 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3276 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3277 { "rx_too_long", GM_RXF_LNG_ERR },
3278 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3279 { "rx_jabber", GM_RXF_JAB_PKT },
3280 { "rx_fcs_error", GM_RXF_FCS_ERR },
3281
3282 { "tx_64_byte_packets", GM_TXF_64B },
3283 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3284 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3285 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3286 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3287 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3288 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3289 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3290 };
3291
3292 static u32 sky2_get_rx_csum(struct net_device *dev)
3293 {
3294 struct sky2_port *sky2 = netdev_priv(dev);
3295
3296 return sky2->rx_csum;
3297 }
3298
3299 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3300 {
3301 struct sky2_port *sky2 = netdev_priv(dev);
3302
3303 sky2->rx_csum = data;
3304
3305 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3306 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3307
3308 return 0;
3309 }
3310
3311 static u32 sky2_get_msglevel(struct net_device *netdev)
3312 {
3313 struct sky2_port *sky2 = netdev_priv(netdev);
3314 return sky2->msg_enable;
3315 }
3316
3317 static int sky2_nway_reset(struct net_device *dev)
3318 {
3319 struct sky2_port *sky2 = netdev_priv(dev);
3320
3321 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3322 return -EINVAL;
3323
3324 sky2_phy_reinit(sky2);
3325 sky2_set_multicast(dev);
3326
3327 return 0;
3328 }
3329
3330 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3331 {
3332 struct sky2_hw *hw = sky2->hw;
3333 unsigned port = sky2->port;
3334 int i;
3335
3336 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3337 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3338 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3339 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3340
3341 for (i = 2; i < count; i++)
3342 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3343 }
3344
3345 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3346 {
3347 struct sky2_port *sky2 = netdev_priv(netdev);
3348 sky2->msg_enable = value;
3349 }
3350
3351 static int sky2_get_sset_count(struct net_device *dev, int sset)
3352 {
3353 switch (sset) {
3354 case ETH_SS_STATS:
3355 return ARRAY_SIZE(sky2_stats);
3356 default:
3357 return -EOPNOTSUPP;
3358 }
3359 }
3360
3361 static void sky2_get_ethtool_stats(struct net_device *dev,
3362 struct ethtool_stats *stats, u64 * data)
3363 {
3364 struct sky2_port *sky2 = netdev_priv(dev);
3365
3366 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3367 }
3368
3369 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3370 {
3371 int i;
3372
3373 switch (stringset) {
3374 case ETH_SS_STATS:
3375 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3376 memcpy(data + i * ETH_GSTRING_LEN,
3377 sky2_stats[i].name, ETH_GSTRING_LEN);
3378 break;
3379 }
3380 }
3381
3382 static int sky2_set_mac_address(struct net_device *dev, void *p)
3383 {
3384 struct sky2_port *sky2 = netdev_priv(dev);
3385 struct sky2_hw *hw = sky2->hw;
3386 unsigned port = sky2->port;
3387 const struct sockaddr *addr = p;
3388
3389 if (!is_valid_ether_addr(addr->sa_data))
3390 return -EADDRNOTAVAIL;
3391
3392 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3393 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3394 dev->dev_addr, ETH_ALEN);
3395 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3396 dev->dev_addr, ETH_ALEN);
3397
3398 /* virtual address for data */
3399 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3400
3401 /* physical address: used for pause frames */
3402 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3403
3404 return 0;
3405 }
3406
3407 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3408 {
3409 u32 bit;
3410
3411 bit = ether_crc(ETH_ALEN, addr) & 63;
3412 filter[bit >> 3] |= 1 << (bit & 7);
3413 }
3414
3415 static void sky2_set_multicast(struct net_device *dev)
3416 {
3417 struct sky2_port *sky2 = netdev_priv(dev);
3418 struct sky2_hw *hw = sky2->hw;
3419 unsigned port = sky2->port;
3420 struct dev_mc_list *list = dev->mc_list;
3421 u16 reg;
3422 u8 filter[8];
3423 int rx_pause;
3424 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3425
3426 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3427 memset(filter, 0, sizeof(filter));
3428
3429 reg = gma_read16(hw, port, GM_RX_CTRL);
3430 reg |= GM_RXCR_UCF_ENA;
3431
3432 if (dev->flags & IFF_PROMISC) /* promiscuous */
3433 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3434 else if (dev->flags & IFF_ALLMULTI)
3435 memset(filter, 0xff, sizeof(filter));
3436 else if (dev->mc_count == 0 && !rx_pause)
3437 reg &= ~GM_RXCR_MCF_ENA;
3438 else {
3439 int i;
3440 reg |= GM_RXCR_MCF_ENA;
3441
3442 if (rx_pause)
3443 sky2_add_filter(filter, pause_mc_addr);
3444
3445 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3446 sky2_add_filter(filter, list->dmi_addr);
3447 }
3448
3449 gma_write16(hw, port, GM_MC_ADDR_H1,
3450 (u16) filter[0] | ((u16) filter[1] << 8));
3451 gma_write16(hw, port, GM_MC_ADDR_H2,
3452 (u16) filter[2] | ((u16) filter[3] << 8));
3453 gma_write16(hw, port, GM_MC_ADDR_H3,
3454 (u16) filter[4] | ((u16) filter[5] << 8));
3455 gma_write16(hw, port, GM_MC_ADDR_H4,
3456 (u16) filter[6] | ((u16) filter[7] << 8));
3457
3458 gma_write16(hw, port, GM_RX_CTRL, reg);
3459 }
3460
3461 /* Can have one global because blinking is controlled by
3462 * ethtool and that is always under RTNL mutex
3463 */
3464 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3465 {
3466 struct sky2_hw *hw = sky2->hw;
3467 unsigned port = sky2->port;
3468
3469 spin_lock_bh(&sky2->phy_lock);
3470 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3471 hw->chip_id == CHIP_ID_YUKON_EX ||
3472 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3473 u16 pg;
3474 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3475 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3476
3477 switch (mode) {
3478 case MO_LED_OFF:
3479 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3480 PHY_M_LEDC_LOS_CTRL(8) |
3481 PHY_M_LEDC_INIT_CTRL(8) |
3482 PHY_M_LEDC_STA1_CTRL(8) |
3483 PHY_M_LEDC_STA0_CTRL(8));
3484 break;
3485 case MO_LED_ON:
3486 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3487 PHY_M_LEDC_LOS_CTRL(9) |
3488 PHY_M_LEDC_INIT_CTRL(9) |
3489 PHY_M_LEDC_STA1_CTRL(9) |
3490 PHY_M_LEDC_STA0_CTRL(9));
3491 break;
3492 case MO_LED_BLINK:
3493 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3494 PHY_M_LEDC_LOS_CTRL(0xa) |
3495 PHY_M_LEDC_INIT_CTRL(0xa) |
3496 PHY_M_LEDC_STA1_CTRL(0xa) |
3497 PHY_M_LEDC_STA0_CTRL(0xa));
3498 break;
3499 case MO_LED_NORM:
3500 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3501 PHY_M_LEDC_LOS_CTRL(1) |
3502 PHY_M_LEDC_INIT_CTRL(8) |
3503 PHY_M_LEDC_STA1_CTRL(7) |
3504 PHY_M_LEDC_STA0_CTRL(7));
3505 }
3506
3507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3508 } else
3509 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3510 PHY_M_LED_MO_DUP(mode) |
3511 PHY_M_LED_MO_10(mode) |
3512 PHY_M_LED_MO_100(mode) |
3513 PHY_M_LED_MO_1000(mode) |
3514 PHY_M_LED_MO_RX(mode) |
3515 PHY_M_LED_MO_TX(mode));
3516
3517 spin_unlock_bh(&sky2->phy_lock);
3518 }
3519
3520 /* blink LED's for finding board */
3521 static int sky2_phys_id(struct net_device *dev, u32 data)
3522 {
3523 struct sky2_port *sky2 = netdev_priv(dev);
3524 unsigned int i;
3525
3526 if (data == 0)
3527 data = UINT_MAX;
3528
3529 for (i = 0; i < data; i++) {
3530 sky2_led(sky2, MO_LED_ON);
3531 if (msleep_interruptible(500))
3532 break;
3533 sky2_led(sky2, MO_LED_OFF);
3534 if (msleep_interruptible(500))
3535 break;
3536 }
3537 sky2_led(sky2, MO_LED_NORM);
3538
3539 return 0;
3540 }
3541
3542 static void sky2_get_pauseparam(struct net_device *dev,
3543 struct ethtool_pauseparam *ecmd)
3544 {
3545 struct sky2_port *sky2 = netdev_priv(dev);
3546
3547 switch (sky2->flow_mode) {
3548 case FC_NONE:
3549 ecmd->tx_pause = ecmd->rx_pause = 0;
3550 break;
3551 case FC_TX:
3552 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3553 break;
3554 case FC_RX:
3555 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3556 break;
3557 case FC_BOTH:
3558 ecmd->tx_pause = ecmd->rx_pause = 1;
3559 }
3560
3561 ecmd->autoneg = sky2->autoneg;
3562 }
3563
3564 static int sky2_set_pauseparam(struct net_device *dev,
3565 struct ethtool_pauseparam *ecmd)
3566 {
3567 struct sky2_port *sky2 = netdev_priv(dev);
3568
3569 sky2->autoneg = ecmd->autoneg;
3570 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3571
3572 if (netif_running(dev))
3573 sky2_phy_reinit(sky2);
3574
3575 return 0;
3576 }
3577
3578 static int sky2_get_coalesce(struct net_device *dev,
3579 struct ethtool_coalesce *ecmd)
3580 {
3581 struct sky2_port *sky2 = netdev_priv(dev);
3582 struct sky2_hw *hw = sky2->hw;
3583
3584 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3585 ecmd->tx_coalesce_usecs = 0;
3586 else {
3587 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3588 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3589 }
3590 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3591
3592 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3593 ecmd->rx_coalesce_usecs = 0;
3594 else {
3595 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3596 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3597 }
3598 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3599
3600 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3601 ecmd->rx_coalesce_usecs_irq = 0;
3602 else {
3603 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3604 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3605 }
3606
3607 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3608
3609 return 0;
3610 }
3611
3612 /* Note: this affect both ports */
3613 static int sky2_set_coalesce(struct net_device *dev,
3614 struct ethtool_coalesce *ecmd)
3615 {
3616 struct sky2_port *sky2 = netdev_priv(dev);
3617 struct sky2_hw *hw = sky2->hw;
3618 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3619
3620 if (ecmd->tx_coalesce_usecs > tmax ||
3621 ecmd->rx_coalesce_usecs > tmax ||
3622 ecmd->rx_coalesce_usecs_irq > tmax)
3623 return -EINVAL;
3624
3625 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3626 return -EINVAL;
3627 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3628 return -EINVAL;
3629 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3630 return -EINVAL;
3631
3632 if (ecmd->tx_coalesce_usecs == 0)
3633 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3634 else {
3635 sky2_write32(hw, STAT_TX_TIMER_INI,
3636 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3637 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3638 }
3639 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3640
3641 if (ecmd->rx_coalesce_usecs == 0)
3642 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3643 else {
3644 sky2_write32(hw, STAT_LEV_TIMER_INI,
3645 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3646 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3647 }
3648 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3649
3650 if (ecmd->rx_coalesce_usecs_irq == 0)
3651 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3652 else {
3653 sky2_write32(hw, STAT_ISR_TIMER_INI,
3654 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3655 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3656 }
3657 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3658 return 0;
3659 }
3660
3661 static void sky2_get_ringparam(struct net_device *dev,
3662 struct ethtool_ringparam *ering)
3663 {
3664 struct sky2_port *sky2 = netdev_priv(dev);
3665
3666 ering->rx_max_pending = RX_MAX_PENDING;
3667 ering->rx_mini_max_pending = 0;
3668 ering->rx_jumbo_max_pending = 0;
3669 ering->tx_max_pending = TX_RING_SIZE - 1;
3670
3671 ering->rx_pending = sky2->rx_pending;
3672 ering->rx_mini_pending = 0;
3673 ering->rx_jumbo_pending = 0;
3674 ering->tx_pending = sky2->tx_pending;
3675 }
3676
3677 static int sky2_set_ringparam(struct net_device *dev,
3678 struct ethtool_ringparam *ering)
3679 {
3680 struct sky2_port *sky2 = netdev_priv(dev);
3681 int err = 0;
3682
3683 if (ering->rx_pending > RX_MAX_PENDING ||
3684 ering->rx_pending < 8 ||
3685 ering->tx_pending < MAX_SKB_TX_LE ||
3686 ering->tx_pending > TX_RING_SIZE - 1)
3687 return -EINVAL;
3688
3689 if (netif_running(dev))
3690 sky2_down(dev);
3691
3692 sky2->rx_pending = ering->rx_pending;
3693 sky2->tx_pending = ering->tx_pending;
3694
3695 if (netif_running(dev)) {
3696 err = sky2_up(dev);
3697 if (err)
3698 dev_close(dev);
3699 }
3700
3701 return err;
3702 }
3703
3704 static int sky2_get_regs_len(struct net_device *dev)
3705 {
3706 return 0x4000;
3707 }
3708
3709 /*
3710 * Returns copy of control register region
3711 * Note: ethtool_get_regs always provides full size (16k) buffer
3712 */
3713 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3714 void *p)
3715 {
3716 const struct sky2_port *sky2 = netdev_priv(dev);
3717 const void __iomem *io = sky2->hw->regs;
3718 unsigned int b;
3719
3720 regs->version = 1;
3721
3722 for (b = 0; b < 128; b++) {
3723 /* This complicated switch statement is to make sure and
3724 * only access regions that are unreserved.
3725 * Some blocks are only valid on dual port cards.
3726 * and block 3 has some special diagnostic registers that
3727 * are poison.
3728 */
3729 switch (b) {
3730 case 3:
3731 /* skip diagnostic ram region */
3732 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3733 break;
3734
3735 /* dual port cards only */
3736 case 5: /* Tx Arbiter 2 */
3737 case 9: /* RX2 */
3738 case 14 ... 15: /* TX2 */
3739 case 17: case 19: /* Ram Buffer 2 */
3740 case 22 ... 23: /* Tx Ram Buffer 2 */
3741 case 25: /* Rx MAC Fifo 1 */
3742 case 27: /* Tx MAC Fifo 2 */
3743 case 31: /* GPHY 2 */
3744 case 40 ... 47: /* Pattern Ram 2 */
3745 case 52: case 54: /* TCP Segmentation 2 */
3746 case 112 ... 116: /* GMAC 2 */
3747 if (sky2->hw->ports == 1)
3748 goto reserved;
3749 /* fall through */
3750 case 0: /* Control */
3751 case 2: /* Mac address */
3752 case 4: /* Tx Arbiter 1 */
3753 case 7: /* PCI express reg */
3754 case 8: /* RX1 */
3755 case 12 ... 13: /* TX1 */
3756 case 16: case 18:/* Rx Ram Buffer 1 */
3757 case 20 ... 21: /* Tx Ram Buffer 1 */
3758 case 24: /* Rx MAC Fifo 1 */
3759 case 26: /* Tx MAC Fifo 1 */
3760 case 28 ... 29: /* Descriptor and status unit */
3761 case 30: /* GPHY 1*/
3762 case 32 ... 39: /* Pattern Ram 1 */
3763 case 48: case 50: /* TCP Segmentation 1 */
3764 case 56 ... 60: /* PCI space */
3765 case 80 ... 84: /* GMAC 1 */
3766 memcpy_fromio(p, io, 128);
3767 break;
3768 default:
3769 reserved:
3770 memset(p, 0, 128);
3771 }
3772
3773 p += 128;
3774 io += 128;
3775 }
3776 }
3777
3778 /* In order to do Jumbo packets on these chips, need to turn off the
3779 * transmit store/forward. Therefore checksum offload won't work.
3780 */
3781 static int no_tx_offload(struct net_device *dev)
3782 {
3783 const struct sky2_port *sky2 = netdev_priv(dev);
3784 const struct sky2_hw *hw = sky2->hw;
3785
3786 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3787 }
3788
3789 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3790 {
3791 if (data && no_tx_offload(dev))
3792 return -EINVAL;
3793
3794 return ethtool_op_set_tx_csum(dev, data);
3795 }
3796
3797
3798 static int sky2_set_tso(struct net_device *dev, u32 data)
3799 {
3800 if (data && no_tx_offload(dev))
3801 return -EINVAL;
3802
3803 return ethtool_op_set_tso(dev, data);
3804 }
3805
3806 static int sky2_get_eeprom_len(struct net_device *dev)
3807 {
3808 struct sky2_port *sky2 = netdev_priv(dev);
3809 struct sky2_hw *hw = sky2->hw;
3810 u16 reg2;
3811
3812 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3813 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3814 }
3815
3816 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3817 {
3818 u32 val;
3819
3820 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3821
3822 do {
3823 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3824 } while (!(offset & PCI_VPD_ADDR_F));
3825
3826 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3827 return val;
3828 }
3829
3830 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3831 {
3832 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3833 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3834 do {
3835 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3836 } while (offset & PCI_VPD_ADDR_F);
3837 }
3838
3839 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3840 u8 *data)
3841 {
3842 struct sky2_port *sky2 = netdev_priv(dev);
3843 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3844 int length = eeprom->len;
3845 u16 offset = eeprom->offset;
3846
3847 if (!cap)
3848 return -EINVAL;
3849
3850 eeprom->magic = SKY2_EEPROM_MAGIC;
3851
3852 while (length > 0) {
3853 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3854 int n = min_t(int, length, sizeof(val));
3855
3856 memcpy(data, &val, n);
3857 length -= n;
3858 data += n;
3859 offset += n;
3860 }
3861 return 0;
3862 }
3863
3864 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3865 u8 *data)
3866 {
3867 struct sky2_port *sky2 = netdev_priv(dev);
3868 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3869 int length = eeprom->len;
3870 u16 offset = eeprom->offset;
3871
3872 if (!cap)
3873 return -EINVAL;
3874
3875 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3876 return -EINVAL;
3877
3878 while (length > 0) {
3879 u32 val;
3880 int n = min_t(int, length, sizeof(val));
3881
3882 if (n < sizeof(val))
3883 val = sky2_vpd_read(sky2->hw, cap, offset);
3884 memcpy(&val, data, n);
3885
3886 sky2_vpd_write(sky2->hw, cap, offset, val);
3887
3888 length -= n;
3889 data += n;
3890 offset += n;
3891 }
3892 return 0;
3893 }
3894
3895
3896 static const struct ethtool_ops sky2_ethtool_ops = {
3897 .get_settings = sky2_get_settings,
3898 .set_settings = sky2_set_settings,
3899 .get_drvinfo = sky2_get_drvinfo,
3900 .get_wol = sky2_get_wol,
3901 .set_wol = sky2_set_wol,
3902 .get_msglevel = sky2_get_msglevel,
3903 .set_msglevel = sky2_set_msglevel,
3904 .nway_reset = sky2_nway_reset,
3905 .get_regs_len = sky2_get_regs_len,
3906 .get_regs = sky2_get_regs,
3907 .get_link = ethtool_op_get_link,
3908 .get_eeprom_len = sky2_get_eeprom_len,
3909 .get_eeprom = sky2_get_eeprom,
3910 .set_eeprom = sky2_set_eeprom,
3911 .set_sg = ethtool_op_set_sg,
3912 .set_tx_csum = sky2_set_tx_csum,
3913 .set_tso = sky2_set_tso,
3914 .get_rx_csum = sky2_get_rx_csum,
3915 .set_rx_csum = sky2_set_rx_csum,
3916 .get_strings = sky2_get_strings,
3917 .get_coalesce = sky2_get_coalesce,
3918 .set_coalesce = sky2_set_coalesce,
3919 .get_ringparam = sky2_get_ringparam,
3920 .set_ringparam = sky2_set_ringparam,
3921 .get_pauseparam = sky2_get_pauseparam,
3922 .set_pauseparam = sky2_set_pauseparam,
3923 .phys_id = sky2_phys_id,
3924 .get_sset_count = sky2_get_sset_count,
3925 .get_ethtool_stats = sky2_get_ethtool_stats,
3926 };
3927
3928 #ifdef CONFIG_SKY2_DEBUG
3929
3930 static struct dentry *sky2_debug;
3931
3932 static int sky2_debug_show(struct seq_file *seq, void *v)
3933 {
3934 struct net_device *dev = seq->private;
3935 const struct sky2_port *sky2 = netdev_priv(dev);
3936 struct sky2_hw *hw = sky2->hw;
3937 unsigned port = sky2->port;
3938 unsigned idx, last;
3939 int sop;
3940
3941 if (!netif_running(dev))
3942 return -ENETDOWN;
3943
3944 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3945 sky2_read32(hw, B0_ISRC),
3946 sky2_read32(hw, B0_IMSK),
3947 sky2_read32(hw, B0_Y2_SP_ICR));
3948
3949 napi_disable(&hw->napi);
3950 last = sky2_read16(hw, STAT_PUT_IDX);
3951
3952 if (hw->st_idx == last)
3953 seq_puts(seq, "Status ring (empty)\n");
3954 else {
3955 seq_puts(seq, "Status ring\n");
3956 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3957 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3958 const struct sky2_status_le *le = hw->st_le + idx;
3959 seq_printf(seq, "[%d] %#x %d %#x\n",
3960 idx, le->opcode, le->length, le->status);
3961 }
3962 seq_puts(seq, "\n");
3963 }
3964
3965 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3966 sky2->tx_cons, sky2->tx_prod,
3967 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3968 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3969
3970 /* Dump contents of tx ring */
3971 sop = 1;
3972 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3973 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3974 const struct sky2_tx_le *le = sky2->tx_le + idx;
3975 u32 a = le32_to_cpu(le->addr);
3976
3977 if (sop)
3978 seq_printf(seq, "%u:", idx);
3979 sop = 0;
3980
3981 switch(le->opcode & ~HW_OWNER) {
3982 case OP_ADDR64:
3983 seq_printf(seq, " %#x:", a);
3984 break;
3985 case OP_LRGLEN:
3986 seq_printf(seq, " mtu=%d", a);
3987 break;
3988 case OP_VLAN:
3989 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3990 break;
3991 case OP_TCPLISW:
3992 seq_printf(seq, " csum=%#x", a);
3993 break;
3994 case OP_LARGESEND:
3995 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3996 break;
3997 case OP_PACKET:
3998 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3999 break;
4000 case OP_BUFFER:
4001 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4002 break;
4003 default:
4004 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4005 a, le16_to_cpu(le->length));
4006 }
4007
4008 if (le->ctrl & EOP) {
4009 seq_putc(seq, '\n');
4010 sop = 1;
4011 }
4012 }
4013
4014 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4015 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4016 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4017 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4018
4019 sky2_read32(hw, B0_Y2_SP_LISR);
4020 napi_enable(&hw->napi);
4021 return 0;
4022 }
4023
4024 static int sky2_debug_open(struct inode *inode, struct file *file)
4025 {
4026 return single_open(file, sky2_debug_show, inode->i_private);
4027 }
4028
4029 static const struct file_operations sky2_debug_fops = {
4030 .owner = THIS_MODULE,
4031 .open = sky2_debug_open,
4032 .read = seq_read,
4033 .llseek = seq_lseek,
4034 .release = single_release,
4035 };
4036
4037 /*
4038 * Use network device events to create/remove/rename
4039 * debugfs file entries
4040 */
4041 static int sky2_device_event(struct notifier_block *unused,
4042 unsigned long event, void *ptr)
4043 {
4044 struct net_device *dev = ptr;
4045 struct sky2_port *sky2 = netdev_priv(dev);
4046
4047 if (dev->open != sky2_up || !sky2_debug)
4048 return NOTIFY_DONE;
4049
4050 switch(event) {
4051 case NETDEV_CHANGENAME:
4052 if (sky2->debugfs) {
4053 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4054 sky2_debug, dev->name);
4055 }
4056 break;
4057
4058 case NETDEV_GOING_DOWN:
4059 if (sky2->debugfs) {
4060 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4061 dev->name);
4062 debugfs_remove(sky2->debugfs);
4063 sky2->debugfs = NULL;
4064 }
4065 break;
4066
4067 case NETDEV_UP:
4068 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4069 sky2_debug, dev,
4070 &sky2_debug_fops);
4071 if (IS_ERR(sky2->debugfs))
4072 sky2->debugfs = NULL;
4073 }
4074
4075 return NOTIFY_DONE;
4076 }
4077
4078 static struct notifier_block sky2_notifier = {
4079 .notifier_call = sky2_device_event,
4080 };
4081
4082
4083 static __init void sky2_debug_init(void)
4084 {
4085 struct dentry *ent;
4086
4087 ent = debugfs_create_dir("sky2", NULL);
4088 if (!ent || IS_ERR(ent))
4089 return;
4090
4091 sky2_debug = ent;
4092 register_netdevice_notifier(&sky2_notifier);
4093 }
4094
4095 static __exit void sky2_debug_cleanup(void)
4096 {
4097 if (sky2_debug) {
4098 unregister_netdevice_notifier(&sky2_notifier);
4099 debugfs_remove(sky2_debug);
4100 sky2_debug = NULL;
4101 }
4102 }
4103
4104 #else
4105 #define sky2_debug_init()
4106 #define sky2_debug_cleanup()
4107 #endif
4108
4109
4110 /* Initialize network device */
4111 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4112 unsigned port,
4113 int highmem, int wol)
4114 {
4115 struct sky2_port *sky2;
4116 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4117
4118 if (!dev) {
4119 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4120 return NULL;
4121 }
4122
4123 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4124 dev->irq = hw->pdev->irq;
4125 dev->open = sky2_up;
4126 dev->stop = sky2_down;
4127 dev->do_ioctl = sky2_ioctl;
4128 dev->hard_start_xmit = sky2_xmit_frame;
4129 dev->set_multicast_list = sky2_set_multicast;
4130 dev->set_mac_address = sky2_set_mac_address;
4131 dev->change_mtu = sky2_change_mtu;
4132 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4133 dev->tx_timeout = sky2_tx_timeout;
4134 dev->watchdog_timeo = TX_WATCHDOG;
4135 #ifdef CONFIG_NET_POLL_CONTROLLER
4136 if (port == 0)
4137 dev->poll_controller = sky2_netpoll;
4138 #endif
4139
4140 sky2 = netdev_priv(dev);
4141 sky2->netdev = dev;
4142 sky2->hw = hw;
4143 sky2->msg_enable = netif_msg_init(debug, default_msg);
4144
4145 /* Auto speed and flow control */
4146 sky2->autoneg = AUTONEG_ENABLE;
4147 sky2->flow_mode = FC_BOTH;
4148
4149 sky2->duplex = -1;
4150 sky2->speed = -1;
4151 sky2->advertising = sky2_supported_modes(hw);
4152 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4153 sky2->wol = wol;
4154
4155 spin_lock_init(&sky2->phy_lock);
4156 sky2->tx_pending = TX_DEF_PENDING;
4157 sky2->rx_pending = RX_DEF_PENDING;
4158
4159 hw->dev[port] = dev;
4160
4161 sky2->port = port;
4162
4163 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4164 if (highmem)
4165 dev->features |= NETIF_F_HIGHDMA;
4166
4167 #ifdef SKY2_VLAN_TAG_USED
4168 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4169 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4170 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4171 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4172 dev->vlan_rx_register = sky2_vlan_rx_register;
4173 }
4174 #endif
4175
4176 /* read the mac address */
4177 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4178 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4179
4180 return dev;
4181 }
4182
4183 static void __devinit sky2_show_addr(struct net_device *dev)
4184 {
4185 const struct sky2_port *sky2 = netdev_priv(dev);
4186 DECLARE_MAC_BUF(mac);
4187
4188 if (netif_msg_probe(sky2))
4189 printk(KERN_INFO PFX "%s: addr %s\n",
4190 dev->name, print_mac(mac, dev->dev_addr));
4191 }
4192
4193 /* Handle software interrupt used during MSI test */
4194 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4195 {
4196 struct sky2_hw *hw = dev_id;
4197 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4198
4199 if (status == 0)
4200 return IRQ_NONE;
4201
4202 if (status & Y2_IS_IRQ_SW) {
4203 hw->flags |= SKY2_HW_USE_MSI;
4204 wake_up(&hw->msi_wait);
4205 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4206 }
4207 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4208
4209 return IRQ_HANDLED;
4210 }
4211
4212 /* Test interrupt path by forcing a a software IRQ */
4213 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4214 {
4215 struct pci_dev *pdev = hw->pdev;
4216 int err;
4217
4218 init_waitqueue_head (&hw->msi_wait);
4219
4220 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4221
4222 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4223 if (err) {
4224 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4225 return err;
4226 }
4227
4228 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4229 sky2_read8(hw, B0_CTST);
4230
4231 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4232
4233 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4234 /* MSI test failed, go back to INTx mode */
4235 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4236 "switching to INTx mode.\n");
4237
4238 err = -EOPNOTSUPP;
4239 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4240 }
4241
4242 sky2_write32(hw, B0_IMSK, 0);
4243 sky2_read32(hw, B0_IMSK);
4244
4245 free_irq(pdev->irq, hw);
4246
4247 return err;
4248 }
4249
4250 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4251 {
4252 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4253 u16 value;
4254
4255 if (!pm)
4256 return 0;
4257 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4258 return 0;
4259 return value & PCI_PM_CTRL_PME_ENABLE;
4260 }
4261
4262 /* This driver supports yukon2 chipset only */
4263 static const char *sky2_name(u8 chipid, char *buf, int sz)
4264 {
4265 const char *name[] = {
4266 "XL", /* 0xb3 */
4267 "EC Ultra", /* 0xb4 */
4268 "Extreme", /* 0xb5 */
4269 "EC", /* 0xb6 */
4270 "FE", /* 0xb7 */
4271 "FE+", /* 0xb8 */
4272 "Supreme", /* 0xb9 */
4273 "UL 2", /* 0xba */
4274 };
4275
4276 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4277 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4278 else
4279 snprintf(buf, sz, "(chip %#x)", chipid);
4280 return buf;
4281 }
4282
4283 static int __devinit sky2_probe(struct pci_dev *pdev,
4284 const struct pci_device_id *ent)
4285 {
4286 struct net_device *dev;
4287 struct sky2_hw *hw;
4288 int err, using_dac = 0, wol_default;
4289 char buf1[16];
4290
4291 err = pci_enable_device(pdev);
4292 if (err) {
4293 dev_err(&pdev->dev, "cannot enable PCI device\n");
4294 goto err_out;
4295 }
4296
4297 err = pci_request_regions(pdev, DRV_NAME);
4298 if (err) {
4299 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4300 goto err_out_disable;
4301 }
4302
4303 pci_set_master(pdev);
4304
4305 if (sizeof(dma_addr_t) > sizeof(u32) &&
4306 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4307 using_dac = 1;
4308 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4309 if (err < 0) {
4310 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4311 "for consistent allocations\n");
4312 goto err_out_free_regions;
4313 }
4314 } else {
4315 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4316 if (err) {
4317 dev_err(&pdev->dev, "no usable DMA configuration\n");
4318 goto err_out_free_regions;
4319 }
4320 }
4321
4322 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4323
4324 err = -ENOMEM;
4325 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4326 if (!hw) {
4327 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4328 goto err_out_free_regions;
4329 }
4330
4331 hw->pdev = pdev;
4332
4333 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4334 if (!hw->regs) {
4335 dev_err(&pdev->dev, "cannot map device registers\n");
4336 goto err_out_free_hw;
4337 }
4338
4339 #ifdef __BIG_ENDIAN
4340 /* The sk98lin vendor driver uses hardware byte swapping but
4341 * this driver uses software swapping.
4342 */
4343 {
4344 u32 reg;
4345 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4346 reg &= ~PCI_REV_DESC;
4347 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4348 }
4349 #endif
4350
4351 /* ring for status responses */
4352 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4353 if (!hw->st_le)
4354 goto err_out_iounmap;
4355
4356 err = sky2_init(hw);
4357 if (err)
4358 goto err_out_iounmap;
4359
4360 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4361 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4362 pdev->irq, sky2_name(hw->chip_id, buf1, sizeof(buf1)),
4363 hw->chip_rev);
4364
4365 sky2_reset(hw);
4366
4367 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4368 if (!dev) {
4369 err = -ENOMEM;
4370 goto err_out_free_pci;
4371 }
4372
4373 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4374 err = sky2_test_msi(hw);
4375 if (err == -EOPNOTSUPP)
4376 pci_disable_msi(pdev);
4377 else if (err)
4378 goto err_out_free_netdev;
4379 }
4380
4381 err = register_netdev(dev);
4382 if (err) {
4383 dev_err(&pdev->dev, "cannot register net device\n");
4384 goto err_out_free_netdev;
4385 }
4386
4387 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4388
4389 err = request_irq(pdev->irq, sky2_intr,
4390 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4391 dev->name, hw);
4392 if (err) {
4393 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4394 goto err_out_unregister;
4395 }
4396 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4397 napi_enable(&hw->napi);
4398
4399 sky2_show_addr(dev);
4400
4401 if (hw->ports > 1) {
4402 struct net_device *dev1;
4403
4404 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4405 if (!dev1)
4406 dev_warn(&pdev->dev, "allocation for second device failed\n");
4407 else if ((err = register_netdev(dev1))) {
4408 dev_warn(&pdev->dev,
4409 "register of second port failed (%d)\n", err);
4410 hw->dev[1] = NULL;
4411 free_netdev(dev1);
4412 } else
4413 sky2_show_addr(dev1);
4414 }
4415
4416 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4417 INIT_WORK(&hw->restart_work, sky2_restart);
4418
4419 pci_set_drvdata(pdev, hw);
4420
4421 return 0;
4422
4423 err_out_unregister:
4424 if (hw->flags & SKY2_HW_USE_MSI)
4425 pci_disable_msi(pdev);
4426 unregister_netdev(dev);
4427 err_out_free_netdev:
4428 free_netdev(dev);
4429 err_out_free_pci:
4430 sky2_write8(hw, B0_CTST, CS_RST_SET);
4431 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4432 err_out_iounmap:
4433 iounmap(hw->regs);
4434 err_out_free_hw:
4435 kfree(hw);
4436 err_out_free_regions:
4437 pci_release_regions(pdev);
4438 err_out_disable:
4439 pci_disable_device(pdev);
4440 err_out:
4441 pci_set_drvdata(pdev, NULL);
4442 return err;
4443 }
4444
4445 static void __devexit sky2_remove(struct pci_dev *pdev)
4446 {
4447 struct sky2_hw *hw = pci_get_drvdata(pdev);
4448 int i;
4449
4450 if (!hw)
4451 return;
4452
4453 del_timer_sync(&hw->watchdog_timer);
4454 cancel_work_sync(&hw->restart_work);
4455
4456 for (i = hw->ports-1; i >= 0; --i)
4457 unregister_netdev(hw->dev[i]);
4458
4459 sky2_write32(hw, B0_IMSK, 0);
4460
4461 sky2_power_aux(hw);
4462
4463 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4464 sky2_write8(hw, B0_CTST, CS_RST_SET);
4465 sky2_read8(hw, B0_CTST);
4466
4467 free_irq(pdev->irq, hw);
4468 if (hw->flags & SKY2_HW_USE_MSI)
4469 pci_disable_msi(pdev);
4470 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4471 pci_release_regions(pdev);
4472 pci_disable_device(pdev);
4473
4474 for (i = hw->ports-1; i >= 0; --i)
4475 free_netdev(hw->dev[i]);
4476
4477 iounmap(hw->regs);
4478 kfree(hw);
4479
4480 pci_set_drvdata(pdev, NULL);
4481 }
4482
4483 #ifdef CONFIG_PM
4484 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4485 {
4486 struct sky2_hw *hw = pci_get_drvdata(pdev);
4487 int i, wol = 0;
4488
4489 if (!hw)
4490 return 0;
4491
4492 del_timer_sync(&hw->watchdog_timer);
4493 cancel_work_sync(&hw->restart_work);
4494
4495 for (i = 0; i < hw->ports; i++) {
4496 struct net_device *dev = hw->dev[i];
4497 struct sky2_port *sky2 = netdev_priv(dev);
4498
4499 netif_device_detach(dev);
4500 if (netif_running(dev))
4501 sky2_down(dev);
4502
4503 if (sky2->wol)
4504 sky2_wol_init(sky2);
4505
4506 wol |= sky2->wol;
4507 }
4508
4509 sky2_write32(hw, B0_IMSK, 0);
4510 napi_disable(&hw->napi);
4511 sky2_power_aux(hw);
4512
4513 pci_save_state(pdev);
4514 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4515 sky2_power_state(hw, pci_choose_state(pdev, state));
4516
4517 return 0;
4518 }
4519
4520 static int sky2_resume(struct pci_dev *pdev)
4521 {
4522 struct sky2_hw *hw = pci_get_drvdata(pdev);
4523 int i, err;
4524
4525 if (!hw)
4526 return 0;
4527
4528 sky2_power_state(hw, PCI_D0);
4529
4530 err = pci_restore_state(pdev);
4531 if (err)
4532 goto out;
4533
4534 pci_enable_wake(pdev, PCI_D0, 0);
4535
4536 /* Re-enable all clocks */
4537 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4538 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4539 hw->chip_id == CHIP_ID_YUKON_FE_P)
4540 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4541
4542 sky2_reset(hw);
4543 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4544 napi_enable(&hw->napi);
4545
4546 for (i = 0; i < hw->ports; i++) {
4547 struct net_device *dev = hw->dev[i];
4548
4549 netif_device_attach(dev);
4550 if (netif_running(dev)) {
4551 err = sky2_up(dev);
4552 if (err) {
4553 printk(KERN_ERR PFX "%s: could not up: %d\n",
4554 dev->name, err);
4555 rtnl_lock();
4556 dev_close(dev);
4557 rtnl_unlock();
4558 goto out;
4559 }
4560 }
4561 }
4562
4563 return 0;
4564 out:
4565 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4566 pci_disable_device(pdev);
4567 return err;
4568 }
4569 #endif
4570
4571 static void sky2_shutdown(struct pci_dev *pdev)
4572 {
4573 struct sky2_hw *hw = pci_get_drvdata(pdev);
4574 int i, wol = 0;
4575
4576 if (!hw)
4577 return;
4578
4579 del_timer_sync(&hw->watchdog_timer);
4580
4581 for (i = 0; i < hw->ports; i++) {
4582 struct net_device *dev = hw->dev[i];
4583 struct sky2_port *sky2 = netdev_priv(dev);
4584
4585 if (sky2->wol) {
4586 wol = 1;
4587 sky2_wol_init(sky2);
4588 }
4589 }
4590
4591 if (wol)
4592 sky2_power_aux(hw);
4593
4594 pci_enable_wake(pdev, PCI_D3hot, wol);
4595 pci_enable_wake(pdev, PCI_D3cold, wol);
4596
4597 pci_disable_device(pdev);
4598 sky2_power_state(hw, PCI_D3hot);
4599 }
4600
4601 static struct pci_driver sky2_driver = {
4602 .name = DRV_NAME,
4603 .id_table = sky2_id_table,
4604 .probe = sky2_probe,
4605 .remove = __devexit_p(sky2_remove),
4606 #ifdef CONFIG_PM
4607 .suspend = sky2_suspend,
4608 .resume = sky2_resume,
4609 #endif
4610 .shutdown = sky2_shutdown,
4611 };
4612
4613 static int __init sky2_init_module(void)
4614 {
4615 sky2_debug_init();
4616 return pci_register_driver(&sky2_driver);
4617 }
4618
4619 static void __exit sky2_cleanup_module(void)
4620 {
4621 pci_unregister_driver(&sky2_driver);
4622 sky2_debug_cleanup();
4623 }
4624
4625 module_init(sky2_init_module);
4626 module_exit(sky2_cleanup_module);
4627
4628 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4629 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4630 MODULE_LICENSE("GPL");
4631 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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