2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.22"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg
=
85 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
86 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
89 static int debug
= -1; /* defaults above */
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly
= 128;
94 module_param(copybreak
, int, 0);
95 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
97 static int disable_msi
= 0;
98 module_param(disable_msi
, int, 0);
99 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
101 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table
) = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4355) }, /* 88E8040T */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436D) }, /* 88E8055 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4370) }, /* 88E8075 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4380) }, /* 88E8057 */
144 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
146 /* Avoid conditionals by using array */
147 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
148 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
149 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
151 static void sky2_set_multicast(struct net_device
*dev
);
153 /* Access to PHY via serial interconnect */
154 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
158 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
159 gma_write16(hw
, port
, GM_SMI_CTRL
,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
162 for (i
= 0; i
< PHY_RETRIES
; i
++) {
163 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
167 if (!(ctrl
& GM_SMI_CT_BUSY
))
173 dev_warn(&hw
->pdev
->dev
,"%s: phy write timeout\n", hw
->dev
[port
]->name
);
177 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
181 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
185 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
186 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
188 for (i
= 0; i
< PHY_RETRIES
; i
++) {
189 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
193 if (ctrl
& GM_SMI_CT_RD_VAL
) {
194 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
201 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
204 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
208 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
211 __gm_phy_read(hw
, port
, reg
, &v
);
216 static void sky2_power_on(struct sky2_hw
*hw
)
218 /* switch power to VCC (WA for VAUX problem) */
219 sky2_write8(hw
, B0_POWER_CTRL
,
220 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
222 /* disable Core Clock Division, */
223 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
225 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
226 /* enable bits are inverted */
227 sky2_write8(hw
, B2_Y2_CLK_GATE
,
228 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
229 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
230 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
232 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
234 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
237 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
239 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
240 /* set all bits to 0 except bits 15..12 and 8 */
241 reg
&= P_ASPM_CONTROL_MSK
;
242 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
244 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
245 /* set all bits to 0 except bits 28 & 27 */
246 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
247 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
249 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
251 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
252 reg
= sky2_read32(hw
, B2_GP_IO
);
253 reg
|= GLB_GPIO_STAT_RACE_DIS
;
254 sky2_write32(hw
, B2_GP_IO
, reg
);
256 sky2_read32(hw
, B2_GP_IO
);
260 static void sky2_power_aux(struct sky2_hw
*hw
)
262 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
263 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
265 /* enable bits are inverted */
266 sky2_write8(hw
, B2_Y2_CLK_GATE
,
267 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
268 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
269 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
271 /* switch power to VAUX */
272 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
273 sky2_write8(hw
, B0_POWER_CTRL
,
274 (PC_VAUX_ENA
| PC_VCC_ENA
|
275 PC_VAUX_ON
| PC_VCC_OFF
));
278 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
282 /* disable all GMAC IRQ's */
283 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
285 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
286 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
287 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
288 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
290 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
291 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
292 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
295 /* flow control to advertise bits */
296 static const u16 copper_fc_adv
[] = {
298 [FC_TX
] = PHY_M_AN_ASP
,
299 [FC_RX
] = PHY_M_AN_PC
,
300 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
303 /* flow control to advertise bits when using 1000BaseX */
304 static const u16 fiber_fc_adv
[] = {
305 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
306 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
307 [FC_RX
] = PHY_M_P_SYM_MD_X
,
308 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
311 /* flow control to GMA disable bits */
312 static const u16 gm_fc_disable
[] = {
313 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
314 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
315 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
320 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
322 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
323 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
325 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
326 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
327 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
329 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
331 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
333 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
334 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
335 /* set downshift counter to 3x and enable downshift */
336 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
338 /* set master & slave downshift counter to 1x */
339 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
341 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
344 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
345 if (sky2_is_copper(hw
)) {
346 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
347 /* enable automatic crossover */
348 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
350 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
351 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
354 /* Enable Class A driver for FE+ A0 */
355 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
356 spec
|= PHY_M_FESC_SEL_CL_A
;
357 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
360 /* disable energy detect */
361 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
363 /* enable automatic crossover */
364 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
366 /* downshift on PHY 88E1112 and 88E1149 is changed */
367 if (sky2
->autoneg
== AUTONEG_ENABLE
368 && (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
369 /* set downshift counter to 3x and enable downshift */
370 ctrl
&= ~PHY_M_PC_DSC_MSK
;
371 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
375 /* workaround for deviation #4.88 (CRC errors) */
376 /* disable Automatic Crossover */
378 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
381 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
383 /* special setup for PHY 88E1112 Fiber */
384 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
385 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
387 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
388 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
389 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
390 ctrl
&= ~PHY_M_MAC_MD_MSK
;
391 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
392 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
394 if (hw
->pmd_type
== 'P') {
395 /* select page 1 to access Fiber registers */
396 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
398 /* for SFP-module set SIGDET polarity to low */
399 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
400 ctrl
|= PHY_M_FIB_SIGD_POL
;
401 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
404 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
412 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
413 if (sky2_is_copper(hw
)) {
414 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
415 ct1000
|= PHY_M_1000C_AFD
;
416 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
417 ct1000
|= PHY_M_1000C_AHD
;
418 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
419 adv
|= PHY_M_AN_100_FD
;
420 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
421 adv
|= PHY_M_AN_100_HD
;
422 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
423 adv
|= PHY_M_AN_10_FD
;
424 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
425 adv
|= PHY_M_AN_10_HD
;
427 adv
|= copper_fc_adv
[sky2
->flow_mode
];
428 } else { /* special defines for FIBER (88E1040S only) */
429 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
430 adv
|= PHY_M_AN_1000X_AFD
;
431 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
432 adv
|= PHY_M_AN_1000X_AHD
;
434 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
437 /* Restart Auto-negotiation */
438 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
440 /* forced speed/duplex settings */
441 ct1000
= PHY_M_1000C_MSE
;
443 /* Disable auto update for duplex flow control and speed */
444 reg
|= GM_GPCR_AU_ALL_DIS
;
446 switch (sky2
->speed
) {
448 ctrl
|= PHY_CT_SP1000
;
449 reg
|= GM_GPCR_SPEED_1000
;
452 ctrl
|= PHY_CT_SP100
;
453 reg
|= GM_GPCR_SPEED_100
;
457 if (sky2
->duplex
== DUPLEX_FULL
) {
458 reg
|= GM_GPCR_DUP_FULL
;
459 ctrl
|= PHY_CT_DUP_MD
;
460 } else if (sky2
->speed
< SPEED_1000
)
461 sky2
->flow_mode
= FC_NONE
;
464 reg
|= gm_fc_disable
[sky2
->flow_mode
];
466 /* Forward pause packets to GMAC? */
467 if (sky2
->flow_mode
& FC_RX
)
468 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
470 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
473 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
475 if (hw
->flags
& SKY2_HW_GIGABIT
)
476 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
478 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
479 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
481 /* Setup Phy LED's */
482 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
485 switch (hw
->chip_id
) {
486 case CHIP_ID_YUKON_FE
:
487 /* on 88E3082 these bits are at 11..9 (shifted left) */
488 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
490 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
492 /* delete ACT LED control bits */
493 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
494 /* change ACT LED control to blink mode */
495 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
496 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
499 case CHIP_ID_YUKON_FE_P
:
500 /* Enable Link Partner Next Page */
501 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
502 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
504 /* disable Energy Detect and enable scrambler */
505 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
506 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
508 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
509 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
510 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
511 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
513 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
516 case CHIP_ID_YUKON_XL
:
517 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
519 /* select page 3 to access LED control register */
520 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
522 /* set LED Function Control register */
523 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
524 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
525 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
526 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
527 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
529 /* set Polarity Control register */
530 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
531 (PHY_M_POLC_LS1_P_MIX(4) |
532 PHY_M_POLC_IS0_P_MIX(4) |
533 PHY_M_POLC_LOS_CTRL(2) |
534 PHY_M_POLC_INIT_CTRL(2) |
535 PHY_M_POLC_STA1_CTRL(2) |
536 PHY_M_POLC_STA0_CTRL(2)));
538 /* restore page register */
539 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
542 case CHIP_ID_YUKON_EC_U
:
543 case CHIP_ID_YUKON_EX
:
544 case CHIP_ID_YUKON_SUPR
:
545 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
547 /* select page 3 to access LED control register */
548 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
550 /* set LED Function Control register */
551 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
552 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
553 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
554 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
555 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
557 /* set Blink Rate in LED Timer Control Register */
558 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
559 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
560 /* restore page register */
561 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
565 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
566 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
568 /* turn off the Rx LED (LED_RX) */
569 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
572 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_UL_2
) {
573 /* apply fixes in PHY AFE */
574 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
576 /* increase differential signal amplitude in 10BASE-T */
577 gm_phy_write(hw
, port
, 0x18, 0xaa99);
578 gm_phy_write(hw
, port
, 0x17, 0x2011);
580 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
581 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
582 gm_phy_write(hw
, port
, 0x18, 0xa204);
583 gm_phy_write(hw
, port
, 0x17, 0x2002);
586 /* set page register to 0 */
587 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
588 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
589 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
590 /* apply workaround for integrated resistors calibration */
591 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
592 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
593 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
&&
594 hw
->chip_id
< CHIP_ID_YUKON_SUPR
) {
595 /* no effect on Yukon-XL */
596 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
598 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
599 /* turn on 100 Mbps LED (LED_LINK100) */
600 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
604 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
608 /* Enable phy interrupt on auto-negotiation complete (or link up) */
609 if (sky2
->autoneg
== AUTONEG_ENABLE
)
610 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
612 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
615 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
616 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
618 static void sky2_phy_power_up(struct sky2_hw
*hw
, unsigned port
)
622 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
623 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
624 reg1
&= ~phy_power
[port
];
626 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
627 reg1
|= coma_mode
[port
];
629 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
630 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
631 sky2_pci_read32(hw
, PCI_DEV_REG1
);
633 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
634 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_ANE
);
635 else if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
)
636 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
639 static void sky2_phy_power_down(struct sky2_hw
*hw
, unsigned port
)
644 /* release GPHY Control reset */
645 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
647 /* release GMAC reset */
648 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
650 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
651 /* select page 2 to access MAC control register */
652 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
654 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
655 /* allow GMII Power Down */
656 ctrl
&= ~PHY_M_MAC_GMIF_PUP
;
657 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
659 /* set page register back to 0 */
660 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
663 /* setup General Purpose Control Register */
664 gma_write16(hw
, port
, GM_GP_CTRL
,
665 GM_GPCR_FL_PASS
| GM_GPCR_SPEED_100
| GM_GPCR_AU_ALL_DIS
);
667 if (hw
->chip_id
!= CHIP_ID_YUKON_EC
) {
668 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
669 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
671 /* enable Power Down */
672 ctrl
|= PHY_M_PC_POW_D_ENA
;
673 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
676 /* set IEEE compatible Power Down Mode (dev. #4.99) */
677 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_PDOWN
);
680 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
681 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
682 reg1
|= phy_power
[port
]; /* set PHY to PowerDown/COMA Mode */
683 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
684 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
687 /* Force a renegotiation */
688 static void sky2_phy_reinit(struct sky2_port
*sky2
)
690 spin_lock_bh(&sky2
->phy_lock
);
691 sky2_phy_init(sky2
->hw
, sky2
->port
);
692 spin_unlock_bh(&sky2
->phy_lock
);
695 /* Put device in state to listen for Wake On Lan */
696 static void sky2_wol_init(struct sky2_port
*sky2
)
698 struct sky2_hw
*hw
= sky2
->hw
;
699 unsigned port
= sky2
->port
;
700 enum flow_control save_mode
;
704 /* Bring hardware out of reset */
705 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
706 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
708 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
709 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
712 * sky2_reset will re-enable on resume
714 save_mode
= sky2
->flow_mode
;
715 ctrl
= sky2
->advertising
;
717 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
718 sky2
->flow_mode
= FC_NONE
;
720 spin_lock_bh(&sky2
->phy_lock
);
721 sky2_phy_power_up(hw
, port
);
722 sky2_phy_init(hw
, port
);
723 spin_unlock_bh(&sky2
->phy_lock
);
725 sky2
->flow_mode
= save_mode
;
726 sky2
->advertising
= ctrl
;
728 /* Set GMAC to no flow control and auto update for speed/duplex */
729 gma_write16(hw
, port
, GM_GP_CTRL
,
730 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
731 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
733 /* Set WOL address */
734 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
735 sky2
->netdev
->dev_addr
, ETH_ALEN
);
737 /* Turn on appropriate WOL control bits */
738 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
740 if (sky2
->wol
& WAKE_PHY
)
741 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
743 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
745 if (sky2
->wol
& WAKE_MAGIC
)
746 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
748 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
750 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
751 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
753 /* Turn on legacy PCI-Express PME mode */
754 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
755 reg1
|= PCI_Y2_PME_LEGACY
;
756 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
759 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
763 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
765 struct net_device
*dev
= hw
->dev
[port
];
767 if ( (hw
->chip_id
== CHIP_ID_YUKON_EX
&&
768 hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) ||
769 hw
->chip_id
== CHIP_ID_YUKON_FE_P
||
770 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
771 /* Yukon-Extreme B0 and further Extreme devices */
772 /* enable Store & Forward mode for TX */
774 if (dev
->mtu
<= ETH_DATA_LEN
)
775 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
776 TX_JUMBO_DIS
| TX_STFW_ENA
);
779 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
780 TX_JUMBO_ENA
| TX_STFW_ENA
);
782 if (dev
->mtu
<= ETH_DATA_LEN
)
783 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
785 /* set Tx GMAC FIFO Almost Empty Threshold */
786 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
787 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
789 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
791 /* Can't do offload because of lack of store/forward */
792 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_ALL_CSUM
);
797 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
799 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
803 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
805 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
806 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
808 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
810 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
811 /* WA DEV_472 -- looks like crossed wires on port 2 */
812 /* clear GMAC 1 Control reset */
813 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
815 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
816 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
817 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
818 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
819 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
822 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
824 /* Enable Transmit FIFO Underrun */
825 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
827 spin_lock_bh(&sky2
->phy_lock
);
828 sky2_phy_power_up(hw
, port
);
829 sky2_phy_init(hw
, port
);
830 spin_unlock_bh(&sky2
->phy_lock
);
833 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
834 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
836 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
837 gma_read16(hw
, port
, i
);
838 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
840 /* transmit control */
841 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
843 /* receive control reg: unicast + multicast + no FCS */
844 gma_write16(hw
, port
, GM_RX_CTRL
,
845 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
847 /* transmit flow control */
848 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
850 /* transmit parameter */
851 gma_write16(hw
, port
, GM_TX_PARAM
,
852 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
853 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
854 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
855 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
857 /* serial mode register */
858 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
859 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
861 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
862 reg
|= GM_SMOD_JUMBO_ENA
;
864 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
866 /* virtual address for data */
867 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
869 /* physical address: used for pause frames */
870 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
872 /* ignore counter overflows */
873 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
874 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
875 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
877 /* Configure Rx MAC FIFO */
878 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
879 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
880 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
881 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
882 rx_reg
|= GMF_RX_OVER_ON
;
884 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
886 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
887 /* Hardware errata - clear flush mask */
888 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
890 /* Flush Rx MAC FIFO on any flow control or error */
891 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
894 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
895 reg
= RX_GMF_FL_THR_DEF
+ 1;
896 /* Another magic mystery workaround from sk98lin */
897 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
898 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
900 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
902 /* Configure Tx MAC FIFO */
903 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
904 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
906 /* On chips without ram buffer, pause is controled by MAC level */
907 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
)) {
908 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
909 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
911 sky2_set_tx_stfwd(hw
, port
);
914 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
915 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
916 /* disable dynamic watermark */
917 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
918 reg
&= ~TX_DYN_WM_ENA
;
919 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
923 /* Assign Ram Buffer allocation to queue */
924 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
928 /* convert from K bytes to qwords used for hw register */
931 end
= start
+ space
- 1;
933 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
934 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
935 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
936 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
937 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
939 if (q
== Q_R1
|| q
== Q_R2
) {
940 u32 tp
= space
- space
/4;
942 /* On receive queue's set the thresholds
943 * give receiver priority when > 3/4 full
944 * send pause when down to 2K
946 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
947 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
950 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
951 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
953 /* Enable store & forward on Tx queue's because
954 * Tx FIFO is only 1K on Yukon
956 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
959 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
960 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
963 /* Setup Bus Memory Interface */
964 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
966 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
967 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
968 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
969 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
972 /* Setup prefetch unit registers. This is the interface between
973 * hardware and driver list elements
975 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
978 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
979 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
980 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
981 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
982 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
983 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
985 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
988 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
990 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
992 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
997 static void tx_init(struct sky2_port
*sky2
)
999 struct sky2_tx_le
*le
;
1001 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1002 sky2
->tx_tcpsum
= 0;
1003 sky2
->tx_last_mss
= 0;
1005 le
= get_tx_le(sky2
);
1007 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1010 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
1011 struct sky2_tx_le
*le
)
1013 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
1016 /* Update chip's next pointer */
1017 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
1019 /* Make sure write' to descriptors are complete before we tell hardware */
1021 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
1023 /* Synchronize I/O on since next processor may write to tail */
1028 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
1030 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
1031 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
1036 /* Build description to hardware for one receive segment */
1037 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
1038 dma_addr_t map
, unsigned len
)
1040 struct sky2_rx_le
*le
;
1042 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1043 le
= sky2_next_rx(sky2
);
1044 le
->addr
= cpu_to_le32(upper_32_bits(map
));
1045 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1048 le
= sky2_next_rx(sky2
);
1049 le
->addr
= cpu_to_le32((u32
) map
);
1050 le
->length
= cpu_to_le16(len
);
1051 le
->opcode
= op
| HW_OWNER
;
1054 /* Build description to hardware for one possibly fragmented skb */
1055 static void sky2_rx_submit(struct sky2_port
*sky2
,
1056 const struct rx_ring_info
*re
)
1060 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1062 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1063 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1067 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1070 struct sk_buff
*skb
= re
->skb
;
1073 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1074 pci_unmap_len_set(re
, data_size
, size
);
1076 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1077 re
->frag_addr
[i
] = pci_map_page(pdev
,
1078 skb_shinfo(skb
)->frags
[i
].page
,
1079 skb_shinfo(skb
)->frags
[i
].page_offset
,
1080 skb_shinfo(skb
)->frags
[i
].size
,
1081 PCI_DMA_FROMDEVICE
);
1084 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1086 struct sk_buff
*skb
= re
->skb
;
1089 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1090 PCI_DMA_FROMDEVICE
);
1092 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1093 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1094 skb_shinfo(skb
)->frags
[i
].size
,
1095 PCI_DMA_FROMDEVICE
);
1098 /* Tell chip where to start receive checksum.
1099 * Actually has two checksums, but set both same to avoid possible byte
1102 static void rx_set_checksum(struct sky2_port
*sky2
)
1104 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1106 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1108 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1110 sky2_write32(sky2
->hw
,
1111 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1112 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1116 * The RX Stop command will not work for Yukon-2 if the BMU does not
1117 * reach the end of packet and since we can't make sure that we have
1118 * incoming data, we must reset the BMU while it is not doing a DMA
1119 * transfer. Since it is possible that the RX path is still active,
1120 * the RX RAM buffer will be stopped first, so any possible incoming
1121 * data will not trigger a DMA. After the RAM buffer is stopped, the
1122 * BMU is polled until any DMA in progress is ended and only then it
1125 static void sky2_rx_stop(struct sky2_port
*sky2
)
1127 struct sky2_hw
*hw
= sky2
->hw
;
1128 unsigned rxq
= rxqaddr
[sky2
->port
];
1131 /* disable the RAM Buffer receive queue */
1132 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1134 for (i
= 0; i
< 0xffff; i
++)
1135 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1136 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1139 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1140 sky2
->netdev
->name
);
1142 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1144 /* reset the Rx prefetch unit */
1145 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1149 /* Clean out receive buffer area, assumes receiver hardware stopped */
1150 static void sky2_rx_clean(struct sky2_port
*sky2
)
1154 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1155 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1156 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1159 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1166 /* Basic MII support */
1167 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1169 struct mii_ioctl_data
*data
= if_mii(ifr
);
1170 struct sky2_port
*sky2
= netdev_priv(dev
);
1171 struct sky2_hw
*hw
= sky2
->hw
;
1172 int err
= -EOPNOTSUPP
;
1174 if (!netif_running(dev
))
1175 return -ENODEV
; /* Phy still in reset */
1179 data
->phy_id
= PHY_ADDR_MARV
;
1185 spin_lock_bh(&sky2
->phy_lock
);
1186 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1187 spin_unlock_bh(&sky2
->phy_lock
);
1189 data
->val_out
= val
;
1194 if (!capable(CAP_NET_ADMIN
))
1197 spin_lock_bh(&sky2
->phy_lock
);
1198 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1200 spin_unlock_bh(&sky2
->phy_lock
);
1206 #ifdef SKY2_VLAN_TAG_USED
1207 static void sky2_set_vlan_mode(struct sky2_hw
*hw
, u16 port
, bool onoff
)
1210 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1212 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1215 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1217 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1222 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1224 struct sky2_port
*sky2
= netdev_priv(dev
);
1225 struct sky2_hw
*hw
= sky2
->hw
;
1226 u16 port
= sky2
->port
;
1228 netif_tx_lock_bh(dev
);
1229 napi_disable(&hw
->napi
);
1232 sky2_set_vlan_mode(hw
, port
, grp
!= NULL
);
1234 sky2_read32(hw
, B0_Y2_SP_LISR
);
1235 napi_enable(&hw
->napi
);
1236 netif_tx_unlock_bh(dev
);
1241 * Allocate an skb for receiving. If the MTU is large enough
1242 * make the skb non-linear with a fragment list of pages.
1244 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1246 struct sk_buff
*skb
;
1249 if (sky2
->hw
->flags
& SKY2_HW_RAM_BUFFER
) {
1250 unsigned char *start
;
1252 * Workaround for a bug in FIFO that cause hang
1253 * if the FIFO if the receive buffer is not 64 byte aligned.
1254 * The buffer returned from netdev_alloc_skb is
1255 * aligned except if slab debugging is enabled.
1257 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ 8);
1260 start
= PTR_ALIGN(skb
->data
, 8);
1261 skb_reserve(skb
, start
- skb
->data
);
1263 skb
= netdev_alloc_skb(sky2
->netdev
,
1264 sky2
->rx_data_size
+ NET_IP_ALIGN
);
1267 skb_reserve(skb
, NET_IP_ALIGN
);
1270 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1271 struct page
*page
= alloc_page(GFP_ATOMIC
);
1275 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1285 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1287 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1291 * Allocate and setup receiver buffer pool.
1292 * Normal case this ends up creating one list element for skb
1293 * in the receive ring. Worst case if using large MTU and each
1294 * allocation falls on a different 64 bit region, that results
1295 * in 6 list elements per ring entry.
1296 * One element is used for checksum enable/disable, and one
1297 * extra to avoid wrap.
1299 static int sky2_rx_start(struct sky2_port
*sky2
)
1301 struct sky2_hw
*hw
= sky2
->hw
;
1302 struct rx_ring_info
*re
;
1303 unsigned rxq
= rxqaddr
[sky2
->port
];
1304 unsigned i
, size
, thresh
;
1306 sky2
->rx_put
= sky2
->rx_next
= 0;
1309 /* On PCI express lowering the watermark gives better performance */
1310 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1311 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1313 /* These chips have no ram buffer?
1314 * MAC Rx RAM Read is controlled by hardware */
1315 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1316 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1317 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1318 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1320 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1322 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1323 rx_set_checksum(sky2
);
1325 /* Space needed for frame data + headers rounded up */
1326 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1328 /* Stopping point for hardware truncation */
1329 thresh
= (size
- 8) / sizeof(u32
);
1331 sky2
->rx_nfrags
= size
>> PAGE_SHIFT
;
1332 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1334 /* Compute residue after pages */
1335 size
-= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1337 /* Optimize to handle small packets and headers */
1338 if (size
< copybreak
)
1340 if (size
< ETH_HLEN
)
1343 sky2
->rx_data_size
= size
;
1346 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1347 re
= sky2
->rx_ring
+ i
;
1349 re
->skb
= sky2_rx_alloc(sky2
);
1353 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1354 sky2_rx_submit(sky2
, re
);
1358 * The receiver hangs if it receives frames larger than the
1359 * packet buffer. As a workaround, truncate oversize frames, but
1360 * the register is limited to 9 bits, so if you do frames > 2052
1361 * you better get the MTU right!
1364 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1366 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1367 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1370 /* Tell chip about available buffers */
1371 sky2_rx_update(sky2
, rxq
);
1374 sky2_rx_clean(sky2
);
1378 /* Bring up network interface. */
1379 static int sky2_up(struct net_device
*dev
)
1381 struct sky2_port
*sky2
= netdev_priv(dev
);
1382 struct sky2_hw
*hw
= sky2
->hw
;
1383 unsigned port
= sky2
->port
;
1385 int cap
, err
= -ENOMEM
;
1386 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1389 * On dual port PCI-X card, there is an problem where status
1390 * can be received out of order due to split transactions
1392 if (otherdev
&& netif_running(otherdev
) &&
1393 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1396 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1397 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1398 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1402 if (netif_msg_ifup(sky2
))
1403 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1405 netif_carrier_off(dev
);
1407 /* must be power of 2 */
1408 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1410 sizeof(struct sky2_tx_le
),
1415 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1422 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1426 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1428 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1433 sky2_mac_init(hw
, port
);
1435 /* Register is number of 4K blocks on internal RAM buffer. */
1436 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1440 hw
->flags
|= SKY2_HW_RAM_BUFFER
;
1441 pr_debug(PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1443 rxspace
= ramsize
/ 2;
1445 rxspace
= 8 + (2*(ramsize
- 16))/3;
1447 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1448 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1450 /* Make sure SyncQ is disabled */
1451 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1455 sky2_qset(hw
, txqaddr
[port
]);
1457 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1458 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1459 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1461 /* Set almost empty threshold */
1462 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1463 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1464 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1466 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1469 #ifdef SKY2_VLAN_TAG_USED
1470 sky2_set_vlan_mode(hw
, port
, sky2
->vlgrp
!= NULL
);
1473 err
= sky2_rx_start(sky2
);
1477 /* Enable interrupts from phy/mac for port */
1478 imask
= sky2_read32(hw
, B0_IMSK
);
1479 imask
|= portirq_msk
[port
];
1480 sky2_write32(hw
, B0_IMSK
, imask
);
1482 sky2_set_multicast(dev
);
1487 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1488 sky2
->rx_le
, sky2
->rx_le_map
);
1492 pci_free_consistent(hw
->pdev
,
1493 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1494 sky2
->tx_le
, sky2
->tx_le_map
);
1497 kfree(sky2
->tx_ring
);
1498 kfree(sky2
->rx_ring
);
1500 sky2
->tx_ring
= NULL
;
1501 sky2
->rx_ring
= NULL
;
1505 /* Modular subtraction in ring */
1506 static inline int tx_dist(unsigned tail
, unsigned head
)
1508 return (head
- tail
) & (TX_RING_SIZE
- 1);
1511 /* Number of list elements available for next tx */
1512 static inline int tx_avail(const struct sky2_port
*sky2
)
1514 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1517 /* Estimate of number of transmit list elements required */
1518 static unsigned tx_le_req(const struct sk_buff
*skb
)
1522 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1523 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1525 if (skb_is_gso(skb
))
1528 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1535 * Put one packet in ring for transmit.
1536 * A single packet can generate multiple list elements, and
1537 * the number of ring elements will probably be less than the number
1538 * of list elements used.
1540 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1542 struct sky2_port
*sky2
= netdev_priv(dev
);
1543 struct sky2_hw
*hw
= sky2
->hw
;
1544 struct sky2_tx_le
*le
= NULL
;
1545 struct tx_ring_info
*re
;
1551 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1552 return NETDEV_TX_BUSY
;
1554 if (unlikely(netif_msg_tx_queued(sky2
)))
1555 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1556 dev
->name
, sky2
->tx_prod
, skb
->len
);
1558 len
= skb_headlen(skb
);
1559 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1561 /* Send high bits if needed */
1562 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1563 le
= get_tx_le(sky2
);
1564 le
->addr
= cpu_to_le32(upper_32_bits(mapping
));
1565 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1568 /* Check for TCP Segmentation Offload */
1569 mss
= skb_shinfo(skb
)->gso_size
;
1572 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1573 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1575 if (mss
!= sky2
->tx_last_mss
) {
1576 le
= get_tx_le(sky2
);
1577 le
->addr
= cpu_to_le32(mss
);
1579 if (hw
->flags
& SKY2_HW_NEW_LE
)
1580 le
->opcode
= OP_MSS
| HW_OWNER
;
1582 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1583 sky2
->tx_last_mss
= mss
;
1588 #ifdef SKY2_VLAN_TAG_USED
1589 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1590 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1592 le
= get_tx_le(sky2
);
1594 le
->opcode
= OP_VLAN
|HW_OWNER
;
1596 le
->opcode
|= OP_VLAN
;
1597 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1602 /* Handle TCP checksum offload */
1603 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1604 /* On Yukon EX (some versions) encoding change. */
1605 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1606 ctrl
|= CALSUM
; /* auto checksum */
1608 const unsigned offset
= skb_transport_offset(skb
);
1611 tcpsum
= offset
<< 16; /* sum start */
1612 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1614 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1615 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1618 if (tcpsum
!= sky2
->tx_tcpsum
) {
1619 sky2
->tx_tcpsum
= tcpsum
;
1621 le
= get_tx_le(sky2
);
1622 le
->addr
= cpu_to_le32(tcpsum
);
1623 le
->length
= 0; /* initial checksum value */
1624 le
->ctrl
= 1; /* one packet */
1625 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1630 le
= get_tx_le(sky2
);
1631 le
->addr
= cpu_to_le32((u32
) mapping
);
1632 le
->length
= cpu_to_le16(len
);
1634 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1636 re
= tx_le_re(sky2
, le
);
1638 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1639 pci_unmap_len_set(re
, maplen
, len
);
1641 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1642 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1644 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1645 frag
->size
, PCI_DMA_TODEVICE
);
1647 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1648 le
= get_tx_le(sky2
);
1649 le
->addr
= cpu_to_le32(upper_32_bits(mapping
));
1651 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1654 le
= get_tx_le(sky2
);
1655 le
->addr
= cpu_to_le32((u32
) mapping
);
1656 le
->length
= cpu_to_le16(frag
->size
);
1658 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1660 re
= tx_le_re(sky2
, le
);
1662 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1663 pci_unmap_len_set(re
, maplen
, frag
->size
);
1668 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1669 netif_stop_queue(dev
);
1671 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1673 dev
->trans_start
= jiffies
;
1674 return NETDEV_TX_OK
;
1678 * Free ring elements from starting at tx_cons until "done"
1680 * NB: the hardware will tell us about partial completion of multi-part
1681 * buffers so make sure not to free skb to early.
1683 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1685 struct net_device
*dev
= sky2
->netdev
;
1686 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1689 BUG_ON(done
>= TX_RING_SIZE
);
1691 for (idx
= sky2
->tx_cons
; idx
!= done
;
1692 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1693 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1694 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1696 switch(le
->opcode
& ~HW_OWNER
) {
1699 pci_unmap_single(pdev
,
1700 pci_unmap_addr(re
, mapaddr
),
1701 pci_unmap_len(re
, maplen
),
1705 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1706 pci_unmap_len(re
, maplen
),
1711 if (le
->ctrl
& EOP
) {
1712 if (unlikely(netif_msg_tx_done(sky2
)))
1713 printk(KERN_DEBUG
"%s: tx done %u\n",
1716 dev
->stats
.tx_packets
++;
1717 dev
->stats
.tx_bytes
+= re
->skb
->len
;
1719 dev_kfree_skb_any(re
->skb
);
1720 sky2
->tx_next
= RING_NEXT(idx
, TX_RING_SIZE
);
1724 sky2
->tx_cons
= idx
;
1727 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1728 netif_wake_queue(dev
);
1731 /* Cleanup all untransmitted buffers, assume transmitter not running */
1732 static void sky2_tx_clean(struct net_device
*dev
)
1734 struct sky2_port
*sky2
= netdev_priv(dev
);
1736 netif_tx_lock_bh(dev
);
1737 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1738 netif_tx_unlock_bh(dev
);
1741 /* Network shutdown */
1742 static int sky2_down(struct net_device
*dev
)
1744 struct sky2_port
*sky2
= netdev_priv(dev
);
1745 struct sky2_hw
*hw
= sky2
->hw
;
1746 unsigned port
= sky2
->port
;
1750 /* Never really got started! */
1754 if (netif_msg_ifdown(sky2
))
1755 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1757 /* Disable port IRQ */
1758 imask
= sky2_read32(hw
, B0_IMSK
);
1759 imask
&= ~portirq_msk
[port
];
1760 sky2_write32(hw
, B0_IMSK
, imask
);
1762 synchronize_irq(hw
->pdev
->irq
);
1764 sky2_gmac_reset(hw
, port
);
1766 /* Stop transmitter */
1767 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1768 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1770 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1771 RB_RST_SET
| RB_DIS_OP_MD
);
1773 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1774 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1775 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1777 /* Make sure no packets are pending */
1778 napi_synchronize(&hw
->napi
);
1780 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1782 /* Workaround shared GMAC reset */
1783 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1784 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1785 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1787 /* Disable Force Sync bit and Enable Alloc bit */
1788 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1789 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1791 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1792 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1793 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1795 /* Reset the PCI FIFO of the async Tx queue */
1796 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1797 BMU_RST_SET
| BMU_FIFO_RST
);
1799 /* Reset the Tx prefetch units */
1800 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1803 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1807 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1808 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1810 sky2_phy_power_down(hw
, port
);
1812 /* turn off LED's */
1813 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1816 sky2_rx_clean(sky2
);
1818 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1819 sky2
->rx_le
, sky2
->rx_le_map
);
1820 kfree(sky2
->rx_ring
);
1822 pci_free_consistent(hw
->pdev
,
1823 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1824 sky2
->tx_le
, sky2
->tx_le_map
);
1825 kfree(sky2
->tx_ring
);
1830 sky2
->rx_ring
= NULL
;
1831 sky2
->tx_ring
= NULL
;
1836 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1838 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
1841 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
1842 if (aux
& PHY_M_PS_SPEED_100
)
1848 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1849 case PHY_M_PS_SPEED_1000
:
1851 case PHY_M_PS_SPEED_100
:
1858 static void sky2_link_up(struct sky2_port
*sky2
)
1860 struct sky2_hw
*hw
= sky2
->hw
;
1861 unsigned port
= sky2
->port
;
1863 static const char *fc_name
[] = {
1871 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1872 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1873 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1875 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1877 netif_carrier_on(sky2
->netdev
);
1879 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
1881 /* Turn on link LED */
1882 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1883 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1885 if (netif_msg_link(sky2
))
1886 printk(KERN_INFO PFX
1887 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1888 sky2
->netdev
->name
, sky2
->speed
,
1889 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1890 fc_name
[sky2
->flow_status
]);
1893 static void sky2_link_down(struct sky2_port
*sky2
)
1895 struct sky2_hw
*hw
= sky2
->hw
;
1896 unsigned port
= sky2
->port
;
1899 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1901 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1902 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1903 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1905 netif_carrier_off(sky2
->netdev
);
1907 /* Turn on link LED */
1908 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1910 if (netif_msg_link(sky2
))
1911 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1913 sky2_phy_init(hw
, port
);
1916 static enum flow_control
sky2_flow(int rx
, int tx
)
1919 return tx
? FC_BOTH
: FC_RX
;
1921 return tx
? FC_TX
: FC_NONE
;
1924 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1926 struct sky2_hw
*hw
= sky2
->hw
;
1927 unsigned port
= sky2
->port
;
1930 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1931 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1932 if (lpa
& PHY_M_AN_RF
) {
1933 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1937 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1938 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1939 sky2
->netdev
->name
);
1943 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1944 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1946 /* Since the pause result bits seem to in different positions on
1947 * different chips. look at registers.
1949 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
1950 /* Shift for bits in fiber PHY */
1951 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1952 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1954 if (advert
& ADVERTISE_1000XPAUSE
)
1955 advert
|= ADVERTISE_PAUSE_CAP
;
1956 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1957 advert
|= ADVERTISE_PAUSE_ASYM
;
1958 if (lpa
& LPA_1000XPAUSE
)
1959 lpa
|= LPA_PAUSE_CAP
;
1960 if (lpa
& LPA_1000XPAUSE_ASYM
)
1961 lpa
|= LPA_PAUSE_ASYM
;
1964 sky2
->flow_status
= FC_NONE
;
1965 if (advert
& ADVERTISE_PAUSE_CAP
) {
1966 if (lpa
& LPA_PAUSE_CAP
)
1967 sky2
->flow_status
= FC_BOTH
;
1968 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1969 sky2
->flow_status
= FC_RX
;
1970 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1971 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1972 sky2
->flow_status
= FC_TX
;
1975 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1976 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1977 sky2
->flow_status
= FC_NONE
;
1979 if (sky2
->flow_status
& FC_TX
)
1980 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1982 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1987 /* Interrupt from PHY */
1988 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1990 struct net_device
*dev
= hw
->dev
[port
];
1991 struct sky2_port
*sky2
= netdev_priv(dev
);
1992 u16 istatus
, phystat
;
1994 if (!netif_running(dev
))
1997 spin_lock(&sky2
->phy_lock
);
1998 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1999 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2001 if (netif_msg_intr(sky2
))
2002 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2003 sky2
->netdev
->name
, istatus
, phystat
);
2005 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
2006 if (sky2_autoneg_done(sky2
, phystat
) == 0)
2011 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2012 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
2014 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2016 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2018 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2019 if (phystat
& PHY_M_PS_LINK_UP
)
2022 sky2_link_down(sky2
);
2025 spin_unlock(&sky2
->phy_lock
);
2028 /* Transmit timeout is only called if we are running, carrier is up
2029 * and tx queue is full (stopped).
2031 static void sky2_tx_timeout(struct net_device
*dev
)
2033 struct sky2_port
*sky2
= netdev_priv(dev
);
2034 struct sky2_hw
*hw
= sky2
->hw
;
2036 if (netif_msg_timer(sky2
))
2037 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
2039 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
2040 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
2041 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
2042 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
2044 /* can't restart safely under softirq */
2045 schedule_work(&hw
->restart_work
);
2048 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
2050 struct sky2_port
*sky2
= netdev_priv(dev
);
2051 struct sky2_hw
*hw
= sky2
->hw
;
2052 unsigned port
= sky2
->port
;
2057 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2060 if (new_mtu
> ETH_DATA_LEN
&&
2061 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2062 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2065 if (!netif_running(dev
)) {
2070 imask
= sky2_read32(hw
, B0_IMSK
);
2071 sky2_write32(hw
, B0_IMSK
, 0);
2073 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2074 netif_stop_queue(dev
);
2075 napi_disable(&hw
->napi
);
2077 synchronize_irq(hw
->pdev
->irq
);
2079 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
))
2080 sky2_set_tx_stfwd(hw
, port
);
2082 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2083 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2085 sky2_rx_clean(sky2
);
2089 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
2090 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2092 if (dev
->mtu
> ETH_DATA_LEN
)
2093 mode
|= GM_SMOD_JUMBO_ENA
;
2095 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2097 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2099 err
= sky2_rx_start(sky2
);
2100 sky2_write32(hw
, B0_IMSK
, imask
);
2102 sky2_read32(hw
, B0_Y2_SP_LISR
);
2103 napi_enable(&hw
->napi
);
2108 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2110 netif_wake_queue(dev
);
2116 /* For small just reuse existing skb for next receive */
2117 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2118 const struct rx_ring_info
*re
,
2121 struct sk_buff
*skb
;
2123 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
2125 skb_reserve(skb
, 2);
2126 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2127 length
, PCI_DMA_FROMDEVICE
);
2128 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2129 skb
->ip_summed
= re
->skb
->ip_summed
;
2130 skb
->csum
= re
->skb
->csum
;
2131 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2132 length
, PCI_DMA_FROMDEVICE
);
2133 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2134 skb_put(skb
, length
);
2139 /* Adjust length of skb with fragments to match received data */
2140 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2141 unsigned int length
)
2146 /* put header into skb */
2147 size
= min(length
, hdr_space
);
2152 num_frags
= skb_shinfo(skb
)->nr_frags
;
2153 for (i
= 0; i
< num_frags
; i
++) {
2154 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2157 /* don't need this page */
2158 __free_page(frag
->page
);
2159 --skb_shinfo(skb
)->nr_frags
;
2161 size
= min(length
, (unsigned) PAGE_SIZE
);
2164 skb
->data_len
+= size
;
2165 skb
->truesize
+= size
;
2172 /* Normal packet - take skb from ring element and put in a new one */
2173 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2174 struct rx_ring_info
*re
,
2175 unsigned int length
)
2177 struct sk_buff
*skb
, *nskb
;
2178 unsigned hdr_space
= sky2
->rx_data_size
;
2180 /* Don't be tricky about reusing pages (yet) */
2181 nskb
= sky2_rx_alloc(sky2
);
2182 if (unlikely(!nskb
))
2186 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2188 prefetch(skb
->data
);
2190 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2192 if (skb_shinfo(skb
)->nr_frags
)
2193 skb_put_frags(skb
, hdr_space
, length
);
2195 skb_put(skb
, length
);
2200 * Receive one packet.
2201 * For larger packets, get new buffer.
2203 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2204 u16 length
, u32 status
)
2206 struct sky2_port
*sky2
= netdev_priv(dev
);
2207 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2208 struct sk_buff
*skb
= NULL
;
2209 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2211 #ifdef SKY2_VLAN_TAG_USED
2212 /* Account for vlan tag */
2213 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
))
2217 if (unlikely(netif_msg_rx_status(sky2
)))
2218 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2219 dev
->name
, sky2
->rx_next
, status
, length
);
2221 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2222 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2224 /* This chip has hardware problems that generates bogus status.
2225 * So do only marginal checking and expect higher level protocols
2226 * to handle crap frames.
2228 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2229 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2233 if (status
& GMR_FS_ANY_ERR
)
2236 if (!(status
& GMR_FS_RX_OK
))
2239 /* if length reported by DMA does not match PHY, packet was truncated */
2240 if (length
!= count
)
2244 if (length
< copybreak
)
2245 skb
= receive_copy(sky2
, re
, length
);
2247 skb
= receive_new(sky2
, re
, length
);
2249 sky2_rx_submit(sky2
, re
);
2254 /* Truncation of overlength packets
2255 causes PHY length to not match MAC length */
2256 ++dev
->stats
.rx_length_errors
;
2257 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2258 pr_info(PFX
"%s: rx length error: status %#x length %d\n",
2259 dev
->name
, status
, length
);
2263 ++dev
->stats
.rx_errors
;
2264 if (status
& GMR_FS_RX_FF_OV
) {
2265 dev
->stats
.rx_over_errors
++;
2269 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2270 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2271 dev
->name
, status
, length
);
2273 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2274 dev
->stats
.rx_length_errors
++;
2275 if (status
& GMR_FS_FRAGMENT
)
2276 dev
->stats
.rx_frame_errors
++;
2277 if (status
& GMR_FS_CRC_ERR
)
2278 dev
->stats
.rx_crc_errors
++;
2283 /* Transmit complete */
2284 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2286 struct sky2_port
*sky2
= netdev_priv(dev
);
2288 if (netif_running(dev
)) {
2290 sky2_tx_complete(sky2
, last
);
2291 netif_tx_unlock(dev
);
2295 /* Process status response ring */
2296 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2299 unsigned rx
[2] = { 0, 0 };
2303 struct sky2_port
*sky2
;
2304 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2306 struct net_device
*dev
;
2307 struct sk_buff
*skb
;
2310 u8 opcode
= le
->opcode
;
2312 if (!(opcode
& HW_OWNER
))
2315 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2317 port
= le
->css
& CSS_LINK_BIT
;
2318 dev
= hw
->dev
[port
];
2319 sky2
= netdev_priv(dev
);
2320 length
= le16_to_cpu(le
->length
);
2321 status
= le32_to_cpu(le
->status
);
2324 switch (opcode
& ~HW_OWNER
) {
2327 skb
= sky2_receive(dev
, length
, status
);
2328 if (unlikely(!skb
)) {
2329 dev
->stats
.rx_dropped
++;
2333 /* This chip reports checksum status differently */
2334 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2335 if (sky2
->rx_csum
&&
2336 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2337 (le
->css
& CSS_TCPUDPCSOK
))
2338 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2340 skb
->ip_summed
= CHECKSUM_NONE
;
2343 skb
->protocol
= eth_type_trans(skb
, dev
);
2344 dev
->stats
.rx_packets
++;
2345 dev
->stats
.rx_bytes
+= skb
->len
;
2346 dev
->last_rx
= jiffies
;
2348 #ifdef SKY2_VLAN_TAG_USED
2349 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2350 vlan_hwaccel_receive_skb(skb
,
2352 be16_to_cpu(sky2
->rx_tag
));
2355 netif_receive_skb(skb
);
2357 /* Stop after net poll weight */
2358 if (++work_done
>= to_do
)
2362 #ifdef SKY2_VLAN_TAG_USED
2364 sky2
->rx_tag
= length
;
2368 sky2
->rx_tag
= length
;
2375 /* If this happens then driver assuming wrong format */
2376 if (unlikely(hw
->flags
& SKY2_HW_NEW_LE
)) {
2377 if (net_ratelimit())
2378 printk(KERN_NOTICE
"%s: unexpected"
2379 " checksum status\n",
2384 /* Both checksum counters are programmed to start at
2385 * the same offset, so unless there is a problem they
2386 * should match. This failure is an early indication that
2387 * hardware receive checksumming won't work.
2389 if (likely(status
>> 16 == (status
& 0xffff))) {
2390 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2391 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2392 skb
->csum
= status
& 0xffff;
2394 printk(KERN_NOTICE PFX
"%s: hardware receive "
2395 "checksum problem (status = %#x)\n",
2398 sky2_write32(sky2
->hw
,
2399 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2405 /* TX index reports status for both ports */
2406 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2407 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2409 sky2_tx_done(hw
->dev
[1],
2410 ((status
>> 24) & 0xff)
2411 | (u16
)(length
& 0xf) << 8);
2415 if (net_ratelimit())
2416 printk(KERN_WARNING PFX
2417 "unknown status opcode 0x%x\n", opcode
);
2419 } while (hw
->st_idx
!= idx
);
2421 /* Fully processed status ring so clear irq */
2422 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2426 sky2_rx_update(netdev_priv(hw
->dev
[0]), Q_R1
);
2429 sky2_rx_update(netdev_priv(hw
->dev
[1]), Q_R2
);
2434 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2436 struct net_device
*dev
= hw
->dev
[port
];
2438 if (net_ratelimit())
2439 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2442 if (status
& Y2_IS_PAR_RD1
) {
2443 if (net_ratelimit())
2444 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2447 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2450 if (status
& Y2_IS_PAR_WR1
) {
2451 if (net_ratelimit())
2452 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2455 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2458 if (status
& Y2_IS_PAR_MAC1
) {
2459 if (net_ratelimit())
2460 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2461 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2464 if (status
& Y2_IS_PAR_RX1
) {
2465 if (net_ratelimit())
2466 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2467 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2470 if (status
& Y2_IS_TCP_TXA1
) {
2471 if (net_ratelimit())
2472 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2474 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2478 static void sky2_hw_intr(struct sky2_hw
*hw
)
2480 struct pci_dev
*pdev
= hw
->pdev
;
2481 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2482 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2486 if (status
& Y2_IS_TIST_OV
)
2487 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2489 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2492 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2493 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2494 if (net_ratelimit())
2495 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2498 sky2_pci_write16(hw
, PCI_STATUS
,
2499 pci_err
| PCI_STATUS_ERROR_BITS
);
2500 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2503 if (status
& Y2_IS_PCI_EXP
) {
2504 /* PCI-Express uncorrectable Error occurred */
2507 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2508 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2509 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2511 if (net_ratelimit())
2512 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2514 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2515 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2518 if (status
& Y2_HWE_L1_MASK
)
2519 sky2_hw_error(hw
, 0, status
);
2521 if (status
& Y2_HWE_L1_MASK
)
2522 sky2_hw_error(hw
, 1, status
);
2525 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2527 struct net_device
*dev
= hw
->dev
[port
];
2528 struct sky2_port
*sky2
= netdev_priv(dev
);
2529 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2531 if (netif_msg_intr(sky2
))
2532 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2535 if (status
& GM_IS_RX_CO_OV
)
2536 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2538 if (status
& GM_IS_TX_CO_OV
)
2539 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2541 if (status
& GM_IS_RX_FF_OR
) {
2542 ++dev
->stats
.rx_fifo_errors
;
2543 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2546 if (status
& GM_IS_TX_FF_UR
) {
2547 ++dev
->stats
.tx_fifo_errors
;
2548 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2552 /* This should never happen it is a bug. */
2553 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2554 u16 q
, unsigned ring_size
)
2556 struct net_device
*dev
= hw
->dev
[port
];
2557 struct sky2_port
*sky2
= netdev_priv(dev
);
2559 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2560 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2562 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2563 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2564 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2565 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2567 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2570 static int sky2_rx_hung(struct net_device
*dev
)
2572 struct sky2_port
*sky2
= netdev_priv(dev
);
2573 struct sky2_hw
*hw
= sky2
->hw
;
2574 unsigned port
= sky2
->port
;
2575 unsigned rxq
= rxqaddr
[port
];
2576 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2577 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2578 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2579 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2581 /* If idle and MAC or PCI is stuck */
2582 if (sky2
->check
.last
== dev
->last_rx
&&
2583 ((mac_rp
== sky2
->check
.mac_rp
&&
2584 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2585 /* Check if the PCI RX hang */
2586 (fifo_rp
== sky2
->check
.fifo_rp
&&
2587 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2588 printk(KERN_DEBUG PFX
"%s: hung mac %d:%d fifo %d (%d:%d)\n",
2589 dev
->name
, mac_lev
, mac_rp
, fifo_lev
, fifo_rp
,
2590 sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2593 sky2
->check
.last
= dev
->last_rx
;
2594 sky2
->check
.mac_rp
= mac_rp
;
2595 sky2
->check
.mac_lev
= mac_lev
;
2596 sky2
->check
.fifo_rp
= fifo_rp
;
2597 sky2
->check
.fifo_lev
= fifo_lev
;
2602 static void sky2_watchdog(unsigned long arg
)
2604 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2606 /* Check for lost IRQ once a second */
2607 if (sky2_read32(hw
, B0_ISRC
)) {
2608 napi_schedule(&hw
->napi
);
2612 for (i
= 0; i
< hw
->ports
; i
++) {
2613 struct net_device
*dev
= hw
->dev
[i
];
2614 if (!netif_running(dev
))
2618 /* For chips with Rx FIFO, check if stuck */
2619 if ((hw
->flags
& SKY2_HW_RAM_BUFFER
) &&
2620 sky2_rx_hung(dev
)) {
2621 pr_info(PFX
"%s: receiver hang detected\n",
2623 schedule_work(&hw
->restart_work
);
2632 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2635 /* Hardware/software error handling */
2636 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2638 if (net_ratelimit())
2639 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2641 if (status
& Y2_IS_HW_ERR
)
2644 if (status
& Y2_IS_IRQ_MAC1
)
2645 sky2_mac_intr(hw
, 0);
2647 if (status
& Y2_IS_IRQ_MAC2
)
2648 sky2_mac_intr(hw
, 1);
2650 if (status
& Y2_IS_CHK_RX1
)
2651 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2653 if (status
& Y2_IS_CHK_RX2
)
2654 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2656 if (status
& Y2_IS_CHK_TXA1
)
2657 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2659 if (status
& Y2_IS_CHK_TXA2
)
2660 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2663 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
2665 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
2666 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2670 if (unlikely(status
& Y2_IS_ERROR
))
2671 sky2_err_intr(hw
, status
);
2673 if (status
& Y2_IS_IRQ_PHY1
)
2674 sky2_phy_intr(hw
, 0);
2676 if (status
& Y2_IS_IRQ_PHY2
)
2677 sky2_phy_intr(hw
, 1);
2679 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
2680 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
2682 if (work_done
>= work_limit
)
2686 /* Bug/Errata workaround?
2687 * Need to kick the TX irq moderation timer.
2689 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_START
) {
2690 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2691 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2693 napi_complete(napi
);
2694 sky2_read32(hw
, B0_Y2_SP_LISR
);
2700 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2702 struct sky2_hw
*hw
= dev_id
;
2705 /* Reading this mask interrupts as side effect */
2706 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2707 if (status
== 0 || status
== ~0)
2710 prefetch(&hw
->st_le
[hw
->st_idx
]);
2712 napi_schedule(&hw
->napi
);
2717 #ifdef CONFIG_NET_POLL_CONTROLLER
2718 static void sky2_netpoll(struct net_device
*dev
)
2720 struct sky2_port
*sky2
= netdev_priv(dev
);
2722 napi_schedule(&sky2
->hw
->napi
);
2726 /* Chip internal frequency for clock calculations */
2727 static u32
sky2_mhz(const struct sky2_hw
*hw
)
2729 switch (hw
->chip_id
) {
2730 case CHIP_ID_YUKON_EC
:
2731 case CHIP_ID_YUKON_EC_U
:
2732 case CHIP_ID_YUKON_EX
:
2733 case CHIP_ID_YUKON_SUPR
:
2734 case CHIP_ID_YUKON_UL_2
:
2737 case CHIP_ID_YUKON_FE
:
2740 case CHIP_ID_YUKON_FE_P
:
2743 case CHIP_ID_YUKON_XL
:
2751 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2753 return sky2_mhz(hw
) * us
;
2756 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2758 return clk
/ sky2_mhz(hw
);
2762 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2766 /* Enable all clocks and check for bad PCI access */
2767 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2769 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2771 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2772 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2774 switch(hw
->chip_id
) {
2775 case CHIP_ID_YUKON_XL
:
2776 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_NEWER_PHY
;
2779 case CHIP_ID_YUKON_EC_U
:
2780 hw
->flags
= SKY2_HW_GIGABIT
2782 | SKY2_HW_ADV_POWER_CTL
;
2785 case CHIP_ID_YUKON_EX
:
2786 hw
->flags
= SKY2_HW_GIGABIT
2789 | SKY2_HW_ADV_POWER_CTL
;
2791 /* New transmit checksum */
2792 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
2793 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
2796 case CHIP_ID_YUKON_EC
:
2797 /* This rev is really old, and requires untested workarounds */
2798 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2799 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
2802 hw
->flags
= SKY2_HW_GIGABIT
;
2805 case CHIP_ID_YUKON_FE
:
2808 case CHIP_ID_YUKON_FE_P
:
2809 hw
->flags
= SKY2_HW_NEWER_PHY
2811 | SKY2_HW_AUTO_TX_SUM
2812 | SKY2_HW_ADV_POWER_CTL
;
2815 case CHIP_ID_YUKON_SUPR
:
2816 hw
->flags
= SKY2_HW_GIGABIT
2819 | SKY2_HW_AUTO_TX_SUM
2820 | SKY2_HW_ADV_POWER_CTL
;
2823 case CHIP_ID_YUKON_UL_2
:
2824 hw
->flags
= SKY2_HW_GIGABIT
2825 | SKY2_HW_ADV_POWER_CTL
;
2829 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2834 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2835 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
2836 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
2839 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2840 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2841 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2848 static void sky2_reset(struct sky2_hw
*hw
)
2850 struct pci_dev
*pdev
= hw
->pdev
;
2853 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
2856 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2857 status
= sky2_read16(hw
, HCU_CCSR
);
2858 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2859 HCU_CCSR_UC_STATE_MSK
);
2860 sky2_write16(hw
, HCU_CCSR
, status
);
2862 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2863 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2866 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2867 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2869 /* allow writes to PCI config */
2870 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2872 /* clear PCI errors, if any */
2873 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2874 status
|= PCI_STATUS_ERROR_BITS
;
2875 sky2_pci_write16(hw
, PCI_STATUS
, status
);
2877 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2879 cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2881 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2884 /* If error bit is stuck on ignore it */
2885 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
2886 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
2888 hwe_mask
|= Y2_IS_PCI_EXP
;
2892 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2894 for (i
= 0; i
< hw
->ports
; i
++) {
2895 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2896 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2898 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
2899 hw
->chip_id
== CHIP_ID_YUKON_SUPR
)
2900 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
2901 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
2905 /* Clear I2C IRQ noise */
2906 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2908 /* turn off hardware timer (unused) */
2909 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2910 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2912 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2914 /* Turn off descriptor polling */
2915 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2917 /* Turn off receive timestamp */
2918 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2919 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2921 /* enable the Tx Arbiters */
2922 for (i
= 0; i
< hw
->ports
; i
++)
2923 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2925 /* Initialize ram interface */
2926 for (i
= 0; i
< hw
->ports
; i
++) {
2927 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2929 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2930 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2931 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2932 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2933 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2934 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2935 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2936 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2937 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2938 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2939 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2940 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2943 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
2945 for (i
= 0; i
< hw
->ports
; i
++)
2946 sky2_gmac_reset(hw
, i
);
2948 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2951 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2952 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2954 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2955 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2957 /* Set the list last index */
2958 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2960 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2961 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2963 /* set Status-FIFO ISR watermark */
2964 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2965 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2967 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2969 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2970 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2971 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2973 /* enable status unit */
2974 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2976 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2977 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2978 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2981 static void sky2_restart(struct work_struct
*work
)
2983 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2984 struct net_device
*dev
;
2988 for (i
= 0; i
< hw
->ports
; i
++) {
2990 if (netif_running(dev
))
2994 napi_disable(&hw
->napi
);
2995 sky2_write32(hw
, B0_IMSK
, 0);
2997 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2998 napi_enable(&hw
->napi
);
3000 for (i
= 0; i
< hw
->ports
; i
++) {
3002 if (netif_running(dev
)) {
3005 printk(KERN_INFO PFX
"%s: could not restart %d\n",
3015 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
3017 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
3020 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3022 const struct sky2_port
*sky2
= netdev_priv(dev
);
3024 wol
->supported
= sky2_wol_supported(sky2
->hw
);
3025 wol
->wolopts
= sky2
->wol
;
3028 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3030 struct sky2_port
*sky2
= netdev_priv(dev
);
3031 struct sky2_hw
*hw
= sky2
->hw
;
3033 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
3036 sky2
->wol
= wol
->wolopts
;
3038 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3039 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3040 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
3041 sky2_write32(hw
, B0_CTST
, sky2
->wol
3042 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
3044 if (!netif_running(dev
))
3045 sky2_wol_init(sky2
);
3049 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
3051 if (sky2_is_copper(hw
)) {
3052 u32 modes
= SUPPORTED_10baseT_Half
3053 | SUPPORTED_10baseT_Full
3054 | SUPPORTED_100baseT_Half
3055 | SUPPORTED_100baseT_Full
3056 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
3058 if (hw
->flags
& SKY2_HW_GIGABIT
)
3059 modes
|= SUPPORTED_1000baseT_Half
3060 | SUPPORTED_1000baseT_Full
;
3063 return SUPPORTED_1000baseT_Half
3064 | SUPPORTED_1000baseT_Full
3069 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3071 struct sky2_port
*sky2
= netdev_priv(dev
);
3072 struct sky2_hw
*hw
= sky2
->hw
;
3074 ecmd
->transceiver
= XCVR_INTERNAL
;
3075 ecmd
->supported
= sky2_supported_modes(hw
);
3076 ecmd
->phy_address
= PHY_ADDR_MARV
;
3077 if (sky2_is_copper(hw
)) {
3078 ecmd
->port
= PORT_TP
;
3079 ecmd
->speed
= sky2
->speed
;
3081 ecmd
->speed
= SPEED_1000
;
3082 ecmd
->port
= PORT_FIBRE
;
3085 ecmd
->advertising
= sky2
->advertising
;
3086 ecmd
->autoneg
= sky2
->autoneg
;
3087 ecmd
->duplex
= sky2
->duplex
;
3091 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3093 struct sky2_port
*sky2
= netdev_priv(dev
);
3094 const struct sky2_hw
*hw
= sky2
->hw
;
3095 u32 supported
= sky2_supported_modes(hw
);
3097 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3098 ecmd
->advertising
= supported
;
3104 switch (ecmd
->speed
) {
3106 if (ecmd
->duplex
== DUPLEX_FULL
)
3107 setting
= SUPPORTED_1000baseT_Full
;
3108 else if (ecmd
->duplex
== DUPLEX_HALF
)
3109 setting
= SUPPORTED_1000baseT_Half
;
3114 if (ecmd
->duplex
== DUPLEX_FULL
)
3115 setting
= SUPPORTED_100baseT_Full
;
3116 else if (ecmd
->duplex
== DUPLEX_HALF
)
3117 setting
= SUPPORTED_100baseT_Half
;
3123 if (ecmd
->duplex
== DUPLEX_FULL
)
3124 setting
= SUPPORTED_10baseT_Full
;
3125 else if (ecmd
->duplex
== DUPLEX_HALF
)
3126 setting
= SUPPORTED_10baseT_Half
;
3134 if ((setting
& supported
) == 0)
3137 sky2
->speed
= ecmd
->speed
;
3138 sky2
->duplex
= ecmd
->duplex
;
3141 sky2
->autoneg
= ecmd
->autoneg
;
3142 sky2
->advertising
= ecmd
->advertising
;
3144 if (netif_running(dev
)) {
3145 sky2_phy_reinit(sky2
);
3146 sky2_set_multicast(dev
);
3152 static void sky2_get_drvinfo(struct net_device
*dev
,
3153 struct ethtool_drvinfo
*info
)
3155 struct sky2_port
*sky2
= netdev_priv(dev
);
3157 strcpy(info
->driver
, DRV_NAME
);
3158 strcpy(info
->version
, DRV_VERSION
);
3159 strcpy(info
->fw_version
, "N/A");
3160 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
3163 static const struct sky2_stat
{
3164 char name
[ETH_GSTRING_LEN
];
3167 { "tx_bytes", GM_TXO_OK_HI
},
3168 { "rx_bytes", GM_RXO_OK_HI
},
3169 { "tx_broadcast", GM_TXF_BC_OK
},
3170 { "rx_broadcast", GM_RXF_BC_OK
},
3171 { "tx_multicast", GM_TXF_MC_OK
},
3172 { "rx_multicast", GM_RXF_MC_OK
},
3173 { "tx_unicast", GM_TXF_UC_OK
},
3174 { "rx_unicast", GM_RXF_UC_OK
},
3175 { "tx_mac_pause", GM_TXF_MPAUSE
},
3176 { "rx_mac_pause", GM_RXF_MPAUSE
},
3177 { "collisions", GM_TXF_COL
},
3178 { "late_collision",GM_TXF_LAT_COL
},
3179 { "aborted", GM_TXF_ABO_COL
},
3180 { "single_collisions", GM_TXF_SNG_COL
},
3181 { "multi_collisions", GM_TXF_MUL_COL
},
3183 { "rx_short", GM_RXF_SHT
},
3184 { "rx_runt", GM_RXE_FRAG
},
3185 { "rx_64_byte_packets", GM_RXF_64B
},
3186 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3187 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3188 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3189 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3190 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3191 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3192 { "rx_too_long", GM_RXF_LNG_ERR
},
3193 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3194 { "rx_jabber", GM_RXF_JAB_PKT
},
3195 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3197 { "tx_64_byte_packets", GM_TXF_64B
},
3198 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3199 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3200 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3201 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3202 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3203 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3204 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3207 static u32
sky2_get_rx_csum(struct net_device
*dev
)
3209 struct sky2_port
*sky2
= netdev_priv(dev
);
3211 return sky2
->rx_csum
;
3214 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
3216 struct sky2_port
*sky2
= netdev_priv(dev
);
3218 sky2
->rx_csum
= data
;
3220 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
3221 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
3226 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3228 struct sky2_port
*sky2
= netdev_priv(netdev
);
3229 return sky2
->msg_enable
;
3232 static int sky2_nway_reset(struct net_device
*dev
)
3234 struct sky2_port
*sky2
= netdev_priv(dev
);
3236 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
3239 sky2_phy_reinit(sky2
);
3240 sky2_set_multicast(dev
);
3245 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3247 struct sky2_hw
*hw
= sky2
->hw
;
3248 unsigned port
= sky2
->port
;
3251 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3252 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3253 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3254 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3256 for (i
= 2; i
< count
; i
++)
3257 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3260 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3262 struct sky2_port
*sky2
= netdev_priv(netdev
);
3263 sky2
->msg_enable
= value
;
3266 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3270 return ARRAY_SIZE(sky2_stats
);
3276 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3277 struct ethtool_stats
*stats
, u64
* data
)
3279 struct sky2_port
*sky2
= netdev_priv(dev
);
3281 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3284 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3288 switch (stringset
) {
3290 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3291 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3292 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3297 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3299 struct sky2_port
*sky2
= netdev_priv(dev
);
3300 struct sky2_hw
*hw
= sky2
->hw
;
3301 unsigned port
= sky2
->port
;
3302 const struct sockaddr
*addr
= p
;
3304 if (!is_valid_ether_addr(addr
->sa_data
))
3305 return -EADDRNOTAVAIL
;
3307 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3308 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3309 dev
->dev_addr
, ETH_ALEN
);
3310 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3311 dev
->dev_addr
, ETH_ALEN
);
3313 /* virtual address for data */
3314 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3316 /* physical address: used for pause frames */
3317 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3322 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3326 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3327 filter
[bit
>> 3] |= 1 << (bit
& 7);
3330 static void sky2_set_multicast(struct net_device
*dev
)
3332 struct sky2_port
*sky2
= netdev_priv(dev
);
3333 struct sky2_hw
*hw
= sky2
->hw
;
3334 unsigned port
= sky2
->port
;
3335 struct dev_mc_list
*list
= dev
->mc_list
;
3339 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3341 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3342 memset(filter
, 0, sizeof(filter
));
3344 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3345 reg
|= GM_RXCR_UCF_ENA
;
3347 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3348 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3349 else if (dev
->flags
& IFF_ALLMULTI
)
3350 memset(filter
, 0xff, sizeof(filter
));
3351 else if (dev
->mc_count
== 0 && !rx_pause
)
3352 reg
&= ~GM_RXCR_MCF_ENA
;
3355 reg
|= GM_RXCR_MCF_ENA
;
3358 sky2_add_filter(filter
, pause_mc_addr
);
3360 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3361 sky2_add_filter(filter
, list
->dmi_addr
);
3364 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3365 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3366 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3367 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3368 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3369 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3370 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3371 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3373 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3376 /* Can have one global because blinking is controlled by
3377 * ethtool and that is always under RTNL mutex
3379 static void sky2_led(struct sky2_port
*sky2
, enum led_mode mode
)
3381 struct sky2_hw
*hw
= sky2
->hw
;
3382 unsigned port
= sky2
->port
;
3384 spin_lock_bh(&sky2
->phy_lock
);
3385 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3386 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3387 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3389 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3390 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3394 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3395 PHY_M_LEDC_LOS_CTRL(8) |
3396 PHY_M_LEDC_INIT_CTRL(8) |
3397 PHY_M_LEDC_STA1_CTRL(8) |
3398 PHY_M_LEDC_STA0_CTRL(8));
3401 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3402 PHY_M_LEDC_LOS_CTRL(9) |
3403 PHY_M_LEDC_INIT_CTRL(9) |
3404 PHY_M_LEDC_STA1_CTRL(9) |
3405 PHY_M_LEDC_STA0_CTRL(9));
3408 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3409 PHY_M_LEDC_LOS_CTRL(0xa) |
3410 PHY_M_LEDC_INIT_CTRL(0xa) |
3411 PHY_M_LEDC_STA1_CTRL(0xa) |
3412 PHY_M_LEDC_STA0_CTRL(0xa));
3415 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3416 PHY_M_LEDC_LOS_CTRL(1) |
3417 PHY_M_LEDC_INIT_CTRL(8) |
3418 PHY_M_LEDC_STA1_CTRL(7) |
3419 PHY_M_LEDC_STA0_CTRL(7));
3422 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3424 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3425 PHY_M_LED_MO_DUP(mode
) |
3426 PHY_M_LED_MO_10(mode
) |
3427 PHY_M_LED_MO_100(mode
) |
3428 PHY_M_LED_MO_1000(mode
) |
3429 PHY_M_LED_MO_RX(mode
) |
3430 PHY_M_LED_MO_TX(mode
));
3432 spin_unlock_bh(&sky2
->phy_lock
);
3435 /* blink LED's for finding board */
3436 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3438 struct sky2_port
*sky2
= netdev_priv(dev
);
3444 for (i
= 0; i
< data
; i
++) {
3445 sky2_led(sky2
, MO_LED_ON
);
3446 if (msleep_interruptible(500))
3448 sky2_led(sky2
, MO_LED_OFF
);
3449 if (msleep_interruptible(500))
3452 sky2_led(sky2
, MO_LED_NORM
);
3457 static void sky2_get_pauseparam(struct net_device
*dev
,
3458 struct ethtool_pauseparam
*ecmd
)
3460 struct sky2_port
*sky2
= netdev_priv(dev
);
3462 switch (sky2
->flow_mode
) {
3464 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3467 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3470 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3473 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3476 ecmd
->autoneg
= sky2
->autoneg
;
3479 static int sky2_set_pauseparam(struct net_device
*dev
,
3480 struct ethtool_pauseparam
*ecmd
)
3482 struct sky2_port
*sky2
= netdev_priv(dev
);
3484 sky2
->autoneg
= ecmd
->autoneg
;
3485 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3487 if (netif_running(dev
))
3488 sky2_phy_reinit(sky2
);
3493 static int sky2_get_coalesce(struct net_device
*dev
,
3494 struct ethtool_coalesce
*ecmd
)
3496 struct sky2_port
*sky2
= netdev_priv(dev
);
3497 struct sky2_hw
*hw
= sky2
->hw
;
3499 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3500 ecmd
->tx_coalesce_usecs
= 0;
3502 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3503 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3505 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3507 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3508 ecmd
->rx_coalesce_usecs
= 0;
3510 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3511 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3513 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3515 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3516 ecmd
->rx_coalesce_usecs_irq
= 0;
3518 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3519 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3522 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3527 /* Note: this affect both ports */
3528 static int sky2_set_coalesce(struct net_device
*dev
,
3529 struct ethtool_coalesce
*ecmd
)
3531 struct sky2_port
*sky2
= netdev_priv(dev
);
3532 struct sky2_hw
*hw
= sky2
->hw
;
3533 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3535 if (ecmd
->tx_coalesce_usecs
> tmax
||
3536 ecmd
->rx_coalesce_usecs
> tmax
||
3537 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3540 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3542 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3544 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3547 if (ecmd
->tx_coalesce_usecs
== 0)
3548 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3550 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3551 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3552 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3554 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3556 if (ecmd
->rx_coalesce_usecs
== 0)
3557 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3559 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3560 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3561 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3563 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3565 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3566 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3568 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3569 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3570 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3572 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3576 static void sky2_get_ringparam(struct net_device
*dev
,
3577 struct ethtool_ringparam
*ering
)
3579 struct sky2_port
*sky2
= netdev_priv(dev
);
3581 ering
->rx_max_pending
= RX_MAX_PENDING
;
3582 ering
->rx_mini_max_pending
= 0;
3583 ering
->rx_jumbo_max_pending
= 0;
3584 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3586 ering
->rx_pending
= sky2
->rx_pending
;
3587 ering
->rx_mini_pending
= 0;
3588 ering
->rx_jumbo_pending
= 0;
3589 ering
->tx_pending
= sky2
->tx_pending
;
3592 static int sky2_set_ringparam(struct net_device
*dev
,
3593 struct ethtool_ringparam
*ering
)
3595 struct sky2_port
*sky2
= netdev_priv(dev
);
3598 if (ering
->rx_pending
> RX_MAX_PENDING
||
3599 ering
->rx_pending
< 8 ||
3600 ering
->tx_pending
< MAX_SKB_TX_LE
||
3601 ering
->tx_pending
> TX_RING_SIZE
- 1)
3604 if (netif_running(dev
))
3607 sky2
->rx_pending
= ering
->rx_pending
;
3608 sky2
->tx_pending
= ering
->tx_pending
;
3610 if (netif_running(dev
)) {
3619 static int sky2_get_regs_len(struct net_device
*dev
)
3625 * Returns copy of control register region
3626 * Note: ethtool_get_regs always provides full size (16k) buffer
3628 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3631 const struct sky2_port
*sky2
= netdev_priv(dev
);
3632 const void __iomem
*io
= sky2
->hw
->regs
;
3637 for (b
= 0; b
< 128; b
++) {
3638 /* This complicated switch statement is to make sure and
3639 * only access regions that are unreserved.
3640 * Some blocks are only valid on dual port cards.
3641 * and block 3 has some special diagnostic registers that
3646 /* skip diagnostic ram region */
3647 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
3650 /* dual port cards only */
3651 case 5: /* Tx Arbiter 2 */
3653 case 14 ... 15: /* TX2 */
3654 case 17: case 19: /* Ram Buffer 2 */
3655 case 22 ... 23: /* Tx Ram Buffer 2 */
3656 case 25: /* Rx MAC Fifo 1 */
3657 case 27: /* Tx MAC Fifo 2 */
3658 case 31: /* GPHY 2 */
3659 case 40 ... 47: /* Pattern Ram 2 */
3660 case 52: case 54: /* TCP Segmentation 2 */
3661 case 112 ... 116: /* GMAC 2 */
3662 if (sky2
->hw
->ports
== 1)
3665 case 0: /* Control */
3666 case 2: /* Mac address */
3667 case 4: /* Tx Arbiter 1 */
3668 case 7: /* PCI express reg */
3670 case 12 ... 13: /* TX1 */
3671 case 16: case 18:/* Rx Ram Buffer 1 */
3672 case 20 ... 21: /* Tx Ram Buffer 1 */
3673 case 24: /* Rx MAC Fifo 1 */
3674 case 26: /* Tx MAC Fifo 1 */
3675 case 28 ... 29: /* Descriptor and status unit */
3676 case 30: /* GPHY 1*/
3677 case 32 ... 39: /* Pattern Ram 1 */
3678 case 48: case 50: /* TCP Segmentation 1 */
3679 case 56 ... 60: /* PCI space */
3680 case 80 ... 84: /* GMAC 1 */
3681 memcpy_fromio(p
, io
, 128);
3693 /* In order to do Jumbo packets on these chips, need to turn off the
3694 * transmit store/forward. Therefore checksum offload won't work.
3696 static int no_tx_offload(struct net_device
*dev
)
3698 const struct sky2_port
*sky2
= netdev_priv(dev
);
3699 const struct sky2_hw
*hw
= sky2
->hw
;
3701 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3704 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3706 if (data
&& no_tx_offload(dev
))
3709 return ethtool_op_set_tx_csum(dev
, data
);
3713 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3715 if (data
&& no_tx_offload(dev
))
3718 return ethtool_op_set_tso(dev
, data
);
3721 static int sky2_get_eeprom_len(struct net_device
*dev
)
3723 struct sky2_port
*sky2
= netdev_priv(dev
);
3724 struct sky2_hw
*hw
= sky2
->hw
;
3727 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
3728 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3731 static u32
sky2_vpd_read(struct sky2_hw
*hw
, int cap
, u16 offset
)
3735 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3738 offset
= sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
);
3739 } while (!(offset
& PCI_VPD_ADDR_F
));
3741 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3745 static void sky2_vpd_write(struct sky2_hw
*hw
, int cap
, u16 offset
, u32 val
)
3747 sky2_pci_write16(hw
, cap
+ PCI_VPD_DATA
, val
);
3748 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
3750 offset
= sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
);
3751 } while (offset
& PCI_VPD_ADDR_F
);
3754 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3757 struct sky2_port
*sky2
= netdev_priv(dev
);
3758 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3759 int length
= eeprom
->len
;
3760 u16 offset
= eeprom
->offset
;
3765 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
3767 while (length
> 0) {
3768 u32 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3769 int n
= min_t(int, length
, sizeof(val
));
3771 memcpy(data
, &val
, n
);
3779 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3782 struct sky2_port
*sky2
= netdev_priv(dev
);
3783 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3784 int length
= eeprom
->len
;
3785 u16 offset
= eeprom
->offset
;
3790 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
3793 while (length
> 0) {
3795 int n
= min_t(int, length
, sizeof(val
));
3797 if (n
< sizeof(val
))
3798 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3799 memcpy(&val
, data
, n
);
3801 sky2_vpd_write(sky2
->hw
, cap
, offset
, val
);
3811 static const struct ethtool_ops sky2_ethtool_ops
= {
3812 .get_settings
= sky2_get_settings
,
3813 .set_settings
= sky2_set_settings
,
3814 .get_drvinfo
= sky2_get_drvinfo
,
3815 .get_wol
= sky2_get_wol
,
3816 .set_wol
= sky2_set_wol
,
3817 .get_msglevel
= sky2_get_msglevel
,
3818 .set_msglevel
= sky2_set_msglevel
,
3819 .nway_reset
= sky2_nway_reset
,
3820 .get_regs_len
= sky2_get_regs_len
,
3821 .get_regs
= sky2_get_regs
,
3822 .get_link
= ethtool_op_get_link
,
3823 .get_eeprom_len
= sky2_get_eeprom_len
,
3824 .get_eeprom
= sky2_get_eeprom
,
3825 .set_eeprom
= sky2_set_eeprom
,
3826 .set_sg
= ethtool_op_set_sg
,
3827 .set_tx_csum
= sky2_set_tx_csum
,
3828 .set_tso
= sky2_set_tso
,
3829 .get_rx_csum
= sky2_get_rx_csum
,
3830 .set_rx_csum
= sky2_set_rx_csum
,
3831 .get_strings
= sky2_get_strings
,
3832 .get_coalesce
= sky2_get_coalesce
,
3833 .set_coalesce
= sky2_set_coalesce
,
3834 .get_ringparam
= sky2_get_ringparam
,
3835 .set_ringparam
= sky2_set_ringparam
,
3836 .get_pauseparam
= sky2_get_pauseparam
,
3837 .set_pauseparam
= sky2_set_pauseparam
,
3838 .phys_id
= sky2_phys_id
,
3839 .get_sset_count
= sky2_get_sset_count
,
3840 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3843 #ifdef CONFIG_SKY2_DEBUG
3845 static struct dentry
*sky2_debug
;
3847 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
3849 struct net_device
*dev
= seq
->private;
3850 const struct sky2_port
*sky2
= netdev_priv(dev
);
3851 struct sky2_hw
*hw
= sky2
->hw
;
3852 unsigned port
= sky2
->port
;
3856 if (!netif_running(dev
))
3859 seq_printf(seq
, "IRQ src=%x mask=%x control=%x\n",
3860 sky2_read32(hw
, B0_ISRC
),
3861 sky2_read32(hw
, B0_IMSK
),
3862 sky2_read32(hw
, B0_Y2_SP_ICR
));
3864 napi_disable(&hw
->napi
);
3865 last
= sky2_read16(hw
, STAT_PUT_IDX
);
3867 if (hw
->st_idx
== last
)
3868 seq_puts(seq
, "Status ring (empty)\n");
3870 seq_puts(seq
, "Status ring\n");
3871 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
3872 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
3873 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
3874 seq_printf(seq
, "[%d] %#x %d %#x\n",
3875 idx
, le
->opcode
, le
->length
, le
->status
);
3877 seq_puts(seq
, "\n");
3880 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
3881 sky2
->tx_cons
, sky2
->tx_prod
,
3882 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
3883 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
3885 /* Dump contents of tx ring */
3887 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< TX_RING_SIZE
;
3888 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
3889 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
3890 u32 a
= le32_to_cpu(le
->addr
);
3893 seq_printf(seq
, "%u:", idx
);
3896 switch(le
->opcode
& ~HW_OWNER
) {
3898 seq_printf(seq
, " %#x:", a
);
3901 seq_printf(seq
, " mtu=%d", a
);
3904 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
3907 seq_printf(seq
, " csum=%#x", a
);
3910 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
3913 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
3916 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
3919 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
3920 a
, le16_to_cpu(le
->length
));
3923 if (le
->ctrl
& EOP
) {
3924 seq_putc(seq
, '\n');
3929 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
3930 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
3931 last
= sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
3932 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
3934 sky2_read32(hw
, B0_Y2_SP_LISR
);
3935 napi_enable(&hw
->napi
);
3939 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
3941 return single_open(file
, sky2_debug_show
, inode
->i_private
);
3944 static const struct file_operations sky2_debug_fops
= {
3945 .owner
= THIS_MODULE
,
3946 .open
= sky2_debug_open
,
3948 .llseek
= seq_lseek
,
3949 .release
= single_release
,
3953 * Use network device events to create/remove/rename
3954 * debugfs file entries
3956 static int sky2_device_event(struct notifier_block
*unused
,
3957 unsigned long event
, void *ptr
)
3959 struct net_device
*dev
= ptr
;
3960 struct sky2_port
*sky2
= netdev_priv(dev
);
3962 if (dev
->open
!= sky2_up
|| !sky2_debug
)
3966 case NETDEV_CHANGENAME
:
3967 if (sky2
->debugfs
) {
3968 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
3969 sky2_debug
, dev
->name
);
3973 case NETDEV_GOING_DOWN
:
3974 if (sky2
->debugfs
) {
3975 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
3977 debugfs_remove(sky2
->debugfs
);
3978 sky2
->debugfs
= NULL
;
3983 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
3986 if (IS_ERR(sky2
->debugfs
))
3987 sky2
->debugfs
= NULL
;
3993 static struct notifier_block sky2_notifier
= {
3994 .notifier_call
= sky2_device_event
,
3998 static __init
void sky2_debug_init(void)
4002 ent
= debugfs_create_dir("sky2", NULL
);
4003 if (!ent
|| IS_ERR(ent
))
4007 register_netdevice_notifier(&sky2_notifier
);
4010 static __exit
void sky2_debug_cleanup(void)
4013 unregister_netdevice_notifier(&sky2_notifier
);
4014 debugfs_remove(sky2_debug
);
4020 #define sky2_debug_init()
4021 #define sky2_debug_cleanup()
4025 /* Initialize network device */
4026 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
4028 int highmem
, int wol
)
4030 struct sky2_port
*sky2
;
4031 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
4034 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
4038 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
4039 dev
->irq
= hw
->pdev
->irq
;
4040 dev
->open
= sky2_up
;
4041 dev
->stop
= sky2_down
;
4042 dev
->do_ioctl
= sky2_ioctl
;
4043 dev
->hard_start_xmit
= sky2_xmit_frame
;
4044 dev
->set_multicast_list
= sky2_set_multicast
;
4045 dev
->set_mac_address
= sky2_set_mac_address
;
4046 dev
->change_mtu
= sky2_change_mtu
;
4047 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
4048 dev
->tx_timeout
= sky2_tx_timeout
;
4049 dev
->watchdog_timeo
= TX_WATCHDOG
;
4050 #ifdef CONFIG_NET_POLL_CONTROLLER
4052 dev
->poll_controller
= sky2_netpoll
;
4055 sky2
= netdev_priv(dev
);
4058 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
4060 /* Auto speed and flow control */
4061 sky2
->autoneg
= AUTONEG_ENABLE
;
4062 sky2
->flow_mode
= FC_BOTH
;
4066 sky2
->advertising
= sky2_supported_modes(hw
);
4067 sky2
->rx_csum
= (hw
->chip_id
!= CHIP_ID_YUKON_XL
);
4070 spin_lock_init(&sky2
->phy_lock
);
4071 sky2
->tx_pending
= TX_DEF_PENDING
;
4072 sky2
->rx_pending
= RX_DEF_PENDING
;
4074 hw
->dev
[port
] = dev
;
4078 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
4080 dev
->features
|= NETIF_F_HIGHDMA
;
4082 #ifdef SKY2_VLAN_TAG_USED
4083 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4084 if (!(sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
4085 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)) {
4086 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4087 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
4091 /* read the mac address */
4092 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4093 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4098 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4100 const struct sky2_port
*sky2
= netdev_priv(dev
);
4101 DECLARE_MAC_BUF(mac
);
4103 if (netif_msg_probe(sky2
))
4104 printk(KERN_INFO PFX
"%s: addr %s\n",
4105 dev
->name
, print_mac(mac
, dev
->dev_addr
));
4108 /* Handle software interrupt used during MSI test */
4109 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4111 struct sky2_hw
*hw
= dev_id
;
4112 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4117 if (status
& Y2_IS_IRQ_SW
) {
4118 hw
->flags
|= SKY2_HW_USE_MSI
;
4119 wake_up(&hw
->msi_wait
);
4120 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4122 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4127 /* Test interrupt path by forcing a a software IRQ */
4128 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4130 struct pci_dev
*pdev
= hw
->pdev
;
4133 init_waitqueue_head (&hw
->msi_wait
);
4135 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4137 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4139 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4143 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4144 sky2_read8(hw
, B0_CTST
);
4146 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4148 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4149 /* MSI test failed, go back to INTx mode */
4150 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4151 "switching to INTx mode.\n");
4154 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4157 sky2_write32(hw
, B0_IMSK
, 0);
4158 sky2_read32(hw
, B0_IMSK
);
4160 free_irq(pdev
->irq
, hw
);
4165 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
4167 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
4172 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
4174 return value
& PCI_PM_CTRL_PME_ENABLE
;
4177 /* This driver supports yukon2 chipset only */
4178 static const char *sky2_name(u8 chipid
, char *buf
, int sz
)
4180 const char *name
[] = {
4182 "EC Ultra", /* 0xb4 */
4183 "Extreme", /* 0xb5 */
4187 "Supreme", /* 0xb9 */
4191 if (chipid
>= CHIP_ID_YUKON_XL
&& chipid
< CHIP_ID_YUKON_UL_2
)
4192 strncpy(buf
, name
[chipid
- CHIP_ID_YUKON_XL
], sz
);
4194 snprintf(buf
, sz
, "(chip %#x)", chipid
);
4198 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4199 const struct pci_device_id
*ent
)
4201 struct net_device
*dev
;
4203 int err
, using_dac
= 0, wol_default
;
4206 err
= pci_enable_device(pdev
);
4208 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4212 err
= pci_request_regions(pdev
, DRV_NAME
);
4214 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4215 goto err_out_disable
;
4218 pci_set_master(pdev
);
4220 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4221 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
4223 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
4225 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4226 "for consistent allocations\n");
4227 goto err_out_free_regions
;
4230 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
4232 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4233 goto err_out_free_regions
;
4237 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
4240 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
4242 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4243 goto err_out_free_regions
;
4248 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4250 dev_err(&pdev
->dev
, "cannot map device registers\n");
4251 goto err_out_free_hw
;
4255 /* The sk98lin vendor driver uses hardware byte swapping but
4256 * this driver uses software swapping.
4260 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
4261 reg
&= ~PCI_REV_DESC
;
4262 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
4266 /* ring for status responses */
4267 hw
->st_le
= pci_alloc_consistent(pdev
, STATUS_LE_BYTES
, &hw
->st_dma
);
4269 goto err_out_iounmap
;
4271 err
= sky2_init(hw
);
4273 goto err_out_iounmap
;
4275 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4276 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
4277 pdev
->irq
, sky2_name(hw
->chip_id
, buf1
, sizeof(buf1
)),
4282 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4285 goto err_out_free_pci
;
4288 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4289 err
= sky2_test_msi(hw
);
4290 if (err
== -EOPNOTSUPP
)
4291 pci_disable_msi(pdev
);
4293 goto err_out_free_netdev
;
4296 err
= register_netdev(dev
);
4298 dev_err(&pdev
->dev
, "cannot register net device\n");
4299 goto err_out_free_netdev
;
4302 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
4304 err
= request_irq(pdev
->irq
, sky2_intr
,
4305 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
4308 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4309 goto err_out_unregister
;
4311 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4312 napi_enable(&hw
->napi
);
4314 sky2_show_addr(dev
);
4316 if (hw
->ports
> 1) {
4317 struct net_device
*dev1
;
4319 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4321 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
4322 else if ((err
= register_netdev(dev1
))) {
4323 dev_warn(&pdev
->dev
,
4324 "register of second port failed (%d)\n", err
);
4328 sky2_show_addr(dev1
);
4331 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4332 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4334 pci_set_drvdata(pdev
, hw
);
4339 if (hw
->flags
& SKY2_HW_USE_MSI
)
4340 pci_disable_msi(pdev
);
4341 unregister_netdev(dev
);
4342 err_out_free_netdev
:
4345 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4346 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4351 err_out_free_regions
:
4352 pci_release_regions(pdev
);
4354 pci_disable_device(pdev
);
4356 pci_set_drvdata(pdev
, NULL
);
4360 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4362 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4368 del_timer_sync(&hw
->watchdog_timer
);
4369 cancel_work_sync(&hw
->restart_work
);
4371 for (i
= hw
->ports
-1; i
>= 0; --i
)
4372 unregister_netdev(hw
->dev
[i
]);
4374 sky2_write32(hw
, B0_IMSK
, 0);
4378 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
4379 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4380 sky2_read8(hw
, B0_CTST
);
4382 free_irq(pdev
->irq
, hw
);
4383 if (hw
->flags
& SKY2_HW_USE_MSI
)
4384 pci_disable_msi(pdev
);
4385 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4386 pci_release_regions(pdev
);
4387 pci_disable_device(pdev
);
4389 for (i
= hw
->ports
-1; i
>= 0; --i
)
4390 free_netdev(hw
->dev
[i
]);
4395 pci_set_drvdata(pdev
, NULL
);
4399 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4401 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4407 del_timer_sync(&hw
->watchdog_timer
);
4408 cancel_work_sync(&hw
->restart_work
);
4410 for (i
= 0; i
< hw
->ports
; i
++) {
4411 struct net_device
*dev
= hw
->dev
[i
];
4412 struct sky2_port
*sky2
= netdev_priv(dev
);
4414 netif_device_detach(dev
);
4415 if (netif_running(dev
))
4419 sky2_wol_init(sky2
);
4424 sky2_write32(hw
, B0_IMSK
, 0);
4425 napi_disable(&hw
->napi
);
4428 pci_save_state(pdev
);
4429 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4430 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4435 static int sky2_resume(struct pci_dev
*pdev
)
4437 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4443 err
= pci_set_power_state(pdev
, PCI_D0
);
4447 err
= pci_restore_state(pdev
);
4451 pci_enable_wake(pdev
, PCI_D0
, 0);
4453 /* Re-enable all clocks */
4454 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
4455 hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
4456 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
4457 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4460 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4461 napi_enable(&hw
->napi
);
4463 for (i
= 0; i
< hw
->ports
; i
++) {
4464 struct net_device
*dev
= hw
->dev
[i
];
4466 netif_device_attach(dev
);
4467 if (netif_running(dev
)) {
4470 printk(KERN_ERR PFX
"%s: could not up: %d\n",
4482 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4483 pci_disable_device(pdev
);
4488 static void sky2_shutdown(struct pci_dev
*pdev
)
4490 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4496 del_timer_sync(&hw
->watchdog_timer
);
4498 for (i
= 0; i
< hw
->ports
; i
++) {
4499 struct net_device
*dev
= hw
->dev
[i
];
4500 struct sky2_port
*sky2
= netdev_priv(dev
);
4504 sky2_wol_init(sky2
);
4511 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4512 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4514 pci_disable_device(pdev
);
4515 pci_set_power_state(pdev
, PCI_D3hot
);
4518 static struct pci_driver sky2_driver
= {
4520 .id_table
= sky2_id_table
,
4521 .probe
= sky2_probe
,
4522 .remove
= __devexit_p(sky2_remove
),
4524 .suspend
= sky2_suspend
,
4525 .resume
= sky2_resume
,
4527 .shutdown
= sky2_shutdown
,
4530 static int __init
sky2_init_module(void)
4533 return pci_register_driver(&sky2_driver
);
4536 static void __exit
sky2_cleanup_module(void)
4538 pci_unregister_driver(&sky2_driver
);
4539 sky2_debug_cleanup();
4542 module_init(sky2_init_module
);
4543 module_exit(sky2_cleanup_module
);
4545 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4546 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4547 MODULE_LICENSE("GPL");
4548 MODULE_VERSION(DRV_VERSION
);