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ea23da53677b0c9740767a0324a7c8cdee859b0e
[deliverable/linux.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/in.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.2"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 256;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static int idle_timeout = 100;
102 module_param(idle_timeout, int, 0);
103 MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
123 { 0 }
124 };
125
126 MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131
132 /* This driver supports yukon2 chipset only */
133 static const char *yukon2_name[] = {
134 "XL", /* 0xb3 */
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
137 "EC", /* 0xb6 */
138 "FE", /* 0xb7 */
139 };
140
141 /* Access to external PHY */
142 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
143 {
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
152 return 0;
153 udelay(1);
154 }
155
156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
157 return -ETIMEDOUT;
158 }
159
160 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
161 {
162 int i;
163
164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
166
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
170 return 0;
171 }
172
173 udelay(1);
174 }
175
176 return -ETIMEDOUT;
177 }
178
179 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
180 {
181 u16 v;
182
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
185 return v;
186 }
187
188 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
189 {
190 u16 power_control;
191 u32 reg1;
192 int vaux;
193 int ret = 0;
194
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
197
198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
201
202 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
203
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
206
207 switch (state) {
208 case PCI_D0:
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 /* Turn off phy power saving */
226 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
228
229 /* looks like this XL is back asswards .. */
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
232 if (hw->ports > 1)
233 reg1 |= PCI_Y2_PHY2_COMA;
234 }
235
236 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
239 reg1 &= P_ASPM_CONTROL_MSK;
240 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
241 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
242 }
243
244 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
245
246 break;
247
248 case PCI_D3hot:
249 case PCI_D3cold:
250 /* Turn on phy power saving */
251 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
254 else
255 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
256 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
257
258 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
259 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
260 else
261 /* enable bits are inverted */
262 sky2_write8(hw, B2_Y2_CLK_GATE,
263 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
264 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
265 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
266
267 /* switch power to VAUX */
268 if (vaux && state != PCI_D3cold)
269 sky2_write8(hw, B0_POWER_CTRL,
270 (PC_VAUX_ENA | PC_VCC_ENA |
271 PC_VAUX_ON | PC_VCC_OFF));
272 break;
273 default:
274 printk(KERN_ERR PFX "Unknown power state %d\n", state);
275 ret = -1;
276 }
277
278 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
280 return ret;
281 }
282
283 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
284 {
285 u16 reg;
286
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
289 /* disable PHY IRQs */
290 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
291
292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300 }
301
302 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
303 {
304 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
305 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
306
307 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
308 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
309
310 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
311 PHY_M_EC_MAC_S_MSK);
312 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
313
314 if (hw->chip_id == CHIP_ID_YUKON_EC)
315 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
316 else
317 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
318
319 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
320 }
321
322 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
323 if (hw->copper) {
324 if (hw->chip_id == CHIP_ID_YUKON_FE) {
325 /* enable automatic crossover */
326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
327 } else {
328 /* disable energy detect */
329 ctrl &= ~PHY_M_PC_EN_DET_MSK;
330
331 /* enable automatic crossover */
332 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
333
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 hw->chip_id == CHIP_ID_YUKON_XL) {
336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 }
339 }
340 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
341 } else {
342 /* workaround for deviation #4.88 (CRC errors) */
343 /* disable Automatic Crossover */
344
345 ctrl &= ~PHY_M_PC_MDIX_MSK;
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 if (hw->chip_id == CHIP_ID_YUKON_XL) {
349 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl &= ~PHY_M_MAC_MD_MSK;
353 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
354 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
355
356 /* select page 1 to access Fiber registers */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
358 }
359 }
360
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
363 ctrl &= ~PHY_CT_ANE;
364 else
365 ctrl |= PHY_CT_ANE;
366
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
369
370 ctrl = 0;
371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
373
374 if (sky2->autoneg == AUTONEG_ENABLE) {
375 if (hw->copper) {
376 if (sky2->advertising & ADVERTISED_1000baseT_Full)
377 ct1000 |= PHY_M_1000C_AFD;
378 if (sky2->advertising & ADVERTISED_1000baseT_Half)
379 ct1000 |= PHY_M_1000C_AHD;
380 if (sky2->advertising & ADVERTISED_100baseT_Full)
381 adv |= PHY_M_AN_100_FD;
382 if (sky2->advertising & ADVERTISED_100baseT_Half)
383 adv |= PHY_M_AN_100_HD;
384 if (sky2->advertising & ADVERTISED_10baseT_Full)
385 adv |= PHY_M_AN_10_FD;
386 if (sky2->advertising & ADVERTISED_10baseT_Half)
387 adv |= PHY_M_AN_10_HD;
388 } else /* special defines for FIBER (88E1011S only) */
389 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
390
391 /* Set Flow-control capabilities */
392 if (sky2->tx_pause && sky2->rx_pause)
393 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
394 else if (sky2->rx_pause && !sky2->tx_pause)
395 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
396 else if (!sky2->rx_pause && sky2->tx_pause)
397 adv |= PHY_AN_PAUSE_ASYM; /* local */
398
399 /* Restart Auto-negotiation */
400 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
401 } else {
402 /* forced speed/duplex settings */
403 ct1000 = PHY_M_1000C_MSE;
404
405 if (sky2->duplex == DUPLEX_FULL)
406 ctrl |= PHY_CT_DUP_MD;
407
408 switch (sky2->speed) {
409 case SPEED_1000:
410 ctrl |= PHY_CT_SP1000;
411 break;
412 case SPEED_100:
413 ctrl |= PHY_CT_SP100;
414 break;
415 }
416
417 ctrl |= PHY_CT_RESET;
418 }
419
420 if (hw->chip_id != CHIP_ID_YUKON_FE)
421 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
422
423 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
424 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
425
426 /* Setup Phy LED's */
427 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
428 ledover = 0;
429
430 switch (hw->chip_id) {
431 case CHIP_ID_YUKON_FE:
432 /* on 88E3082 these bits are at 11..9 (shifted left) */
433 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
434
435 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
436
437 /* delete ACT LED control bits */
438 ctrl &= ~PHY_M_FELP_LED1_MSK;
439 /* change ACT LED control to blink mode */
440 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
441 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
442 break;
443
444 case CHIP_ID_YUKON_XL:
445 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
446
447 /* select page 3 to access LED control register */
448 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
449
450 /* set LED Function Control register */
451 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
452 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
453 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
454 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
455
456 /* set Polarity Control register */
457 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
458 (PHY_M_POLC_LS1_P_MIX(4) |
459 PHY_M_POLC_IS0_P_MIX(4) |
460 PHY_M_POLC_LOS_CTRL(2) |
461 PHY_M_POLC_INIT_CTRL(2) |
462 PHY_M_POLC_STA1_CTRL(2) |
463 PHY_M_POLC_STA0_CTRL(2)));
464
465 /* restore page register */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
467 break;
468
469 default:
470 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
471 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
472 /* turn off the Rx LED (LED_RX) */
473 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
474 }
475
476 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
477 /* apply fixes in PHY AFE */
478 gm_phy_write(hw, port, 22, 255);
479 /* increase differential signal amplitude in 10BASE-T */
480 gm_phy_write(hw, port, 24, 0xaa99);
481 gm_phy_write(hw, port, 23, 0x2011);
482
483 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
484 gm_phy_write(hw, port, 24, 0xa204);
485 gm_phy_write(hw, port, 23, 0x2002);
486
487 /* set page register to 0 */
488 gm_phy_write(hw, port, 22, 0);
489 } else {
490 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
491
492 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
493 /* turn on 100 Mbps LED (LED_LINK100) */
494 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
495 }
496
497 if (ledover)
498 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
499
500 }
501 /* Enable phy interrupt on auto-negotiation complete (or link up) */
502 if (sky2->autoneg == AUTONEG_ENABLE)
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
504 else
505 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
506 }
507
508 /* Force a renegotiation */
509 static void sky2_phy_reinit(struct sky2_port *sky2)
510 {
511 spin_lock_bh(&sky2->phy_lock);
512 sky2_phy_init(sky2->hw, sky2->port);
513 spin_unlock_bh(&sky2->phy_lock);
514 }
515
516 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
517 {
518 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
519 u16 reg;
520 int i;
521 const u8 *addr = hw->dev[port]->dev_addr;
522
523 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
524 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
525
526 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
527
528 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
529 /* WA DEV_472 -- looks like crossed wires on port 2 */
530 /* clear GMAC 1 Control reset */
531 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
532 do {
533 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
534 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
535 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
536 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
537 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
538 }
539
540 if (sky2->autoneg == AUTONEG_DISABLE) {
541 reg = gma_read16(hw, port, GM_GP_CTRL);
542 reg |= GM_GPCR_AU_ALL_DIS;
543 gma_write16(hw, port, GM_GP_CTRL, reg);
544 gma_read16(hw, port, GM_GP_CTRL);
545
546 switch (sky2->speed) {
547 case SPEED_1000:
548 reg &= ~GM_GPCR_SPEED_100;
549 reg |= GM_GPCR_SPEED_1000;
550 break;
551 case SPEED_100:
552 reg &= ~GM_GPCR_SPEED_1000;
553 reg |= GM_GPCR_SPEED_100;
554 break;
555 case SPEED_10:
556 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
557 break;
558 }
559
560 if (sky2->duplex == DUPLEX_FULL)
561 reg |= GM_GPCR_DUP_FULL;
562 } else
563 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564
565 if (!sky2->tx_pause && !sky2->rx_pause) {
566 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
567 reg |=
568 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
569 } else if (sky2->tx_pause && !sky2->rx_pause) {
570 /* disable Rx flow-control */
571 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
572 }
573
574 gma_write16(hw, port, GM_GP_CTRL, reg);
575
576 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
577
578 spin_lock_bh(&sky2->phy_lock);
579 sky2_phy_init(hw, port);
580 spin_unlock_bh(&sky2->phy_lock);
581
582 /* MIB clear */
583 reg = gma_read16(hw, port, GM_PHY_ADDR);
584 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
585
586 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
587 gma_read16(hw, port, i);
588 gma_write16(hw, port, GM_PHY_ADDR, reg);
589
590 /* transmit control */
591 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
592
593 /* receive control reg: unicast + multicast + no FCS */
594 gma_write16(hw, port, GM_RX_CTRL,
595 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
596
597 /* transmit flow control */
598 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
599
600 /* transmit parameter */
601 gma_write16(hw, port, GM_TX_PARAM,
602 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
603 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
604 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
605 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
606
607 /* serial mode register */
608 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
609 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
610
611 if (hw->dev[port]->mtu > ETH_DATA_LEN)
612 reg |= GM_SMOD_JUMBO_ENA;
613
614 gma_write16(hw, port, GM_SERIAL_MODE, reg);
615
616 /* virtual address for data */
617 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
618
619 /* physical address: used for pause frames */
620 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
621
622 /* ignore counter overflows */
623 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
624 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
625 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
626
627 /* Configure Rx MAC FIFO */
628 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
629 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
630 GMF_OPER_ON | GMF_RX_F_FL_ON);
631
632 /* Flush Rx MAC FIFO on any flow control or error */
633 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
634
635 /* Set threshold to 0xa (64 bytes)
636 * ASF disabled so no need to do WA dev #4.30
637 */
638 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
639
640 /* Configure Tx MAC FIFO */
641 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
642 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
643
644 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
645 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
646 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
647 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
648 /* set Tx GMAC FIFO Almost Empty Threshold */
649 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
650 /* Disable Store & Forward mode for TX */
651 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
652 }
653 }
654
655 }
656
657 /* Assign Ram Buffer allocation.
658 * start and end are in units of 4k bytes
659 * ram registers are in units of 64bit words
660 */
661 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
662 {
663 u32 start, end;
664
665 start = startk * 4096/8;
666 end = (endk * 4096/8) - 1;
667
668 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
669 sky2_write32(hw, RB_ADDR(q, RB_START), start);
670 sky2_write32(hw, RB_ADDR(q, RB_END), end);
671 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
672 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
673
674 if (q == Q_R1 || q == Q_R2) {
675 u32 space = (endk - startk) * 4096/8;
676 u32 tp = space - space/4;
677
678 /* On receive queue's set the thresholds
679 * give receiver priority when > 3/4 full
680 * send pause when down to 2K
681 */
682 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
683 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
684
685 tp = space - 2048/8;
686 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
687 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
688 } else {
689 /* Enable store & forward on Tx queue's because
690 * Tx FIFO is only 1K on Yukon
691 */
692 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
693 }
694
695 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
696 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
697 }
698
699 /* Setup Bus Memory Interface */
700 static void sky2_qset(struct sky2_hw *hw, u16 q)
701 {
702 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
703 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
704 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
705 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
706 }
707
708 /* Setup prefetch unit registers. This is the interface between
709 * hardware and driver list elements
710 */
711 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
712 u64 addr, u32 last)
713 {
714 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
715 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
716 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
717 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
718 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
719 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
720
721 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
722 }
723
724 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
725 {
726 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
727
728 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
729 return le;
730 }
731
732 /* Update chip's next pointer */
733 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
734 {
735 wmb();
736 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
737 mmiowb();
738 }
739
740
741 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
742 {
743 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
744 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
745 return le;
746 }
747
748 /* Return high part of DMA address (could be 32 or 64 bit) */
749 static inline u32 high32(dma_addr_t a)
750 {
751 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
752 }
753
754 /* Build description to hardware about buffer */
755 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
756 {
757 struct sky2_rx_le *le;
758 u32 hi = high32(map);
759 u16 len = sky2->rx_bufsize;
760
761 if (sky2->rx_addr64 != hi) {
762 le = sky2_next_rx(sky2);
763 le->addr = cpu_to_le32(hi);
764 le->ctrl = 0;
765 le->opcode = OP_ADDR64 | HW_OWNER;
766 sky2->rx_addr64 = high32(map + len);
767 }
768
769 le = sky2_next_rx(sky2);
770 le->addr = cpu_to_le32((u32) map);
771 le->length = cpu_to_le16(len);
772 le->ctrl = 0;
773 le->opcode = OP_PACKET | HW_OWNER;
774 }
775
776
777 /* Tell chip where to start receive checksum.
778 * Actually has two checksums, but set both same to avoid possible byte
779 * order problems.
780 */
781 static void rx_set_checksum(struct sky2_port *sky2)
782 {
783 struct sky2_rx_le *le;
784
785 le = sky2_next_rx(sky2);
786 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
787 le->ctrl = 0;
788 le->opcode = OP_TCPSTART | HW_OWNER;
789
790 sky2_write32(sky2->hw,
791 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
792 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
793
794 }
795
796 /*
797 * The RX Stop command will not work for Yukon-2 if the BMU does not
798 * reach the end of packet and since we can't make sure that we have
799 * incoming data, we must reset the BMU while it is not doing a DMA
800 * transfer. Since it is possible that the RX path is still active,
801 * the RX RAM buffer will be stopped first, so any possible incoming
802 * data will not trigger a DMA. After the RAM buffer is stopped, the
803 * BMU is polled until any DMA in progress is ended and only then it
804 * will be reset.
805 */
806 static void sky2_rx_stop(struct sky2_port *sky2)
807 {
808 struct sky2_hw *hw = sky2->hw;
809 unsigned rxq = rxqaddr[sky2->port];
810 int i;
811
812 /* disable the RAM Buffer receive queue */
813 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
814
815 for (i = 0; i < 0xffff; i++)
816 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
817 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
818 goto stopped;
819
820 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
821 sky2->netdev->name);
822 stopped:
823 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
824
825 /* reset the Rx prefetch unit */
826 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
827 }
828
829 /* Clean out receive buffer area, assumes receiver hardware stopped */
830 static void sky2_rx_clean(struct sky2_port *sky2)
831 {
832 unsigned i;
833
834 memset(sky2->rx_le, 0, RX_LE_BYTES);
835 for (i = 0; i < sky2->rx_pending; i++) {
836 struct ring_info *re = sky2->rx_ring + i;
837
838 if (re->skb) {
839 pci_unmap_single(sky2->hw->pdev,
840 re->mapaddr, sky2->rx_bufsize,
841 PCI_DMA_FROMDEVICE);
842 kfree_skb(re->skb);
843 re->skb = NULL;
844 }
845 }
846 }
847
848 /* Basic MII support */
849 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
850 {
851 struct mii_ioctl_data *data = if_mii(ifr);
852 struct sky2_port *sky2 = netdev_priv(dev);
853 struct sky2_hw *hw = sky2->hw;
854 int err = -EOPNOTSUPP;
855
856 if (!netif_running(dev))
857 return -ENODEV; /* Phy still in reset */
858
859 switch (cmd) {
860 case SIOCGMIIPHY:
861 data->phy_id = PHY_ADDR_MARV;
862
863 /* fallthru */
864 case SIOCGMIIREG: {
865 u16 val = 0;
866
867 spin_lock_bh(&sky2->phy_lock);
868 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
869 spin_unlock_bh(&sky2->phy_lock);
870
871 data->val_out = val;
872 break;
873 }
874
875 case SIOCSMIIREG:
876 if (!capable(CAP_NET_ADMIN))
877 return -EPERM;
878
879 spin_lock_bh(&sky2->phy_lock);
880 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
881 data->val_in);
882 spin_unlock_bh(&sky2->phy_lock);
883 break;
884 }
885 return err;
886 }
887
888 #ifdef SKY2_VLAN_TAG_USED
889 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
890 {
891 struct sky2_port *sky2 = netdev_priv(dev);
892 struct sky2_hw *hw = sky2->hw;
893 u16 port = sky2->port;
894
895 spin_lock_bh(&sky2->tx_lock);
896
897 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
898 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
899 sky2->vlgrp = grp;
900
901 spin_unlock_bh(&sky2->tx_lock);
902 }
903
904 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
905 {
906 struct sky2_port *sky2 = netdev_priv(dev);
907 struct sky2_hw *hw = sky2->hw;
908 u16 port = sky2->port;
909
910 spin_lock_bh(&sky2->tx_lock);
911
912 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
913 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
914 if (sky2->vlgrp)
915 sky2->vlgrp->vlan_devices[vid] = NULL;
916
917 spin_unlock_bh(&sky2->tx_lock);
918 }
919 #endif
920
921 /*
922 * It appears the hardware has a bug in the FIFO logic that
923 * cause it to hang if the FIFO gets overrun and the receive buffer
924 * is not aligned. ALso alloc_skb() won't align properly if slab
925 * debugging is enabled.
926 */
927 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
928 {
929 struct sk_buff *skb;
930
931 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
932 if (likely(skb)) {
933 unsigned long p = (unsigned long) skb->data;
934 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
935 }
936
937 return skb;
938 }
939
940 /*
941 * Allocate and setup receiver buffer pool.
942 * In case of 64 bit dma, there are 2X as many list elements
943 * available as ring entries
944 * and need to reserve one list element so we don't wrap around.
945 */
946 static int sky2_rx_start(struct sky2_port *sky2)
947 {
948 struct sky2_hw *hw = sky2->hw;
949 unsigned rxq = rxqaddr[sky2->port];
950 int i;
951
952 sky2->rx_put = sky2->rx_next = 0;
953 sky2_qset(hw, rxq);
954
955 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
956 /* MAC Rx RAM Read is controlled by hardware */
957 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
958 }
959
960 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
961
962 rx_set_checksum(sky2);
963 for (i = 0; i < sky2->rx_pending; i++) {
964 struct ring_info *re = sky2->rx_ring + i;
965
966 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
967 if (!re->skb)
968 goto nomem;
969
970 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
971 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
972 sky2_rx_add(sky2, re->mapaddr);
973 }
974
975 /* Truncate oversize frames */
976 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
977 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
978
979 /* Tell chip about available buffers */
980 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
981 return 0;
982 nomem:
983 sky2_rx_clean(sky2);
984 return -ENOMEM;
985 }
986
987 /* Bring up network interface. */
988 static int sky2_up(struct net_device *dev)
989 {
990 struct sky2_port *sky2 = netdev_priv(dev);
991 struct sky2_hw *hw = sky2->hw;
992 unsigned port = sky2->port;
993 u32 ramsize, rxspace, imask;
994 int err = -ENOMEM;
995
996 if (netif_msg_ifup(sky2))
997 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
998
999 /* must be power of 2 */
1000 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1001 TX_RING_SIZE *
1002 sizeof(struct sky2_tx_le),
1003 &sky2->tx_le_map);
1004 if (!sky2->tx_le)
1005 goto err_out;
1006
1007 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1008 GFP_KERNEL);
1009 if (!sky2->tx_ring)
1010 goto err_out;
1011 sky2->tx_prod = sky2->tx_cons = 0;
1012
1013 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1014 &sky2->rx_le_map);
1015 if (!sky2->rx_le)
1016 goto err_out;
1017 memset(sky2->rx_le, 0, RX_LE_BYTES);
1018
1019 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1020 GFP_KERNEL);
1021 if (!sky2->rx_ring)
1022 goto err_out;
1023
1024 sky2_mac_init(hw, port);
1025
1026 /* Determine available ram buffer space (in 4K blocks).
1027 * Note: not sure about the FE setting below yet
1028 */
1029 if (hw->chip_id == CHIP_ID_YUKON_FE)
1030 ramsize = 4;
1031 else
1032 ramsize = sky2_read8(hw, B2_E_0);
1033
1034 /* Give transmitter one third (rounded up) */
1035 rxspace = ramsize - (ramsize + 2) / 3;
1036
1037 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1038 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1039
1040 /* Make sure SyncQ is disabled */
1041 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1042 RB_RST_SET);
1043
1044 sky2_qset(hw, txqaddr[port]);
1045
1046 /* Set almost empty threshold */
1047 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1048 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1049
1050 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1051 TX_RING_SIZE - 1);
1052
1053 err = sky2_rx_start(sky2);
1054 if (err)
1055 goto err_out;
1056
1057 /* Enable interrupts from phy/mac for port */
1058 imask = sky2_read32(hw, B0_IMSK);
1059 imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1060 sky2_write32(hw, B0_IMSK, imask);
1061
1062 return 0;
1063
1064 err_out:
1065 if (sky2->rx_le) {
1066 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1067 sky2->rx_le, sky2->rx_le_map);
1068 sky2->rx_le = NULL;
1069 }
1070 if (sky2->tx_le) {
1071 pci_free_consistent(hw->pdev,
1072 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1073 sky2->tx_le, sky2->tx_le_map);
1074 sky2->tx_le = NULL;
1075 }
1076 kfree(sky2->tx_ring);
1077 kfree(sky2->rx_ring);
1078
1079 sky2->tx_ring = NULL;
1080 sky2->rx_ring = NULL;
1081 return err;
1082 }
1083
1084 /* Modular subtraction in ring */
1085 static inline int tx_dist(unsigned tail, unsigned head)
1086 {
1087 return (head - tail) & (TX_RING_SIZE - 1);
1088 }
1089
1090 /* Number of list elements available for next tx */
1091 static inline int tx_avail(const struct sky2_port *sky2)
1092 {
1093 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1094 }
1095
1096 /* Estimate of number of transmit list elements required */
1097 static unsigned tx_le_req(const struct sk_buff *skb)
1098 {
1099 unsigned count;
1100
1101 count = sizeof(dma_addr_t) / sizeof(u32);
1102 count += skb_shinfo(skb)->nr_frags * count;
1103
1104 if (skb_shinfo(skb)->tso_size)
1105 ++count;
1106
1107 if (skb->ip_summed == CHECKSUM_HW)
1108 ++count;
1109
1110 return count;
1111 }
1112
1113 /*
1114 * Put one packet in ring for transmit.
1115 * A single packet can generate multiple list elements, and
1116 * the number of ring elements will probably be less than the number
1117 * of list elements used.
1118 *
1119 * No BH disabling for tx_lock here (like tg3)
1120 */
1121 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1122 {
1123 struct sky2_port *sky2 = netdev_priv(dev);
1124 struct sky2_hw *hw = sky2->hw;
1125 struct sky2_tx_le *le = NULL;
1126 struct tx_ring_info *re;
1127 unsigned i, len;
1128 int avail;
1129 dma_addr_t mapping;
1130 u32 addr64;
1131 u16 mss;
1132 u8 ctrl;
1133
1134 /* No BH disabling for tx_lock here. We are running in BH disabled
1135 * context and TX reclaim runs via poll inside of a software
1136 * interrupt, and no related locks in IRQ processing.
1137 */
1138 if (!spin_trylock(&sky2->tx_lock))
1139 return NETDEV_TX_LOCKED;
1140
1141 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1142 /* There is a known but harmless race with lockless tx
1143 * and netif_stop_queue.
1144 */
1145 if (!netif_queue_stopped(dev)) {
1146 netif_stop_queue(dev);
1147 if (net_ratelimit())
1148 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1149 dev->name);
1150 }
1151 spin_unlock(&sky2->tx_lock);
1152
1153 return NETDEV_TX_BUSY;
1154 }
1155
1156 if (unlikely(netif_msg_tx_queued(sky2)))
1157 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1158 dev->name, sky2->tx_prod, skb->len);
1159
1160 len = skb_headlen(skb);
1161 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1162 addr64 = high32(mapping);
1163
1164 re = sky2->tx_ring + sky2->tx_prod;
1165
1166 /* Send high bits if changed or crosses boundary */
1167 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1168 le = get_tx_le(sky2);
1169 le->tx.addr = cpu_to_le32(addr64);
1170 le->ctrl = 0;
1171 le->opcode = OP_ADDR64 | HW_OWNER;
1172 sky2->tx_addr64 = high32(mapping + len);
1173 }
1174
1175 /* Check for TCP Segmentation Offload */
1176 mss = skb_shinfo(skb)->tso_size;
1177 if (mss != 0) {
1178 /* just drop the packet if non-linear expansion fails */
1179 if (skb_header_cloned(skb) &&
1180 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1181 dev_kfree_skb(skb);
1182 goto out_unlock;
1183 }
1184
1185 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1186 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1187 mss += ETH_HLEN;
1188 }
1189
1190 if (mss != sky2->tx_last_mss) {
1191 le = get_tx_le(sky2);
1192 le->tx.tso.size = cpu_to_le16(mss);
1193 le->tx.tso.rsvd = 0;
1194 le->opcode = OP_LRGLEN | HW_OWNER;
1195 le->ctrl = 0;
1196 sky2->tx_last_mss = mss;
1197 }
1198
1199 ctrl = 0;
1200 #ifdef SKY2_VLAN_TAG_USED
1201 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1202 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1203 if (!le) {
1204 le = get_tx_le(sky2);
1205 le->tx.addr = 0;
1206 le->opcode = OP_VLAN|HW_OWNER;
1207 le->ctrl = 0;
1208 } else
1209 le->opcode |= OP_VLAN;
1210 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1211 ctrl |= INS_VLAN;
1212 }
1213 #endif
1214
1215 /* Handle TCP checksum offload */
1216 if (skb->ip_summed == CHECKSUM_HW) {
1217 u16 hdr = skb->h.raw - skb->data;
1218 u16 offset = hdr + skb->csum;
1219
1220 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1221 if (skb->nh.iph->protocol == IPPROTO_UDP)
1222 ctrl |= UDPTCP;
1223
1224 le = get_tx_le(sky2);
1225 le->tx.csum.start = cpu_to_le16(hdr);
1226 le->tx.csum.offset = cpu_to_le16(offset);
1227 le->length = 0; /* initial checksum value */
1228 le->ctrl = 1; /* one packet */
1229 le->opcode = OP_TCPLISW | HW_OWNER;
1230 }
1231
1232 le = get_tx_le(sky2);
1233 le->tx.addr = cpu_to_le32((u32) mapping);
1234 le->length = cpu_to_le16(len);
1235 le->ctrl = ctrl;
1236 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1237
1238 /* Record the transmit mapping info */
1239 re->skb = skb;
1240 pci_unmap_addr_set(re, mapaddr, mapping);
1241
1242 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1243 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1244 struct tx_ring_info *fre;
1245
1246 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1247 frag->size, PCI_DMA_TODEVICE);
1248 addr64 = high32(mapping);
1249 if (addr64 != sky2->tx_addr64) {
1250 le = get_tx_le(sky2);
1251 le->tx.addr = cpu_to_le32(addr64);
1252 le->ctrl = 0;
1253 le->opcode = OP_ADDR64 | HW_OWNER;
1254 sky2->tx_addr64 = addr64;
1255 }
1256
1257 le = get_tx_le(sky2);
1258 le->tx.addr = cpu_to_le32((u32) mapping);
1259 le->length = cpu_to_le16(frag->size);
1260 le->ctrl = ctrl;
1261 le->opcode = OP_BUFFER | HW_OWNER;
1262
1263 fre = sky2->tx_ring
1264 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1265 pci_unmap_addr_set(fre, mapaddr, mapping);
1266 }
1267
1268 re->idx = sky2->tx_prod;
1269 le->ctrl |= EOP;
1270
1271 avail = tx_avail(sky2);
1272 if (mss != 0 || avail < TX_MIN_PENDING) {
1273 le->ctrl |= FRC_STAT;
1274 if (avail <= MAX_SKB_TX_LE)
1275 netif_stop_queue(dev);
1276 }
1277
1278 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1279
1280 out_unlock:
1281 spin_unlock(&sky2->tx_lock);
1282
1283 dev->trans_start = jiffies;
1284 return NETDEV_TX_OK;
1285 }
1286
1287 /*
1288 * Free ring elements from starting at tx_cons until "done"
1289 *
1290 * NB: the hardware will tell us about partial completion of multi-part
1291 * buffers; these are deferred until completion.
1292 */
1293 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1294 {
1295 struct net_device *dev = sky2->netdev;
1296 struct pci_dev *pdev = sky2->hw->pdev;
1297 u16 nxt, put;
1298 unsigned i;
1299
1300 BUG_ON(done >= TX_RING_SIZE);
1301
1302 if (unlikely(netif_msg_tx_done(sky2)))
1303 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1304 dev->name, done);
1305
1306 for (put = sky2->tx_cons; put != done; put = nxt) {
1307 struct tx_ring_info *re = sky2->tx_ring + put;
1308 struct sk_buff *skb = re->skb;
1309
1310 nxt = re->idx;
1311 BUG_ON(nxt >= TX_RING_SIZE);
1312 prefetch(sky2->tx_ring + nxt);
1313
1314 /* Check for partial status */
1315 if (tx_dist(put, done) < tx_dist(put, nxt))
1316 break;
1317
1318 skb = re->skb;
1319 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1320 skb_headlen(skb), PCI_DMA_TODEVICE);
1321
1322 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1323 struct tx_ring_info *fre;
1324 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
1325 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1326 skb_shinfo(skb)->frags[i].size,
1327 PCI_DMA_TODEVICE);
1328 }
1329
1330 dev_kfree_skb(skb);
1331 }
1332
1333 sky2->tx_cons = put;
1334 if (tx_avail(sky2) > MAX_SKB_TX_LE)
1335 netif_wake_queue(dev);
1336 }
1337
1338 /* Cleanup all untransmitted buffers, assume transmitter not running */
1339 static void sky2_tx_clean(struct sky2_port *sky2)
1340 {
1341 spin_lock_bh(&sky2->tx_lock);
1342 sky2_tx_complete(sky2, sky2->tx_prod);
1343 spin_unlock_bh(&sky2->tx_lock);
1344 }
1345
1346 /* Network shutdown */
1347 static int sky2_down(struct net_device *dev)
1348 {
1349 struct sky2_port *sky2 = netdev_priv(dev);
1350 struct sky2_hw *hw = sky2->hw;
1351 unsigned port = sky2->port;
1352 u16 ctrl;
1353 u32 imask;
1354
1355 /* Never really got started! */
1356 if (!sky2->tx_le)
1357 return 0;
1358
1359 if (netif_msg_ifdown(sky2))
1360 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1361
1362 /* Stop more packets from being queued */
1363 netif_stop_queue(dev);
1364
1365 sky2_phy_reset(hw, port);
1366
1367 /* Stop transmitter */
1368 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1369 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1370
1371 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1372 RB_RST_SET | RB_DIS_OP_MD);
1373
1374 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1375 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1376 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1377
1378 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1379
1380 /* Workaround shared GMAC reset */
1381 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1382 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1383 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1384
1385 /* Disable Force Sync bit and Enable Alloc bit */
1386 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1387 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1388
1389 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1390 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1391 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1392
1393 /* Reset the PCI FIFO of the async Tx queue */
1394 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1395 BMU_RST_SET | BMU_FIFO_RST);
1396
1397 /* Reset the Tx prefetch units */
1398 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1399 PREF_UNIT_RST_SET);
1400
1401 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1402
1403 sky2_rx_stop(sky2);
1404
1405 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1407
1408 /* Disable port IRQ */
1409 imask = sky2_read32(hw, B0_IMSK);
1410 imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1411 sky2_write32(hw, B0_IMSK, imask);
1412
1413 /* turn off LED's */
1414 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1415
1416 synchronize_irq(hw->pdev->irq);
1417
1418 sky2_tx_clean(sky2);
1419 sky2_rx_clean(sky2);
1420
1421 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1422 sky2->rx_le, sky2->rx_le_map);
1423 kfree(sky2->rx_ring);
1424
1425 pci_free_consistent(hw->pdev,
1426 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1427 sky2->tx_le, sky2->tx_le_map);
1428 kfree(sky2->tx_ring);
1429
1430 sky2->tx_le = NULL;
1431 sky2->rx_le = NULL;
1432
1433 sky2->rx_ring = NULL;
1434 sky2->tx_ring = NULL;
1435
1436 return 0;
1437 }
1438
1439 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1440 {
1441 if (!hw->copper)
1442 return SPEED_1000;
1443
1444 if (hw->chip_id == CHIP_ID_YUKON_FE)
1445 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1446
1447 switch (aux & PHY_M_PS_SPEED_MSK) {
1448 case PHY_M_PS_SPEED_1000:
1449 return SPEED_1000;
1450 case PHY_M_PS_SPEED_100:
1451 return SPEED_100;
1452 default:
1453 return SPEED_10;
1454 }
1455 }
1456
1457 static void sky2_link_up(struct sky2_port *sky2)
1458 {
1459 struct sky2_hw *hw = sky2->hw;
1460 unsigned port = sky2->port;
1461 u16 reg;
1462
1463 /* Enable Transmit FIFO Underrun */
1464 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1465
1466 reg = gma_read16(hw, port, GM_GP_CTRL);
1467 if (sky2->autoneg == AUTONEG_DISABLE) {
1468 reg |= GM_GPCR_AU_ALL_DIS;
1469
1470 /* Is write/read necessary? Copied from sky2_mac_init */
1471 gma_write16(hw, port, GM_GP_CTRL, reg);
1472 gma_read16(hw, port, GM_GP_CTRL);
1473
1474 switch (sky2->speed) {
1475 case SPEED_1000:
1476 reg &= ~GM_GPCR_SPEED_100;
1477 reg |= GM_GPCR_SPEED_1000;
1478 break;
1479 case SPEED_100:
1480 reg &= ~GM_GPCR_SPEED_1000;
1481 reg |= GM_GPCR_SPEED_100;
1482 break;
1483 case SPEED_10:
1484 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1485 break;
1486 }
1487 } else
1488 reg &= ~GM_GPCR_AU_ALL_DIS;
1489
1490 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1491 reg |= GM_GPCR_DUP_FULL;
1492
1493 /* enable Rx/Tx */
1494 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1495 gma_write16(hw, port, GM_GP_CTRL, reg);
1496 gma_read16(hw, port, GM_GP_CTRL);
1497
1498 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1499
1500 netif_carrier_on(sky2->netdev);
1501 netif_wake_queue(sky2->netdev);
1502
1503 /* Turn on link LED */
1504 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1505 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1506
1507 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1508 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1509
1510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1512 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1513 SPEED_10 ? 7 : 0) |
1514 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1515 SPEED_100 ? 7 : 0) |
1516 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1517 SPEED_1000 ? 7 : 0));
1518 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1519 }
1520
1521 if (netif_msg_link(sky2))
1522 printk(KERN_INFO PFX
1523 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1524 sky2->netdev->name, sky2->speed,
1525 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1526 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1527 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1528 }
1529
1530 static void sky2_link_down(struct sky2_port *sky2)
1531 {
1532 struct sky2_hw *hw = sky2->hw;
1533 unsigned port = sky2->port;
1534 u16 reg;
1535
1536 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1537
1538 reg = gma_read16(hw, port, GM_GP_CTRL);
1539 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1540 gma_write16(hw, port, GM_GP_CTRL, reg);
1541 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1542
1543 if (sky2->rx_pause && !sky2->tx_pause) {
1544 /* restore Asymmetric Pause bit */
1545 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1546 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1547 | PHY_M_AN_ASP);
1548 }
1549
1550 netif_carrier_off(sky2->netdev);
1551 netif_stop_queue(sky2->netdev);
1552
1553 /* Turn on link LED */
1554 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1555
1556 if (netif_msg_link(sky2))
1557 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1558 sky2_phy_init(hw, port);
1559 }
1560
1561 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1562 {
1563 struct sky2_hw *hw = sky2->hw;
1564 unsigned port = sky2->port;
1565 u16 lpa;
1566
1567 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1568
1569 if (lpa & PHY_M_AN_RF) {
1570 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1571 return -1;
1572 }
1573
1574 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1575 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1576 printk(KERN_ERR PFX "%s: master/slave fault",
1577 sky2->netdev->name);
1578 return -1;
1579 }
1580
1581 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1582 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1583 sky2->netdev->name);
1584 return -1;
1585 }
1586
1587 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1588
1589 sky2->speed = sky2_phy_speed(hw, aux);
1590
1591 /* Pause bits are offset (9..8) */
1592 if (hw->chip_id == CHIP_ID_YUKON_XL)
1593 aux >>= 6;
1594
1595 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1596 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1597
1598 if ((sky2->tx_pause || sky2->rx_pause)
1599 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1601 else
1602 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1603
1604 return 0;
1605 }
1606
1607 /* Interrupt from PHY */
1608 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1609 {
1610 struct net_device *dev = hw->dev[port];
1611 struct sky2_port *sky2 = netdev_priv(dev);
1612 u16 istatus, phystat;
1613
1614 spin_lock(&sky2->phy_lock);
1615 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1616 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1617
1618 if (!netif_running(dev))
1619 goto out;
1620
1621 if (netif_msg_intr(sky2))
1622 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1623 sky2->netdev->name, istatus, phystat);
1624
1625 if (istatus & PHY_M_IS_AN_COMPL) {
1626 if (sky2_autoneg_done(sky2, phystat) == 0)
1627 sky2_link_up(sky2);
1628 goto out;
1629 }
1630
1631 if (istatus & PHY_M_IS_LSP_CHANGE)
1632 sky2->speed = sky2_phy_speed(hw, phystat);
1633
1634 if (istatus & PHY_M_IS_DUP_CHANGE)
1635 sky2->duplex =
1636 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1637
1638 if (istatus & PHY_M_IS_LST_CHANGE) {
1639 if (phystat & PHY_M_PS_LINK_UP)
1640 sky2_link_up(sky2);
1641 else
1642 sky2_link_down(sky2);
1643 }
1644 out:
1645 spin_unlock(&sky2->phy_lock);
1646 }
1647
1648
1649 /* Transmit timeout is only called if we are running, carries is up
1650 * and tx queue is full (stopped).
1651 */
1652 static void sky2_tx_timeout(struct net_device *dev)
1653 {
1654 struct sky2_port *sky2 = netdev_priv(dev);
1655 struct sky2_hw *hw = sky2->hw;
1656 unsigned txq = txqaddr[sky2->port];
1657 u16 report, done;
1658
1659 if (netif_msg_timer(sky2))
1660 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1661
1662 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1663 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1664
1665 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1666 dev->name,
1667 sky2->tx_cons, sky2->tx_prod, report, done);
1668
1669 if (report != done) {
1670 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1671
1672 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1673 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1674 } else if (report != sky2->tx_cons) {
1675 printk(KERN_INFO PFX "status report lost?\n");
1676
1677 spin_lock_bh(&sky2->tx_lock);
1678 sky2_tx_complete(sky2, report);
1679 spin_unlock_bh(&sky2->tx_lock);
1680 } else {
1681 printk(KERN_INFO PFX "hardware hung? flushing\n");
1682
1683 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1684 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1685
1686 sky2_tx_clean(sky2);
1687
1688 sky2_qset(hw, txq);
1689 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1690 }
1691 }
1692
1693
1694 /* Want receive buffer size to be multiple of 64 bits
1695 * and incl room for vlan and truncation
1696 */
1697 static inline unsigned sky2_buf_size(int mtu)
1698 {
1699 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1700 }
1701
1702 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1703 {
1704 struct sky2_port *sky2 = netdev_priv(dev);
1705 struct sky2_hw *hw = sky2->hw;
1706 int err;
1707 u16 ctl, mode;
1708 u32 imask;
1709
1710 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1711 return -EINVAL;
1712
1713 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1714 return -EINVAL;
1715
1716 if (!netif_running(dev)) {
1717 dev->mtu = new_mtu;
1718 return 0;
1719 }
1720
1721 imask = sky2_read32(hw, B0_IMSK);
1722 sky2_write32(hw, B0_IMSK, 0);
1723
1724 dev->trans_start = jiffies; /* prevent tx timeout */
1725 netif_stop_queue(dev);
1726 netif_poll_disable(hw->dev[0]);
1727
1728 synchronize_irq(hw->pdev->irq);
1729
1730 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1731 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1732 sky2_rx_stop(sky2);
1733 sky2_rx_clean(sky2);
1734
1735 dev->mtu = new_mtu;
1736 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1737 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1738 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1739
1740 if (dev->mtu > ETH_DATA_LEN)
1741 mode |= GM_SMOD_JUMBO_ENA;
1742
1743 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1744
1745 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1746
1747 err = sky2_rx_start(sky2);
1748 sky2_write32(hw, B0_IMSK, imask);
1749
1750 if (err)
1751 dev_close(dev);
1752 else {
1753 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1754
1755 netif_poll_enable(hw->dev[0]);
1756 netif_wake_queue(dev);
1757 }
1758
1759 return err;
1760 }
1761
1762 /*
1763 * Receive one packet.
1764 * For small packets or errors, just reuse existing skb.
1765 * For larger packets, get new buffer.
1766 */
1767 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1768 u16 length, u32 status)
1769 {
1770 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1771 struct sk_buff *skb = NULL;
1772
1773 if (unlikely(netif_msg_rx_status(sky2)))
1774 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1775 sky2->netdev->name, sky2->rx_next, status, length);
1776
1777 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1778 prefetch(sky2->rx_ring + sky2->rx_next);
1779
1780 if (status & GMR_FS_ANY_ERR)
1781 goto error;
1782
1783 if (!(status & GMR_FS_RX_OK))
1784 goto resubmit;
1785
1786 if (length > sky2->netdev->mtu + ETH_HLEN)
1787 goto oversize;
1788
1789 if (length < copybreak) {
1790 skb = alloc_skb(length + 2, GFP_ATOMIC);
1791 if (!skb)
1792 goto resubmit;
1793
1794 skb_reserve(skb, 2);
1795 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1796 length, PCI_DMA_FROMDEVICE);
1797 memcpy(skb->data, re->skb->data, length);
1798 skb->ip_summed = re->skb->ip_summed;
1799 skb->csum = re->skb->csum;
1800 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1801 length, PCI_DMA_FROMDEVICE);
1802 } else {
1803 struct sk_buff *nskb;
1804
1805 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1806 if (!nskb)
1807 goto resubmit;
1808
1809 skb = re->skb;
1810 re->skb = nskb;
1811 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1812 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1813 prefetch(skb->data);
1814
1815 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1816 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1817 }
1818
1819 skb_put(skb, length);
1820 resubmit:
1821 re->skb->ip_summed = CHECKSUM_NONE;
1822 sky2_rx_add(sky2, re->mapaddr);
1823
1824 /* Tell receiver about new buffers. */
1825 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
1826
1827 return skb;
1828
1829 oversize:
1830 ++sky2->net_stats.rx_over_errors;
1831 goto resubmit;
1832
1833 error:
1834 ++sky2->net_stats.rx_errors;
1835
1836 if (netif_msg_rx_err(sky2) && net_ratelimit())
1837 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1838 sky2->netdev->name, status, length);
1839
1840 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1841 sky2->net_stats.rx_length_errors++;
1842 if (status & GMR_FS_FRAGMENT)
1843 sky2->net_stats.rx_frame_errors++;
1844 if (status & GMR_FS_CRC_ERR)
1845 sky2->net_stats.rx_crc_errors++;
1846 if (status & GMR_FS_RX_FF_OV)
1847 sky2->net_stats.rx_fifo_errors++;
1848
1849 goto resubmit;
1850 }
1851
1852 /* Transmit complete */
1853 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1854 {
1855 struct sky2_port *sky2 = netdev_priv(dev);
1856
1857 if (netif_running(dev)) {
1858 spin_lock(&sky2->tx_lock);
1859 sky2_tx_complete(sky2, last);
1860 spin_unlock(&sky2->tx_lock);
1861 }
1862 }
1863
1864 /* Process status response ring */
1865 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1866 {
1867 int work_done = 0;
1868 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1869
1870 rmb();
1871
1872 while (hw->st_idx != hwidx) {
1873 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1874 struct net_device *dev;
1875 struct sky2_port *sky2;
1876 struct sk_buff *skb;
1877 u32 status;
1878 u16 length;
1879
1880 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1881
1882 BUG_ON(le->link >= 2);
1883 dev = hw->dev[le->link];
1884
1885 sky2 = netdev_priv(dev);
1886 length = le->length;
1887 status = le->status;
1888
1889 switch (le->opcode & ~HW_OWNER) {
1890 case OP_RXSTAT:
1891 skb = sky2_receive(sky2, length, status);
1892 if (!skb)
1893 break;
1894
1895 skb->dev = dev;
1896 skb->protocol = eth_type_trans(skb, dev);
1897 dev->last_rx = jiffies;
1898
1899 #ifdef SKY2_VLAN_TAG_USED
1900 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1901 vlan_hwaccel_receive_skb(skb,
1902 sky2->vlgrp,
1903 be16_to_cpu(sky2->rx_tag));
1904 } else
1905 #endif
1906 netif_receive_skb(skb);
1907
1908 if (++work_done >= to_do)
1909 goto exit_loop;
1910 break;
1911
1912 #ifdef SKY2_VLAN_TAG_USED
1913 case OP_RXVLAN:
1914 sky2->rx_tag = length;
1915 break;
1916
1917 case OP_RXCHKSVLAN:
1918 sky2->rx_tag = length;
1919 /* fall through */
1920 #endif
1921 case OP_RXCHKS:
1922 skb = sky2->rx_ring[sky2->rx_next].skb;
1923 skb->ip_summed = CHECKSUM_HW;
1924 skb->csum = le16_to_cpu(status);
1925 break;
1926
1927 case OP_TXINDEXLE:
1928 /* TX index reports status for both ports */
1929 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1930 sky2_tx_done(hw->dev[0], status & 0xfff);
1931 if (hw->dev[1])
1932 sky2_tx_done(hw->dev[1],
1933 ((status >> 24) & 0xff)
1934 | (u16)(length & 0xf) << 8);
1935 break;
1936
1937 default:
1938 if (net_ratelimit())
1939 printk(KERN_WARNING PFX
1940 "unknown status opcode 0x%x\n", le->opcode);
1941 goto exit_loop;
1942 }
1943 }
1944
1945 exit_loop:
1946 return work_done;
1947 }
1948
1949 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1950 {
1951 struct net_device *dev = hw->dev[port];
1952
1953 if (net_ratelimit())
1954 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1955 dev->name, status);
1956
1957 if (status & Y2_IS_PAR_RD1) {
1958 if (net_ratelimit())
1959 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1960 dev->name);
1961 /* Clear IRQ */
1962 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1963 }
1964
1965 if (status & Y2_IS_PAR_WR1) {
1966 if (net_ratelimit())
1967 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1968 dev->name);
1969
1970 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1971 }
1972
1973 if (status & Y2_IS_PAR_MAC1) {
1974 if (net_ratelimit())
1975 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1976 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1977 }
1978
1979 if (status & Y2_IS_PAR_RX1) {
1980 if (net_ratelimit())
1981 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1982 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1983 }
1984
1985 if (status & Y2_IS_TCP_TXA1) {
1986 if (net_ratelimit())
1987 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1988 dev->name);
1989 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1990 }
1991 }
1992
1993 static void sky2_hw_intr(struct sky2_hw *hw)
1994 {
1995 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1996
1997 if (status & Y2_IS_TIST_OV)
1998 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1999
2000 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2001 u16 pci_err;
2002
2003 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2004 if (net_ratelimit())
2005 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2006 pci_name(hw->pdev), pci_err);
2007
2008 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2009 sky2_pci_write16(hw, PCI_STATUS,
2010 pci_err | PCI_STATUS_ERROR_BITS);
2011 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2012 }
2013
2014 if (status & Y2_IS_PCI_EXP) {
2015 /* PCI-Express uncorrectable Error occurred */
2016 u32 pex_err;
2017
2018 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2019
2020 if (net_ratelimit())
2021 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2022 pci_name(hw->pdev), pex_err);
2023
2024 /* clear the interrupt */
2025 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2026 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2027 0xffffffffUL);
2028 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2029
2030 if (pex_err & PEX_FATAL_ERRORS) {
2031 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2032 hwmsk &= ~Y2_IS_PCI_EXP;
2033 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2034 }
2035 }
2036
2037 if (status & Y2_HWE_L1_MASK)
2038 sky2_hw_error(hw, 0, status);
2039 status >>= 8;
2040 if (status & Y2_HWE_L1_MASK)
2041 sky2_hw_error(hw, 1, status);
2042 }
2043
2044 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2045 {
2046 struct net_device *dev = hw->dev[port];
2047 struct sky2_port *sky2 = netdev_priv(dev);
2048 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2049
2050 if (netif_msg_intr(sky2))
2051 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2052 dev->name, status);
2053
2054 if (status & GM_IS_RX_FF_OR) {
2055 ++sky2->net_stats.rx_fifo_errors;
2056 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2057 }
2058
2059 if (status & GM_IS_TX_FF_UR) {
2060 ++sky2->net_stats.tx_fifo_errors;
2061 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2062 }
2063 }
2064
2065 /* This should never happen it is a fatal situation */
2066 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2067 const char *rxtx, u32 mask)
2068 {
2069 struct net_device *dev = hw->dev[port];
2070 struct sky2_port *sky2 = netdev_priv(dev);
2071 u32 imask;
2072
2073 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2074 dev ? dev->name : "<not registered>", rxtx);
2075
2076 imask = sky2_read32(hw, B0_IMSK);
2077 imask &= ~mask;
2078 sky2_write32(hw, B0_IMSK, imask);
2079
2080 if (dev) {
2081 spin_lock(&sky2->phy_lock);
2082 sky2_link_down(sky2);
2083 spin_unlock(&sky2->phy_lock);
2084 }
2085 }
2086
2087 /* If idle then force a fake soft NAPI poll once a second
2088 * to work around cases where sharing an edge triggered interrupt.
2089 */
2090 static void sky2_idle(unsigned long arg)
2091 {
2092 struct sky2_hw *hw = (struct sky2_hw *) arg;
2093 struct net_device *dev = hw->dev[0];
2094
2095 if (__netif_rx_schedule_prep(dev))
2096 __netif_rx_schedule(dev);
2097
2098 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2099 }
2100
2101
2102 static int sky2_poll(struct net_device *dev0, int *budget)
2103 {
2104 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2105 int work_limit = min(dev0->quota, *budget);
2106 int work_done = 0;
2107 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2108
2109 if (status & Y2_IS_HW_ERR)
2110 sky2_hw_intr(hw);
2111
2112 if (status & Y2_IS_IRQ_PHY1)
2113 sky2_phy_intr(hw, 0);
2114
2115 if (status & Y2_IS_IRQ_PHY2)
2116 sky2_phy_intr(hw, 1);
2117
2118 if (status & Y2_IS_IRQ_MAC1)
2119 sky2_mac_intr(hw, 0);
2120
2121 if (status & Y2_IS_IRQ_MAC2)
2122 sky2_mac_intr(hw, 1);
2123
2124 if (status & Y2_IS_CHK_RX1)
2125 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2126
2127 if (status & Y2_IS_CHK_RX2)
2128 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2129
2130 if (status & Y2_IS_CHK_TXA1)
2131 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2132
2133 if (status & Y2_IS_CHK_TXA2)
2134 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2135
2136 if (status & Y2_IS_STAT_BMU)
2137 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2138
2139 work_done = sky2_status_intr(hw, work_limit);
2140 *budget -= work_done;
2141 dev0->quota -= work_done;
2142
2143 if (work_done >= work_limit)
2144 return 1;
2145
2146 netif_rx_complete(dev0);
2147
2148 status = sky2_read32(hw, B0_Y2_SP_LISR);
2149 return 0;
2150 }
2151
2152 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2153 {
2154 struct sky2_hw *hw = dev_id;
2155 struct net_device *dev0 = hw->dev[0];
2156 u32 status;
2157
2158 /* Reading this mask interrupts as side effect */
2159 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2160 if (status == 0 || status == ~0)
2161 return IRQ_NONE;
2162
2163 prefetch(&hw->st_le[hw->st_idx]);
2164 if (likely(__netif_rx_schedule_prep(dev0)))
2165 __netif_rx_schedule(dev0);
2166
2167 return IRQ_HANDLED;
2168 }
2169
2170 #ifdef CONFIG_NET_POLL_CONTROLLER
2171 static void sky2_netpoll(struct net_device *dev)
2172 {
2173 struct sky2_port *sky2 = netdev_priv(dev);
2174
2175 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2176 }
2177 #endif
2178
2179 /* Chip internal frequency for clock calculations */
2180 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2181 {
2182 switch (hw->chip_id) {
2183 case CHIP_ID_YUKON_EC:
2184 case CHIP_ID_YUKON_EC_U:
2185 return 125; /* 125 Mhz */
2186 case CHIP_ID_YUKON_FE:
2187 return 100; /* 100 Mhz */
2188 default: /* YUKON_XL */
2189 return 156; /* 156 Mhz */
2190 }
2191 }
2192
2193 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2194 {
2195 return sky2_mhz(hw) * us;
2196 }
2197
2198 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2199 {
2200 return clk / sky2_mhz(hw);
2201 }
2202
2203
2204 static int __devinit sky2_reset(struct sky2_hw *hw)
2205 {
2206 u16 status;
2207 u8 t8, pmd_type;
2208 int i;
2209
2210 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2211
2212 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2213 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2214 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2215 pci_name(hw->pdev), hw->chip_id);
2216 return -EOPNOTSUPP;
2217 }
2218
2219 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2220
2221 /* This rev is really old, and requires untested workarounds */
2222 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2223 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2224 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2225 hw->chip_id, hw->chip_rev);
2226 return -EOPNOTSUPP;
2227 }
2228
2229 /* This chip is new and not tested yet */
2230 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
2231 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2232 pci_name(hw->pdev));
2233 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2234 }
2235
2236 /* disable ASF */
2237 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2238 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2239 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2240 }
2241
2242 /* do a SW reset */
2243 sky2_write8(hw, B0_CTST, CS_RST_SET);
2244 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2245
2246 /* clear PCI errors, if any */
2247 status = sky2_pci_read16(hw, PCI_STATUS);
2248
2249 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2250 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2251
2252
2253 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2254
2255 /* clear any PEX errors */
2256 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2257 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2258
2259
2260 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2261 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2262
2263 hw->ports = 1;
2264 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2265 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2266 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2267 ++hw->ports;
2268 }
2269
2270 sky2_set_power_state(hw, PCI_D0);
2271
2272 for (i = 0; i < hw->ports; i++) {
2273 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2274 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2275 }
2276
2277 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2278
2279 /* Clear I2C IRQ noise */
2280 sky2_write32(hw, B2_I2C_IRQ, 1);
2281
2282 /* turn off hardware timer (unused) */
2283 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2284 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2285
2286 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2287
2288 /* Turn off descriptor polling */
2289 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2290
2291 /* Turn off receive timestamp */
2292 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2293 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2294
2295 /* enable the Tx Arbiters */
2296 for (i = 0; i < hw->ports; i++)
2297 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2298
2299 /* Initialize ram interface */
2300 for (i = 0; i < hw->ports; i++) {
2301 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2302
2303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2304 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2305 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2306 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2307 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2308 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2309 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2310 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2311 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2312 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2313 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2314 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2315 }
2316
2317 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2318
2319 for (i = 0; i < hw->ports; i++)
2320 sky2_phy_reset(hw, i);
2321
2322 memset(hw->st_le, 0, STATUS_LE_BYTES);
2323 hw->st_idx = 0;
2324
2325 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2326 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2327
2328 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2329 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2330
2331 /* Set the list last index */
2332 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2333
2334 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2335 sky2_write8(hw, STAT_FIFO_WM, 16);
2336
2337 /* set Status-FIFO ISR watermark */
2338 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2339 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2340 else
2341 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2342
2343 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2344 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2345 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2346
2347 /* enable status unit */
2348 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2349
2350 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2351 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2352 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2353
2354 return 0;
2355 }
2356
2357 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2358 {
2359 u32 modes;
2360 if (hw->copper) {
2361 modes = SUPPORTED_10baseT_Half
2362 | SUPPORTED_10baseT_Full
2363 | SUPPORTED_100baseT_Half
2364 | SUPPORTED_100baseT_Full
2365 | SUPPORTED_Autoneg | SUPPORTED_TP;
2366
2367 if (hw->chip_id != CHIP_ID_YUKON_FE)
2368 modes |= SUPPORTED_1000baseT_Half
2369 | SUPPORTED_1000baseT_Full;
2370 } else
2371 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2372 | SUPPORTED_Autoneg;
2373 return modes;
2374 }
2375
2376 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2377 {
2378 struct sky2_port *sky2 = netdev_priv(dev);
2379 struct sky2_hw *hw = sky2->hw;
2380
2381 ecmd->transceiver = XCVR_INTERNAL;
2382 ecmd->supported = sky2_supported_modes(hw);
2383 ecmd->phy_address = PHY_ADDR_MARV;
2384 if (hw->copper) {
2385 ecmd->supported = SUPPORTED_10baseT_Half
2386 | SUPPORTED_10baseT_Full
2387 | SUPPORTED_100baseT_Half
2388 | SUPPORTED_100baseT_Full
2389 | SUPPORTED_1000baseT_Half
2390 | SUPPORTED_1000baseT_Full
2391 | SUPPORTED_Autoneg | SUPPORTED_TP;
2392 ecmd->port = PORT_TP;
2393 } else
2394 ecmd->port = PORT_FIBRE;
2395
2396 ecmd->advertising = sky2->advertising;
2397 ecmd->autoneg = sky2->autoneg;
2398 ecmd->speed = sky2->speed;
2399 ecmd->duplex = sky2->duplex;
2400 return 0;
2401 }
2402
2403 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2404 {
2405 struct sky2_port *sky2 = netdev_priv(dev);
2406 const struct sky2_hw *hw = sky2->hw;
2407 u32 supported = sky2_supported_modes(hw);
2408
2409 if (ecmd->autoneg == AUTONEG_ENABLE) {
2410 ecmd->advertising = supported;
2411 sky2->duplex = -1;
2412 sky2->speed = -1;
2413 } else {
2414 u32 setting;
2415
2416 switch (ecmd->speed) {
2417 case SPEED_1000:
2418 if (ecmd->duplex == DUPLEX_FULL)
2419 setting = SUPPORTED_1000baseT_Full;
2420 else if (ecmd->duplex == DUPLEX_HALF)
2421 setting = SUPPORTED_1000baseT_Half;
2422 else
2423 return -EINVAL;
2424 break;
2425 case SPEED_100:
2426 if (ecmd->duplex == DUPLEX_FULL)
2427 setting = SUPPORTED_100baseT_Full;
2428 else if (ecmd->duplex == DUPLEX_HALF)
2429 setting = SUPPORTED_100baseT_Half;
2430 else
2431 return -EINVAL;
2432 break;
2433
2434 case SPEED_10:
2435 if (ecmd->duplex == DUPLEX_FULL)
2436 setting = SUPPORTED_10baseT_Full;
2437 else if (ecmd->duplex == DUPLEX_HALF)
2438 setting = SUPPORTED_10baseT_Half;
2439 else
2440 return -EINVAL;
2441 break;
2442 default:
2443 return -EINVAL;
2444 }
2445
2446 if ((setting & supported) == 0)
2447 return -EINVAL;
2448
2449 sky2->speed = ecmd->speed;
2450 sky2->duplex = ecmd->duplex;
2451 }
2452
2453 sky2->autoneg = ecmd->autoneg;
2454 sky2->advertising = ecmd->advertising;
2455
2456 if (netif_running(dev))
2457 sky2_phy_reinit(sky2);
2458
2459 return 0;
2460 }
2461
2462 static void sky2_get_drvinfo(struct net_device *dev,
2463 struct ethtool_drvinfo *info)
2464 {
2465 struct sky2_port *sky2 = netdev_priv(dev);
2466
2467 strcpy(info->driver, DRV_NAME);
2468 strcpy(info->version, DRV_VERSION);
2469 strcpy(info->fw_version, "N/A");
2470 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2471 }
2472
2473 static const struct sky2_stat {
2474 char name[ETH_GSTRING_LEN];
2475 u16 offset;
2476 } sky2_stats[] = {
2477 { "tx_bytes", GM_TXO_OK_HI },
2478 { "rx_bytes", GM_RXO_OK_HI },
2479 { "tx_broadcast", GM_TXF_BC_OK },
2480 { "rx_broadcast", GM_RXF_BC_OK },
2481 { "tx_multicast", GM_TXF_MC_OK },
2482 { "rx_multicast", GM_RXF_MC_OK },
2483 { "tx_unicast", GM_TXF_UC_OK },
2484 { "rx_unicast", GM_RXF_UC_OK },
2485 { "tx_mac_pause", GM_TXF_MPAUSE },
2486 { "rx_mac_pause", GM_RXF_MPAUSE },
2487 { "collisions", GM_TXF_COL },
2488 { "late_collision",GM_TXF_LAT_COL },
2489 { "aborted", GM_TXF_ABO_COL },
2490 { "single_collisions", GM_TXF_SNG_COL },
2491 { "multi_collisions", GM_TXF_MUL_COL },
2492
2493 { "rx_short", GM_RXF_SHT },
2494 { "rx_runt", GM_RXE_FRAG },
2495 { "rx_64_byte_packets", GM_RXF_64B },
2496 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2497 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2498 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2499 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2500 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2501 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2502 { "rx_too_long", GM_RXF_LNG_ERR },
2503 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2504 { "rx_jabber", GM_RXF_JAB_PKT },
2505 { "rx_fcs_error", GM_RXF_FCS_ERR },
2506
2507 { "tx_64_byte_packets", GM_TXF_64B },
2508 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2509 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2510 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2511 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2512 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2513 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2514 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2515 };
2516
2517 static u32 sky2_get_rx_csum(struct net_device *dev)
2518 {
2519 struct sky2_port *sky2 = netdev_priv(dev);
2520
2521 return sky2->rx_csum;
2522 }
2523
2524 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2525 {
2526 struct sky2_port *sky2 = netdev_priv(dev);
2527
2528 sky2->rx_csum = data;
2529
2530 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2531 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2532
2533 return 0;
2534 }
2535
2536 static u32 sky2_get_msglevel(struct net_device *netdev)
2537 {
2538 struct sky2_port *sky2 = netdev_priv(netdev);
2539 return sky2->msg_enable;
2540 }
2541
2542 static int sky2_nway_reset(struct net_device *dev)
2543 {
2544 struct sky2_port *sky2 = netdev_priv(dev);
2545
2546 if (sky2->autoneg != AUTONEG_ENABLE)
2547 return -EINVAL;
2548
2549 sky2_phy_reinit(sky2);
2550
2551 return 0;
2552 }
2553
2554 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2555 {
2556 struct sky2_hw *hw = sky2->hw;
2557 unsigned port = sky2->port;
2558 int i;
2559
2560 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2561 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2562 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2563 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2564
2565 for (i = 2; i < count; i++)
2566 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2567 }
2568
2569 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2570 {
2571 struct sky2_port *sky2 = netdev_priv(netdev);
2572 sky2->msg_enable = value;
2573 }
2574
2575 static int sky2_get_stats_count(struct net_device *dev)
2576 {
2577 return ARRAY_SIZE(sky2_stats);
2578 }
2579
2580 static void sky2_get_ethtool_stats(struct net_device *dev,
2581 struct ethtool_stats *stats, u64 * data)
2582 {
2583 struct sky2_port *sky2 = netdev_priv(dev);
2584
2585 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2586 }
2587
2588 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2589 {
2590 int i;
2591
2592 switch (stringset) {
2593 case ETH_SS_STATS:
2594 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2595 memcpy(data + i * ETH_GSTRING_LEN,
2596 sky2_stats[i].name, ETH_GSTRING_LEN);
2597 break;
2598 }
2599 }
2600
2601 /* Use hardware MIB variables for critical path statistics and
2602 * transmit feedback not reported at interrupt.
2603 * Other errors are accounted for in interrupt handler.
2604 */
2605 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2606 {
2607 struct sky2_port *sky2 = netdev_priv(dev);
2608 u64 data[13];
2609
2610 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2611
2612 sky2->net_stats.tx_bytes = data[0];
2613 sky2->net_stats.rx_bytes = data[1];
2614 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2615 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2616 sky2->net_stats.multicast = data[3] + data[5];
2617 sky2->net_stats.collisions = data[10];
2618 sky2->net_stats.tx_aborted_errors = data[12];
2619
2620 return &sky2->net_stats;
2621 }
2622
2623 static int sky2_set_mac_address(struct net_device *dev, void *p)
2624 {
2625 struct sky2_port *sky2 = netdev_priv(dev);
2626 struct sky2_hw *hw = sky2->hw;
2627 unsigned port = sky2->port;
2628 const struct sockaddr *addr = p;
2629
2630 if (!is_valid_ether_addr(addr->sa_data))
2631 return -EADDRNOTAVAIL;
2632
2633 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2634 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2635 dev->dev_addr, ETH_ALEN);
2636 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2637 dev->dev_addr, ETH_ALEN);
2638
2639 /* virtual address for data */
2640 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2641
2642 /* physical address: used for pause frames */
2643 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2644
2645 return 0;
2646 }
2647
2648 static void sky2_set_multicast(struct net_device *dev)
2649 {
2650 struct sky2_port *sky2 = netdev_priv(dev);
2651 struct sky2_hw *hw = sky2->hw;
2652 unsigned port = sky2->port;
2653 struct dev_mc_list *list = dev->mc_list;
2654 u16 reg;
2655 u8 filter[8];
2656
2657 memset(filter, 0, sizeof(filter));
2658
2659 reg = gma_read16(hw, port, GM_RX_CTRL);
2660 reg |= GM_RXCR_UCF_ENA;
2661
2662 if (dev->flags & IFF_PROMISC) /* promiscuous */
2663 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2664 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2665 memset(filter, 0xff, sizeof(filter));
2666 else if (dev->mc_count == 0) /* no multicast */
2667 reg &= ~GM_RXCR_MCF_ENA;
2668 else {
2669 int i;
2670 reg |= GM_RXCR_MCF_ENA;
2671
2672 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2673 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2674 filter[bit / 8] |= 1 << (bit % 8);
2675 }
2676 }
2677
2678 gma_write16(hw, port, GM_MC_ADDR_H1,
2679 (u16) filter[0] | ((u16) filter[1] << 8));
2680 gma_write16(hw, port, GM_MC_ADDR_H2,
2681 (u16) filter[2] | ((u16) filter[3] << 8));
2682 gma_write16(hw, port, GM_MC_ADDR_H3,
2683 (u16) filter[4] | ((u16) filter[5] << 8));
2684 gma_write16(hw, port, GM_MC_ADDR_H4,
2685 (u16) filter[6] | ((u16) filter[7] << 8));
2686
2687 gma_write16(hw, port, GM_RX_CTRL, reg);
2688 }
2689
2690 /* Can have one global because blinking is controlled by
2691 * ethtool and that is always under RTNL mutex
2692 */
2693 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2694 {
2695 u16 pg;
2696
2697 switch (hw->chip_id) {
2698 case CHIP_ID_YUKON_XL:
2699 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2700 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2701 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2702 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2703 PHY_M_LEDC_INIT_CTRL(7) |
2704 PHY_M_LEDC_STA1_CTRL(7) |
2705 PHY_M_LEDC_STA0_CTRL(7))
2706 : 0);
2707
2708 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2709 break;
2710
2711 default:
2712 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2713 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2714 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2715 PHY_M_LED_MO_10(MO_LED_ON) |
2716 PHY_M_LED_MO_100(MO_LED_ON) |
2717 PHY_M_LED_MO_1000(MO_LED_ON) |
2718 PHY_M_LED_MO_RX(MO_LED_ON)
2719 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2720 PHY_M_LED_MO_10(MO_LED_OFF) |
2721 PHY_M_LED_MO_100(MO_LED_OFF) |
2722 PHY_M_LED_MO_1000(MO_LED_OFF) |
2723 PHY_M_LED_MO_RX(MO_LED_OFF));
2724
2725 }
2726 }
2727
2728 /* blink LED's for finding board */
2729 static int sky2_phys_id(struct net_device *dev, u32 data)
2730 {
2731 struct sky2_port *sky2 = netdev_priv(dev);
2732 struct sky2_hw *hw = sky2->hw;
2733 unsigned port = sky2->port;
2734 u16 ledctrl, ledover = 0;
2735 long ms;
2736 int interrupted;
2737 int onoff = 1;
2738
2739 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2740 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2741 else
2742 ms = data * 1000;
2743
2744 /* save initial values */
2745 spin_lock_bh(&sky2->phy_lock);
2746 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2747 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2748 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2749 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2750 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2751 } else {
2752 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2753 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2754 }
2755
2756 interrupted = 0;
2757 while (!interrupted && ms > 0) {
2758 sky2_led(hw, port, onoff);
2759 onoff = !onoff;
2760
2761 spin_unlock_bh(&sky2->phy_lock);
2762 interrupted = msleep_interruptible(250);
2763 spin_lock_bh(&sky2->phy_lock);
2764
2765 ms -= 250;
2766 }
2767
2768 /* resume regularly scheduled programming */
2769 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2770 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2771 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2772 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2773 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2774 } else {
2775 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2776 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2777 }
2778 spin_unlock_bh(&sky2->phy_lock);
2779
2780 return 0;
2781 }
2782
2783 static void sky2_get_pauseparam(struct net_device *dev,
2784 struct ethtool_pauseparam *ecmd)
2785 {
2786 struct sky2_port *sky2 = netdev_priv(dev);
2787
2788 ecmd->tx_pause = sky2->tx_pause;
2789 ecmd->rx_pause = sky2->rx_pause;
2790 ecmd->autoneg = sky2->autoneg;
2791 }
2792
2793 static int sky2_set_pauseparam(struct net_device *dev,
2794 struct ethtool_pauseparam *ecmd)
2795 {
2796 struct sky2_port *sky2 = netdev_priv(dev);
2797 int err = 0;
2798
2799 sky2->autoneg = ecmd->autoneg;
2800 sky2->tx_pause = ecmd->tx_pause != 0;
2801 sky2->rx_pause = ecmd->rx_pause != 0;
2802
2803 sky2_phy_reinit(sky2);
2804
2805 return err;
2806 }
2807
2808 static int sky2_get_coalesce(struct net_device *dev,
2809 struct ethtool_coalesce *ecmd)
2810 {
2811 struct sky2_port *sky2 = netdev_priv(dev);
2812 struct sky2_hw *hw = sky2->hw;
2813
2814 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2815 ecmd->tx_coalesce_usecs = 0;
2816 else {
2817 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2818 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2819 }
2820 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2821
2822 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2823 ecmd->rx_coalesce_usecs = 0;
2824 else {
2825 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2826 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2827 }
2828 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2829
2830 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2831 ecmd->rx_coalesce_usecs_irq = 0;
2832 else {
2833 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2834 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2835 }
2836
2837 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2838
2839 return 0;
2840 }
2841
2842 /* Note: this affect both ports */
2843 static int sky2_set_coalesce(struct net_device *dev,
2844 struct ethtool_coalesce *ecmd)
2845 {
2846 struct sky2_port *sky2 = netdev_priv(dev);
2847 struct sky2_hw *hw = sky2->hw;
2848 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2849
2850 if (ecmd->tx_coalesce_usecs > tmax ||
2851 ecmd->rx_coalesce_usecs > tmax ||
2852 ecmd->rx_coalesce_usecs_irq > tmax)
2853 return -EINVAL;
2854
2855 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2856 return -EINVAL;
2857 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2858 return -EINVAL;
2859 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2860 return -EINVAL;
2861
2862 if (ecmd->tx_coalesce_usecs == 0)
2863 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2864 else {
2865 sky2_write32(hw, STAT_TX_TIMER_INI,
2866 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2867 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2868 }
2869 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2870
2871 if (ecmd->rx_coalesce_usecs == 0)
2872 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2873 else {
2874 sky2_write32(hw, STAT_LEV_TIMER_INI,
2875 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2876 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2877 }
2878 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2879
2880 if (ecmd->rx_coalesce_usecs_irq == 0)
2881 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2882 else {
2883 sky2_write32(hw, STAT_ISR_TIMER_INI,
2884 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2885 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2886 }
2887 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2888 return 0;
2889 }
2890
2891 static void sky2_get_ringparam(struct net_device *dev,
2892 struct ethtool_ringparam *ering)
2893 {
2894 struct sky2_port *sky2 = netdev_priv(dev);
2895
2896 ering->rx_max_pending = RX_MAX_PENDING;
2897 ering->rx_mini_max_pending = 0;
2898 ering->rx_jumbo_max_pending = 0;
2899 ering->tx_max_pending = TX_RING_SIZE - 1;
2900
2901 ering->rx_pending = sky2->rx_pending;
2902 ering->rx_mini_pending = 0;
2903 ering->rx_jumbo_pending = 0;
2904 ering->tx_pending = sky2->tx_pending;
2905 }
2906
2907 static int sky2_set_ringparam(struct net_device *dev,
2908 struct ethtool_ringparam *ering)
2909 {
2910 struct sky2_port *sky2 = netdev_priv(dev);
2911 int err = 0;
2912
2913 if (ering->rx_pending > RX_MAX_PENDING ||
2914 ering->rx_pending < 8 ||
2915 ering->tx_pending < MAX_SKB_TX_LE ||
2916 ering->tx_pending > TX_RING_SIZE - 1)
2917 return -EINVAL;
2918
2919 if (netif_running(dev))
2920 sky2_down(dev);
2921
2922 sky2->rx_pending = ering->rx_pending;
2923 sky2->tx_pending = ering->tx_pending;
2924
2925 if (netif_running(dev)) {
2926 err = sky2_up(dev);
2927 if (err)
2928 dev_close(dev);
2929 else
2930 sky2_set_multicast(dev);
2931 }
2932
2933 return err;
2934 }
2935
2936 static int sky2_get_regs_len(struct net_device *dev)
2937 {
2938 return 0x4000;
2939 }
2940
2941 /*
2942 * Returns copy of control register region
2943 * Note: access to the RAM address register set will cause timeouts.
2944 */
2945 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2946 void *p)
2947 {
2948 const struct sky2_port *sky2 = netdev_priv(dev);
2949 const void __iomem *io = sky2->hw->regs;
2950
2951 BUG_ON(regs->len < B3_RI_WTO_R1);
2952 regs->version = 1;
2953 memset(p, 0, regs->len);
2954
2955 memcpy_fromio(p, io, B3_RAM_ADDR);
2956
2957 memcpy_fromio(p + B3_RI_WTO_R1,
2958 io + B3_RI_WTO_R1,
2959 regs->len - B3_RI_WTO_R1);
2960 }
2961
2962 static struct ethtool_ops sky2_ethtool_ops = {
2963 .get_settings = sky2_get_settings,
2964 .set_settings = sky2_set_settings,
2965 .get_drvinfo = sky2_get_drvinfo,
2966 .get_msglevel = sky2_get_msglevel,
2967 .set_msglevel = sky2_set_msglevel,
2968 .nway_reset = sky2_nway_reset,
2969 .get_regs_len = sky2_get_regs_len,
2970 .get_regs = sky2_get_regs,
2971 .get_link = ethtool_op_get_link,
2972 .get_sg = ethtool_op_get_sg,
2973 .set_sg = ethtool_op_set_sg,
2974 .get_tx_csum = ethtool_op_get_tx_csum,
2975 .set_tx_csum = ethtool_op_set_tx_csum,
2976 .get_tso = ethtool_op_get_tso,
2977 .set_tso = ethtool_op_set_tso,
2978 .get_rx_csum = sky2_get_rx_csum,
2979 .set_rx_csum = sky2_set_rx_csum,
2980 .get_strings = sky2_get_strings,
2981 .get_coalesce = sky2_get_coalesce,
2982 .set_coalesce = sky2_set_coalesce,
2983 .get_ringparam = sky2_get_ringparam,
2984 .set_ringparam = sky2_set_ringparam,
2985 .get_pauseparam = sky2_get_pauseparam,
2986 .set_pauseparam = sky2_set_pauseparam,
2987 .phys_id = sky2_phys_id,
2988 .get_stats_count = sky2_get_stats_count,
2989 .get_ethtool_stats = sky2_get_ethtool_stats,
2990 .get_perm_addr = ethtool_op_get_perm_addr,
2991 };
2992
2993 /* Initialize network device */
2994 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2995 unsigned port, int highmem)
2996 {
2997 struct sky2_port *sky2;
2998 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2999
3000 if (!dev) {
3001 printk(KERN_ERR "sky2 etherdev alloc failed");
3002 return NULL;
3003 }
3004
3005 SET_MODULE_OWNER(dev);
3006 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3007 dev->irq = hw->pdev->irq;
3008 dev->open = sky2_up;
3009 dev->stop = sky2_down;
3010 dev->do_ioctl = sky2_ioctl;
3011 dev->hard_start_xmit = sky2_xmit_frame;
3012 dev->get_stats = sky2_get_stats;
3013 dev->set_multicast_list = sky2_set_multicast;
3014 dev->set_mac_address = sky2_set_mac_address;
3015 dev->change_mtu = sky2_change_mtu;
3016 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3017 dev->tx_timeout = sky2_tx_timeout;
3018 dev->watchdog_timeo = TX_WATCHDOG;
3019 if (port == 0)
3020 dev->poll = sky2_poll;
3021 dev->weight = NAPI_WEIGHT;
3022 #ifdef CONFIG_NET_POLL_CONTROLLER
3023 dev->poll_controller = sky2_netpoll;
3024 #endif
3025
3026 sky2 = netdev_priv(dev);
3027 sky2->netdev = dev;
3028 sky2->hw = hw;
3029 sky2->msg_enable = netif_msg_init(debug, default_msg);
3030
3031 spin_lock_init(&sky2->tx_lock);
3032 /* Auto speed and flow control */
3033 sky2->autoneg = AUTONEG_ENABLE;
3034 sky2->tx_pause = 1;
3035 sky2->rx_pause = 1;
3036 sky2->duplex = -1;
3037 sky2->speed = -1;
3038 sky2->advertising = sky2_supported_modes(hw);
3039
3040 /* Receive checksum disabled for Yukon XL
3041 * because of observed problems with incorrect
3042 * values when multiple packets are received in one interrupt
3043 */
3044 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3045
3046 spin_lock_init(&sky2->phy_lock);
3047 sky2->tx_pending = TX_DEF_PENDING;
3048 sky2->rx_pending = RX_DEF_PENDING;
3049 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3050
3051 hw->dev[port] = dev;
3052
3053 sky2->port = port;
3054
3055 dev->features |= NETIF_F_LLTX;
3056 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3057 dev->features |= NETIF_F_TSO;
3058 if (highmem)
3059 dev->features |= NETIF_F_HIGHDMA;
3060 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3061
3062 #ifdef SKY2_VLAN_TAG_USED
3063 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3064 dev->vlan_rx_register = sky2_vlan_rx_register;
3065 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3066 #endif
3067
3068 /* read the mac address */
3069 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3070 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3071
3072 /* device is off until link detection */
3073 netif_carrier_off(dev);
3074 netif_stop_queue(dev);
3075
3076 return dev;
3077 }
3078
3079 static void __devinit sky2_show_addr(struct net_device *dev)
3080 {
3081 const struct sky2_port *sky2 = netdev_priv(dev);
3082
3083 if (netif_msg_probe(sky2))
3084 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3085 dev->name,
3086 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3087 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3088 }
3089
3090 /* Handle software interrupt used during MSI test */
3091 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3092 struct pt_regs *regs)
3093 {
3094 struct sky2_hw *hw = dev_id;
3095 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3096
3097 if (status == 0)
3098 return IRQ_NONE;
3099
3100 if (status & Y2_IS_IRQ_SW) {
3101 hw->msi_detected = 1;
3102 wake_up(&hw->msi_wait);
3103 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3104 }
3105 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3106
3107 return IRQ_HANDLED;
3108 }
3109
3110 /* Test interrupt path by forcing a a software IRQ */
3111 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3112 {
3113 struct pci_dev *pdev = hw->pdev;
3114 int err;
3115
3116 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3117
3118 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3119 if (err) {
3120 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3121 pci_name(pdev), pdev->irq);
3122 return err;
3123 }
3124
3125 init_waitqueue_head (&hw->msi_wait);
3126
3127 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3128 wmb();
3129
3130 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3131
3132 if (!hw->msi_detected) {
3133 /* MSI test failed, go back to INTx mode */
3134 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3135 "switching to INTx mode. Please report this failure to "
3136 "the PCI maintainer and include system chipset information.\n",
3137 pci_name(pdev));
3138
3139 err = -EOPNOTSUPP;
3140 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3141 }
3142
3143 sky2_write32(hw, B0_IMSK, 0);
3144
3145 free_irq(pdev->irq, hw);
3146
3147 return err;
3148 }
3149
3150 static int __devinit sky2_probe(struct pci_dev *pdev,
3151 const struct pci_device_id *ent)
3152 {
3153 struct net_device *dev, *dev1 = NULL;
3154 struct sky2_hw *hw;
3155 int err, pm_cap, using_dac = 0;
3156
3157 err = pci_enable_device(pdev);
3158 if (err) {
3159 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3160 pci_name(pdev));
3161 goto err_out;
3162 }
3163
3164 err = pci_request_regions(pdev, DRV_NAME);
3165 if (err) {
3166 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3167 pci_name(pdev));
3168 goto err_out;
3169 }
3170
3171 pci_set_master(pdev);
3172
3173 /* Find power-management capability. */
3174 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3175 if (pm_cap == 0) {
3176 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3177 "aborting.\n");
3178 err = -EIO;
3179 goto err_out_free_regions;
3180 }
3181
3182 if (sizeof(dma_addr_t) > sizeof(u32) &&
3183 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3184 using_dac = 1;
3185 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3186 if (err < 0) {
3187 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3188 "for consistent allocations\n", pci_name(pdev));
3189 goto err_out_free_regions;
3190 }
3191
3192 } else {
3193 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3194 if (err) {
3195 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3196 pci_name(pdev));
3197 goto err_out_free_regions;
3198 }
3199 }
3200
3201 err = -ENOMEM;
3202 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3203 if (!hw) {
3204 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3205 pci_name(pdev));
3206 goto err_out_free_regions;
3207 }
3208
3209 hw->pdev = pdev;
3210
3211 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3212 if (!hw->regs) {
3213 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3214 pci_name(pdev));
3215 goto err_out_free_hw;
3216 }
3217 hw->pm_cap = pm_cap;
3218
3219 #ifdef __BIG_ENDIAN
3220 /* byte swap descriptors in hardware */
3221 {
3222 u32 reg;
3223
3224 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3225 reg |= PCI_REV_DESC;
3226 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3227 }
3228 #endif
3229
3230 /* ring for status responses */
3231 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3232 &hw->st_dma);
3233 if (!hw->st_le)
3234 goto err_out_iounmap;
3235
3236 err = sky2_reset(hw);
3237 if (err)
3238 goto err_out_iounmap;
3239
3240 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3241 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3242 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3243 hw->chip_id, hw->chip_rev);
3244
3245 dev = sky2_init_netdev(hw, 0, using_dac);
3246 if (!dev)
3247 goto err_out_free_pci;
3248
3249 err = register_netdev(dev);
3250 if (err) {
3251 printk(KERN_ERR PFX "%s: cannot register net device\n",
3252 pci_name(pdev));
3253 goto err_out_free_netdev;
3254 }
3255
3256 sky2_show_addr(dev);
3257
3258 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3259 if (register_netdev(dev1) == 0)
3260 sky2_show_addr(dev1);
3261 else {
3262 /* Failure to register second port need not be fatal */
3263 printk(KERN_WARNING PFX
3264 "register of second port failed\n");
3265 hw->dev[1] = NULL;
3266 free_netdev(dev1);
3267 }
3268 }
3269
3270 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3271 err = sky2_test_msi(hw);
3272 if (err == -EOPNOTSUPP)
3273 pci_disable_msi(pdev);
3274 else if (err)
3275 goto err_out_unregister;
3276 }
3277
3278 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3279 if (err) {
3280 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3281 pci_name(pdev), pdev->irq);
3282 goto err_out_unregister;
3283 }
3284
3285 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3286
3287 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3288 if (idle_timeout > 0)
3289 mod_timer(&hw->idle_timer,
3290 jiffies + msecs_to_jiffies(idle_timeout));
3291
3292 pci_set_drvdata(pdev, hw);
3293
3294 return 0;
3295
3296 err_out_unregister:
3297 pci_disable_msi(pdev);
3298 if (dev1) {
3299 unregister_netdev(dev1);
3300 free_netdev(dev1);
3301 }
3302 unregister_netdev(dev);
3303 err_out_free_netdev:
3304 free_netdev(dev);
3305 err_out_free_pci:
3306 sky2_write8(hw, B0_CTST, CS_RST_SET);
3307 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3308 err_out_iounmap:
3309 iounmap(hw->regs);
3310 err_out_free_hw:
3311 kfree(hw);
3312 err_out_free_regions:
3313 pci_release_regions(pdev);
3314 pci_disable_device(pdev);
3315 err_out:
3316 return err;
3317 }
3318
3319 static void __devexit sky2_remove(struct pci_dev *pdev)
3320 {
3321 struct sky2_hw *hw = pci_get_drvdata(pdev);
3322 struct net_device *dev0, *dev1;
3323
3324 if (!hw)
3325 return;
3326
3327 del_timer_sync(&hw->idle_timer);
3328
3329 sky2_write32(hw, B0_IMSK, 0);
3330 dev0 = hw->dev[0];
3331 dev1 = hw->dev[1];
3332 if (dev1)
3333 unregister_netdev(dev1);
3334 unregister_netdev(dev0);
3335
3336 sky2_set_power_state(hw, PCI_D3hot);
3337 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3338 sky2_write8(hw, B0_CTST, CS_RST_SET);
3339 sky2_read8(hw, B0_CTST);
3340
3341 free_irq(pdev->irq, hw);
3342 pci_disable_msi(pdev);
3343 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3344 pci_release_regions(pdev);
3345 pci_disable_device(pdev);
3346
3347 if (dev1)
3348 free_netdev(dev1);
3349 free_netdev(dev0);
3350 iounmap(hw->regs);
3351 kfree(hw);
3352
3353 pci_set_drvdata(pdev, NULL);
3354 }
3355
3356 #ifdef CONFIG_PM
3357 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3358 {
3359 struct sky2_hw *hw = pci_get_drvdata(pdev);
3360 int i;
3361
3362 for (i = 0; i < 2; i++) {
3363 struct net_device *dev = hw->dev[i];
3364
3365 if (dev) {
3366 if (!netif_running(dev))
3367 continue;
3368
3369 sky2_down(dev);
3370 netif_device_detach(dev);
3371 }
3372 }
3373
3374 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3375 }
3376
3377 static int sky2_resume(struct pci_dev *pdev)
3378 {
3379 struct sky2_hw *hw = pci_get_drvdata(pdev);
3380 int i, err;
3381
3382 pci_restore_state(pdev);
3383 pci_enable_wake(pdev, PCI_D0, 0);
3384 err = sky2_set_power_state(hw, PCI_D0);
3385 if (err)
3386 goto out;
3387
3388 err = sky2_reset(hw);
3389 if (err)
3390 goto out;
3391
3392 for (i = 0; i < 2; i++) {
3393 struct net_device *dev = hw->dev[i];
3394 if (dev && netif_running(dev)) {
3395 netif_device_attach(dev);
3396 err = sky2_up(dev);
3397 if (err) {
3398 printk(KERN_ERR PFX "%s: could not up: %d\n",
3399 dev->name, err);
3400 dev_close(dev);
3401 break;
3402 }
3403 }
3404 }
3405 out:
3406 return err;
3407 }
3408 #endif
3409
3410 static struct pci_driver sky2_driver = {
3411 .name = DRV_NAME,
3412 .id_table = sky2_id_table,
3413 .probe = sky2_probe,
3414 .remove = __devexit_p(sky2_remove),
3415 #ifdef CONFIG_PM
3416 .suspend = sky2_suspend,
3417 .resume = sky2_resume,
3418 #endif
3419 };
3420
3421 static int __init sky2_init_module(void)
3422 {
3423 return pci_register_driver(&sky2_driver);
3424 }
3425
3426 static void __exit sky2_cleanup_module(void)
3427 {
3428 pci_unregister_driver(&sky2_driver);
3429 }
3430
3431 module_init(sky2_init_module);
3432 module_exit(sky2_cleanup_module);
3433
3434 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3435 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3436 MODULE_LICENSE("GPL");
3437 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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