2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 static const u32 default_msg
=
83 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
84 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
87 static int debug
= -1; /* defaults above */
88 module_param(debug
, int, 0);
89 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly
= 256;
92 module_param(copybreak
, int, 0);
93 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
95 static int disable_msi
= 0;
96 module_param(disable_msi
, int, 0);
97 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
99 static const struct pci_device_id sky2_id_table
[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) },
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
122 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
124 /* Avoid conditionals by using array */
125 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
126 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
128 /* This driver supports yukon2 chipset only */
129 static const char *yukon2_name
[] = {
131 "EC Ultra", /* 0xb4 */
132 "UNKNOWN", /* 0xb5 */
137 /* Access to external PHY */
138 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
142 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
143 gma_write16(hw
, port
, GM_SMI_CTRL
,
144 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
146 for (i
= 0; i
< PHY_RETRIES
; i
++) {
147 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
152 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
156 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
160 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
161 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
163 for (i
= 0; i
< PHY_RETRIES
; i
++) {
164 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
165 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
175 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
179 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
180 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
184 static int sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
191 pr_debug("sky2_set_power_state %d\n", state
);
192 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
194 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
195 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
196 (power_control
& PCI_PM_CAP_PME_D3cold
);
198 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
200 power_control
|= PCI_PM_CTRL_PME_STATUS
;
201 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw
, B0_POWER_CTRL
,
207 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
209 /* disable Core Clock Division, */
210 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
212 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
213 /* enable bits are inverted */
214 sky2_write8(hw
, B2_Y2_CLK_GATE
,
215 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
216 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
217 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
219 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
221 /* Turn off phy power saving */
222 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
223 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
225 /* looks like this XL is back asswards .. */
226 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
227 reg1
|= PCI_Y2_PHY1_COMA
;
229 reg1
|= PCI_Y2_PHY2_COMA
;
232 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
233 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
234 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
235 reg1
&= P_ASPM_CONTROL_MSK
;
236 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
237 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
240 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
246 /* Turn on phy power saving */
247 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
248 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
249 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
251 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
252 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
254 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
255 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
257 /* enable bits are inverted */
258 sky2_write8(hw
, B2_Y2_CLK_GATE
,
259 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
260 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
261 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
263 /* switch power to VAUX */
264 if (vaux
&& state
!= PCI_D3cold
)
265 sky2_write8(hw
, B0_POWER_CTRL
,
266 (PC_VAUX_ENA
| PC_VCC_ENA
|
267 PC_VAUX_ON
| PC_VCC_OFF
));
270 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
274 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
275 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
279 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
283 /* disable all GMAC IRQ's */
284 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
285 /* disable PHY IRQs */
286 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
288 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
289 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
290 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
291 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
293 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
294 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
295 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
298 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
300 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
301 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
303 if (sky2
->autoneg
== AUTONEG_ENABLE
&& hw
->chip_id
!= CHIP_ID_YUKON_XL
) {
304 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
306 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
308 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
310 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
311 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
313 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
315 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
318 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
320 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
321 /* enable automatic crossover */
322 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
324 /* disable energy detect */
325 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
327 /* enable automatic crossover */
328 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
330 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
331 hw
->chip_id
== CHIP_ID_YUKON_XL
) {
332 ctrl
&= ~PHY_M_PC_DSC_MSK
;
333 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
336 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
338 /* workaround for deviation #4.88 (CRC errors) */
339 /* disable Automatic Crossover */
341 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
342 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
344 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
345 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
346 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
347 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
348 ctrl
&= ~PHY_M_MAC_MD_MSK
;
349 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
350 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
352 /* select page 1 to access Fiber registers */
353 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
357 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
358 if (sky2
->autoneg
== AUTONEG_DISABLE
)
363 ctrl
|= PHY_CT_RESET
;
364 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
370 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
372 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
373 ct1000
|= PHY_M_1000C_AFD
;
374 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
375 ct1000
|= PHY_M_1000C_AHD
;
376 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
377 adv
|= PHY_M_AN_100_FD
;
378 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
379 adv
|= PHY_M_AN_100_HD
;
380 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
381 adv
|= PHY_M_AN_10_FD
;
382 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
383 adv
|= PHY_M_AN_10_HD
;
384 } else /* special defines for FIBER (88E1011S only) */
385 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
387 /* Set Flow-control capabilities */
388 if (sky2
->tx_pause
&& sky2
->rx_pause
)
389 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
390 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
391 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
392 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
393 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
395 /* Restart Auto-negotiation */
396 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
398 /* forced speed/duplex settings */
399 ct1000
= PHY_M_1000C_MSE
;
401 if (sky2
->duplex
== DUPLEX_FULL
)
402 ctrl
|= PHY_CT_DUP_MD
;
404 switch (sky2
->speed
) {
406 ctrl
|= PHY_CT_SP1000
;
409 ctrl
|= PHY_CT_SP100
;
413 ctrl
|= PHY_CT_RESET
;
416 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
417 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
419 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
420 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
422 /* Setup Phy LED's */
423 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
426 switch (hw
->chip_id
) {
427 case CHIP_ID_YUKON_FE
:
428 /* on 88E3082 these bits are at 11..9 (shifted left) */
429 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
431 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
433 /* delete ACT LED control bits */
434 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
435 /* change ACT LED control to blink mode */
436 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
437 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
440 case CHIP_ID_YUKON_XL
:
441 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
443 /* select page 3 to access LED control register */
444 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
446 /* set LED Function Control register */
447 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
448 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
449 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
450 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
452 /* set Polarity Control register */
453 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
454 (PHY_M_POLC_LS1_P_MIX(4) |
455 PHY_M_POLC_IS0_P_MIX(4) |
456 PHY_M_POLC_LOS_CTRL(2) |
457 PHY_M_POLC_INIT_CTRL(2) |
458 PHY_M_POLC_STA1_CTRL(2) |
459 PHY_M_POLC_STA0_CTRL(2)));
461 /* restore page register */
462 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
466 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
467 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
468 /* turn off the Rx LED (LED_RX) */
469 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
472 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
473 /* apply fixes in PHY AFE */
474 gm_phy_write(hw
, port
, 22, 255);
475 /* increase differential signal amplitude in 10BASE-T */
476 gm_phy_write(hw
, port
, 24, 0xaa99);
477 gm_phy_write(hw
, port
, 23, 0x2011);
479 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
480 gm_phy_write(hw
, port
, 24, 0xa204);
481 gm_phy_write(hw
, port
, 23, 0x2002);
483 /* set page register to 0 */
484 gm_phy_write(hw
, port
, 22, 0);
486 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
488 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
489 /* turn on 100 Mbps LED (LED_LINK100) */
490 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
494 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
497 /* Enable phy interrupt on auto-negotiation complete (or link up) */
498 if (sky2
->autoneg
== AUTONEG_ENABLE
)
499 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
501 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
504 /* Force a renegotiation */
505 static void sky2_phy_reinit(struct sky2_port
*sky2
)
507 spin_lock_bh(&sky2
->phy_lock
);
508 sky2_phy_init(sky2
->hw
, sky2
->port
);
509 spin_unlock_bh(&sky2
->phy_lock
);
512 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
514 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
517 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
519 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
520 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
522 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
524 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
525 /* WA DEV_472 -- looks like crossed wires on port 2 */
526 /* clear GMAC 1 Control reset */
527 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
529 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
530 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
531 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
532 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
533 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
536 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
537 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
538 reg
|= GM_GPCR_AU_ALL_DIS
;
539 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
540 gma_read16(hw
, port
, GM_GP_CTRL
);
542 switch (sky2
->speed
) {
544 reg
&= ~GM_GPCR_SPEED_100
;
545 reg
|= GM_GPCR_SPEED_1000
;
548 reg
&= ~GM_GPCR_SPEED_1000
;
549 reg
|= GM_GPCR_SPEED_100
;
552 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
556 if (sky2
->duplex
== DUPLEX_FULL
)
557 reg
|= GM_GPCR_DUP_FULL
;
559 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
561 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
562 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
564 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
565 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
566 /* disable Rx flow-control */
567 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
570 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
572 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
574 spin_lock_bh(&sky2
->phy_lock
);
575 sky2_phy_init(hw
, port
);
576 spin_unlock_bh(&sky2
->phy_lock
);
579 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
580 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
582 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
583 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8 * i
);
584 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
586 /* transmit control */
587 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
589 /* receive control reg: unicast + multicast + no FCS */
590 gma_write16(hw
, port
, GM_RX_CTRL
,
591 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
593 /* transmit flow control */
594 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
596 /* transmit parameter */
597 gma_write16(hw
, port
, GM_TX_PARAM
,
598 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
599 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
600 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
601 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
603 /* serial mode register */
604 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
605 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
607 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
608 reg
|= GM_SMOD_JUMBO_ENA
;
610 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
612 /* virtual address for data */
613 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
615 /* physical address: used for pause frames */
616 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
618 /* ignore counter overflows */
619 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
620 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
621 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
623 /* Configure Rx MAC FIFO */
624 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
625 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
626 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
628 /* Flush Rx MAC FIFO on any flow control or error */
629 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
631 /* Set threshold to 0xa (64 bytes)
632 * ASF disabled so no need to do WA dev #4.30
634 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
636 /* Configure Tx MAC FIFO */
637 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
638 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
640 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
641 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
642 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
643 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
644 /* set Tx GMAC FIFO Almost Empty Threshold */
645 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
646 /* Disable Store & Forward mode for TX */
647 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
653 /* Assign Ram Buffer allocation.
654 * start and end are in units of 4k bytes
655 * ram registers are in units of 64bit words
657 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
661 start
= startk
* 4096/8;
662 end
= (endk
* 4096/8) - 1;
664 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
665 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
666 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
667 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
668 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
670 if (q
== Q_R1
|| q
== Q_R2
) {
671 u32 space
= (endk
- startk
) * 4096/8;
672 u32 tp
= space
- space
/4;
674 /* On receive queue's set the thresholds
675 * give receiver priority when > 3/4 full
676 * send pause when down to 2K
678 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
679 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
682 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
683 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
685 /* Enable store & forward on Tx queue's because
686 * Tx FIFO is only 1K on Yukon
688 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
691 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
692 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
695 /* Setup Bus Memory Interface */
696 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
698 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
699 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
700 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
701 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
704 /* Setup prefetch unit registers. This is the interface between
705 * hardware and driver list elements
707 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
710 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
711 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
712 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
713 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
714 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
715 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
717 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
720 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
722 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
724 sky2
->tx_prod
= (sky2
->tx_prod
+ 1) % TX_RING_SIZE
;
728 /* Update chip's next pointer */
729 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
732 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
737 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
739 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
740 sky2
->rx_put
= (sky2
->rx_put
+ 1) % RX_LE_SIZE
;
744 /* Return high part of DMA address (could be 32 or 64 bit) */
745 static inline u32
high32(dma_addr_t a
)
747 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
750 /* Build description to hardware about buffer */
751 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
753 struct sky2_rx_le
*le
;
754 u32 hi
= high32(map
);
755 u16 len
= sky2
->rx_bufsize
;
757 if (sky2
->rx_addr64
!= hi
) {
758 le
= sky2_next_rx(sky2
);
759 le
->addr
= cpu_to_le32(hi
);
761 le
->opcode
= OP_ADDR64
| HW_OWNER
;
762 sky2
->rx_addr64
= high32(map
+ len
);
765 le
= sky2_next_rx(sky2
);
766 le
->addr
= cpu_to_le32((u32
) map
);
767 le
->length
= cpu_to_le16(len
);
769 le
->opcode
= OP_PACKET
| HW_OWNER
;
773 /* Tell chip where to start receive checksum.
774 * Actually has two checksums, but set both same to avoid possible byte
777 static void rx_set_checksum(struct sky2_port
*sky2
)
779 struct sky2_rx_le
*le
;
781 le
= sky2_next_rx(sky2
);
782 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
784 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
786 sky2_write32(sky2
->hw
,
787 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
788 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
793 * The RX Stop command will not work for Yukon-2 if the BMU does not
794 * reach the end of packet and since we can't make sure that we have
795 * incoming data, we must reset the BMU while it is not doing a DMA
796 * transfer. Since it is possible that the RX path is still active,
797 * the RX RAM buffer will be stopped first, so any possible incoming
798 * data will not trigger a DMA. After the RAM buffer is stopped, the
799 * BMU is polled until any DMA in progress is ended and only then it
802 static void sky2_rx_stop(struct sky2_port
*sky2
)
804 struct sky2_hw
*hw
= sky2
->hw
;
805 unsigned rxq
= rxqaddr
[sky2
->port
];
808 /* disable the RAM Buffer receive queue */
809 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
811 for (i
= 0; i
< 0xffff; i
++)
812 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
813 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
816 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
819 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
821 /* reset the Rx prefetch unit */
822 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
825 /* Clean out receive buffer area, assumes receiver hardware stopped */
826 static void sky2_rx_clean(struct sky2_port
*sky2
)
830 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
831 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
832 struct ring_info
*re
= sky2
->rx_ring
+ i
;
835 pci_unmap_single(sky2
->hw
->pdev
,
836 re
->mapaddr
, sky2
->rx_bufsize
,
844 /* Basic MII support */
845 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
847 struct mii_ioctl_data
*data
= if_mii(ifr
);
848 struct sky2_port
*sky2
= netdev_priv(dev
);
849 struct sky2_hw
*hw
= sky2
->hw
;
850 int err
= -EOPNOTSUPP
;
852 if (!netif_running(dev
))
853 return -ENODEV
; /* Phy still in reset */
857 data
->phy_id
= PHY_ADDR_MARV
;
863 spin_lock_bh(&sky2
->phy_lock
);
864 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
865 spin_unlock_bh(&sky2
->phy_lock
);
872 if (!capable(CAP_NET_ADMIN
))
875 spin_lock_bh(&sky2
->phy_lock
);
876 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
878 spin_unlock_bh(&sky2
->phy_lock
);
884 #ifdef SKY2_VLAN_TAG_USED
885 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
887 struct sky2_port
*sky2
= netdev_priv(dev
);
888 struct sky2_hw
*hw
= sky2
->hw
;
889 u16 port
= sky2
->port
;
891 spin_lock_bh(&sky2
->tx_lock
);
893 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
894 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
897 spin_unlock_bh(&sky2
->tx_lock
);
900 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
902 struct sky2_port
*sky2
= netdev_priv(dev
);
903 struct sky2_hw
*hw
= sky2
->hw
;
904 u16 port
= sky2
->port
;
906 spin_lock_bh(&sky2
->tx_lock
);
908 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
909 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
911 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
913 spin_unlock_bh(&sky2
->tx_lock
);
918 * It appears the hardware has a bug in the FIFO logic that
919 * cause it to hang if the FIFO gets overrun and the receive buffer
920 * is not aligned. ALso alloc_skb() won't align properly if slab
921 * debugging is enabled.
923 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
927 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
929 unsigned long p
= (unsigned long) skb
->data
;
931 ((p
+ RX_SKB_ALIGN
- 1) & ~(RX_SKB_ALIGN
- 1)) - p
);
938 * Allocate and setup receiver buffer pool.
939 * In case of 64 bit dma, there are 2X as many list elements
940 * available as ring entries
941 * and need to reserve one list element so we don't wrap around.
943 static int sky2_rx_start(struct sky2_port
*sky2
)
945 struct sky2_hw
*hw
= sky2
->hw
;
946 unsigned rxq
= rxqaddr
[sky2
->port
];
949 sky2
->rx_put
= sky2
->rx_next
= 0;
952 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
953 /* MAC Rx RAM Read is controlled by hardware */
954 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
957 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
959 rx_set_checksum(sky2
);
960 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
961 struct ring_info
*re
= sky2
->rx_ring
+ i
;
963 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
967 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
968 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
969 sky2_rx_add(sky2
, re
->mapaddr
);
972 /* Truncate oversize frames */
973 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), sky2
->rx_bufsize
- 8);
974 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
976 /* Tell chip about available buffers */
977 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
984 /* Bring up network interface. */
985 static int sky2_up(struct net_device
*dev
)
987 struct sky2_port
*sky2
= netdev_priv(dev
);
988 struct sky2_hw
*hw
= sky2
->hw
;
989 unsigned port
= sky2
->port
;
990 u32 ramsize
, rxspace
, imask
;
993 if (netif_msg_ifup(sky2
))
994 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
996 /* must be power of 2 */
997 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
999 sizeof(struct sky2_tx_le
),
1004 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1008 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1010 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1014 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1016 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1021 sky2_mac_init(hw
, port
);
1023 /* Determine available ram buffer space (in 4K blocks).
1024 * Note: not sure about the FE setting below yet
1026 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1029 ramsize
= sky2_read8(hw
, B2_E_0
);
1031 /* Give transmitter one third (rounded up) */
1032 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1034 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1035 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1037 /* Make sure SyncQ is disabled */
1038 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1041 sky2_qset(hw
, txqaddr
[port
]);
1043 /* Set almost empty threshold */
1044 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1045 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1047 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1050 err
= sky2_rx_start(sky2
);
1054 /* Enable interrupts from phy/mac for port */
1055 imask
= sky2_read32(hw
, B0_IMSK
);
1056 imask
|= (port
== 0) ? Y2_IS_PORT_1
: Y2_IS_PORT_2
;
1057 sky2_write32(hw
, B0_IMSK
, imask
);
1063 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1064 sky2
->rx_le
, sky2
->rx_le_map
);
1068 pci_free_consistent(hw
->pdev
,
1069 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1070 sky2
->tx_le
, sky2
->tx_le_map
);
1073 kfree(sky2
->tx_ring
);
1074 kfree(sky2
->rx_ring
);
1076 sky2
->tx_ring
= NULL
;
1077 sky2
->rx_ring
= NULL
;
1081 /* Modular subtraction in ring */
1082 static inline int tx_dist(unsigned tail
, unsigned head
)
1084 return (head
- tail
) % TX_RING_SIZE
;
1087 /* Number of list elements available for next tx */
1088 static inline int tx_avail(const struct sky2_port
*sky2
)
1090 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1093 /* Estimate of number of transmit list elements required */
1094 static unsigned tx_le_req(const struct sk_buff
*skb
)
1098 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1099 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1101 if (skb_shinfo(skb
)->tso_size
)
1104 if (skb
->ip_summed
== CHECKSUM_HW
)
1111 * Put one packet in ring for transmit.
1112 * A single packet can generate multiple list elements, and
1113 * the number of ring elements will probably be less than the number
1114 * of list elements used.
1116 * No BH disabling for tx_lock here (like tg3)
1118 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1120 struct sky2_port
*sky2
= netdev_priv(dev
);
1121 struct sky2_hw
*hw
= sky2
->hw
;
1122 struct sky2_tx_le
*le
= NULL
;
1123 struct tx_ring_info
*re
;
1131 /* No BH disabling for tx_lock here. We are running in BH disabled
1132 * context and TX reclaim runs via poll inside of a software
1133 * interrupt, and no related locks in IRQ processing.
1135 if (!spin_trylock(&sky2
->tx_lock
))
1136 return NETDEV_TX_LOCKED
;
1138 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1139 /* There is a known but harmless race with lockless tx
1140 * and netif_stop_queue.
1142 if (!netif_queue_stopped(dev
)) {
1143 netif_stop_queue(dev
);
1144 if (net_ratelimit())
1145 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1148 spin_unlock(&sky2
->tx_lock
);
1150 return NETDEV_TX_BUSY
;
1153 if (unlikely(netif_msg_tx_queued(sky2
)))
1154 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1155 dev
->name
, sky2
->tx_prod
, skb
->len
);
1157 len
= skb_headlen(skb
);
1158 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1159 addr64
= high32(mapping
);
1161 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1163 /* Send high bits if changed or crosses boundary */
1164 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1165 le
= get_tx_le(sky2
);
1166 le
->tx
.addr
= cpu_to_le32(addr64
);
1168 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1169 sky2
->tx_addr64
= high32(mapping
+ len
);
1172 /* Check for TCP Segmentation Offload */
1173 mss
= skb_shinfo(skb
)->tso_size
;
1175 /* just drop the packet if non-linear expansion fails */
1176 if (skb_header_cloned(skb
) &&
1177 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1178 dev_kfree_skb_any(skb
);
1182 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1183 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1187 if (mss
!= sky2
->tx_last_mss
) {
1188 le
= get_tx_le(sky2
);
1189 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1190 le
->tx
.tso
.rsvd
= 0;
1191 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1193 sky2
->tx_last_mss
= mss
;
1197 #ifdef SKY2_VLAN_TAG_USED
1198 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1199 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1201 le
= get_tx_le(sky2
);
1203 le
->opcode
= OP_VLAN
|HW_OWNER
;
1206 le
->opcode
|= OP_VLAN
;
1207 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1212 /* Handle TCP checksum offload */
1213 if (skb
->ip_summed
== CHECKSUM_HW
) {
1214 u16 hdr
= skb
->h
.raw
- skb
->data
;
1215 u16 offset
= hdr
+ skb
->csum
;
1217 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1218 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1221 le
= get_tx_le(sky2
);
1222 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1223 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1224 le
->length
= 0; /* initial checksum value */
1225 le
->ctrl
= 1; /* one packet */
1226 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1229 le
= get_tx_le(sky2
);
1230 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1231 le
->length
= cpu_to_le16(len
);
1233 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1235 /* Record the transmit mapping info */
1237 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1239 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1240 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1241 struct tx_ring_info
*fre
;
1243 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1244 frag
->size
, PCI_DMA_TODEVICE
);
1245 addr64
= high32(mapping
);
1246 if (addr64
!= sky2
->tx_addr64
) {
1247 le
= get_tx_le(sky2
);
1248 le
->tx
.addr
= cpu_to_le32(addr64
);
1250 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1251 sky2
->tx_addr64
= addr64
;
1254 le
= get_tx_le(sky2
);
1255 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1256 le
->length
= cpu_to_le16(frag
->size
);
1258 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1261 + ((re
- sky2
->tx_ring
) + i
+ 1) % TX_RING_SIZE
;
1262 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1265 re
->idx
= sky2
->tx_prod
;
1268 avail
= tx_avail(sky2
);
1269 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1270 le
->ctrl
|= FRC_STAT
;
1271 if (avail
<= MAX_SKB_TX_LE
)
1272 netif_stop_queue(dev
);
1275 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1278 spin_unlock(&sky2
->tx_lock
);
1280 dev
->trans_start
= jiffies
;
1281 return NETDEV_TX_OK
;
1285 * Free ring elements from starting at tx_cons until "done"
1287 * NB: the hardware will tell us about partial completion of multi-part
1288 * buffers; these are deferred until completion.
1290 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1292 struct net_device
*dev
= sky2
->netdev
;
1293 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1297 BUG_ON(done
>= TX_RING_SIZE
);
1299 if (unlikely(netif_msg_tx_done(sky2
)))
1300 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1303 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1304 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1305 struct sk_buff
*skb
= re
->skb
;
1308 BUG_ON(nxt
>= TX_RING_SIZE
);
1309 prefetch(sky2
->tx_ring
+ nxt
);
1311 /* Check for partial status */
1312 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1316 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1317 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1319 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1320 struct tx_ring_info
*fre
;
1321 fre
= sky2
->tx_ring
+ (put
+ i
+ 1) % TX_RING_SIZE
;
1322 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1323 skb_shinfo(skb
)->frags
[i
].size
,
1327 dev_kfree_skb_any(skb
);
1330 sky2
->tx_cons
= put
;
1331 if (netif_queue_stopped(dev
) && tx_avail(sky2
) > MAX_SKB_TX_LE
)
1332 netif_wake_queue(dev
);
1335 /* Cleanup all untransmitted buffers, assume transmitter not running */
1336 static void sky2_tx_clean(struct sky2_port
*sky2
)
1338 spin_lock_bh(&sky2
->tx_lock
);
1339 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1340 spin_unlock_bh(&sky2
->tx_lock
);
1343 /* Network shutdown */
1344 static int sky2_down(struct net_device
*dev
)
1346 struct sky2_port
*sky2
= netdev_priv(dev
);
1347 struct sky2_hw
*hw
= sky2
->hw
;
1348 unsigned port
= sky2
->port
;
1352 /* Never really got started! */
1356 if (netif_msg_ifdown(sky2
))
1357 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1359 /* Stop more packets from being queued */
1360 netif_stop_queue(dev
);
1362 sky2_phy_reset(hw
, port
);
1364 /* Stop transmitter */
1365 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1366 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1368 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1369 RB_RST_SET
| RB_DIS_OP_MD
);
1371 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1372 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1373 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1375 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1377 /* Workaround shared GMAC reset */
1378 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1379 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1380 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1382 /* Disable Force Sync bit and Enable Alloc bit */
1383 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1384 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1386 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1387 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1388 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1390 /* Reset the PCI FIFO of the async Tx queue */
1391 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1392 BMU_RST_SET
| BMU_FIFO_RST
);
1394 /* Reset the Tx prefetch units */
1395 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1398 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1402 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1403 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1405 /* Disable port IRQ */
1406 imask
= sky2_read32(hw
, B0_IMSK
);
1407 imask
&= ~(sky2
->port
== 0) ? Y2_IS_PORT_1
: Y2_IS_PORT_2
;
1408 sky2_write32(hw
, B0_IMSK
, imask
);
1410 /* turn off LED's */
1411 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1413 synchronize_irq(hw
->pdev
->irq
);
1415 sky2_tx_clean(sky2
);
1416 sky2_rx_clean(sky2
);
1418 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1419 sky2
->rx_le
, sky2
->rx_le_map
);
1420 kfree(sky2
->rx_ring
);
1422 pci_free_consistent(hw
->pdev
,
1423 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1424 sky2
->tx_le
, sky2
->tx_le_map
);
1425 kfree(sky2
->tx_ring
);
1430 sky2
->rx_ring
= NULL
;
1431 sky2
->tx_ring
= NULL
;
1436 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1441 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1442 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1444 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1445 case PHY_M_PS_SPEED_1000
:
1447 case PHY_M_PS_SPEED_100
:
1454 static void sky2_link_up(struct sky2_port
*sky2
)
1456 struct sky2_hw
*hw
= sky2
->hw
;
1457 unsigned port
= sky2
->port
;
1460 /* Enable Transmit FIFO Underrun */
1461 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1463 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1464 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1465 reg
|= GM_GPCR_AU_ALL_DIS
;
1467 /* Is write/read necessary? Copied from sky2_mac_init */
1468 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1469 gma_read16(hw
, port
, GM_GP_CTRL
);
1471 switch (sky2
->speed
) {
1473 reg
&= ~GM_GPCR_SPEED_100
;
1474 reg
|= GM_GPCR_SPEED_1000
;
1477 reg
&= ~GM_GPCR_SPEED_1000
;
1478 reg
|= GM_GPCR_SPEED_100
;
1481 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1485 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1487 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1488 reg
|= GM_GPCR_DUP_FULL
;
1491 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1492 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1493 gma_read16(hw
, port
, GM_GP_CTRL
);
1495 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1497 netif_carrier_on(sky2
->netdev
);
1498 netif_wake_queue(sky2
->netdev
);
1500 /* Turn on link LED */
1501 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1502 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1504 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
1505 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1507 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1508 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1509 PHY_M_LEDC_INIT_CTRL(sky2
->speed
==
1511 PHY_M_LEDC_STA1_CTRL(sky2
->speed
==
1512 SPEED_100
? 7 : 0) |
1513 PHY_M_LEDC_STA0_CTRL(sky2
->speed
==
1514 SPEED_1000
? 7 : 0));
1515 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1518 if (netif_msg_link(sky2
))
1519 printk(KERN_INFO PFX
1520 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1521 sky2
->netdev
->name
, sky2
->speed
,
1522 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1523 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1524 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1527 static void sky2_link_down(struct sky2_port
*sky2
)
1529 struct sky2_hw
*hw
= sky2
->hw
;
1530 unsigned port
= sky2
->port
;
1533 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1535 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1536 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1537 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1538 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1540 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1541 /* restore Asymmetric Pause bit */
1542 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1543 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1547 netif_carrier_off(sky2
->netdev
);
1548 netif_stop_queue(sky2
->netdev
);
1550 /* Turn on link LED */
1551 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1553 if (netif_msg_link(sky2
))
1554 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1555 sky2_phy_init(hw
, port
);
1558 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1560 struct sky2_hw
*hw
= sky2
->hw
;
1561 unsigned port
= sky2
->port
;
1564 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1566 if (lpa
& PHY_M_AN_RF
) {
1567 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1571 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1572 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1573 printk(KERN_ERR PFX
"%s: master/slave fault",
1574 sky2
->netdev
->name
);
1578 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1579 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1580 sky2
->netdev
->name
);
1584 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1586 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1588 /* Pause bits are offset (9..8) */
1589 if (hw
->chip_id
== CHIP_ID_YUKON_XL
)
1592 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1593 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1595 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1596 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1597 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1599 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1604 /* Interrupt from PHY */
1605 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1607 struct net_device
*dev
= hw
->dev
[port
];
1608 struct sky2_port
*sky2
= netdev_priv(dev
);
1609 u16 istatus
, phystat
;
1611 spin_lock(&sky2
->phy_lock
);
1612 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1613 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1615 if (!netif_running(dev
))
1618 if (netif_msg_intr(sky2
))
1619 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1620 sky2
->netdev
->name
, istatus
, phystat
);
1622 if (istatus
& PHY_M_IS_AN_COMPL
) {
1623 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1628 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1629 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1631 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1633 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1635 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1636 if (phystat
& PHY_M_PS_LINK_UP
)
1639 sky2_link_down(sky2
);
1642 spin_unlock(&sky2
->phy_lock
);
1646 /* Transmit timeout is only called if we are running, carries is up
1647 * and tx queue is full (stopped).
1649 static void sky2_tx_timeout(struct net_device
*dev
)
1651 struct sky2_port
*sky2
= netdev_priv(dev
);
1652 struct sky2_hw
*hw
= sky2
->hw
;
1653 unsigned txq
= txqaddr
[sky2
->port
];
1655 if (netif_msg_timer(sky2
))
1656 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1658 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1659 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1661 sky2_tx_clean(sky2
);
1664 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1668 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1669 /* Want receive buffer size to be multiple of 64 bits
1670 * and incl room for vlan and truncation
1672 static inline unsigned sky2_buf_size(int mtu
)
1674 return roundup(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1677 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1679 struct sky2_port
*sky2
= netdev_priv(dev
);
1680 struct sky2_hw
*hw
= sky2
->hw
;
1685 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1688 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1691 if (!netif_running(dev
)) {
1696 imask
= sky2_read32(hw
, B0_IMSK
);
1697 sky2_write32(hw
, B0_IMSK
, 0);
1699 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1700 netif_stop_queue(dev
);
1701 netif_poll_disable(hw
->dev
[0]);
1703 synchronize_irq(hw
->pdev
->irq
);
1705 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1706 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1708 sky2_rx_clean(sky2
);
1711 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1712 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1713 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1715 if (dev
->mtu
> ETH_DATA_LEN
)
1716 mode
|= GM_SMOD_JUMBO_ENA
;
1718 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1720 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1722 err
= sky2_rx_start(sky2
);
1723 sky2_write32(hw
, B0_IMSK
, imask
);
1728 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1730 netif_poll_enable(hw
->dev
[0]);
1731 netif_wake_queue(dev
);
1738 * Receive one packet.
1739 * For small packets or errors, just reuse existing skb.
1740 * For larger packets, get new buffer.
1742 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1743 u16 length
, u32 status
)
1745 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1746 struct sk_buff
*skb
= NULL
;
1748 if (unlikely(netif_msg_rx_status(sky2
)))
1749 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1750 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1752 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1753 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1755 if (status
& GMR_FS_ANY_ERR
)
1758 if (!(status
& GMR_FS_RX_OK
))
1761 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1764 if (length
< copybreak
) {
1765 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1769 skb_reserve(skb
, 2);
1770 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1771 length
, PCI_DMA_FROMDEVICE
);
1772 memcpy(skb
->data
, re
->skb
->data
, length
);
1773 skb
->ip_summed
= re
->skb
->ip_summed
;
1774 skb
->csum
= re
->skb
->csum
;
1775 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1776 length
, PCI_DMA_FROMDEVICE
);
1778 struct sk_buff
*nskb
;
1780 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1786 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1787 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1788 prefetch(skb
->data
);
1790 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1791 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1794 skb_put(skb
, length
);
1796 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1797 sky2_rx_add(sky2
, re
->mapaddr
);
1799 /* Tell receiver about new buffers. */
1800 sky2_put_idx(sky2
->hw
, rxqaddr
[sky2
->port
], sky2
->rx_put
);
1805 ++sky2
->net_stats
.rx_over_errors
;
1809 ++sky2
->net_stats
.rx_errors
;
1811 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1812 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1813 sky2
->netdev
->name
, status
, length
);
1815 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1816 sky2
->net_stats
.rx_length_errors
++;
1817 if (status
& GMR_FS_FRAGMENT
)
1818 sky2
->net_stats
.rx_frame_errors
++;
1819 if (status
& GMR_FS_CRC_ERR
)
1820 sky2
->net_stats
.rx_crc_errors
++;
1821 if (status
& GMR_FS_RX_FF_OV
)
1822 sky2
->net_stats
.rx_fifo_errors
++;
1827 /* Transmit complete */
1828 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1830 struct sky2_port
*sky2
= netdev_priv(dev
);
1832 if (netif_running(dev
)) {
1833 spin_lock(&sky2
->tx_lock
);
1834 sky2_tx_complete(sky2
, last
);
1835 spin_unlock(&sky2
->tx_lock
);
1839 /* Process status response ring */
1840 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1847 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1848 struct net_device
*dev
;
1849 struct sky2_port
*sky2
;
1850 struct sk_buff
*skb
;
1855 opcode
= le
->opcode
;
1858 opcode
&= ~HW_OWNER
;
1860 hw
->st_idx
= (hw
->st_idx
+ 1) % STATUS_RING_SIZE
;
1865 dev
= hw
->dev
[link
];
1867 sky2
= netdev_priv(dev
);
1868 length
= le
->length
;
1869 status
= le
->status
;
1873 skb
= sky2_receive(sky2
, length
, status
);
1878 skb
->protocol
= eth_type_trans(skb
, dev
);
1879 dev
->last_rx
= jiffies
;
1881 #ifdef SKY2_VLAN_TAG_USED
1882 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1883 vlan_hwaccel_receive_skb(skb
,
1885 be16_to_cpu(sky2
->rx_tag
));
1888 netif_receive_skb(skb
);
1890 if (++work_done
>= to_do
)
1894 #ifdef SKY2_VLAN_TAG_USED
1896 sky2
->rx_tag
= length
;
1900 sky2
->rx_tag
= length
;
1904 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1905 skb
->ip_summed
= CHECKSUM_HW
;
1906 skb
->csum
= le16_to_cpu(status
);
1910 /* TX index reports status for both ports */
1911 sky2_tx_done(hw
->dev
[0], status
& 0xffff);
1913 sky2_tx_done(hw
->dev
[1],
1914 ((status
>> 24) & 0xff)
1915 | (u16
)(length
& 0xf) << 8);
1919 if (net_ratelimit())
1920 printk(KERN_WARNING PFX
1921 "unknown status opcode 0x%x\n", opcode
);
1930 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
1932 struct net_device
*dev
= hw
->dev
[port
];
1934 if (net_ratelimit())
1935 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
1938 if (status
& Y2_IS_PAR_RD1
) {
1939 if (net_ratelimit())
1940 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
1943 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
1946 if (status
& Y2_IS_PAR_WR1
) {
1947 if (net_ratelimit())
1948 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
1951 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
1954 if (status
& Y2_IS_PAR_MAC1
) {
1955 if (net_ratelimit())
1956 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
1957 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
1960 if (status
& Y2_IS_PAR_RX1
) {
1961 if (net_ratelimit())
1962 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
1963 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
1966 if (status
& Y2_IS_TCP_TXA1
) {
1967 if (net_ratelimit())
1968 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
1970 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
1974 static void sky2_hw_intr(struct sky2_hw
*hw
)
1976 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
1978 if (status
& Y2_IS_TIST_OV
)
1979 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
1981 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
1984 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
1985 if (net_ratelimit())
1986 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
1987 pci_name(hw
->pdev
), pci_err
);
1989 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
1990 sky2_pci_write16(hw
, PCI_STATUS
,
1991 pci_err
| PCI_STATUS_ERROR_BITS
);
1992 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
1995 if (status
& Y2_IS_PCI_EXP
) {
1996 /* PCI-Express uncorrectable Error occurred */
1999 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2001 if (net_ratelimit())
2002 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2003 pci_name(hw
->pdev
), pex_err
);
2005 /* clear the interrupt */
2006 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2007 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2009 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2011 if (pex_err
& PEX_FATAL_ERRORS
) {
2012 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2013 hwmsk
&= ~Y2_IS_PCI_EXP
;
2014 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2018 if (status
& Y2_HWE_L1_MASK
)
2019 sky2_hw_error(hw
, 0, status
);
2021 if (status
& Y2_HWE_L1_MASK
)
2022 sky2_hw_error(hw
, 1, status
);
2025 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2027 struct net_device
*dev
= hw
->dev
[port
];
2028 struct sky2_port
*sky2
= netdev_priv(dev
);
2029 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2031 if (netif_msg_intr(sky2
))
2032 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2035 if (status
& GM_IS_RX_FF_OR
) {
2036 ++sky2
->net_stats
.rx_fifo_errors
;
2037 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2040 if (status
& GM_IS_TX_FF_UR
) {
2041 ++sky2
->net_stats
.tx_fifo_errors
;
2042 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2047 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2049 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2050 int work_limit
= min(dev0
->quota
, *budget
);
2052 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2054 if (status
& Y2_IS_HW_ERR
)
2057 if (status
& Y2_IS_IRQ_PHY1
)
2058 sky2_phy_intr(hw
, 0);
2060 if (status
& Y2_IS_IRQ_PHY2
)
2061 sky2_phy_intr(hw
, 1);
2063 if (status
& Y2_IS_IRQ_MAC1
)
2064 sky2_mac_intr(hw
, 0);
2066 if (status
& Y2_IS_IRQ_MAC2
)
2067 sky2_mac_intr(hw
, 1);
2069 if (status
& Y2_IS_STAT_BMU
) {
2070 work_done
= sky2_status_intr(hw
, work_limit
);
2071 *budget
-= work_done
;
2072 dev0
->quota
-= work_done
;
2074 if (work_done
>= work_limit
)
2077 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2080 netif_rx_complete(dev0
);
2082 status
= sky2_read32(hw
, B0_Y2_SP_LISR
);
2086 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2088 struct sky2_hw
*hw
= dev_id
;
2089 struct net_device
*dev0
= hw
->dev
[0];
2092 /* Reading this mask interrupts as side effect */
2093 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2094 if (status
== 0 || status
== ~0)
2097 prefetch(&hw
->st_le
[hw
->st_idx
]);
2098 if (likely(__netif_rx_schedule_prep(dev0
)))
2099 __netif_rx_schedule(dev0
);
2104 #ifdef CONFIG_NET_POLL_CONTROLLER
2105 static void sky2_netpoll(struct net_device
*dev
)
2107 struct sky2_port
*sky2
= netdev_priv(dev
);
2109 sky2_intr(sky2
->hw
->pdev
->irq
, sky2
->hw
, NULL
);
2113 /* Chip internal frequency for clock calculations */
2114 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2116 switch (hw
->chip_id
) {
2117 case CHIP_ID_YUKON_EC
:
2118 case CHIP_ID_YUKON_EC_U
:
2119 return 125; /* 125 Mhz */
2120 case CHIP_ID_YUKON_FE
:
2121 return 100; /* 100 Mhz */
2122 default: /* YUKON_XL */
2123 return 156; /* 156 Mhz */
2127 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2129 return sky2_mhz(hw
) * us
;
2132 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2134 return clk
/ sky2_mhz(hw
);
2138 static int sky2_reset(struct sky2_hw
*hw
)
2144 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2146 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2147 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2148 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2149 pci_name(hw
->pdev
), hw
->chip_id
);
2153 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2155 /* This rev is really old, and requires untested workarounds */
2156 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2157 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2158 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2159 hw
->chip_id
, hw
->chip_rev
);
2163 /* This chip is new and not tested yet */
2164 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
2165 pr_info(PFX
"%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2166 pci_name(hw
->pdev
));
2167 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2171 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2172 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2173 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2177 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2178 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2180 /* clear PCI errors, if any */
2181 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2183 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2184 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2187 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2189 /* clear any PEX errors */
2190 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2191 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2194 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2195 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2198 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2199 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2200 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2204 sky2_set_power_state(hw
, PCI_D0
);
2206 for (i
= 0; i
< hw
->ports
; i
++) {
2207 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2208 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2211 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2213 /* Clear I2C IRQ noise */
2214 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2216 /* turn off hardware timer (unused) */
2217 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2218 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2220 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2222 /* Turn off descriptor polling */
2223 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2225 /* Turn off receive timestamp */
2226 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2227 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2229 /* enable the Tx Arbiters */
2230 for (i
= 0; i
< hw
->ports
; i
++)
2231 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2233 /* Initialize ram interface */
2234 for (i
= 0; i
< hw
->ports
; i
++) {
2235 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2237 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2238 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2239 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2240 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2241 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2242 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2243 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2244 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2245 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2246 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2247 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2248 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2251 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2253 for (i
= 0; i
< hw
->ports
; i
++)
2254 sky2_phy_reset(hw
, i
);
2256 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2259 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2260 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2262 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2263 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2265 /* Set the list last index */
2266 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2268 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2269 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2271 /* set Status-FIFO ISR watermark */
2272 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2273 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2275 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2277 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2278 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2279 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2281 /* enable status unit */
2282 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2284 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2285 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2286 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2291 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2295 modes
= SUPPORTED_10baseT_Half
2296 | SUPPORTED_10baseT_Full
2297 | SUPPORTED_100baseT_Half
2298 | SUPPORTED_100baseT_Full
2299 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2301 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2302 modes
|= SUPPORTED_1000baseT_Half
2303 | SUPPORTED_1000baseT_Full
;
2305 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2306 | SUPPORTED_Autoneg
;
2310 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2312 struct sky2_port
*sky2
= netdev_priv(dev
);
2313 struct sky2_hw
*hw
= sky2
->hw
;
2315 ecmd
->transceiver
= XCVR_INTERNAL
;
2316 ecmd
->supported
= sky2_supported_modes(hw
);
2317 ecmd
->phy_address
= PHY_ADDR_MARV
;
2319 ecmd
->supported
= SUPPORTED_10baseT_Half
2320 | SUPPORTED_10baseT_Full
2321 | SUPPORTED_100baseT_Half
2322 | SUPPORTED_100baseT_Full
2323 | SUPPORTED_1000baseT_Half
2324 | SUPPORTED_1000baseT_Full
2325 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2326 ecmd
->port
= PORT_TP
;
2328 ecmd
->port
= PORT_FIBRE
;
2330 ecmd
->advertising
= sky2
->advertising
;
2331 ecmd
->autoneg
= sky2
->autoneg
;
2332 ecmd
->speed
= sky2
->speed
;
2333 ecmd
->duplex
= sky2
->duplex
;
2337 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2339 struct sky2_port
*sky2
= netdev_priv(dev
);
2340 const struct sky2_hw
*hw
= sky2
->hw
;
2341 u32 supported
= sky2_supported_modes(hw
);
2343 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2344 ecmd
->advertising
= supported
;
2350 switch (ecmd
->speed
) {
2352 if (ecmd
->duplex
== DUPLEX_FULL
)
2353 setting
= SUPPORTED_1000baseT_Full
;
2354 else if (ecmd
->duplex
== DUPLEX_HALF
)
2355 setting
= SUPPORTED_1000baseT_Half
;
2360 if (ecmd
->duplex
== DUPLEX_FULL
)
2361 setting
= SUPPORTED_100baseT_Full
;
2362 else if (ecmd
->duplex
== DUPLEX_HALF
)
2363 setting
= SUPPORTED_100baseT_Half
;
2369 if (ecmd
->duplex
== DUPLEX_FULL
)
2370 setting
= SUPPORTED_10baseT_Full
;
2371 else if (ecmd
->duplex
== DUPLEX_HALF
)
2372 setting
= SUPPORTED_10baseT_Half
;
2380 if ((setting
& supported
) == 0)
2383 sky2
->speed
= ecmd
->speed
;
2384 sky2
->duplex
= ecmd
->duplex
;
2387 sky2
->autoneg
= ecmd
->autoneg
;
2388 sky2
->advertising
= ecmd
->advertising
;
2390 if (netif_running(dev
))
2391 sky2_phy_reinit(sky2
);
2396 static void sky2_get_drvinfo(struct net_device
*dev
,
2397 struct ethtool_drvinfo
*info
)
2399 struct sky2_port
*sky2
= netdev_priv(dev
);
2401 strcpy(info
->driver
, DRV_NAME
);
2402 strcpy(info
->version
, DRV_VERSION
);
2403 strcpy(info
->fw_version
, "N/A");
2404 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2407 static const struct sky2_stat
{
2408 char name
[ETH_GSTRING_LEN
];
2411 { "tx_bytes", GM_TXO_OK_HI
},
2412 { "rx_bytes", GM_RXO_OK_HI
},
2413 { "tx_broadcast", GM_TXF_BC_OK
},
2414 { "rx_broadcast", GM_RXF_BC_OK
},
2415 { "tx_multicast", GM_TXF_MC_OK
},
2416 { "rx_multicast", GM_RXF_MC_OK
},
2417 { "tx_unicast", GM_TXF_UC_OK
},
2418 { "rx_unicast", GM_RXF_UC_OK
},
2419 { "tx_mac_pause", GM_TXF_MPAUSE
},
2420 { "rx_mac_pause", GM_RXF_MPAUSE
},
2421 { "collisions", GM_TXF_SNG_COL
},
2422 { "late_collision",GM_TXF_LAT_COL
},
2423 { "aborted", GM_TXF_ABO_COL
},
2424 { "multi_collisions", GM_TXF_MUL_COL
},
2425 { "fifo_underrun", GM_TXE_FIFO_UR
},
2426 { "fifo_overflow", GM_RXE_FIFO_OV
},
2427 { "rx_toolong", GM_RXF_LNG_ERR
},
2428 { "rx_jabber", GM_RXF_JAB_PKT
},
2429 { "rx_runt", GM_RXE_FRAG
},
2430 { "rx_too_long", GM_RXF_LNG_ERR
},
2431 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2434 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2436 struct sky2_port
*sky2
= netdev_priv(dev
);
2438 return sky2
->rx_csum
;
2441 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2443 struct sky2_port
*sky2
= netdev_priv(dev
);
2445 sky2
->rx_csum
= data
;
2447 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2448 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2453 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2455 struct sky2_port
*sky2
= netdev_priv(netdev
);
2456 return sky2
->msg_enable
;
2459 static int sky2_nway_reset(struct net_device
*dev
)
2461 struct sky2_port
*sky2
= netdev_priv(dev
);
2463 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2466 sky2_phy_reinit(sky2
);
2471 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2473 struct sky2_hw
*hw
= sky2
->hw
;
2474 unsigned port
= sky2
->port
;
2477 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2478 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2479 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2480 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2482 for (i
= 2; i
< count
; i
++)
2483 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2486 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2488 struct sky2_port
*sky2
= netdev_priv(netdev
);
2489 sky2
->msg_enable
= value
;
2492 static int sky2_get_stats_count(struct net_device
*dev
)
2494 return ARRAY_SIZE(sky2_stats
);
2497 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2498 struct ethtool_stats
*stats
, u64
* data
)
2500 struct sky2_port
*sky2
= netdev_priv(dev
);
2502 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2505 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2509 switch (stringset
) {
2511 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2512 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2513 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2518 /* Use hardware MIB variables for critical path statistics and
2519 * transmit feedback not reported at interrupt.
2520 * Other errors are accounted for in interrupt handler.
2522 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2524 struct sky2_port
*sky2
= netdev_priv(dev
);
2527 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2529 sky2
->net_stats
.tx_bytes
= data
[0];
2530 sky2
->net_stats
.rx_bytes
= data
[1];
2531 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2532 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2533 sky2
->net_stats
.multicast
= data
[5] + data
[7];
2534 sky2
->net_stats
.collisions
= data
[10];
2535 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2537 return &sky2
->net_stats
;
2540 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2542 struct sky2_port
*sky2
= netdev_priv(dev
);
2543 struct sky2_hw
*hw
= sky2
->hw
;
2544 unsigned port
= sky2
->port
;
2545 const struct sockaddr
*addr
= p
;
2547 if (!is_valid_ether_addr(addr
->sa_data
))
2548 return -EADDRNOTAVAIL
;
2550 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2551 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2552 dev
->dev_addr
, ETH_ALEN
);
2553 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2554 dev
->dev_addr
, ETH_ALEN
);
2556 /* virtual address for data */
2557 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2559 /* physical address: used for pause frames */
2560 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2565 static void sky2_set_multicast(struct net_device
*dev
)
2567 struct sky2_port
*sky2
= netdev_priv(dev
);
2568 struct sky2_hw
*hw
= sky2
->hw
;
2569 unsigned port
= sky2
->port
;
2570 struct dev_mc_list
*list
= dev
->mc_list
;
2574 memset(filter
, 0, sizeof(filter
));
2576 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2577 reg
|= GM_RXCR_UCF_ENA
;
2579 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2580 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2581 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2582 memset(filter
, 0xff, sizeof(filter
));
2583 else if (dev
->mc_count
== 0) /* no multicast */
2584 reg
&= ~GM_RXCR_MCF_ENA
;
2587 reg
|= GM_RXCR_MCF_ENA
;
2589 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2590 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2591 filter
[bit
/ 8] |= 1 << (bit
% 8);
2595 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2596 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2597 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2598 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2599 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2600 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2601 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2602 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2604 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2607 /* Can have one global because blinking is controlled by
2608 * ethtool and that is always under RTNL mutex
2610 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2614 switch (hw
->chip_id
) {
2615 case CHIP_ID_YUKON_XL
:
2616 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2617 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2618 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2619 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2620 PHY_M_LEDC_INIT_CTRL(7) |
2621 PHY_M_LEDC_STA1_CTRL(7) |
2622 PHY_M_LEDC_STA0_CTRL(7))
2625 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2629 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2630 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2631 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2632 PHY_M_LED_MO_10(MO_LED_ON
) |
2633 PHY_M_LED_MO_100(MO_LED_ON
) |
2634 PHY_M_LED_MO_1000(MO_LED_ON
) |
2635 PHY_M_LED_MO_RX(MO_LED_ON
)
2636 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2637 PHY_M_LED_MO_10(MO_LED_OFF
) |
2638 PHY_M_LED_MO_100(MO_LED_OFF
) |
2639 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2640 PHY_M_LED_MO_RX(MO_LED_OFF
));
2645 /* blink LED's for finding board */
2646 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2648 struct sky2_port
*sky2
= netdev_priv(dev
);
2649 struct sky2_hw
*hw
= sky2
->hw
;
2650 unsigned port
= sky2
->port
;
2651 u16 ledctrl
, ledover
= 0;
2656 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2657 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2661 /* save initial values */
2662 spin_lock_bh(&sky2
->phy_lock
);
2663 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2664 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2665 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2666 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2667 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2669 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2670 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2674 while (!interrupted
&& ms
> 0) {
2675 sky2_led(hw
, port
, onoff
);
2678 spin_unlock_bh(&sky2
->phy_lock
);
2679 interrupted
= msleep_interruptible(250);
2680 spin_lock_bh(&sky2
->phy_lock
);
2685 /* resume regularly scheduled programming */
2686 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2687 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2688 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2689 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2690 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2692 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2693 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2695 spin_unlock_bh(&sky2
->phy_lock
);
2700 static void sky2_get_pauseparam(struct net_device
*dev
,
2701 struct ethtool_pauseparam
*ecmd
)
2703 struct sky2_port
*sky2
= netdev_priv(dev
);
2705 ecmd
->tx_pause
= sky2
->tx_pause
;
2706 ecmd
->rx_pause
= sky2
->rx_pause
;
2707 ecmd
->autoneg
= sky2
->autoneg
;
2710 static int sky2_set_pauseparam(struct net_device
*dev
,
2711 struct ethtool_pauseparam
*ecmd
)
2713 struct sky2_port
*sky2
= netdev_priv(dev
);
2716 sky2
->autoneg
= ecmd
->autoneg
;
2717 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2718 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2720 sky2_phy_reinit(sky2
);
2725 static int sky2_get_coalesce(struct net_device
*dev
,
2726 struct ethtool_coalesce
*ecmd
)
2728 struct sky2_port
*sky2
= netdev_priv(dev
);
2729 struct sky2_hw
*hw
= sky2
->hw
;
2731 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2732 ecmd
->tx_coalesce_usecs
= 0;
2734 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2735 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2737 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2739 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2740 ecmd
->rx_coalesce_usecs
= 0;
2742 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2743 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2745 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2747 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2748 ecmd
->rx_coalesce_usecs_irq
= 0;
2750 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2751 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2754 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2759 /* Note: this affect both ports */
2760 static int sky2_set_coalesce(struct net_device
*dev
,
2761 struct ethtool_coalesce
*ecmd
)
2763 struct sky2_port
*sky2
= netdev_priv(dev
);
2764 struct sky2_hw
*hw
= sky2
->hw
;
2765 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2767 if (ecmd
->tx_coalesce_usecs
> tmax
||
2768 ecmd
->rx_coalesce_usecs
> tmax
||
2769 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2772 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2774 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2776 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2779 if (ecmd
->tx_coalesce_usecs
== 0)
2780 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2782 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2783 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2784 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2786 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2788 if (ecmd
->rx_coalesce_usecs
== 0)
2789 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2791 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2792 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2793 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2795 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2797 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2798 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2800 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2801 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2802 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2804 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2808 static void sky2_get_ringparam(struct net_device
*dev
,
2809 struct ethtool_ringparam
*ering
)
2811 struct sky2_port
*sky2
= netdev_priv(dev
);
2813 ering
->rx_max_pending
= RX_MAX_PENDING
;
2814 ering
->rx_mini_max_pending
= 0;
2815 ering
->rx_jumbo_max_pending
= 0;
2816 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2818 ering
->rx_pending
= sky2
->rx_pending
;
2819 ering
->rx_mini_pending
= 0;
2820 ering
->rx_jumbo_pending
= 0;
2821 ering
->tx_pending
= sky2
->tx_pending
;
2824 static int sky2_set_ringparam(struct net_device
*dev
,
2825 struct ethtool_ringparam
*ering
)
2827 struct sky2_port
*sky2
= netdev_priv(dev
);
2830 if (ering
->rx_pending
> RX_MAX_PENDING
||
2831 ering
->rx_pending
< 8 ||
2832 ering
->tx_pending
< MAX_SKB_TX_LE
||
2833 ering
->tx_pending
> TX_RING_SIZE
- 1)
2836 if (netif_running(dev
))
2839 sky2
->rx_pending
= ering
->rx_pending
;
2840 sky2
->tx_pending
= ering
->tx_pending
;
2842 if (netif_running(dev
)) {
2847 sky2_set_multicast(dev
);
2853 static int sky2_get_regs_len(struct net_device
*dev
)
2859 * Returns copy of control register region
2860 * Note: access to the RAM address register set will cause timeouts.
2862 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2865 const struct sky2_port
*sky2
= netdev_priv(dev
);
2866 const void __iomem
*io
= sky2
->hw
->regs
;
2868 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
2870 memset(p
, 0, regs
->len
);
2872 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
2874 memcpy_fromio(p
+ B3_RI_WTO_R1
,
2876 regs
->len
- B3_RI_WTO_R1
);
2879 static struct ethtool_ops sky2_ethtool_ops
= {
2880 .get_settings
= sky2_get_settings
,
2881 .set_settings
= sky2_set_settings
,
2882 .get_drvinfo
= sky2_get_drvinfo
,
2883 .get_msglevel
= sky2_get_msglevel
,
2884 .set_msglevel
= sky2_set_msglevel
,
2885 .nway_reset
= sky2_nway_reset
,
2886 .get_regs_len
= sky2_get_regs_len
,
2887 .get_regs
= sky2_get_regs
,
2888 .get_link
= ethtool_op_get_link
,
2889 .get_sg
= ethtool_op_get_sg
,
2890 .set_sg
= ethtool_op_set_sg
,
2891 .get_tx_csum
= ethtool_op_get_tx_csum
,
2892 .set_tx_csum
= ethtool_op_set_tx_csum
,
2893 .get_tso
= ethtool_op_get_tso
,
2894 .set_tso
= ethtool_op_set_tso
,
2895 .get_rx_csum
= sky2_get_rx_csum
,
2896 .set_rx_csum
= sky2_set_rx_csum
,
2897 .get_strings
= sky2_get_strings
,
2898 .get_coalesce
= sky2_get_coalesce
,
2899 .set_coalesce
= sky2_set_coalesce
,
2900 .get_ringparam
= sky2_get_ringparam
,
2901 .set_ringparam
= sky2_set_ringparam
,
2902 .get_pauseparam
= sky2_get_pauseparam
,
2903 .set_pauseparam
= sky2_set_pauseparam
,
2904 .phys_id
= sky2_phys_id
,
2905 .get_stats_count
= sky2_get_stats_count
,
2906 .get_ethtool_stats
= sky2_get_ethtool_stats
,
2907 .get_perm_addr
= ethtool_op_get_perm_addr
,
2910 /* Initialize network device */
2911 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
2912 unsigned port
, int highmem
)
2914 struct sky2_port
*sky2
;
2915 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
2918 printk(KERN_ERR
"sky2 etherdev alloc failed");
2922 SET_MODULE_OWNER(dev
);
2923 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
2924 dev
->irq
= hw
->pdev
->irq
;
2925 dev
->open
= sky2_up
;
2926 dev
->stop
= sky2_down
;
2927 dev
->do_ioctl
= sky2_ioctl
;
2928 dev
->hard_start_xmit
= sky2_xmit_frame
;
2929 dev
->get_stats
= sky2_get_stats
;
2930 dev
->set_multicast_list
= sky2_set_multicast
;
2931 dev
->set_mac_address
= sky2_set_mac_address
;
2932 dev
->change_mtu
= sky2_change_mtu
;
2933 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
2934 dev
->tx_timeout
= sky2_tx_timeout
;
2935 dev
->watchdog_timeo
= TX_WATCHDOG
;
2937 dev
->poll
= sky2_poll
;
2938 dev
->weight
= NAPI_WEIGHT
;
2939 #ifdef CONFIG_NET_POLL_CONTROLLER
2940 dev
->poll_controller
= sky2_netpoll
;
2943 sky2
= netdev_priv(dev
);
2946 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
2948 spin_lock_init(&sky2
->tx_lock
);
2949 /* Auto speed and flow control */
2950 sky2
->autoneg
= AUTONEG_ENABLE
;
2955 sky2
->advertising
= sky2_supported_modes(hw
);
2957 /* Receive checksum disabled for Yukon XL
2958 * because of observed problems with incorrect
2959 * values when multiple packets are received in one interrupt
2961 sky2
->rx_csum
= (hw
->chip_id
!= CHIP_ID_YUKON_XL
);
2963 spin_lock_init(&sky2
->phy_lock
);
2964 sky2
->tx_pending
= TX_DEF_PENDING
;
2965 sky2
->rx_pending
= RX_DEF_PENDING
;
2966 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
2968 hw
->dev
[port
] = dev
;
2972 dev
->features
|= NETIF_F_LLTX
;
2973 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
2974 dev
->features
|= NETIF_F_TSO
;
2976 dev
->features
|= NETIF_F_HIGHDMA
;
2977 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
2979 #ifdef SKY2_VLAN_TAG_USED
2980 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2981 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
2982 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
2985 /* read the mac address */
2986 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
2987 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
2989 /* device is off until link detection */
2990 netif_carrier_off(dev
);
2991 netif_stop_queue(dev
);
2996 static void __devinit
sky2_show_addr(struct net_device
*dev
)
2998 const struct sky2_port
*sky2
= netdev_priv(dev
);
3000 if (netif_msg_probe(sky2
))
3001 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3003 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3004 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3007 /* Handle software interrupt used during MSI test */
3008 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3009 struct pt_regs
*regs
)
3011 struct sky2_hw
*hw
= dev_id
;
3012 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3017 if (status
& Y2_IS_IRQ_SW
) {
3018 hw
->msi_detected
= 1;
3019 wake_up(&hw
->msi_wait
);
3020 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3022 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3027 /* Test interrupt path by forcing a a software IRQ */
3028 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3030 struct pci_dev
*pdev
= hw
->pdev
;
3033 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3035 err
= request_irq(pdev
->irq
, sky2_test_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3037 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3038 pci_name(pdev
), pdev
->irq
);
3042 init_waitqueue_head (&hw
->msi_wait
);
3044 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3047 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3049 if (!hw
->msi_detected
) {
3050 /* MSI test failed, go back to INTx mode */
3051 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3052 "switching to INTx mode. Please report this failure to "
3053 "the PCI maintainer and include system chipset information.\n",
3057 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3060 sky2_write32(hw
, B0_IMSK
, 0);
3062 free_irq(pdev
->irq
, hw
);
3067 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3068 const struct pci_device_id
*ent
)
3070 struct net_device
*dev
, *dev1
= NULL
;
3072 int err
, pm_cap
, using_dac
= 0;
3074 err
= pci_enable_device(pdev
);
3076 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3081 err
= pci_request_regions(pdev
, DRV_NAME
);
3083 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3088 pci_set_master(pdev
);
3090 /* Find power-management capability. */
3091 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3093 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3096 goto err_out_free_regions
;
3099 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3100 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3102 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3104 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3105 "for consistent allocations\n", pci_name(pdev
));
3106 goto err_out_free_regions
;
3110 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3112 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3114 goto err_out_free_regions
;
3119 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3121 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3123 goto err_out_free_regions
;
3128 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3130 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3132 goto err_out_free_hw
;
3134 hw
->pm_cap
= pm_cap
;
3137 /* byte swap descriptors in hardware */
3141 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3142 reg
|= PCI_REV_DESC
;
3143 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3147 /* ring for status responses */
3148 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3151 goto err_out_iounmap
;
3153 err
= sky2_reset(hw
);
3155 goto err_out_iounmap
;
3157 printk(KERN_INFO PFX
"v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3158 DRV_VERSION
, pci_resource_start(pdev
, 0), pdev
->irq
,
3159 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3160 hw
->chip_id
, hw
->chip_rev
);
3162 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3164 goto err_out_free_pci
;
3166 err
= register_netdev(dev
);
3168 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3170 goto err_out_free_netdev
;
3173 sky2_show_addr(dev
);
3175 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3176 if (register_netdev(dev1
) == 0)
3177 sky2_show_addr(dev1
);
3179 /* Failure to register second port need not be fatal */
3180 printk(KERN_WARNING PFX
3181 "register of second port failed\n");
3187 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3188 err
= sky2_test_msi(hw
);
3189 if (err
== -EOPNOTSUPP
)
3190 pci_disable_msi(pdev
);
3192 goto err_out_unregister
;
3195 err
= request_irq(pdev
->irq
, sky2_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3197 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3198 pci_name(pdev
), pdev
->irq
);
3199 goto err_out_unregister
;
3202 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3204 pci_set_drvdata(pdev
, hw
);
3209 pci_disable_msi(pdev
);
3211 unregister_netdev(dev1
);
3214 unregister_netdev(dev
);
3215 err_out_free_netdev
:
3218 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3219 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3224 err_out_free_regions
:
3225 pci_release_regions(pdev
);
3226 pci_disable_device(pdev
);
3231 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3233 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3234 struct net_device
*dev0
, *dev1
;
3242 unregister_netdev(dev1
);
3243 unregister_netdev(dev0
);
3245 sky2_write32(hw
, B0_IMSK
, 0);
3246 sky2_set_power_state(hw
, PCI_D3hot
);
3247 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3248 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3249 sky2_read8(hw
, B0_CTST
);
3251 free_irq(pdev
->irq
, hw
);
3252 pci_disable_msi(pdev
);
3253 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3254 pci_release_regions(pdev
);
3255 pci_disable_device(pdev
);
3263 pci_set_drvdata(pdev
, NULL
);
3267 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3269 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3272 for (i
= 0; i
< 2; i
++) {
3273 struct net_device
*dev
= hw
->dev
[i
];
3276 if (!netif_running(dev
))
3280 netif_device_detach(dev
);
3284 return sky2_set_power_state(hw
, pci_choose_state(pdev
, state
));
3287 static int sky2_resume(struct pci_dev
*pdev
)
3289 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3292 pci_restore_state(pdev
);
3293 pci_enable_wake(pdev
, PCI_D0
, 0);
3294 err
= sky2_set_power_state(hw
, PCI_D0
);
3298 err
= sky2_reset(hw
);
3302 for (i
= 0; i
< 2; i
++) {
3303 struct net_device
*dev
= hw
->dev
[i
];
3304 if (dev
&& netif_running(dev
)) {
3305 netif_device_attach(dev
);
3308 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3320 static struct pci_driver sky2_driver
= {
3322 .id_table
= sky2_id_table
,
3323 .probe
= sky2_probe
,
3324 .remove
= __devexit_p(sky2_remove
),
3326 .suspend
= sky2_suspend
,
3327 .resume
= sky2_resume
,
3331 static int __init
sky2_init_module(void)
3333 return pci_register_driver(&sky2_driver
);
3336 static void __exit
sky2_cleanup_module(void)
3338 pci_unregister_driver(&sky2_driver
);
3341 module_init(sky2_init_module
);
3342 module_exit(sky2_cleanup_module
);
3344 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3345 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3346 MODULE_LICENSE("GPL");
3347 MODULE_VERSION(DRV_VERSION
);