2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.13"
53 #define PFX DRV_NAME " "
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81 static const u32 default_msg
=
82 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
83 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
86 static int debug
= -1; /* defaults above */
87 module_param(debug
, int, 0);
88 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly
= 128;
91 module_param(copybreak
, int, 0);
92 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
94 static int disable_msi
= 0;
95 module_param(disable_msi
, int, 0);
96 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
98 static int idle_timeout
= 0;
99 module_param(idle_timeout
, int, 0);
100 MODULE_PARM_DESC(idle_timeout
, "Watchdog timer for lost interrupts (ms)");
102 static const struct pci_device_id sky2_id_table
[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
127 /* This device causes data corruption problems that are not resolved */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
139 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
141 /* Avoid conditionals by using array */
142 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
143 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
144 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
146 /* This driver supports yukon2 chipset only */
147 static const char *yukon2_name
[] = {
149 "EC Ultra", /* 0xb4 */
150 "Extreme", /* 0xb5 */
155 /* Access to external PHY */
156 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
160 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
161 gma_write16(hw
, port
, GM_SMI_CTRL
,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
164 for (i
= 0; i
< PHY_RETRIES
; i
++) {
165 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
170 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
174 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
178 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
179 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
181 for (i
= 0; i
< PHY_RETRIES
; i
++) {
182 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
183 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
193 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
197 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
198 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
203 static void sky2_power_on(struct sky2_hw
*hw
)
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw
, B0_POWER_CTRL
,
207 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
209 /* disable Core Clock Division, */
210 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
212 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
213 /* enable bits are inverted */
214 sky2_write8(hw
, B2_Y2_CLK_GATE
,
215 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
216 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
217 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
219 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
221 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
224 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
225 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
226 reg1
&= P_ASPM_CONTROL_MSK
;
227 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
228 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
232 static void sky2_power_aux(struct sky2_hw
*hw
)
234 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
235 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
237 /* enable bits are inverted */
238 sky2_write8(hw
, B2_Y2_CLK_GATE
,
239 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
240 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
241 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
243 /* switch power to VAUX */
244 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
245 sky2_write8(hw
, B0_POWER_CTRL
,
246 (PC_VAUX_ENA
| PC_VCC_ENA
|
247 PC_VAUX_ON
| PC_VCC_OFF
));
250 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
254 /* disable all GMAC IRQ's */
255 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
256 /* disable PHY IRQs */
257 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
259 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
260 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
261 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
262 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
264 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
265 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
266 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
269 /* flow control to advertise bits */
270 static const u16 copper_fc_adv
[] = {
272 [FC_TX
] = PHY_M_AN_ASP
,
273 [FC_RX
] = PHY_M_AN_PC
,
274 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
277 /* flow control to advertise bits when using 1000BaseX */
278 static const u16 fiber_fc_adv
[] = {
279 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
280 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
281 [FC_RX
] = PHY_M_P_SYM_MD_X
,
282 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
285 /* flow control to GMA disable bits */
286 static const u16 gm_fc_disable
[] = {
287 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
288 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
289 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
294 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
296 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
297 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
299 if (sky2
->autoneg
== AUTONEG_ENABLE
300 && !(hw
->chip_id
== CHIP_ID_YUKON_XL
301 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
302 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
303 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
305 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
307 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
309 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
310 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
312 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
314 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
317 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
318 if (sky2_is_copper(hw
)) {
319 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
320 /* enable automatic crossover */
321 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
323 /* disable energy detect */
324 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
326 /* enable automatic crossover */
327 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
329 if (sky2
->autoneg
== AUTONEG_ENABLE
330 && (hw
->chip_id
== CHIP_ID_YUKON_XL
331 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
332 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
333 ctrl
&= ~PHY_M_PC_DSC_MSK
;
334 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
338 /* workaround for deviation #4.88 (CRC errors) */
339 /* disable Automatic Crossover */
341 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
344 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
346 /* special setup for PHY 88E1112 Fiber */
347 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
348 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
350 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
351 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
352 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
353 ctrl
&= ~PHY_M_MAC_MD_MSK
;
354 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
355 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
357 if (hw
->pmd_type
== 'P') {
358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
361 /* for SFP-module set SIGDET polarity to low */
362 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
363 ctrl
|= PHY_M_FIB_SIGD_POL
;
364 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
367 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
375 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
376 if (sky2_is_copper(hw
)) {
377 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
378 ct1000
|= PHY_M_1000C_AFD
;
379 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
380 ct1000
|= PHY_M_1000C_AHD
;
381 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
382 adv
|= PHY_M_AN_100_FD
;
383 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
384 adv
|= PHY_M_AN_100_HD
;
385 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
386 adv
|= PHY_M_AN_10_FD
;
387 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
388 adv
|= PHY_M_AN_10_HD
;
390 adv
|= copper_fc_adv
[sky2
->flow_mode
];
391 } else { /* special defines for FIBER (88E1040S only) */
392 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
393 adv
|= PHY_M_AN_1000X_AFD
;
394 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
395 adv
|= PHY_M_AN_1000X_AHD
;
397 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
400 /* Restart Auto-negotiation */
401 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
403 /* forced speed/duplex settings */
404 ct1000
= PHY_M_1000C_MSE
;
406 /* Disable auto update for duplex flow control and speed */
407 reg
|= GM_GPCR_AU_ALL_DIS
;
409 switch (sky2
->speed
) {
411 ctrl
|= PHY_CT_SP1000
;
412 reg
|= GM_GPCR_SPEED_1000
;
415 ctrl
|= PHY_CT_SP100
;
416 reg
|= GM_GPCR_SPEED_100
;
420 if (sky2
->duplex
== DUPLEX_FULL
) {
421 reg
|= GM_GPCR_DUP_FULL
;
422 ctrl
|= PHY_CT_DUP_MD
;
423 } else if (sky2
->speed
< SPEED_1000
)
424 sky2
->flow_mode
= FC_NONE
;
427 reg
|= gm_fc_disable
[sky2
->flow_mode
];
429 /* Forward pause packets to GMAC? */
430 if (sky2
->flow_mode
& FC_RX
)
431 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
433 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
436 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
438 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
439 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
441 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
442 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
444 /* Setup Phy LED's */
445 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
448 switch (hw
->chip_id
) {
449 case CHIP_ID_YUKON_FE
:
450 /* on 88E3082 these bits are at 11..9 (shifted left) */
451 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
453 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
455 /* delete ACT LED control bits */
456 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
457 /* change ACT LED control to blink mode */
458 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
459 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
462 case CHIP_ID_YUKON_XL
:
463 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
465 /* select page 3 to access LED control register */
466 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
468 /* set LED Function Control register */
469 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
470 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
471 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
472 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
473 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
475 /* set Polarity Control register */
476 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
477 (PHY_M_POLC_LS1_P_MIX(4) |
478 PHY_M_POLC_IS0_P_MIX(4) |
479 PHY_M_POLC_LOS_CTRL(2) |
480 PHY_M_POLC_INIT_CTRL(2) |
481 PHY_M_POLC_STA1_CTRL(2) |
482 PHY_M_POLC_STA0_CTRL(2)));
484 /* restore page register */
485 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
488 case CHIP_ID_YUKON_EC_U
:
489 case CHIP_ID_YUKON_EX
:
490 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
492 /* select page 3 to access LED control register */
493 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
495 /* set LED Function Control register */
496 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
497 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
498 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
499 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
500 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
502 /* set Blink Rate in LED Timer Control Register */
503 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
504 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
505 /* restore page register */
506 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
510 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
511 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
512 /* turn off the Rx LED (LED_RX) */
513 ledover
&= ~PHY_M_LED_MO_RX
;
516 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
517 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
518 /* apply fixes in PHY AFE */
519 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
521 /* increase differential signal amplitude in 10BASE-T */
522 gm_phy_write(hw
, port
, 0x18, 0xaa99);
523 gm_phy_write(hw
, port
, 0x17, 0x2011);
525 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
526 gm_phy_write(hw
, port
, 0x18, 0xa204);
527 gm_phy_write(hw
, port
, 0x17, 0x2002);
529 /* set page register to 0 */
530 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
531 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
532 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
534 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
535 /* turn on 100 Mbps LED (LED_LINK100) */
536 ledover
|= PHY_M_LED_MO_100
;
540 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
544 /* Enable phy interrupt on auto-negotiation complete (or link up) */
545 if (sky2
->autoneg
== AUTONEG_ENABLE
)
546 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
548 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
551 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
554 static const u32 phy_power
[]
555 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
557 /* looks like this XL is back asswards .. */
558 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
561 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
562 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
564 /* Turn off phy power saving */
565 reg1
&= ~phy_power
[port
];
567 reg1
|= phy_power
[port
];
569 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
570 sky2_pci_read32(hw
, PCI_DEV_REG1
);
571 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
575 /* Force a renegotiation */
576 static void sky2_phy_reinit(struct sky2_port
*sky2
)
578 spin_lock_bh(&sky2
->phy_lock
);
579 sky2_phy_init(sky2
->hw
, sky2
->port
);
580 spin_unlock_bh(&sky2
->phy_lock
);
583 /* Put device in state to listen for Wake On Lan */
584 static void sky2_wol_init(struct sky2_port
*sky2
)
586 struct sky2_hw
*hw
= sky2
->hw
;
587 unsigned port
= sky2
->port
;
588 enum flow_control save_mode
;
592 /* Bring hardware out of reset */
593 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
594 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
596 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
597 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
600 * sky2_reset will re-enable on resume
602 save_mode
= sky2
->flow_mode
;
603 ctrl
= sky2
->advertising
;
605 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
606 sky2
->flow_mode
= FC_NONE
;
607 sky2_phy_power(hw
, port
, 1);
608 sky2_phy_reinit(sky2
);
610 sky2
->flow_mode
= save_mode
;
611 sky2
->advertising
= ctrl
;
613 /* Set GMAC to no flow control and auto update for speed/duplex */
614 gma_write16(hw
, port
, GM_GP_CTRL
,
615 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
616 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
618 /* Set WOL address */
619 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
620 sky2
->netdev
->dev_addr
, ETH_ALEN
);
622 /* Turn on appropriate WOL control bits */
623 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
625 if (sky2
->wol
& WAKE_PHY
)
626 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
628 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
630 if (sky2
->wol
& WAKE_MAGIC
)
631 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
633 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
635 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
636 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
638 /* Turn on legacy PCI-Express PME mode */
639 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
640 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
641 reg1
|= PCI_Y2_PME_LEGACY
;
642 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
643 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
646 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
650 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
652 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
655 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
657 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
658 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
660 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
662 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
663 /* WA DEV_472 -- looks like crossed wires on port 2 */
664 /* clear GMAC 1 Control reset */
665 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
667 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
668 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
669 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
670 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
671 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
674 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
676 /* Enable Transmit FIFO Underrun */
677 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
679 spin_lock_bh(&sky2
->phy_lock
);
680 sky2_phy_init(hw
, port
);
681 spin_unlock_bh(&sky2
->phy_lock
);
684 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
685 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
687 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
688 gma_read16(hw
, port
, i
);
689 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
691 /* transmit control */
692 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
694 /* receive control reg: unicast + multicast + no FCS */
695 gma_write16(hw
, port
, GM_RX_CTRL
,
696 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
698 /* transmit flow control */
699 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
701 /* transmit parameter */
702 gma_write16(hw
, port
, GM_TX_PARAM
,
703 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
704 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
705 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
706 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
708 /* serial mode register */
709 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
710 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
712 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
713 reg
|= GM_SMOD_JUMBO_ENA
;
715 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
717 /* virtual address for data */
718 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
720 /* physical address: used for pause frames */
721 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
723 /* ignore counter overflows */
724 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
725 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
726 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
728 /* Configure Rx MAC FIFO */
729 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
730 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
731 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
733 /* Flush Rx MAC FIFO on any flow control or error */
734 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
736 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
737 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
739 /* Configure Tx MAC FIFO */
740 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
741 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
743 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
744 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
745 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
746 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
747 /* set Tx GMAC FIFO Almost Empty Threshold */
748 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
749 /* Disable Store & Forward mode for TX */
750 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
756 /* Assign Ram Buffer allocation to queue */
757 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
761 /* convert from K bytes to qwords used for hw register */
764 end
= start
+ space
- 1;
766 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
767 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
768 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
769 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
770 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
772 if (q
== Q_R1
|| q
== Q_R2
) {
773 u32 tp
= space
- space
/4;
775 /* On receive queue's set the thresholds
776 * give receiver priority when > 3/4 full
777 * send pause when down to 2K
779 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
780 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
783 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
784 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
786 /* Enable store & forward on Tx queue's because
787 * Tx FIFO is only 1K on Yukon
789 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
792 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
793 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
796 /* Setup Bus Memory Interface */
797 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
799 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
800 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
801 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
802 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
805 /* Setup prefetch unit registers. This is the interface between
806 * hardware and driver list elements
808 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
811 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
812 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
813 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
814 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
815 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
816 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
818 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
821 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
823 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
825 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
830 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
831 struct sky2_tx_le
*le
)
833 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
836 /* Update chip's next pointer */
837 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
839 q
= Y2_QADDR(q
, PREF_UNIT_PUT_IDX
);
841 sky2_write16(hw
, q
, idx
);
846 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
848 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
849 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
854 /* Return high part of DMA address (could be 32 or 64 bit) */
855 static inline u32
high32(dma_addr_t a
)
857 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
860 /* Build description to hardware for one receive segment */
861 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
862 dma_addr_t map
, unsigned len
)
864 struct sky2_rx_le
*le
;
865 u32 hi
= high32(map
);
867 if (sky2
->rx_addr64
!= hi
) {
868 le
= sky2_next_rx(sky2
);
869 le
->addr
= cpu_to_le32(hi
);
870 le
->opcode
= OP_ADDR64
| HW_OWNER
;
871 sky2
->rx_addr64
= high32(map
+ len
);
874 le
= sky2_next_rx(sky2
);
875 le
->addr
= cpu_to_le32((u32
) map
);
876 le
->length
= cpu_to_le16(len
);
877 le
->opcode
= op
| HW_OWNER
;
880 /* Build description to hardware for one possibly fragmented skb */
881 static void sky2_rx_submit(struct sky2_port
*sky2
,
882 const struct rx_ring_info
*re
)
886 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
888 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
889 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
893 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
896 struct sk_buff
*skb
= re
->skb
;
899 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
900 pci_unmap_len_set(re
, data_size
, size
);
902 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
903 re
->frag_addr
[i
] = pci_map_page(pdev
,
904 skb_shinfo(skb
)->frags
[i
].page
,
905 skb_shinfo(skb
)->frags
[i
].page_offset
,
906 skb_shinfo(skb
)->frags
[i
].size
,
910 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
912 struct sk_buff
*skb
= re
->skb
;
915 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
918 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
919 pci_unmap_page(pdev
, re
->frag_addr
[i
],
920 skb_shinfo(skb
)->frags
[i
].size
,
924 /* Tell chip where to start receive checksum.
925 * Actually has two checksums, but set both same to avoid possible byte
928 static void rx_set_checksum(struct sky2_port
*sky2
)
930 struct sky2_rx_le
*le
;
932 le
= sky2_next_rx(sky2
);
933 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
935 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
937 sky2_write32(sky2
->hw
,
938 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
939 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
944 * The RX Stop command will not work for Yukon-2 if the BMU does not
945 * reach the end of packet and since we can't make sure that we have
946 * incoming data, we must reset the BMU while it is not doing a DMA
947 * transfer. Since it is possible that the RX path is still active,
948 * the RX RAM buffer will be stopped first, so any possible incoming
949 * data will not trigger a DMA. After the RAM buffer is stopped, the
950 * BMU is polled until any DMA in progress is ended and only then it
953 static void sky2_rx_stop(struct sky2_port
*sky2
)
955 struct sky2_hw
*hw
= sky2
->hw
;
956 unsigned rxq
= rxqaddr
[sky2
->port
];
959 /* disable the RAM Buffer receive queue */
960 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
962 for (i
= 0; i
< 0xffff; i
++)
963 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
964 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
967 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
970 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
972 /* reset the Rx prefetch unit */
973 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
976 /* Clean out receive buffer area, assumes receiver hardware stopped */
977 static void sky2_rx_clean(struct sky2_port
*sky2
)
981 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
982 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
983 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
986 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
993 /* Basic MII support */
994 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
996 struct mii_ioctl_data
*data
= if_mii(ifr
);
997 struct sky2_port
*sky2
= netdev_priv(dev
);
998 struct sky2_hw
*hw
= sky2
->hw
;
999 int err
= -EOPNOTSUPP
;
1001 if (!netif_running(dev
))
1002 return -ENODEV
; /* Phy still in reset */
1006 data
->phy_id
= PHY_ADDR_MARV
;
1012 spin_lock_bh(&sky2
->phy_lock
);
1013 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1014 spin_unlock_bh(&sky2
->phy_lock
);
1016 data
->val_out
= val
;
1021 if (!capable(CAP_NET_ADMIN
))
1024 spin_lock_bh(&sky2
->phy_lock
);
1025 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1027 spin_unlock_bh(&sky2
->phy_lock
);
1033 #ifdef SKY2_VLAN_TAG_USED
1034 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1036 struct sky2_port
*sky2
= netdev_priv(dev
);
1037 struct sky2_hw
*hw
= sky2
->hw
;
1038 u16 port
= sky2
->port
;
1040 netif_tx_lock_bh(dev
);
1042 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
1043 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
1046 netif_tx_unlock_bh(dev
);
1049 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
1051 struct sky2_port
*sky2
= netdev_priv(dev
);
1052 struct sky2_hw
*hw
= sky2
->hw
;
1053 u16 port
= sky2
->port
;
1055 netif_tx_lock_bh(dev
);
1057 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
1058 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
1059 vlan_group_set_device(sky2
->vlgrp
, vid
, NULL
);
1061 netif_tx_unlock_bh(dev
);
1066 * Allocate an skb for receiving. If the MTU is large enough
1067 * make the skb non-linear with a fragment list of pages.
1069 * It appears the hardware has a bug in the FIFO logic that
1070 * cause it to hang if the FIFO gets overrun and the receive buffer
1071 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1072 * aligned except if slab debugging is enabled.
1074 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1076 struct sk_buff
*skb
;
1080 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1084 p
= (unsigned long) skb
->data
;
1085 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1087 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1088 struct page
*page
= alloc_page(GFP_ATOMIC
);
1092 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1103 * Allocate and setup receiver buffer pool.
1104 * Normal case this ends up creating one list element for skb
1105 * in the receive ring. Worst case if using large MTU and each
1106 * allocation falls on a different 64 bit region, that results
1107 * in 6 list elements per ring entry.
1108 * One element is used for checksum enable/disable, and one
1109 * extra to avoid wrap.
1111 static int sky2_rx_start(struct sky2_port
*sky2
)
1113 struct sky2_hw
*hw
= sky2
->hw
;
1114 struct rx_ring_info
*re
;
1115 unsigned rxq
= rxqaddr
[sky2
->port
];
1116 unsigned i
, size
, space
, thresh
;
1118 sky2
->rx_put
= sky2
->rx_next
= 0;
1121 /* On PCI express lowering the watermark gives better performance */
1122 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1123 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1125 /* These chips have no ram buffer?
1126 * MAC Rx RAM Read is controlled by hardware */
1127 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1128 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1129 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1130 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
1132 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1134 rx_set_checksum(sky2
);
1136 /* Space needed for frame data + headers rounded up */
1137 size
= ALIGN(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8)
1140 /* Stopping point for hardware truncation */
1141 thresh
= (size
- 8) / sizeof(u32
);
1143 /* Account for overhead of skb - to avoid order > 0 allocation */
1144 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1145 + sizeof(struct skb_shared_info
);
1147 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1148 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1150 if (sky2
->rx_nfrags
!= 0) {
1151 /* Compute residue after pages */
1152 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1159 /* Optimize to handle small packets and headers */
1160 if (size
< copybreak
)
1162 if (size
< ETH_HLEN
)
1165 sky2
->rx_data_size
= size
;
1168 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1169 re
= sky2
->rx_ring
+ i
;
1171 re
->skb
= sky2_rx_alloc(sky2
);
1175 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1176 sky2_rx_submit(sky2
, re
);
1180 * The receiver hangs if it receives frames larger than the
1181 * packet buffer. As a workaround, truncate oversize frames, but
1182 * the register is limited to 9 bits, so if you do frames > 2052
1183 * you better get the MTU right!
1186 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1188 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1189 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1192 /* Tell chip about available buffers */
1193 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1196 sky2_rx_clean(sky2
);
1200 /* Bring up network interface. */
1201 static int sky2_up(struct net_device
*dev
)
1203 struct sky2_port
*sky2
= netdev_priv(dev
);
1204 struct sky2_hw
*hw
= sky2
->hw
;
1205 unsigned port
= sky2
->port
;
1207 int cap
, err
= -ENOMEM
;
1208 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1211 * On dual port PCI-X card, there is an problem where status
1212 * can be received out of order due to split transactions
1214 if (otherdev
&& netif_running(otherdev
) &&
1215 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1216 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1219 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1220 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1221 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1227 if (netif_msg_ifup(sky2
))
1228 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1230 /* must be power of 2 */
1231 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1233 sizeof(struct sky2_tx_le
),
1238 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1242 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1244 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1248 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1250 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1255 sky2_phy_power(hw
, port
, 1);
1257 sky2_mac_init(hw
, port
);
1259 /* Register is number of 4K blocks on internal RAM buffer. */
1260 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1261 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1267 rxspace
= ramsize
/ 2;
1269 rxspace
= 8 + (2*(ramsize
- 16))/3;
1271 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1272 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1274 /* Make sure SyncQ is disabled */
1275 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1279 sky2_qset(hw
, txqaddr
[port
]);
1281 /* Set almost empty threshold */
1282 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1283 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1284 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1286 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1289 err
= sky2_rx_start(sky2
);
1293 /* Enable interrupts from phy/mac for port */
1294 imask
= sky2_read32(hw
, B0_IMSK
);
1295 imask
|= portirq_msk
[port
];
1296 sky2_write32(hw
, B0_IMSK
, imask
);
1302 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1303 sky2
->rx_le
, sky2
->rx_le_map
);
1307 pci_free_consistent(hw
->pdev
,
1308 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1309 sky2
->tx_le
, sky2
->tx_le_map
);
1312 kfree(sky2
->tx_ring
);
1313 kfree(sky2
->rx_ring
);
1315 sky2
->tx_ring
= NULL
;
1316 sky2
->rx_ring
= NULL
;
1320 /* Modular subtraction in ring */
1321 static inline int tx_dist(unsigned tail
, unsigned head
)
1323 return (head
- tail
) & (TX_RING_SIZE
- 1);
1326 /* Number of list elements available for next tx */
1327 static inline int tx_avail(const struct sky2_port
*sky2
)
1329 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1332 /* Estimate of number of transmit list elements required */
1333 static unsigned tx_le_req(const struct sk_buff
*skb
)
1337 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1338 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1340 if (skb_is_gso(skb
))
1343 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1350 * Put one packet in ring for transmit.
1351 * A single packet can generate multiple list elements, and
1352 * the number of ring elements will probably be less than the number
1353 * of list elements used.
1355 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1357 struct sky2_port
*sky2
= netdev_priv(dev
);
1358 struct sky2_hw
*hw
= sky2
->hw
;
1359 struct sky2_tx_le
*le
= NULL
;
1360 struct tx_ring_info
*re
;
1367 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1368 return NETDEV_TX_BUSY
;
1370 if (unlikely(netif_msg_tx_queued(sky2
)))
1371 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1372 dev
->name
, sky2
->tx_prod
, skb
->len
);
1374 len
= skb_headlen(skb
);
1375 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1376 addr64
= high32(mapping
);
1378 /* Send high bits if changed or crosses boundary */
1379 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1380 le
= get_tx_le(sky2
);
1381 le
->addr
= cpu_to_le32(addr64
);
1382 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1383 sky2
->tx_addr64
= high32(mapping
+ len
);
1386 /* Check for TCP Segmentation Offload */
1387 mss
= skb_shinfo(skb
)->gso_size
;
1389 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1390 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1393 if (mss
!= sky2
->tx_last_mss
) {
1394 le
= get_tx_le(sky2
);
1395 le
->addr
= cpu_to_le32(mss
);
1396 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1397 sky2
->tx_last_mss
= mss
;
1402 #ifdef SKY2_VLAN_TAG_USED
1403 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1404 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1406 le
= get_tx_le(sky2
);
1408 le
->opcode
= OP_VLAN
|HW_OWNER
;
1410 le
->opcode
|= OP_VLAN
;
1411 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1416 /* Handle TCP checksum offload */
1417 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1418 unsigned offset
= skb
->h
.raw
- skb
->data
;
1421 tcpsum
= offset
<< 16; /* sum start */
1422 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1424 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1425 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1428 if (tcpsum
!= sky2
->tx_tcpsum
) {
1429 sky2
->tx_tcpsum
= tcpsum
;
1431 le
= get_tx_le(sky2
);
1432 le
->addr
= cpu_to_le32(tcpsum
);
1433 le
->length
= 0; /* initial checksum value */
1434 le
->ctrl
= 1; /* one packet */
1435 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1439 le
= get_tx_le(sky2
);
1440 le
->addr
= cpu_to_le32((u32
) mapping
);
1441 le
->length
= cpu_to_le16(len
);
1443 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1445 re
= tx_le_re(sky2
, le
);
1447 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1448 pci_unmap_len_set(re
, maplen
, len
);
1450 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1451 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1453 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1454 frag
->size
, PCI_DMA_TODEVICE
);
1455 addr64
= high32(mapping
);
1456 if (addr64
!= sky2
->tx_addr64
) {
1457 le
= get_tx_le(sky2
);
1458 le
->addr
= cpu_to_le32(addr64
);
1460 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1461 sky2
->tx_addr64
= addr64
;
1464 le
= get_tx_le(sky2
);
1465 le
->addr
= cpu_to_le32((u32
) mapping
);
1466 le
->length
= cpu_to_le16(frag
->size
);
1468 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1470 re
= tx_le_re(sky2
, le
);
1472 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1473 pci_unmap_len_set(re
, maplen
, frag
->size
);
1478 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1479 netif_stop_queue(dev
);
1481 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1483 dev
->trans_start
= jiffies
;
1484 return NETDEV_TX_OK
;
1488 * Free ring elements from starting at tx_cons until "done"
1490 * NB: the hardware will tell us about partial completion of multi-part
1491 * buffers so make sure not to free skb to early.
1493 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1495 struct net_device
*dev
= sky2
->netdev
;
1496 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1499 BUG_ON(done
>= TX_RING_SIZE
);
1501 for (idx
= sky2
->tx_cons
; idx
!= done
;
1502 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1503 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1504 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1506 switch(le
->opcode
& ~HW_OWNER
) {
1509 pci_unmap_single(pdev
,
1510 pci_unmap_addr(re
, mapaddr
),
1511 pci_unmap_len(re
, maplen
),
1515 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1516 pci_unmap_len(re
, maplen
),
1521 if (le
->ctrl
& EOP
) {
1522 if (unlikely(netif_msg_tx_done(sky2
)))
1523 printk(KERN_DEBUG
"%s: tx done %u\n",
1525 sky2
->net_stats
.tx_packets
++;
1526 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1528 dev_kfree_skb_any(re
->skb
);
1531 le
->opcode
= 0; /* paranoia */
1534 sky2
->tx_cons
= idx
;
1535 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1536 netif_wake_queue(dev
);
1539 /* Cleanup all untransmitted buffers, assume transmitter not running */
1540 static void sky2_tx_clean(struct net_device
*dev
)
1542 struct sky2_port
*sky2
= netdev_priv(dev
);
1544 netif_tx_lock_bh(dev
);
1545 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1546 netif_tx_unlock_bh(dev
);
1549 /* Network shutdown */
1550 static int sky2_down(struct net_device
*dev
)
1552 struct sky2_port
*sky2
= netdev_priv(dev
);
1553 struct sky2_hw
*hw
= sky2
->hw
;
1554 unsigned port
= sky2
->port
;
1558 /* Never really got started! */
1562 if (netif_msg_ifdown(sky2
))
1563 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1565 /* Stop more packets from being queued */
1566 netif_stop_queue(dev
);
1567 netif_carrier_off(dev
);
1569 /* Disable port IRQ */
1570 imask
= sky2_read32(hw
, B0_IMSK
);
1571 imask
&= ~portirq_msk
[port
];
1572 sky2_write32(hw
, B0_IMSK
, imask
);
1575 * Both ports share the NAPI poll on port 0, so if necessary undo the
1576 * the disable that is done in dev_close.
1578 if (sky2
->port
== 0 && hw
->ports
> 1)
1579 netif_poll_enable(dev
);
1581 sky2_gmac_reset(hw
, port
);
1583 /* Stop transmitter */
1584 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1585 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1587 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1588 RB_RST_SET
| RB_DIS_OP_MD
);
1590 /* WA for dev. #4.209 */
1591 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1592 && (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
|| hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1593 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1594 sky2
->speed
!= SPEED_1000
?
1595 TX_STFW_ENA
: TX_STFW_DIS
);
1597 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1598 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1599 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1601 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1603 /* Workaround shared GMAC reset */
1604 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1605 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1606 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1608 /* Disable Force Sync bit and Enable Alloc bit */
1609 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1610 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1612 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1613 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1614 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1616 /* Reset the PCI FIFO of the async Tx queue */
1617 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1618 BMU_RST_SET
| BMU_FIFO_RST
);
1620 /* Reset the Tx prefetch units */
1621 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1624 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1628 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1629 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1631 sky2_phy_power(hw
, port
, 0);
1633 /* turn off LED's */
1634 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1636 synchronize_irq(hw
->pdev
->irq
);
1639 sky2_rx_clean(sky2
);
1641 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1642 sky2
->rx_le
, sky2
->rx_le_map
);
1643 kfree(sky2
->rx_ring
);
1645 pci_free_consistent(hw
->pdev
,
1646 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1647 sky2
->tx_le
, sky2
->tx_le_map
);
1648 kfree(sky2
->tx_ring
);
1653 sky2
->rx_ring
= NULL
;
1654 sky2
->tx_ring
= NULL
;
1659 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1661 if (!sky2_is_copper(hw
))
1664 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1665 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1667 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1668 case PHY_M_PS_SPEED_1000
:
1670 case PHY_M_PS_SPEED_100
:
1677 static void sky2_link_up(struct sky2_port
*sky2
)
1679 struct sky2_hw
*hw
= sky2
->hw
;
1680 unsigned port
= sky2
->port
;
1682 static const char *fc_name
[] = {
1690 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1691 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1692 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1694 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1696 netif_carrier_on(sky2
->netdev
);
1697 netif_wake_queue(sky2
->netdev
);
1699 /* Turn on link LED */
1700 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1701 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1703 if (hw
->chip_id
== CHIP_ID_YUKON_XL
1704 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
1705 || hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1706 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1707 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1709 switch(sky2
->speed
) {
1711 led
|= PHY_M_LEDC_INIT_CTRL(7);
1715 led
|= PHY_M_LEDC_STA1_CTRL(7);
1719 led
|= PHY_M_LEDC_STA0_CTRL(7);
1723 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1724 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1725 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1728 if (netif_msg_link(sky2
))
1729 printk(KERN_INFO PFX
1730 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1731 sky2
->netdev
->name
, sky2
->speed
,
1732 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1733 fc_name
[sky2
->flow_status
]);
1736 static void sky2_link_down(struct sky2_port
*sky2
)
1738 struct sky2_hw
*hw
= sky2
->hw
;
1739 unsigned port
= sky2
->port
;
1742 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1744 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1745 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1746 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1748 netif_carrier_off(sky2
->netdev
);
1749 netif_stop_queue(sky2
->netdev
);
1751 /* Turn on link LED */
1752 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1754 if (netif_msg_link(sky2
))
1755 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1757 sky2_phy_init(hw
, port
);
1760 static enum flow_control
sky2_flow(int rx
, int tx
)
1763 return tx
? FC_BOTH
: FC_RX
;
1765 return tx
? FC_TX
: FC_NONE
;
1768 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1770 struct sky2_hw
*hw
= sky2
->hw
;
1771 unsigned port
= sky2
->port
;
1774 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1775 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1776 if (lpa
& PHY_M_AN_RF
) {
1777 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1781 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1782 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1783 sky2
->netdev
->name
);
1787 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1788 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1790 /* Since the pause result bits seem to in different positions on
1791 * different chips. look at registers.
1793 if (!sky2_is_copper(hw
)) {
1794 /* Shift for bits in fiber PHY */
1795 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1796 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1798 if (advert
& ADVERTISE_1000XPAUSE
)
1799 advert
|= ADVERTISE_PAUSE_CAP
;
1800 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1801 advert
|= ADVERTISE_PAUSE_ASYM
;
1802 if (lpa
& LPA_1000XPAUSE
)
1803 lpa
|= LPA_PAUSE_CAP
;
1804 if (lpa
& LPA_1000XPAUSE_ASYM
)
1805 lpa
|= LPA_PAUSE_ASYM
;
1808 sky2
->flow_status
= FC_NONE
;
1809 if (advert
& ADVERTISE_PAUSE_CAP
) {
1810 if (lpa
& LPA_PAUSE_CAP
)
1811 sky2
->flow_status
= FC_BOTH
;
1812 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1813 sky2
->flow_status
= FC_RX
;
1814 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1815 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1816 sky2
->flow_status
= FC_TX
;
1819 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1820 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1821 sky2
->flow_status
= FC_NONE
;
1823 if (sky2
->flow_status
& FC_TX
)
1824 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1826 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1831 /* Interrupt from PHY */
1832 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1834 struct net_device
*dev
= hw
->dev
[port
];
1835 struct sky2_port
*sky2
= netdev_priv(dev
);
1836 u16 istatus
, phystat
;
1838 if (!netif_running(dev
))
1841 spin_lock(&sky2
->phy_lock
);
1842 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1843 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1845 if (netif_msg_intr(sky2
))
1846 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1847 sky2
->netdev
->name
, istatus
, phystat
);
1849 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1850 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1855 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1856 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1858 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1860 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1862 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1863 if (phystat
& PHY_M_PS_LINK_UP
)
1866 sky2_link_down(sky2
);
1869 spin_unlock(&sky2
->phy_lock
);
1872 /* Transmit timeout is only called if we are running, carrier is up
1873 * and tx queue is full (stopped).
1875 static void sky2_tx_timeout(struct net_device
*dev
)
1877 struct sky2_port
*sky2
= netdev_priv(dev
);
1878 struct sky2_hw
*hw
= sky2
->hw
;
1880 if (netif_msg_timer(sky2
))
1881 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1883 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1884 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1885 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1886 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1888 /* can't restart safely under softirq */
1889 schedule_work(&hw
->restart_work
);
1892 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1894 struct sky2_port
*sky2
= netdev_priv(dev
);
1895 struct sky2_hw
*hw
= sky2
->hw
;
1900 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1903 /* TSO on Yukon Ultra and MTU > 1500 not supported */
1904 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1905 dev
->features
&= ~NETIF_F_TSO
;
1907 if (!netif_running(dev
)) {
1912 imask
= sky2_read32(hw
, B0_IMSK
);
1913 sky2_write32(hw
, B0_IMSK
, 0);
1915 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1916 netif_stop_queue(dev
);
1917 netif_poll_disable(hw
->dev
[0]);
1919 synchronize_irq(hw
->pdev
->irq
);
1921 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1922 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1924 sky2_rx_clean(sky2
);
1928 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1929 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1931 if (dev
->mtu
> ETH_DATA_LEN
)
1932 mode
|= GM_SMOD_JUMBO_ENA
;
1934 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1936 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1938 err
= sky2_rx_start(sky2
);
1939 sky2_write32(hw
, B0_IMSK
, imask
);
1944 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1946 netif_poll_enable(hw
->dev
[0]);
1947 netif_wake_queue(dev
);
1953 /* For small just reuse existing skb for next receive */
1954 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
1955 const struct rx_ring_info
*re
,
1958 struct sk_buff
*skb
;
1960 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
1962 skb_reserve(skb
, 2);
1963 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
1964 length
, PCI_DMA_FROMDEVICE
);
1965 memcpy(skb
->data
, re
->skb
->data
, length
);
1966 skb
->ip_summed
= re
->skb
->ip_summed
;
1967 skb
->csum
= re
->skb
->csum
;
1968 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
1969 length
, PCI_DMA_FROMDEVICE
);
1970 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1971 skb_put(skb
, length
);
1976 /* Adjust length of skb with fragments to match received data */
1977 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
1978 unsigned int length
)
1983 /* put header into skb */
1984 size
= min(length
, hdr_space
);
1989 num_frags
= skb_shinfo(skb
)->nr_frags
;
1990 for (i
= 0; i
< num_frags
; i
++) {
1991 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1994 /* don't need this page */
1995 __free_page(frag
->page
);
1996 --skb_shinfo(skb
)->nr_frags
;
1998 size
= min(length
, (unsigned) PAGE_SIZE
);
2001 skb
->data_len
+= size
;
2002 skb
->truesize
+= size
;
2009 /* Normal packet - take skb from ring element and put in a new one */
2010 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2011 struct rx_ring_info
*re
,
2012 unsigned int length
)
2014 struct sk_buff
*skb
, *nskb
;
2015 unsigned hdr_space
= sky2
->rx_data_size
;
2017 pr_debug(PFX
"receive new length=%d\n", length
);
2019 /* Don't be tricky about reusing pages (yet) */
2020 nskb
= sky2_rx_alloc(sky2
);
2021 if (unlikely(!nskb
))
2025 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2027 prefetch(skb
->data
);
2029 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2031 if (skb_shinfo(skb
)->nr_frags
)
2032 skb_put_frags(skb
, hdr_space
, length
);
2034 skb_put(skb
, length
);
2039 * Receive one packet.
2040 * For larger packets, get new buffer.
2042 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2043 u16 length
, u32 status
)
2045 struct sky2_port
*sky2
= netdev_priv(dev
);
2046 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2047 struct sk_buff
*skb
= NULL
;
2049 if (unlikely(netif_msg_rx_status(sky2
)))
2050 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2051 dev
->name
, sky2
->rx_next
, status
, length
);
2053 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2054 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2056 if (status
& GMR_FS_ANY_ERR
)
2059 if (!(status
& GMR_FS_RX_OK
))
2062 if (length
< copybreak
)
2063 skb
= receive_copy(sky2
, re
, length
);
2065 skb
= receive_new(sky2
, re
, length
);
2067 sky2_rx_submit(sky2
, re
);
2072 ++sky2
->net_stats
.rx_errors
;
2073 if (status
& GMR_FS_RX_FF_OV
) {
2074 sky2
->net_stats
.rx_over_errors
++;
2078 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2079 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2080 dev
->name
, status
, length
);
2082 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2083 sky2
->net_stats
.rx_length_errors
++;
2084 if (status
& GMR_FS_FRAGMENT
)
2085 sky2
->net_stats
.rx_frame_errors
++;
2086 if (status
& GMR_FS_CRC_ERR
)
2087 sky2
->net_stats
.rx_crc_errors
++;
2092 /* Transmit complete */
2093 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2095 struct sky2_port
*sky2
= netdev_priv(dev
);
2097 if (netif_running(dev
)) {
2099 sky2_tx_complete(sky2
, last
);
2100 netif_tx_unlock(dev
);
2104 /* Process status response ring */
2105 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2107 struct sky2_port
*sky2
;
2109 unsigned buf_write
[2] = { 0, 0 };
2110 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2114 while (hw
->st_idx
!= hwidx
) {
2115 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2116 struct net_device
*dev
;
2117 struct sk_buff
*skb
;
2121 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2123 BUG_ON(le
->link
>= 2);
2124 dev
= hw
->dev
[le
->link
];
2126 sky2
= netdev_priv(dev
);
2127 length
= le16_to_cpu(le
->length
);
2128 status
= le32_to_cpu(le
->status
);
2130 switch (le
->opcode
& ~HW_OWNER
) {
2132 skb
= sky2_receive(dev
, length
, status
);
2136 skb
->protocol
= eth_type_trans(skb
, dev
);
2137 sky2
->net_stats
.rx_packets
++;
2138 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2139 dev
->last_rx
= jiffies
;
2141 #ifdef SKY2_VLAN_TAG_USED
2142 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2143 vlan_hwaccel_receive_skb(skb
,
2145 be16_to_cpu(sky2
->rx_tag
));
2148 netif_receive_skb(skb
);
2150 /* Update receiver after 16 frames */
2151 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
2153 sky2_put_idx(hw
, rxqaddr
[le
->link
], sky2
->rx_put
);
2154 buf_write
[le
->link
] = 0;
2157 /* Stop after net poll weight */
2158 if (++work_done
>= to_do
)
2162 #ifdef SKY2_VLAN_TAG_USED
2164 sky2
->rx_tag
= length
;
2168 sky2
->rx_tag
= length
;
2175 /* Both checksum counters are programmed to start at
2176 * the same offset, so unless there is a problem they
2177 * should match. This failure is an early indication that
2178 * hardware receive checksumming won't work.
2180 if (likely(status
>> 16 == (status
& 0xffff))) {
2181 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2182 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2183 skb
->csum
= status
& 0xffff;
2185 printk(KERN_NOTICE PFX
"%s: hardware receive "
2186 "checksum problem (status = %#x)\n",
2189 sky2_write32(sky2
->hw
,
2190 Q_ADDR(rxqaddr
[le
->link
], Q_CSR
),
2196 /* TX index reports status for both ports */
2197 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2198 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2200 sky2_tx_done(hw
->dev
[1],
2201 ((status
>> 24) & 0xff)
2202 | (u16
)(length
& 0xf) << 8);
2206 if (net_ratelimit())
2207 printk(KERN_WARNING PFX
2208 "unknown status opcode 0x%x\n", le
->opcode
);
2213 /* Fully processed status ring so clear irq */
2214 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2218 sky2
= netdev_priv(hw
->dev
[0]);
2219 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2223 sky2
= netdev_priv(hw
->dev
[1]);
2224 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2230 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2232 struct net_device
*dev
= hw
->dev
[port
];
2234 if (net_ratelimit())
2235 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2238 if (status
& Y2_IS_PAR_RD1
) {
2239 if (net_ratelimit())
2240 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2243 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2246 if (status
& Y2_IS_PAR_WR1
) {
2247 if (net_ratelimit())
2248 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2251 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2254 if (status
& Y2_IS_PAR_MAC1
) {
2255 if (net_ratelimit())
2256 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2257 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2260 if (status
& Y2_IS_PAR_RX1
) {
2261 if (net_ratelimit())
2262 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2263 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2266 if (status
& Y2_IS_TCP_TXA1
) {
2267 if (net_ratelimit())
2268 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2270 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2274 static void sky2_hw_intr(struct sky2_hw
*hw
)
2276 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2278 if (status
& Y2_IS_TIST_OV
)
2279 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2281 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2284 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2285 if (net_ratelimit())
2286 dev_err(&hw
->pdev
->dev
, "PCI hardware error (0x%x)\n",
2289 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2290 sky2_pci_write16(hw
, PCI_STATUS
,
2291 pci_err
| PCI_STATUS_ERROR_BITS
);
2292 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2295 if (status
& Y2_IS_PCI_EXP
) {
2296 /* PCI-Express uncorrectable Error occurred */
2299 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2301 if (net_ratelimit())
2302 dev_err(&hw
->pdev
->dev
, "PCI Express error (0x%x)\n",
2305 /* clear the interrupt */
2306 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2307 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2309 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2311 if (pex_err
& PEX_FATAL_ERRORS
) {
2312 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2313 hwmsk
&= ~Y2_IS_PCI_EXP
;
2314 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2318 if (status
& Y2_HWE_L1_MASK
)
2319 sky2_hw_error(hw
, 0, status
);
2321 if (status
& Y2_HWE_L1_MASK
)
2322 sky2_hw_error(hw
, 1, status
);
2325 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2327 struct net_device
*dev
= hw
->dev
[port
];
2328 struct sky2_port
*sky2
= netdev_priv(dev
);
2329 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2331 if (netif_msg_intr(sky2
))
2332 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2335 if (status
& GM_IS_RX_FF_OR
) {
2336 ++sky2
->net_stats
.rx_fifo_errors
;
2337 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2340 if (status
& GM_IS_TX_FF_UR
) {
2341 ++sky2
->net_stats
.tx_fifo_errors
;
2342 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2346 /* This should never happen it is a fatal situation */
2347 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2348 const char *rxtx
, u32 mask
)
2350 struct net_device
*dev
= hw
->dev
[port
];
2351 struct sky2_port
*sky2
= netdev_priv(dev
);
2354 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2355 dev
? dev
->name
: "<not registered>", rxtx
);
2357 imask
= sky2_read32(hw
, B0_IMSK
);
2359 sky2_write32(hw
, B0_IMSK
, imask
);
2362 spin_lock(&sky2
->phy_lock
);
2363 sky2_link_down(sky2
);
2364 spin_unlock(&sky2
->phy_lock
);
2368 /* If idle then force a fake soft NAPI poll once a second
2369 * to work around cases where sharing an edge triggered interrupt.
2371 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2373 if (idle_timeout
> 0)
2374 mod_timer(&hw
->idle_timer
,
2375 jiffies
+ msecs_to_jiffies(idle_timeout
));
2378 static void sky2_idle(unsigned long arg
)
2380 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2381 struct net_device
*dev
= hw
->dev
[0];
2383 if (__netif_rx_schedule_prep(dev
))
2384 __netif_rx_schedule(dev
);
2386 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2390 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2392 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2393 int work_limit
= min(dev0
->quota
, *budget
);
2395 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2397 if (status
& Y2_IS_HW_ERR
)
2400 if (status
& Y2_IS_IRQ_PHY1
)
2401 sky2_phy_intr(hw
, 0);
2403 if (status
& Y2_IS_IRQ_PHY2
)
2404 sky2_phy_intr(hw
, 1);
2406 if (status
& Y2_IS_IRQ_MAC1
)
2407 sky2_mac_intr(hw
, 0);
2409 if (status
& Y2_IS_IRQ_MAC2
)
2410 sky2_mac_intr(hw
, 1);
2412 if (status
& Y2_IS_CHK_RX1
)
2413 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2415 if (status
& Y2_IS_CHK_RX2
)
2416 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2418 if (status
& Y2_IS_CHK_TXA1
)
2419 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2421 if (status
& Y2_IS_CHK_TXA2
)
2422 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2424 work_done
= sky2_status_intr(hw
, work_limit
);
2425 if (work_done
< work_limit
) {
2426 netif_rx_complete(dev0
);
2428 sky2_read32(hw
, B0_Y2_SP_LISR
);
2431 *budget
-= work_done
;
2432 dev0
->quota
-= work_done
;
2437 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2439 struct sky2_hw
*hw
= dev_id
;
2440 struct net_device
*dev0
= hw
->dev
[0];
2443 /* Reading this mask interrupts as side effect */
2444 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2445 if (status
== 0 || status
== ~0)
2448 prefetch(&hw
->st_le
[hw
->st_idx
]);
2449 if (likely(__netif_rx_schedule_prep(dev0
)))
2450 __netif_rx_schedule(dev0
);
2455 #ifdef CONFIG_NET_POLL_CONTROLLER
2456 static void sky2_netpoll(struct net_device
*dev
)
2458 struct sky2_port
*sky2
= netdev_priv(dev
);
2459 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2461 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2462 __netif_rx_schedule(dev0
);
2466 /* Chip internal frequency for clock calculations */
2467 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2469 switch (hw
->chip_id
) {
2470 case CHIP_ID_YUKON_EC
:
2471 case CHIP_ID_YUKON_EC_U
:
2472 case CHIP_ID_YUKON_EX
:
2473 return 125; /* 125 Mhz */
2474 case CHIP_ID_YUKON_FE
:
2475 return 100; /* 100 Mhz */
2476 default: /* YUKON_XL */
2477 return 156; /* 156 Mhz */
2481 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2483 return sky2_mhz(hw
) * us
;
2486 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2488 return clk
/ sky2_mhz(hw
);
2492 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2496 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2498 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2499 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2500 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2505 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2506 dev_warn(&hw
->pdev
->dev
, "this driver not yet tested on this chip type\n"
2507 "Please report success or failure to <netdev@vger.kernel.org>\n");
2509 /* Make sure and enable all clocks */
2510 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2511 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2513 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2515 /* This rev is really old, and requires untested workarounds */
2516 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2517 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2518 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2519 hw
->chip_id
, hw
->chip_rev
);
2523 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2525 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2526 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2527 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2534 static void sky2_reset(struct sky2_hw
*hw
)
2540 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2541 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2542 status
= sky2_read16(hw
, HCU_CCSR
);
2543 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2544 HCU_CCSR_UC_STATE_MSK
);
2545 sky2_write16(hw
, HCU_CCSR
, status
);
2547 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2548 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2552 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2553 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2555 /* clear PCI errors, if any */
2556 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2558 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2559 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2562 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2564 /* clear any PEX errors */
2565 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2566 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2571 for (i
= 0; i
< hw
->ports
; i
++) {
2572 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2573 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2576 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2578 /* Clear I2C IRQ noise */
2579 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2581 /* turn off hardware timer (unused) */
2582 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2583 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2585 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2587 /* Turn off descriptor polling */
2588 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2590 /* Turn off receive timestamp */
2591 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2592 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2594 /* enable the Tx Arbiters */
2595 for (i
= 0; i
< hw
->ports
; i
++)
2596 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2598 /* Initialize ram interface */
2599 for (i
= 0; i
< hw
->ports
; i
++) {
2600 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2602 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2603 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2604 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2605 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2606 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2607 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2608 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2609 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2610 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2611 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2612 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2613 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2616 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2618 for (i
= 0; i
< hw
->ports
; i
++)
2619 sky2_gmac_reset(hw
, i
);
2621 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2624 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2625 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2627 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2628 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2630 /* Set the list last index */
2631 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2633 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2634 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2636 /* set Status-FIFO ISR watermark */
2637 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2638 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2640 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2642 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2643 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2644 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2646 /* enable status unit */
2647 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2649 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2650 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2651 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2654 static void sky2_restart(struct work_struct
*work
)
2656 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2657 struct net_device
*dev
;
2660 dev_dbg(&hw
->pdev
->dev
, "restarting\n");
2662 del_timer_sync(&hw
->idle_timer
);
2665 sky2_write32(hw
, B0_IMSK
, 0);
2666 sky2_read32(hw
, B0_IMSK
);
2668 netif_poll_disable(hw
->dev
[0]);
2670 for (i
= 0; i
< hw
->ports
; i
++) {
2672 if (netif_running(dev
))
2677 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2678 netif_poll_enable(hw
->dev
[0]);
2680 for (i
= 0; i
< hw
->ports
; i
++) {
2682 if (netif_running(dev
)) {
2685 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2692 sky2_idle_start(hw
);
2697 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2699 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2702 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2704 const struct sky2_port
*sky2
= netdev_priv(dev
);
2706 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2707 wol
->wolopts
= sky2
->wol
;
2710 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2712 struct sky2_port
*sky2
= netdev_priv(dev
);
2713 struct sky2_hw
*hw
= sky2
->hw
;
2715 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2718 sky2
->wol
= wol
->wolopts
;
2720 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2721 sky2_write32(hw
, B0_CTST
, sky2
->wol
2722 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2724 if (!netif_running(dev
))
2725 sky2_wol_init(sky2
);
2729 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2731 if (sky2_is_copper(hw
)) {
2732 u32 modes
= SUPPORTED_10baseT_Half
2733 | SUPPORTED_10baseT_Full
2734 | SUPPORTED_100baseT_Half
2735 | SUPPORTED_100baseT_Full
2736 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2738 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2739 modes
|= SUPPORTED_1000baseT_Half
2740 | SUPPORTED_1000baseT_Full
;
2743 return SUPPORTED_1000baseT_Half
2744 | SUPPORTED_1000baseT_Full
2749 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2751 struct sky2_port
*sky2
= netdev_priv(dev
);
2752 struct sky2_hw
*hw
= sky2
->hw
;
2754 ecmd
->transceiver
= XCVR_INTERNAL
;
2755 ecmd
->supported
= sky2_supported_modes(hw
);
2756 ecmd
->phy_address
= PHY_ADDR_MARV
;
2757 if (sky2_is_copper(hw
)) {
2758 ecmd
->supported
= SUPPORTED_10baseT_Half
2759 | SUPPORTED_10baseT_Full
2760 | SUPPORTED_100baseT_Half
2761 | SUPPORTED_100baseT_Full
2762 | SUPPORTED_1000baseT_Half
2763 | SUPPORTED_1000baseT_Full
2764 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2765 ecmd
->port
= PORT_TP
;
2766 ecmd
->speed
= sky2
->speed
;
2768 ecmd
->speed
= SPEED_1000
;
2769 ecmd
->port
= PORT_FIBRE
;
2772 ecmd
->advertising
= sky2
->advertising
;
2773 ecmd
->autoneg
= sky2
->autoneg
;
2774 ecmd
->duplex
= sky2
->duplex
;
2778 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2780 struct sky2_port
*sky2
= netdev_priv(dev
);
2781 const struct sky2_hw
*hw
= sky2
->hw
;
2782 u32 supported
= sky2_supported_modes(hw
);
2784 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2785 ecmd
->advertising
= supported
;
2791 switch (ecmd
->speed
) {
2793 if (ecmd
->duplex
== DUPLEX_FULL
)
2794 setting
= SUPPORTED_1000baseT_Full
;
2795 else if (ecmd
->duplex
== DUPLEX_HALF
)
2796 setting
= SUPPORTED_1000baseT_Half
;
2801 if (ecmd
->duplex
== DUPLEX_FULL
)
2802 setting
= SUPPORTED_100baseT_Full
;
2803 else if (ecmd
->duplex
== DUPLEX_HALF
)
2804 setting
= SUPPORTED_100baseT_Half
;
2810 if (ecmd
->duplex
== DUPLEX_FULL
)
2811 setting
= SUPPORTED_10baseT_Full
;
2812 else if (ecmd
->duplex
== DUPLEX_HALF
)
2813 setting
= SUPPORTED_10baseT_Half
;
2821 if ((setting
& supported
) == 0)
2824 sky2
->speed
= ecmd
->speed
;
2825 sky2
->duplex
= ecmd
->duplex
;
2828 sky2
->autoneg
= ecmd
->autoneg
;
2829 sky2
->advertising
= ecmd
->advertising
;
2831 if (netif_running(dev
))
2832 sky2_phy_reinit(sky2
);
2837 static void sky2_get_drvinfo(struct net_device
*dev
,
2838 struct ethtool_drvinfo
*info
)
2840 struct sky2_port
*sky2
= netdev_priv(dev
);
2842 strcpy(info
->driver
, DRV_NAME
);
2843 strcpy(info
->version
, DRV_VERSION
);
2844 strcpy(info
->fw_version
, "N/A");
2845 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2848 static const struct sky2_stat
{
2849 char name
[ETH_GSTRING_LEN
];
2852 { "tx_bytes", GM_TXO_OK_HI
},
2853 { "rx_bytes", GM_RXO_OK_HI
},
2854 { "tx_broadcast", GM_TXF_BC_OK
},
2855 { "rx_broadcast", GM_RXF_BC_OK
},
2856 { "tx_multicast", GM_TXF_MC_OK
},
2857 { "rx_multicast", GM_RXF_MC_OK
},
2858 { "tx_unicast", GM_TXF_UC_OK
},
2859 { "rx_unicast", GM_RXF_UC_OK
},
2860 { "tx_mac_pause", GM_TXF_MPAUSE
},
2861 { "rx_mac_pause", GM_RXF_MPAUSE
},
2862 { "collisions", GM_TXF_COL
},
2863 { "late_collision",GM_TXF_LAT_COL
},
2864 { "aborted", GM_TXF_ABO_COL
},
2865 { "single_collisions", GM_TXF_SNG_COL
},
2866 { "multi_collisions", GM_TXF_MUL_COL
},
2868 { "rx_short", GM_RXF_SHT
},
2869 { "rx_runt", GM_RXE_FRAG
},
2870 { "rx_64_byte_packets", GM_RXF_64B
},
2871 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2872 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2873 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2874 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2875 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2876 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2877 { "rx_too_long", GM_RXF_LNG_ERR
},
2878 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2879 { "rx_jabber", GM_RXF_JAB_PKT
},
2880 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2882 { "tx_64_byte_packets", GM_TXF_64B
},
2883 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2884 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2885 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2886 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2887 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2888 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2889 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2892 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2894 struct sky2_port
*sky2
= netdev_priv(dev
);
2896 return sky2
->rx_csum
;
2899 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2901 struct sky2_port
*sky2
= netdev_priv(dev
);
2903 sky2
->rx_csum
= data
;
2905 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2906 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2911 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2913 struct sky2_port
*sky2
= netdev_priv(netdev
);
2914 return sky2
->msg_enable
;
2917 static int sky2_nway_reset(struct net_device
*dev
)
2919 struct sky2_port
*sky2
= netdev_priv(dev
);
2921 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
2924 sky2_phy_reinit(sky2
);
2929 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2931 struct sky2_hw
*hw
= sky2
->hw
;
2932 unsigned port
= sky2
->port
;
2935 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2936 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2937 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2938 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2940 for (i
= 2; i
< count
; i
++)
2941 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2944 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2946 struct sky2_port
*sky2
= netdev_priv(netdev
);
2947 sky2
->msg_enable
= value
;
2950 static int sky2_get_stats_count(struct net_device
*dev
)
2952 return ARRAY_SIZE(sky2_stats
);
2955 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2956 struct ethtool_stats
*stats
, u64
* data
)
2958 struct sky2_port
*sky2
= netdev_priv(dev
);
2960 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2963 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2967 switch (stringset
) {
2969 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2970 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2971 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2976 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2978 struct sky2_port
*sky2
= netdev_priv(dev
);
2979 return &sky2
->net_stats
;
2982 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2984 struct sky2_port
*sky2
= netdev_priv(dev
);
2985 struct sky2_hw
*hw
= sky2
->hw
;
2986 unsigned port
= sky2
->port
;
2987 const struct sockaddr
*addr
= p
;
2989 if (!is_valid_ether_addr(addr
->sa_data
))
2990 return -EADDRNOTAVAIL
;
2992 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2993 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2994 dev
->dev_addr
, ETH_ALEN
);
2995 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2996 dev
->dev_addr
, ETH_ALEN
);
2998 /* virtual address for data */
2999 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3001 /* physical address: used for pause frames */
3002 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3007 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3011 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3012 filter
[bit
>> 3] |= 1 << (bit
& 7);
3015 static void sky2_set_multicast(struct net_device
*dev
)
3017 struct sky2_port
*sky2
= netdev_priv(dev
);
3018 struct sky2_hw
*hw
= sky2
->hw
;
3019 unsigned port
= sky2
->port
;
3020 struct dev_mc_list
*list
= dev
->mc_list
;
3024 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3026 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3027 memset(filter
, 0, sizeof(filter
));
3029 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3030 reg
|= GM_RXCR_UCF_ENA
;
3032 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3033 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3034 else if (dev
->flags
& IFF_ALLMULTI
)
3035 memset(filter
, 0xff, sizeof(filter
));
3036 else if (dev
->mc_count
== 0 && !rx_pause
)
3037 reg
&= ~GM_RXCR_MCF_ENA
;
3040 reg
|= GM_RXCR_MCF_ENA
;
3043 sky2_add_filter(filter
, pause_mc_addr
);
3045 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3046 sky2_add_filter(filter
, list
->dmi_addr
);
3049 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3050 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3051 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3052 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3053 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3054 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3055 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3056 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3058 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3061 /* Can have one global because blinking is controlled by
3062 * ethtool and that is always under RTNL mutex
3064 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3068 switch (hw
->chip_id
) {
3069 case CHIP_ID_YUKON_XL
:
3070 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3071 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3072 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3073 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3074 PHY_M_LEDC_INIT_CTRL(7) |
3075 PHY_M_LEDC_STA1_CTRL(7) |
3076 PHY_M_LEDC_STA0_CTRL(7))
3079 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3083 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3084 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3085 on
? PHY_M_LED_ALL
: 0);
3089 /* blink LED's for finding board */
3090 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3092 struct sky2_port
*sky2
= netdev_priv(dev
);
3093 struct sky2_hw
*hw
= sky2
->hw
;
3094 unsigned port
= sky2
->port
;
3095 u16 ledctrl
, ledover
= 0;
3100 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3101 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3105 /* save initial values */
3106 spin_lock_bh(&sky2
->phy_lock
);
3107 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3108 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3109 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3110 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3111 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3113 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3114 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3118 while (!interrupted
&& ms
> 0) {
3119 sky2_led(hw
, port
, onoff
);
3122 spin_unlock_bh(&sky2
->phy_lock
);
3123 interrupted
= msleep_interruptible(250);
3124 spin_lock_bh(&sky2
->phy_lock
);
3129 /* resume regularly scheduled programming */
3130 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3131 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3132 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3133 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3134 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3136 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3137 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3139 spin_unlock_bh(&sky2
->phy_lock
);
3144 static void sky2_get_pauseparam(struct net_device
*dev
,
3145 struct ethtool_pauseparam
*ecmd
)
3147 struct sky2_port
*sky2
= netdev_priv(dev
);
3149 switch (sky2
->flow_mode
) {
3151 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3154 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3157 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3160 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3163 ecmd
->autoneg
= sky2
->autoneg
;
3166 static int sky2_set_pauseparam(struct net_device
*dev
,
3167 struct ethtool_pauseparam
*ecmd
)
3169 struct sky2_port
*sky2
= netdev_priv(dev
);
3171 sky2
->autoneg
= ecmd
->autoneg
;
3172 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3174 if (netif_running(dev
))
3175 sky2_phy_reinit(sky2
);
3180 static int sky2_get_coalesce(struct net_device
*dev
,
3181 struct ethtool_coalesce
*ecmd
)
3183 struct sky2_port
*sky2
= netdev_priv(dev
);
3184 struct sky2_hw
*hw
= sky2
->hw
;
3186 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3187 ecmd
->tx_coalesce_usecs
= 0;
3189 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3190 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3192 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3194 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3195 ecmd
->rx_coalesce_usecs
= 0;
3197 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3198 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3200 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3202 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3203 ecmd
->rx_coalesce_usecs_irq
= 0;
3205 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3206 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3209 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3214 /* Note: this affect both ports */
3215 static int sky2_set_coalesce(struct net_device
*dev
,
3216 struct ethtool_coalesce
*ecmd
)
3218 struct sky2_port
*sky2
= netdev_priv(dev
);
3219 struct sky2_hw
*hw
= sky2
->hw
;
3220 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3222 if (ecmd
->tx_coalesce_usecs
> tmax
||
3223 ecmd
->rx_coalesce_usecs
> tmax
||
3224 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3227 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3229 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3231 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3234 if (ecmd
->tx_coalesce_usecs
== 0)
3235 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3237 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3238 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3239 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3241 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3243 if (ecmd
->rx_coalesce_usecs
== 0)
3244 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3246 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3247 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3248 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3250 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3252 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3253 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3255 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3256 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3257 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3259 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3263 static void sky2_get_ringparam(struct net_device
*dev
,
3264 struct ethtool_ringparam
*ering
)
3266 struct sky2_port
*sky2
= netdev_priv(dev
);
3268 ering
->rx_max_pending
= RX_MAX_PENDING
;
3269 ering
->rx_mini_max_pending
= 0;
3270 ering
->rx_jumbo_max_pending
= 0;
3271 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3273 ering
->rx_pending
= sky2
->rx_pending
;
3274 ering
->rx_mini_pending
= 0;
3275 ering
->rx_jumbo_pending
= 0;
3276 ering
->tx_pending
= sky2
->tx_pending
;
3279 static int sky2_set_ringparam(struct net_device
*dev
,
3280 struct ethtool_ringparam
*ering
)
3282 struct sky2_port
*sky2
= netdev_priv(dev
);
3285 if (ering
->rx_pending
> RX_MAX_PENDING
||
3286 ering
->rx_pending
< 8 ||
3287 ering
->tx_pending
< MAX_SKB_TX_LE
||
3288 ering
->tx_pending
> TX_RING_SIZE
- 1)
3291 if (netif_running(dev
))
3294 sky2
->rx_pending
= ering
->rx_pending
;
3295 sky2
->tx_pending
= ering
->tx_pending
;
3297 if (netif_running(dev
)) {
3302 sky2_set_multicast(dev
);
3308 static int sky2_get_regs_len(struct net_device
*dev
)
3314 * Returns copy of control register region
3315 * Note: access to the RAM address register set will cause timeouts.
3317 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3320 const struct sky2_port
*sky2
= netdev_priv(dev
);
3321 const void __iomem
*io
= sky2
->hw
->regs
;
3323 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3325 memset(p
, 0, regs
->len
);
3327 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3329 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3331 regs
->len
- B3_RI_WTO_R1
);
3334 static const struct ethtool_ops sky2_ethtool_ops
= {
3335 .get_settings
= sky2_get_settings
,
3336 .set_settings
= sky2_set_settings
,
3337 .get_drvinfo
= sky2_get_drvinfo
,
3338 .get_wol
= sky2_get_wol
,
3339 .set_wol
= sky2_set_wol
,
3340 .get_msglevel
= sky2_get_msglevel
,
3341 .set_msglevel
= sky2_set_msglevel
,
3342 .nway_reset
= sky2_nway_reset
,
3343 .get_regs_len
= sky2_get_regs_len
,
3344 .get_regs
= sky2_get_regs
,
3345 .get_link
= ethtool_op_get_link
,
3346 .get_sg
= ethtool_op_get_sg
,
3347 .set_sg
= ethtool_op_set_sg
,
3348 .get_tx_csum
= ethtool_op_get_tx_csum
,
3349 .set_tx_csum
= ethtool_op_set_tx_csum
,
3350 .get_tso
= ethtool_op_get_tso
,
3351 .set_tso
= ethtool_op_set_tso
,
3352 .get_rx_csum
= sky2_get_rx_csum
,
3353 .set_rx_csum
= sky2_set_rx_csum
,
3354 .get_strings
= sky2_get_strings
,
3355 .get_coalesce
= sky2_get_coalesce
,
3356 .set_coalesce
= sky2_set_coalesce
,
3357 .get_ringparam
= sky2_get_ringparam
,
3358 .set_ringparam
= sky2_set_ringparam
,
3359 .get_pauseparam
= sky2_get_pauseparam
,
3360 .set_pauseparam
= sky2_set_pauseparam
,
3361 .phys_id
= sky2_phys_id
,
3362 .get_stats_count
= sky2_get_stats_count
,
3363 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3364 .get_perm_addr
= ethtool_op_get_perm_addr
,
3367 /* Initialize network device */
3368 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3370 int highmem
, int wol
)
3372 struct sky2_port
*sky2
;
3373 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3376 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed");
3380 SET_MODULE_OWNER(dev
);
3381 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3382 dev
->irq
= hw
->pdev
->irq
;
3383 dev
->open
= sky2_up
;
3384 dev
->stop
= sky2_down
;
3385 dev
->do_ioctl
= sky2_ioctl
;
3386 dev
->hard_start_xmit
= sky2_xmit_frame
;
3387 dev
->get_stats
= sky2_get_stats
;
3388 dev
->set_multicast_list
= sky2_set_multicast
;
3389 dev
->set_mac_address
= sky2_set_mac_address
;
3390 dev
->change_mtu
= sky2_change_mtu
;
3391 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3392 dev
->tx_timeout
= sky2_tx_timeout
;
3393 dev
->watchdog_timeo
= TX_WATCHDOG
;
3395 dev
->poll
= sky2_poll
;
3396 dev
->weight
= NAPI_WEIGHT
;
3397 #ifdef CONFIG_NET_POLL_CONTROLLER
3398 /* Network console (only works on port 0)
3399 * because netpoll makes assumptions about NAPI
3402 dev
->poll_controller
= sky2_netpoll
;
3405 sky2
= netdev_priv(dev
);
3408 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3410 /* Auto speed and flow control */
3411 sky2
->autoneg
= AUTONEG_ENABLE
;
3412 sky2
->flow_mode
= FC_BOTH
;
3416 sky2
->advertising
= sky2_supported_modes(hw
);
3420 spin_lock_init(&sky2
->phy_lock
);
3421 sky2
->tx_pending
= TX_DEF_PENDING
;
3422 sky2
->rx_pending
= RX_DEF_PENDING
;
3424 hw
->dev
[port
] = dev
;
3428 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
3430 dev
->features
|= NETIF_F_HIGHDMA
;
3432 #ifdef SKY2_VLAN_TAG_USED
3433 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3434 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3435 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3438 /* read the mac address */
3439 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3440 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3442 /* device is off until link detection */
3443 netif_carrier_off(dev
);
3444 netif_stop_queue(dev
);
3449 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3451 const struct sky2_port
*sky2
= netdev_priv(dev
);
3453 if (netif_msg_probe(sky2
))
3454 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3456 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3457 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3460 /* Handle software interrupt used during MSI test */
3461 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3463 struct sky2_hw
*hw
= dev_id
;
3464 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3469 if (status
& Y2_IS_IRQ_SW
) {
3471 wake_up(&hw
->msi_wait
);
3472 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3474 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3479 /* Test interrupt path by forcing a a software IRQ */
3480 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3482 struct pci_dev
*pdev
= hw
->pdev
;
3485 init_waitqueue_head (&hw
->msi_wait
);
3487 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3489 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3491 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3495 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3496 sky2_read8(hw
, B0_CTST
);
3498 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3501 /* MSI test failed, go back to INTx mode */
3502 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
3503 "switching to INTx mode.\n");
3506 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3509 sky2_write32(hw
, B0_IMSK
, 0);
3510 sky2_read32(hw
, B0_IMSK
);
3512 free_irq(pdev
->irq
, hw
);
3517 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
3519 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3524 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
3526 return value
& PCI_PM_CTRL_PME_ENABLE
;
3529 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3530 const struct pci_device_id
*ent
)
3532 struct net_device
*dev
;
3534 int err
, using_dac
= 0, wol_default
;
3536 err
= pci_enable_device(pdev
);
3538 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3542 err
= pci_request_regions(pdev
, DRV_NAME
);
3544 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3548 pci_set_master(pdev
);
3550 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3551 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3553 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3555 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
3556 "for consistent allocations\n");
3557 goto err_out_free_regions
;
3560 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3562 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3563 goto err_out_free_regions
;
3567 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
3570 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3572 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3573 goto err_out_free_regions
;
3578 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3580 dev_err(&pdev
->dev
, "cannot map device registers\n");
3581 goto err_out_free_hw
;
3585 /* The sk98lin vendor driver uses hardware byte swapping but
3586 * this driver uses software swapping.
3590 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3591 reg
&= ~PCI_REV_DESC
;
3592 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3596 /* ring for status responses */
3597 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3600 goto err_out_iounmap
;
3602 err
= sky2_init(hw
);
3604 goto err_out_iounmap
;
3606 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3607 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3608 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3609 hw
->chip_id
, hw
->chip_rev
);
3613 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
3616 goto err_out_free_pci
;
3619 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3620 err
= sky2_test_msi(hw
);
3621 if (err
== -EOPNOTSUPP
)
3622 pci_disable_msi(pdev
);
3624 goto err_out_free_netdev
;
3627 err
= register_netdev(dev
);
3629 dev_err(&pdev
->dev
, "cannot register net device\n");
3630 goto err_out_free_netdev
;
3633 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
3636 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3637 goto err_out_unregister
;
3639 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3641 sky2_show_addr(dev
);
3643 if (hw
->ports
> 1) {
3644 struct net_device
*dev1
;
3646 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
3648 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
3649 else if ((err
= register_netdev(dev1
))) {
3650 dev_warn(&pdev
->dev
,
3651 "register of second port failed (%d)\n", err
);
3655 sky2_show_addr(dev1
);
3658 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3659 INIT_WORK(&hw
->restart_work
, sky2_restart
);
3661 sky2_idle_start(hw
);
3663 pci_set_drvdata(pdev
, hw
);
3669 pci_disable_msi(pdev
);
3670 unregister_netdev(dev
);
3671 err_out_free_netdev
:
3674 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3675 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3680 err_out_free_regions
:
3681 pci_release_regions(pdev
);
3682 pci_disable_device(pdev
);
3687 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3689 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3690 struct net_device
*dev0
, *dev1
;
3695 del_timer_sync(&hw
->idle_timer
);
3697 flush_scheduled_work();
3699 sky2_write32(hw
, B0_IMSK
, 0);
3700 synchronize_irq(hw
->pdev
->irq
);
3705 unregister_netdev(dev1
);
3706 unregister_netdev(dev0
);
3710 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3711 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3712 sky2_read8(hw
, B0_CTST
);
3714 free_irq(pdev
->irq
, hw
);
3716 pci_disable_msi(pdev
);
3717 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3718 pci_release_regions(pdev
);
3719 pci_disable_device(pdev
);
3727 pci_set_drvdata(pdev
, NULL
);
3731 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3733 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3736 del_timer_sync(&hw
->idle_timer
);
3737 netif_poll_disable(hw
->dev
[0]);
3739 for (i
= 0; i
< hw
->ports
; i
++) {
3740 struct net_device
*dev
= hw
->dev
[i
];
3741 struct sky2_port
*sky2
= netdev_priv(dev
);
3743 if (netif_running(dev
))
3747 sky2_wol_init(sky2
);
3752 sky2_write32(hw
, B0_IMSK
, 0);
3755 pci_save_state(pdev
);
3756 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3757 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3762 static int sky2_resume(struct pci_dev
*pdev
)
3764 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3767 err
= pci_set_power_state(pdev
, PCI_D0
);
3771 err
= pci_restore_state(pdev
);
3775 pci_enable_wake(pdev
, PCI_D0
, 0);
3777 /* Re-enable all clocks */
3778 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
3779 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
3783 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3785 for (i
= 0; i
< hw
->ports
; i
++) {
3786 struct net_device
*dev
= hw
->dev
[i
];
3787 if (netif_running(dev
)) {
3790 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3798 netif_poll_enable(hw
->dev
[0]);
3799 sky2_idle_start(hw
);
3802 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
3803 pci_disable_device(pdev
);
3808 static void sky2_shutdown(struct pci_dev
*pdev
)
3810 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3813 del_timer_sync(&hw
->idle_timer
);
3814 netif_poll_disable(hw
->dev
[0]);
3816 for (i
= 0; i
< hw
->ports
; i
++) {
3817 struct net_device
*dev
= hw
->dev
[i
];
3818 struct sky2_port
*sky2
= netdev_priv(dev
);
3822 sky2_wol_init(sky2
);
3829 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
3830 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
3832 pci_disable_device(pdev
);
3833 pci_set_power_state(pdev
, PCI_D3hot
);
3837 static struct pci_driver sky2_driver
= {
3839 .id_table
= sky2_id_table
,
3840 .probe
= sky2_probe
,
3841 .remove
= __devexit_p(sky2_remove
),
3843 .suspend
= sky2_suspend
,
3844 .resume
= sky2_resume
,
3846 .shutdown
= sky2_shutdown
,
3849 static int __init
sky2_init_module(void)
3851 return pci_register_driver(&sky2_driver
);
3854 static void __exit
sky2_cleanup_module(void)
3856 pci_unregister_driver(&sky2_driver
);
3859 module_init(sky2_init_module
);
3860 module_exit(sky2_cleanup_module
);
3862 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3863 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3864 MODULE_LICENSE("GPL");
3865 MODULE_VERSION(DRV_VERSION
);