2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define is_ec_a1(hw) \
65 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
66 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
68 #define RX_LE_SIZE 512
69 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
70 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
71 #define RX_DEF_PENDING RX_MAX_PENDING
72 #define RX_SKB_ALIGN 8
74 #define TX_RING_SIZE 512
75 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
76 #define TX_MIN_PENDING 64
77 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
79 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
80 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
81 #define ETH_JUMBO_MTU 9000
82 #define TX_WATCHDOG (5 * HZ)
83 #define NAPI_WEIGHT 64
84 #define PHY_RETRIES 1000
86 static const u32 default_msg
=
87 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
88 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
91 static int debug
= -1; /* defaults above */
92 module_param(debug
, int, 0);
93 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
95 static int copybreak __read_mostly
= 256;
96 module_param(copybreak
, int, 0);
97 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
99 static const struct pci_device_id sky2_id_table
[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) },
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
122 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
124 /* Avoid conditionals by using array */
125 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
126 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
128 /* This driver supports yukon2 chipset only */
129 static const char *yukon2_name
[] = {
131 "EC Ultra", /* 0xb4 */
132 "UNKNOWN", /* 0xb5 */
137 /* Access to external PHY */
138 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
142 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
143 gma_write16(hw
, port
, GM_SMI_CTRL
,
144 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
146 for (i
= 0; i
< PHY_RETRIES
; i
++) {
147 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
152 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
156 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
160 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
161 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
163 for (i
= 0; i
< PHY_RETRIES
; i
++) {
164 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
165 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
175 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
179 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
180 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
184 static int sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
191 pr_debug("sky2_set_power_state %d\n", state
);
192 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
194 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
195 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
196 (power_control
& PCI_PM_CAP_PME_D3cold
);
198 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
200 power_control
|= PCI_PM_CTRL_PME_STATUS
;
201 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw
, B0_POWER_CTRL
,
207 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
209 /* disable Core Clock Division, */
210 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
212 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
213 /* enable bits are inverted */
214 sky2_write8(hw
, B2_Y2_CLK_GATE
,
215 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
216 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
217 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
219 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
221 /* Turn off phy power saving */
222 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
223 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
225 /* looks like this XL is back asswards .. */
226 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
227 reg1
|= PCI_Y2_PHY1_COMA
;
229 reg1
|= PCI_Y2_PHY2_COMA
;
232 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
233 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
234 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
235 reg1
&= P_ASPM_CONTROL_MSK
;
236 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
237 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
240 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
246 /* Turn on phy power saving */
247 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
248 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
249 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
251 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
252 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
254 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
255 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
257 /* enable bits are inverted */
258 sky2_write8(hw
, B2_Y2_CLK_GATE
,
259 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
260 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
261 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
263 /* switch power to VAUX */
264 if (vaux
&& state
!= PCI_D3cold
)
265 sky2_write8(hw
, B0_POWER_CTRL
,
266 (PC_VAUX_ENA
| PC_VCC_ENA
|
267 PC_VAUX_ON
| PC_VCC_OFF
));
270 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
274 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
275 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
279 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
283 /* disable all GMAC IRQ's */
284 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
285 /* disable PHY IRQs */
286 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
288 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
289 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
290 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
291 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
293 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
294 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
295 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
298 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
300 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
301 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
303 if (sky2
->autoneg
== AUTONEG_ENABLE
&& hw
->chip_id
!= CHIP_ID_YUKON_XL
) {
304 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
306 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
308 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
310 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
311 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
313 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
315 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
318 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
320 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
321 /* enable automatic crossover */
322 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
324 /* disable energy detect */
325 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
327 /* enable automatic crossover */
328 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
330 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
331 hw
->chip_id
== CHIP_ID_YUKON_XL
) {
332 ctrl
&= ~PHY_M_PC_DSC_MSK
;
333 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
336 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
338 /* workaround for deviation #4.88 (CRC errors) */
339 /* disable Automatic Crossover */
341 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
342 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
344 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
345 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
346 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
347 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
348 ctrl
&= ~PHY_M_MAC_MD_MSK
;
349 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
350 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
352 /* select page 1 to access Fiber registers */
353 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
357 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
358 if (sky2
->autoneg
== AUTONEG_DISABLE
)
363 ctrl
|= PHY_CT_RESET
;
364 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
370 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
372 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
373 ct1000
|= PHY_M_1000C_AFD
;
374 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
375 ct1000
|= PHY_M_1000C_AHD
;
376 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
377 adv
|= PHY_M_AN_100_FD
;
378 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
379 adv
|= PHY_M_AN_100_HD
;
380 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
381 adv
|= PHY_M_AN_10_FD
;
382 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
383 adv
|= PHY_M_AN_10_HD
;
384 } else /* special defines for FIBER (88E1011S only) */
385 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
387 /* Set Flow-control capabilities */
388 if (sky2
->tx_pause
&& sky2
->rx_pause
)
389 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
390 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
391 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
392 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
393 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
395 /* Restart Auto-negotiation */
396 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
398 /* forced speed/duplex settings */
399 ct1000
= PHY_M_1000C_MSE
;
401 if (sky2
->duplex
== DUPLEX_FULL
)
402 ctrl
|= PHY_CT_DUP_MD
;
404 switch (sky2
->speed
) {
406 ctrl
|= PHY_CT_SP1000
;
409 ctrl
|= PHY_CT_SP100
;
413 ctrl
|= PHY_CT_RESET
;
416 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
417 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
419 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
420 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
422 /* Setup Phy LED's */
423 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
426 switch (hw
->chip_id
) {
427 case CHIP_ID_YUKON_FE
:
428 /* on 88E3082 these bits are at 11..9 (shifted left) */
429 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
431 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
433 /* delete ACT LED control bits */
434 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
435 /* change ACT LED control to blink mode */
436 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
437 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
440 case CHIP_ID_YUKON_XL
:
441 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
443 /* select page 3 to access LED control register */
444 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
446 /* set LED Function Control register */
447 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
448 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
449 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
450 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
452 /* set Polarity Control register */
453 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
454 (PHY_M_POLC_LS1_P_MIX(4) |
455 PHY_M_POLC_IS0_P_MIX(4) |
456 PHY_M_POLC_LOS_CTRL(2) |
457 PHY_M_POLC_INIT_CTRL(2) |
458 PHY_M_POLC_STA1_CTRL(2) |
459 PHY_M_POLC_STA0_CTRL(2)));
461 /* restore page register */
462 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
466 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
467 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
468 /* turn off the Rx LED (LED_RX) */
469 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
472 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
473 /* apply fixes in PHY AFE */
474 gm_phy_write(hw
, port
, 22, 255);
475 /* increase differential signal amplitude in 10BASE-T */
476 gm_phy_write(hw
, port
, 24, 0xaa99);
477 gm_phy_write(hw
, port
, 23, 0x2011);
479 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
480 gm_phy_write(hw
, port
, 24, 0xa204);
481 gm_phy_write(hw
, port
, 23, 0x2002);
483 /* set page register to 0 */
484 gm_phy_write(hw
, port
, 22, 0);
486 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
488 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
489 /* turn on 100 Mbps LED (LED_LINK100) */
490 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
494 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
497 /* Enable phy interrupt on auto-negotiation complete (or link up) */
498 if (sky2
->autoneg
== AUTONEG_ENABLE
)
499 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
501 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
504 /* Force a renegotiation */
505 static void sky2_phy_reinit(struct sky2_port
*sky2
)
507 down(&sky2
->phy_sema
);
508 sky2_phy_init(sky2
->hw
, sky2
->port
);
512 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
514 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
517 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
519 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
520 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
522 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
524 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
525 /* WA DEV_472 -- looks like crossed wires on port 2 */
526 /* clear GMAC 1 Control reset */
527 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
529 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
530 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
531 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
532 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
533 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
536 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
537 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
538 reg
|= GM_GPCR_AU_ALL_DIS
;
539 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
540 gma_read16(hw
, port
, GM_GP_CTRL
);
542 switch (sky2
->speed
) {
544 reg
&= ~GM_GPCR_SPEED_100
;
545 reg
|= GM_GPCR_SPEED_1000
;
548 reg
&= ~GM_GPCR_SPEED_1000
;
549 reg
|= GM_GPCR_SPEED_100
;
552 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
556 if (sky2
->duplex
== DUPLEX_FULL
)
557 reg
|= GM_GPCR_DUP_FULL
;
559 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
561 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
562 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
564 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
565 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
566 /* disable Rx flow-control */
567 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
570 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
572 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
574 down(&sky2
->phy_sema
);
575 sky2_phy_init(hw
, port
);
579 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
580 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
582 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
583 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8 * i
);
584 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
586 /* transmit control */
587 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
589 /* receive control reg: unicast + multicast + no FCS */
590 gma_write16(hw
, port
, GM_RX_CTRL
,
591 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
593 /* transmit flow control */
594 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
596 /* transmit parameter */
597 gma_write16(hw
, port
, GM_TX_PARAM
,
598 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
599 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
600 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
601 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
603 /* serial mode register */
604 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
605 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
607 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
608 reg
|= GM_SMOD_JUMBO_ENA
;
610 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
612 /* virtual address for data */
613 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
615 /* physical address: used for pause frames */
616 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
618 /* ignore counter overflows */
619 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
620 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
621 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
623 /* Configure Rx MAC FIFO */
624 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
625 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
626 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
628 /* Flush Rx MAC FIFO on any flow control or error */
629 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
631 /* Set threshold to 0xa (64 bytes)
632 * ASF disabled so no need to do WA dev #4.30
634 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
636 /* Configure Tx MAC FIFO */
637 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
638 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
640 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
641 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
642 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
643 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
644 /* set Tx GMAC FIFO Almost Empty Threshold */
645 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
646 /* Disable Store & Forward mode for TX */
647 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
653 /* Assign Ram Buffer allocation.
654 * start and end are in units of 4k bytes
655 * ram registers are in units of 64bit words
657 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
661 start
= startk
* 4096/8;
662 end
= (endk
* 4096/8) - 1;
664 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
665 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
666 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
667 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
668 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
670 if (q
== Q_R1
|| q
== Q_R2
) {
671 u32 space
= (endk
- startk
) * 4096/8;
672 u32 tp
= space
- space
/4;
674 /* On receive queue's set the thresholds
675 * give receiver priority when > 3/4 full
676 * send pause when down to 2K
678 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
679 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
682 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
683 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
685 /* Enable store & forward on Tx queue's because
686 * Tx FIFO is only 1K on Yukon
688 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
691 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
692 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
695 /* Setup Bus Memory Interface */
696 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
698 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
699 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
700 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
701 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
704 /* Setup prefetch unit registers. This is the interface between
705 * hardware and driver list elements
707 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
710 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
711 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
712 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
713 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
714 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
715 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
717 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
720 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
722 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
724 sky2
->tx_prod
= (sky2
->tx_prod
+ 1) % TX_RING_SIZE
;
729 * This is a workaround code taken from SysKonnect sk98lin driver
730 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
732 static void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
,
733 u16 idx
, u16
*last
, u16 size
)
736 if (is_ec_a1(hw
) && idx
< *last
) {
737 u16 hwget
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
740 /* Start prefetching again */
741 sky2_write8(hw
, Y2_QADDR(q
, PREF_UNIT_FIFO_WM
), 0xe0);
745 if (hwget
== size
- 1) {
746 /* set watermark to one list element */
747 sky2_write8(hw
, Y2_QADDR(q
, PREF_UNIT_FIFO_WM
), 8);
749 /* set put index to first list element */
750 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), 0);
751 } else /* have hardware go to end of list */
752 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
),
756 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
763 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
765 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
766 sky2
->rx_put
= (sky2
->rx_put
+ 1) % RX_LE_SIZE
;
770 /* Return high part of DMA address (could be 32 or 64 bit) */
771 static inline u32
high32(dma_addr_t a
)
773 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
776 /* Build description to hardware about buffer */
777 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
779 struct sky2_rx_le
*le
;
780 u32 hi
= high32(map
);
781 u16 len
= sky2
->rx_bufsize
;
783 if (sky2
->rx_addr64
!= hi
) {
784 le
= sky2_next_rx(sky2
);
785 le
->addr
= cpu_to_le32(hi
);
787 le
->opcode
= OP_ADDR64
| HW_OWNER
;
788 sky2
->rx_addr64
= high32(map
+ len
);
791 le
= sky2_next_rx(sky2
);
792 le
->addr
= cpu_to_le32((u32
) map
);
793 le
->length
= cpu_to_le16(len
);
795 le
->opcode
= OP_PACKET
| HW_OWNER
;
799 /* Tell chip where to start receive checksum.
800 * Actually has two checksums, but set both same to avoid possible byte
803 static void rx_set_checksum(struct sky2_port
*sky2
)
805 struct sky2_rx_le
*le
;
807 le
= sky2_next_rx(sky2
);
808 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
810 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
812 sky2_write32(sky2
->hw
,
813 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
814 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
819 * The RX Stop command will not work for Yukon-2 if the BMU does not
820 * reach the end of packet and since we can't make sure that we have
821 * incoming data, we must reset the BMU while it is not doing a DMA
822 * transfer. Since it is possible that the RX path is still active,
823 * the RX RAM buffer will be stopped first, so any possible incoming
824 * data will not trigger a DMA. After the RAM buffer is stopped, the
825 * BMU is polled until any DMA in progress is ended and only then it
828 static void sky2_rx_stop(struct sky2_port
*sky2
)
830 struct sky2_hw
*hw
= sky2
->hw
;
831 unsigned rxq
= rxqaddr
[sky2
->port
];
834 /* disable the RAM Buffer receive queue */
835 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
837 for (i
= 0; i
< 0xffff; i
++)
838 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
839 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
842 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
845 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
847 /* reset the Rx prefetch unit */
848 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
851 /* Clean out receive buffer area, assumes receiver hardware stopped */
852 static void sky2_rx_clean(struct sky2_port
*sky2
)
856 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
857 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
858 struct ring_info
*re
= sky2
->rx_ring
+ i
;
861 pci_unmap_single(sky2
->hw
->pdev
,
862 re
->mapaddr
, sky2
->rx_bufsize
,
870 /* Basic MII support */
871 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
873 struct mii_ioctl_data
*data
= if_mii(ifr
);
874 struct sky2_port
*sky2
= netdev_priv(dev
);
875 struct sky2_hw
*hw
= sky2
->hw
;
876 int err
= -EOPNOTSUPP
;
878 if (!netif_running(dev
))
879 return -ENODEV
; /* Phy still in reset */
883 data
->phy_id
= PHY_ADDR_MARV
;
889 down(&sky2
->phy_sema
);
890 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
898 if (!capable(CAP_NET_ADMIN
))
901 down(&sky2
->phy_sema
);
902 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
910 #ifdef SKY2_VLAN_TAG_USED
911 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
913 struct sky2_port
*sky2
= netdev_priv(dev
);
914 struct sky2_hw
*hw
= sky2
->hw
;
915 u16 port
= sky2
->port
;
917 spin_lock_bh(&sky2
->tx_lock
);
919 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
920 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
923 spin_unlock_bh(&sky2
->tx_lock
);
926 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
928 struct sky2_port
*sky2
= netdev_priv(dev
);
929 struct sky2_hw
*hw
= sky2
->hw
;
930 u16 port
= sky2
->port
;
932 spin_lock_bh(&sky2
->tx_lock
);
934 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
935 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
937 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
939 spin_unlock_bh(&sky2
->tx_lock
);
944 * It appears the hardware has a bug in the FIFO logic that
945 * cause it to hang if the FIFO gets overrun and the receive buffer
946 * is not aligned. ALso alloc_skb() won't align properly if slab
947 * debugging is enabled.
949 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
953 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
955 unsigned long p
= (unsigned long) skb
->data
;
957 ((p
+ RX_SKB_ALIGN
- 1) & ~(RX_SKB_ALIGN
- 1)) - p
);
964 * Allocate and setup receiver buffer pool.
965 * In case of 64 bit dma, there are 2X as many list elements
966 * available as ring entries
967 * and need to reserve one list element so we don't wrap around.
969 static int sky2_rx_start(struct sky2_port
*sky2
)
971 struct sky2_hw
*hw
= sky2
->hw
;
972 unsigned rxq
= rxqaddr
[sky2
->port
];
975 sky2
->rx_put
= sky2
->rx_next
= 0;
978 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
979 /* MAC Rx RAM Read is controlled by hardware */
980 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
983 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
985 rx_set_checksum(sky2
);
986 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
987 struct ring_info
*re
= sky2
->rx_ring
+ i
;
989 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
993 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
994 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
995 sky2_rx_add(sky2
, re
->mapaddr
);
998 /* Truncate oversize frames */
999 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), sky2
->rx_bufsize
- 8);
1000 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1002 /* Tell chip about available buffers */
1003 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1004 sky2
->rx_last_put
= sky2_read16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
));
1007 sky2_rx_clean(sky2
);
1011 /* Bring up network interface. */
1012 static int sky2_up(struct net_device
*dev
)
1014 struct sky2_port
*sky2
= netdev_priv(dev
);
1015 struct sky2_hw
*hw
= sky2
->hw
;
1016 unsigned port
= sky2
->port
;
1017 u32 ramsize
, rxspace
;
1020 if (netif_msg_ifup(sky2
))
1021 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1023 /* must be power of 2 */
1024 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1026 sizeof(struct sky2_tx_le
),
1031 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1035 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1037 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1041 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1043 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1048 sky2_mac_init(hw
, port
);
1050 /* Determine available ram buffer space (in 4K blocks).
1051 * Note: not sure about the FE setting below yet
1053 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1056 ramsize
= sky2_read8(hw
, B2_E_0
);
1058 /* Give transmitter one third (rounded up) */
1059 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1061 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1062 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1064 /* Make sure SyncQ is disabled */
1065 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1068 sky2_qset(hw
, txqaddr
[port
]);
1070 /* Set almost empty threshold */
1071 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1072 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1074 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1077 err
= sky2_rx_start(sky2
);
1081 /* Enable interrupts from phy/mac for port */
1082 spin_lock_irq(&hw
->hw_lock
);
1083 hw
->intr_mask
|= (port
== 0) ? Y2_IS_PORT_1
: Y2_IS_PORT_2
;
1084 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1085 spin_unlock_irq(&hw
->hw_lock
);
1090 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1091 sky2
->rx_le
, sky2
->rx_le_map
);
1095 pci_free_consistent(hw
->pdev
,
1096 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1097 sky2
->tx_le
, sky2
->tx_le_map
);
1100 kfree(sky2
->tx_ring
);
1101 kfree(sky2
->rx_ring
);
1103 sky2
->tx_ring
= NULL
;
1104 sky2
->rx_ring
= NULL
;
1108 /* Modular subtraction in ring */
1109 static inline int tx_dist(unsigned tail
, unsigned head
)
1111 return (head
- tail
) % TX_RING_SIZE
;
1114 /* Number of list elements available for next tx */
1115 static inline int tx_avail(const struct sky2_port
*sky2
)
1117 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1120 /* Estimate of number of transmit list elements required */
1121 static unsigned tx_le_req(const struct sk_buff
*skb
)
1125 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1126 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1128 if (skb_shinfo(skb
)->tso_size
)
1131 if (skb
->ip_summed
== CHECKSUM_HW
)
1138 * Put one packet in ring for transmit.
1139 * A single packet can generate multiple list elements, and
1140 * the number of ring elements will probably be less than the number
1141 * of list elements used.
1143 * No BH disabling for tx_lock here (like tg3)
1145 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1147 struct sky2_port
*sky2
= netdev_priv(dev
);
1148 struct sky2_hw
*hw
= sky2
->hw
;
1149 struct sky2_tx_le
*le
= NULL
;
1150 struct tx_ring_info
*re
;
1158 /* No BH disabling for tx_lock here. We are running in BH disabled
1159 * context and TX reclaim runs via poll inside of a software
1160 * interrupt, and no related locks in IRQ processing.
1162 if (!spin_trylock(&sky2
->tx_lock
))
1163 return NETDEV_TX_LOCKED
;
1165 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1166 /* There is a known but harmless race with lockless tx
1167 * and netif_stop_queue.
1169 if (!netif_queue_stopped(dev
)) {
1170 netif_stop_queue(dev
);
1171 if (net_ratelimit())
1172 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1175 spin_unlock(&sky2
->tx_lock
);
1177 return NETDEV_TX_BUSY
;
1180 if (unlikely(netif_msg_tx_queued(sky2
)))
1181 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1182 dev
->name
, sky2
->tx_prod
, skb
->len
);
1184 len
= skb_headlen(skb
);
1185 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1186 addr64
= high32(mapping
);
1188 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1190 /* Send high bits if changed or crosses boundary */
1191 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1192 le
= get_tx_le(sky2
);
1193 le
->tx
.addr
= cpu_to_le32(addr64
);
1195 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1196 sky2
->tx_addr64
= high32(mapping
+ len
);
1199 /* Check for TCP Segmentation Offload */
1200 mss
= skb_shinfo(skb
)->tso_size
;
1202 /* just drop the packet if non-linear expansion fails */
1203 if (skb_header_cloned(skb
) &&
1204 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1205 dev_kfree_skb_any(skb
);
1209 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1210 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1214 if (mss
!= sky2
->tx_last_mss
) {
1215 le
= get_tx_le(sky2
);
1216 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1217 le
->tx
.tso
.rsvd
= 0;
1218 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1220 sky2
->tx_last_mss
= mss
;
1224 #ifdef SKY2_VLAN_TAG_USED
1225 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1226 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1228 le
= get_tx_le(sky2
);
1230 le
->opcode
= OP_VLAN
|HW_OWNER
;
1233 le
->opcode
|= OP_VLAN
;
1234 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1239 /* Handle TCP checksum offload */
1240 if (skb
->ip_summed
== CHECKSUM_HW
) {
1241 u16 hdr
= skb
->h
.raw
- skb
->data
;
1242 u16 offset
= hdr
+ skb
->csum
;
1244 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1245 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1248 le
= get_tx_le(sky2
);
1249 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1250 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1251 le
->length
= 0; /* initial checksum value */
1252 le
->ctrl
= 1; /* one packet */
1253 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1256 le
= get_tx_le(sky2
);
1257 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1258 le
->length
= cpu_to_le16(len
);
1260 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1262 /* Record the transmit mapping info */
1264 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1266 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1267 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1268 struct tx_ring_info
*fre
;
1270 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1271 frag
->size
, PCI_DMA_TODEVICE
);
1272 addr64
= high32(mapping
);
1273 if (addr64
!= sky2
->tx_addr64
) {
1274 le
= get_tx_le(sky2
);
1275 le
->tx
.addr
= cpu_to_le32(addr64
);
1277 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1278 sky2
->tx_addr64
= addr64
;
1281 le
= get_tx_le(sky2
);
1282 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1283 le
->length
= cpu_to_le16(frag
->size
);
1285 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1288 + ((re
- sky2
->tx_ring
) + i
+ 1) % TX_RING_SIZE
;
1289 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1292 re
->idx
= sky2
->tx_prod
;
1295 avail
= tx_avail(sky2
);
1296 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1297 le
->ctrl
|= FRC_STAT
;
1298 if (avail
<= MAX_SKB_TX_LE
)
1299 netif_stop_queue(dev
);
1302 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
,
1303 &sky2
->tx_last_put
, TX_RING_SIZE
);
1306 spin_unlock(&sky2
->tx_lock
);
1308 dev
->trans_start
= jiffies
;
1309 return NETDEV_TX_OK
;
1313 * Free ring elements from starting at tx_cons until "done"
1315 * NB: the hardware will tell us about partial completion of multi-part
1316 * buffers; these are deferred until completion.
1318 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1320 struct net_device
*dev
= sky2
->netdev
;
1321 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1325 BUG_ON(done
>= TX_RING_SIZE
);
1327 if (unlikely(netif_msg_tx_done(sky2
)))
1328 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1331 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1332 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1333 struct sk_buff
*skb
= re
->skb
;
1336 BUG_ON(nxt
>= TX_RING_SIZE
);
1337 prefetch(sky2
->tx_ring
+ nxt
);
1339 /* Check for partial status */
1340 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1344 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1345 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1347 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1348 struct tx_ring_info
*fre
;
1349 fre
= sky2
->tx_ring
+ (put
+ i
+ 1) % TX_RING_SIZE
;
1350 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1351 skb_shinfo(skb
)->frags
[i
].size
,
1355 dev_kfree_skb_any(skb
);
1358 sky2
->tx_cons
= put
;
1359 if (netif_queue_stopped(dev
) && tx_avail(sky2
) > MAX_SKB_TX_LE
)
1360 netif_wake_queue(dev
);
1363 /* Cleanup all untransmitted buffers, assume transmitter not running */
1364 static void sky2_tx_clean(struct sky2_port
*sky2
)
1366 spin_lock_bh(&sky2
->tx_lock
);
1367 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1368 spin_unlock_bh(&sky2
->tx_lock
);
1371 /* Network shutdown */
1372 static int sky2_down(struct net_device
*dev
)
1374 struct sky2_port
*sky2
= netdev_priv(dev
);
1375 struct sky2_hw
*hw
= sky2
->hw
;
1376 unsigned port
= sky2
->port
;
1379 /* Never really got started! */
1383 if (netif_msg_ifdown(sky2
))
1384 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1386 /* Stop more packets from being queued */
1387 netif_stop_queue(dev
);
1389 /* Disable port IRQ */
1390 spin_lock_irq(&hw
->hw_lock
);
1391 hw
->intr_mask
&= ~((sky2
->port
== 0) ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
);
1392 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1393 spin_unlock_irq(&hw
->hw_lock
);
1395 flush_scheduled_work();
1397 sky2_phy_reset(hw
, port
);
1399 /* Stop transmitter */
1400 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1401 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1403 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1404 RB_RST_SET
| RB_DIS_OP_MD
);
1406 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1407 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1408 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1410 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1412 /* Workaround shared GMAC reset */
1413 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1414 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1415 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1417 /* Disable Force Sync bit and Enable Alloc bit */
1418 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1419 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1421 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1422 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1423 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1425 /* Reset the PCI FIFO of the async Tx queue */
1426 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1427 BMU_RST_SET
| BMU_FIFO_RST
);
1429 /* Reset the Tx prefetch units */
1430 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1433 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1437 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1438 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1440 /* turn off LED's */
1441 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1443 synchronize_irq(hw
->pdev
->irq
);
1445 sky2_tx_clean(sky2
);
1446 sky2_rx_clean(sky2
);
1448 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1449 sky2
->rx_le
, sky2
->rx_le_map
);
1450 kfree(sky2
->rx_ring
);
1452 pci_free_consistent(hw
->pdev
,
1453 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1454 sky2
->tx_le
, sky2
->tx_le_map
);
1455 kfree(sky2
->tx_ring
);
1460 sky2
->rx_ring
= NULL
;
1461 sky2
->tx_ring
= NULL
;
1466 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1471 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1472 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1474 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1475 case PHY_M_PS_SPEED_1000
:
1477 case PHY_M_PS_SPEED_100
:
1484 static void sky2_link_up(struct sky2_port
*sky2
)
1486 struct sky2_hw
*hw
= sky2
->hw
;
1487 unsigned port
= sky2
->port
;
1490 /* Enable Transmit FIFO Underrun */
1491 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1493 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1494 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1495 reg
|= GM_GPCR_AU_ALL_DIS
;
1497 /* Is write/read necessary? Copied from sky2_mac_init */
1498 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1499 gma_read16(hw
, port
, GM_GP_CTRL
);
1501 switch (sky2
->speed
) {
1503 reg
&= ~GM_GPCR_SPEED_100
;
1504 reg
|= GM_GPCR_SPEED_1000
;
1507 reg
&= ~GM_GPCR_SPEED_1000
;
1508 reg
|= GM_GPCR_SPEED_100
;
1511 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1515 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1517 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1518 reg
|= GM_GPCR_DUP_FULL
;
1521 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1522 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1523 gma_read16(hw
, port
, GM_GP_CTRL
);
1525 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1527 netif_carrier_on(sky2
->netdev
);
1528 netif_wake_queue(sky2
->netdev
);
1530 /* Turn on link LED */
1531 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1532 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1534 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
1535 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1537 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1538 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1539 PHY_M_LEDC_INIT_CTRL(sky2
->speed
==
1541 PHY_M_LEDC_STA1_CTRL(sky2
->speed
==
1542 SPEED_100
? 7 : 0) |
1543 PHY_M_LEDC_STA0_CTRL(sky2
->speed
==
1544 SPEED_1000
? 7 : 0));
1545 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1548 if (netif_msg_link(sky2
))
1549 printk(KERN_INFO PFX
1550 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1551 sky2
->netdev
->name
, sky2
->speed
,
1552 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1553 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1554 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1557 static void sky2_link_down(struct sky2_port
*sky2
)
1559 struct sky2_hw
*hw
= sky2
->hw
;
1560 unsigned port
= sky2
->port
;
1563 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1565 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1566 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1567 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1568 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1570 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1571 /* restore Asymmetric Pause bit */
1572 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1573 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1577 netif_carrier_off(sky2
->netdev
);
1578 netif_stop_queue(sky2
->netdev
);
1580 /* Turn on link LED */
1581 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1583 if (netif_msg_link(sky2
))
1584 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1585 sky2_phy_init(hw
, port
);
1588 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1590 struct sky2_hw
*hw
= sky2
->hw
;
1591 unsigned port
= sky2
->port
;
1594 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1596 if (lpa
& PHY_M_AN_RF
) {
1597 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1601 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1602 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1603 printk(KERN_ERR PFX
"%s: master/slave fault",
1604 sky2
->netdev
->name
);
1608 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1609 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1610 sky2
->netdev
->name
);
1614 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1616 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1618 /* Pause bits are offset (9..8) */
1619 if (hw
->chip_id
== CHIP_ID_YUKON_XL
)
1622 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1623 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1625 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1626 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1627 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1629 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1635 * Interrupt from PHY are handled outside of interrupt context
1636 * because accessing phy registers requires spin wait which might
1637 * cause excess interrupt latency.
1639 static void sky2_phy_task(void *arg
)
1641 struct sky2_port
*sky2
= arg
;
1642 struct sky2_hw
*hw
= sky2
->hw
;
1643 u16 istatus
, phystat
;
1645 down(&sky2
->phy_sema
);
1646 istatus
= gm_phy_read(hw
, sky2
->port
, PHY_MARV_INT_STAT
);
1647 phystat
= gm_phy_read(hw
, sky2
->port
, PHY_MARV_PHY_STAT
);
1649 if (netif_msg_intr(sky2
))
1650 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1651 sky2
->netdev
->name
, istatus
, phystat
);
1653 if (istatus
& PHY_M_IS_AN_COMPL
) {
1654 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1659 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1660 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1662 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1664 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1666 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1667 if (phystat
& PHY_M_PS_LINK_UP
)
1670 sky2_link_down(sky2
);
1673 up(&sky2
->phy_sema
);
1675 spin_lock_irq(&hw
->hw_lock
);
1676 hw
->intr_mask
|= (sky2
->port
== 0) ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
;
1677 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1678 spin_unlock_irq(&hw
->hw_lock
);
1682 /* Transmit timeout is only called if we are running, carries is up
1683 * and tx queue is full (stopped).
1685 static void sky2_tx_timeout(struct net_device
*dev
)
1687 struct sky2_port
*sky2
= netdev_priv(dev
);
1688 struct sky2_hw
*hw
= sky2
->hw
;
1689 unsigned txq
= txqaddr
[sky2
->port
];
1692 /* Maybe we just missed an status interrupt */
1693 spin_lock(&sky2
->tx_lock
);
1694 ridx
= sky2_read16(hw
,
1695 sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1696 sky2_tx_complete(sky2
, ridx
);
1697 spin_unlock(&sky2
->tx_lock
);
1699 if (!netif_queue_stopped(dev
)) {
1700 if (net_ratelimit())
1701 pr_info(PFX
"transmit interrupt missed? recovered\n");
1705 if (netif_msg_timer(sky2
))
1706 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1708 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1709 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1711 sky2_tx_clean(sky2
);
1714 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1718 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1719 /* Want receive buffer size to be multiple of 64 bits
1720 * and incl room for vlan and truncation
1722 static inline unsigned sky2_buf_size(int mtu
)
1724 return roundup(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1727 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1729 struct sky2_port
*sky2
= netdev_priv(dev
);
1730 struct sky2_hw
*hw
= sky2
->hw
;
1734 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1737 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1740 if (!netif_running(dev
)) {
1745 sky2_write32(hw
, B0_IMSK
, 0);
1747 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1748 netif_stop_queue(dev
);
1749 netif_poll_disable(hw
->dev
[0]);
1751 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1752 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1754 sky2_rx_clean(sky2
);
1757 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1758 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1759 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1761 if (dev
->mtu
> ETH_DATA_LEN
)
1762 mode
|= GM_SMOD_JUMBO_ENA
;
1764 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1766 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1768 err
= sky2_rx_start(sky2
);
1769 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1774 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1776 netif_poll_enable(hw
->dev
[0]);
1777 netif_wake_queue(dev
);
1784 * Receive one packet.
1785 * For small packets or errors, just reuse existing skb.
1786 * For larger packets, get new buffer.
1788 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1789 u16 length
, u32 status
)
1791 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1792 struct sk_buff
*skb
= NULL
;
1794 if (unlikely(netif_msg_rx_status(sky2
)))
1795 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1796 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1798 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1799 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1801 if (status
& GMR_FS_ANY_ERR
)
1804 if (!(status
& GMR_FS_RX_OK
))
1807 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1810 if (length
< copybreak
) {
1811 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1815 skb_reserve(skb
, 2);
1816 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1817 length
, PCI_DMA_FROMDEVICE
);
1818 memcpy(skb
->data
, re
->skb
->data
, length
);
1819 skb
->ip_summed
= re
->skb
->ip_summed
;
1820 skb
->csum
= re
->skb
->csum
;
1821 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1822 length
, PCI_DMA_FROMDEVICE
);
1824 struct sk_buff
*nskb
;
1826 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1832 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1833 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1834 prefetch(skb
->data
);
1836 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1837 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1840 skb_put(skb
, length
);
1842 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1843 sky2_rx_add(sky2
, re
->mapaddr
);
1845 /* Tell receiver about new buffers. */
1846 sky2_put_idx(sky2
->hw
, rxqaddr
[sky2
->port
], sky2
->rx_put
,
1847 &sky2
->rx_last_put
, RX_LE_SIZE
);
1852 ++sky2
->net_stats
.rx_over_errors
;
1856 ++sky2
->net_stats
.rx_errors
;
1858 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1859 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1860 sky2
->netdev
->name
, status
, length
);
1862 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1863 sky2
->net_stats
.rx_length_errors
++;
1864 if (status
& GMR_FS_FRAGMENT
)
1865 sky2
->net_stats
.rx_frame_errors
++;
1866 if (status
& GMR_FS_CRC_ERR
)
1867 sky2
->net_stats
.rx_crc_errors
++;
1868 if (status
& GMR_FS_RX_FF_OV
)
1869 sky2
->net_stats
.rx_fifo_errors
++;
1875 * Check for transmit complete
1877 #define TX_NO_STATUS 0xffff
1879 static void sky2_tx_check(struct sky2_hw
*hw
, int port
, u16 last
)
1881 if (last
!= TX_NO_STATUS
) {
1882 struct net_device
*dev
= hw
->dev
[port
];
1883 if (dev
&& netif_running(dev
)) {
1884 struct sky2_port
*sky2
= netdev_priv(dev
);
1886 spin_lock(&sky2
->tx_lock
);
1887 sky2_tx_complete(sky2
, last
);
1888 spin_unlock(&sky2
->tx_lock
);
1894 * Both ports share the same status interrupt, therefore there is only
1897 static int sky2_poll(struct net_device
*dev0
, int *budget
)
1899 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
1900 unsigned int to_do
= min(dev0
->quota
, *budget
);
1901 unsigned int work_done
= 0;
1903 u16 tx_done
[2] = { TX_NO_STATUS
, TX_NO_STATUS
};
1905 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
1908 * Kick the STAT_LEV_TIMER_CTRL timer.
1909 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1910 * The if clause is there to start the timer only if it has been
1911 * configured correctly and not been disabled via ethtool.
1913 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_START
) {
1914 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
1915 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
1918 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1919 BUG_ON(hwidx
>= STATUS_RING_SIZE
);
1922 while (hwidx
!= hw
->st_idx
) {
1923 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1924 struct net_device
*dev
;
1925 struct sky2_port
*sky2
;
1926 struct sk_buff
*skb
;
1930 le
= hw
->st_le
+ hw
->st_idx
;
1931 hw
->st_idx
= (hw
->st_idx
+ 1) % STATUS_RING_SIZE
;
1932 prefetch(hw
->st_le
+ hw
->st_idx
);
1934 BUG_ON(le
->link
>= 2);
1935 dev
= hw
->dev
[le
->link
];
1936 if (dev
== NULL
|| !netif_running(dev
))
1939 sky2
= netdev_priv(dev
);
1940 status
= le32_to_cpu(le
->status
);
1941 length
= le16_to_cpu(le
->length
);
1943 switch (le
->opcode
& ~HW_OWNER
) {
1945 skb
= sky2_receive(sky2
, length
, status
);
1950 skb
->protocol
= eth_type_trans(skb
, dev
);
1951 dev
->last_rx
= jiffies
;
1953 #ifdef SKY2_VLAN_TAG_USED
1954 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1955 vlan_hwaccel_receive_skb(skb
,
1957 be16_to_cpu(sky2
->rx_tag
));
1960 netif_receive_skb(skb
);
1962 if (++work_done
>= to_do
)
1966 #ifdef SKY2_VLAN_TAG_USED
1968 sky2
->rx_tag
= length
;
1972 sky2
->rx_tag
= length
;
1976 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1977 skb
->ip_summed
= CHECKSUM_HW
;
1978 skb
->csum
= le16_to_cpu(status
);
1982 /* TX index reports status for both ports */
1983 tx_done
[0] = status
& 0xffff;
1984 tx_done
[1] = ((status
>> 24) & 0xff)
1985 | (u16
)(length
& 0xf) << 8;
1989 if (net_ratelimit())
1990 printk(KERN_WARNING PFX
1991 "unknown status opcode 0x%x\n", le
->opcode
);
1997 sky2_tx_check(hw
, 0, tx_done
[0]);
1998 sky2_tx_check(hw
, 1, tx_done
[1]);
2000 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_START
) {
2001 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2002 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2005 if (likely(work_done
< to_do
)) {
2006 spin_lock_irq(&hw
->hw_lock
);
2007 __netif_rx_complete(dev0
);
2009 hw
->intr_mask
|= Y2_IS_STAT_BMU
;
2010 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2011 spin_unlock_irq(&hw
->hw_lock
);
2015 *budget
-= work_done
;
2016 dev0
->quota
-= work_done
;
2021 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2023 struct net_device
*dev
= hw
->dev
[port
];
2025 if (net_ratelimit())
2026 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2029 if (status
& Y2_IS_PAR_RD1
) {
2030 if (net_ratelimit())
2031 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2034 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2037 if (status
& Y2_IS_PAR_WR1
) {
2038 if (net_ratelimit())
2039 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2042 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2045 if (status
& Y2_IS_PAR_MAC1
) {
2046 if (net_ratelimit())
2047 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2048 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2051 if (status
& Y2_IS_PAR_RX1
) {
2052 if (net_ratelimit())
2053 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2054 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2057 if (status
& Y2_IS_TCP_TXA1
) {
2058 if (net_ratelimit())
2059 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2061 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2065 static void sky2_hw_intr(struct sky2_hw
*hw
)
2067 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2069 if (status
& Y2_IS_TIST_OV
)
2070 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2072 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2075 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2076 if (net_ratelimit())
2077 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2078 pci_name(hw
->pdev
), pci_err
);
2080 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2081 sky2_pci_write16(hw
, PCI_STATUS
,
2082 pci_err
| PCI_STATUS_ERROR_BITS
);
2083 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2086 if (status
& Y2_IS_PCI_EXP
) {
2087 /* PCI-Express uncorrectable Error occurred */
2090 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2092 if (net_ratelimit())
2093 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2094 pci_name(hw
->pdev
), pex_err
);
2096 /* clear the interrupt */
2097 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2098 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2100 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2102 if (pex_err
& PEX_FATAL_ERRORS
) {
2103 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2104 hwmsk
&= ~Y2_IS_PCI_EXP
;
2105 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2109 if (status
& Y2_HWE_L1_MASK
)
2110 sky2_hw_error(hw
, 0, status
);
2112 if (status
& Y2_HWE_L1_MASK
)
2113 sky2_hw_error(hw
, 1, status
);
2116 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2118 struct net_device
*dev
= hw
->dev
[port
];
2119 struct sky2_port
*sky2
= netdev_priv(dev
);
2120 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2122 if (netif_msg_intr(sky2
))
2123 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2126 if (status
& GM_IS_RX_FF_OR
) {
2127 ++sky2
->net_stats
.rx_fifo_errors
;
2128 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2131 if (status
& GM_IS_TX_FF_UR
) {
2132 ++sky2
->net_stats
.tx_fifo_errors
;
2133 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2137 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2139 struct net_device
*dev
= hw
->dev
[port
];
2140 struct sky2_port
*sky2
= netdev_priv(dev
);
2142 hw
->intr_mask
&= ~(port
== 0 ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
);
2143 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2145 schedule_work(&sky2
->phy_task
);
2148 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2150 struct sky2_hw
*hw
= dev_id
;
2151 struct net_device
*dev0
= hw
->dev
[0];
2154 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2155 if (status
== 0 || status
== ~0)
2158 spin_lock(&hw
->hw_lock
);
2159 if (status
& Y2_IS_HW_ERR
)
2162 /* Do NAPI for Rx and Tx status */
2163 if (status
& Y2_IS_STAT_BMU
) {
2164 hw
->intr_mask
&= ~Y2_IS_STAT_BMU
;
2165 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2167 if (likely(__netif_rx_schedule_prep(dev0
))) {
2168 prefetch(&hw
->st_le
[hw
->st_idx
]);
2169 __netif_rx_schedule(dev0
);
2173 if (status
& Y2_IS_IRQ_PHY1
)
2174 sky2_phy_intr(hw
, 0);
2176 if (status
& Y2_IS_IRQ_PHY2
)
2177 sky2_phy_intr(hw
, 1);
2179 if (status
& Y2_IS_IRQ_MAC1
)
2180 sky2_mac_intr(hw
, 0);
2182 if (status
& Y2_IS_IRQ_MAC2
)
2183 sky2_mac_intr(hw
, 1);
2185 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
2187 spin_unlock(&hw
->hw_lock
);
2192 #ifdef CONFIG_NET_POLL_CONTROLLER
2193 static void sky2_netpoll(struct net_device
*dev
)
2195 struct sky2_port
*sky2
= netdev_priv(dev
);
2197 sky2_intr(sky2
->hw
->pdev
->irq
, sky2
->hw
, NULL
);
2201 /* Chip internal frequency for clock calculations */
2202 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2204 switch (hw
->chip_id
) {
2205 case CHIP_ID_YUKON_EC
:
2206 case CHIP_ID_YUKON_EC_U
:
2207 return 125; /* 125 Mhz */
2208 case CHIP_ID_YUKON_FE
:
2209 return 100; /* 100 Mhz */
2210 default: /* YUKON_XL */
2211 return 156; /* 156 Mhz */
2215 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2217 return sky2_mhz(hw
) * us
;
2220 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2222 return clk
/ sky2_mhz(hw
);
2226 static int sky2_reset(struct sky2_hw
*hw
)
2232 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2234 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2235 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2236 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2237 pci_name(hw
->pdev
), hw
->chip_id
);
2242 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2243 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2244 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2248 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2249 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2251 /* clear PCI errors, if any */
2252 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2254 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2255 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2258 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2260 /* clear any PEX errors */
2261 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2262 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2265 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2266 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2269 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2270 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2271 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2274 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2276 sky2_set_power_state(hw
, PCI_D0
);
2278 for (i
= 0; i
< hw
->ports
; i
++) {
2279 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2280 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2283 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2285 /* Clear I2C IRQ noise */
2286 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2288 /* turn off hardware timer (unused) */
2289 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2290 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2292 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2294 /* Turn off descriptor polling */
2295 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2297 /* Turn off receive timestamp */
2298 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2299 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2301 /* enable the Tx Arbiters */
2302 for (i
= 0; i
< hw
->ports
; i
++)
2303 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2305 /* Initialize ram interface */
2306 for (i
= 0; i
< hw
->ports
; i
++) {
2307 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2309 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2310 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2311 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2312 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2313 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2314 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2315 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2316 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2317 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2318 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2319 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2320 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2323 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2325 for (i
= 0; i
< hw
->ports
; i
++)
2326 sky2_phy_reset(hw
, i
);
2328 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2331 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2332 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2334 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2335 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2337 /* Set the list last index */
2338 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2340 /* These status setup values are copied from SysKonnect's driver */
2342 /* WA for dev. #4.3 */
2343 sky2_write16(hw
, STAT_TX_IDX_TH
, 0xfff); /* Tx Threshold */
2345 /* set Status-FIFO watermark */
2346 sky2_write8(hw
, STAT_FIFO_WM
, 0x21); /* WA for dev. #4.18 */
2348 /* set Status-FIFO ISR watermark */
2349 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 0x07); /* WA for dev. #4.18 */
2350 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 10000));
2352 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2353 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2355 /* set Status-FIFO ISR watermark */
2356 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2357 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2359 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2361 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2362 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 7));
2365 /* enable status unit */
2366 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2368 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2369 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2370 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2375 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2379 modes
= SUPPORTED_10baseT_Half
2380 | SUPPORTED_10baseT_Full
2381 | SUPPORTED_100baseT_Half
2382 | SUPPORTED_100baseT_Full
2383 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2385 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2386 modes
|= SUPPORTED_1000baseT_Half
2387 | SUPPORTED_1000baseT_Full
;
2389 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2390 | SUPPORTED_Autoneg
;
2394 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2396 struct sky2_port
*sky2
= netdev_priv(dev
);
2397 struct sky2_hw
*hw
= sky2
->hw
;
2399 ecmd
->transceiver
= XCVR_INTERNAL
;
2400 ecmd
->supported
= sky2_supported_modes(hw
);
2401 ecmd
->phy_address
= PHY_ADDR_MARV
;
2403 ecmd
->supported
= SUPPORTED_10baseT_Half
2404 | SUPPORTED_10baseT_Full
2405 | SUPPORTED_100baseT_Half
2406 | SUPPORTED_100baseT_Full
2407 | SUPPORTED_1000baseT_Half
2408 | SUPPORTED_1000baseT_Full
2409 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2410 ecmd
->port
= PORT_TP
;
2412 ecmd
->port
= PORT_FIBRE
;
2414 ecmd
->advertising
= sky2
->advertising
;
2415 ecmd
->autoneg
= sky2
->autoneg
;
2416 ecmd
->speed
= sky2
->speed
;
2417 ecmd
->duplex
= sky2
->duplex
;
2421 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2423 struct sky2_port
*sky2
= netdev_priv(dev
);
2424 const struct sky2_hw
*hw
= sky2
->hw
;
2425 u32 supported
= sky2_supported_modes(hw
);
2427 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2428 ecmd
->advertising
= supported
;
2434 switch (ecmd
->speed
) {
2436 if (ecmd
->duplex
== DUPLEX_FULL
)
2437 setting
= SUPPORTED_1000baseT_Full
;
2438 else if (ecmd
->duplex
== DUPLEX_HALF
)
2439 setting
= SUPPORTED_1000baseT_Half
;
2444 if (ecmd
->duplex
== DUPLEX_FULL
)
2445 setting
= SUPPORTED_100baseT_Full
;
2446 else if (ecmd
->duplex
== DUPLEX_HALF
)
2447 setting
= SUPPORTED_100baseT_Half
;
2453 if (ecmd
->duplex
== DUPLEX_FULL
)
2454 setting
= SUPPORTED_10baseT_Full
;
2455 else if (ecmd
->duplex
== DUPLEX_HALF
)
2456 setting
= SUPPORTED_10baseT_Half
;
2464 if ((setting
& supported
) == 0)
2467 sky2
->speed
= ecmd
->speed
;
2468 sky2
->duplex
= ecmd
->duplex
;
2471 sky2
->autoneg
= ecmd
->autoneg
;
2472 sky2
->advertising
= ecmd
->advertising
;
2474 if (netif_running(dev
))
2475 sky2_phy_reinit(sky2
);
2480 static void sky2_get_drvinfo(struct net_device
*dev
,
2481 struct ethtool_drvinfo
*info
)
2483 struct sky2_port
*sky2
= netdev_priv(dev
);
2485 strcpy(info
->driver
, DRV_NAME
);
2486 strcpy(info
->version
, DRV_VERSION
);
2487 strcpy(info
->fw_version
, "N/A");
2488 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2491 static const struct sky2_stat
{
2492 char name
[ETH_GSTRING_LEN
];
2495 { "tx_bytes", GM_TXO_OK_HI
},
2496 { "rx_bytes", GM_RXO_OK_HI
},
2497 { "tx_broadcast", GM_TXF_BC_OK
},
2498 { "rx_broadcast", GM_RXF_BC_OK
},
2499 { "tx_multicast", GM_TXF_MC_OK
},
2500 { "rx_multicast", GM_RXF_MC_OK
},
2501 { "tx_unicast", GM_TXF_UC_OK
},
2502 { "rx_unicast", GM_RXF_UC_OK
},
2503 { "tx_mac_pause", GM_TXF_MPAUSE
},
2504 { "rx_mac_pause", GM_RXF_MPAUSE
},
2505 { "collisions", GM_TXF_SNG_COL
},
2506 { "late_collision",GM_TXF_LAT_COL
},
2507 { "aborted", GM_TXF_ABO_COL
},
2508 { "multi_collisions", GM_TXF_MUL_COL
},
2509 { "fifo_underrun", GM_TXE_FIFO_UR
},
2510 { "fifo_overflow", GM_RXE_FIFO_OV
},
2511 { "rx_toolong", GM_RXF_LNG_ERR
},
2512 { "rx_jabber", GM_RXF_JAB_PKT
},
2513 { "rx_runt", GM_RXE_FRAG
},
2514 { "rx_too_long", GM_RXF_LNG_ERR
},
2515 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2518 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2520 struct sky2_port
*sky2
= netdev_priv(dev
);
2522 return sky2
->rx_csum
;
2525 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2527 struct sky2_port
*sky2
= netdev_priv(dev
);
2529 sky2
->rx_csum
= data
;
2531 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2532 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2537 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2539 struct sky2_port
*sky2
= netdev_priv(netdev
);
2540 return sky2
->msg_enable
;
2543 static int sky2_nway_reset(struct net_device
*dev
)
2545 struct sky2_port
*sky2
= netdev_priv(dev
);
2547 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2550 sky2_phy_reinit(sky2
);
2555 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2557 struct sky2_hw
*hw
= sky2
->hw
;
2558 unsigned port
= sky2
->port
;
2561 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2562 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2563 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2564 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2566 for (i
= 2; i
< count
; i
++)
2567 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2570 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2572 struct sky2_port
*sky2
= netdev_priv(netdev
);
2573 sky2
->msg_enable
= value
;
2576 static int sky2_get_stats_count(struct net_device
*dev
)
2578 return ARRAY_SIZE(sky2_stats
);
2581 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2582 struct ethtool_stats
*stats
, u64
* data
)
2584 struct sky2_port
*sky2
= netdev_priv(dev
);
2586 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2589 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2593 switch (stringset
) {
2595 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2596 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2597 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2602 /* Use hardware MIB variables for critical path statistics and
2603 * transmit feedback not reported at interrupt.
2604 * Other errors are accounted for in interrupt handler.
2606 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2608 struct sky2_port
*sky2
= netdev_priv(dev
);
2611 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2613 sky2
->net_stats
.tx_bytes
= data
[0];
2614 sky2
->net_stats
.rx_bytes
= data
[1];
2615 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2616 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2617 sky2
->net_stats
.multicast
= data
[5] + data
[7];
2618 sky2
->net_stats
.collisions
= data
[10];
2619 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2621 return &sky2
->net_stats
;
2624 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2626 struct sky2_port
*sky2
= netdev_priv(dev
);
2627 struct sky2_hw
*hw
= sky2
->hw
;
2628 unsigned port
= sky2
->port
;
2629 const struct sockaddr
*addr
= p
;
2631 if (!is_valid_ether_addr(addr
->sa_data
))
2632 return -EADDRNOTAVAIL
;
2634 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2635 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2636 dev
->dev_addr
, ETH_ALEN
);
2637 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2638 dev
->dev_addr
, ETH_ALEN
);
2640 /* virtual address for data */
2641 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2643 /* physical address: used for pause frames */
2644 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2649 static void sky2_set_multicast(struct net_device
*dev
)
2651 struct sky2_port
*sky2
= netdev_priv(dev
);
2652 struct sky2_hw
*hw
= sky2
->hw
;
2653 unsigned port
= sky2
->port
;
2654 struct dev_mc_list
*list
= dev
->mc_list
;
2658 memset(filter
, 0, sizeof(filter
));
2660 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2661 reg
|= GM_RXCR_UCF_ENA
;
2663 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2664 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2665 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2666 memset(filter
, 0xff, sizeof(filter
));
2667 else if (dev
->mc_count
== 0) /* no multicast */
2668 reg
&= ~GM_RXCR_MCF_ENA
;
2671 reg
|= GM_RXCR_MCF_ENA
;
2673 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2674 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2675 filter
[bit
/ 8] |= 1 << (bit
% 8);
2679 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2680 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2681 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2682 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2683 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2684 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2685 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2686 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2688 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2691 /* Can have one global because blinking is controlled by
2692 * ethtool and that is always under RTNL mutex
2694 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2698 switch (hw
->chip_id
) {
2699 case CHIP_ID_YUKON_XL
:
2700 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2701 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2702 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2703 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2704 PHY_M_LEDC_INIT_CTRL(7) |
2705 PHY_M_LEDC_STA1_CTRL(7) |
2706 PHY_M_LEDC_STA0_CTRL(7))
2709 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2713 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2714 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2715 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2716 PHY_M_LED_MO_10(MO_LED_ON
) |
2717 PHY_M_LED_MO_100(MO_LED_ON
) |
2718 PHY_M_LED_MO_1000(MO_LED_ON
) |
2719 PHY_M_LED_MO_RX(MO_LED_ON
)
2720 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2721 PHY_M_LED_MO_10(MO_LED_OFF
) |
2722 PHY_M_LED_MO_100(MO_LED_OFF
) |
2723 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2724 PHY_M_LED_MO_RX(MO_LED_OFF
));
2729 /* blink LED's for finding board */
2730 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2732 struct sky2_port
*sky2
= netdev_priv(dev
);
2733 struct sky2_hw
*hw
= sky2
->hw
;
2734 unsigned port
= sky2
->port
;
2735 u16 ledctrl
, ledover
= 0;
2740 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2741 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2745 /* save initial values */
2746 down(&sky2
->phy_sema
);
2747 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2748 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2749 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2750 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2751 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2753 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2754 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2758 while (!interrupted
&& ms
> 0) {
2759 sky2_led(hw
, port
, onoff
);
2762 up(&sky2
->phy_sema
);
2763 interrupted
= msleep_interruptible(250);
2764 down(&sky2
->phy_sema
);
2769 /* resume regularly scheduled programming */
2770 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2771 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2772 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2773 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2774 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2776 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2777 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2779 up(&sky2
->phy_sema
);
2784 static void sky2_get_pauseparam(struct net_device
*dev
,
2785 struct ethtool_pauseparam
*ecmd
)
2787 struct sky2_port
*sky2
= netdev_priv(dev
);
2789 ecmd
->tx_pause
= sky2
->tx_pause
;
2790 ecmd
->rx_pause
= sky2
->rx_pause
;
2791 ecmd
->autoneg
= sky2
->autoneg
;
2794 static int sky2_set_pauseparam(struct net_device
*dev
,
2795 struct ethtool_pauseparam
*ecmd
)
2797 struct sky2_port
*sky2
= netdev_priv(dev
);
2800 sky2
->autoneg
= ecmd
->autoneg
;
2801 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2802 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2804 sky2_phy_reinit(sky2
);
2810 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2812 struct sky2_port
*sky2
= netdev_priv(dev
);
2814 wol
->supported
= WAKE_MAGIC
;
2815 wol
->wolopts
= sky2
->wol
? WAKE_MAGIC
: 0;
2818 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2820 struct sky2_port
*sky2
= netdev_priv(dev
);
2821 struct sky2_hw
*hw
= sky2
->hw
;
2823 if (wol
->wolopts
!= WAKE_MAGIC
&& wol
->wolopts
!= 0)
2826 sky2
->wol
= wol
->wolopts
== WAKE_MAGIC
;
2829 memcpy_toio(hw
->regs
+ WOL_MAC_ADDR
, dev
->dev_addr
, ETH_ALEN
);
2831 sky2_write16(hw
, WOL_CTRL_STAT
,
2832 WOL_CTL_ENA_PME_ON_MAGIC_PKT
|
2833 WOL_CTL_ENA_MAGIC_PKT_UNIT
);
2835 sky2_write16(hw
, WOL_CTRL_STAT
, WOL_CTL_DEFAULT
);
2841 static int sky2_get_coalesce(struct net_device
*dev
,
2842 struct ethtool_coalesce
*ecmd
)
2844 struct sky2_port
*sky2
= netdev_priv(dev
);
2845 struct sky2_hw
*hw
= sky2
->hw
;
2847 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2848 ecmd
->tx_coalesce_usecs
= 0;
2850 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2851 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2853 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2855 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2856 ecmd
->rx_coalesce_usecs
= 0;
2858 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2859 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2861 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2863 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2864 ecmd
->rx_coalesce_usecs_irq
= 0;
2866 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2867 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2870 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2875 /* Note: this affect both ports */
2876 static int sky2_set_coalesce(struct net_device
*dev
,
2877 struct ethtool_coalesce
*ecmd
)
2879 struct sky2_port
*sky2
= netdev_priv(dev
);
2880 struct sky2_hw
*hw
= sky2
->hw
;
2881 const u32 tmin
= sky2_clk2us(hw
, 1);
2882 const u32 tmax
= 5000;
2884 if (ecmd
->tx_coalesce_usecs
!= 0 &&
2885 (ecmd
->tx_coalesce_usecs
< tmin
|| ecmd
->tx_coalesce_usecs
> tmax
))
2888 if (ecmd
->rx_coalesce_usecs
!= 0 &&
2889 (ecmd
->rx_coalesce_usecs
< tmin
|| ecmd
->rx_coalesce_usecs
> tmax
))
2892 if (ecmd
->rx_coalesce_usecs_irq
!= 0 &&
2893 (ecmd
->rx_coalesce_usecs_irq
< tmin
|| ecmd
->rx_coalesce_usecs_irq
> tmax
))
2896 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2898 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2900 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2903 if (ecmd
->tx_coalesce_usecs
== 0)
2904 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2906 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2907 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2908 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2910 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2912 if (ecmd
->rx_coalesce_usecs
== 0)
2913 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2915 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2916 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2917 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2919 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2921 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2922 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2924 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2925 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2926 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2928 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2932 static void sky2_get_ringparam(struct net_device
*dev
,
2933 struct ethtool_ringparam
*ering
)
2935 struct sky2_port
*sky2
= netdev_priv(dev
);
2937 ering
->rx_max_pending
= RX_MAX_PENDING
;
2938 ering
->rx_mini_max_pending
= 0;
2939 ering
->rx_jumbo_max_pending
= 0;
2940 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2942 ering
->rx_pending
= sky2
->rx_pending
;
2943 ering
->rx_mini_pending
= 0;
2944 ering
->rx_jumbo_pending
= 0;
2945 ering
->tx_pending
= sky2
->tx_pending
;
2948 static int sky2_set_ringparam(struct net_device
*dev
,
2949 struct ethtool_ringparam
*ering
)
2951 struct sky2_port
*sky2
= netdev_priv(dev
);
2954 if (ering
->rx_pending
> RX_MAX_PENDING
||
2955 ering
->rx_pending
< 8 ||
2956 ering
->tx_pending
< MAX_SKB_TX_LE
||
2957 ering
->tx_pending
> TX_RING_SIZE
- 1)
2960 if (netif_running(dev
))
2963 sky2
->rx_pending
= ering
->rx_pending
;
2964 sky2
->tx_pending
= ering
->tx_pending
;
2966 if (netif_running(dev
)) {
2971 sky2_set_multicast(dev
);
2977 static int sky2_get_regs_len(struct net_device
*dev
)
2983 * Returns copy of control register region
2984 * Note: access to the RAM address register set will cause timeouts.
2986 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2989 const struct sky2_port
*sky2
= netdev_priv(dev
);
2990 const void __iomem
*io
= sky2
->hw
->regs
;
2992 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
2994 memset(p
, 0, regs
->len
);
2996 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
2998 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3000 regs
->len
- B3_RI_WTO_R1
);
3003 static struct ethtool_ops sky2_ethtool_ops
= {
3004 .get_settings
= sky2_get_settings
,
3005 .set_settings
= sky2_set_settings
,
3006 .get_drvinfo
= sky2_get_drvinfo
,
3007 .get_msglevel
= sky2_get_msglevel
,
3008 .set_msglevel
= sky2_set_msglevel
,
3009 .nway_reset
= sky2_nway_reset
,
3010 .get_regs_len
= sky2_get_regs_len
,
3011 .get_regs
= sky2_get_regs
,
3012 .get_link
= ethtool_op_get_link
,
3013 .get_sg
= ethtool_op_get_sg
,
3014 .set_sg
= ethtool_op_set_sg
,
3015 .get_tx_csum
= ethtool_op_get_tx_csum
,
3016 .set_tx_csum
= ethtool_op_set_tx_csum
,
3017 .get_tso
= ethtool_op_get_tso
,
3018 .set_tso
= ethtool_op_set_tso
,
3019 .get_rx_csum
= sky2_get_rx_csum
,
3020 .set_rx_csum
= sky2_set_rx_csum
,
3021 .get_strings
= sky2_get_strings
,
3022 .get_coalesce
= sky2_get_coalesce
,
3023 .set_coalesce
= sky2_set_coalesce
,
3024 .get_ringparam
= sky2_get_ringparam
,
3025 .set_ringparam
= sky2_set_ringparam
,
3026 .get_pauseparam
= sky2_get_pauseparam
,
3027 .set_pauseparam
= sky2_set_pauseparam
,
3029 .get_wol
= sky2_get_wol
,
3030 .set_wol
= sky2_set_wol
,
3032 .phys_id
= sky2_phys_id
,
3033 .get_stats_count
= sky2_get_stats_count
,
3034 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3035 .get_perm_addr
= ethtool_op_get_perm_addr
,
3038 /* Initialize network device */
3039 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3040 unsigned port
, int highmem
)
3042 struct sky2_port
*sky2
;
3043 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3046 printk(KERN_ERR
"sky2 etherdev alloc failed");
3050 SET_MODULE_OWNER(dev
);
3051 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3052 dev
->irq
= hw
->pdev
->irq
;
3053 dev
->open
= sky2_up
;
3054 dev
->stop
= sky2_down
;
3055 dev
->do_ioctl
= sky2_ioctl
;
3056 dev
->hard_start_xmit
= sky2_xmit_frame
;
3057 dev
->get_stats
= sky2_get_stats
;
3058 dev
->set_multicast_list
= sky2_set_multicast
;
3059 dev
->set_mac_address
= sky2_set_mac_address
;
3060 dev
->change_mtu
= sky2_change_mtu
;
3061 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3062 dev
->tx_timeout
= sky2_tx_timeout
;
3063 dev
->watchdog_timeo
= TX_WATCHDOG
;
3065 dev
->poll
= sky2_poll
;
3066 dev
->weight
= NAPI_WEIGHT
;
3067 #ifdef CONFIG_NET_POLL_CONTROLLER
3068 dev
->poll_controller
= sky2_netpoll
;
3071 sky2
= netdev_priv(dev
);
3074 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3076 spin_lock_init(&sky2
->tx_lock
);
3077 /* Auto speed and flow control */
3078 sky2
->autoneg
= AUTONEG_ENABLE
;
3083 sky2
->advertising
= sky2_supported_modes(hw
);
3085 /* Receive checksum disabled for Yukon XL
3086 * because of observed problems with incorrect
3087 * values when multiple packets are received in one interrupt
3089 sky2
->rx_csum
= (hw
->chip_id
!= CHIP_ID_YUKON_XL
);
3091 INIT_WORK(&sky2
->phy_task
, sky2_phy_task
, sky2
);
3092 init_MUTEX(&sky2
->phy_sema
);
3093 sky2
->tx_pending
= TX_DEF_PENDING
;
3094 sky2
->rx_pending
= is_ec_a1(hw
) ? 8 : RX_DEF_PENDING
;
3095 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3097 hw
->dev
[port
] = dev
;
3101 dev
->features
|= NETIF_F_LLTX
;
3102 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3103 dev
->features
|= NETIF_F_TSO
;
3105 dev
->features
|= NETIF_F_HIGHDMA
;
3106 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3108 #ifdef SKY2_VLAN_TAG_USED
3109 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3110 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3111 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3114 /* read the mac address */
3115 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3116 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3118 /* device is off until link detection */
3119 netif_carrier_off(dev
);
3120 netif_stop_queue(dev
);
3125 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3127 const struct sky2_port
*sky2
= netdev_priv(dev
);
3129 if (netif_msg_probe(sky2
))
3130 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3132 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3133 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3136 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3137 const struct pci_device_id
*ent
)
3139 struct net_device
*dev
, *dev1
= NULL
;
3141 int err
, pm_cap
, using_dac
= 0;
3143 err
= pci_enable_device(pdev
);
3145 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3150 err
= pci_request_regions(pdev
, DRV_NAME
);
3152 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3157 pci_set_master(pdev
);
3159 /* Find power-management capability. */
3160 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3162 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3165 goto err_out_free_regions
;
3168 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3169 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3171 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3173 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3174 "for consistent allocations\n", pci_name(pdev
));
3175 goto err_out_free_regions
;
3179 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3181 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3183 goto err_out_free_regions
;
3188 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3190 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3192 goto err_out_free_regions
;
3197 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3199 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3201 goto err_out_free_hw
;
3203 hw
->pm_cap
= pm_cap
;
3204 spin_lock_init(&hw
->hw_lock
);
3207 /* byte swap descriptors in hardware */
3211 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3212 reg
|= PCI_REV_DESC
;
3213 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3217 /* ring for status responses */
3218 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3221 goto err_out_iounmap
;
3223 err
= sky2_reset(hw
);
3225 goto err_out_iounmap
;
3227 printk(KERN_INFO PFX
"v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3228 DRV_VERSION
, pci_resource_start(pdev
, 0), pdev
->irq
,
3229 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3230 hw
->chip_id
, hw
->chip_rev
);
3232 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3234 goto err_out_free_pci
;
3236 err
= register_netdev(dev
);
3238 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3240 goto err_out_free_netdev
;
3243 sky2_show_addr(dev
);
3245 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3246 if (register_netdev(dev1
) == 0)
3247 sky2_show_addr(dev1
);
3249 /* Failure to register second port need not be fatal */
3250 printk(KERN_WARNING PFX
3251 "register of second port failed\n");
3257 err
= request_irq(pdev
->irq
, sky2_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3259 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3260 pci_name(pdev
), pdev
->irq
);
3261 goto err_out_unregister
;
3264 hw
->intr_mask
= Y2_IS_BASE
;
3265 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3267 pci_set_drvdata(pdev
, hw
);
3273 unregister_netdev(dev1
);
3276 unregister_netdev(dev
);
3277 err_out_free_netdev
:
3280 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3281 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3286 err_out_free_regions
:
3287 pci_release_regions(pdev
);
3288 pci_disable_device(pdev
);
3293 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3295 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3296 struct net_device
*dev0
, *dev1
;
3304 unregister_netdev(dev1
);
3305 unregister_netdev(dev0
);
3307 sky2_write32(hw
, B0_IMSK
, 0);
3308 sky2_set_power_state(hw
, PCI_D3hot
);
3309 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3310 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3311 sky2_read8(hw
, B0_CTST
);
3313 free_irq(pdev
->irq
, hw
);
3314 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3315 pci_release_regions(pdev
);
3316 pci_disable_device(pdev
);
3324 pci_set_drvdata(pdev
, NULL
);
3328 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3330 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3333 for (i
= 0; i
< 2; i
++) {
3334 struct net_device
*dev
= hw
->dev
[i
];
3337 if (!netif_running(dev
))
3341 netif_device_detach(dev
);
3345 return sky2_set_power_state(hw
, pci_choose_state(pdev
, state
));
3348 static int sky2_resume(struct pci_dev
*pdev
)
3350 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3353 pci_restore_state(pdev
);
3354 pci_enable_wake(pdev
, PCI_D0
, 0);
3355 err
= sky2_set_power_state(hw
, PCI_D0
);
3359 err
= sky2_reset(hw
);
3363 for (i
= 0; i
< 2; i
++) {
3364 struct net_device
*dev
= hw
->dev
[i
];
3365 if (dev
&& netif_running(dev
)) {
3366 netif_device_attach(dev
);
3369 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3381 static struct pci_driver sky2_driver
= {
3383 .id_table
= sky2_id_table
,
3384 .probe
= sky2_probe
,
3385 .remove
= __devexit_p(sky2_remove
),
3387 .suspend
= sky2_suspend
,
3388 .resume
= sky2_resume
,
3392 static int __init
sky2_init_module(void)
3394 return pci_register_driver(&sky2_driver
);
3397 static void __exit
sky2_cleanup_module(void)
3399 pci_unregister_driver(&sky2_driver
);
3402 module_init(sky2_init_module
);
3403 module_exit(sky2_cleanup_module
);
3405 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3406 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3407 MODULE_LICENSE("GPL");
3408 MODULE_VERSION(DRV_VERSION
);