2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.2"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 static const u32 default_msg
=
83 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
84 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
87 static int debug
= -1; /* defaults above */
88 module_param(debug
, int, 0);
89 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly
= 256;
92 module_param(copybreak
, int, 0);
93 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
95 static int disable_msi
= 0;
96 module_param(disable_msi
, int, 0);
97 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
99 static const struct pci_device_id sky2_id_table
[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
120 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
122 /* Avoid conditionals by using array */
123 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
124 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
126 /* This driver supports yukon2 chipset only */
127 static const char *yukon2_name
[] = {
129 "EC Ultra", /* 0xb4 */
130 "UNKNOWN", /* 0xb5 */
135 /* Access to external PHY */
136 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
140 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
141 gma_write16(hw
, port
, GM_SMI_CTRL
,
142 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
144 for (i
= 0; i
< PHY_RETRIES
; i
++) {
145 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
150 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
154 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
158 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
159 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
161 for (i
= 0; i
< PHY_RETRIES
; i
++) {
162 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
163 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
173 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
177 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
178 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
182 static int sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
189 pr_debug("sky2_set_power_state %d\n", state
);
190 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
192 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
193 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
194 (power_control
& PCI_PM_CAP_PME_D3cold
);
196 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
198 power_control
|= PCI_PM_CTRL_PME_STATUS
;
199 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw
, B0_POWER_CTRL
,
205 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
207 /* disable Core Clock Division, */
208 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
210 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
211 /* enable bits are inverted */
212 sky2_write8(hw
, B2_Y2_CLK_GATE
,
213 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
214 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
215 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
217 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
219 /* Turn off phy power saving */
220 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
221 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
223 /* looks like this XL is back asswards .. */
224 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
225 reg1
|= PCI_Y2_PHY1_COMA
;
227 reg1
|= PCI_Y2_PHY2_COMA
;
230 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
231 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
232 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
233 reg1
&= P_ASPM_CONTROL_MSK
;
234 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
235 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
238 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
244 /* Turn on phy power saving */
245 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
246 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
247 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
249 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
250 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
252 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
253 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
255 /* enable bits are inverted */
256 sky2_write8(hw
, B2_Y2_CLK_GATE
,
257 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
258 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
259 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
261 /* switch power to VAUX */
262 if (vaux
&& state
!= PCI_D3cold
)
263 sky2_write8(hw
, B0_POWER_CTRL
,
264 (PC_VAUX_ENA
| PC_VCC_ENA
|
265 PC_VAUX_ON
| PC_VCC_OFF
));
268 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
272 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
273 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
277 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
283 /* disable PHY IRQs */
284 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
286 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
287 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
288 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
289 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
291 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
292 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
293 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
296 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
298 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
299 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
301 if (sky2
->autoneg
== AUTONEG_ENABLE
&& hw
->chip_id
!= CHIP_ID_YUKON_XL
) {
302 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
304 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
306 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
308 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
309 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
311 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
313 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
316 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
318 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
319 /* enable automatic crossover */
320 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
322 /* disable energy detect */
323 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
325 /* enable automatic crossover */
326 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
328 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
329 hw
->chip_id
== CHIP_ID_YUKON_XL
) {
330 ctrl
&= ~PHY_M_PC_DSC_MSK
;
331 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
334 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
336 /* workaround for deviation #4.88 (CRC errors) */
337 /* disable Automatic Crossover */
339 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
340 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
342 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
343 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
344 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
345 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
346 ctrl
&= ~PHY_M_MAC_MD_MSK
;
347 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
348 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
350 /* select page 1 to access Fiber registers */
351 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
355 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
356 if (sky2
->autoneg
== AUTONEG_DISABLE
)
361 ctrl
|= PHY_CT_RESET
;
362 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
368 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
370 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
371 ct1000
|= PHY_M_1000C_AFD
;
372 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
373 ct1000
|= PHY_M_1000C_AHD
;
374 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
375 adv
|= PHY_M_AN_100_FD
;
376 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
377 adv
|= PHY_M_AN_100_HD
;
378 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
379 adv
|= PHY_M_AN_10_FD
;
380 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
381 adv
|= PHY_M_AN_10_HD
;
382 } else /* special defines for FIBER (88E1011S only) */
383 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
385 /* Set Flow-control capabilities */
386 if (sky2
->tx_pause
&& sky2
->rx_pause
)
387 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
388 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
389 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
390 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
391 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
393 /* Restart Auto-negotiation */
394 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
396 /* forced speed/duplex settings */
397 ct1000
= PHY_M_1000C_MSE
;
399 if (sky2
->duplex
== DUPLEX_FULL
)
400 ctrl
|= PHY_CT_DUP_MD
;
402 switch (sky2
->speed
) {
404 ctrl
|= PHY_CT_SP1000
;
407 ctrl
|= PHY_CT_SP100
;
411 ctrl
|= PHY_CT_RESET
;
414 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
415 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
417 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
418 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
420 /* Setup Phy LED's */
421 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
424 switch (hw
->chip_id
) {
425 case CHIP_ID_YUKON_FE
:
426 /* on 88E3082 these bits are at 11..9 (shifted left) */
427 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
429 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
431 /* delete ACT LED control bits */
432 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
433 /* change ACT LED control to blink mode */
434 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
435 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
438 case CHIP_ID_YUKON_XL
:
439 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
441 /* select page 3 to access LED control register */
442 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
444 /* set LED Function Control register */
445 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
446 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
447 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
448 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
450 /* set Polarity Control register */
451 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
452 (PHY_M_POLC_LS1_P_MIX(4) |
453 PHY_M_POLC_IS0_P_MIX(4) |
454 PHY_M_POLC_LOS_CTRL(2) |
455 PHY_M_POLC_INIT_CTRL(2) |
456 PHY_M_POLC_STA1_CTRL(2) |
457 PHY_M_POLC_STA0_CTRL(2)));
459 /* restore page register */
460 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
464 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
465 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
466 /* turn off the Rx LED (LED_RX) */
467 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
470 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
471 /* apply fixes in PHY AFE */
472 gm_phy_write(hw
, port
, 22, 255);
473 /* increase differential signal amplitude in 10BASE-T */
474 gm_phy_write(hw
, port
, 24, 0xaa99);
475 gm_phy_write(hw
, port
, 23, 0x2011);
477 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
478 gm_phy_write(hw
, port
, 24, 0xa204);
479 gm_phy_write(hw
, port
, 23, 0x2002);
481 /* set page register to 0 */
482 gm_phy_write(hw
, port
, 22, 0);
484 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
486 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
487 /* turn on 100 Mbps LED (LED_LINK100) */
488 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
492 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
495 /* Enable phy interrupt on auto-negotiation complete (or link up) */
496 if (sky2
->autoneg
== AUTONEG_ENABLE
)
497 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
499 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
502 /* Force a renegotiation */
503 static void sky2_phy_reinit(struct sky2_port
*sky2
)
505 spin_lock_bh(&sky2
->phy_lock
);
506 sky2_phy_init(sky2
->hw
, sky2
->port
);
507 spin_unlock_bh(&sky2
->phy_lock
);
510 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
512 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
515 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
517 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
518 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
520 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
522 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
523 /* WA DEV_472 -- looks like crossed wires on port 2 */
524 /* clear GMAC 1 Control reset */
525 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
527 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
528 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
529 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
530 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
531 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
534 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
535 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
536 reg
|= GM_GPCR_AU_ALL_DIS
;
537 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
538 gma_read16(hw
, port
, GM_GP_CTRL
);
540 switch (sky2
->speed
) {
542 reg
&= ~GM_GPCR_SPEED_100
;
543 reg
|= GM_GPCR_SPEED_1000
;
546 reg
&= ~GM_GPCR_SPEED_1000
;
547 reg
|= GM_GPCR_SPEED_100
;
550 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
554 if (sky2
->duplex
== DUPLEX_FULL
)
555 reg
|= GM_GPCR_DUP_FULL
;
557 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
559 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
560 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
562 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
563 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
564 /* disable Rx flow-control */
565 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
568 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
570 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
572 spin_lock_bh(&sky2
->phy_lock
);
573 sky2_phy_init(hw
, port
);
574 spin_unlock_bh(&sky2
->phy_lock
);
577 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
578 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
580 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
581 gma_read16(hw
, port
, i
);
582 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
584 /* transmit control */
585 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
587 /* receive control reg: unicast + multicast + no FCS */
588 gma_write16(hw
, port
, GM_RX_CTRL
,
589 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
591 /* transmit flow control */
592 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
594 /* transmit parameter */
595 gma_write16(hw
, port
, GM_TX_PARAM
,
596 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
597 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
598 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
599 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
601 /* serial mode register */
602 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
603 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
605 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
606 reg
|= GM_SMOD_JUMBO_ENA
;
608 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
610 /* virtual address for data */
611 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
613 /* physical address: used for pause frames */
614 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
616 /* ignore counter overflows */
617 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
618 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
619 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
621 /* Configure Rx MAC FIFO */
622 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
623 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
624 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
626 /* Flush Rx MAC FIFO on any flow control or error */
627 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
629 /* Set threshold to 0xa (64 bytes)
630 * ASF disabled so no need to do WA dev #4.30
632 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
634 /* Configure Tx MAC FIFO */
635 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
636 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
638 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
639 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
640 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
641 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
642 /* set Tx GMAC FIFO Almost Empty Threshold */
643 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
644 /* Disable Store & Forward mode for TX */
645 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
651 /* Assign Ram Buffer allocation.
652 * start and end are in units of 4k bytes
653 * ram registers are in units of 64bit words
655 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
659 start
= startk
* 4096/8;
660 end
= (endk
* 4096/8) - 1;
662 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
663 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
664 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
665 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
666 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
668 if (q
== Q_R1
|| q
== Q_R2
) {
669 u32 space
= (endk
- startk
) * 4096/8;
670 u32 tp
= space
- space
/4;
672 /* On receive queue's set the thresholds
673 * give receiver priority when > 3/4 full
674 * send pause when down to 2K
676 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
677 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
680 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
681 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
683 /* Enable store & forward on Tx queue's because
684 * Tx FIFO is only 1K on Yukon
686 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
689 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
690 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
693 /* Setup Bus Memory Interface */
694 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
696 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
697 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
698 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
699 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
702 /* Setup prefetch unit registers. This is the interface between
703 * hardware and driver list elements
705 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
708 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
709 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
710 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
711 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
712 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
713 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
715 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
718 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
720 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
722 sky2
->tx_prod
= (sky2
->tx_prod
+ 1) % TX_RING_SIZE
;
726 /* Update chip's next pointer */
727 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
730 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
735 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
737 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
738 sky2
->rx_put
= (sky2
->rx_put
+ 1) % RX_LE_SIZE
;
742 /* Return high part of DMA address (could be 32 or 64 bit) */
743 static inline u32
high32(dma_addr_t a
)
745 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
748 /* Build description to hardware about buffer */
749 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
751 struct sky2_rx_le
*le
;
752 u32 hi
= high32(map
);
753 u16 len
= sky2
->rx_bufsize
;
755 if (sky2
->rx_addr64
!= hi
) {
756 le
= sky2_next_rx(sky2
);
757 le
->addr
= cpu_to_le32(hi
);
759 le
->opcode
= OP_ADDR64
| HW_OWNER
;
760 sky2
->rx_addr64
= high32(map
+ len
);
763 le
= sky2_next_rx(sky2
);
764 le
->addr
= cpu_to_le32((u32
) map
);
765 le
->length
= cpu_to_le16(len
);
767 le
->opcode
= OP_PACKET
| HW_OWNER
;
771 /* Tell chip where to start receive checksum.
772 * Actually has two checksums, but set both same to avoid possible byte
775 static void rx_set_checksum(struct sky2_port
*sky2
)
777 struct sky2_rx_le
*le
;
779 le
= sky2_next_rx(sky2
);
780 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
782 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
784 sky2_write32(sky2
->hw
,
785 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
786 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
791 * The RX Stop command will not work for Yukon-2 if the BMU does not
792 * reach the end of packet and since we can't make sure that we have
793 * incoming data, we must reset the BMU while it is not doing a DMA
794 * transfer. Since it is possible that the RX path is still active,
795 * the RX RAM buffer will be stopped first, so any possible incoming
796 * data will not trigger a DMA. After the RAM buffer is stopped, the
797 * BMU is polled until any DMA in progress is ended and only then it
800 static void sky2_rx_stop(struct sky2_port
*sky2
)
802 struct sky2_hw
*hw
= sky2
->hw
;
803 unsigned rxq
= rxqaddr
[sky2
->port
];
806 /* disable the RAM Buffer receive queue */
807 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
809 for (i
= 0; i
< 0xffff; i
++)
810 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
811 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
814 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
817 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
819 /* reset the Rx prefetch unit */
820 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
823 /* Clean out receive buffer area, assumes receiver hardware stopped */
824 static void sky2_rx_clean(struct sky2_port
*sky2
)
828 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
829 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
830 struct ring_info
*re
= sky2
->rx_ring
+ i
;
833 pci_unmap_single(sky2
->hw
->pdev
,
834 re
->mapaddr
, sky2
->rx_bufsize
,
842 /* Basic MII support */
843 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
845 struct mii_ioctl_data
*data
= if_mii(ifr
);
846 struct sky2_port
*sky2
= netdev_priv(dev
);
847 struct sky2_hw
*hw
= sky2
->hw
;
848 int err
= -EOPNOTSUPP
;
850 if (!netif_running(dev
))
851 return -ENODEV
; /* Phy still in reset */
855 data
->phy_id
= PHY_ADDR_MARV
;
861 spin_lock_bh(&sky2
->phy_lock
);
862 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
863 spin_unlock_bh(&sky2
->phy_lock
);
870 if (!capable(CAP_NET_ADMIN
))
873 spin_lock_bh(&sky2
->phy_lock
);
874 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
876 spin_unlock_bh(&sky2
->phy_lock
);
882 #ifdef SKY2_VLAN_TAG_USED
883 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
885 struct sky2_port
*sky2
= netdev_priv(dev
);
886 struct sky2_hw
*hw
= sky2
->hw
;
887 u16 port
= sky2
->port
;
889 spin_lock_bh(&sky2
->tx_lock
);
891 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
892 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
895 spin_unlock_bh(&sky2
->tx_lock
);
898 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
900 struct sky2_port
*sky2
= netdev_priv(dev
);
901 struct sky2_hw
*hw
= sky2
->hw
;
902 u16 port
= sky2
->port
;
904 spin_lock_bh(&sky2
->tx_lock
);
906 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
907 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
909 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
911 spin_unlock_bh(&sky2
->tx_lock
);
916 * It appears the hardware has a bug in the FIFO logic that
917 * cause it to hang if the FIFO gets overrun and the receive buffer
918 * is not aligned. ALso alloc_skb() won't align properly if slab
919 * debugging is enabled.
921 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
925 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
927 unsigned long p
= (unsigned long) skb
->data
;
928 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
935 * Allocate and setup receiver buffer pool.
936 * In case of 64 bit dma, there are 2X as many list elements
937 * available as ring entries
938 * and need to reserve one list element so we don't wrap around.
940 static int sky2_rx_start(struct sky2_port
*sky2
)
942 struct sky2_hw
*hw
= sky2
->hw
;
943 unsigned rxq
= rxqaddr
[sky2
->port
];
946 sky2
->rx_put
= sky2
->rx_next
= 0;
949 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
950 /* MAC Rx RAM Read is controlled by hardware */
951 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
954 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
956 rx_set_checksum(sky2
);
957 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
958 struct ring_info
*re
= sky2
->rx_ring
+ i
;
960 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
964 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
965 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
966 sky2_rx_add(sky2
, re
->mapaddr
);
969 /* Truncate oversize frames */
970 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), sky2
->rx_bufsize
- 8);
971 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
973 /* Tell chip about available buffers */
974 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
981 /* Bring up network interface. */
982 static int sky2_up(struct net_device
*dev
)
984 struct sky2_port
*sky2
= netdev_priv(dev
);
985 struct sky2_hw
*hw
= sky2
->hw
;
986 unsigned port
= sky2
->port
;
987 u32 ramsize
, rxspace
, imask
;
990 if (netif_msg_ifup(sky2
))
991 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
993 /* must be power of 2 */
994 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
996 sizeof(struct sky2_tx_le
),
1001 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1005 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1007 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1011 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1013 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1018 sky2_mac_init(hw
, port
);
1020 /* Determine available ram buffer space (in 4K blocks).
1021 * Note: not sure about the FE setting below yet
1023 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1026 ramsize
= sky2_read8(hw
, B2_E_0
);
1028 /* Give transmitter one third (rounded up) */
1029 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1031 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1032 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1034 /* Make sure SyncQ is disabled */
1035 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1038 sky2_qset(hw
, txqaddr
[port
]);
1040 /* Set almost empty threshold */
1041 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1042 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1044 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1047 err
= sky2_rx_start(sky2
);
1051 /* Enable interrupts from phy/mac for port */
1052 imask
= sky2_read32(hw
, B0_IMSK
);
1053 imask
|= (port
== 0) ? Y2_IS_PORT_1
: Y2_IS_PORT_2
;
1054 sky2_write32(hw
, B0_IMSK
, imask
);
1060 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1061 sky2
->rx_le
, sky2
->rx_le_map
);
1065 pci_free_consistent(hw
->pdev
,
1066 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1067 sky2
->tx_le
, sky2
->tx_le_map
);
1070 kfree(sky2
->tx_ring
);
1071 kfree(sky2
->rx_ring
);
1073 sky2
->tx_ring
= NULL
;
1074 sky2
->rx_ring
= NULL
;
1078 /* Modular subtraction in ring */
1079 static inline int tx_dist(unsigned tail
, unsigned head
)
1081 return (head
- tail
) % TX_RING_SIZE
;
1084 /* Number of list elements available for next tx */
1085 static inline int tx_avail(const struct sky2_port
*sky2
)
1087 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1090 /* Estimate of number of transmit list elements required */
1091 static unsigned tx_le_req(const struct sk_buff
*skb
)
1095 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1096 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1098 if (skb_shinfo(skb
)->tso_size
)
1101 if (skb
->ip_summed
== CHECKSUM_HW
)
1108 * Put one packet in ring for transmit.
1109 * A single packet can generate multiple list elements, and
1110 * the number of ring elements will probably be less than the number
1111 * of list elements used.
1113 * No BH disabling for tx_lock here (like tg3)
1115 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1117 struct sky2_port
*sky2
= netdev_priv(dev
);
1118 struct sky2_hw
*hw
= sky2
->hw
;
1119 struct sky2_tx_le
*le
= NULL
;
1120 struct tx_ring_info
*re
;
1128 /* No BH disabling for tx_lock here. We are running in BH disabled
1129 * context and TX reclaim runs via poll inside of a software
1130 * interrupt, and no related locks in IRQ processing.
1132 if (!spin_trylock(&sky2
->tx_lock
))
1133 return NETDEV_TX_LOCKED
;
1135 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1136 /* There is a known but harmless race with lockless tx
1137 * and netif_stop_queue.
1139 if (!netif_queue_stopped(dev
)) {
1140 netif_stop_queue(dev
);
1141 if (net_ratelimit())
1142 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1145 spin_unlock(&sky2
->tx_lock
);
1147 return NETDEV_TX_BUSY
;
1150 if (unlikely(netif_msg_tx_queued(sky2
)))
1151 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1152 dev
->name
, sky2
->tx_prod
, skb
->len
);
1154 len
= skb_headlen(skb
);
1155 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1156 addr64
= high32(mapping
);
1158 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1160 /* Send high bits if changed or crosses boundary */
1161 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1162 le
= get_tx_le(sky2
);
1163 le
->tx
.addr
= cpu_to_le32(addr64
);
1165 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1166 sky2
->tx_addr64
= high32(mapping
+ len
);
1169 /* Check for TCP Segmentation Offload */
1170 mss
= skb_shinfo(skb
)->tso_size
;
1172 /* just drop the packet if non-linear expansion fails */
1173 if (skb_header_cloned(skb
) &&
1174 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1179 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1180 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1184 if (mss
!= sky2
->tx_last_mss
) {
1185 le
= get_tx_le(sky2
);
1186 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1187 le
->tx
.tso
.rsvd
= 0;
1188 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1190 sky2
->tx_last_mss
= mss
;
1194 #ifdef SKY2_VLAN_TAG_USED
1195 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1196 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1198 le
= get_tx_le(sky2
);
1200 le
->opcode
= OP_VLAN
|HW_OWNER
;
1203 le
->opcode
|= OP_VLAN
;
1204 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1209 /* Handle TCP checksum offload */
1210 if (skb
->ip_summed
== CHECKSUM_HW
) {
1211 u16 hdr
= skb
->h
.raw
- skb
->data
;
1212 u16 offset
= hdr
+ skb
->csum
;
1214 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1215 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1218 le
= get_tx_le(sky2
);
1219 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1220 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1221 le
->length
= 0; /* initial checksum value */
1222 le
->ctrl
= 1; /* one packet */
1223 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1226 le
= get_tx_le(sky2
);
1227 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1228 le
->length
= cpu_to_le16(len
);
1230 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1232 /* Record the transmit mapping info */
1234 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1236 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1237 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1238 struct tx_ring_info
*fre
;
1240 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1241 frag
->size
, PCI_DMA_TODEVICE
);
1242 addr64
= high32(mapping
);
1243 if (addr64
!= sky2
->tx_addr64
) {
1244 le
= get_tx_le(sky2
);
1245 le
->tx
.addr
= cpu_to_le32(addr64
);
1247 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1248 sky2
->tx_addr64
= addr64
;
1251 le
= get_tx_le(sky2
);
1252 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1253 le
->length
= cpu_to_le16(frag
->size
);
1255 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1258 + ((re
- sky2
->tx_ring
) + i
+ 1) % TX_RING_SIZE
;
1259 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1262 re
->idx
= sky2
->tx_prod
;
1265 avail
= tx_avail(sky2
);
1266 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1267 le
->ctrl
|= FRC_STAT
;
1268 if (avail
<= MAX_SKB_TX_LE
)
1269 netif_stop_queue(dev
);
1272 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1275 spin_unlock(&sky2
->tx_lock
);
1277 dev
->trans_start
= jiffies
;
1278 return NETDEV_TX_OK
;
1282 * Free ring elements from starting at tx_cons until "done"
1284 * NB: the hardware will tell us about partial completion of multi-part
1285 * buffers; these are deferred until completion.
1287 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1289 struct net_device
*dev
= sky2
->netdev
;
1290 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1294 BUG_ON(done
>= TX_RING_SIZE
);
1296 if (unlikely(netif_msg_tx_done(sky2
)))
1297 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1300 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1301 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1302 struct sk_buff
*skb
= re
->skb
;
1305 BUG_ON(nxt
>= TX_RING_SIZE
);
1306 prefetch(sky2
->tx_ring
+ nxt
);
1308 /* Check for partial status */
1309 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1313 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1314 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1316 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1317 struct tx_ring_info
*fre
;
1318 fre
= sky2
->tx_ring
+ (put
+ i
+ 1) % TX_RING_SIZE
;
1319 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1320 skb_shinfo(skb
)->frags
[i
].size
,
1327 sky2
->tx_cons
= put
;
1328 if (tx_avail(sky2
) > MAX_SKB_TX_LE
)
1329 netif_wake_queue(dev
);
1332 /* Cleanup all untransmitted buffers, assume transmitter not running */
1333 static void sky2_tx_clean(struct sky2_port
*sky2
)
1335 spin_lock_bh(&sky2
->tx_lock
);
1336 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1337 spin_unlock_bh(&sky2
->tx_lock
);
1340 /* Network shutdown */
1341 static int sky2_down(struct net_device
*dev
)
1343 struct sky2_port
*sky2
= netdev_priv(dev
);
1344 struct sky2_hw
*hw
= sky2
->hw
;
1345 unsigned port
= sky2
->port
;
1349 /* Never really got started! */
1353 if (netif_msg_ifdown(sky2
))
1354 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1356 /* Stop more packets from being queued */
1357 netif_stop_queue(dev
);
1359 sky2_phy_reset(hw
, port
);
1361 /* Stop transmitter */
1362 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1363 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1365 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1366 RB_RST_SET
| RB_DIS_OP_MD
);
1368 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1369 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1370 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1372 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1374 /* Workaround shared GMAC reset */
1375 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1376 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1377 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1379 /* Disable Force Sync bit and Enable Alloc bit */
1380 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1381 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1383 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1384 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1385 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1387 /* Reset the PCI FIFO of the async Tx queue */
1388 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1389 BMU_RST_SET
| BMU_FIFO_RST
);
1391 /* Reset the Tx prefetch units */
1392 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1395 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1399 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1400 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1402 /* Disable port IRQ */
1403 imask
= sky2_read32(hw
, B0_IMSK
);
1404 imask
&= ~(sky2
->port
== 0) ? Y2_IS_PORT_1
: Y2_IS_PORT_2
;
1405 sky2_write32(hw
, B0_IMSK
, imask
);
1407 /* turn off LED's */
1408 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1410 synchronize_irq(hw
->pdev
->irq
);
1412 sky2_tx_clean(sky2
);
1413 sky2_rx_clean(sky2
);
1415 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1416 sky2
->rx_le
, sky2
->rx_le_map
);
1417 kfree(sky2
->rx_ring
);
1419 pci_free_consistent(hw
->pdev
,
1420 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1421 sky2
->tx_le
, sky2
->tx_le_map
);
1422 kfree(sky2
->tx_ring
);
1427 sky2
->rx_ring
= NULL
;
1428 sky2
->tx_ring
= NULL
;
1433 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1438 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1439 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1441 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1442 case PHY_M_PS_SPEED_1000
:
1444 case PHY_M_PS_SPEED_100
:
1451 static void sky2_link_up(struct sky2_port
*sky2
)
1453 struct sky2_hw
*hw
= sky2
->hw
;
1454 unsigned port
= sky2
->port
;
1457 /* Enable Transmit FIFO Underrun */
1458 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1460 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1461 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1462 reg
|= GM_GPCR_AU_ALL_DIS
;
1464 /* Is write/read necessary? Copied from sky2_mac_init */
1465 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1466 gma_read16(hw
, port
, GM_GP_CTRL
);
1468 switch (sky2
->speed
) {
1470 reg
&= ~GM_GPCR_SPEED_100
;
1471 reg
|= GM_GPCR_SPEED_1000
;
1474 reg
&= ~GM_GPCR_SPEED_1000
;
1475 reg
|= GM_GPCR_SPEED_100
;
1478 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1482 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1484 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1485 reg
|= GM_GPCR_DUP_FULL
;
1488 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1489 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1490 gma_read16(hw
, port
, GM_GP_CTRL
);
1492 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1494 netif_carrier_on(sky2
->netdev
);
1495 netif_wake_queue(sky2
->netdev
);
1497 /* Turn on link LED */
1498 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1499 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1501 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
1502 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1504 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1505 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1506 PHY_M_LEDC_INIT_CTRL(sky2
->speed
==
1508 PHY_M_LEDC_STA1_CTRL(sky2
->speed
==
1509 SPEED_100
? 7 : 0) |
1510 PHY_M_LEDC_STA0_CTRL(sky2
->speed
==
1511 SPEED_1000
? 7 : 0));
1512 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1515 if (netif_msg_link(sky2
))
1516 printk(KERN_INFO PFX
1517 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1518 sky2
->netdev
->name
, sky2
->speed
,
1519 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1520 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1521 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1524 static void sky2_link_down(struct sky2_port
*sky2
)
1526 struct sky2_hw
*hw
= sky2
->hw
;
1527 unsigned port
= sky2
->port
;
1530 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1532 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1533 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1534 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1535 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1537 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1538 /* restore Asymmetric Pause bit */
1539 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1540 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1544 netif_carrier_off(sky2
->netdev
);
1545 netif_stop_queue(sky2
->netdev
);
1547 /* Turn on link LED */
1548 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1550 if (netif_msg_link(sky2
))
1551 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1552 sky2_phy_init(hw
, port
);
1555 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1557 struct sky2_hw
*hw
= sky2
->hw
;
1558 unsigned port
= sky2
->port
;
1561 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1563 if (lpa
& PHY_M_AN_RF
) {
1564 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1568 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1569 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1570 printk(KERN_ERR PFX
"%s: master/slave fault",
1571 sky2
->netdev
->name
);
1575 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1576 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1577 sky2
->netdev
->name
);
1581 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1583 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1585 /* Pause bits are offset (9..8) */
1586 if (hw
->chip_id
== CHIP_ID_YUKON_XL
)
1589 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1590 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1592 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1593 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1594 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1596 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1601 /* Interrupt from PHY */
1602 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1604 struct net_device
*dev
= hw
->dev
[port
];
1605 struct sky2_port
*sky2
= netdev_priv(dev
);
1606 u16 istatus
, phystat
;
1608 spin_lock(&sky2
->phy_lock
);
1609 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1610 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1612 if (!netif_running(dev
))
1615 if (netif_msg_intr(sky2
))
1616 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1617 sky2
->netdev
->name
, istatus
, phystat
);
1619 if (istatus
& PHY_M_IS_AN_COMPL
) {
1620 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1625 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1626 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1628 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1630 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1632 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1633 if (phystat
& PHY_M_PS_LINK_UP
)
1636 sky2_link_down(sky2
);
1639 spin_unlock(&sky2
->phy_lock
);
1643 /* Transmit timeout is only called if we are running, carries is up
1644 * and tx queue is full (stopped).
1646 static void sky2_tx_timeout(struct net_device
*dev
)
1648 struct sky2_port
*sky2
= netdev_priv(dev
);
1649 struct sky2_hw
*hw
= sky2
->hw
;
1650 unsigned txq
= txqaddr
[sky2
->port
];
1653 if (netif_msg_timer(sky2
))
1654 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1656 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1657 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1659 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1661 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1663 if (report
!= done
) {
1664 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1666 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1667 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1668 } else if (report
!= sky2
->tx_cons
) {
1669 printk(KERN_INFO PFX
"status report lost?\n");
1671 spin_lock_bh(&sky2
->tx_lock
);
1672 sky2_tx_complete(sky2
, report
);
1673 spin_unlock_bh(&sky2
->tx_lock
);
1675 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1677 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1678 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1680 sky2_tx_clean(sky2
);
1683 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1688 /* Want receive buffer size to be multiple of 64 bits
1689 * and incl room for vlan and truncation
1691 static inline unsigned sky2_buf_size(int mtu
)
1693 return ALIGN(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1696 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1698 struct sky2_port
*sky2
= netdev_priv(dev
);
1699 struct sky2_hw
*hw
= sky2
->hw
;
1704 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1707 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1710 if (!netif_running(dev
)) {
1715 imask
= sky2_read32(hw
, B0_IMSK
);
1716 sky2_write32(hw
, B0_IMSK
, 0);
1718 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1719 netif_stop_queue(dev
);
1720 netif_poll_disable(hw
->dev
[0]);
1722 synchronize_irq(hw
->pdev
->irq
);
1724 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1725 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1727 sky2_rx_clean(sky2
);
1730 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1731 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1732 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1734 if (dev
->mtu
> ETH_DATA_LEN
)
1735 mode
|= GM_SMOD_JUMBO_ENA
;
1737 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1739 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1741 err
= sky2_rx_start(sky2
);
1742 sky2_write32(hw
, B0_IMSK
, imask
);
1747 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1749 netif_poll_enable(hw
->dev
[0]);
1750 netif_wake_queue(dev
);
1757 * Receive one packet.
1758 * For small packets or errors, just reuse existing skb.
1759 * For larger packets, get new buffer.
1761 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1762 u16 length
, u32 status
)
1764 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1765 struct sk_buff
*skb
= NULL
;
1767 if (unlikely(netif_msg_rx_status(sky2
)))
1768 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1769 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1771 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1772 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1774 if (status
& GMR_FS_ANY_ERR
)
1777 if (!(status
& GMR_FS_RX_OK
))
1780 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1783 if (length
< copybreak
) {
1784 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1788 skb_reserve(skb
, 2);
1789 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1790 length
, PCI_DMA_FROMDEVICE
);
1791 memcpy(skb
->data
, re
->skb
->data
, length
);
1792 skb
->ip_summed
= re
->skb
->ip_summed
;
1793 skb
->csum
= re
->skb
->csum
;
1794 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1795 length
, PCI_DMA_FROMDEVICE
);
1797 struct sk_buff
*nskb
;
1799 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1805 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1806 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1807 prefetch(skb
->data
);
1809 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1810 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1813 skb_put(skb
, length
);
1815 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1816 sky2_rx_add(sky2
, re
->mapaddr
);
1818 /* Tell receiver about new buffers. */
1819 sky2_put_idx(sky2
->hw
, rxqaddr
[sky2
->port
], sky2
->rx_put
);
1824 ++sky2
->net_stats
.rx_over_errors
;
1828 ++sky2
->net_stats
.rx_errors
;
1830 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1831 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1832 sky2
->netdev
->name
, status
, length
);
1834 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1835 sky2
->net_stats
.rx_length_errors
++;
1836 if (status
& GMR_FS_FRAGMENT
)
1837 sky2
->net_stats
.rx_frame_errors
++;
1838 if (status
& GMR_FS_CRC_ERR
)
1839 sky2
->net_stats
.rx_crc_errors
++;
1840 if (status
& GMR_FS_RX_FF_OV
)
1841 sky2
->net_stats
.rx_fifo_errors
++;
1846 /* Transmit complete */
1847 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1849 struct sky2_port
*sky2
= netdev_priv(dev
);
1851 if (netif_running(dev
)) {
1852 spin_lock(&sky2
->tx_lock
);
1853 sky2_tx_complete(sky2
, last
);
1854 spin_unlock(&sky2
->tx_lock
);
1858 /* Process status response ring */
1859 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1866 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1867 struct net_device
*dev
;
1868 struct sky2_port
*sky2
;
1869 struct sk_buff
*skb
;
1874 opcode
= le
->opcode
;
1877 opcode
&= ~HW_OWNER
;
1879 hw
->st_idx
= (hw
->st_idx
+ 1) % STATUS_RING_SIZE
;
1884 dev
= hw
->dev
[link
];
1886 sky2
= netdev_priv(dev
);
1887 length
= le
->length
;
1888 status
= le
->status
;
1892 skb
= sky2_receive(sky2
, length
, status
);
1897 skb
->protocol
= eth_type_trans(skb
, dev
);
1898 dev
->last_rx
= jiffies
;
1900 #ifdef SKY2_VLAN_TAG_USED
1901 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1902 vlan_hwaccel_receive_skb(skb
,
1904 be16_to_cpu(sky2
->rx_tag
));
1907 netif_receive_skb(skb
);
1909 if (++work_done
>= to_do
)
1913 #ifdef SKY2_VLAN_TAG_USED
1915 sky2
->rx_tag
= length
;
1919 sky2
->rx_tag
= length
;
1923 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1924 skb
->ip_summed
= CHECKSUM_HW
;
1925 skb
->csum
= le16_to_cpu(status
);
1929 /* TX index reports status for both ports */
1930 sky2_tx_done(hw
->dev
[0], status
& 0xffff);
1932 sky2_tx_done(hw
->dev
[1],
1933 ((status
>> 24) & 0xff)
1934 | (u16
)(length
& 0xf) << 8);
1938 if (net_ratelimit())
1939 printk(KERN_WARNING PFX
1940 "unknown status opcode 0x%x\n", opcode
);
1949 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
1951 struct net_device
*dev
= hw
->dev
[port
];
1953 if (net_ratelimit())
1954 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
1957 if (status
& Y2_IS_PAR_RD1
) {
1958 if (net_ratelimit())
1959 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
1962 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
1965 if (status
& Y2_IS_PAR_WR1
) {
1966 if (net_ratelimit())
1967 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
1970 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
1973 if (status
& Y2_IS_PAR_MAC1
) {
1974 if (net_ratelimit())
1975 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
1976 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
1979 if (status
& Y2_IS_PAR_RX1
) {
1980 if (net_ratelimit())
1981 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
1982 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
1985 if (status
& Y2_IS_TCP_TXA1
) {
1986 if (net_ratelimit())
1987 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
1989 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
1993 static void sky2_hw_intr(struct sky2_hw
*hw
)
1995 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
1997 if (status
& Y2_IS_TIST_OV
)
1998 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2000 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2003 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2004 if (net_ratelimit())
2005 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2006 pci_name(hw
->pdev
), pci_err
);
2008 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2009 sky2_pci_write16(hw
, PCI_STATUS
,
2010 pci_err
| PCI_STATUS_ERROR_BITS
);
2011 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2014 if (status
& Y2_IS_PCI_EXP
) {
2015 /* PCI-Express uncorrectable Error occurred */
2018 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2020 if (net_ratelimit())
2021 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2022 pci_name(hw
->pdev
), pex_err
);
2024 /* clear the interrupt */
2025 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2026 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2028 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2030 if (pex_err
& PEX_FATAL_ERRORS
) {
2031 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2032 hwmsk
&= ~Y2_IS_PCI_EXP
;
2033 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2037 if (status
& Y2_HWE_L1_MASK
)
2038 sky2_hw_error(hw
, 0, status
);
2040 if (status
& Y2_HWE_L1_MASK
)
2041 sky2_hw_error(hw
, 1, status
);
2044 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2046 struct net_device
*dev
= hw
->dev
[port
];
2047 struct sky2_port
*sky2
= netdev_priv(dev
);
2048 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2050 if (netif_msg_intr(sky2
))
2051 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2054 if (status
& GM_IS_RX_FF_OR
) {
2055 ++sky2
->net_stats
.rx_fifo_errors
;
2056 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2059 if (status
& GM_IS_TX_FF_UR
) {
2060 ++sky2
->net_stats
.tx_fifo_errors
;
2061 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2065 /* This should never happen it is a fatal situation */
2066 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2067 const char *rxtx
, u32 mask
)
2069 struct net_device
*dev
= hw
->dev
[port
];
2070 struct sky2_port
*sky2
= netdev_priv(dev
);
2073 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2074 dev
? dev
->name
: "<not registered>", rxtx
);
2076 imask
= sky2_read32(hw
, B0_IMSK
);
2078 sky2_write32(hw
, B0_IMSK
, imask
);
2081 spin_lock(&sky2
->phy_lock
);
2082 sky2_link_down(sky2
);
2083 spin_unlock(&sky2
->phy_lock
);
2087 /* If idle then force a fake soft NAPI poll once a second
2088 * to work around cases where sharing an edge triggered interrupt.
2090 static void sky2_idle(unsigned long arg
)
2092 struct net_device
*dev
= (struct net_device
*) arg
;
2094 local_irq_disable();
2095 if (__netif_rx_schedule_prep(dev
))
2096 __netif_rx_schedule(dev
);
2101 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2103 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2104 int work_limit
= min(dev0
->quota
, *budget
);
2106 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2108 if (status
& Y2_IS_HW_ERR
)
2111 if (status
& Y2_IS_IRQ_PHY1
)
2112 sky2_phy_intr(hw
, 0);
2114 if (status
& Y2_IS_IRQ_PHY2
)
2115 sky2_phy_intr(hw
, 1);
2117 if (status
& Y2_IS_IRQ_MAC1
)
2118 sky2_mac_intr(hw
, 0);
2120 if (status
& Y2_IS_IRQ_MAC2
)
2121 sky2_mac_intr(hw
, 1);
2123 if (status
& Y2_IS_CHK_RX1
)
2124 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2126 if (status
& Y2_IS_CHK_RX2
)
2127 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2129 if (status
& Y2_IS_CHK_TXA1
)
2130 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2132 if (status
& Y2_IS_CHK_TXA2
)
2133 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2135 if (status
& Y2_IS_STAT_BMU
)
2136 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2138 work_done
= sky2_status_intr(hw
, work_limit
);
2139 *budget
-= work_done
;
2140 dev0
->quota
-= work_done
;
2142 if (work_done
>= work_limit
)
2145 mod_timer(&hw
->idle_timer
, jiffies
+ HZ
);
2147 netif_rx_complete(dev0
);
2149 status
= sky2_read32(hw
, B0_Y2_SP_LISR
);
2153 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2155 struct sky2_hw
*hw
= dev_id
;
2156 struct net_device
*dev0
= hw
->dev
[0];
2159 /* Reading this mask interrupts as side effect */
2160 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2161 if (status
== 0 || status
== ~0)
2164 prefetch(&hw
->st_le
[hw
->st_idx
]);
2165 if (likely(__netif_rx_schedule_prep(dev0
)))
2166 __netif_rx_schedule(dev0
);
2168 printk(KERN_DEBUG PFX
"irq race detected\n");
2173 #ifdef CONFIG_NET_POLL_CONTROLLER
2174 static void sky2_netpoll(struct net_device
*dev
)
2176 struct sky2_port
*sky2
= netdev_priv(dev
);
2178 sky2_intr(sky2
->hw
->pdev
->irq
, sky2
->hw
, NULL
);
2182 /* Chip internal frequency for clock calculations */
2183 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2185 switch (hw
->chip_id
) {
2186 case CHIP_ID_YUKON_EC
:
2187 case CHIP_ID_YUKON_EC_U
:
2188 return 125; /* 125 Mhz */
2189 case CHIP_ID_YUKON_FE
:
2190 return 100; /* 100 Mhz */
2191 default: /* YUKON_XL */
2192 return 156; /* 156 Mhz */
2196 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2198 return sky2_mhz(hw
) * us
;
2201 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2203 return clk
/ sky2_mhz(hw
);
2207 static int __devinit
sky2_reset(struct sky2_hw
*hw
)
2213 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2215 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2216 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2217 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2218 pci_name(hw
->pdev
), hw
->chip_id
);
2222 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2224 /* This rev is really old, and requires untested workarounds */
2225 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2226 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2227 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2228 hw
->chip_id
, hw
->chip_rev
);
2232 /* This chip is new and not tested yet */
2233 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
2234 pr_info(PFX
"%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2235 pci_name(hw
->pdev
));
2236 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2240 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2241 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2242 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2246 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2247 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2249 /* clear PCI errors, if any */
2250 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2252 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2253 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2256 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2258 /* clear any PEX errors */
2259 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2260 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2263 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2264 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2267 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2268 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2269 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2273 sky2_set_power_state(hw
, PCI_D0
);
2275 for (i
= 0; i
< hw
->ports
; i
++) {
2276 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2277 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2280 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2282 /* Clear I2C IRQ noise */
2283 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2285 /* turn off hardware timer (unused) */
2286 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2287 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2289 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2291 /* Turn off descriptor polling */
2292 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2294 /* Turn off receive timestamp */
2295 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2296 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2298 /* enable the Tx Arbiters */
2299 for (i
= 0; i
< hw
->ports
; i
++)
2300 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2302 /* Initialize ram interface */
2303 for (i
= 0; i
< hw
->ports
; i
++) {
2304 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2306 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2307 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2308 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2309 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2310 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2311 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2312 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2313 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2314 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2315 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2316 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2317 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2320 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2322 for (i
= 0; i
< hw
->ports
; i
++)
2323 sky2_phy_reset(hw
, i
);
2325 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2328 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2329 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2331 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2332 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2334 /* Set the list last index */
2335 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2337 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2338 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2340 /* set Status-FIFO ISR watermark */
2341 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2342 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2344 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2346 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2347 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2348 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2350 /* enable status unit */
2351 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2353 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2354 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2355 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2360 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2364 modes
= SUPPORTED_10baseT_Half
2365 | SUPPORTED_10baseT_Full
2366 | SUPPORTED_100baseT_Half
2367 | SUPPORTED_100baseT_Full
2368 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2370 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2371 modes
|= SUPPORTED_1000baseT_Half
2372 | SUPPORTED_1000baseT_Full
;
2374 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2375 | SUPPORTED_Autoneg
;
2379 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2381 struct sky2_port
*sky2
= netdev_priv(dev
);
2382 struct sky2_hw
*hw
= sky2
->hw
;
2384 ecmd
->transceiver
= XCVR_INTERNAL
;
2385 ecmd
->supported
= sky2_supported_modes(hw
);
2386 ecmd
->phy_address
= PHY_ADDR_MARV
;
2388 ecmd
->supported
= SUPPORTED_10baseT_Half
2389 | SUPPORTED_10baseT_Full
2390 | SUPPORTED_100baseT_Half
2391 | SUPPORTED_100baseT_Full
2392 | SUPPORTED_1000baseT_Half
2393 | SUPPORTED_1000baseT_Full
2394 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2395 ecmd
->port
= PORT_TP
;
2397 ecmd
->port
= PORT_FIBRE
;
2399 ecmd
->advertising
= sky2
->advertising
;
2400 ecmd
->autoneg
= sky2
->autoneg
;
2401 ecmd
->speed
= sky2
->speed
;
2402 ecmd
->duplex
= sky2
->duplex
;
2406 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2408 struct sky2_port
*sky2
= netdev_priv(dev
);
2409 const struct sky2_hw
*hw
= sky2
->hw
;
2410 u32 supported
= sky2_supported_modes(hw
);
2412 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2413 ecmd
->advertising
= supported
;
2419 switch (ecmd
->speed
) {
2421 if (ecmd
->duplex
== DUPLEX_FULL
)
2422 setting
= SUPPORTED_1000baseT_Full
;
2423 else if (ecmd
->duplex
== DUPLEX_HALF
)
2424 setting
= SUPPORTED_1000baseT_Half
;
2429 if (ecmd
->duplex
== DUPLEX_FULL
)
2430 setting
= SUPPORTED_100baseT_Full
;
2431 else if (ecmd
->duplex
== DUPLEX_HALF
)
2432 setting
= SUPPORTED_100baseT_Half
;
2438 if (ecmd
->duplex
== DUPLEX_FULL
)
2439 setting
= SUPPORTED_10baseT_Full
;
2440 else if (ecmd
->duplex
== DUPLEX_HALF
)
2441 setting
= SUPPORTED_10baseT_Half
;
2449 if ((setting
& supported
) == 0)
2452 sky2
->speed
= ecmd
->speed
;
2453 sky2
->duplex
= ecmd
->duplex
;
2456 sky2
->autoneg
= ecmd
->autoneg
;
2457 sky2
->advertising
= ecmd
->advertising
;
2459 if (netif_running(dev
))
2460 sky2_phy_reinit(sky2
);
2465 static void sky2_get_drvinfo(struct net_device
*dev
,
2466 struct ethtool_drvinfo
*info
)
2468 struct sky2_port
*sky2
= netdev_priv(dev
);
2470 strcpy(info
->driver
, DRV_NAME
);
2471 strcpy(info
->version
, DRV_VERSION
);
2472 strcpy(info
->fw_version
, "N/A");
2473 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2476 static const struct sky2_stat
{
2477 char name
[ETH_GSTRING_LEN
];
2480 { "tx_bytes", GM_TXO_OK_HI
},
2481 { "rx_bytes", GM_RXO_OK_HI
},
2482 { "tx_broadcast", GM_TXF_BC_OK
},
2483 { "rx_broadcast", GM_RXF_BC_OK
},
2484 { "tx_multicast", GM_TXF_MC_OK
},
2485 { "rx_multicast", GM_RXF_MC_OK
},
2486 { "tx_unicast", GM_TXF_UC_OK
},
2487 { "rx_unicast", GM_RXF_UC_OK
},
2488 { "tx_mac_pause", GM_TXF_MPAUSE
},
2489 { "rx_mac_pause", GM_RXF_MPAUSE
},
2490 { "collisions", GM_TXF_COL
},
2491 { "late_collision",GM_TXF_LAT_COL
},
2492 { "aborted", GM_TXF_ABO_COL
},
2493 { "single_collisions", GM_TXF_SNG_COL
},
2494 { "multi_collisions", GM_TXF_MUL_COL
},
2496 { "rx_short", GM_RXF_SHT
},
2497 { "rx_runt", GM_RXE_FRAG
},
2498 { "rx_64_byte_packets", GM_RXF_64B
},
2499 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2500 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2501 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2502 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2503 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2504 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2505 { "rx_too_long", GM_RXF_LNG_ERR
},
2506 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2507 { "rx_jabber", GM_RXF_JAB_PKT
},
2508 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2510 { "tx_64_byte_packets", GM_TXF_64B
},
2511 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2512 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2513 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2514 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2515 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2516 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2517 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2520 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2522 struct sky2_port
*sky2
= netdev_priv(dev
);
2524 return sky2
->rx_csum
;
2527 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2529 struct sky2_port
*sky2
= netdev_priv(dev
);
2531 sky2
->rx_csum
= data
;
2533 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2534 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2539 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2541 struct sky2_port
*sky2
= netdev_priv(netdev
);
2542 return sky2
->msg_enable
;
2545 static int sky2_nway_reset(struct net_device
*dev
)
2547 struct sky2_port
*sky2
= netdev_priv(dev
);
2549 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2552 sky2_phy_reinit(sky2
);
2557 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2559 struct sky2_hw
*hw
= sky2
->hw
;
2560 unsigned port
= sky2
->port
;
2563 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2564 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2565 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2566 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2568 for (i
= 2; i
< count
; i
++)
2569 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2572 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2574 struct sky2_port
*sky2
= netdev_priv(netdev
);
2575 sky2
->msg_enable
= value
;
2578 static int sky2_get_stats_count(struct net_device
*dev
)
2580 return ARRAY_SIZE(sky2_stats
);
2583 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2584 struct ethtool_stats
*stats
, u64
* data
)
2586 struct sky2_port
*sky2
= netdev_priv(dev
);
2588 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2591 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2595 switch (stringset
) {
2597 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2598 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2599 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2604 /* Use hardware MIB variables for critical path statistics and
2605 * transmit feedback not reported at interrupt.
2606 * Other errors are accounted for in interrupt handler.
2608 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2610 struct sky2_port
*sky2
= netdev_priv(dev
);
2613 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2615 sky2
->net_stats
.tx_bytes
= data
[0];
2616 sky2
->net_stats
.rx_bytes
= data
[1];
2617 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2618 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2619 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2620 sky2
->net_stats
.collisions
= data
[10];
2621 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2623 return &sky2
->net_stats
;
2626 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2628 struct sky2_port
*sky2
= netdev_priv(dev
);
2629 struct sky2_hw
*hw
= sky2
->hw
;
2630 unsigned port
= sky2
->port
;
2631 const struct sockaddr
*addr
= p
;
2633 if (!is_valid_ether_addr(addr
->sa_data
))
2634 return -EADDRNOTAVAIL
;
2636 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2637 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2638 dev
->dev_addr
, ETH_ALEN
);
2639 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2640 dev
->dev_addr
, ETH_ALEN
);
2642 /* virtual address for data */
2643 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2645 /* physical address: used for pause frames */
2646 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2651 static void sky2_set_multicast(struct net_device
*dev
)
2653 struct sky2_port
*sky2
= netdev_priv(dev
);
2654 struct sky2_hw
*hw
= sky2
->hw
;
2655 unsigned port
= sky2
->port
;
2656 struct dev_mc_list
*list
= dev
->mc_list
;
2660 memset(filter
, 0, sizeof(filter
));
2662 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2663 reg
|= GM_RXCR_UCF_ENA
;
2665 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2666 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2667 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2668 memset(filter
, 0xff, sizeof(filter
));
2669 else if (dev
->mc_count
== 0) /* no multicast */
2670 reg
&= ~GM_RXCR_MCF_ENA
;
2673 reg
|= GM_RXCR_MCF_ENA
;
2675 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2676 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2677 filter
[bit
/ 8] |= 1 << (bit
% 8);
2681 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2682 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2683 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2684 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2685 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2686 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2687 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2688 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2690 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2693 /* Can have one global because blinking is controlled by
2694 * ethtool and that is always under RTNL mutex
2696 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2700 switch (hw
->chip_id
) {
2701 case CHIP_ID_YUKON_XL
:
2702 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2703 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2704 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2705 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2706 PHY_M_LEDC_INIT_CTRL(7) |
2707 PHY_M_LEDC_STA1_CTRL(7) |
2708 PHY_M_LEDC_STA0_CTRL(7))
2711 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2715 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2716 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2717 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2718 PHY_M_LED_MO_10(MO_LED_ON
) |
2719 PHY_M_LED_MO_100(MO_LED_ON
) |
2720 PHY_M_LED_MO_1000(MO_LED_ON
) |
2721 PHY_M_LED_MO_RX(MO_LED_ON
)
2722 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2723 PHY_M_LED_MO_10(MO_LED_OFF
) |
2724 PHY_M_LED_MO_100(MO_LED_OFF
) |
2725 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2726 PHY_M_LED_MO_RX(MO_LED_OFF
));
2731 /* blink LED's for finding board */
2732 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2734 struct sky2_port
*sky2
= netdev_priv(dev
);
2735 struct sky2_hw
*hw
= sky2
->hw
;
2736 unsigned port
= sky2
->port
;
2737 u16 ledctrl
, ledover
= 0;
2742 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2743 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2747 /* save initial values */
2748 spin_lock_bh(&sky2
->phy_lock
);
2749 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2750 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2751 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2752 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2753 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2755 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2756 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2760 while (!interrupted
&& ms
> 0) {
2761 sky2_led(hw
, port
, onoff
);
2764 spin_unlock_bh(&sky2
->phy_lock
);
2765 interrupted
= msleep_interruptible(250);
2766 spin_lock_bh(&sky2
->phy_lock
);
2771 /* resume regularly scheduled programming */
2772 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2773 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2774 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2775 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2776 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2778 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2779 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2781 spin_unlock_bh(&sky2
->phy_lock
);
2786 static void sky2_get_pauseparam(struct net_device
*dev
,
2787 struct ethtool_pauseparam
*ecmd
)
2789 struct sky2_port
*sky2
= netdev_priv(dev
);
2791 ecmd
->tx_pause
= sky2
->tx_pause
;
2792 ecmd
->rx_pause
= sky2
->rx_pause
;
2793 ecmd
->autoneg
= sky2
->autoneg
;
2796 static int sky2_set_pauseparam(struct net_device
*dev
,
2797 struct ethtool_pauseparam
*ecmd
)
2799 struct sky2_port
*sky2
= netdev_priv(dev
);
2802 sky2
->autoneg
= ecmd
->autoneg
;
2803 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2804 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2806 sky2_phy_reinit(sky2
);
2811 static int sky2_get_coalesce(struct net_device
*dev
,
2812 struct ethtool_coalesce
*ecmd
)
2814 struct sky2_port
*sky2
= netdev_priv(dev
);
2815 struct sky2_hw
*hw
= sky2
->hw
;
2817 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2818 ecmd
->tx_coalesce_usecs
= 0;
2820 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2821 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2823 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2825 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2826 ecmd
->rx_coalesce_usecs
= 0;
2828 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2829 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2831 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2833 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2834 ecmd
->rx_coalesce_usecs_irq
= 0;
2836 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2837 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2840 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2845 /* Note: this affect both ports */
2846 static int sky2_set_coalesce(struct net_device
*dev
,
2847 struct ethtool_coalesce
*ecmd
)
2849 struct sky2_port
*sky2
= netdev_priv(dev
);
2850 struct sky2_hw
*hw
= sky2
->hw
;
2851 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2853 if (ecmd
->tx_coalesce_usecs
> tmax
||
2854 ecmd
->rx_coalesce_usecs
> tmax
||
2855 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2858 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2860 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2862 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2865 if (ecmd
->tx_coalesce_usecs
== 0)
2866 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2868 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2869 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2870 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2872 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2874 if (ecmd
->rx_coalesce_usecs
== 0)
2875 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2877 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2878 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2879 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2881 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2883 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2884 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2886 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2887 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2888 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2890 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2894 static void sky2_get_ringparam(struct net_device
*dev
,
2895 struct ethtool_ringparam
*ering
)
2897 struct sky2_port
*sky2
= netdev_priv(dev
);
2899 ering
->rx_max_pending
= RX_MAX_PENDING
;
2900 ering
->rx_mini_max_pending
= 0;
2901 ering
->rx_jumbo_max_pending
= 0;
2902 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2904 ering
->rx_pending
= sky2
->rx_pending
;
2905 ering
->rx_mini_pending
= 0;
2906 ering
->rx_jumbo_pending
= 0;
2907 ering
->tx_pending
= sky2
->tx_pending
;
2910 static int sky2_set_ringparam(struct net_device
*dev
,
2911 struct ethtool_ringparam
*ering
)
2913 struct sky2_port
*sky2
= netdev_priv(dev
);
2916 if (ering
->rx_pending
> RX_MAX_PENDING
||
2917 ering
->rx_pending
< 8 ||
2918 ering
->tx_pending
< MAX_SKB_TX_LE
||
2919 ering
->tx_pending
> TX_RING_SIZE
- 1)
2922 if (netif_running(dev
))
2925 sky2
->rx_pending
= ering
->rx_pending
;
2926 sky2
->tx_pending
= ering
->tx_pending
;
2928 if (netif_running(dev
)) {
2933 sky2_set_multicast(dev
);
2939 static int sky2_get_regs_len(struct net_device
*dev
)
2945 * Returns copy of control register region
2946 * Note: access to the RAM address register set will cause timeouts.
2948 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2951 const struct sky2_port
*sky2
= netdev_priv(dev
);
2952 const void __iomem
*io
= sky2
->hw
->regs
;
2954 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
2956 memset(p
, 0, regs
->len
);
2958 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
2960 memcpy_fromio(p
+ B3_RI_WTO_R1
,
2962 regs
->len
- B3_RI_WTO_R1
);
2965 static struct ethtool_ops sky2_ethtool_ops
= {
2966 .get_settings
= sky2_get_settings
,
2967 .set_settings
= sky2_set_settings
,
2968 .get_drvinfo
= sky2_get_drvinfo
,
2969 .get_msglevel
= sky2_get_msglevel
,
2970 .set_msglevel
= sky2_set_msglevel
,
2971 .nway_reset
= sky2_nway_reset
,
2972 .get_regs_len
= sky2_get_regs_len
,
2973 .get_regs
= sky2_get_regs
,
2974 .get_link
= ethtool_op_get_link
,
2975 .get_sg
= ethtool_op_get_sg
,
2976 .set_sg
= ethtool_op_set_sg
,
2977 .get_tx_csum
= ethtool_op_get_tx_csum
,
2978 .set_tx_csum
= ethtool_op_set_tx_csum
,
2979 .get_tso
= ethtool_op_get_tso
,
2980 .set_tso
= ethtool_op_set_tso
,
2981 .get_rx_csum
= sky2_get_rx_csum
,
2982 .set_rx_csum
= sky2_set_rx_csum
,
2983 .get_strings
= sky2_get_strings
,
2984 .get_coalesce
= sky2_get_coalesce
,
2985 .set_coalesce
= sky2_set_coalesce
,
2986 .get_ringparam
= sky2_get_ringparam
,
2987 .set_ringparam
= sky2_set_ringparam
,
2988 .get_pauseparam
= sky2_get_pauseparam
,
2989 .set_pauseparam
= sky2_set_pauseparam
,
2990 .phys_id
= sky2_phys_id
,
2991 .get_stats_count
= sky2_get_stats_count
,
2992 .get_ethtool_stats
= sky2_get_ethtool_stats
,
2993 .get_perm_addr
= ethtool_op_get_perm_addr
,
2996 /* Initialize network device */
2997 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
2998 unsigned port
, int highmem
)
3000 struct sky2_port
*sky2
;
3001 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3004 printk(KERN_ERR
"sky2 etherdev alloc failed");
3008 SET_MODULE_OWNER(dev
);
3009 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3010 dev
->irq
= hw
->pdev
->irq
;
3011 dev
->open
= sky2_up
;
3012 dev
->stop
= sky2_down
;
3013 dev
->do_ioctl
= sky2_ioctl
;
3014 dev
->hard_start_xmit
= sky2_xmit_frame
;
3015 dev
->get_stats
= sky2_get_stats
;
3016 dev
->set_multicast_list
= sky2_set_multicast
;
3017 dev
->set_mac_address
= sky2_set_mac_address
;
3018 dev
->change_mtu
= sky2_change_mtu
;
3019 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3020 dev
->tx_timeout
= sky2_tx_timeout
;
3021 dev
->watchdog_timeo
= TX_WATCHDOG
;
3023 dev
->poll
= sky2_poll
;
3024 dev
->weight
= NAPI_WEIGHT
;
3025 #ifdef CONFIG_NET_POLL_CONTROLLER
3026 dev
->poll_controller
= sky2_netpoll
;
3029 sky2
= netdev_priv(dev
);
3032 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3034 spin_lock_init(&sky2
->tx_lock
);
3035 /* Auto speed and flow control */
3036 sky2
->autoneg
= AUTONEG_ENABLE
;
3041 sky2
->advertising
= sky2_supported_modes(hw
);
3043 /* Receive checksum disabled for Yukon XL
3044 * because of observed problems with incorrect
3045 * values when multiple packets are received in one interrupt
3047 sky2
->rx_csum
= (hw
->chip_id
!= CHIP_ID_YUKON_XL
);
3049 spin_lock_init(&sky2
->phy_lock
);
3050 sky2
->tx_pending
= TX_DEF_PENDING
;
3051 sky2
->rx_pending
= RX_DEF_PENDING
;
3052 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3054 hw
->dev
[port
] = dev
;
3058 dev
->features
|= NETIF_F_LLTX
;
3059 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3060 dev
->features
|= NETIF_F_TSO
;
3062 dev
->features
|= NETIF_F_HIGHDMA
;
3063 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3065 #ifdef SKY2_VLAN_TAG_USED
3066 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3067 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3068 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3071 /* read the mac address */
3072 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3073 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3075 /* device is off until link detection */
3076 netif_carrier_off(dev
);
3077 netif_stop_queue(dev
);
3082 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3084 const struct sky2_port
*sky2
= netdev_priv(dev
);
3086 if (netif_msg_probe(sky2
))
3087 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3089 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3090 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3093 /* Handle software interrupt used during MSI test */
3094 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3095 struct pt_regs
*regs
)
3097 struct sky2_hw
*hw
= dev_id
;
3098 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3103 if (status
& Y2_IS_IRQ_SW
) {
3104 hw
->msi_detected
= 1;
3105 wake_up(&hw
->msi_wait
);
3106 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3108 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3113 /* Test interrupt path by forcing a a software IRQ */
3114 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3116 struct pci_dev
*pdev
= hw
->pdev
;
3119 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3121 err
= request_irq(pdev
->irq
, sky2_test_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3123 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3124 pci_name(pdev
), pdev
->irq
);
3128 init_waitqueue_head (&hw
->msi_wait
);
3130 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3133 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3135 if (!hw
->msi_detected
) {
3136 /* MSI test failed, go back to INTx mode */
3137 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3138 "switching to INTx mode. Please report this failure to "
3139 "the PCI maintainer and include system chipset information.\n",
3143 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3146 sky2_write32(hw
, B0_IMSK
, 0);
3148 free_irq(pdev
->irq
, hw
);
3153 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3154 const struct pci_device_id
*ent
)
3156 struct net_device
*dev
, *dev1
= NULL
;
3158 int err
, pm_cap
, using_dac
= 0;
3160 err
= pci_enable_device(pdev
);
3162 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3167 err
= pci_request_regions(pdev
, DRV_NAME
);
3169 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3174 pci_set_master(pdev
);
3176 /* Find power-management capability. */
3177 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3179 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3182 goto err_out_free_regions
;
3185 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3186 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3188 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3190 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3191 "for consistent allocations\n", pci_name(pdev
));
3192 goto err_out_free_regions
;
3196 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3198 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3200 goto err_out_free_regions
;
3205 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3207 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3209 goto err_out_free_regions
;
3214 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3216 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3218 goto err_out_free_hw
;
3220 hw
->pm_cap
= pm_cap
;
3223 /* byte swap descriptors in hardware */
3227 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3228 reg
|= PCI_REV_DESC
;
3229 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3233 /* ring for status responses */
3234 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3237 goto err_out_iounmap
;
3239 err
= sky2_reset(hw
);
3241 goto err_out_iounmap
;
3243 printk(KERN_INFO PFX
"v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3244 DRV_VERSION
, pci_resource_start(pdev
, 0), pdev
->irq
,
3245 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3246 hw
->chip_id
, hw
->chip_rev
);
3248 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3250 goto err_out_free_pci
;
3252 err
= register_netdev(dev
);
3254 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3256 goto err_out_free_netdev
;
3259 sky2_show_addr(dev
);
3261 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3262 if (register_netdev(dev1
) == 0)
3263 sky2_show_addr(dev1
);
3265 /* Failure to register second port need not be fatal */
3266 printk(KERN_WARNING PFX
3267 "register of second port failed\n");
3273 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3274 err
= sky2_test_msi(hw
);
3275 if (err
== -EOPNOTSUPP
)
3276 pci_disable_msi(pdev
);
3278 goto err_out_unregister
;
3281 err
= request_irq(pdev
->irq
, sky2_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3283 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3284 pci_name(pdev
), pdev
->irq
);
3285 goto err_out_unregister
;
3288 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3290 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) dev
);
3292 pci_set_drvdata(pdev
, hw
);
3297 pci_disable_msi(pdev
);
3299 unregister_netdev(dev1
);
3302 unregister_netdev(dev
);
3303 err_out_free_netdev
:
3306 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3307 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3312 err_out_free_regions
:
3313 pci_release_regions(pdev
);
3314 pci_disable_device(pdev
);
3319 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3321 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3322 struct net_device
*dev0
, *dev1
;
3327 del_timer_sync(&hw
->idle_timer
);
3329 sky2_write32(hw
, B0_IMSK
, 0);
3333 unregister_netdev(dev1
);
3334 unregister_netdev(dev0
);
3336 sky2_set_power_state(hw
, PCI_D3hot
);
3337 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3338 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3339 sky2_read8(hw
, B0_CTST
);
3341 free_irq(pdev
->irq
, hw
);
3342 pci_disable_msi(pdev
);
3343 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3344 pci_release_regions(pdev
);
3345 pci_disable_device(pdev
);
3353 pci_set_drvdata(pdev
, NULL
);
3357 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3359 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3362 for (i
= 0; i
< 2; i
++) {
3363 struct net_device
*dev
= hw
->dev
[i
];
3366 if (!netif_running(dev
))
3370 netif_device_detach(dev
);
3374 return sky2_set_power_state(hw
, pci_choose_state(pdev
, state
));
3377 static int sky2_resume(struct pci_dev
*pdev
)
3379 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3382 pci_restore_state(pdev
);
3383 pci_enable_wake(pdev
, PCI_D0
, 0);
3384 err
= sky2_set_power_state(hw
, PCI_D0
);
3388 err
= sky2_reset(hw
);
3392 for (i
= 0; i
< 2; i
++) {
3393 struct net_device
*dev
= hw
->dev
[i
];
3394 if (dev
&& netif_running(dev
)) {
3395 netif_device_attach(dev
);
3398 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3410 static struct pci_driver sky2_driver
= {
3412 .id_table
= sky2_id_table
,
3413 .probe
= sky2_probe
,
3414 .remove
= __devexit_p(sky2_remove
),
3416 .suspend
= sky2_suspend
,
3417 .resume
= sky2_resume
,
3421 static int __init
sky2_init_module(void)
3423 return pci_register_driver(&sky2_driver
);
3426 static void __exit
sky2_cleanup_module(void)
3428 pci_unregister_driver(&sky2_driver
);
3431 module_init(sky2_init_module
);
3432 module_exit(sky2_cleanup_module
);
3434 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3435 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3436 MODULE_LICENSE("GPL");
3437 MODULE_VERSION(DRV_VERSION
);