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Merge branch 'for-2.6.25' of git://git.secretlab.ca/git/linux-2.6-mpc52xx into for...
[deliverable/linux.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.21"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { 0 }
140 };
141
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
148
149 /* This driver supports yukon2 chipset only */
150 static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
153 "Extreme", /* 0xb5 */
154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
156 "FE+", /* 0xb8 */
157 };
158
159 static void sky2_set_multicast(struct net_device *dev);
160
161 /* Access to PHY via serial interconnect */
162 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
163 {
164 int i;
165
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
169
170 for (i = 0; i < PHY_RETRIES; i++) {
171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
172 if (ctrl == 0xffff)
173 goto io_error;
174
175 if (!(ctrl & GM_SMI_CT_BUSY))
176 return 0;
177
178 udelay(10);
179 }
180
181 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
182 return -ETIMEDOUT;
183
184 io_error:
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
186 return -EIO;
187 }
188
189 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
190 {
191 int i;
192
193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
195
196 for (i = 0; i < PHY_RETRIES; i++) {
197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
198 if (ctrl == 0xffff)
199 goto io_error;
200
201 if (ctrl & GM_SMI_CT_RD_VAL) {
202 *val = gma_read16(hw, port, GM_SMI_DATA);
203 return 0;
204 }
205
206 udelay(10);
207 }
208
209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
210 return -ETIMEDOUT;
211 io_error:
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
213 return -EIO;
214 }
215
216 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
217 {
218 u16 v;
219 __gm_phy_read(hw, port, reg, &v);
220 return v;
221 }
222
223
224 static void sky2_power_on(struct sky2_hw *hw)
225 {
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
229
230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
232
233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239 else
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
241
242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
243 u32 reg;
244
245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
246
247 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
248 /* set all bits to 0 except bits 15..12 and 8 */
249 reg &= P_ASPM_CONTROL_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
251
252 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
253 /* set all bits to 0 except bits 28 & 27 */
254 reg &= P_CTL_TIM_VMAIN_AV_MSK;
255 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
256
257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
258
259 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
260 reg = sky2_read32(hw, B2_GP_IO);
261 reg |= GLB_GPIO_STAT_RACE_DIS;
262 sky2_write32(hw, B2_GP_IO, reg);
263
264 sky2_read32(hw, B2_GP_IO);
265 }
266 }
267
268 static void sky2_power_aux(struct sky2_hw *hw)
269 {
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
279 /* switch power to VAUX */
280 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
284 }
285
286 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
287 {
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
292
293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301 }
302
303 /* flow control to advertise bits */
304 static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309 };
310
311 /* flow control to advertise bits when using 1000BaseX */
312 static const u16 fiber_fc_adv[] = {
313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
317 };
318
319 /* flow control to GMA disable bits */
320 static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325 };
326
327
328 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329 {
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
332
333 if (sky2->autoneg == AUTONEG_ENABLE &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
338 PHY_M_EC_MAC_S_MSK);
339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
342 if (hw->chip_id == CHIP_ID_YUKON_EC)
343 /* set downshift counter to 3x and enable downshift */
344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 if (sky2_is_copper(hw)) {
354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
367 } else {
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373
374 /* downshift on PHY 88E1112 and 88E1149 is changed */
375 if (sky2->autoneg == AUTONEG_ENABLE
376 && (hw->flags & SKY2_HW_NEWER_PHY)) {
377 /* set downshift counter to 3x and enable downshift */
378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
380 }
381 }
382 } else {
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
385
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
387 }
388
389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390
391 /* special setup for PHY 88E1112 Fiber */
392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
394
395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 if (hw->pmd_type == 'P') {
403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
405
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
410 }
411
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
413 }
414
415 ctrl = PHY_CT_RESET;
416 ct1000 = 0;
417 adv = PHY_AN_CSMA;
418 reg = 0;
419
420 if (sky2->autoneg == AUTONEG_ENABLE) {
421 if (sky2_is_copper(hw)) {
422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
434
435 adv |= copper_fc_adv[sky2->flow_mode];
436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
441
442 adv |= fiber_fc_adv[sky2->flow_mode];
443 }
444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
451 /* Disable auto update for duplex flow control and speed */
452 reg |= GM_GPCR_AU_ALL_DIS;
453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
457 reg |= GM_GPCR_SPEED_1000;
458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
461 reg |= GM_GPCR_SPEED_100;
462 break;
463 }
464
465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
470
471
472 reg |= gm_fc_disable[sky2->flow_mode];
473
474 /* Forward pause packets to GMAC? */
475 if (sky2->flow_mode & FC_RX)
476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
477 else
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
479 }
480
481 gma_write16(hw, port, GM_GP_CTRL, reg);
482
483 if (hw->flags & SKY2_HW_GIGABIT)
484 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
485
486 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
488
489 /* Setup Phy LED's */
490 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
491 ledover = 0;
492
493 switch (hw->chip_id) {
494 case CHIP_ID_YUKON_FE:
495 /* on 88E3082 these bits are at 11..9 (shifted left) */
496 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
497
498 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
499
500 /* delete ACT LED control bits */
501 ctrl &= ~PHY_M_FELP_LED1_MSK;
502 /* change ACT LED control to blink mode */
503 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
504 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
505 break;
506
507 case CHIP_ID_YUKON_FE_P:
508 /* Enable Link Partner Next Page */
509 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
510 ctrl |= PHY_M_PC_ENA_LIP_NP;
511
512 /* disable Energy Detect and enable scrambler */
513 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
515
516 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
517 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
518 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
519 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
520
521 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
522 break;
523
524 case CHIP_ID_YUKON_XL:
525 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
526
527 /* select page 3 to access LED control register */
528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
529
530 /* set LED Function Control register */
531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
532 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
533 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
534 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
535 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
536
537 /* set Polarity Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
539 (PHY_M_POLC_LS1_P_MIX(4) |
540 PHY_M_POLC_IS0_P_MIX(4) |
541 PHY_M_POLC_LOS_CTRL(2) |
542 PHY_M_POLC_INIT_CTRL(2) |
543 PHY_M_POLC_STA1_CTRL(2) |
544 PHY_M_POLC_STA0_CTRL(2)));
545
546 /* restore page register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
548 break;
549
550 case CHIP_ID_YUKON_EC_U:
551 case CHIP_ID_YUKON_EX:
552 case CHIP_ID_YUKON_SUPR:
553 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
554
555 /* select page 3 to access LED control register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
557
558 /* set LED Function Control register */
559 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
560 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
561 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
562 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
563 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
564
565 /* set Blink Rate in LED Timer Control Register */
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
567 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
568 /* restore page register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
570 break;
571
572 default:
573 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
574 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
575 /* turn off the Rx LED (LED_RX) */
576 ledover &= ~PHY_M_LED_MO_RX;
577 }
578
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
580 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
581 /* apply fixes in PHY AFE */
582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
583
584 /* increase differential signal amplitude in 10BASE-T */
585 gm_phy_write(hw, port, 0x18, 0xaa99);
586 gm_phy_write(hw, port, 0x17, 0x2011);
587
588 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
589 gm_phy_write(hw, port, 0x18, 0xa204);
590 gm_phy_write(hw, port, 0x17, 0x2002);
591
592 /* set page register to 0 */
593 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
594 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
595 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
596 /* apply workaround for integrated resistors calibration */
597 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
598 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
599 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
600 /* no effect on Yukon-XL */
601 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
602
603 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
604 /* turn on 100 Mbps LED (LED_LINK100) */
605 ledover |= PHY_M_LED_MO_100;
606 }
607
608 if (ledover)
609 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
610
611 }
612
613 /* Enable phy interrupt on auto-negotiation complete (or link up) */
614 if (sky2->autoneg == AUTONEG_ENABLE)
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
616 else
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
618 }
619
620 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
621 {
622 u32 reg1;
623 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
624 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
625
626 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
627 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
628 /* Turn on/off phy power saving */
629 if (onoff)
630 reg1 &= ~phy_power[port];
631 else
632 reg1 |= phy_power[port];
633
634 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
635 reg1 |= coma_mode[port];
636
637 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
638 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
639 sky2_pci_read32(hw, PCI_DEV_REG1);
640
641 udelay(100);
642 }
643
644 /* Force a renegotiation */
645 static void sky2_phy_reinit(struct sky2_port *sky2)
646 {
647 spin_lock_bh(&sky2->phy_lock);
648 sky2_phy_init(sky2->hw, sky2->port);
649 spin_unlock_bh(&sky2->phy_lock);
650 }
651
652 /* Put device in state to listen for Wake On Lan */
653 static void sky2_wol_init(struct sky2_port *sky2)
654 {
655 struct sky2_hw *hw = sky2->hw;
656 unsigned port = sky2->port;
657 enum flow_control save_mode;
658 u16 ctrl;
659 u32 reg1;
660
661 /* Bring hardware out of reset */
662 sky2_write16(hw, B0_CTST, CS_RST_CLR);
663 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
664
665 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
666 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
667
668 /* Force to 10/100
669 * sky2_reset will re-enable on resume
670 */
671 save_mode = sky2->flow_mode;
672 ctrl = sky2->advertising;
673
674 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
675 sky2->flow_mode = FC_NONE;
676 sky2_phy_power(hw, port, 1);
677 sky2_phy_reinit(sky2);
678
679 sky2->flow_mode = save_mode;
680 sky2->advertising = ctrl;
681
682 /* Set GMAC to no flow control and auto update for speed/duplex */
683 gma_write16(hw, port, GM_GP_CTRL,
684 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
685 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
686
687 /* Set WOL address */
688 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
689 sky2->netdev->dev_addr, ETH_ALEN);
690
691 /* Turn on appropriate WOL control bits */
692 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
693 ctrl = 0;
694 if (sky2->wol & WAKE_PHY)
695 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
696 else
697 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
698
699 if (sky2->wol & WAKE_MAGIC)
700 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
701 else
702 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
703
704 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
705 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
706
707 /* Turn on legacy PCI-Express PME mode */
708 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
709 reg1 |= PCI_Y2_PME_LEGACY;
710 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
711
712 /* block receiver */
713 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
714
715 }
716
717 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
718 {
719 struct net_device *dev = hw->dev[port];
720
721 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
722 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
723 hw->chip_id == CHIP_ID_YUKON_FE_P ||
724 hw->chip_id == CHIP_ID_YUKON_SUPR) {
725 /* Yukon-Extreme B0 and further Extreme devices */
726 /* enable Store & Forward mode for TX */
727
728 if (dev->mtu <= ETH_DATA_LEN)
729 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
730 TX_JUMBO_DIS | TX_STFW_ENA);
731
732 else
733 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
734 TX_JUMBO_ENA| TX_STFW_ENA);
735 } else {
736 if (dev->mtu <= ETH_DATA_LEN)
737 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
738 else {
739 /* set Tx GMAC FIFO Almost Empty Threshold */
740 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
741 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
742
743 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
744
745 /* Can't do offload because of lack of store/forward */
746 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
747 }
748 }
749 }
750
751 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
752 {
753 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
754 u16 reg;
755 u32 rx_reg;
756 int i;
757 const u8 *addr = hw->dev[port]->dev_addr;
758
759 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
760 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
761
762 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
763
764 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
765 /* WA DEV_472 -- looks like crossed wires on port 2 */
766 /* clear GMAC 1 Control reset */
767 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
768 do {
769 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
770 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
771 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
772 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
773 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
774 }
775
776 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
777
778 /* Enable Transmit FIFO Underrun */
779 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
780
781 spin_lock_bh(&sky2->phy_lock);
782 sky2_phy_init(hw, port);
783 spin_unlock_bh(&sky2->phy_lock);
784
785 /* MIB clear */
786 reg = gma_read16(hw, port, GM_PHY_ADDR);
787 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
788
789 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
790 gma_read16(hw, port, i);
791 gma_write16(hw, port, GM_PHY_ADDR, reg);
792
793 /* transmit control */
794 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
795
796 /* receive control reg: unicast + multicast + no FCS */
797 gma_write16(hw, port, GM_RX_CTRL,
798 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
799
800 /* transmit flow control */
801 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
802
803 /* transmit parameter */
804 gma_write16(hw, port, GM_TX_PARAM,
805 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
806 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
807 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
808 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
809
810 /* serial mode register */
811 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
812 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
813
814 if (hw->dev[port]->mtu > ETH_DATA_LEN)
815 reg |= GM_SMOD_JUMBO_ENA;
816
817 gma_write16(hw, port, GM_SERIAL_MODE, reg);
818
819 /* virtual address for data */
820 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
821
822 /* physical address: used for pause frames */
823 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
824
825 /* ignore counter overflows */
826 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
827 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
828 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
829
830 /* Configure Rx MAC FIFO */
831 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
832 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
833 if (hw->chip_id == CHIP_ID_YUKON_EX ||
834 hw->chip_id == CHIP_ID_YUKON_FE_P)
835 rx_reg |= GMF_RX_OVER_ON;
836
837 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
838
839 if (hw->chip_id == CHIP_ID_YUKON_XL) {
840 /* Hardware errata - clear flush mask */
841 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
842 } else {
843 /* Flush Rx MAC FIFO on any flow control or error */
844 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
845 }
846
847 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
848 reg = RX_GMF_FL_THR_DEF + 1;
849 /* Another magic mystery workaround from sk98lin */
850 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
851 hw->chip_rev == CHIP_REV_YU_FE2_A0)
852 reg = 0x178;
853 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
854
855 /* Configure Tx MAC FIFO */
856 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
857 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
858
859 /* On chips without ram buffer, pause is controled by MAC level */
860 if (sky2_read8(hw, B2_E_0) == 0) {
861 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
862 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
863
864 sky2_set_tx_stfwd(hw, port);
865 }
866
867 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
868 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
869 /* disable dynamic watermark */
870 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
871 reg &= ~TX_DYN_WM_ENA;
872 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
873 }
874 }
875
876 /* Assign Ram Buffer allocation to queue */
877 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
878 {
879 u32 end;
880
881 /* convert from K bytes to qwords used for hw register */
882 start *= 1024/8;
883 space *= 1024/8;
884 end = start + space - 1;
885
886 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
887 sky2_write32(hw, RB_ADDR(q, RB_START), start);
888 sky2_write32(hw, RB_ADDR(q, RB_END), end);
889 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
890 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
891
892 if (q == Q_R1 || q == Q_R2) {
893 u32 tp = space - space/4;
894
895 /* On receive queue's set the thresholds
896 * give receiver priority when > 3/4 full
897 * send pause when down to 2K
898 */
899 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
900 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
901
902 tp = space - 2048/8;
903 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
904 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
905 } else {
906 /* Enable store & forward on Tx queue's because
907 * Tx FIFO is only 1K on Yukon
908 */
909 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
910 }
911
912 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
913 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
914 }
915
916 /* Setup Bus Memory Interface */
917 static void sky2_qset(struct sky2_hw *hw, u16 q)
918 {
919 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
920 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
921 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
922 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
923 }
924
925 /* Setup prefetch unit registers. This is the interface between
926 * hardware and driver list elements
927 */
928 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
929 u64 addr, u32 last)
930 {
931 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
932 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
933 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
934 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
935 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
936 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
937
938 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
939 }
940
941 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
942 {
943 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
944
945 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
946 le->ctrl = 0;
947 return le;
948 }
949
950 static void tx_init(struct sky2_port *sky2)
951 {
952 struct sky2_tx_le *le;
953
954 sky2->tx_prod = sky2->tx_cons = 0;
955 sky2->tx_tcpsum = 0;
956 sky2->tx_last_mss = 0;
957
958 le = get_tx_le(sky2);
959 le->addr = 0;
960 le->opcode = OP_ADDR64 | HW_OWNER;
961 }
962
963 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
964 struct sky2_tx_le *le)
965 {
966 return sky2->tx_ring + (le - sky2->tx_le);
967 }
968
969 /* Update chip's next pointer */
970 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
971 {
972 /* Make sure write' to descriptors are complete before we tell hardware */
973 wmb();
974 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
975
976 /* Synchronize I/O on since next processor may write to tail */
977 mmiowb();
978 }
979
980
981 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
982 {
983 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
984 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
985 le->ctrl = 0;
986 return le;
987 }
988
989 /* Build description to hardware for one receive segment */
990 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
991 dma_addr_t map, unsigned len)
992 {
993 struct sky2_rx_le *le;
994
995 if (sizeof(dma_addr_t) > sizeof(u32)) {
996 le = sky2_next_rx(sky2);
997 le->addr = cpu_to_le32(upper_32_bits(map));
998 le->opcode = OP_ADDR64 | HW_OWNER;
999 }
1000
1001 le = sky2_next_rx(sky2);
1002 le->addr = cpu_to_le32((u32) map);
1003 le->length = cpu_to_le16(len);
1004 le->opcode = op | HW_OWNER;
1005 }
1006
1007 /* Build description to hardware for one possibly fragmented skb */
1008 static void sky2_rx_submit(struct sky2_port *sky2,
1009 const struct rx_ring_info *re)
1010 {
1011 int i;
1012
1013 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1014
1015 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1016 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1017 }
1018
1019
1020 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1021 unsigned size)
1022 {
1023 struct sk_buff *skb = re->skb;
1024 int i;
1025
1026 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1027 pci_unmap_len_set(re, data_size, size);
1028
1029 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1030 re->frag_addr[i] = pci_map_page(pdev,
1031 skb_shinfo(skb)->frags[i].page,
1032 skb_shinfo(skb)->frags[i].page_offset,
1033 skb_shinfo(skb)->frags[i].size,
1034 PCI_DMA_FROMDEVICE);
1035 }
1036
1037 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1038 {
1039 struct sk_buff *skb = re->skb;
1040 int i;
1041
1042 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1043 PCI_DMA_FROMDEVICE);
1044
1045 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1046 pci_unmap_page(pdev, re->frag_addr[i],
1047 skb_shinfo(skb)->frags[i].size,
1048 PCI_DMA_FROMDEVICE);
1049 }
1050
1051 /* Tell chip where to start receive checksum.
1052 * Actually has two checksums, but set both same to avoid possible byte
1053 * order problems.
1054 */
1055 static void rx_set_checksum(struct sky2_port *sky2)
1056 {
1057 struct sky2_rx_le *le = sky2_next_rx(sky2);
1058
1059 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1060 le->ctrl = 0;
1061 le->opcode = OP_TCPSTART | HW_OWNER;
1062
1063 sky2_write32(sky2->hw,
1064 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1065 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1066 }
1067
1068 /*
1069 * The RX Stop command will not work for Yukon-2 if the BMU does not
1070 * reach the end of packet and since we can't make sure that we have
1071 * incoming data, we must reset the BMU while it is not doing a DMA
1072 * transfer. Since it is possible that the RX path is still active,
1073 * the RX RAM buffer will be stopped first, so any possible incoming
1074 * data will not trigger a DMA. After the RAM buffer is stopped, the
1075 * BMU is polled until any DMA in progress is ended and only then it
1076 * will be reset.
1077 */
1078 static void sky2_rx_stop(struct sky2_port *sky2)
1079 {
1080 struct sky2_hw *hw = sky2->hw;
1081 unsigned rxq = rxqaddr[sky2->port];
1082 int i;
1083
1084 /* disable the RAM Buffer receive queue */
1085 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1086
1087 for (i = 0; i < 0xffff; i++)
1088 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1089 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1090 goto stopped;
1091
1092 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1093 sky2->netdev->name);
1094 stopped:
1095 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1096
1097 /* reset the Rx prefetch unit */
1098 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1099 mmiowb();
1100 }
1101
1102 /* Clean out receive buffer area, assumes receiver hardware stopped */
1103 static void sky2_rx_clean(struct sky2_port *sky2)
1104 {
1105 unsigned i;
1106
1107 memset(sky2->rx_le, 0, RX_LE_BYTES);
1108 for (i = 0; i < sky2->rx_pending; i++) {
1109 struct rx_ring_info *re = sky2->rx_ring + i;
1110
1111 if (re->skb) {
1112 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1113 kfree_skb(re->skb);
1114 re->skb = NULL;
1115 }
1116 }
1117 }
1118
1119 /* Basic MII support */
1120 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1121 {
1122 struct mii_ioctl_data *data = if_mii(ifr);
1123 struct sky2_port *sky2 = netdev_priv(dev);
1124 struct sky2_hw *hw = sky2->hw;
1125 int err = -EOPNOTSUPP;
1126
1127 if (!netif_running(dev))
1128 return -ENODEV; /* Phy still in reset */
1129
1130 switch (cmd) {
1131 case SIOCGMIIPHY:
1132 data->phy_id = PHY_ADDR_MARV;
1133
1134 /* fallthru */
1135 case SIOCGMIIREG: {
1136 u16 val = 0;
1137
1138 spin_lock_bh(&sky2->phy_lock);
1139 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1140 spin_unlock_bh(&sky2->phy_lock);
1141
1142 data->val_out = val;
1143 break;
1144 }
1145
1146 case SIOCSMIIREG:
1147 if (!capable(CAP_NET_ADMIN))
1148 return -EPERM;
1149
1150 spin_lock_bh(&sky2->phy_lock);
1151 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1152 data->val_in);
1153 spin_unlock_bh(&sky2->phy_lock);
1154 break;
1155 }
1156 return err;
1157 }
1158
1159 #ifdef SKY2_VLAN_TAG_USED
1160 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1161 {
1162 struct sky2_port *sky2 = netdev_priv(dev);
1163 struct sky2_hw *hw = sky2->hw;
1164 u16 port = sky2->port;
1165
1166 netif_tx_lock_bh(dev);
1167 napi_disable(&hw->napi);
1168
1169 sky2->vlgrp = grp;
1170 if (grp) {
1171 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1172 RX_VLAN_STRIP_ON);
1173 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1174 TX_VLAN_TAG_ON);
1175 } else {
1176 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1177 RX_VLAN_STRIP_OFF);
1178 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1179 TX_VLAN_TAG_OFF);
1180 }
1181
1182 sky2_read32(hw, B0_Y2_SP_LISR);
1183 napi_enable(&hw->napi);
1184 netif_tx_unlock_bh(dev);
1185 }
1186 #endif
1187
1188 /*
1189 * Allocate an skb for receiving. If the MTU is large enough
1190 * make the skb non-linear with a fragment list of pages.
1191 */
1192 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1193 {
1194 struct sk_buff *skb;
1195 int i;
1196
1197 if (sky2->hw->flags & SKY2_HW_FIFO_HANG_CHECK) {
1198 unsigned char *start;
1199 /*
1200 * Workaround for a bug in FIFO that cause hang
1201 * if the FIFO if the receive buffer is not 64 byte aligned.
1202 * The buffer returned from netdev_alloc_skb is
1203 * aligned except if slab debugging is enabled.
1204 */
1205 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1206 if (!skb)
1207 goto nomem;
1208 start = PTR_ALIGN(skb->data, 8);
1209 skb_reserve(skb, start - skb->data);
1210 } else {
1211 skb = netdev_alloc_skb(sky2->netdev,
1212 sky2->rx_data_size + NET_IP_ALIGN);
1213 if (!skb)
1214 goto nomem;
1215 skb_reserve(skb, NET_IP_ALIGN);
1216 }
1217
1218 for (i = 0; i < sky2->rx_nfrags; i++) {
1219 struct page *page = alloc_page(GFP_ATOMIC);
1220
1221 if (!page)
1222 goto free_partial;
1223 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1224 }
1225
1226 return skb;
1227 free_partial:
1228 kfree_skb(skb);
1229 nomem:
1230 return NULL;
1231 }
1232
1233 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1234 {
1235 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1236 }
1237
1238 /*
1239 * Allocate and setup receiver buffer pool.
1240 * Normal case this ends up creating one list element for skb
1241 * in the receive ring. Worst case if using large MTU and each
1242 * allocation falls on a different 64 bit region, that results
1243 * in 6 list elements per ring entry.
1244 * One element is used for checksum enable/disable, and one
1245 * extra to avoid wrap.
1246 */
1247 static int sky2_rx_start(struct sky2_port *sky2)
1248 {
1249 struct sky2_hw *hw = sky2->hw;
1250 struct rx_ring_info *re;
1251 unsigned rxq = rxqaddr[sky2->port];
1252 unsigned i, size, thresh;
1253
1254 sky2->rx_put = sky2->rx_next = 0;
1255 sky2_qset(hw, rxq);
1256
1257 /* On PCI express lowering the watermark gives better performance */
1258 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1259 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1260
1261 /* These chips have no ram buffer?
1262 * MAC Rx RAM Read is controlled by hardware */
1263 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1264 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1265 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1266 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1267
1268 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1269
1270 if (!(hw->flags & SKY2_HW_NEW_LE))
1271 rx_set_checksum(sky2);
1272
1273 /* Space needed for frame data + headers rounded up */
1274 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1275
1276 /* Stopping point for hardware truncation */
1277 thresh = (size - 8) / sizeof(u32);
1278
1279 sky2->rx_nfrags = size >> PAGE_SHIFT;
1280 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1281
1282 /* Compute residue after pages */
1283 size -= sky2->rx_nfrags << PAGE_SHIFT;
1284
1285 /* Optimize to handle small packets and headers */
1286 if (size < copybreak)
1287 size = copybreak;
1288 if (size < ETH_HLEN)
1289 size = ETH_HLEN;
1290
1291 sky2->rx_data_size = size;
1292
1293 /* Fill Rx ring */
1294 for (i = 0; i < sky2->rx_pending; i++) {
1295 re = sky2->rx_ring + i;
1296
1297 re->skb = sky2_rx_alloc(sky2);
1298 if (!re->skb)
1299 goto nomem;
1300
1301 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1302 sky2_rx_submit(sky2, re);
1303 }
1304
1305 /*
1306 * The receiver hangs if it receives frames larger than the
1307 * packet buffer. As a workaround, truncate oversize frames, but
1308 * the register is limited to 9 bits, so if you do frames > 2052
1309 * you better get the MTU right!
1310 */
1311 if (thresh > 0x1ff)
1312 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1313 else {
1314 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1315 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1316 }
1317
1318 /* Tell chip about available buffers */
1319 sky2_rx_update(sky2, rxq);
1320 return 0;
1321 nomem:
1322 sky2_rx_clean(sky2);
1323 return -ENOMEM;
1324 }
1325
1326 /* Bring up network interface. */
1327 static int sky2_up(struct net_device *dev)
1328 {
1329 struct sky2_port *sky2 = netdev_priv(dev);
1330 struct sky2_hw *hw = sky2->hw;
1331 unsigned port = sky2->port;
1332 u32 imask, ramsize;
1333 int cap, err = -ENOMEM;
1334 struct net_device *otherdev = hw->dev[sky2->port^1];
1335
1336 /*
1337 * On dual port PCI-X card, there is an problem where status
1338 * can be received out of order due to split transactions
1339 */
1340 if (otherdev && netif_running(otherdev) &&
1341 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1342 u16 cmd;
1343
1344 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1345 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1346 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1347
1348 }
1349
1350 if (netif_msg_ifup(sky2))
1351 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1352
1353 netif_carrier_off(dev);
1354
1355 /* must be power of 2 */
1356 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1357 TX_RING_SIZE *
1358 sizeof(struct sky2_tx_le),
1359 &sky2->tx_le_map);
1360 if (!sky2->tx_le)
1361 goto err_out;
1362
1363 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1364 GFP_KERNEL);
1365 if (!sky2->tx_ring)
1366 goto err_out;
1367
1368 tx_init(sky2);
1369
1370 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1371 &sky2->rx_le_map);
1372 if (!sky2->rx_le)
1373 goto err_out;
1374 memset(sky2->rx_le, 0, RX_LE_BYTES);
1375
1376 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1377 GFP_KERNEL);
1378 if (!sky2->rx_ring)
1379 goto err_out;
1380
1381 sky2_phy_power(hw, port, 1);
1382
1383 sky2_mac_init(hw, port);
1384
1385 /* Register is number of 4K blocks on internal RAM buffer. */
1386 ramsize = sky2_read8(hw, B2_E_0) * 4;
1387 if (ramsize > 0) {
1388 u32 rxspace;
1389
1390 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1391 if (ramsize < 16)
1392 rxspace = ramsize / 2;
1393 else
1394 rxspace = 8 + (2*(ramsize - 16))/3;
1395
1396 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1397 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1398
1399 /* Make sure SyncQ is disabled */
1400 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1401 RB_RST_SET);
1402 }
1403
1404 sky2_qset(hw, txqaddr[port]);
1405
1406 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1407 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1408 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1409
1410 /* Set almost empty threshold */
1411 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1412 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1413 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1414
1415 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1416 TX_RING_SIZE - 1);
1417
1418 err = sky2_rx_start(sky2);
1419 if (err)
1420 goto err_out;
1421
1422 /* Enable interrupts from phy/mac for port */
1423 imask = sky2_read32(hw, B0_IMSK);
1424 imask |= portirq_msk[port];
1425 sky2_write32(hw, B0_IMSK, imask);
1426
1427 sky2_set_multicast(dev);
1428 return 0;
1429
1430 err_out:
1431 if (sky2->rx_le) {
1432 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1433 sky2->rx_le, sky2->rx_le_map);
1434 sky2->rx_le = NULL;
1435 }
1436 if (sky2->tx_le) {
1437 pci_free_consistent(hw->pdev,
1438 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1439 sky2->tx_le, sky2->tx_le_map);
1440 sky2->tx_le = NULL;
1441 }
1442 kfree(sky2->tx_ring);
1443 kfree(sky2->rx_ring);
1444
1445 sky2->tx_ring = NULL;
1446 sky2->rx_ring = NULL;
1447 return err;
1448 }
1449
1450 /* Modular subtraction in ring */
1451 static inline int tx_dist(unsigned tail, unsigned head)
1452 {
1453 return (head - tail) & (TX_RING_SIZE - 1);
1454 }
1455
1456 /* Number of list elements available for next tx */
1457 static inline int tx_avail(const struct sky2_port *sky2)
1458 {
1459 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1460 }
1461
1462 /* Estimate of number of transmit list elements required */
1463 static unsigned tx_le_req(const struct sk_buff *skb)
1464 {
1465 unsigned count;
1466
1467 count = sizeof(dma_addr_t) / sizeof(u32);
1468 count += skb_shinfo(skb)->nr_frags * count;
1469
1470 if (skb_is_gso(skb))
1471 ++count;
1472
1473 if (skb->ip_summed == CHECKSUM_PARTIAL)
1474 ++count;
1475
1476 return count;
1477 }
1478
1479 /*
1480 * Put one packet in ring for transmit.
1481 * A single packet can generate multiple list elements, and
1482 * the number of ring elements will probably be less than the number
1483 * of list elements used.
1484 */
1485 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1486 {
1487 struct sky2_port *sky2 = netdev_priv(dev);
1488 struct sky2_hw *hw = sky2->hw;
1489 struct sky2_tx_le *le = NULL;
1490 struct tx_ring_info *re;
1491 unsigned i, len;
1492 dma_addr_t mapping;
1493 u16 mss;
1494 u8 ctrl;
1495
1496 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1497 return NETDEV_TX_BUSY;
1498
1499 if (unlikely(netif_msg_tx_queued(sky2)))
1500 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1501 dev->name, sky2->tx_prod, skb->len);
1502
1503 len = skb_headlen(skb);
1504 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1505
1506 /* Send high bits if needed */
1507 if (sizeof(dma_addr_t) > sizeof(u32)) {
1508 le = get_tx_le(sky2);
1509 le->addr = cpu_to_le32(upper_32_bits(mapping));
1510 le->opcode = OP_ADDR64 | HW_OWNER;
1511 }
1512
1513 /* Check for TCP Segmentation Offload */
1514 mss = skb_shinfo(skb)->gso_size;
1515 if (mss != 0) {
1516
1517 if (!(hw->flags & SKY2_HW_NEW_LE))
1518 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1519
1520 if (mss != sky2->tx_last_mss) {
1521 le = get_tx_le(sky2);
1522 le->addr = cpu_to_le32(mss);
1523
1524 if (hw->flags & SKY2_HW_NEW_LE)
1525 le->opcode = OP_MSS | HW_OWNER;
1526 else
1527 le->opcode = OP_LRGLEN | HW_OWNER;
1528 sky2->tx_last_mss = mss;
1529 }
1530 }
1531
1532 ctrl = 0;
1533 #ifdef SKY2_VLAN_TAG_USED
1534 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1535 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1536 if (!le) {
1537 le = get_tx_le(sky2);
1538 le->addr = 0;
1539 le->opcode = OP_VLAN|HW_OWNER;
1540 } else
1541 le->opcode |= OP_VLAN;
1542 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1543 ctrl |= INS_VLAN;
1544 }
1545 #endif
1546
1547 /* Handle TCP checksum offload */
1548 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1549 /* On Yukon EX (some versions) encoding change. */
1550 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1551 ctrl |= CALSUM; /* auto checksum */
1552 else {
1553 const unsigned offset = skb_transport_offset(skb);
1554 u32 tcpsum;
1555
1556 tcpsum = offset << 16; /* sum start */
1557 tcpsum |= offset + skb->csum_offset; /* sum write */
1558
1559 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1560 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1561 ctrl |= UDPTCP;
1562
1563 if (tcpsum != sky2->tx_tcpsum) {
1564 sky2->tx_tcpsum = tcpsum;
1565
1566 le = get_tx_le(sky2);
1567 le->addr = cpu_to_le32(tcpsum);
1568 le->length = 0; /* initial checksum value */
1569 le->ctrl = 1; /* one packet */
1570 le->opcode = OP_TCPLISW | HW_OWNER;
1571 }
1572 }
1573 }
1574
1575 le = get_tx_le(sky2);
1576 le->addr = cpu_to_le32((u32) mapping);
1577 le->length = cpu_to_le16(len);
1578 le->ctrl = ctrl;
1579 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1580
1581 re = tx_le_re(sky2, le);
1582 re->skb = skb;
1583 pci_unmap_addr_set(re, mapaddr, mapping);
1584 pci_unmap_len_set(re, maplen, len);
1585
1586 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1587 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1588
1589 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1590 frag->size, PCI_DMA_TODEVICE);
1591
1592 if (sizeof(dma_addr_t) > sizeof(u32)) {
1593 le = get_tx_le(sky2);
1594 le->addr = cpu_to_le32(upper_32_bits(mapping));
1595 le->ctrl = 0;
1596 le->opcode = OP_ADDR64 | HW_OWNER;
1597 }
1598
1599 le = get_tx_le(sky2);
1600 le->addr = cpu_to_le32((u32) mapping);
1601 le->length = cpu_to_le16(frag->size);
1602 le->ctrl = ctrl;
1603 le->opcode = OP_BUFFER | HW_OWNER;
1604
1605 re = tx_le_re(sky2, le);
1606 re->skb = skb;
1607 pci_unmap_addr_set(re, mapaddr, mapping);
1608 pci_unmap_len_set(re, maplen, frag->size);
1609 }
1610
1611 le->ctrl |= EOP;
1612
1613 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1614 netif_stop_queue(dev);
1615
1616 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1617
1618 dev->trans_start = jiffies;
1619 return NETDEV_TX_OK;
1620 }
1621
1622 /*
1623 * Free ring elements from starting at tx_cons until "done"
1624 *
1625 * NB: the hardware will tell us about partial completion of multi-part
1626 * buffers so make sure not to free skb to early.
1627 */
1628 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1629 {
1630 struct net_device *dev = sky2->netdev;
1631 struct pci_dev *pdev = sky2->hw->pdev;
1632 unsigned idx;
1633
1634 BUG_ON(done >= TX_RING_SIZE);
1635
1636 for (idx = sky2->tx_cons; idx != done;
1637 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1638 struct sky2_tx_le *le = sky2->tx_le + idx;
1639 struct tx_ring_info *re = sky2->tx_ring + idx;
1640
1641 switch(le->opcode & ~HW_OWNER) {
1642 case OP_LARGESEND:
1643 case OP_PACKET:
1644 pci_unmap_single(pdev,
1645 pci_unmap_addr(re, mapaddr),
1646 pci_unmap_len(re, maplen),
1647 PCI_DMA_TODEVICE);
1648 break;
1649 case OP_BUFFER:
1650 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1651 pci_unmap_len(re, maplen),
1652 PCI_DMA_TODEVICE);
1653 break;
1654 }
1655
1656 if (le->ctrl & EOP) {
1657 if (unlikely(netif_msg_tx_done(sky2)))
1658 printk(KERN_DEBUG "%s: tx done %u\n",
1659 dev->name, idx);
1660
1661 dev->stats.tx_packets++;
1662 dev->stats.tx_bytes += re->skb->len;
1663
1664 dev_kfree_skb_any(re->skb);
1665 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1666 }
1667 }
1668
1669 sky2->tx_cons = idx;
1670 smp_mb();
1671
1672 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1673 netif_wake_queue(dev);
1674 }
1675
1676 /* Cleanup all untransmitted buffers, assume transmitter not running */
1677 static void sky2_tx_clean(struct net_device *dev)
1678 {
1679 struct sky2_port *sky2 = netdev_priv(dev);
1680
1681 netif_tx_lock_bh(dev);
1682 sky2_tx_complete(sky2, sky2->tx_prod);
1683 netif_tx_unlock_bh(dev);
1684 }
1685
1686 /* Network shutdown */
1687 static int sky2_down(struct net_device *dev)
1688 {
1689 struct sky2_port *sky2 = netdev_priv(dev);
1690 struct sky2_hw *hw = sky2->hw;
1691 unsigned port = sky2->port;
1692 u16 ctrl;
1693 u32 imask;
1694
1695 /* Never really got started! */
1696 if (!sky2->tx_le)
1697 return 0;
1698
1699 if (netif_msg_ifdown(sky2))
1700 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1701
1702 /* Stop more packets from being queued */
1703 netif_stop_queue(dev);
1704
1705 /* Disable port IRQ */
1706 imask = sky2_read32(hw, B0_IMSK);
1707 imask &= ~portirq_msk[port];
1708 sky2_write32(hw, B0_IMSK, imask);
1709
1710 synchronize_irq(hw->pdev->irq);
1711
1712 sky2_gmac_reset(hw, port);
1713
1714 /* Stop transmitter */
1715 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1716 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1717
1718 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1719 RB_RST_SET | RB_DIS_OP_MD);
1720
1721 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1722 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1723 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1724
1725 /* Make sure no packets are pending */
1726 napi_synchronize(&hw->napi);
1727
1728 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1729
1730 /* Workaround shared GMAC reset */
1731 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1732 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1733 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1734
1735 /* Disable Force Sync bit and Enable Alloc bit */
1736 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1737 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1738
1739 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1740 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1741 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1742
1743 /* Reset the PCI FIFO of the async Tx queue */
1744 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1745 BMU_RST_SET | BMU_FIFO_RST);
1746
1747 /* Reset the Tx prefetch units */
1748 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1749 PREF_UNIT_RST_SET);
1750
1751 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1752
1753 sky2_rx_stop(sky2);
1754
1755 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1756 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1757
1758 sky2_phy_power(hw, port, 0);
1759
1760 netif_carrier_off(dev);
1761
1762 /* turn off LED's */
1763 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1764
1765 sky2_tx_clean(dev);
1766 sky2_rx_clean(sky2);
1767
1768 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1769 sky2->rx_le, sky2->rx_le_map);
1770 kfree(sky2->rx_ring);
1771
1772 pci_free_consistent(hw->pdev,
1773 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1774 sky2->tx_le, sky2->tx_le_map);
1775 kfree(sky2->tx_ring);
1776
1777 sky2->tx_le = NULL;
1778 sky2->rx_le = NULL;
1779
1780 sky2->rx_ring = NULL;
1781 sky2->tx_ring = NULL;
1782
1783 return 0;
1784 }
1785
1786 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1787 {
1788 if (hw->flags & SKY2_HW_FIBRE_PHY)
1789 return SPEED_1000;
1790
1791 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1792 if (aux & PHY_M_PS_SPEED_100)
1793 return SPEED_100;
1794 else
1795 return SPEED_10;
1796 }
1797
1798 switch (aux & PHY_M_PS_SPEED_MSK) {
1799 case PHY_M_PS_SPEED_1000:
1800 return SPEED_1000;
1801 case PHY_M_PS_SPEED_100:
1802 return SPEED_100;
1803 default:
1804 return SPEED_10;
1805 }
1806 }
1807
1808 static void sky2_link_up(struct sky2_port *sky2)
1809 {
1810 struct sky2_hw *hw = sky2->hw;
1811 unsigned port = sky2->port;
1812 u16 reg;
1813 static const char *fc_name[] = {
1814 [FC_NONE] = "none",
1815 [FC_TX] = "tx",
1816 [FC_RX] = "rx",
1817 [FC_BOTH] = "both",
1818 };
1819
1820 /* enable Rx/Tx */
1821 reg = gma_read16(hw, port, GM_GP_CTRL);
1822 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1823 gma_write16(hw, port, GM_GP_CTRL, reg);
1824
1825 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1826
1827 netif_carrier_on(sky2->netdev);
1828
1829 mod_timer(&hw->watchdog_timer, jiffies + 1);
1830
1831 /* Turn on link LED */
1832 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1833 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1834
1835 if (netif_msg_link(sky2))
1836 printk(KERN_INFO PFX
1837 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1838 sky2->netdev->name, sky2->speed,
1839 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1840 fc_name[sky2->flow_status]);
1841 }
1842
1843 static void sky2_link_down(struct sky2_port *sky2)
1844 {
1845 struct sky2_hw *hw = sky2->hw;
1846 unsigned port = sky2->port;
1847 u16 reg;
1848
1849 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1850
1851 reg = gma_read16(hw, port, GM_GP_CTRL);
1852 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1853 gma_write16(hw, port, GM_GP_CTRL, reg);
1854
1855 netif_carrier_off(sky2->netdev);
1856
1857 /* Turn on link LED */
1858 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1859
1860 if (netif_msg_link(sky2))
1861 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1862
1863 sky2_phy_init(hw, port);
1864 }
1865
1866 static enum flow_control sky2_flow(int rx, int tx)
1867 {
1868 if (rx)
1869 return tx ? FC_BOTH : FC_RX;
1870 else
1871 return tx ? FC_TX : FC_NONE;
1872 }
1873
1874 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1875 {
1876 struct sky2_hw *hw = sky2->hw;
1877 unsigned port = sky2->port;
1878 u16 advert, lpa;
1879
1880 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1881 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1882 if (lpa & PHY_M_AN_RF) {
1883 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1884 return -1;
1885 }
1886
1887 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1888 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1889 sky2->netdev->name);
1890 return -1;
1891 }
1892
1893 sky2->speed = sky2_phy_speed(hw, aux);
1894 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1895
1896 /* Since the pause result bits seem to in different positions on
1897 * different chips. look at registers.
1898 */
1899 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1900 /* Shift for bits in fiber PHY */
1901 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1902 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1903
1904 if (advert & ADVERTISE_1000XPAUSE)
1905 advert |= ADVERTISE_PAUSE_CAP;
1906 if (advert & ADVERTISE_1000XPSE_ASYM)
1907 advert |= ADVERTISE_PAUSE_ASYM;
1908 if (lpa & LPA_1000XPAUSE)
1909 lpa |= LPA_PAUSE_CAP;
1910 if (lpa & LPA_1000XPAUSE_ASYM)
1911 lpa |= LPA_PAUSE_ASYM;
1912 }
1913
1914 sky2->flow_status = FC_NONE;
1915 if (advert & ADVERTISE_PAUSE_CAP) {
1916 if (lpa & LPA_PAUSE_CAP)
1917 sky2->flow_status = FC_BOTH;
1918 else if (advert & ADVERTISE_PAUSE_ASYM)
1919 sky2->flow_status = FC_RX;
1920 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1921 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1922 sky2->flow_status = FC_TX;
1923 }
1924
1925 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1926 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1927 sky2->flow_status = FC_NONE;
1928
1929 if (sky2->flow_status & FC_TX)
1930 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1931 else
1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1933
1934 return 0;
1935 }
1936
1937 /* Interrupt from PHY */
1938 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1939 {
1940 struct net_device *dev = hw->dev[port];
1941 struct sky2_port *sky2 = netdev_priv(dev);
1942 u16 istatus, phystat;
1943
1944 if (!netif_running(dev))
1945 return;
1946
1947 spin_lock(&sky2->phy_lock);
1948 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1949 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1950
1951 if (netif_msg_intr(sky2))
1952 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1953 sky2->netdev->name, istatus, phystat);
1954
1955 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1956 if (sky2_autoneg_done(sky2, phystat) == 0)
1957 sky2_link_up(sky2);
1958 goto out;
1959 }
1960
1961 if (istatus & PHY_M_IS_LSP_CHANGE)
1962 sky2->speed = sky2_phy_speed(hw, phystat);
1963
1964 if (istatus & PHY_M_IS_DUP_CHANGE)
1965 sky2->duplex =
1966 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1967
1968 if (istatus & PHY_M_IS_LST_CHANGE) {
1969 if (phystat & PHY_M_PS_LINK_UP)
1970 sky2_link_up(sky2);
1971 else
1972 sky2_link_down(sky2);
1973 }
1974 out:
1975 spin_unlock(&sky2->phy_lock);
1976 }
1977
1978 /* Transmit timeout is only called if we are running, carrier is up
1979 * and tx queue is full (stopped).
1980 */
1981 static void sky2_tx_timeout(struct net_device *dev)
1982 {
1983 struct sky2_port *sky2 = netdev_priv(dev);
1984 struct sky2_hw *hw = sky2->hw;
1985
1986 if (netif_msg_timer(sky2))
1987 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1988
1989 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1990 dev->name, sky2->tx_cons, sky2->tx_prod,
1991 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1992 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1993
1994 /* can't restart safely under softirq */
1995 schedule_work(&hw->restart_work);
1996 }
1997
1998 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1999 {
2000 struct sky2_port *sky2 = netdev_priv(dev);
2001 struct sky2_hw *hw = sky2->hw;
2002 unsigned port = sky2->port;
2003 int err;
2004 u16 ctl, mode;
2005 u32 imask;
2006
2007 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2008 return -EINVAL;
2009
2010 if (new_mtu > ETH_DATA_LEN &&
2011 (hw->chip_id == CHIP_ID_YUKON_FE ||
2012 hw->chip_id == CHIP_ID_YUKON_FE_P))
2013 return -EINVAL;
2014
2015 if (!netif_running(dev)) {
2016 dev->mtu = new_mtu;
2017 return 0;
2018 }
2019
2020 imask = sky2_read32(hw, B0_IMSK);
2021 sky2_write32(hw, B0_IMSK, 0);
2022
2023 dev->trans_start = jiffies; /* prevent tx timeout */
2024 netif_stop_queue(dev);
2025 napi_disable(&hw->napi);
2026
2027 synchronize_irq(hw->pdev->irq);
2028
2029 if (sky2_read8(hw, B2_E_0) == 0)
2030 sky2_set_tx_stfwd(hw, port);
2031
2032 ctl = gma_read16(hw, port, GM_GP_CTRL);
2033 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2034 sky2_rx_stop(sky2);
2035 sky2_rx_clean(sky2);
2036
2037 dev->mtu = new_mtu;
2038
2039 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2040 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2041
2042 if (dev->mtu > ETH_DATA_LEN)
2043 mode |= GM_SMOD_JUMBO_ENA;
2044
2045 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2046
2047 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2048
2049 err = sky2_rx_start(sky2);
2050 sky2_write32(hw, B0_IMSK, imask);
2051
2052 sky2_read32(hw, B0_Y2_SP_LISR);
2053 napi_enable(&hw->napi);
2054
2055 if (err)
2056 dev_close(dev);
2057 else {
2058 gma_write16(hw, port, GM_GP_CTRL, ctl);
2059
2060 netif_wake_queue(dev);
2061 }
2062
2063 return err;
2064 }
2065
2066 /* For small just reuse existing skb for next receive */
2067 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2068 const struct rx_ring_info *re,
2069 unsigned length)
2070 {
2071 struct sk_buff *skb;
2072
2073 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2074 if (likely(skb)) {
2075 skb_reserve(skb, 2);
2076 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2077 length, PCI_DMA_FROMDEVICE);
2078 skb_copy_from_linear_data(re->skb, skb->data, length);
2079 skb->ip_summed = re->skb->ip_summed;
2080 skb->csum = re->skb->csum;
2081 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2082 length, PCI_DMA_FROMDEVICE);
2083 re->skb->ip_summed = CHECKSUM_NONE;
2084 skb_put(skb, length);
2085 }
2086 return skb;
2087 }
2088
2089 /* Adjust length of skb with fragments to match received data */
2090 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2091 unsigned int length)
2092 {
2093 int i, num_frags;
2094 unsigned int size;
2095
2096 /* put header into skb */
2097 size = min(length, hdr_space);
2098 skb->tail += size;
2099 skb->len += size;
2100 length -= size;
2101
2102 num_frags = skb_shinfo(skb)->nr_frags;
2103 for (i = 0; i < num_frags; i++) {
2104 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2105
2106 if (length == 0) {
2107 /* don't need this page */
2108 __free_page(frag->page);
2109 --skb_shinfo(skb)->nr_frags;
2110 } else {
2111 size = min(length, (unsigned) PAGE_SIZE);
2112
2113 frag->size = size;
2114 skb->data_len += size;
2115 skb->truesize += size;
2116 skb->len += size;
2117 length -= size;
2118 }
2119 }
2120 }
2121
2122 /* Normal packet - take skb from ring element and put in a new one */
2123 static struct sk_buff *receive_new(struct sky2_port *sky2,
2124 struct rx_ring_info *re,
2125 unsigned int length)
2126 {
2127 struct sk_buff *skb, *nskb;
2128 unsigned hdr_space = sky2->rx_data_size;
2129
2130 /* Don't be tricky about reusing pages (yet) */
2131 nskb = sky2_rx_alloc(sky2);
2132 if (unlikely(!nskb))
2133 return NULL;
2134
2135 skb = re->skb;
2136 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2137
2138 prefetch(skb->data);
2139 re->skb = nskb;
2140 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2141
2142 if (skb_shinfo(skb)->nr_frags)
2143 skb_put_frags(skb, hdr_space, length);
2144 else
2145 skb_put(skb, length);
2146 return skb;
2147 }
2148
2149 /*
2150 * Receive one packet.
2151 * For larger packets, get new buffer.
2152 */
2153 static struct sk_buff *sky2_receive(struct net_device *dev,
2154 u16 length, u32 status)
2155 {
2156 struct sky2_port *sky2 = netdev_priv(dev);
2157 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2158 struct sk_buff *skb = NULL;
2159 u16 count = (status & GMR_FS_LEN) >> 16;
2160
2161 #ifdef SKY2_VLAN_TAG_USED
2162 /* Account for vlan tag */
2163 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2164 count -= VLAN_HLEN;
2165 #endif
2166
2167 if (unlikely(netif_msg_rx_status(sky2)))
2168 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2169 dev->name, sky2->rx_next, status, length);
2170
2171 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2172 prefetch(sky2->rx_ring + sky2->rx_next);
2173
2174 /* This chip has hardware problems that generates bogus status.
2175 * So do only marginal checking and expect higher level protocols
2176 * to handle crap frames.
2177 */
2178 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2179 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2180 length != count)
2181 goto okay;
2182
2183 if (status & GMR_FS_ANY_ERR)
2184 goto error;
2185
2186 if (!(status & GMR_FS_RX_OK))
2187 goto resubmit;
2188
2189 /* if length reported by DMA does not match PHY, packet was truncated */
2190 if (length != count)
2191 goto len_error;
2192
2193 okay:
2194 if (length < copybreak)
2195 skb = receive_copy(sky2, re, length);
2196 else
2197 skb = receive_new(sky2, re, length);
2198 resubmit:
2199 sky2_rx_submit(sky2, re);
2200
2201 return skb;
2202
2203 len_error:
2204 /* Truncation of overlength packets
2205 causes PHY length to not match MAC length */
2206 ++dev->stats.rx_length_errors;
2207 if (netif_msg_rx_err(sky2) && net_ratelimit())
2208 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2209 dev->name, status, length);
2210 goto resubmit;
2211
2212 error:
2213 ++dev->stats.rx_errors;
2214 if (status & GMR_FS_RX_FF_OV) {
2215 dev->stats.rx_over_errors++;
2216 goto resubmit;
2217 }
2218
2219 if (netif_msg_rx_err(sky2) && net_ratelimit())
2220 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2221 dev->name, status, length);
2222
2223 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2224 dev->stats.rx_length_errors++;
2225 if (status & GMR_FS_FRAGMENT)
2226 dev->stats.rx_frame_errors++;
2227 if (status & GMR_FS_CRC_ERR)
2228 dev->stats.rx_crc_errors++;
2229
2230 goto resubmit;
2231 }
2232
2233 /* Transmit complete */
2234 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2235 {
2236 struct sky2_port *sky2 = netdev_priv(dev);
2237
2238 if (netif_running(dev)) {
2239 netif_tx_lock(dev);
2240 sky2_tx_complete(sky2, last);
2241 netif_tx_unlock(dev);
2242 }
2243 }
2244
2245 /* Process status response ring */
2246 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2247 {
2248 int work_done = 0;
2249 unsigned rx[2] = { 0, 0 };
2250
2251 rmb();
2252 do {
2253 struct sky2_port *sky2;
2254 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2255 unsigned port;
2256 struct net_device *dev;
2257 struct sk_buff *skb;
2258 u32 status;
2259 u16 length;
2260 u8 opcode = le->opcode;
2261
2262 if (!(opcode & HW_OWNER))
2263 break;
2264
2265 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2266
2267 port = le->css & CSS_LINK_BIT;
2268 dev = hw->dev[port];
2269 sky2 = netdev_priv(dev);
2270 length = le16_to_cpu(le->length);
2271 status = le32_to_cpu(le->status);
2272
2273 le->opcode = 0;
2274 switch (opcode & ~HW_OWNER) {
2275 case OP_RXSTAT:
2276 ++rx[port];
2277 skb = sky2_receive(dev, length, status);
2278 if (unlikely(!skb)) {
2279 dev->stats.rx_dropped++;
2280 break;
2281 }
2282
2283 /* This chip reports checksum status differently */
2284 if (hw->flags & SKY2_HW_NEW_LE) {
2285 if (sky2->rx_csum &&
2286 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2287 (le->css & CSS_TCPUDPCSOK))
2288 skb->ip_summed = CHECKSUM_UNNECESSARY;
2289 else
2290 skb->ip_summed = CHECKSUM_NONE;
2291 }
2292
2293 skb->protocol = eth_type_trans(skb, dev);
2294 dev->stats.rx_packets++;
2295 dev->stats.rx_bytes += skb->len;
2296 dev->last_rx = jiffies;
2297
2298 #ifdef SKY2_VLAN_TAG_USED
2299 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2300 vlan_hwaccel_receive_skb(skb,
2301 sky2->vlgrp,
2302 be16_to_cpu(sky2->rx_tag));
2303 } else
2304 #endif
2305 netif_receive_skb(skb);
2306
2307 /* Stop after net poll weight */
2308 if (++work_done >= to_do)
2309 goto exit_loop;
2310 break;
2311
2312 #ifdef SKY2_VLAN_TAG_USED
2313 case OP_RXVLAN:
2314 sky2->rx_tag = length;
2315 break;
2316
2317 case OP_RXCHKSVLAN:
2318 sky2->rx_tag = length;
2319 /* fall through */
2320 #endif
2321 case OP_RXCHKS:
2322 if (!sky2->rx_csum)
2323 break;
2324
2325 /* If this happens then driver assuming wrong format */
2326 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2327 if (net_ratelimit())
2328 printk(KERN_NOTICE "%s: unexpected"
2329 " checksum status\n",
2330 dev->name);
2331 break;
2332 }
2333
2334 /* Both checksum counters are programmed to start at
2335 * the same offset, so unless there is a problem they
2336 * should match. This failure is an early indication that
2337 * hardware receive checksumming won't work.
2338 */
2339 if (likely(status >> 16 == (status & 0xffff))) {
2340 skb = sky2->rx_ring[sky2->rx_next].skb;
2341 skb->ip_summed = CHECKSUM_COMPLETE;
2342 skb->csum = status & 0xffff;
2343 } else {
2344 printk(KERN_NOTICE PFX "%s: hardware receive "
2345 "checksum problem (status = %#x)\n",
2346 dev->name, status);
2347 sky2->rx_csum = 0;
2348 sky2_write32(sky2->hw,
2349 Q_ADDR(rxqaddr[port], Q_CSR),
2350 BMU_DIS_RX_CHKSUM);
2351 }
2352 break;
2353
2354 case OP_TXINDEXLE:
2355 /* TX index reports status for both ports */
2356 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2357 sky2_tx_done(hw->dev[0], status & 0xfff);
2358 if (hw->dev[1])
2359 sky2_tx_done(hw->dev[1],
2360 ((status >> 24) & 0xff)
2361 | (u16)(length & 0xf) << 8);
2362 break;
2363
2364 default:
2365 if (net_ratelimit())
2366 printk(KERN_WARNING PFX
2367 "unknown status opcode 0x%x\n", opcode);
2368 }
2369 } while (hw->st_idx != idx);
2370
2371 /* Fully processed status ring so clear irq */
2372 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2373
2374 exit_loop:
2375 if (rx[0])
2376 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2377
2378 if (rx[1])
2379 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2380
2381 return work_done;
2382 }
2383
2384 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2385 {
2386 struct net_device *dev = hw->dev[port];
2387
2388 if (net_ratelimit())
2389 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2390 dev->name, status);
2391
2392 if (status & Y2_IS_PAR_RD1) {
2393 if (net_ratelimit())
2394 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2395 dev->name);
2396 /* Clear IRQ */
2397 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2398 }
2399
2400 if (status & Y2_IS_PAR_WR1) {
2401 if (net_ratelimit())
2402 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2403 dev->name);
2404
2405 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2406 }
2407
2408 if (status & Y2_IS_PAR_MAC1) {
2409 if (net_ratelimit())
2410 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2411 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2412 }
2413
2414 if (status & Y2_IS_PAR_RX1) {
2415 if (net_ratelimit())
2416 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2417 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2418 }
2419
2420 if (status & Y2_IS_TCP_TXA1) {
2421 if (net_ratelimit())
2422 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2423 dev->name);
2424 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2425 }
2426 }
2427
2428 static void sky2_hw_intr(struct sky2_hw *hw)
2429 {
2430 struct pci_dev *pdev = hw->pdev;
2431 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2432 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2433
2434 status &= hwmsk;
2435
2436 if (status & Y2_IS_TIST_OV)
2437 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2438
2439 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2440 u16 pci_err;
2441
2442 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2443 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2444 if (net_ratelimit())
2445 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2446 pci_err);
2447
2448 sky2_pci_write16(hw, PCI_STATUS,
2449 pci_err | PCI_STATUS_ERROR_BITS);
2450 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2451 }
2452
2453 if (status & Y2_IS_PCI_EXP) {
2454 /* PCI-Express uncorrectable Error occurred */
2455 u32 err;
2456
2457 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2458 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2459 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2460 0xfffffffful);
2461 if (net_ratelimit())
2462 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2463
2464 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2465 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2466 }
2467
2468 if (status & Y2_HWE_L1_MASK)
2469 sky2_hw_error(hw, 0, status);
2470 status >>= 8;
2471 if (status & Y2_HWE_L1_MASK)
2472 sky2_hw_error(hw, 1, status);
2473 }
2474
2475 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2476 {
2477 struct net_device *dev = hw->dev[port];
2478 struct sky2_port *sky2 = netdev_priv(dev);
2479 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2480
2481 if (netif_msg_intr(sky2))
2482 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2483 dev->name, status);
2484
2485 if (status & GM_IS_RX_CO_OV)
2486 gma_read16(hw, port, GM_RX_IRQ_SRC);
2487
2488 if (status & GM_IS_TX_CO_OV)
2489 gma_read16(hw, port, GM_TX_IRQ_SRC);
2490
2491 if (status & GM_IS_RX_FF_OR) {
2492 ++dev->stats.rx_fifo_errors;
2493 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2494 }
2495
2496 if (status & GM_IS_TX_FF_UR) {
2497 ++dev->stats.tx_fifo_errors;
2498 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2499 }
2500 }
2501
2502 /* This should never happen it is a bug. */
2503 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2504 u16 q, unsigned ring_size)
2505 {
2506 struct net_device *dev = hw->dev[port];
2507 struct sky2_port *sky2 = netdev_priv(dev);
2508 unsigned idx;
2509 const u64 *le = (q == Q_R1 || q == Q_R2)
2510 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2511
2512 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2513 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2514 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2515 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2516
2517 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2518 }
2519
2520 static int sky2_rx_hung(struct net_device *dev)
2521 {
2522 struct sky2_port *sky2 = netdev_priv(dev);
2523 struct sky2_hw *hw = sky2->hw;
2524 unsigned port = sky2->port;
2525 unsigned rxq = rxqaddr[port];
2526 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2527 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2528 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2529 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2530
2531 /* If idle and MAC or PCI is stuck */
2532 if (sky2->check.last == dev->last_rx &&
2533 ((mac_rp == sky2->check.mac_rp &&
2534 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2535 /* Check if the PCI RX hang */
2536 (fifo_rp == sky2->check.fifo_rp &&
2537 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2538 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2539 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2540 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2541 return 1;
2542 } else {
2543 sky2->check.last = dev->last_rx;
2544 sky2->check.mac_rp = mac_rp;
2545 sky2->check.mac_lev = mac_lev;
2546 sky2->check.fifo_rp = fifo_rp;
2547 sky2->check.fifo_lev = fifo_lev;
2548 return 0;
2549 }
2550 }
2551
2552 static void sky2_watchdog(unsigned long arg)
2553 {
2554 struct sky2_hw *hw = (struct sky2_hw *) arg;
2555
2556 /* Check for lost IRQ once a second */
2557 if (sky2_read32(hw, B0_ISRC)) {
2558 napi_schedule(&hw->napi);
2559 } else {
2560 int i, active = 0;
2561
2562 for (i = 0; i < hw->ports; i++) {
2563 struct net_device *dev = hw->dev[i];
2564 if (!netif_running(dev))
2565 continue;
2566 ++active;
2567
2568 /* For chips with Rx FIFO, check if stuck */
2569 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2570 sky2_rx_hung(dev)) {
2571 pr_info(PFX "%s: receiver hang detected\n",
2572 dev->name);
2573 schedule_work(&hw->restart_work);
2574 return;
2575 }
2576 }
2577
2578 if (active == 0)
2579 return;
2580 }
2581
2582 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2583 }
2584
2585 /* Hardware/software error handling */
2586 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2587 {
2588 if (net_ratelimit())
2589 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2590
2591 if (status & Y2_IS_HW_ERR)
2592 sky2_hw_intr(hw);
2593
2594 if (status & Y2_IS_IRQ_MAC1)
2595 sky2_mac_intr(hw, 0);
2596
2597 if (status & Y2_IS_IRQ_MAC2)
2598 sky2_mac_intr(hw, 1);
2599
2600 if (status & Y2_IS_CHK_RX1)
2601 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2602
2603 if (status & Y2_IS_CHK_RX2)
2604 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2605
2606 if (status & Y2_IS_CHK_TXA1)
2607 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2608
2609 if (status & Y2_IS_CHK_TXA2)
2610 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2611 }
2612
2613 static int sky2_poll(struct napi_struct *napi, int work_limit)
2614 {
2615 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2616 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2617 int work_done = 0;
2618 u16 idx;
2619
2620 if (unlikely(status & Y2_IS_ERROR))
2621 sky2_err_intr(hw, status);
2622
2623 if (status & Y2_IS_IRQ_PHY1)
2624 sky2_phy_intr(hw, 0);
2625
2626 if (status & Y2_IS_IRQ_PHY2)
2627 sky2_phy_intr(hw, 1);
2628
2629 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2630 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2631
2632 if (work_done >= work_limit)
2633 goto done;
2634 }
2635
2636 /* Bug/Errata workaround?
2637 * Need to kick the TX irq moderation timer.
2638 */
2639 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2640 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2641 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2642 }
2643 napi_complete(napi);
2644 sky2_read32(hw, B0_Y2_SP_LISR);
2645 done:
2646
2647 return work_done;
2648 }
2649
2650 static irqreturn_t sky2_intr(int irq, void *dev_id)
2651 {
2652 struct sky2_hw *hw = dev_id;
2653 u32 status;
2654
2655 /* Reading this mask interrupts as side effect */
2656 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2657 if (status == 0 || status == ~0)
2658 return IRQ_NONE;
2659
2660 prefetch(&hw->st_le[hw->st_idx]);
2661
2662 napi_schedule(&hw->napi);
2663
2664 return IRQ_HANDLED;
2665 }
2666
2667 #ifdef CONFIG_NET_POLL_CONTROLLER
2668 static void sky2_netpoll(struct net_device *dev)
2669 {
2670 struct sky2_port *sky2 = netdev_priv(dev);
2671
2672 napi_schedule(&sky2->hw->napi);
2673 }
2674 #endif
2675
2676 /* Chip internal frequency for clock calculations */
2677 static u32 sky2_mhz(const struct sky2_hw *hw)
2678 {
2679 switch (hw->chip_id) {
2680 case CHIP_ID_YUKON_EC:
2681 case CHIP_ID_YUKON_EC_U:
2682 case CHIP_ID_YUKON_EX:
2683 case CHIP_ID_YUKON_SUPR:
2684 return 125;
2685
2686 case CHIP_ID_YUKON_FE:
2687 return 100;
2688
2689 case CHIP_ID_YUKON_FE_P:
2690 return 50;
2691
2692 case CHIP_ID_YUKON_XL:
2693 return 156;
2694
2695 default:
2696 BUG();
2697 }
2698 }
2699
2700 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2701 {
2702 return sky2_mhz(hw) * us;
2703 }
2704
2705 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2706 {
2707 return clk / sky2_mhz(hw);
2708 }
2709
2710
2711 static int __devinit sky2_init(struct sky2_hw *hw)
2712 {
2713 u8 t8;
2714
2715 /* Enable all clocks and check for bad PCI access */
2716 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2717
2718 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2719
2720 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2721 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2722
2723 switch(hw->chip_id) {
2724 case CHIP_ID_YUKON_XL:
2725 hw->flags = SKY2_HW_GIGABIT
2726 | SKY2_HW_NEWER_PHY;
2727 if (hw->chip_rev < 3)
2728 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2729
2730 break;
2731
2732 case CHIP_ID_YUKON_EC_U:
2733 hw->flags = SKY2_HW_GIGABIT
2734 | SKY2_HW_NEWER_PHY
2735 | SKY2_HW_ADV_POWER_CTL;
2736 break;
2737
2738 case CHIP_ID_YUKON_EX:
2739 hw->flags = SKY2_HW_GIGABIT
2740 | SKY2_HW_NEWER_PHY
2741 | SKY2_HW_NEW_LE
2742 | SKY2_HW_ADV_POWER_CTL;
2743
2744 /* New transmit checksum */
2745 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2746 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2747 break;
2748
2749 case CHIP_ID_YUKON_EC:
2750 /* This rev is really old, and requires untested workarounds */
2751 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2752 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2753 return -EOPNOTSUPP;
2754 }
2755 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2756 break;
2757
2758 case CHIP_ID_YUKON_FE:
2759 break;
2760
2761 case CHIP_ID_YUKON_FE_P:
2762 hw->flags = SKY2_HW_NEWER_PHY
2763 | SKY2_HW_NEW_LE
2764 | SKY2_HW_AUTO_TX_SUM
2765 | SKY2_HW_ADV_POWER_CTL;
2766 break;
2767
2768 case CHIP_ID_YUKON_SUPR:
2769 hw->flags = SKY2_HW_GIGABIT
2770 | SKY2_HW_NEWER_PHY
2771 | SKY2_HW_NEW_LE
2772 | SKY2_HW_AUTO_TX_SUM
2773 | SKY2_HW_ADV_POWER_CTL;
2774 break;
2775
2776 default:
2777 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2778 hw->chip_id);
2779 return -EOPNOTSUPP;
2780 }
2781
2782 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2783 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2784 hw->flags |= SKY2_HW_FIBRE_PHY;
2785
2786
2787 hw->ports = 1;
2788 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2789 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2790 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2791 ++hw->ports;
2792 }
2793
2794 return 0;
2795 }
2796
2797 static void sky2_reset(struct sky2_hw *hw)
2798 {
2799 struct pci_dev *pdev = hw->pdev;
2800 u16 status;
2801 int i, cap;
2802 u32 hwe_mask = Y2_HWE_ALL_MASK;
2803
2804 /* disable ASF */
2805 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2806 status = sky2_read16(hw, HCU_CCSR);
2807 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2808 HCU_CCSR_UC_STATE_MSK);
2809 sky2_write16(hw, HCU_CCSR, status);
2810 } else
2811 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2812 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2813
2814 /* do a SW reset */
2815 sky2_write8(hw, B0_CTST, CS_RST_SET);
2816 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2817
2818 /* allow writes to PCI config */
2819 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2820
2821 /* clear PCI errors, if any */
2822 status = sky2_pci_read16(hw, PCI_STATUS);
2823 status |= PCI_STATUS_ERROR_BITS;
2824 sky2_pci_write16(hw, PCI_STATUS, status);
2825
2826 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2827
2828 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2829 if (cap) {
2830 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2831 0xfffffffful);
2832
2833 /* If error bit is stuck on ignore it */
2834 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2835 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2836 else
2837 hwe_mask |= Y2_IS_PCI_EXP;
2838 }
2839
2840 sky2_power_on(hw);
2841 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2842
2843 for (i = 0; i < hw->ports; i++) {
2844 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2845 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2846
2847 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2848 hw->chip_id == CHIP_ID_YUKON_SUPR)
2849 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2850 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2851 | GMC_BYP_RETR_ON);
2852 }
2853
2854 /* Clear I2C IRQ noise */
2855 sky2_write32(hw, B2_I2C_IRQ, 1);
2856
2857 /* turn off hardware timer (unused) */
2858 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2859 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2860
2861 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2862
2863 /* Turn off descriptor polling */
2864 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2865
2866 /* Turn off receive timestamp */
2867 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2868 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2869
2870 /* enable the Tx Arbiters */
2871 for (i = 0; i < hw->ports; i++)
2872 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2873
2874 /* Initialize ram interface */
2875 for (i = 0; i < hw->ports; i++) {
2876 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2877
2878 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2879 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2880 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2881 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2882 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2883 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2884 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2885 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2886 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2887 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2888 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2889 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2890 }
2891
2892 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2893
2894 for (i = 0; i < hw->ports; i++)
2895 sky2_gmac_reset(hw, i);
2896
2897 memset(hw->st_le, 0, STATUS_LE_BYTES);
2898 hw->st_idx = 0;
2899
2900 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2901 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2902
2903 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2904 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2905
2906 /* Set the list last index */
2907 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2908
2909 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2910 sky2_write8(hw, STAT_FIFO_WM, 16);
2911
2912 /* set Status-FIFO ISR watermark */
2913 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2914 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2915 else
2916 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2917
2918 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2919 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2920 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2921
2922 /* enable status unit */
2923 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2924
2925 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2926 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2927 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2928 }
2929
2930 static void sky2_restart(struct work_struct *work)
2931 {
2932 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2933 struct net_device *dev;
2934 int i, err;
2935
2936 rtnl_lock();
2937 for (i = 0; i < hw->ports; i++) {
2938 dev = hw->dev[i];
2939 if (netif_running(dev))
2940 sky2_down(dev);
2941 }
2942
2943 napi_disable(&hw->napi);
2944 sky2_write32(hw, B0_IMSK, 0);
2945 sky2_reset(hw);
2946 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2947 napi_enable(&hw->napi);
2948
2949 for (i = 0; i < hw->ports; i++) {
2950 dev = hw->dev[i];
2951 if (netif_running(dev)) {
2952 err = sky2_up(dev);
2953 if (err) {
2954 printk(KERN_INFO PFX "%s: could not restart %d\n",
2955 dev->name, err);
2956 dev_close(dev);
2957 }
2958 }
2959 }
2960
2961 rtnl_unlock();
2962 }
2963
2964 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2965 {
2966 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2967 }
2968
2969 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2970 {
2971 const struct sky2_port *sky2 = netdev_priv(dev);
2972
2973 wol->supported = sky2_wol_supported(sky2->hw);
2974 wol->wolopts = sky2->wol;
2975 }
2976
2977 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2978 {
2979 struct sky2_port *sky2 = netdev_priv(dev);
2980 struct sky2_hw *hw = sky2->hw;
2981
2982 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2983 return -EOPNOTSUPP;
2984
2985 sky2->wol = wol->wolopts;
2986
2987 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2988 hw->chip_id == CHIP_ID_YUKON_EX ||
2989 hw->chip_id == CHIP_ID_YUKON_FE_P)
2990 sky2_write32(hw, B0_CTST, sky2->wol
2991 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2992
2993 if (!netif_running(dev))
2994 sky2_wol_init(sky2);
2995 return 0;
2996 }
2997
2998 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2999 {
3000 if (sky2_is_copper(hw)) {
3001 u32 modes = SUPPORTED_10baseT_Half
3002 | SUPPORTED_10baseT_Full
3003 | SUPPORTED_100baseT_Half
3004 | SUPPORTED_100baseT_Full
3005 | SUPPORTED_Autoneg | SUPPORTED_TP;
3006
3007 if (hw->flags & SKY2_HW_GIGABIT)
3008 modes |= SUPPORTED_1000baseT_Half
3009 | SUPPORTED_1000baseT_Full;
3010 return modes;
3011 } else
3012 return SUPPORTED_1000baseT_Half
3013 | SUPPORTED_1000baseT_Full
3014 | SUPPORTED_Autoneg
3015 | SUPPORTED_FIBRE;
3016 }
3017
3018 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3019 {
3020 struct sky2_port *sky2 = netdev_priv(dev);
3021 struct sky2_hw *hw = sky2->hw;
3022
3023 ecmd->transceiver = XCVR_INTERNAL;
3024 ecmd->supported = sky2_supported_modes(hw);
3025 ecmd->phy_address = PHY_ADDR_MARV;
3026 if (sky2_is_copper(hw)) {
3027 ecmd->port = PORT_TP;
3028 ecmd->speed = sky2->speed;
3029 } else {
3030 ecmd->speed = SPEED_1000;
3031 ecmd->port = PORT_FIBRE;
3032 }
3033
3034 ecmd->advertising = sky2->advertising;
3035 ecmd->autoneg = sky2->autoneg;
3036 ecmd->duplex = sky2->duplex;
3037 return 0;
3038 }
3039
3040 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3041 {
3042 struct sky2_port *sky2 = netdev_priv(dev);
3043 const struct sky2_hw *hw = sky2->hw;
3044 u32 supported = sky2_supported_modes(hw);
3045
3046 if (ecmd->autoneg == AUTONEG_ENABLE) {
3047 ecmd->advertising = supported;
3048 sky2->duplex = -1;
3049 sky2->speed = -1;
3050 } else {
3051 u32 setting;
3052
3053 switch (ecmd->speed) {
3054 case SPEED_1000:
3055 if (ecmd->duplex == DUPLEX_FULL)
3056 setting = SUPPORTED_1000baseT_Full;
3057 else if (ecmd->duplex == DUPLEX_HALF)
3058 setting = SUPPORTED_1000baseT_Half;
3059 else
3060 return -EINVAL;
3061 break;
3062 case SPEED_100:
3063 if (ecmd->duplex == DUPLEX_FULL)
3064 setting = SUPPORTED_100baseT_Full;
3065 else if (ecmd->duplex == DUPLEX_HALF)
3066 setting = SUPPORTED_100baseT_Half;
3067 else
3068 return -EINVAL;
3069 break;
3070
3071 case SPEED_10:
3072 if (ecmd->duplex == DUPLEX_FULL)
3073 setting = SUPPORTED_10baseT_Full;
3074 else if (ecmd->duplex == DUPLEX_HALF)
3075 setting = SUPPORTED_10baseT_Half;
3076 else
3077 return -EINVAL;
3078 break;
3079 default:
3080 return -EINVAL;
3081 }
3082
3083 if ((setting & supported) == 0)
3084 return -EINVAL;
3085
3086 sky2->speed = ecmd->speed;
3087 sky2->duplex = ecmd->duplex;
3088 }
3089
3090 sky2->autoneg = ecmd->autoneg;
3091 sky2->advertising = ecmd->advertising;
3092
3093 if (netif_running(dev)) {
3094 sky2_phy_reinit(sky2);
3095 sky2_set_multicast(dev);
3096 }
3097
3098 return 0;
3099 }
3100
3101 static void sky2_get_drvinfo(struct net_device *dev,
3102 struct ethtool_drvinfo *info)
3103 {
3104 struct sky2_port *sky2 = netdev_priv(dev);
3105
3106 strcpy(info->driver, DRV_NAME);
3107 strcpy(info->version, DRV_VERSION);
3108 strcpy(info->fw_version, "N/A");
3109 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3110 }
3111
3112 static const struct sky2_stat {
3113 char name[ETH_GSTRING_LEN];
3114 u16 offset;
3115 } sky2_stats[] = {
3116 { "tx_bytes", GM_TXO_OK_HI },
3117 { "rx_bytes", GM_RXO_OK_HI },
3118 { "tx_broadcast", GM_TXF_BC_OK },
3119 { "rx_broadcast", GM_RXF_BC_OK },
3120 { "tx_multicast", GM_TXF_MC_OK },
3121 { "rx_multicast", GM_RXF_MC_OK },
3122 { "tx_unicast", GM_TXF_UC_OK },
3123 { "rx_unicast", GM_RXF_UC_OK },
3124 { "tx_mac_pause", GM_TXF_MPAUSE },
3125 { "rx_mac_pause", GM_RXF_MPAUSE },
3126 { "collisions", GM_TXF_COL },
3127 { "late_collision",GM_TXF_LAT_COL },
3128 { "aborted", GM_TXF_ABO_COL },
3129 { "single_collisions", GM_TXF_SNG_COL },
3130 { "multi_collisions", GM_TXF_MUL_COL },
3131
3132 { "rx_short", GM_RXF_SHT },
3133 { "rx_runt", GM_RXE_FRAG },
3134 { "rx_64_byte_packets", GM_RXF_64B },
3135 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3136 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3137 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3138 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3139 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3140 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3141 { "rx_too_long", GM_RXF_LNG_ERR },
3142 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3143 { "rx_jabber", GM_RXF_JAB_PKT },
3144 { "rx_fcs_error", GM_RXF_FCS_ERR },
3145
3146 { "tx_64_byte_packets", GM_TXF_64B },
3147 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3148 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3149 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3150 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3151 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3152 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3153 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3154 };
3155
3156 static u32 sky2_get_rx_csum(struct net_device *dev)
3157 {
3158 struct sky2_port *sky2 = netdev_priv(dev);
3159
3160 return sky2->rx_csum;
3161 }
3162
3163 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3164 {
3165 struct sky2_port *sky2 = netdev_priv(dev);
3166
3167 sky2->rx_csum = data;
3168
3169 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3170 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3171
3172 return 0;
3173 }
3174
3175 static u32 sky2_get_msglevel(struct net_device *netdev)
3176 {
3177 struct sky2_port *sky2 = netdev_priv(netdev);
3178 return sky2->msg_enable;
3179 }
3180
3181 static int sky2_nway_reset(struct net_device *dev)
3182 {
3183 struct sky2_port *sky2 = netdev_priv(dev);
3184
3185 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3186 return -EINVAL;
3187
3188 sky2_phy_reinit(sky2);
3189 sky2_set_multicast(dev);
3190
3191 return 0;
3192 }
3193
3194 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3195 {
3196 struct sky2_hw *hw = sky2->hw;
3197 unsigned port = sky2->port;
3198 int i;
3199
3200 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3201 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3202 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3203 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3204
3205 for (i = 2; i < count; i++)
3206 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3207 }
3208
3209 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3210 {
3211 struct sky2_port *sky2 = netdev_priv(netdev);
3212 sky2->msg_enable = value;
3213 }
3214
3215 static int sky2_get_sset_count(struct net_device *dev, int sset)
3216 {
3217 switch (sset) {
3218 case ETH_SS_STATS:
3219 return ARRAY_SIZE(sky2_stats);
3220 default:
3221 return -EOPNOTSUPP;
3222 }
3223 }
3224
3225 static void sky2_get_ethtool_stats(struct net_device *dev,
3226 struct ethtool_stats *stats, u64 * data)
3227 {
3228 struct sky2_port *sky2 = netdev_priv(dev);
3229
3230 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3231 }
3232
3233 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3234 {
3235 int i;
3236
3237 switch (stringset) {
3238 case ETH_SS_STATS:
3239 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3240 memcpy(data + i * ETH_GSTRING_LEN,
3241 sky2_stats[i].name, ETH_GSTRING_LEN);
3242 break;
3243 }
3244 }
3245
3246 static int sky2_set_mac_address(struct net_device *dev, void *p)
3247 {
3248 struct sky2_port *sky2 = netdev_priv(dev);
3249 struct sky2_hw *hw = sky2->hw;
3250 unsigned port = sky2->port;
3251 const struct sockaddr *addr = p;
3252
3253 if (!is_valid_ether_addr(addr->sa_data))
3254 return -EADDRNOTAVAIL;
3255
3256 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3257 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3258 dev->dev_addr, ETH_ALEN);
3259 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3260 dev->dev_addr, ETH_ALEN);
3261
3262 /* virtual address for data */
3263 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3264
3265 /* physical address: used for pause frames */
3266 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3267
3268 return 0;
3269 }
3270
3271 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3272 {
3273 u32 bit;
3274
3275 bit = ether_crc(ETH_ALEN, addr) & 63;
3276 filter[bit >> 3] |= 1 << (bit & 7);
3277 }
3278
3279 static void sky2_set_multicast(struct net_device *dev)
3280 {
3281 struct sky2_port *sky2 = netdev_priv(dev);
3282 struct sky2_hw *hw = sky2->hw;
3283 unsigned port = sky2->port;
3284 struct dev_mc_list *list = dev->mc_list;
3285 u16 reg;
3286 u8 filter[8];
3287 int rx_pause;
3288 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3289
3290 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3291 memset(filter, 0, sizeof(filter));
3292
3293 reg = gma_read16(hw, port, GM_RX_CTRL);
3294 reg |= GM_RXCR_UCF_ENA;
3295
3296 if (dev->flags & IFF_PROMISC) /* promiscuous */
3297 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3298 else if (dev->flags & IFF_ALLMULTI)
3299 memset(filter, 0xff, sizeof(filter));
3300 else if (dev->mc_count == 0 && !rx_pause)
3301 reg &= ~GM_RXCR_MCF_ENA;
3302 else {
3303 int i;
3304 reg |= GM_RXCR_MCF_ENA;
3305
3306 if (rx_pause)
3307 sky2_add_filter(filter, pause_mc_addr);
3308
3309 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3310 sky2_add_filter(filter, list->dmi_addr);
3311 }
3312
3313 gma_write16(hw, port, GM_MC_ADDR_H1,
3314 (u16) filter[0] | ((u16) filter[1] << 8));
3315 gma_write16(hw, port, GM_MC_ADDR_H2,
3316 (u16) filter[2] | ((u16) filter[3] << 8));
3317 gma_write16(hw, port, GM_MC_ADDR_H3,
3318 (u16) filter[4] | ((u16) filter[5] << 8));
3319 gma_write16(hw, port, GM_MC_ADDR_H4,
3320 (u16) filter[6] | ((u16) filter[7] << 8));
3321
3322 gma_write16(hw, port, GM_RX_CTRL, reg);
3323 }
3324
3325 /* Can have one global because blinking is controlled by
3326 * ethtool and that is always under RTNL mutex
3327 */
3328 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3329 {
3330 u16 pg;
3331
3332 switch (hw->chip_id) {
3333 case CHIP_ID_YUKON_XL:
3334 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3335 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3336 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3337 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3338 PHY_M_LEDC_INIT_CTRL(7) |
3339 PHY_M_LEDC_STA1_CTRL(7) |
3340 PHY_M_LEDC_STA0_CTRL(7))
3341 : 0);
3342
3343 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3344 break;
3345
3346 default:
3347 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3348 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3349 on ? PHY_M_LED_ALL : 0);
3350 }
3351 }
3352
3353 /* blink LED's for finding board */
3354 static int sky2_phys_id(struct net_device *dev, u32 data)
3355 {
3356 struct sky2_port *sky2 = netdev_priv(dev);
3357 struct sky2_hw *hw = sky2->hw;
3358 unsigned port = sky2->port;
3359 u16 ledctrl, ledover = 0;
3360 long ms;
3361 int interrupted;
3362 int onoff = 1;
3363
3364 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3365 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3366 else
3367 ms = data * 1000;
3368
3369 /* save initial values */
3370 spin_lock_bh(&sky2->phy_lock);
3371 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3372 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3374 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3375 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3376 } else {
3377 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3378 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3379 }
3380
3381 interrupted = 0;
3382 while (!interrupted && ms > 0) {
3383 sky2_led(hw, port, onoff);
3384 onoff = !onoff;
3385
3386 spin_unlock_bh(&sky2->phy_lock);
3387 interrupted = msleep_interruptible(250);
3388 spin_lock_bh(&sky2->phy_lock);
3389
3390 ms -= 250;
3391 }
3392
3393 /* resume regularly scheduled programming */
3394 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3395 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3397 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3399 } else {
3400 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3401 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3402 }
3403 spin_unlock_bh(&sky2->phy_lock);
3404
3405 return 0;
3406 }
3407
3408 static void sky2_get_pauseparam(struct net_device *dev,
3409 struct ethtool_pauseparam *ecmd)
3410 {
3411 struct sky2_port *sky2 = netdev_priv(dev);
3412
3413 switch (sky2->flow_mode) {
3414 case FC_NONE:
3415 ecmd->tx_pause = ecmd->rx_pause = 0;
3416 break;
3417 case FC_TX:
3418 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3419 break;
3420 case FC_RX:
3421 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3422 break;
3423 case FC_BOTH:
3424 ecmd->tx_pause = ecmd->rx_pause = 1;
3425 }
3426
3427 ecmd->autoneg = sky2->autoneg;
3428 }
3429
3430 static int sky2_set_pauseparam(struct net_device *dev,
3431 struct ethtool_pauseparam *ecmd)
3432 {
3433 struct sky2_port *sky2 = netdev_priv(dev);
3434
3435 sky2->autoneg = ecmd->autoneg;
3436 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3437
3438 if (netif_running(dev))
3439 sky2_phy_reinit(sky2);
3440
3441 return 0;
3442 }
3443
3444 static int sky2_get_coalesce(struct net_device *dev,
3445 struct ethtool_coalesce *ecmd)
3446 {
3447 struct sky2_port *sky2 = netdev_priv(dev);
3448 struct sky2_hw *hw = sky2->hw;
3449
3450 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3451 ecmd->tx_coalesce_usecs = 0;
3452 else {
3453 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3454 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3455 }
3456 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3457
3458 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3459 ecmd->rx_coalesce_usecs = 0;
3460 else {
3461 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3462 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3463 }
3464 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3465
3466 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3467 ecmd->rx_coalesce_usecs_irq = 0;
3468 else {
3469 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3470 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3471 }
3472
3473 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3474
3475 return 0;
3476 }
3477
3478 /* Note: this affect both ports */
3479 static int sky2_set_coalesce(struct net_device *dev,
3480 struct ethtool_coalesce *ecmd)
3481 {
3482 struct sky2_port *sky2 = netdev_priv(dev);
3483 struct sky2_hw *hw = sky2->hw;
3484 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3485
3486 if (ecmd->tx_coalesce_usecs > tmax ||
3487 ecmd->rx_coalesce_usecs > tmax ||
3488 ecmd->rx_coalesce_usecs_irq > tmax)
3489 return -EINVAL;
3490
3491 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3492 return -EINVAL;
3493 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3494 return -EINVAL;
3495 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3496 return -EINVAL;
3497
3498 if (ecmd->tx_coalesce_usecs == 0)
3499 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3500 else {
3501 sky2_write32(hw, STAT_TX_TIMER_INI,
3502 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3503 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3504 }
3505 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3506
3507 if (ecmd->rx_coalesce_usecs == 0)
3508 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3509 else {
3510 sky2_write32(hw, STAT_LEV_TIMER_INI,
3511 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3512 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3513 }
3514 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3515
3516 if (ecmd->rx_coalesce_usecs_irq == 0)
3517 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3518 else {
3519 sky2_write32(hw, STAT_ISR_TIMER_INI,
3520 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3521 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3522 }
3523 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3524 return 0;
3525 }
3526
3527 static void sky2_get_ringparam(struct net_device *dev,
3528 struct ethtool_ringparam *ering)
3529 {
3530 struct sky2_port *sky2 = netdev_priv(dev);
3531
3532 ering->rx_max_pending = RX_MAX_PENDING;
3533 ering->rx_mini_max_pending = 0;
3534 ering->rx_jumbo_max_pending = 0;
3535 ering->tx_max_pending = TX_RING_SIZE - 1;
3536
3537 ering->rx_pending = sky2->rx_pending;
3538 ering->rx_mini_pending = 0;
3539 ering->rx_jumbo_pending = 0;
3540 ering->tx_pending = sky2->tx_pending;
3541 }
3542
3543 static int sky2_set_ringparam(struct net_device *dev,
3544 struct ethtool_ringparam *ering)
3545 {
3546 struct sky2_port *sky2 = netdev_priv(dev);
3547 int err = 0;
3548
3549 if (ering->rx_pending > RX_MAX_PENDING ||
3550 ering->rx_pending < 8 ||
3551 ering->tx_pending < MAX_SKB_TX_LE ||
3552 ering->tx_pending > TX_RING_SIZE - 1)
3553 return -EINVAL;
3554
3555 if (netif_running(dev))
3556 sky2_down(dev);
3557
3558 sky2->rx_pending = ering->rx_pending;
3559 sky2->tx_pending = ering->tx_pending;
3560
3561 if (netif_running(dev)) {
3562 err = sky2_up(dev);
3563 if (err)
3564 dev_close(dev);
3565 }
3566
3567 return err;
3568 }
3569
3570 static int sky2_get_regs_len(struct net_device *dev)
3571 {
3572 return 0x4000;
3573 }
3574
3575 /*
3576 * Returns copy of control register region
3577 * Note: ethtool_get_regs always provides full size (16k) buffer
3578 */
3579 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3580 void *p)
3581 {
3582 const struct sky2_port *sky2 = netdev_priv(dev);
3583 const void __iomem *io = sky2->hw->regs;
3584 unsigned int b;
3585
3586 regs->version = 1;
3587
3588 for (b = 0; b < 128; b++) {
3589 /* This complicated switch statement is to make sure and
3590 * only access regions that are unreserved.
3591 * Some blocks are only valid on dual port cards.
3592 * and block 3 has some special diagnostic registers that
3593 * are poison.
3594 */
3595 switch (b) {
3596 case 3:
3597 /* skip diagnostic ram region */
3598 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3599 break;
3600
3601 /* dual port cards only */
3602 case 5: /* Tx Arbiter 2 */
3603 case 9: /* RX2 */
3604 case 14 ... 15: /* TX2 */
3605 case 17: case 19: /* Ram Buffer 2 */
3606 case 22 ... 23: /* Tx Ram Buffer 2 */
3607 case 25: /* Rx MAC Fifo 1 */
3608 case 27: /* Tx MAC Fifo 2 */
3609 case 31: /* GPHY 2 */
3610 case 40 ... 47: /* Pattern Ram 2 */
3611 case 52: case 54: /* TCP Segmentation 2 */
3612 case 112 ... 116: /* GMAC 2 */
3613 if (sky2->hw->ports == 1)
3614 goto reserved;
3615 /* fall through */
3616 case 0: /* Control */
3617 case 2: /* Mac address */
3618 case 4: /* Tx Arbiter 1 */
3619 case 7: /* PCI express reg */
3620 case 8: /* RX1 */
3621 case 12 ... 13: /* TX1 */
3622 case 16: case 18:/* Rx Ram Buffer 1 */
3623 case 20 ... 21: /* Tx Ram Buffer 1 */
3624 case 24: /* Rx MAC Fifo 1 */
3625 case 26: /* Tx MAC Fifo 1 */
3626 case 28 ... 29: /* Descriptor and status unit */
3627 case 30: /* GPHY 1*/
3628 case 32 ... 39: /* Pattern Ram 1 */
3629 case 48: case 50: /* TCP Segmentation 1 */
3630 case 56 ... 60: /* PCI space */
3631 case 80 ... 84: /* GMAC 1 */
3632 memcpy_fromio(p, io, 128);
3633 break;
3634 default:
3635 reserved:
3636 memset(p, 0, 128);
3637 }
3638
3639 p += 128;
3640 io += 128;
3641 }
3642 }
3643
3644 /* In order to do Jumbo packets on these chips, need to turn off the
3645 * transmit store/forward. Therefore checksum offload won't work.
3646 */
3647 static int no_tx_offload(struct net_device *dev)
3648 {
3649 const struct sky2_port *sky2 = netdev_priv(dev);
3650 const struct sky2_hw *hw = sky2->hw;
3651
3652 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3653 }
3654
3655 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3656 {
3657 if (data && no_tx_offload(dev))
3658 return -EINVAL;
3659
3660 return ethtool_op_set_tx_csum(dev, data);
3661 }
3662
3663
3664 static int sky2_set_tso(struct net_device *dev, u32 data)
3665 {
3666 if (data && no_tx_offload(dev))
3667 return -EINVAL;
3668
3669 return ethtool_op_set_tso(dev, data);
3670 }
3671
3672 static int sky2_get_eeprom_len(struct net_device *dev)
3673 {
3674 struct sky2_port *sky2 = netdev_priv(dev);
3675 struct sky2_hw *hw = sky2->hw;
3676 u16 reg2;
3677
3678 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3679 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3680 }
3681
3682 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3683 {
3684 u32 val;
3685
3686 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3687
3688 do {
3689 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3690 } while (!(offset & PCI_VPD_ADDR_F));
3691
3692 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3693 return val;
3694 }
3695
3696 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3697 {
3698 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3699 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3700 do {
3701 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3702 } while (offset & PCI_VPD_ADDR_F);
3703 }
3704
3705 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3706 u8 *data)
3707 {
3708 struct sky2_port *sky2 = netdev_priv(dev);
3709 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3710 int length = eeprom->len;
3711 u16 offset = eeprom->offset;
3712
3713 if (!cap)
3714 return -EINVAL;
3715
3716 eeprom->magic = SKY2_EEPROM_MAGIC;
3717
3718 while (length > 0) {
3719 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3720 int n = min_t(int, length, sizeof(val));
3721
3722 memcpy(data, &val, n);
3723 length -= n;
3724 data += n;
3725 offset += n;
3726 }
3727 return 0;
3728 }
3729
3730 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3731 u8 *data)
3732 {
3733 struct sky2_port *sky2 = netdev_priv(dev);
3734 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3735 int length = eeprom->len;
3736 u16 offset = eeprom->offset;
3737
3738 if (!cap)
3739 return -EINVAL;
3740
3741 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3742 return -EINVAL;
3743
3744 while (length > 0) {
3745 u32 val;
3746 int n = min_t(int, length, sizeof(val));
3747
3748 if (n < sizeof(val))
3749 val = sky2_vpd_read(sky2->hw, cap, offset);
3750 memcpy(&val, data, n);
3751
3752 sky2_vpd_write(sky2->hw, cap, offset, val);
3753
3754 length -= n;
3755 data += n;
3756 offset += n;
3757 }
3758 return 0;
3759 }
3760
3761
3762 static const struct ethtool_ops sky2_ethtool_ops = {
3763 .get_settings = sky2_get_settings,
3764 .set_settings = sky2_set_settings,
3765 .get_drvinfo = sky2_get_drvinfo,
3766 .get_wol = sky2_get_wol,
3767 .set_wol = sky2_set_wol,
3768 .get_msglevel = sky2_get_msglevel,
3769 .set_msglevel = sky2_set_msglevel,
3770 .nway_reset = sky2_nway_reset,
3771 .get_regs_len = sky2_get_regs_len,
3772 .get_regs = sky2_get_regs,
3773 .get_link = ethtool_op_get_link,
3774 .get_eeprom_len = sky2_get_eeprom_len,
3775 .get_eeprom = sky2_get_eeprom,
3776 .set_eeprom = sky2_set_eeprom,
3777 .set_sg = ethtool_op_set_sg,
3778 .set_tx_csum = sky2_set_tx_csum,
3779 .set_tso = sky2_set_tso,
3780 .get_rx_csum = sky2_get_rx_csum,
3781 .set_rx_csum = sky2_set_rx_csum,
3782 .get_strings = sky2_get_strings,
3783 .get_coalesce = sky2_get_coalesce,
3784 .set_coalesce = sky2_set_coalesce,
3785 .get_ringparam = sky2_get_ringparam,
3786 .set_ringparam = sky2_set_ringparam,
3787 .get_pauseparam = sky2_get_pauseparam,
3788 .set_pauseparam = sky2_set_pauseparam,
3789 .phys_id = sky2_phys_id,
3790 .get_sset_count = sky2_get_sset_count,
3791 .get_ethtool_stats = sky2_get_ethtool_stats,
3792 };
3793
3794 #ifdef CONFIG_SKY2_DEBUG
3795
3796 static struct dentry *sky2_debug;
3797
3798 static int sky2_debug_show(struct seq_file *seq, void *v)
3799 {
3800 struct net_device *dev = seq->private;
3801 const struct sky2_port *sky2 = netdev_priv(dev);
3802 struct sky2_hw *hw = sky2->hw;
3803 unsigned port = sky2->port;
3804 unsigned idx, last;
3805 int sop;
3806
3807 if (!netif_running(dev))
3808 return -ENETDOWN;
3809
3810 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3811 sky2_read32(hw, B0_ISRC),
3812 sky2_read32(hw, B0_IMSK),
3813 sky2_read32(hw, B0_Y2_SP_ICR));
3814
3815 napi_disable(&hw->napi);
3816 last = sky2_read16(hw, STAT_PUT_IDX);
3817
3818 if (hw->st_idx == last)
3819 seq_puts(seq, "Status ring (empty)\n");
3820 else {
3821 seq_puts(seq, "Status ring\n");
3822 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3823 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3824 const struct sky2_status_le *le = hw->st_le + idx;
3825 seq_printf(seq, "[%d] %#x %d %#x\n",
3826 idx, le->opcode, le->length, le->status);
3827 }
3828 seq_puts(seq, "\n");
3829 }
3830
3831 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3832 sky2->tx_cons, sky2->tx_prod,
3833 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3834 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3835
3836 /* Dump contents of tx ring */
3837 sop = 1;
3838 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3839 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3840 const struct sky2_tx_le *le = sky2->tx_le + idx;
3841 u32 a = le32_to_cpu(le->addr);
3842
3843 if (sop)
3844 seq_printf(seq, "%u:", idx);
3845 sop = 0;
3846
3847 switch(le->opcode & ~HW_OWNER) {
3848 case OP_ADDR64:
3849 seq_printf(seq, " %#x:", a);
3850 break;
3851 case OP_LRGLEN:
3852 seq_printf(seq, " mtu=%d", a);
3853 break;
3854 case OP_VLAN:
3855 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3856 break;
3857 case OP_TCPLISW:
3858 seq_printf(seq, " csum=%#x", a);
3859 break;
3860 case OP_LARGESEND:
3861 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3862 break;
3863 case OP_PACKET:
3864 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3865 break;
3866 case OP_BUFFER:
3867 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3868 break;
3869 default:
3870 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3871 a, le16_to_cpu(le->length));
3872 }
3873
3874 if (le->ctrl & EOP) {
3875 seq_putc(seq, '\n');
3876 sop = 1;
3877 }
3878 }
3879
3880 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3881 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3882 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3883 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3884
3885 sky2_read32(hw, B0_Y2_SP_LISR);
3886 napi_enable(&hw->napi);
3887 return 0;
3888 }
3889
3890 static int sky2_debug_open(struct inode *inode, struct file *file)
3891 {
3892 return single_open(file, sky2_debug_show, inode->i_private);
3893 }
3894
3895 static const struct file_operations sky2_debug_fops = {
3896 .owner = THIS_MODULE,
3897 .open = sky2_debug_open,
3898 .read = seq_read,
3899 .llseek = seq_lseek,
3900 .release = single_release,
3901 };
3902
3903 /*
3904 * Use network device events to create/remove/rename
3905 * debugfs file entries
3906 */
3907 static int sky2_device_event(struct notifier_block *unused,
3908 unsigned long event, void *ptr)
3909 {
3910 struct net_device *dev = ptr;
3911 struct sky2_port *sky2 = netdev_priv(dev);
3912
3913 if (dev->open != sky2_up || !sky2_debug)
3914 return NOTIFY_DONE;
3915
3916 switch(event) {
3917 case NETDEV_CHANGENAME:
3918 if (sky2->debugfs) {
3919 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3920 sky2_debug, dev->name);
3921 }
3922 break;
3923
3924 case NETDEV_GOING_DOWN:
3925 if (sky2->debugfs) {
3926 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3927 dev->name);
3928 debugfs_remove(sky2->debugfs);
3929 sky2->debugfs = NULL;
3930 }
3931 break;
3932
3933 case NETDEV_UP:
3934 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3935 sky2_debug, dev,
3936 &sky2_debug_fops);
3937 if (IS_ERR(sky2->debugfs))
3938 sky2->debugfs = NULL;
3939 }
3940
3941 return NOTIFY_DONE;
3942 }
3943
3944 static struct notifier_block sky2_notifier = {
3945 .notifier_call = sky2_device_event,
3946 };
3947
3948
3949 static __init void sky2_debug_init(void)
3950 {
3951 struct dentry *ent;
3952
3953 ent = debugfs_create_dir("sky2", NULL);
3954 if (!ent || IS_ERR(ent))
3955 return;
3956
3957 sky2_debug = ent;
3958 register_netdevice_notifier(&sky2_notifier);
3959 }
3960
3961 static __exit void sky2_debug_cleanup(void)
3962 {
3963 if (sky2_debug) {
3964 unregister_netdevice_notifier(&sky2_notifier);
3965 debugfs_remove(sky2_debug);
3966 sky2_debug = NULL;
3967 }
3968 }
3969
3970 #else
3971 #define sky2_debug_init()
3972 #define sky2_debug_cleanup()
3973 #endif
3974
3975
3976 /* Initialize network device */
3977 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3978 unsigned port,
3979 int highmem, int wol)
3980 {
3981 struct sky2_port *sky2;
3982 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3983
3984 if (!dev) {
3985 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3986 return NULL;
3987 }
3988
3989 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3990 dev->irq = hw->pdev->irq;
3991 dev->open = sky2_up;
3992 dev->stop = sky2_down;
3993 dev->do_ioctl = sky2_ioctl;
3994 dev->hard_start_xmit = sky2_xmit_frame;
3995 dev->set_multicast_list = sky2_set_multicast;
3996 dev->set_mac_address = sky2_set_mac_address;
3997 dev->change_mtu = sky2_change_mtu;
3998 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3999 dev->tx_timeout = sky2_tx_timeout;
4000 dev->watchdog_timeo = TX_WATCHDOG;
4001 #ifdef CONFIG_NET_POLL_CONTROLLER
4002 if (port == 0)
4003 dev->poll_controller = sky2_netpoll;
4004 #endif
4005
4006 sky2 = netdev_priv(dev);
4007 sky2->netdev = dev;
4008 sky2->hw = hw;
4009 sky2->msg_enable = netif_msg_init(debug, default_msg);
4010
4011 /* Auto speed and flow control */
4012 sky2->autoneg = AUTONEG_ENABLE;
4013 sky2->flow_mode = FC_BOTH;
4014
4015 sky2->duplex = -1;
4016 sky2->speed = -1;
4017 sky2->advertising = sky2_supported_modes(hw);
4018 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4019 sky2->wol = wol;
4020
4021 spin_lock_init(&sky2->phy_lock);
4022 sky2->tx_pending = TX_DEF_PENDING;
4023 sky2->rx_pending = RX_DEF_PENDING;
4024
4025 hw->dev[port] = dev;
4026
4027 sky2->port = port;
4028
4029 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4030 if (highmem)
4031 dev->features |= NETIF_F_HIGHDMA;
4032
4033 #ifdef SKY2_VLAN_TAG_USED
4034 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4035 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4036 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4037 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4038 dev->vlan_rx_register = sky2_vlan_rx_register;
4039 }
4040 #endif
4041
4042 /* read the mac address */
4043 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4044 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4045
4046 return dev;
4047 }
4048
4049 static void __devinit sky2_show_addr(struct net_device *dev)
4050 {
4051 const struct sky2_port *sky2 = netdev_priv(dev);
4052 DECLARE_MAC_BUF(mac);
4053
4054 if (netif_msg_probe(sky2))
4055 printk(KERN_INFO PFX "%s: addr %s\n",
4056 dev->name, print_mac(mac, dev->dev_addr));
4057 }
4058
4059 /* Handle software interrupt used during MSI test */
4060 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4061 {
4062 struct sky2_hw *hw = dev_id;
4063 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4064
4065 if (status == 0)
4066 return IRQ_NONE;
4067
4068 if (status & Y2_IS_IRQ_SW) {
4069 hw->flags |= SKY2_HW_USE_MSI;
4070 wake_up(&hw->msi_wait);
4071 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4072 }
4073 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4074
4075 return IRQ_HANDLED;
4076 }
4077
4078 /* Test interrupt path by forcing a a software IRQ */
4079 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4080 {
4081 struct pci_dev *pdev = hw->pdev;
4082 int err;
4083
4084 init_waitqueue_head (&hw->msi_wait);
4085
4086 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4087
4088 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4089 if (err) {
4090 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4091 return err;
4092 }
4093
4094 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4095 sky2_read8(hw, B0_CTST);
4096
4097 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4098
4099 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4100 /* MSI test failed, go back to INTx mode */
4101 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4102 "switching to INTx mode.\n");
4103
4104 err = -EOPNOTSUPP;
4105 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4106 }
4107
4108 sky2_write32(hw, B0_IMSK, 0);
4109 sky2_read32(hw, B0_IMSK);
4110
4111 free_irq(pdev->irq, hw);
4112
4113 return err;
4114 }
4115
4116 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4117 {
4118 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4119 u16 value;
4120
4121 if (!pm)
4122 return 0;
4123 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4124 return 0;
4125 return value & PCI_PM_CTRL_PME_ENABLE;
4126 }
4127
4128 static int __devinit sky2_probe(struct pci_dev *pdev,
4129 const struct pci_device_id *ent)
4130 {
4131 struct net_device *dev;
4132 struct sky2_hw *hw;
4133 int err, using_dac = 0, wol_default;
4134
4135 err = pci_enable_device(pdev);
4136 if (err) {
4137 dev_err(&pdev->dev, "cannot enable PCI device\n");
4138 goto err_out;
4139 }
4140
4141 err = pci_request_regions(pdev, DRV_NAME);
4142 if (err) {
4143 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4144 goto err_out_disable;
4145 }
4146
4147 pci_set_master(pdev);
4148
4149 if (sizeof(dma_addr_t) > sizeof(u32) &&
4150 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4151 using_dac = 1;
4152 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4153 if (err < 0) {
4154 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4155 "for consistent allocations\n");
4156 goto err_out_free_regions;
4157 }
4158 } else {
4159 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4160 if (err) {
4161 dev_err(&pdev->dev, "no usable DMA configuration\n");
4162 goto err_out_free_regions;
4163 }
4164 }
4165
4166 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4167
4168 err = -ENOMEM;
4169 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4170 if (!hw) {
4171 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4172 goto err_out_free_regions;
4173 }
4174
4175 hw->pdev = pdev;
4176
4177 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4178 if (!hw->regs) {
4179 dev_err(&pdev->dev, "cannot map device registers\n");
4180 goto err_out_free_hw;
4181 }
4182
4183 #ifdef __BIG_ENDIAN
4184 /* The sk98lin vendor driver uses hardware byte swapping but
4185 * this driver uses software swapping.
4186 */
4187 {
4188 u32 reg;
4189 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4190 reg &= ~PCI_REV_DESC;
4191 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4192 }
4193 #endif
4194
4195 /* ring for status responses */
4196 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4197 if (!hw->st_le)
4198 goto err_out_iounmap;
4199
4200 err = sky2_init(hw);
4201 if (err)
4202 goto err_out_iounmap;
4203
4204 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4205 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4206 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4207 hw->chip_id, hw->chip_rev);
4208
4209 sky2_reset(hw);
4210
4211 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4212 if (!dev) {
4213 err = -ENOMEM;
4214 goto err_out_free_pci;
4215 }
4216
4217 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4218 err = sky2_test_msi(hw);
4219 if (err == -EOPNOTSUPP)
4220 pci_disable_msi(pdev);
4221 else if (err)
4222 goto err_out_free_netdev;
4223 }
4224
4225 err = register_netdev(dev);
4226 if (err) {
4227 dev_err(&pdev->dev, "cannot register net device\n");
4228 goto err_out_free_netdev;
4229 }
4230
4231 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4232
4233 err = request_irq(pdev->irq, sky2_intr,
4234 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4235 dev->name, hw);
4236 if (err) {
4237 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4238 goto err_out_unregister;
4239 }
4240 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4241 napi_enable(&hw->napi);
4242
4243 sky2_show_addr(dev);
4244
4245 if (hw->ports > 1) {
4246 struct net_device *dev1;
4247
4248 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4249 if (!dev1)
4250 dev_warn(&pdev->dev, "allocation for second device failed\n");
4251 else if ((err = register_netdev(dev1))) {
4252 dev_warn(&pdev->dev,
4253 "register of second port failed (%d)\n", err);
4254 hw->dev[1] = NULL;
4255 free_netdev(dev1);
4256 } else
4257 sky2_show_addr(dev1);
4258 }
4259
4260 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4261 INIT_WORK(&hw->restart_work, sky2_restart);
4262
4263 pci_set_drvdata(pdev, hw);
4264
4265 return 0;
4266
4267 err_out_unregister:
4268 if (hw->flags & SKY2_HW_USE_MSI)
4269 pci_disable_msi(pdev);
4270 unregister_netdev(dev);
4271 err_out_free_netdev:
4272 free_netdev(dev);
4273 err_out_free_pci:
4274 sky2_write8(hw, B0_CTST, CS_RST_SET);
4275 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4276 err_out_iounmap:
4277 iounmap(hw->regs);
4278 err_out_free_hw:
4279 kfree(hw);
4280 err_out_free_regions:
4281 pci_release_regions(pdev);
4282 err_out_disable:
4283 pci_disable_device(pdev);
4284 err_out:
4285 pci_set_drvdata(pdev, NULL);
4286 return err;
4287 }
4288
4289 static void __devexit sky2_remove(struct pci_dev *pdev)
4290 {
4291 struct sky2_hw *hw = pci_get_drvdata(pdev);
4292 int i;
4293
4294 if (!hw)
4295 return;
4296
4297 del_timer_sync(&hw->watchdog_timer);
4298 cancel_work_sync(&hw->restart_work);
4299
4300 for (i = hw->ports-1; i >= 0; --i)
4301 unregister_netdev(hw->dev[i]);
4302
4303 sky2_write32(hw, B0_IMSK, 0);
4304
4305 sky2_power_aux(hw);
4306
4307 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4308 sky2_write8(hw, B0_CTST, CS_RST_SET);
4309 sky2_read8(hw, B0_CTST);
4310
4311 free_irq(pdev->irq, hw);
4312 if (hw->flags & SKY2_HW_USE_MSI)
4313 pci_disable_msi(pdev);
4314 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4315 pci_release_regions(pdev);
4316 pci_disable_device(pdev);
4317
4318 for (i = hw->ports-1; i >= 0; --i)
4319 free_netdev(hw->dev[i]);
4320
4321 iounmap(hw->regs);
4322 kfree(hw);
4323
4324 pci_set_drvdata(pdev, NULL);
4325 }
4326
4327 #ifdef CONFIG_PM
4328 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4329 {
4330 struct sky2_hw *hw = pci_get_drvdata(pdev);
4331 int i, wol = 0;
4332
4333 if (!hw)
4334 return 0;
4335
4336 for (i = 0; i < hw->ports; i++) {
4337 struct net_device *dev = hw->dev[i];
4338 struct sky2_port *sky2 = netdev_priv(dev);
4339
4340 if (netif_running(dev))
4341 sky2_down(dev);
4342
4343 if (sky2->wol)
4344 sky2_wol_init(sky2);
4345
4346 wol |= sky2->wol;
4347 }
4348
4349 sky2_write32(hw, B0_IMSK, 0);
4350 napi_disable(&hw->napi);
4351 sky2_power_aux(hw);
4352
4353 pci_save_state(pdev);
4354 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4355 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4356
4357 return 0;
4358 }
4359
4360 static int sky2_resume(struct pci_dev *pdev)
4361 {
4362 struct sky2_hw *hw = pci_get_drvdata(pdev);
4363 int i, err;
4364
4365 if (!hw)
4366 return 0;
4367
4368 err = pci_set_power_state(pdev, PCI_D0);
4369 if (err)
4370 goto out;
4371
4372 err = pci_restore_state(pdev);
4373 if (err)
4374 goto out;
4375
4376 pci_enable_wake(pdev, PCI_D0, 0);
4377
4378 /* Re-enable all clocks */
4379 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4380 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4381 hw->chip_id == CHIP_ID_YUKON_FE_P)
4382 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4383
4384 sky2_reset(hw);
4385 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4386 napi_enable(&hw->napi);
4387
4388 for (i = 0; i < hw->ports; i++) {
4389 struct net_device *dev = hw->dev[i];
4390 if (netif_running(dev)) {
4391 err = sky2_up(dev);
4392 if (err) {
4393 printk(KERN_ERR PFX "%s: could not up: %d\n",
4394 dev->name, err);
4395 dev_close(dev);
4396 goto out;
4397 }
4398 }
4399 }
4400
4401 return 0;
4402 out:
4403 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4404 pci_disable_device(pdev);
4405 return err;
4406 }
4407 #endif
4408
4409 static void sky2_shutdown(struct pci_dev *pdev)
4410 {
4411 struct sky2_hw *hw = pci_get_drvdata(pdev);
4412 int i, wol = 0;
4413
4414 if (!hw)
4415 return;
4416
4417 del_timer_sync(&hw->watchdog_timer);
4418
4419 for (i = 0; i < hw->ports; i++) {
4420 struct net_device *dev = hw->dev[i];
4421 struct sky2_port *sky2 = netdev_priv(dev);
4422
4423 if (sky2->wol) {
4424 wol = 1;
4425 sky2_wol_init(sky2);
4426 }
4427 }
4428
4429 if (wol)
4430 sky2_power_aux(hw);
4431
4432 pci_enable_wake(pdev, PCI_D3hot, wol);
4433 pci_enable_wake(pdev, PCI_D3cold, wol);
4434
4435 pci_disable_device(pdev);
4436 pci_set_power_state(pdev, PCI_D3hot);
4437
4438 }
4439
4440 static struct pci_driver sky2_driver = {
4441 .name = DRV_NAME,
4442 .id_table = sky2_id_table,
4443 .probe = sky2_probe,
4444 .remove = __devexit_p(sky2_remove),
4445 #ifdef CONFIG_PM
4446 .suspend = sky2_suspend,
4447 .resume = sky2_resume,
4448 #endif
4449 .shutdown = sky2_shutdown,
4450 };
4451
4452 static int __init sky2_init_module(void)
4453 {
4454 sky2_debug_init();
4455 return pci_register_driver(&sky2_driver);
4456 }
4457
4458 static void __exit sky2_cleanup_module(void)
4459 {
4460 pci_unregister_driver(&sky2_driver);
4461 sky2_debug_cleanup();
4462 }
4463
4464 module_init(sky2_init_module);
4465 module_exit(sky2_cleanup_module);
4466
4467 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4468 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4469 MODULE_LICENSE("GPL");
4470 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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