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[deliverable/linux.git] / drivers / net / smc91x.c
1 /*
2 * smc91x.c
3 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
4 *
5 * Copyright (C) 1996 by Erik Stahlman
6 * Copyright (C) 2001 Standard Microsystems Corporation
7 * Developed by Simple Network Magic Corporation
8 * Copyright (C) 2003 Monta Vista Software, Inc.
9 * Unified SMC91x driver by Nicolas Pitre
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * Arguments:
26 * io = for the base address
27 * irq = for the IRQ
28 * nowait = 0 for normal wait states, 1 eliminates additional wait states
29 *
30 * original author:
31 * Erik Stahlman <erik@vt.edu>
32 *
33 * hardware multicast code:
34 * Peter Cammaert <pc@denkart.be>
35 *
36 * contributors:
37 * Daris A Nevil <dnevil@snmc.com>
38 * Nicolas Pitre <nico@cam.org>
39 * Russell King <rmk@arm.linux.org.uk>
40 *
41 * History:
42 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
43 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
44 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111
45 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111
46 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111
47 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support
48 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races,
49 * more bus abstraction, big cleanup, etc.
50 * 29/09/03 Russell King - add driver model support
51 * - ethtool support
52 * - convert to use generic MII interface
53 * - add link up/down notification
54 * - don't try to handle full negotiation in
55 * smc_phy_configure
56 * - clean up (and fix stack overrun) in PHY
57 * MII read/write functions
58 * 22/09/04 Nicolas Pitre big update (see commit log for details)
59 */
60 static const char version[] =
61 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@cam.org>\n";
62
63 /* Debugging level */
64 #ifndef SMC_DEBUG
65 #define SMC_DEBUG 0
66 #endif
67
68
69 #include <linux/init.h>
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/sched.h>
73 #include <linux/slab.h>
74 #include <linux/delay.h>
75 #include <linux/interrupt.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/crc32.h>
79 #include <linux/platform_device.h>
80 #include <linux/spinlock.h>
81 #include <linux/ethtool.h>
82 #include <linux/mii.h>
83 #include <linux/workqueue.h>
84
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88
89 #include <asm/io.h>
90
91 #include "smc91x.h"
92
93 #ifndef SMC_NOWAIT
94 # define SMC_NOWAIT 0
95 #endif
96 static int nowait = SMC_NOWAIT;
97 module_param(nowait, int, 0400);
98 MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
99
100 /*
101 * Transmit timeout, default 5 seconds.
102 */
103 static int watchdog = 1000;
104 module_param(watchdog, int, 0400);
105 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
106
107 MODULE_LICENSE("GPL");
108 MODULE_ALIAS("platform:smc91x");
109
110 /*
111 * The internal workings of the driver. If you are changing anything
112 * here with the SMC stuff, you should have the datasheet and know
113 * what you are doing.
114 */
115 #define CARDNAME "smc91x"
116
117 /*
118 * Use power-down feature of the chip
119 */
120 #define POWER_DOWN 1
121
122 /*
123 * Wait time for memory to be free. This probably shouldn't be
124 * tuned that much, as waiting for this means nothing else happens
125 * in the system
126 */
127 #define MEMORY_WAIT_TIME 16
128
129 /*
130 * The maximum number of processing loops allowed for each call to the
131 * IRQ handler.
132 */
133 #define MAX_IRQ_LOOPS 8
134
135 /*
136 * This selects whether TX packets are sent one by one to the SMC91x internal
137 * memory and throttled until transmission completes. This may prevent
138 * RX overruns a litle by keeping much of the memory free for RX packets
139 * but to the expense of reduced TX throughput and increased IRQ overhead.
140 * Note this is not a cure for a too slow data bus or too high IRQ latency.
141 */
142 #define THROTTLE_TX_PKTS 0
143
144 /*
145 * The MII clock high/low times. 2x this number gives the MII clock period
146 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
147 */
148 #define MII_DELAY 1
149
150 #if SMC_DEBUG > 0
151 #define DBG(n, args...) \
152 do { \
153 if (SMC_DEBUG >= (n)) \
154 printk(args); \
155 } while (0)
156
157 #define PRINTK(args...) printk(args)
158 #else
159 #define DBG(n, args...) do { } while(0)
160 #define PRINTK(args...) printk(KERN_DEBUG args)
161 #endif
162
163 #if SMC_DEBUG > 3
164 static void PRINT_PKT(u_char *buf, int length)
165 {
166 int i;
167 int remainder;
168 int lines;
169
170 lines = length / 16;
171 remainder = length % 16;
172
173 for (i = 0; i < lines ; i ++) {
174 int cur;
175 for (cur = 0; cur < 8; cur++) {
176 u_char a, b;
177 a = *buf++;
178 b = *buf++;
179 printk("%02x%02x ", a, b);
180 }
181 printk("\n");
182 }
183 for (i = 0; i < remainder/2 ; i++) {
184 u_char a, b;
185 a = *buf++;
186 b = *buf++;
187 printk("%02x%02x ", a, b);
188 }
189 printk("\n");
190 }
191 #else
192 #define PRINT_PKT(x...) do { } while(0)
193 #endif
194
195
196 /* this enables an interrupt in the interrupt mask register */
197 #define SMC_ENABLE_INT(lp, x) do { \
198 unsigned char mask; \
199 spin_lock_irq(&lp->lock); \
200 mask = SMC_GET_INT_MASK(lp); \
201 mask |= (x); \
202 SMC_SET_INT_MASK(lp, mask); \
203 spin_unlock_irq(&lp->lock); \
204 } while (0)
205
206 /* this disables an interrupt from the interrupt mask register */
207 #define SMC_DISABLE_INT(lp, x) do { \
208 unsigned char mask; \
209 spin_lock_irq(&lp->lock); \
210 mask = SMC_GET_INT_MASK(lp); \
211 mask &= ~(x); \
212 SMC_SET_INT_MASK(lp, mask); \
213 spin_unlock_irq(&lp->lock); \
214 } while (0)
215
216 /*
217 * Wait while MMU is busy. This is usually in the order of a few nanosecs
218 * if at all, but let's avoid deadlocking the system if the hardware
219 * decides to go south.
220 */
221 #define SMC_WAIT_MMU_BUSY(lp) do { \
222 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
223 unsigned long timeout = jiffies + 2; \
224 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
225 if (time_after(jiffies, timeout)) { \
226 printk("%s: timeout %s line %d\n", \
227 dev->name, __FILE__, __LINE__); \
228 break; \
229 } \
230 cpu_relax(); \
231 } \
232 } \
233 } while (0)
234
235
236 /*
237 * this does a soft reset on the device
238 */
239 static void smc_reset(struct net_device *dev)
240 {
241 struct smc_local *lp = netdev_priv(dev);
242 void __iomem *ioaddr = lp->base;
243 unsigned int ctl, cfg;
244 struct sk_buff *pending_skb;
245
246 DBG(2, "%s: %s\n", dev->name, __func__);
247
248 /* Disable all interrupts, block TX tasklet */
249 spin_lock_irq(&lp->lock);
250 SMC_SELECT_BANK(lp, 2);
251 SMC_SET_INT_MASK(lp, 0);
252 pending_skb = lp->pending_tx_skb;
253 lp->pending_tx_skb = NULL;
254 spin_unlock_irq(&lp->lock);
255
256 /* free any pending tx skb */
257 if (pending_skb) {
258 dev_kfree_skb(pending_skb);
259 dev->stats.tx_errors++;
260 dev->stats.tx_aborted_errors++;
261 }
262
263 /*
264 * This resets the registers mostly to defaults, but doesn't
265 * affect EEPROM. That seems unnecessary
266 */
267 SMC_SELECT_BANK(lp, 0);
268 SMC_SET_RCR(lp, RCR_SOFTRST);
269
270 /*
271 * Setup the Configuration Register
272 * This is necessary because the CONFIG_REG is not affected
273 * by a soft reset
274 */
275 SMC_SELECT_BANK(lp, 1);
276
277 cfg = CONFIG_DEFAULT;
278
279 /*
280 * Setup for fast accesses if requested. If the card/system
281 * can't handle it then there will be no recovery except for
282 * a hard reset or power cycle
283 */
284 if (lp->cfg.flags & SMC91X_NOWAIT)
285 cfg |= CONFIG_NO_WAIT;
286
287 /*
288 * Release from possible power-down state
289 * Configuration register is not affected by Soft Reset
290 */
291 cfg |= CONFIG_EPH_POWER_EN;
292
293 SMC_SET_CONFIG(lp, cfg);
294
295 /* this should pause enough for the chip to be happy */
296 /*
297 * elaborate? What does the chip _need_? --jgarzik
298 *
299 * This seems to be undocumented, but something the original
300 * driver(s) have always done. Suspect undocumented timing
301 * info/determined empirically. --rmk
302 */
303 udelay(1);
304
305 /* Disable transmit and receive functionality */
306 SMC_SELECT_BANK(lp, 0);
307 SMC_SET_RCR(lp, RCR_CLEAR);
308 SMC_SET_TCR(lp, TCR_CLEAR);
309
310 SMC_SELECT_BANK(lp, 1);
311 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
312
313 /*
314 * Set the control register to automatically release successfully
315 * transmitted packets, to make the best use out of our limited
316 * memory
317 */
318 if(!THROTTLE_TX_PKTS)
319 ctl |= CTL_AUTO_RELEASE;
320 else
321 ctl &= ~CTL_AUTO_RELEASE;
322 SMC_SET_CTL(lp, ctl);
323
324 /* Reset the MMU */
325 SMC_SELECT_BANK(lp, 2);
326 SMC_SET_MMU_CMD(lp, MC_RESET);
327 SMC_WAIT_MMU_BUSY(lp);
328 }
329
330 /*
331 * Enable Interrupts, Receive, and Transmit
332 */
333 static void smc_enable(struct net_device *dev)
334 {
335 struct smc_local *lp = netdev_priv(dev);
336 void __iomem *ioaddr = lp->base;
337 int mask;
338
339 DBG(2, "%s: %s\n", dev->name, __func__);
340
341 /* see the header file for options in TCR/RCR DEFAULT */
342 SMC_SELECT_BANK(lp, 0);
343 SMC_SET_TCR(lp, lp->tcr_cur_mode);
344 SMC_SET_RCR(lp, lp->rcr_cur_mode);
345
346 SMC_SELECT_BANK(lp, 1);
347 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
348
349 /* now, enable interrupts */
350 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
351 if (lp->version >= (CHIP_91100 << 4))
352 mask |= IM_MDINT;
353 SMC_SELECT_BANK(lp, 2);
354 SMC_SET_INT_MASK(lp, mask);
355
356 /*
357 * From this point the register bank must _NOT_ be switched away
358 * to something else than bank 2 without proper locking against
359 * races with any tasklet or interrupt handlers until smc_shutdown()
360 * or smc_reset() is called.
361 */
362 }
363
364 /*
365 * this puts the device in an inactive state
366 */
367 static void smc_shutdown(struct net_device *dev)
368 {
369 struct smc_local *lp = netdev_priv(dev);
370 void __iomem *ioaddr = lp->base;
371 struct sk_buff *pending_skb;
372
373 DBG(2, "%s: %s\n", CARDNAME, __func__);
374
375 /* no more interrupts for me */
376 spin_lock_irq(&lp->lock);
377 SMC_SELECT_BANK(lp, 2);
378 SMC_SET_INT_MASK(lp, 0);
379 pending_skb = lp->pending_tx_skb;
380 lp->pending_tx_skb = NULL;
381 spin_unlock_irq(&lp->lock);
382 if (pending_skb)
383 dev_kfree_skb(pending_skb);
384
385 /* and tell the card to stay away from that nasty outside world */
386 SMC_SELECT_BANK(lp, 0);
387 SMC_SET_RCR(lp, RCR_CLEAR);
388 SMC_SET_TCR(lp, TCR_CLEAR);
389
390 #ifdef POWER_DOWN
391 /* finally, shut the chip down */
392 SMC_SELECT_BANK(lp, 1);
393 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
394 #endif
395 }
396
397 /*
398 * This is the procedure to handle the receipt of a packet.
399 */
400 static inline void smc_rcv(struct net_device *dev)
401 {
402 struct smc_local *lp = netdev_priv(dev);
403 void __iomem *ioaddr = lp->base;
404 unsigned int packet_number, status, packet_len;
405
406 DBG(3, "%s: %s\n", dev->name, __func__);
407
408 packet_number = SMC_GET_RXFIFO(lp);
409 if (unlikely(packet_number & RXFIFO_REMPTY)) {
410 PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name);
411 return;
412 }
413
414 /* read from start of packet */
415 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
416
417 /* First two words are status and packet length */
418 SMC_GET_PKT_HDR(lp, status, packet_len);
419 packet_len &= 0x07ff; /* mask off top bits */
420 DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
421 dev->name, packet_number, status,
422 packet_len, packet_len);
423
424 back:
425 if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
426 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
427 /* accept VLAN packets */
428 status &= ~RS_TOOLONG;
429 goto back;
430 }
431 if (packet_len < 6) {
432 /* bloody hardware */
433 printk(KERN_ERR "%s: fubar (rxlen %u status %x\n",
434 dev->name, packet_len, status);
435 status |= RS_TOOSHORT;
436 }
437 SMC_WAIT_MMU_BUSY(lp);
438 SMC_SET_MMU_CMD(lp, MC_RELEASE);
439 dev->stats.rx_errors++;
440 if (status & RS_ALGNERR)
441 dev->stats.rx_frame_errors++;
442 if (status & (RS_TOOSHORT | RS_TOOLONG))
443 dev->stats.rx_length_errors++;
444 if (status & RS_BADCRC)
445 dev->stats.rx_crc_errors++;
446 } else {
447 struct sk_buff *skb;
448 unsigned char *data;
449 unsigned int data_len;
450
451 /* set multicast stats */
452 if (status & RS_MULTICAST)
453 dev->stats.multicast++;
454
455 /*
456 * Actual payload is packet_len - 6 (or 5 if odd byte).
457 * We want skb_reserve(2) and the final ctrl word
458 * (2 bytes, possibly containing the payload odd byte).
459 * Furthermore, we add 2 bytes to allow rounding up to
460 * multiple of 4 bytes on 32 bit buses.
461 * Hence packet_len - 6 + 2 + 2 + 2.
462 */
463 skb = dev_alloc_skb(packet_len);
464 if (unlikely(skb == NULL)) {
465 printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
466 dev->name);
467 SMC_WAIT_MMU_BUSY(lp);
468 SMC_SET_MMU_CMD(lp, MC_RELEASE);
469 dev->stats.rx_dropped++;
470 return;
471 }
472
473 /* Align IP header to 32 bits */
474 skb_reserve(skb, 2);
475
476 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */
477 if (lp->version == 0x90)
478 status |= RS_ODDFRAME;
479
480 /*
481 * If odd length: packet_len - 5,
482 * otherwise packet_len - 6.
483 * With the trailing ctrl byte it's packet_len - 4.
484 */
485 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
486 data = skb_put(skb, data_len);
487 SMC_PULL_DATA(lp, data, packet_len - 4);
488
489 SMC_WAIT_MMU_BUSY(lp);
490 SMC_SET_MMU_CMD(lp, MC_RELEASE);
491
492 PRINT_PKT(data, packet_len - 4);
493
494 skb->protocol = eth_type_trans(skb, dev);
495 netif_rx(skb);
496 dev->stats.rx_packets++;
497 dev->stats.rx_bytes += data_len;
498 }
499 }
500
501 #ifdef CONFIG_SMP
502 /*
503 * On SMP we have the following problem:
504 *
505 * A = smc_hardware_send_pkt()
506 * B = smc_hard_start_xmit()
507 * C = smc_interrupt()
508 *
509 * A and B can never be executed simultaneously. However, at least on UP,
510 * it is possible (and even desirable) for C to interrupt execution of
511 * A or B in order to have better RX reliability and avoid overruns.
512 * C, just like A and B, must have exclusive access to the chip and
513 * each of them must lock against any other concurrent access.
514 * Unfortunately this is not possible to have C suspend execution of A or
515 * B taking place on another CPU. On UP this is no an issue since A and B
516 * are run from softirq context and C from hard IRQ context, and there is
517 * no other CPU where concurrent access can happen.
518 * If ever there is a way to force at least B and C to always be executed
519 * on the same CPU then we could use read/write locks to protect against
520 * any other concurrent access and C would always interrupt B. But life
521 * isn't that easy in a SMP world...
522 */
523 #define smc_special_trylock(lock) \
524 ({ \
525 int __ret; \
526 local_irq_disable(); \
527 __ret = spin_trylock(lock); \
528 if (!__ret) \
529 local_irq_enable(); \
530 __ret; \
531 })
532 #define smc_special_lock(lock) spin_lock_irq(lock)
533 #define smc_special_unlock(lock) spin_unlock_irq(lock)
534 #else
535 #define smc_special_trylock(lock) (1)
536 #define smc_special_lock(lock) do { } while (0)
537 #define smc_special_unlock(lock) do { } while (0)
538 #endif
539
540 /*
541 * This is called to actually send a packet to the chip.
542 */
543 static void smc_hardware_send_pkt(unsigned long data)
544 {
545 struct net_device *dev = (struct net_device *)data;
546 struct smc_local *lp = netdev_priv(dev);
547 void __iomem *ioaddr = lp->base;
548 struct sk_buff *skb;
549 unsigned int packet_no, len;
550 unsigned char *buf;
551
552 DBG(3, "%s: %s\n", dev->name, __func__);
553
554 if (!smc_special_trylock(&lp->lock)) {
555 netif_stop_queue(dev);
556 tasklet_schedule(&lp->tx_task);
557 return;
558 }
559
560 skb = lp->pending_tx_skb;
561 if (unlikely(!skb)) {
562 smc_special_unlock(&lp->lock);
563 return;
564 }
565 lp->pending_tx_skb = NULL;
566
567 packet_no = SMC_GET_AR(lp);
568 if (unlikely(packet_no & AR_FAILED)) {
569 printk("%s: Memory allocation failed.\n", dev->name);
570 dev->stats.tx_errors++;
571 dev->stats.tx_fifo_errors++;
572 smc_special_unlock(&lp->lock);
573 goto done;
574 }
575
576 /* point to the beginning of the packet */
577 SMC_SET_PN(lp, packet_no);
578 SMC_SET_PTR(lp, PTR_AUTOINC);
579
580 buf = skb->data;
581 len = skb->len;
582 DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n",
583 dev->name, packet_no, len, len, buf);
584 PRINT_PKT(buf, len);
585
586 /*
587 * Send the packet length (+6 for status words, length, and ctl.
588 * The card will pad to 64 bytes with zeroes if packet is too small.
589 */
590 SMC_PUT_PKT_HDR(lp, 0, len + 6);
591
592 /* send the actual data */
593 SMC_PUSH_DATA(lp, buf, len & ~1);
594
595 /* Send final ctl word with the last byte if there is one */
596 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
597
598 /*
599 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
600 * have the effect of having at most one packet queued for TX
601 * in the chip's memory at all time.
602 *
603 * If THROTTLE_TX_PKTS is not set then the queue is stopped only
604 * when memory allocation (MC_ALLOC) does not succeed right away.
605 */
606 if (THROTTLE_TX_PKTS)
607 netif_stop_queue(dev);
608
609 /* queue the packet for TX */
610 SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
611 smc_special_unlock(&lp->lock);
612
613 dev->trans_start = jiffies;
614 dev->stats.tx_packets++;
615 dev->stats.tx_bytes += len;
616
617 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
618
619 done: if (!THROTTLE_TX_PKTS)
620 netif_wake_queue(dev);
621
622 dev_kfree_skb(skb);
623 }
624
625 /*
626 * Since I am not sure if I will have enough room in the chip's ram
627 * to store the packet, I call this routine which either sends it
628 * now, or set the card to generates an interrupt when ready
629 * for the packet.
630 */
631 static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
632 {
633 struct smc_local *lp = netdev_priv(dev);
634 void __iomem *ioaddr = lp->base;
635 unsigned int numPages, poll_count, status;
636
637 DBG(3, "%s: %s\n", dev->name, __func__);
638
639 BUG_ON(lp->pending_tx_skb != NULL);
640
641 /*
642 * The MMU wants the number of pages to be the number of 256 bytes
643 * 'pages', minus 1 (since a packet can't ever have 0 pages :))
644 *
645 * The 91C111 ignores the size bits, but earlier models don't.
646 *
647 * Pkt size for allocating is data length +6 (for additional status
648 * words, length and ctl)
649 *
650 * If odd size then last byte is included in ctl word.
651 */
652 numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
653 if (unlikely(numPages > 7)) {
654 printk("%s: Far too big packet error.\n", dev->name);
655 dev->stats.tx_errors++;
656 dev->stats.tx_dropped++;
657 dev_kfree_skb(skb);
658 return 0;
659 }
660
661 smc_special_lock(&lp->lock);
662
663 /* now, try to allocate the memory */
664 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
665
666 /*
667 * Poll the chip for a short amount of time in case the
668 * allocation succeeds quickly.
669 */
670 poll_count = MEMORY_WAIT_TIME;
671 do {
672 status = SMC_GET_INT(lp);
673 if (status & IM_ALLOC_INT) {
674 SMC_ACK_INT(lp, IM_ALLOC_INT);
675 break;
676 }
677 } while (--poll_count);
678
679 smc_special_unlock(&lp->lock);
680
681 lp->pending_tx_skb = skb;
682 if (!poll_count) {
683 /* oh well, wait until the chip finds memory later */
684 netif_stop_queue(dev);
685 DBG(2, "%s: TX memory allocation deferred.\n", dev->name);
686 SMC_ENABLE_INT(lp, IM_ALLOC_INT);
687 } else {
688 /*
689 * Allocation succeeded: push packet to the chip's own memory
690 * immediately.
691 */
692 smc_hardware_send_pkt((unsigned long)dev);
693 }
694
695 return 0;
696 }
697
698 /*
699 * This handles a TX interrupt, which is only called when:
700 * - a TX error occurred, or
701 * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
702 */
703 static void smc_tx(struct net_device *dev)
704 {
705 struct smc_local *lp = netdev_priv(dev);
706 void __iomem *ioaddr = lp->base;
707 unsigned int saved_packet, packet_no, tx_status, pkt_len;
708
709 DBG(3, "%s: %s\n", dev->name, __func__);
710
711 /* If the TX FIFO is empty then nothing to do */
712 packet_no = SMC_GET_TXFIFO(lp);
713 if (unlikely(packet_no & TXFIFO_TEMPTY)) {
714 PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
715 return;
716 }
717
718 /* select packet to read from */
719 saved_packet = SMC_GET_PN(lp);
720 SMC_SET_PN(lp, packet_no);
721
722 /* read the first word (status word) from this packet */
723 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
724 SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
725 DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
726 dev->name, tx_status, packet_no);
727
728 if (!(tx_status & ES_TX_SUC))
729 dev->stats.tx_errors++;
730
731 if (tx_status & ES_LOSTCARR)
732 dev->stats.tx_carrier_errors++;
733
734 if (tx_status & (ES_LATCOL | ES_16COL)) {
735 PRINTK("%s: %s occurred on last xmit\n", dev->name,
736 (tx_status & ES_LATCOL) ?
737 "late collision" : "too many collisions");
738 dev->stats.tx_window_errors++;
739 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
740 printk(KERN_INFO "%s: unexpectedly large number of "
741 "bad collisions. Please check duplex "
742 "setting.\n", dev->name);
743 }
744 }
745
746 /* kill the packet */
747 SMC_WAIT_MMU_BUSY(lp);
748 SMC_SET_MMU_CMD(lp, MC_FREEPKT);
749
750 /* Don't restore Packet Number Reg until busy bit is cleared */
751 SMC_WAIT_MMU_BUSY(lp);
752 SMC_SET_PN(lp, saved_packet);
753
754 /* re-enable transmit */
755 SMC_SELECT_BANK(lp, 0);
756 SMC_SET_TCR(lp, lp->tcr_cur_mode);
757 SMC_SELECT_BANK(lp, 2);
758 }
759
760
761 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
762
763 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
764 {
765 struct smc_local *lp = netdev_priv(dev);
766 void __iomem *ioaddr = lp->base;
767 unsigned int mii_reg, mask;
768
769 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
770 mii_reg |= MII_MDOE;
771
772 for (mask = 1 << (bits - 1); mask; mask >>= 1) {
773 if (val & mask)
774 mii_reg |= MII_MDO;
775 else
776 mii_reg &= ~MII_MDO;
777
778 SMC_SET_MII(lp, mii_reg);
779 udelay(MII_DELAY);
780 SMC_SET_MII(lp, mii_reg | MII_MCLK);
781 udelay(MII_DELAY);
782 }
783 }
784
785 static unsigned int smc_mii_in(struct net_device *dev, int bits)
786 {
787 struct smc_local *lp = netdev_priv(dev);
788 void __iomem *ioaddr = lp->base;
789 unsigned int mii_reg, mask, val;
790
791 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
792 SMC_SET_MII(lp, mii_reg);
793
794 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
795 if (SMC_GET_MII(lp) & MII_MDI)
796 val |= mask;
797
798 SMC_SET_MII(lp, mii_reg);
799 udelay(MII_DELAY);
800 SMC_SET_MII(lp, mii_reg | MII_MCLK);
801 udelay(MII_DELAY);
802 }
803
804 return val;
805 }
806
807 /*
808 * Reads a register from the MII Management serial interface
809 */
810 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
811 {
812 struct smc_local *lp = netdev_priv(dev);
813 void __iomem *ioaddr = lp->base;
814 unsigned int phydata;
815
816 SMC_SELECT_BANK(lp, 3);
817
818 /* Idle - 32 ones */
819 smc_mii_out(dev, 0xffffffff, 32);
820
821 /* Start code (01) + read (10) + phyaddr + phyreg */
822 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
823
824 /* Turnaround (2bits) + phydata */
825 phydata = smc_mii_in(dev, 18);
826
827 /* Return to idle state */
828 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
829
830 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
831 __func__, phyaddr, phyreg, phydata);
832
833 SMC_SELECT_BANK(lp, 2);
834 return phydata;
835 }
836
837 /*
838 * Writes a register to the MII Management serial interface
839 */
840 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
841 int phydata)
842 {
843 struct smc_local *lp = netdev_priv(dev);
844 void __iomem *ioaddr = lp->base;
845
846 SMC_SELECT_BANK(lp, 3);
847
848 /* Idle - 32 ones */
849 smc_mii_out(dev, 0xffffffff, 32);
850
851 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
852 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
853
854 /* Return to idle state */
855 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
856
857 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
858 __func__, phyaddr, phyreg, phydata);
859
860 SMC_SELECT_BANK(lp, 2);
861 }
862
863 /*
864 * Finds and reports the PHY address
865 */
866 static void smc_phy_detect(struct net_device *dev)
867 {
868 struct smc_local *lp = netdev_priv(dev);
869 int phyaddr;
870
871 DBG(2, "%s: %s\n", dev->name, __func__);
872
873 lp->phy_type = 0;
874
875 /*
876 * Scan all 32 PHY addresses if necessary, starting at
877 * PHY#1 to PHY#31, and then PHY#0 last.
878 */
879 for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
880 unsigned int id1, id2;
881
882 /* Read the PHY identifiers */
883 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1);
884 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2);
885
886 DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n",
887 dev->name, id1, id2);
888
889 /* Make sure it is a valid identifier */
890 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
891 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
892 /* Save the PHY's address */
893 lp->mii.phy_id = phyaddr & 31;
894 lp->phy_type = id1 << 16 | id2;
895 break;
896 }
897 }
898 }
899
900 /*
901 * Sets the PHY to a configuration as determined by the user
902 */
903 static int smc_phy_fixed(struct net_device *dev)
904 {
905 struct smc_local *lp = netdev_priv(dev);
906 void __iomem *ioaddr = lp->base;
907 int phyaddr = lp->mii.phy_id;
908 int bmcr, cfg1;
909
910 DBG(3, "%s: %s\n", dev->name, __func__);
911
912 /* Enter Link Disable state */
913 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
914 cfg1 |= PHY_CFG1_LNKDIS;
915 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
916
917 /*
918 * Set our fixed capabilities
919 * Disable auto-negotiation
920 */
921 bmcr = 0;
922
923 if (lp->ctl_rfduplx)
924 bmcr |= BMCR_FULLDPLX;
925
926 if (lp->ctl_rspeed == 100)
927 bmcr |= BMCR_SPEED100;
928
929 /* Write our capabilities to the phy control register */
930 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
931
932 /* Re-Configure the Receive/Phy Control register */
933 SMC_SELECT_BANK(lp, 0);
934 SMC_SET_RPC(lp, lp->rpc_cur_mode);
935 SMC_SELECT_BANK(lp, 2);
936
937 return 1;
938 }
939
940 /*
941 * smc_phy_reset - reset the phy
942 * @dev: net device
943 * @phy: phy address
944 *
945 * Issue a software reset for the specified PHY and
946 * wait up to 100ms for the reset to complete. We should
947 * not access the PHY for 50ms after issuing the reset.
948 *
949 * The time to wait appears to be dependent on the PHY.
950 *
951 * Must be called with lp->lock locked.
952 */
953 static int smc_phy_reset(struct net_device *dev, int phy)
954 {
955 struct smc_local *lp = netdev_priv(dev);
956 unsigned int bmcr;
957 int timeout;
958
959 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
960
961 for (timeout = 2; timeout; timeout--) {
962 spin_unlock_irq(&lp->lock);
963 msleep(50);
964 spin_lock_irq(&lp->lock);
965
966 bmcr = smc_phy_read(dev, phy, MII_BMCR);
967 if (!(bmcr & BMCR_RESET))
968 break;
969 }
970
971 return bmcr & BMCR_RESET;
972 }
973
974 /*
975 * smc_phy_powerdown - powerdown phy
976 * @dev: net device
977 *
978 * Power down the specified PHY
979 */
980 static void smc_phy_powerdown(struct net_device *dev)
981 {
982 struct smc_local *lp = netdev_priv(dev);
983 unsigned int bmcr;
984 int phy = lp->mii.phy_id;
985
986 if (lp->phy_type == 0)
987 return;
988
989 /* We need to ensure that no calls to smc_phy_configure are
990 pending.
991 */
992 cancel_work_sync(&lp->phy_configure);
993
994 bmcr = smc_phy_read(dev, phy, MII_BMCR);
995 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
996 }
997
998 /*
999 * smc_phy_check_media - check the media status and adjust TCR
1000 * @dev: net device
1001 * @init: set true for initialisation
1002 *
1003 * Select duplex mode depending on negotiation state. This
1004 * also updates our carrier state.
1005 */
1006 static void smc_phy_check_media(struct net_device *dev, int init)
1007 {
1008 struct smc_local *lp = netdev_priv(dev);
1009 void __iomem *ioaddr = lp->base;
1010
1011 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
1012 /* duplex state has changed */
1013 if (lp->mii.full_duplex) {
1014 lp->tcr_cur_mode |= TCR_SWFDUP;
1015 } else {
1016 lp->tcr_cur_mode &= ~TCR_SWFDUP;
1017 }
1018
1019 SMC_SELECT_BANK(lp, 0);
1020 SMC_SET_TCR(lp, lp->tcr_cur_mode);
1021 }
1022 }
1023
1024 /*
1025 * Configures the specified PHY through the MII management interface
1026 * using Autonegotiation.
1027 * Calls smc_phy_fixed() if the user has requested a certain config.
1028 * If RPC ANEG bit is set, the media selection is dependent purely on
1029 * the selection by the MII (either in the MII BMCR reg or the result
1030 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
1031 * is controlled by the RPC SPEED and RPC DPLX bits.
1032 */
1033 static void smc_phy_configure(struct work_struct *work)
1034 {
1035 struct smc_local *lp =
1036 container_of(work, struct smc_local, phy_configure);
1037 struct net_device *dev = lp->dev;
1038 void __iomem *ioaddr = lp->base;
1039 int phyaddr = lp->mii.phy_id;
1040 int my_phy_caps; /* My PHY capabilities */
1041 int my_ad_caps; /* My Advertised capabilities */
1042 int status;
1043
1044 DBG(3, "%s:smc_program_phy()\n", dev->name);
1045
1046 spin_lock_irq(&lp->lock);
1047
1048 /*
1049 * We should not be called if phy_type is zero.
1050 */
1051 if (lp->phy_type == 0)
1052 goto smc_phy_configure_exit;
1053
1054 if (smc_phy_reset(dev, phyaddr)) {
1055 printk("%s: PHY reset timed out\n", dev->name);
1056 goto smc_phy_configure_exit;
1057 }
1058
1059 /*
1060 * Enable PHY Interrupts (for register 18)
1061 * Interrupts listed here are disabled
1062 */
1063 smc_phy_write(dev, phyaddr, PHY_MASK_REG,
1064 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
1065 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
1066 PHY_INT_SPDDET | PHY_INT_DPLXDET);
1067
1068 /* Configure the Receive/Phy Control register */
1069 SMC_SELECT_BANK(lp, 0);
1070 SMC_SET_RPC(lp, lp->rpc_cur_mode);
1071
1072 /* If the user requested no auto neg, then go set his request */
1073 if (lp->mii.force_media) {
1074 smc_phy_fixed(dev);
1075 goto smc_phy_configure_exit;
1076 }
1077
1078 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
1079 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
1080
1081 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
1082 printk(KERN_INFO "Auto negotiation NOT supported\n");
1083 smc_phy_fixed(dev);
1084 goto smc_phy_configure_exit;
1085 }
1086
1087 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
1088
1089 if (my_phy_caps & BMSR_100BASE4)
1090 my_ad_caps |= ADVERTISE_100BASE4;
1091 if (my_phy_caps & BMSR_100FULL)
1092 my_ad_caps |= ADVERTISE_100FULL;
1093 if (my_phy_caps & BMSR_100HALF)
1094 my_ad_caps |= ADVERTISE_100HALF;
1095 if (my_phy_caps & BMSR_10FULL)
1096 my_ad_caps |= ADVERTISE_10FULL;
1097 if (my_phy_caps & BMSR_10HALF)
1098 my_ad_caps |= ADVERTISE_10HALF;
1099
1100 /* Disable capabilities not selected by our user */
1101 if (lp->ctl_rspeed != 100)
1102 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
1103
1104 if (!lp->ctl_rfduplx)
1105 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1106
1107 /* Update our Auto-Neg Advertisement Register */
1108 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
1109 lp->mii.advertising = my_ad_caps;
1110
1111 /*
1112 * Read the register back. Without this, it appears that when
1113 * auto-negotiation is restarted, sometimes it isn't ready and
1114 * the link does not come up.
1115 */
1116 status = smc_phy_read(dev, phyaddr, MII_ADVERTISE);
1117
1118 DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps);
1119 DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps);
1120
1121 /* Restart auto-negotiation process in order to advertise my caps */
1122 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1123
1124 smc_phy_check_media(dev, 1);
1125
1126 smc_phy_configure_exit:
1127 SMC_SELECT_BANK(lp, 2);
1128 spin_unlock_irq(&lp->lock);
1129 }
1130
1131 /*
1132 * smc_phy_interrupt
1133 *
1134 * Purpose: Handle interrupts relating to PHY register 18. This is
1135 * called from the "hard" interrupt handler under our private spinlock.
1136 */
1137 static void smc_phy_interrupt(struct net_device *dev)
1138 {
1139 struct smc_local *lp = netdev_priv(dev);
1140 int phyaddr = lp->mii.phy_id;
1141 int phy18;
1142
1143 DBG(2, "%s: %s\n", dev->name, __func__);
1144
1145 if (lp->phy_type == 0)
1146 return;
1147
1148 for(;;) {
1149 smc_phy_check_media(dev, 0);
1150
1151 /* Read PHY Register 18, Status Output */
1152 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG);
1153 if ((phy18 & PHY_INT_INT) == 0)
1154 break;
1155 }
1156 }
1157
1158 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1159
1160 static void smc_10bt_check_media(struct net_device *dev, int init)
1161 {
1162 struct smc_local *lp = netdev_priv(dev);
1163 void __iomem *ioaddr = lp->base;
1164 unsigned int old_carrier, new_carrier;
1165
1166 old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1167
1168 SMC_SELECT_BANK(lp, 0);
1169 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
1170 SMC_SELECT_BANK(lp, 2);
1171
1172 if (init || (old_carrier != new_carrier)) {
1173 if (!new_carrier) {
1174 netif_carrier_off(dev);
1175 } else {
1176 netif_carrier_on(dev);
1177 }
1178 if (netif_msg_link(lp))
1179 printk(KERN_INFO "%s: link %s\n", dev->name,
1180 new_carrier ? "up" : "down");
1181 }
1182 }
1183
1184 static void smc_eph_interrupt(struct net_device *dev)
1185 {
1186 struct smc_local *lp = netdev_priv(dev);
1187 void __iomem *ioaddr = lp->base;
1188 unsigned int ctl;
1189
1190 smc_10bt_check_media(dev, 0);
1191
1192 SMC_SELECT_BANK(lp, 1);
1193 ctl = SMC_GET_CTL(lp);
1194 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
1195 SMC_SET_CTL(lp, ctl);
1196 SMC_SELECT_BANK(lp, 2);
1197 }
1198
1199 /*
1200 * This is the main routine of the driver, to handle the device when
1201 * it needs some attention.
1202 */
1203 static irqreturn_t smc_interrupt(int irq, void *dev_id)
1204 {
1205 struct net_device *dev = dev_id;
1206 struct smc_local *lp = netdev_priv(dev);
1207 void __iomem *ioaddr = lp->base;
1208 int status, mask, timeout, card_stats;
1209 int saved_pointer;
1210
1211 DBG(3, "%s: %s\n", dev->name, __func__);
1212
1213 spin_lock(&lp->lock);
1214
1215 /* A preamble may be used when there is a potential race
1216 * between the interruptible transmit functions and this
1217 * ISR. */
1218 SMC_INTERRUPT_PREAMBLE;
1219
1220 saved_pointer = SMC_GET_PTR(lp);
1221 mask = SMC_GET_INT_MASK(lp);
1222 SMC_SET_INT_MASK(lp, 0);
1223
1224 /* set a timeout value, so I don't stay here forever */
1225 timeout = MAX_IRQ_LOOPS;
1226
1227 do {
1228 status = SMC_GET_INT(lp);
1229
1230 DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
1231 dev->name, status, mask,
1232 ({ int meminfo; SMC_SELECT_BANK(lp, 0);
1233 meminfo = SMC_GET_MIR(lp);
1234 SMC_SELECT_BANK(lp, 2); meminfo; }),
1235 SMC_GET_FIFO(lp));
1236
1237 status &= mask;
1238 if (!status)
1239 break;
1240
1241 if (status & IM_TX_INT) {
1242 /* do this before RX as it will free memory quickly */
1243 DBG(3, "%s: TX int\n", dev->name);
1244 smc_tx(dev);
1245 SMC_ACK_INT(lp, IM_TX_INT);
1246 if (THROTTLE_TX_PKTS)
1247 netif_wake_queue(dev);
1248 } else if (status & IM_RCV_INT) {
1249 DBG(3, "%s: RX irq\n", dev->name);
1250 smc_rcv(dev);
1251 } else if (status & IM_ALLOC_INT) {
1252 DBG(3, "%s: Allocation irq\n", dev->name);
1253 tasklet_hi_schedule(&lp->tx_task);
1254 mask &= ~IM_ALLOC_INT;
1255 } else if (status & IM_TX_EMPTY_INT) {
1256 DBG(3, "%s: TX empty\n", dev->name);
1257 mask &= ~IM_TX_EMPTY_INT;
1258
1259 /* update stats */
1260 SMC_SELECT_BANK(lp, 0);
1261 card_stats = SMC_GET_COUNTER(lp);
1262 SMC_SELECT_BANK(lp, 2);
1263
1264 /* single collisions */
1265 dev->stats.collisions += card_stats & 0xF;
1266 card_stats >>= 4;
1267
1268 /* multiple collisions */
1269 dev->stats.collisions += card_stats & 0xF;
1270 } else if (status & IM_RX_OVRN_INT) {
1271 DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name,
1272 ({ int eph_st; SMC_SELECT_BANK(lp, 0);
1273 eph_st = SMC_GET_EPH_STATUS(lp);
1274 SMC_SELECT_BANK(lp, 2); eph_st; }));
1275 SMC_ACK_INT(lp, IM_RX_OVRN_INT);
1276 dev->stats.rx_errors++;
1277 dev->stats.rx_fifo_errors++;
1278 } else if (status & IM_EPH_INT) {
1279 smc_eph_interrupt(dev);
1280 } else if (status & IM_MDINT) {
1281 SMC_ACK_INT(lp, IM_MDINT);
1282 smc_phy_interrupt(dev);
1283 } else if (status & IM_ERCV_INT) {
1284 SMC_ACK_INT(lp, IM_ERCV_INT);
1285 PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name);
1286 }
1287 } while (--timeout);
1288
1289 /* restore register states */
1290 SMC_SET_PTR(lp, saved_pointer);
1291 SMC_SET_INT_MASK(lp, mask);
1292 spin_unlock(&lp->lock);
1293
1294 #ifndef CONFIG_NET_POLL_CONTROLLER
1295 if (timeout == MAX_IRQ_LOOPS)
1296 PRINTK("%s: spurious interrupt (mask = 0x%02x)\n",
1297 dev->name, mask);
1298 #endif
1299 DBG(3, "%s: Interrupt done (%d loops)\n",
1300 dev->name, MAX_IRQ_LOOPS - timeout);
1301
1302 /*
1303 * We return IRQ_HANDLED unconditionally here even if there was
1304 * nothing to do. There is a possibility that a packet might
1305 * get enqueued into the chip right after TX_EMPTY_INT is raised
1306 * but just before the CPU acknowledges the IRQ.
1307 * Better take an unneeded IRQ in some occasions than complexifying
1308 * the code for all cases.
1309 */
1310 return IRQ_HANDLED;
1311 }
1312
1313 #ifdef CONFIG_NET_POLL_CONTROLLER
1314 /*
1315 * Polling receive - used by netconsole and other diagnostic tools
1316 * to allow network i/o with interrupts disabled.
1317 */
1318 static void smc_poll_controller(struct net_device *dev)
1319 {
1320 disable_irq(dev->irq);
1321 smc_interrupt(dev->irq, dev);
1322 enable_irq(dev->irq);
1323 }
1324 #endif
1325
1326 /* Our watchdog timed out. Called by the networking layer */
1327 static void smc_timeout(struct net_device *dev)
1328 {
1329 struct smc_local *lp = netdev_priv(dev);
1330 void __iomem *ioaddr = lp->base;
1331 int status, mask, eph_st, meminfo, fifo;
1332
1333 DBG(2, "%s: %s\n", dev->name, __func__);
1334
1335 spin_lock_irq(&lp->lock);
1336 status = SMC_GET_INT(lp);
1337 mask = SMC_GET_INT_MASK(lp);
1338 fifo = SMC_GET_FIFO(lp);
1339 SMC_SELECT_BANK(lp, 0);
1340 eph_st = SMC_GET_EPH_STATUS(lp);
1341 meminfo = SMC_GET_MIR(lp);
1342 SMC_SELECT_BANK(lp, 2);
1343 spin_unlock_irq(&lp->lock);
1344 PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x "
1345 "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
1346 dev->name, status, mask, meminfo, fifo, eph_st );
1347
1348 smc_reset(dev);
1349 smc_enable(dev);
1350
1351 /*
1352 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1353 * smc_phy_configure() calls msleep() which calls schedule_timeout()
1354 * which calls schedule(). Hence we use a work queue.
1355 */
1356 if (lp->phy_type != 0)
1357 schedule_work(&lp->phy_configure);
1358
1359 /* We can accept TX packets again */
1360 dev->trans_start = jiffies;
1361 netif_wake_queue(dev);
1362 }
1363
1364 /*
1365 * This routine will, depending on the values passed to it,
1366 * either make it accept multicast packets, go into
1367 * promiscuous mode (for TCPDUMP and cousins) or accept
1368 * a select set of multicast packets
1369 */
1370 static void smc_set_multicast_list(struct net_device *dev)
1371 {
1372 struct smc_local *lp = netdev_priv(dev);
1373 void __iomem *ioaddr = lp->base;
1374 unsigned char multicast_table[8];
1375 int update_multicast = 0;
1376
1377 DBG(2, "%s: %s\n", dev->name, __func__);
1378
1379 if (dev->flags & IFF_PROMISC) {
1380 DBG(2, "%s: RCR_PRMS\n", dev->name);
1381 lp->rcr_cur_mode |= RCR_PRMS;
1382 }
1383
1384 /* BUG? I never disable promiscuous mode if multicasting was turned on.
1385 Now, I turn off promiscuous mode, but I don't do anything to multicasting
1386 when promiscuous mode is turned on.
1387 */
1388
1389 /*
1390 * Here, I am setting this to accept all multicast packets.
1391 * I don't need to zero the multicast table, because the flag is
1392 * checked before the table is
1393 */
1394 else if (dev->flags & IFF_ALLMULTI || dev->mc_count > 16) {
1395 DBG(2, "%s: RCR_ALMUL\n", dev->name);
1396 lp->rcr_cur_mode |= RCR_ALMUL;
1397 }
1398
1399 /*
1400 * This sets the internal hardware table to filter out unwanted
1401 * multicast packets before they take up memory.
1402 *
1403 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1404 * address are the offset into the table. If that bit is 1, then the
1405 * multicast packet is accepted. Otherwise, it's dropped silently.
1406 *
1407 * To use the 6 bits as an offset into the table, the high 3 bits are
1408 * the number of the 8 bit register, while the low 3 bits are the bit
1409 * within that register.
1410 */
1411 else if (dev->mc_count) {
1412 int i;
1413 struct dev_mc_list *cur_addr;
1414
1415 /* table for flipping the order of 3 bits */
1416 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
1417
1418 /* start with a table of all zeros: reject all */
1419 memset(multicast_table, 0, sizeof(multicast_table));
1420
1421 cur_addr = dev->mc_list;
1422 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
1423 int position;
1424
1425 /* do we have a pointer here? */
1426 if (!cur_addr)
1427 break;
1428 /* make sure this is a multicast address -
1429 shouldn't this be a given if we have it here ? */
1430 if (!(*cur_addr->dmi_addr & 1))
1431 continue;
1432
1433 /* only use the low order bits */
1434 position = crc32_le(~0, cur_addr->dmi_addr, 6) & 0x3f;
1435
1436 /* do some messy swapping to put the bit in the right spot */
1437 multicast_table[invert3[position&7]] |=
1438 (1<<invert3[(position>>3)&7]);
1439 }
1440
1441 /* be sure I get rid of flags I might have set */
1442 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1443
1444 /* now, the table can be loaded into the chipset */
1445 update_multicast = 1;
1446 } else {
1447 DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name);
1448 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1449
1450 /*
1451 * since I'm disabling all multicast entirely, I need to
1452 * clear the multicast list
1453 */
1454 memset(multicast_table, 0, sizeof(multicast_table));
1455 update_multicast = 1;
1456 }
1457
1458 spin_lock_irq(&lp->lock);
1459 SMC_SELECT_BANK(lp, 0);
1460 SMC_SET_RCR(lp, lp->rcr_cur_mode);
1461 if (update_multicast) {
1462 SMC_SELECT_BANK(lp, 3);
1463 SMC_SET_MCAST(lp, multicast_table);
1464 }
1465 SMC_SELECT_BANK(lp, 2);
1466 spin_unlock_irq(&lp->lock);
1467 }
1468
1469
1470 /*
1471 * Open and Initialize the board
1472 *
1473 * Set up everything, reset the card, etc..
1474 */
1475 static int
1476 smc_open(struct net_device *dev)
1477 {
1478 struct smc_local *lp = netdev_priv(dev);
1479
1480 DBG(2, "%s: %s\n", dev->name, __func__);
1481
1482 /*
1483 * Check that the address is valid. If its not, refuse
1484 * to bring the device up. The user must specify an
1485 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1486 */
1487 if (!is_valid_ether_addr(dev->dev_addr)) {
1488 PRINTK("%s: no valid ethernet hw addr\n", __func__);
1489 return -EINVAL;
1490 }
1491
1492 /* Setup the default Register Modes */
1493 lp->tcr_cur_mode = TCR_DEFAULT;
1494 lp->rcr_cur_mode = RCR_DEFAULT;
1495 lp->rpc_cur_mode = RPC_DEFAULT |
1496 lp->cfg.leda << RPC_LSXA_SHFT |
1497 lp->cfg.ledb << RPC_LSXB_SHFT;
1498
1499 /*
1500 * If we are not using a MII interface, we need to
1501 * monitor our own carrier signal to detect faults.
1502 */
1503 if (lp->phy_type == 0)
1504 lp->tcr_cur_mode |= TCR_MON_CSN;
1505
1506 /* reset the hardware */
1507 smc_reset(dev);
1508 smc_enable(dev);
1509
1510 /* Configure the PHY, initialize the link state */
1511 if (lp->phy_type != 0)
1512 smc_phy_configure(&lp->phy_configure);
1513 else {
1514 spin_lock_irq(&lp->lock);
1515 smc_10bt_check_media(dev, 1);
1516 spin_unlock_irq(&lp->lock);
1517 }
1518
1519 netif_start_queue(dev);
1520 return 0;
1521 }
1522
1523 /*
1524 * smc_close
1525 *
1526 * this makes the board clean up everything that it can
1527 * and not talk to the outside world. Caused by
1528 * an 'ifconfig ethX down'
1529 */
1530 static int smc_close(struct net_device *dev)
1531 {
1532 struct smc_local *lp = netdev_priv(dev);
1533
1534 DBG(2, "%s: %s\n", dev->name, __func__);
1535
1536 netif_stop_queue(dev);
1537 netif_carrier_off(dev);
1538
1539 /* clear everything */
1540 smc_shutdown(dev);
1541 tasklet_kill(&lp->tx_task);
1542 smc_phy_powerdown(dev);
1543 return 0;
1544 }
1545
1546 /*
1547 * Ethtool support
1548 */
1549 static int
1550 smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1551 {
1552 struct smc_local *lp = netdev_priv(dev);
1553 int ret;
1554
1555 cmd->maxtxpkt = 1;
1556 cmd->maxrxpkt = 1;
1557
1558 if (lp->phy_type != 0) {
1559 spin_lock_irq(&lp->lock);
1560 ret = mii_ethtool_gset(&lp->mii, cmd);
1561 spin_unlock_irq(&lp->lock);
1562 } else {
1563 cmd->supported = SUPPORTED_10baseT_Half |
1564 SUPPORTED_10baseT_Full |
1565 SUPPORTED_TP | SUPPORTED_AUI;
1566
1567 if (lp->ctl_rspeed == 10)
1568 cmd->speed = SPEED_10;
1569 else if (lp->ctl_rspeed == 100)
1570 cmd->speed = SPEED_100;
1571
1572 cmd->autoneg = AUTONEG_DISABLE;
1573 cmd->transceiver = XCVR_INTERNAL;
1574 cmd->port = 0;
1575 cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF;
1576
1577 ret = 0;
1578 }
1579
1580 return ret;
1581 }
1582
1583 static int
1584 smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1585 {
1586 struct smc_local *lp = netdev_priv(dev);
1587 int ret;
1588
1589 if (lp->phy_type != 0) {
1590 spin_lock_irq(&lp->lock);
1591 ret = mii_ethtool_sset(&lp->mii, cmd);
1592 spin_unlock_irq(&lp->lock);
1593 } else {
1594 if (cmd->autoneg != AUTONEG_DISABLE ||
1595 cmd->speed != SPEED_10 ||
1596 (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
1597 (cmd->port != PORT_TP && cmd->port != PORT_AUI))
1598 return -EINVAL;
1599
1600 // lp->port = cmd->port;
1601 lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
1602
1603 // if (netif_running(dev))
1604 // smc_set_port(dev);
1605
1606 ret = 0;
1607 }
1608
1609 return ret;
1610 }
1611
1612 static void
1613 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1614 {
1615 strncpy(info->driver, CARDNAME, sizeof(info->driver));
1616 strncpy(info->version, version, sizeof(info->version));
1617 strncpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
1618 }
1619
1620 static int smc_ethtool_nwayreset(struct net_device *dev)
1621 {
1622 struct smc_local *lp = netdev_priv(dev);
1623 int ret = -EINVAL;
1624
1625 if (lp->phy_type != 0) {
1626 spin_lock_irq(&lp->lock);
1627 ret = mii_nway_restart(&lp->mii);
1628 spin_unlock_irq(&lp->lock);
1629 }
1630
1631 return ret;
1632 }
1633
1634 static u32 smc_ethtool_getmsglevel(struct net_device *dev)
1635 {
1636 struct smc_local *lp = netdev_priv(dev);
1637 return lp->msg_enable;
1638 }
1639
1640 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level)
1641 {
1642 struct smc_local *lp = netdev_priv(dev);
1643 lp->msg_enable = level;
1644 }
1645
1646 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word)
1647 {
1648 u16 ctl;
1649 struct smc_local *lp = netdev_priv(dev);
1650 void __iomem *ioaddr = lp->base;
1651
1652 spin_lock_irq(&lp->lock);
1653 /* load word into GP register */
1654 SMC_SELECT_BANK(lp, 1);
1655 SMC_SET_GP(lp, word);
1656 /* set the address to put the data in EEPROM */
1657 SMC_SELECT_BANK(lp, 2);
1658 SMC_SET_PTR(lp, addr);
1659 /* tell it to write */
1660 SMC_SELECT_BANK(lp, 1);
1661 ctl = SMC_GET_CTL(lp);
1662 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE));
1663 /* wait for it to finish */
1664 do {
1665 udelay(1);
1666 } while (SMC_GET_CTL(lp) & CTL_STORE);
1667 /* clean up */
1668 SMC_SET_CTL(lp, ctl);
1669 SMC_SELECT_BANK(lp, 2);
1670 spin_unlock_irq(&lp->lock);
1671 return 0;
1672 }
1673
1674 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word)
1675 {
1676 u16 ctl;
1677 struct smc_local *lp = netdev_priv(dev);
1678 void __iomem *ioaddr = lp->base;
1679
1680 spin_lock_irq(&lp->lock);
1681 /* set the EEPROM address to get the data from */
1682 SMC_SELECT_BANK(lp, 2);
1683 SMC_SET_PTR(lp, addr | PTR_READ);
1684 /* tell it to load */
1685 SMC_SELECT_BANK(lp, 1);
1686 SMC_SET_GP(lp, 0xffff); /* init to known */
1687 ctl = SMC_GET_CTL(lp);
1688 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD));
1689 /* wait for it to finish */
1690 do {
1691 udelay(1);
1692 } while (SMC_GET_CTL(lp) & CTL_RELOAD);
1693 /* read word from GP register */
1694 *word = SMC_GET_GP(lp);
1695 /* clean up */
1696 SMC_SET_CTL(lp, ctl);
1697 SMC_SELECT_BANK(lp, 2);
1698 spin_unlock_irq(&lp->lock);
1699 return 0;
1700 }
1701
1702 static int smc_ethtool_geteeprom_len(struct net_device *dev)
1703 {
1704 return 0x23 * 2;
1705 }
1706
1707 static int smc_ethtool_geteeprom(struct net_device *dev,
1708 struct ethtool_eeprom *eeprom, u8 *data)
1709 {
1710 int i;
1711 int imax;
1712
1713 DBG(1, "Reading %d bytes at %d(0x%x)\n",
1714 eeprom->len, eeprom->offset, eeprom->offset);
1715 imax = smc_ethtool_geteeprom_len(dev);
1716 for (i = 0; i < eeprom->len; i += 2) {
1717 int ret;
1718 u16 wbuf;
1719 int offset = i + eeprom->offset;
1720 if (offset > imax)
1721 break;
1722 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf);
1723 if (ret != 0)
1724 return ret;
1725 DBG(2, "Read 0x%x from 0x%x\n", wbuf, offset >> 1);
1726 data[i] = (wbuf >> 8) & 0xff;
1727 data[i+1] = wbuf & 0xff;
1728 }
1729 return 0;
1730 }
1731
1732 static int smc_ethtool_seteeprom(struct net_device *dev,
1733 struct ethtool_eeprom *eeprom, u8 *data)
1734 {
1735 int i;
1736 int imax;
1737
1738 DBG(1, "Writing %d bytes to %d(0x%x)\n",
1739 eeprom->len, eeprom->offset, eeprom->offset);
1740 imax = smc_ethtool_geteeprom_len(dev);
1741 for (i = 0; i < eeprom->len; i += 2) {
1742 int ret;
1743 u16 wbuf;
1744 int offset = i + eeprom->offset;
1745 if (offset > imax)
1746 break;
1747 wbuf = (data[i] << 8) | data[i + 1];
1748 DBG(2, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1);
1749 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf);
1750 if (ret != 0)
1751 return ret;
1752 }
1753 return 0;
1754 }
1755
1756
1757 static const struct ethtool_ops smc_ethtool_ops = {
1758 .get_settings = smc_ethtool_getsettings,
1759 .set_settings = smc_ethtool_setsettings,
1760 .get_drvinfo = smc_ethtool_getdrvinfo,
1761
1762 .get_msglevel = smc_ethtool_getmsglevel,
1763 .set_msglevel = smc_ethtool_setmsglevel,
1764 .nway_reset = smc_ethtool_nwayreset,
1765 .get_link = ethtool_op_get_link,
1766 .get_eeprom_len = smc_ethtool_geteeprom_len,
1767 .get_eeprom = smc_ethtool_geteeprom,
1768 .set_eeprom = smc_ethtool_seteeprom,
1769 };
1770
1771 static const struct net_device_ops smc_netdev_ops = {
1772 .ndo_open = smc_open,
1773 .ndo_stop = smc_close,
1774 .ndo_start_xmit = smc_hard_start_xmit,
1775 .ndo_tx_timeout = smc_timeout,
1776 .ndo_set_multicast_list = smc_set_multicast_list,
1777 .ndo_validate_addr = eth_validate_addr,
1778 .ndo_set_mac_address = eth_mac_addr,
1779 #ifdef CONFIG_NET_POLL_CONTROLLER
1780 .ndo_poll_controller = smc_poll_controller,
1781 #endif
1782 };
1783
1784 /*
1785 * smc_findirq
1786 *
1787 * This routine has a simple purpose -- make the SMC chip generate an
1788 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1789 */
1790 /*
1791 * does this still work?
1792 *
1793 * I just deleted auto_irq.c, since it was never built...
1794 * --jgarzik
1795 */
1796 static int __devinit smc_findirq(struct smc_local *lp)
1797 {
1798 void __iomem *ioaddr = lp->base;
1799 int timeout = 20;
1800 unsigned long cookie;
1801
1802 DBG(2, "%s: %s\n", CARDNAME, __func__);
1803
1804 cookie = probe_irq_on();
1805
1806 /*
1807 * What I try to do here is trigger an ALLOC_INT. This is done
1808 * by allocating a small chunk of memory, which will give an interrupt
1809 * when done.
1810 */
1811 /* enable ALLOCation interrupts ONLY */
1812 SMC_SELECT_BANK(lp, 2);
1813 SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
1814
1815 /*
1816 * Allocate 512 bytes of memory. Note that the chip was just
1817 * reset so all the memory is available
1818 */
1819 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
1820
1821 /*
1822 * Wait until positive that the interrupt has been generated
1823 */
1824 do {
1825 int int_status;
1826 udelay(10);
1827 int_status = SMC_GET_INT(lp);
1828 if (int_status & IM_ALLOC_INT)
1829 break; /* got the interrupt */
1830 } while (--timeout);
1831
1832 /*
1833 * there is really nothing that I can do here if timeout fails,
1834 * as autoirq_report will return a 0 anyway, which is what I
1835 * want in this case. Plus, the clean up is needed in both
1836 * cases.
1837 */
1838
1839 /* and disable all interrupts again */
1840 SMC_SET_INT_MASK(lp, 0);
1841
1842 /* and return what I found */
1843 return probe_irq_off(cookie);
1844 }
1845
1846 /*
1847 * Function: smc_probe(unsigned long ioaddr)
1848 *
1849 * Purpose:
1850 * Tests to see if a given ioaddr points to an SMC91x chip.
1851 * Returns a 0 on success
1852 *
1853 * Algorithm:
1854 * (1) see if the high byte of BANK_SELECT is 0x33
1855 * (2) compare the ioaddr with the base register's address
1856 * (3) see if I recognize the chip ID in the appropriate register
1857 *
1858 * Here I do typical initialization tasks.
1859 *
1860 * o Initialize the structure if needed
1861 * o print out my vanity message if not done so already
1862 * o print out what type of hardware is detected
1863 * o print out the ethernet address
1864 * o find the IRQ
1865 * o set up my private data
1866 * o configure the dev structure with my subroutines
1867 * o actually GRAB the irq.
1868 * o GRAB the region
1869 */
1870 static int __devinit smc_probe(struct net_device *dev, void __iomem *ioaddr,
1871 unsigned long irq_flags)
1872 {
1873 struct smc_local *lp = netdev_priv(dev);
1874 static int version_printed = 0;
1875 int retval;
1876 unsigned int val, revision_register;
1877 const char *version_string;
1878
1879 DBG(2, "%s: %s\n", CARDNAME, __func__);
1880
1881 /* First, see if the high byte is 0x33 */
1882 val = SMC_CURRENT_BANK(lp);
1883 DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val);
1884 if ((val & 0xFF00) != 0x3300) {
1885 if ((val & 0xFF) == 0x33) {
1886 printk(KERN_WARNING
1887 "%s: Detected possible byte-swapped interface"
1888 " at IOADDR %p\n", CARDNAME, ioaddr);
1889 }
1890 retval = -ENODEV;
1891 goto err_out;
1892 }
1893
1894 /*
1895 * The above MIGHT indicate a device, but I need to write to
1896 * further test this.
1897 */
1898 SMC_SELECT_BANK(lp, 0);
1899 val = SMC_CURRENT_BANK(lp);
1900 if ((val & 0xFF00) != 0x3300) {
1901 retval = -ENODEV;
1902 goto err_out;
1903 }
1904
1905 /*
1906 * well, we've already written once, so hopefully another
1907 * time won't hurt. This time, I need to switch the bank
1908 * register to bank 1, so I can access the base address
1909 * register
1910 */
1911 SMC_SELECT_BANK(lp, 1);
1912 val = SMC_GET_BASE(lp);
1913 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1914 if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1915 printk("%s: IOADDR %p doesn't match configuration (%x).\n",
1916 CARDNAME, ioaddr, val);
1917 }
1918
1919 /*
1920 * check if the revision register is something that I
1921 * recognize. These might need to be added to later,
1922 * as future revisions could be added.
1923 */
1924 SMC_SELECT_BANK(lp, 3);
1925 revision_register = SMC_GET_REV(lp);
1926 DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
1927 version_string = chip_ids[ (revision_register >> 4) & 0xF];
1928 if (!version_string || (revision_register & 0xff00) != 0x3300) {
1929 /* I don't recognize this chip, so... */
1930 printk("%s: IO %p: Unrecognized revision register 0x%04x"
1931 ", Contact author.\n", CARDNAME,
1932 ioaddr, revision_register);
1933
1934 retval = -ENODEV;
1935 goto err_out;
1936 }
1937
1938 /* At this point I'll assume that the chip is an SMC91x. */
1939 if (version_printed++ == 0)
1940 printk("%s", version);
1941
1942 /* fill in some of the fields */
1943 dev->base_addr = (unsigned long)ioaddr;
1944 lp->base = ioaddr;
1945 lp->version = revision_register & 0xff;
1946 spin_lock_init(&lp->lock);
1947
1948 /* Get the MAC address */
1949 SMC_SELECT_BANK(lp, 1);
1950 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1951
1952 /* now, reset the chip, and put it into a known state */
1953 smc_reset(dev);
1954
1955 /*
1956 * If dev->irq is 0, then the device has to be banged on to see
1957 * what the IRQ is.
1958 *
1959 * This banging doesn't always detect the IRQ, for unknown reasons.
1960 * a workaround is to reset the chip and try again.
1961 *
1962 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1963 * be what is requested on the command line. I don't do that, mostly
1964 * because the card that I have uses a non-standard method of accessing
1965 * the IRQs, and because this _should_ work in most configurations.
1966 *
1967 * Specifying an IRQ is done with the assumption that the user knows
1968 * what (s)he is doing. No checking is done!!!!
1969 */
1970 if (dev->irq < 1) {
1971 int trials;
1972
1973 trials = 3;
1974 while (trials--) {
1975 dev->irq = smc_findirq(lp);
1976 if (dev->irq)
1977 break;
1978 /* kick the card and try again */
1979 smc_reset(dev);
1980 }
1981 }
1982 if (dev->irq == 0) {
1983 printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
1984 dev->name);
1985 retval = -ENODEV;
1986 goto err_out;
1987 }
1988 dev->irq = irq_canonicalize(dev->irq);
1989
1990 /* Fill in the fields of the device structure with ethernet values. */
1991 ether_setup(dev);
1992
1993 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1994 dev->netdev_ops = &smc_netdev_ops;
1995 dev->ethtool_ops = &smc_ethtool_ops;
1996
1997 tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev);
1998 INIT_WORK(&lp->phy_configure, smc_phy_configure);
1999 lp->dev = dev;
2000 lp->mii.phy_id_mask = 0x1f;
2001 lp->mii.reg_num_mask = 0x1f;
2002 lp->mii.force_media = 0;
2003 lp->mii.full_duplex = 0;
2004 lp->mii.dev = dev;
2005 lp->mii.mdio_read = smc_phy_read;
2006 lp->mii.mdio_write = smc_phy_write;
2007
2008 /*
2009 * Locate the phy, if any.
2010 */
2011 if (lp->version >= (CHIP_91100 << 4))
2012 smc_phy_detect(dev);
2013
2014 /* then shut everything down to save power */
2015 smc_shutdown(dev);
2016 smc_phy_powerdown(dev);
2017
2018 /* Set default parameters */
2019 lp->msg_enable = NETIF_MSG_LINK;
2020 lp->ctl_rfduplx = 0;
2021 lp->ctl_rspeed = 10;
2022
2023 if (lp->version >= (CHIP_91100 << 4)) {
2024 lp->ctl_rfduplx = 1;
2025 lp->ctl_rspeed = 100;
2026 }
2027
2028 /* Grab the IRQ */
2029 retval = request_irq(dev->irq, &smc_interrupt, irq_flags, dev->name, dev);
2030 if (retval)
2031 goto err_out;
2032
2033 #ifdef CONFIG_ARCH_PXA
2034 # ifdef SMC_USE_PXA_DMA
2035 lp->cfg.flags |= SMC91X_USE_DMA;
2036 # endif
2037 if (lp->cfg.flags & SMC91X_USE_DMA) {
2038 int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW,
2039 smc_pxa_dma_irq, NULL);
2040 if (dma >= 0)
2041 dev->dma = dma;
2042 }
2043 #endif
2044
2045 retval = register_netdev(dev);
2046 if (retval == 0) {
2047 /* now, print out the card info, in a short format.. */
2048 printk("%s: %s (rev %d) at %p IRQ %d",
2049 dev->name, version_string, revision_register & 0x0f,
2050 lp->base, dev->irq);
2051
2052 if (dev->dma != (unsigned char)-1)
2053 printk(" DMA %d", dev->dma);
2054
2055 printk("%s%s\n",
2056 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
2057 THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
2058
2059 if (!is_valid_ether_addr(dev->dev_addr)) {
2060 printk("%s: Invalid ethernet MAC address. Please "
2061 "set using ifconfig\n", dev->name);
2062 } else {
2063 /* Print the Ethernet address */
2064 printk("%s: Ethernet addr: %pM\n",
2065 dev->name, dev->dev_addr);
2066 }
2067
2068 if (lp->phy_type == 0) {
2069 PRINTK("%s: No PHY found\n", dev->name);
2070 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) {
2071 PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name);
2072 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) {
2073 PRINTK("%s: PHY LAN83C180\n", dev->name);
2074 }
2075 }
2076
2077 err_out:
2078 #ifdef CONFIG_ARCH_PXA
2079 if (retval && dev->dma != (unsigned char)-1)
2080 pxa_free_dma(dev->dma);
2081 #endif
2082 return retval;
2083 }
2084
2085 static int smc_enable_device(struct platform_device *pdev)
2086 {
2087 struct net_device *ndev = platform_get_drvdata(pdev);
2088 struct smc_local *lp = netdev_priv(ndev);
2089 unsigned long flags;
2090 unsigned char ecor, ecsr;
2091 void __iomem *addr;
2092 struct resource * res;
2093
2094 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2095 if (!res)
2096 return 0;
2097
2098 /*
2099 * Map the attribute space. This is overkill, but clean.
2100 */
2101 addr = ioremap(res->start, ATTRIB_SIZE);
2102 if (!addr)
2103 return -ENOMEM;
2104
2105 /*
2106 * Reset the device. We must disable IRQs around this
2107 * since a reset causes the IRQ line become active.
2108 */
2109 local_irq_save(flags);
2110 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
2111 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
2112 readb(addr + (ECOR << SMC_IO_SHIFT));
2113
2114 /*
2115 * Wait 100us for the chip to reset.
2116 */
2117 udelay(100);
2118
2119 /*
2120 * The device will ignore all writes to the enable bit while
2121 * reset is asserted, even if the reset bit is cleared in the
2122 * same write. Must clear reset first, then enable the device.
2123 */
2124 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
2125 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
2126
2127 /*
2128 * Set the appropriate byte/word mode.
2129 */
2130 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
2131 if (!SMC_16BIT(lp))
2132 ecsr |= ECSR_IOIS8;
2133 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
2134 local_irq_restore(flags);
2135
2136 iounmap(addr);
2137
2138 /*
2139 * Wait for the chip to wake up. We could poll the control
2140 * register in the main register space, but that isn't mapped
2141 * yet. We know this is going to take 750us.
2142 */
2143 msleep(1);
2144
2145 return 0;
2146 }
2147
2148 static int smc_request_attrib(struct platform_device *pdev,
2149 struct net_device *ndev)
2150 {
2151 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2152 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2153
2154 if (!res)
2155 return 0;
2156
2157 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME))
2158 return -EBUSY;
2159
2160 return 0;
2161 }
2162
2163 static void smc_release_attrib(struct platform_device *pdev,
2164 struct net_device *ndev)
2165 {
2166 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2167 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2168
2169 if (res)
2170 release_mem_region(res->start, ATTRIB_SIZE);
2171 }
2172
2173 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev)
2174 {
2175 if (SMC_CAN_USE_DATACS) {
2176 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2177 struct smc_local *lp = netdev_priv(ndev);
2178
2179 if (!res)
2180 return;
2181
2182 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) {
2183 printk(KERN_INFO "%s: failed to request datacs memory region.\n", CARDNAME);
2184 return;
2185 }
2186
2187 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT);
2188 }
2189 }
2190
2191 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev)
2192 {
2193 if (SMC_CAN_USE_DATACS) {
2194 struct smc_local *lp = netdev_priv(ndev);
2195 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2196
2197 if (lp->datacs)
2198 iounmap(lp->datacs);
2199
2200 lp->datacs = NULL;
2201
2202 if (res)
2203 release_mem_region(res->start, SMC_DATA_EXTENT);
2204 }
2205 }
2206
2207 /*
2208 * smc_init(void)
2209 * Input parameters:
2210 * dev->base_addr == 0, try to find all possible locations
2211 * dev->base_addr > 0x1ff, this is the address to check
2212 * dev->base_addr == <anything else>, return failure code
2213 *
2214 * Output:
2215 * 0 --> there is a device
2216 * anything else, error
2217 */
2218 static int __devinit smc_drv_probe(struct platform_device *pdev)
2219 {
2220 struct smc91x_platdata *pd = pdev->dev.platform_data;
2221 struct smc_local *lp;
2222 struct net_device *ndev;
2223 struct resource *res, *ires;
2224 unsigned int __iomem *addr;
2225 unsigned long irq_flags = SMC_IRQ_FLAGS;
2226 int ret;
2227
2228 ndev = alloc_etherdev(sizeof(struct smc_local));
2229 if (!ndev) {
2230 printk("%s: could not allocate device.\n", CARDNAME);
2231 ret = -ENOMEM;
2232 goto out;
2233 }
2234 SET_NETDEV_DEV(ndev, &pdev->dev);
2235
2236 /* get configuration from platform data, only allow use of
2237 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
2238 */
2239
2240 lp = netdev_priv(ndev);
2241
2242 if (pd) {
2243 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2244 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
2245 } else {
2246 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0;
2247 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
2248 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
2249 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
2250 }
2251
2252 if (!lp->cfg.leda && !lp->cfg.ledb) {
2253 lp->cfg.leda = RPC_LSA_DEFAULT;
2254 lp->cfg.ledb = RPC_LSB_DEFAULT;
2255 }
2256
2257 ndev->dma = (unsigned char)-1;
2258
2259 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2260 if (!res)
2261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2262 if (!res) {
2263 ret = -ENODEV;
2264 goto out_free_netdev;
2265 }
2266
2267
2268 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
2269 ret = -EBUSY;
2270 goto out_free_netdev;
2271 }
2272
2273 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2274 if (!ires) {
2275 ret = -ENODEV;
2276 goto out_release_io;
2277 }
2278
2279 ndev->irq = ires->start;
2280
2281 if (ires->flags & IRQF_TRIGGER_MASK)
2282 irq_flags = ires->flags & IRQF_TRIGGER_MASK;
2283
2284 ret = smc_request_attrib(pdev, ndev);
2285 if (ret)
2286 goto out_release_io;
2287 #if defined(CONFIG_SA1100_ASSABET)
2288 NCR_0 |= NCR_ENET_OSC_EN;
2289 #endif
2290 platform_set_drvdata(pdev, ndev);
2291 ret = smc_enable_device(pdev);
2292 if (ret)
2293 goto out_release_attrib;
2294
2295 addr = ioremap(res->start, SMC_IO_EXTENT);
2296 if (!addr) {
2297 ret = -ENOMEM;
2298 goto out_release_attrib;
2299 }
2300
2301 #ifdef CONFIG_ARCH_PXA
2302 {
2303 struct smc_local *lp = netdev_priv(ndev);
2304 lp->device = &pdev->dev;
2305 lp->physaddr = res->start;
2306 }
2307 #endif
2308
2309 ret = smc_probe(ndev, addr, irq_flags);
2310 if (ret != 0)
2311 goto out_iounmap;
2312
2313 smc_request_datacs(pdev, ndev);
2314
2315 return 0;
2316
2317 out_iounmap:
2318 platform_set_drvdata(pdev, NULL);
2319 iounmap(addr);
2320 out_release_attrib:
2321 smc_release_attrib(pdev, ndev);
2322 out_release_io:
2323 release_mem_region(res->start, SMC_IO_EXTENT);
2324 out_free_netdev:
2325 free_netdev(ndev);
2326 out:
2327 printk("%s: not found (%d).\n", CARDNAME, ret);
2328
2329 return ret;
2330 }
2331
2332 static int __devexit smc_drv_remove(struct platform_device *pdev)
2333 {
2334 struct net_device *ndev = platform_get_drvdata(pdev);
2335 struct smc_local *lp = netdev_priv(ndev);
2336 struct resource *res;
2337
2338 platform_set_drvdata(pdev, NULL);
2339
2340 unregister_netdev(ndev);
2341
2342 free_irq(ndev->irq, ndev);
2343
2344 #ifdef CONFIG_ARCH_PXA
2345 if (ndev->dma != (unsigned char)-1)
2346 pxa_free_dma(ndev->dma);
2347 #endif
2348 iounmap(lp->base);
2349
2350 smc_release_datacs(pdev,ndev);
2351 smc_release_attrib(pdev,ndev);
2352
2353 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2354 if (!res)
2355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2356 release_mem_region(res->start, SMC_IO_EXTENT);
2357
2358 free_netdev(ndev);
2359
2360 return 0;
2361 }
2362
2363 static int smc_drv_suspend(struct platform_device *dev, pm_message_t state)
2364 {
2365 struct net_device *ndev = platform_get_drvdata(dev);
2366
2367 if (ndev) {
2368 if (netif_running(ndev)) {
2369 netif_device_detach(ndev);
2370 smc_shutdown(ndev);
2371 smc_phy_powerdown(ndev);
2372 }
2373 }
2374 return 0;
2375 }
2376
2377 static int smc_drv_resume(struct platform_device *dev)
2378 {
2379 struct net_device *ndev = platform_get_drvdata(dev);
2380
2381 if (ndev) {
2382 struct smc_local *lp = netdev_priv(ndev);
2383 smc_enable_device(dev);
2384 if (netif_running(ndev)) {
2385 smc_reset(ndev);
2386 smc_enable(ndev);
2387 if (lp->phy_type != 0)
2388 smc_phy_configure(&lp->phy_configure);
2389 netif_device_attach(ndev);
2390 }
2391 }
2392 return 0;
2393 }
2394
2395 static struct platform_driver smc_driver = {
2396 .probe = smc_drv_probe,
2397 .remove = __devexit_p(smc_drv_remove),
2398 .suspend = smc_drv_suspend,
2399 .resume = smc_drv_resume,
2400 .driver = {
2401 .name = CARDNAME,
2402 .owner = THIS_MODULE,
2403 },
2404 };
2405
2406 static int __init smc_init(void)
2407 {
2408 return platform_driver_register(&smc_driver);
2409 }
2410
2411 static void __exit smc_cleanup(void)
2412 {
2413 platform_driver_unregister(&smc_driver);
2414 }
2415
2416 module_init(smc_init);
2417 module_exit(smc_cleanup);
Linux kernel - Deliverables
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