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[PATCH] b44: fix eeprom endianess issue
[deliverable/linux.git] / drivers / net / smc91x.h
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60 /* We can only do 16-bit reads and writes in the static memory space. */
61 #define SMC_CAN_USE_8BIT 0
62 #define SMC_CAN_USE_16BIT 1
63 #define SMC_CAN_USE_32BIT 0
64 #define SMC_NOWAIT 1
65
66 #define SMC_IO_SHIFT 0
67
68 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70 #define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82 #define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
93 #define SMC_IRQ_FLAGS (0)
94
95 #elif defined(CONFIG_SA1100_PLEB)
96 /* We can only do 16-bit reads and writes in the static memory space. */
97 #define SMC_CAN_USE_8BIT 1
98 #define SMC_CAN_USE_16BIT 1
99 #define SMC_CAN_USE_32BIT 0
100 #define SMC_IO_SHIFT 0
101 #define SMC_NOWAIT 1
102
103 #define SMC_inb(a, r) readb((a) + (r))
104 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105 #define SMC_inw(a, r) readw((a) + (r))
106 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
108 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109 #define SMC_outw(v, a, r) writew(v, (a) + (r))
110 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
111
112 #define SMC_IRQ_FLAGS (0)
113
114 #elif defined(CONFIG_SA1100_ASSABET)
115
116 #include <asm/arch/neponset.h>
117
118 /* We can only do 8-bit reads and writes in the static memory space. */
119 #define SMC_CAN_USE_8BIT 1
120 #define SMC_CAN_USE_16BIT 0
121 #define SMC_CAN_USE_32BIT 0
122 #define SMC_NOWAIT 1
123
124 /* The first two address lines aren't connected... */
125 #define SMC_IO_SHIFT 2
126
127 #define SMC_inb(a, r) readb((a) + (r))
128 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
129 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
132 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
133
134 #define SMC_CAN_USE_8BIT 0
135 #define SMC_CAN_USE_16BIT 1
136 #define SMC_CAN_USE_32BIT 0
137 #define SMC_IO_SHIFT 0
138 #define SMC_NOWAIT 1
139
140 #define SMC_inw(a, r) readw((a) + (r))
141 #define SMC_outw(v, a, r) writew(v, (a) + (r))
142 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
143 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
144
145 #elif defined(CONFIG_ARCH_INNOKOM) || \
146 defined(CONFIG_MACH_MAINSTONE) || \
147 defined(CONFIG_ARCH_PXA_IDP) || \
148 defined(CONFIG_ARCH_RAMSES)
149
150 #define SMC_CAN_USE_8BIT 1
151 #define SMC_CAN_USE_16BIT 1
152 #define SMC_CAN_USE_32BIT 1
153 #define SMC_IO_SHIFT 0
154 #define SMC_NOWAIT 1
155 #define SMC_USE_PXA_DMA 1
156
157 #define SMC_inb(a, r) readb((a) + (r))
158 #define SMC_inw(a, r) readw((a) + (r))
159 #define SMC_inl(a, r) readl((a) + (r))
160 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
161 #define SMC_outl(v, a, r) writel(v, (a) + (r))
162 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
163 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
164
165 /* We actually can't write halfwords properly if not word aligned */
166 static inline void
167 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
168 {
169 if (reg & 2) {
170 unsigned int v = val << 16;
171 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
172 writel(v, ioaddr + (reg & ~2));
173 } else {
174 writew(val, ioaddr + reg);
175 }
176 }
177
178 #elif defined(CONFIG_ARCH_OMAP)
179
180 /* We can only do 16-bit reads and writes in the static memory space. */
181 #define SMC_CAN_USE_8BIT 0
182 #define SMC_CAN_USE_16BIT 1
183 #define SMC_CAN_USE_32BIT 0
184 #define SMC_IO_SHIFT 0
185 #define SMC_NOWAIT 1
186
187 #define SMC_inw(a, r) readw((a) + (r))
188 #define SMC_outw(v, a, r) writew(v, (a) + (r))
189 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
190 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
191
192 #include <asm/mach-types.h>
193 #include <asm/arch/cpu.h>
194
195 #define SMC_IRQ_FLAGS (( \
196 machine_is_omap_h2() \
197 || machine_is_omap_h3() \
198 || machine_is_omap_h4() \
199 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
200 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
201
202
203 #elif defined(CONFIG_SH_SH4202_MICRODEV)
204
205 #define SMC_CAN_USE_8BIT 0
206 #define SMC_CAN_USE_16BIT 1
207 #define SMC_CAN_USE_32BIT 0
208
209 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
210 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
211 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
212 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
213 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
214 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
215 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
216 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
217 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
218 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
219
220 #define SMC_IRQ_FLAGS (0)
221
222 #elif defined(CONFIG_ISA)
223
224 #define SMC_CAN_USE_8BIT 1
225 #define SMC_CAN_USE_16BIT 1
226 #define SMC_CAN_USE_32BIT 0
227
228 #define SMC_inb(a, r) inb((a) + (r))
229 #define SMC_inw(a, r) inw((a) + (r))
230 #define SMC_outb(v, a, r) outb(v, (a) + (r))
231 #define SMC_outw(v, a, r) outw(v, (a) + (r))
232 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
233 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
234
235 #elif defined(CONFIG_M32R)
236
237 #define SMC_CAN_USE_8BIT 0
238 #define SMC_CAN_USE_16BIT 1
239 #define SMC_CAN_USE_32BIT 0
240
241 #define SMC_inb(a, r) inb((u32)a) + (r))
242 #define SMC_inw(a, r) inw(((u32)a) + (r))
243 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
244 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
245 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
246 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
247
248 #define SMC_IRQ_FLAGS (0)
249
250 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
251 #define RPC_LSB_DEFAULT RPC_LED_100_10
252
253 #elif defined(CONFIG_MACH_LPD79520) \
254 || defined(CONFIG_MACH_LPD7A400) \
255 || defined(CONFIG_MACH_LPD7A404)
256
257 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
258 * way that the CPU handles chip selects and the way that the SMC chip
259 * expects the chip select to operate. Refer to
260 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
261 * IOBARRIER is a byte, in order that we read the least-common
262 * denominator. It would be wasteful to read 32 bits from an 8-bit
263 * accessible region.
264 *
265 * There is no explicit protection against interrupts intervening
266 * between the writew and the IOBARRIER. In SMC ISR there is a
267 * preamble that performs an IOBARRIER in the extremely unlikely event
268 * that the driver interrupts itself between a writew to the chip an
269 * the IOBARRIER that follows *and* the cache is large enough that the
270 * first off-chip access while handing the interrupt is to the SMC
271 * chip. Other devices in the same address space as the SMC chip must
272 * be aware of the potential for trouble and perform a similar
273 * IOBARRIER on entry to their ISR.
274 */
275
276 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
277
278 #define SMC_CAN_USE_8BIT 0
279 #define SMC_CAN_USE_16BIT 1
280 #define SMC_CAN_USE_32BIT 0
281 #define SMC_NOWAIT 0
282 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
283
284 #define SMC_inw(a,r)\
285 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
286 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
287
288 #define SMC_insw LPD7_SMC_insw
289 static inline void LPD7_SMC_insw (unsigned char* a, int r,
290 unsigned char* p, int l)
291 {
292 unsigned short* ps = (unsigned short*) p;
293 while (l-- > 0) {
294 *ps++ = readw (a + r);
295 LPD7X_IOBARRIER;
296 }
297 }
298
299 #define SMC_outsw LPD7_SMC_outsw
300 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
301 unsigned char* p, int l)
302 {
303 unsigned short* ps = (unsigned short*) p;
304 while (l-- > 0) {
305 writew (*ps++, a + r);
306 LPD7X_IOBARRIER;
307 }
308 }
309
310 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
311
312 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
313 #define RPC_LSB_DEFAULT RPC_LED_100_10
314
315 #elif defined(CONFIG_SOC_AU1X00)
316
317 #include <au1xxx.h>
318
319 /* We can only do 16-bit reads and writes in the static memory space. */
320 #define SMC_CAN_USE_8BIT 0
321 #define SMC_CAN_USE_16BIT 1
322 #define SMC_CAN_USE_32BIT 0
323 #define SMC_IO_SHIFT 0
324 #define SMC_NOWAIT 1
325
326 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
327 #define SMC_insw(a, r, p, l) \
328 do { \
329 unsigned long _a = (unsigned long)((a) + (r)); \
330 int _l = (l); \
331 u16 *_p = (u16 *)(p); \
332 while (_l-- > 0) \
333 *_p++ = au_readw(_a); \
334 } while(0)
335 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
336 #define SMC_outsw(a, r, p, l) \
337 do { \
338 unsigned long _a = (unsigned long)((a) + (r)); \
339 int _l = (l); \
340 const u16 *_p = (const u16 *)(p); \
341 while (_l-- > 0) \
342 au_writew(*_p++ , _a); \
343 } while(0)
344
345 #define SMC_IRQ_FLAGS (0)
346
347 #elif defined(CONFIG_ARCH_VERSATILE)
348
349 #define SMC_CAN_USE_8BIT 1
350 #define SMC_CAN_USE_16BIT 1
351 #define SMC_CAN_USE_32BIT 1
352 #define SMC_NOWAIT 1
353
354 #define SMC_inb(a, r) readb((a) + (r))
355 #define SMC_inw(a, r) readw((a) + (r))
356 #define SMC_inl(a, r) readl((a) + (r))
357 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
358 #define SMC_outw(v, a, r) writew(v, (a) + (r))
359 #define SMC_outl(v, a, r) writel(v, (a) + (r))
360 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
361 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
362
363 #define SMC_IRQ_FLAGS (0)
364
365 #elif defined(CONFIG_ARCH_VERSATILE)
366
367 #define SMC_CAN_USE_8BIT 1
368 #define SMC_CAN_USE_16BIT 1
369 #define SMC_CAN_USE_32BIT 1
370 #define SMC_NOWAIT 1
371
372 #define SMC_inb(a, r) readb((a) + (r))
373 #define SMC_inw(a, r) readw((a) + (r))
374 #define SMC_inl(a, r) readl((a) + (r))
375 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
376 #define SMC_outw(v, a, r) writew(v, (a) + (r))
377 #define SMC_outl(v, a, r) writel(v, (a) + (r))
378 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
379 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
380
381 #define SMC_IRQ_FLAGS (0)
382
383 #elif defined(CONFIG_ARCH_VERSATILE)
384
385 #define SMC_CAN_USE_8BIT 1
386 #define SMC_CAN_USE_16BIT 1
387 #define SMC_CAN_USE_32BIT 1
388 #define SMC_NOWAIT 1
389
390 #define SMC_inb(a, r) readb((a) + (r))
391 #define SMC_inw(a, r) readw((a) + (r))
392 #define SMC_inl(a, r) readl((a) + (r))
393 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
394 #define SMC_outw(v, a, r) writew(v, (a) + (r))
395 #define SMC_outl(v, a, r) writel(v, (a) + (r))
396 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
397 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
398
399 #define SMC_IRQ_FLAGS (0)
400
401 #elif defined(CONFIG_ARCH_VERSATILE)
402
403 #define SMC_CAN_USE_8BIT 1
404 #define SMC_CAN_USE_16BIT 1
405 #define SMC_CAN_USE_32BIT 1
406 #define SMC_NOWAIT 1
407
408 #define SMC_inb(a, r) readb((a) + (r))
409 #define SMC_inw(a, r) readw((a) + (r))
410 #define SMC_inl(a, r) readl((a) + (r))
411 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
412 #define SMC_outw(v, a, r) writew(v, (a) + (r))
413 #define SMC_outl(v, a, r) writel(v, (a) + (r))
414 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
415 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
416
417 #define SMC_IRQ_FLAGS (0)
418
419 #else
420
421 #define SMC_CAN_USE_8BIT 1
422 #define SMC_CAN_USE_16BIT 1
423 #define SMC_CAN_USE_32BIT 1
424 #define SMC_NOWAIT 1
425
426 #define SMC_inb(a, r) readb((a) + (r))
427 #define SMC_inw(a, r) readw((a) + (r))
428 #define SMC_inl(a, r) readl((a) + (r))
429 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
430 #define SMC_outw(v, a, r) writew(v, (a) + (r))
431 #define SMC_outl(v, a, r) writel(v, (a) + (r))
432 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
433 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
434
435 #define RPC_LSA_DEFAULT RPC_LED_100_10
436 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
437
438 #endif
439
440 #ifdef SMC_USE_PXA_DMA
441 /*
442 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
443 * always happening in irq context so no need to worry about races. TX is
444 * different and probably not worth it for that reason, and not as critical
445 * as RX which can overrun memory and lose packets.
446 */
447 #include <linux/dma-mapping.h>
448 #include <asm/dma.h>
449 #include <asm/arch/pxa-regs.h>
450
451 #ifdef SMC_insl
452 #undef SMC_insl
453 #define SMC_insl(a, r, p, l) \
454 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
455 static inline void
456 smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
457 u_char *buf, int len)
458 {
459 dma_addr_t dmabuf;
460
461 /* fallback if no DMA available */
462 if (dma == (unsigned char)-1) {
463 readsl(ioaddr + reg, buf, len);
464 return;
465 }
466
467 /* 64 bit alignment is required for memory to memory DMA */
468 if ((long)buf & 4) {
469 *((u32 *)buf) = SMC_inl(ioaddr, reg);
470 buf += 4;
471 len--;
472 }
473
474 len *= 4;
475 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
476 DCSR(dma) = DCSR_NODESC;
477 DTADR(dma) = dmabuf;
478 DSADR(dma) = physaddr + reg;
479 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
480 DCMD_WIDTH4 | (DCMD_LENGTH & len));
481 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
482 while (!(DCSR(dma) & DCSR_STOPSTATE))
483 cpu_relax();
484 DCSR(dma) = 0;
485 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
486 }
487 #endif
488
489 #ifdef SMC_insw
490 #undef SMC_insw
491 #define SMC_insw(a, r, p, l) \
492 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
493 static inline void
494 smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
495 u_char *buf, int len)
496 {
497 dma_addr_t dmabuf;
498
499 /* fallback if no DMA available */
500 if (dma == (unsigned char)-1) {
501 readsw(ioaddr + reg, buf, len);
502 return;
503 }
504
505 /* 64 bit alignment is required for memory to memory DMA */
506 while ((long)buf & 6) {
507 *((u16 *)buf) = SMC_inw(ioaddr, reg);
508 buf += 2;
509 len--;
510 }
511
512 len *= 2;
513 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
514 DCSR(dma) = DCSR_NODESC;
515 DTADR(dma) = dmabuf;
516 DSADR(dma) = physaddr + reg;
517 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
518 DCMD_WIDTH2 | (DCMD_LENGTH & len));
519 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
520 while (!(DCSR(dma) & DCSR_STOPSTATE))
521 cpu_relax();
522 DCSR(dma) = 0;
523 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
524 }
525 #endif
526
527 static void
528 smc_pxa_dma_irq(int dma, void *dummy)
529 {
530 DCSR(dma) = 0;
531 }
532 #endif /* SMC_USE_PXA_DMA */
533
534
535 /*
536 * Everything a particular hardware setup needs should have been defined
537 * at this point. Add stubs for the undefined cases, mainly to avoid
538 * compilation warnings since they'll be optimized away, or to prevent buggy
539 * use of them.
540 */
541
542 #if ! SMC_CAN_USE_32BIT
543 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
544 #define SMC_outl(x, ioaddr, reg) BUG()
545 #define SMC_insl(a, r, p, l) BUG()
546 #define SMC_outsl(a, r, p, l) BUG()
547 #endif
548
549 #if !defined(SMC_insl) || !defined(SMC_outsl)
550 #define SMC_insl(a, r, p, l) BUG()
551 #define SMC_outsl(a, r, p, l) BUG()
552 #endif
553
554 #if ! SMC_CAN_USE_16BIT
555
556 /*
557 * Any 16-bit access is performed with two 8-bit accesses if the hardware
558 * can't do it directly. Most registers are 16-bit so those are mandatory.
559 */
560 #define SMC_outw(x, ioaddr, reg) \
561 do { \
562 unsigned int __val16 = (x); \
563 SMC_outb( __val16, ioaddr, reg ); \
564 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
565 } while (0)
566 #define SMC_inw(ioaddr, reg) \
567 ({ \
568 unsigned int __val16; \
569 __val16 = SMC_inb( ioaddr, reg ); \
570 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
571 __val16; \
572 })
573
574 #define SMC_insw(a, r, p, l) BUG()
575 #define SMC_outsw(a, r, p, l) BUG()
576
577 #endif
578
579 #if !defined(SMC_insw) || !defined(SMC_outsw)
580 #define SMC_insw(a, r, p, l) BUG()
581 #define SMC_outsw(a, r, p, l) BUG()
582 #endif
583
584 #if ! SMC_CAN_USE_8BIT
585 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
586 #define SMC_outb(x, ioaddr, reg) BUG()
587 #define SMC_insb(a, r, p, l) BUG()
588 #define SMC_outsb(a, r, p, l) BUG()
589 #endif
590
591 #if !defined(SMC_insb) || !defined(SMC_outsb)
592 #define SMC_insb(a, r, p, l) BUG()
593 #define SMC_outsb(a, r, p, l) BUG()
594 #endif
595
596 #ifndef SMC_CAN_USE_DATACS
597 #define SMC_CAN_USE_DATACS 0
598 #endif
599
600 #ifndef SMC_IO_SHIFT
601 #define SMC_IO_SHIFT 0
602 #endif
603
604 #ifndef SMC_IRQ_FLAGS
605 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
606 #endif
607
608 #ifndef SMC_INTERRUPT_PREAMBLE
609 #define SMC_INTERRUPT_PREAMBLE
610 #endif
611
612
613 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
614 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
615 #define SMC_DATA_EXTENT (4)
616
617 /*
618 . Bank Select Register:
619 .
620 . yyyy yyyy 0000 00xx
621 . xx = bank number
622 . yyyy yyyy = 0x33, for identification purposes.
623 */
624 #define BANK_SELECT (14 << SMC_IO_SHIFT)
625
626
627 // Transmit Control Register
628 /* BANK 0 */
629 #define TCR_REG SMC_REG(0x0000, 0)
630 #define TCR_ENABLE 0x0001 // When 1 we can transmit
631 #define TCR_LOOP 0x0002 // Controls output pin LBK
632 #define TCR_FORCOL 0x0004 // When 1 will force a collision
633 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
634 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
635 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
636 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
637 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
638 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
639 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
640
641 #define TCR_CLEAR 0 /* do NOTHING */
642 /* the default settings for the TCR register : */
643 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
644
645
646 // EPH Status Register
647 /* BANK 0 */
648 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
649 #define ES_TX_SUC 0x0001 // Last TX was successful
650 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
651 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
652 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
653 #define ES_16COL 0x0010 // 16 Collisions Reached
654 #define ES_SQET 0x0020 // Signal Quality Error Test
655 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
656 #define ES_TXDEFR 0x0080 // Transmit Deferred
657 #define ES_LATCOL 0x0200 // Late collision detected on last tx
658 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
659 #define ES_EXC_DEF 0x0800 // Excessive Deferral
660 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
661 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
662 #define ES_TXUNRN 0x8000 // Tx Underrun
663
664
665 // Receive Control Register
666 /* BANK 0 */
667 #define RCR_REG SMC_REG(0x0004, 0)
668 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
669 #define RCR_PRMS 0x0002 // Enable promiscuous mode
670 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
671 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
672 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
673 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
674 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
675 #define RCR_SOFTRST 0x8000 // resets the chip
676
677 /* the normal settings for the RCR register : */
678 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
679 #define RCR_CLEAR 0x0 // set it to a base state
680
681
682 // Counter Register
683 /* BANK 0 */
684 #define COUNTER_REG SMC_REG(0x0006, 0)
685
686
687 // Memory Information Register
688 /* BANK 0 */
689 #define MIR_REG SMC_REG(0x0008, 0)
690
691
692 // Receive/Phy Control Register
693 /* BANK 0 */
694 #define RPC_REG SMC_REG(0x000A, 0)
695 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
696 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
697 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
698 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
699 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
700 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
701 #define RPC_LED_RES (0x01) // LED = Reserved
702 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
703 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
704 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
705 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
706 #define RPC_LED_TX (0x06) // LED = TX packet occurred
707 #define RPC_LED_RX (0x07) // LED = RX packet occurred
708
709 #ifndef RPC_LSA_DEFAULT
710 #define RPC_LSA_DEFAULT RPC_LED_100
711 #endif
712 #ifndef RPC_LSB_DEFAULT
713 #define RPC_LSB_DEFAULT RPC_LED_FD
714 #endif
715
716 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
717
718
719 /* Bank 0 0x0C is reserved */
720
721 // Bank Select Register
722 /* All Banks */
723 #define BSR_REG 0x000E
724
725
726 // Configuration Reg
727 /* BANK 1 */
728 #define CONFIG_REG SMC_REG(0x0000, 1)
729 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
730 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
731 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
732 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
733
734 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
735 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
736
737
738 // Base Address Register
739 /* BANK 1 */
740 #define BASE_REG SMC_REG(0x0002, 1)
741
742
743 // Individual Address Registers
744 /* BANK 1 */
745 #define ADDR0_REG SMC_REG(0x0004, 1)
746 #define ADDR1_REG SMC_REG(0x0006, 1)
747 #define ADDR2_REG SMC_REG(0x0008, 1)
748
749
750 // General Purpose Register
751 /* BANK 1 */
752 #define GP_REG SMC_REG(0x000A, 1)
753
754
755 // Control Register
756 /* BANK 1 */
757 #define CTL_REG SMC_REG(0x000C, 1)
758 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
759 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
760 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
761 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
762 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
763 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
764 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
765 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
766
767
768 // MMU Command Register
769 /* BANK 2 */
770 #define MMU_CMD_REG SMC_REG(0x0000, 2)
771 #define MC_BUSY 1 // When 1 the last release has not completed
772 #define MC_NOP (0<<5) // No Op
773 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
774 #define MC_RESET (2<<5) // Reset MMU to initial state
775 #define MC_REMOVE (3<<5) // Remove the current rx packet
776 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
777 #define MC_FREEPKT (5<<5) // Release packet in PNR register
778 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
779 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
780
781
782 // Packet Number Register
783 /* BANK 2 */
784 #define PN_REG SMC_REG(0x0002, 2)
785
786
787 // Allocation Result Register
788 /* BANK 2 */
789 #define AR_REG SMC_REG(0x0003, 2)
790 #define AR_FAILED 0x80 // Alocation Failed
791
792
793 // TX FIFO Ports Register
794 /* BANK 2 */
795 #define TXFIFO_REG SMC_REG(0x0004, 2)
796 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
797
798 // RX FIFO Ports Register
799 /* BANK 2 */
800 #define RXFIFO_REG SMC_REG(0x0005, 2)
801 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
802
803 #define FIFO_REG SMC_REG(0x0004, 2)
804
805 // Pointer Register
806 /* BANK 2 */
807 #define PTR_REG SMC_REG(0x0006, 2)
808 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
809 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
810 #define PTR_READ 0x2000 // When 1 the operation is a read
811
812
813 // Data Register
814 /* BANK 2 */
815 #define DATA_REG SMC_REG(0x0008, 2)
816
817
818 // Interrupt Status/Acknowledge Register
819 /* BANK 2 */
820 #define INT_REG SMC_REG(0x000C, 2)
821
822
823 // Interrupt Mask Register
824 /* BANK 2 */
825 #define IM_REG SMC_REG(0x000D, 2)
826 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
827 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
828 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
829 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
830 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
831 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
832 #define IM_TX_INT 0x02 // Transmit Interrupt
833 #define IM_RCV_INT 0x01 // Receive Interrupt
834
835
836 // Multicast Table Registers
837 /* BANK 3 */
838 #define MCAST_REG1 SMC_REG(0x0000, 3)
839 #define MCAST_REG2 SMC_REG(0x0002, 3)
840 #define MCAST_REG3 SMC_REG(0x0004, 3)
841 #define MCAST_REG4 SMC_REG(0x0006, 3)
842
843
844 // Management Interface Register (MII)
845 /* BANK 3 */
846 #define MII_REG SMC_REG(0x0008, 3)
847 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
848 #define MII_MDOE 0x0008 // MII Output Enable
849 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
850 #define MII_MDI 0x0002 // MII Input, pin MDI
851 #define MII_MDO 0x0001 // MII Output, pin MDO
852
853
854 // Revision Register
855 /* BANK 3 */
856 /* ( hi: chip id low: rev # ) */
857 #define REV_REG SMC_REG(0x000A, 3)
858
859
860 // Early RCV Register
861 /* BANK 3 */
862 /* this is NOT on SMC9192 */
863 #define ERCV_REG SMC_REG(0x000C, 3)
864 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
865 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
866
867
868 // External Register
869 /* BANK 7 */
870 #define EXT_REG SMC_REG(0x0000, 7)
871
872
873 #define CHIP_9192 3
874 #define CHIP_9194 4
875 #define CHIP_9195 5
876 #define CHIP_9196 6
877 #define CHIP_91100 7
878 #define CHIP_91100FD 8
879 #define CHIP_91111FD 9
880
881 static const char * chip_ids[ 16 ] = {
882 NULL, NULL, NULL,
883 /* 3 */ "SMC91C90/91C92",
884 /* 4 */ "SMC91C94",
885 /* 5 */ "SMC91C95",
886 /* 6 */ "SMC91C96",
887 /* 7 */ "SMC91C100",
888 /* 8 */ "SMC91C100FD",
889 /* 9 */ "SMC91C11xFD",
890 NULL, NULL, NULL,
891 NULL, NULL, NULL};
892
893
894 /*
895 . Receive status bits
896 */
897 #define RS_ALGNERR 0x8000
898 #define RS_BRODCAST 0x4000
899 #define RS_BADCRC 0x2000
900 #define RS_ODDFRAME 0x1000
901 #define RS_TOOLONG 0x0800
902 #define RS_TOOSHORT 0x0400
903 #define RS_MULTICAST 0x0001
904 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
905
906
907 /*
908 * PHY IDs
909 * LAN83C183 == LAN91C111 Internal PHY
910 */
911 #define PHY_LAN83C183 0x0016f840
912 #define PHY_LAN83C180 0x02821c50
913
914 /*
915 * PHY Register Addresses (LAN91C111 Internal PHY)
916 *
917 * Generic PHY registers can be found in <linux/mii.h>
918 *
919 * These phy registers are specific to our on-board phy.
920 */
921
922 // PHY Configuration Register 1
923 #define PHY_CFG1_REG 0x10
924 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
925 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
926 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
927 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
928 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
929 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
930 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
931 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
932 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
933 #define PHY_CFG1_TLVL_MASK 0x003C
934 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
935
936
937 // PHY Configuration Register 2
938 #define PHY_CFG2_REG 0x11
939 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
940 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
941 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
942 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
943
944 // PHY Status Output (and Interrupt status) Register
945 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
946 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
947 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
948 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
949 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
950 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
951 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
952 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
953 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
954 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
955 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
956
957 // PHY Interrupt/Status Mask Register
958 #define PHY_MASK_REG 0x13 // Interrupt Mask
959 // Uses the same bit definitions as PHY_INT_REG
960
961
962 /*
963 * SMC91C96 ethernet config and status registers.
964 * These are in the "attribute" space.
965 */
966 #define ECOR 0x8000
967 #define ECOR_RESET 0x80
968 #define ECOR_LEVEL_IRQ 0x40
969 #define ECOR_WR_ATTRIB 0x04
970 #define ECOR_ENABLE 0x01
971
972 #define ECSR 0x8002
973 #define ECSR_IOIS8 0x20
974 #define ECSR_PWRDWN 0x04
975 #define ECSR_INT 0x02
976
977 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
978
979
980 /*
981 * Macros to abstract register access according to the data bus
982 * capabilities. Please use those and not the in/out primitives.
983 * Note: the following macros do *not* select the bank -- this must
984 * be done separately as needed in the main code. The SMC_REG() macro
985 * only uses the bank argument for debugging purposes (when enabled).
986 *
987 * Note: despite inline functions being safer, everything leading to this
988 * should preferably be macros to let BUG() display the line number in
989 * the core source code since we're interested in the top call site
990 * not in any inline function location.
991 */
992
993 #if SMC_DEBUG > 0
994 #define SMC_REG(reg, bank) \
995 ({ \
996 int __b = SMC_CURRENT_BANK(); \
997 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
998 printk( "%s: bank reg screwed (0x%04x)\n", \
999 CARDNAME, __b ); \
1000 BUG(); \
1001 } \
1002 reg<<SMC_IO_SHIFT; \
1003 })
1004 #else
1005 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1006 #endif
1007
1008 /*
1009 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1010 * aligned to a 32 bit boundary. I tell you that does exist!
1011 * Fortunately the affected register accesses can be easily worked around
1012 * since we can write zeroes to the preceeding 16 bits without adverse
1013 * effects and use a 32-bit access.
1014 *
1015 * Enforce it on any 32-bit capable setup for now.
1016 */
1017 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1018
1019 #define SMC_GET_PN() \
1020 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1021 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1022
1023 #define SMC_SET_PN(x) \
1024 do { \
1025 if (SMC_MUST_ALIGN_WRITE) \
1026 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1027 else if (SMC_CAN_USE_8BIT) \
1028 SMC_outb(x, ioaddr, PN_REG); \
1029 else \
1030 SMC_outw(x, ioaddr, PN_REG); \
1031 } while (0)
1032
1033 #define SMC_GET_AR() \
1034 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1035 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1036
1037 #define SMC_GET_TXFIFO() \
1038 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1039 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1040
1041 #define SMC_GET_RXFIFO() \
1042 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1043 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1044
1045 #define SMC_GET_INT() \
1046 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1047 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1048
1049 #define SMC_ACK_INT(x) \
1050 do { \
1051 if (SMC_CAN_USE_8BIT) \
1052 SMC_outb(x, ioaddr, INT_REG); \
1053 else { \
1054 unsigned long __flags; \
1055 int __mask; \
1056 local_irq_save(__flags); \
1057 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1058 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1059 local_irq_restore(__flags); \
1060 } \
1061 } while (0)
1062
1063 #define SMC_GET_INT_MASK() \
1064 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1065 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1066
1067 #define SMC_SET_INT_MASK(x) \
1068 do { \
1069 if (SMC_CAN_USE_8BIT) \
1070 SMC_outb(x, ioaddr, IM_REG); \
1071 else \
1072 SMC_outw((x) << 8, ioaddr, INT_REG); \
1073 } while (0)
1074
1075 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1076
1077 #define SMC_SELECT_BANK(x) \
1078 do { \
1079 if (SMC_MUST_ALIGN_WRITE) \
1080 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1081 else \
1082 SMC_outw(x, ioaddr, BANK_SELECT); \
1083 } while (0)
1084
1085 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1086
1087 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1088
1089 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1090
1091 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1092
1093 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1094
1095 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1096
1097 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1098
1099 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1100
1101 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1102
1103 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1104
1105 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1106
1107 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1108
1109 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1110
1111 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1112
1113 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1114
1115 #define SMC_SET_PTR(x) \
1116 do { \
1117 if (SMC_MUST_ALIGN_WRITE) \
1118 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1119 else \
1120 SMC_outw(x, ioaddr, PTR_REG); \
1121 } while (0)
1122
1123 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1124
1125 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1126
1127 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1128
1129 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1130
1131 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1132
1133 #define SMC_SET_RPC(x) \
1134 do { \
1135 if (SMC_MUST_ALIGN_WRITE) \
1136 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1137 else \
1138 SMC_outw(x, ioaddr, RPC_REG); \
1139 } while (0)
1140
1141 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1142
1143 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1144
1145 #ifndef SMC_GET_MAC_ADDR
1146 #define SMC_GET_MAC_ADDR(addr) \
1147 do { \
1148 unsigned int __v; \
1149 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1150 addr[0] = __v; addr[1] = __v >> 8; \
1151 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1152 addr[2] = __v; addr[3] = __v >> 8; \
1153 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1154 addr[4] = __v; addr[5] = __v >> 8; \
1155 } while (0)
1156 #endif
1157
1158 #define SMC_SET_MAC_ADDR(addr) \
1159 do { \
1160 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1161 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1162 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1163 } while (0)
1164
1165 #define SMC_SET_MCAST(x) \
1166 do { \
1167 const unsigned char *mt = (x); \
1168 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1169 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1170 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1171 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1172 } while (0)
1173
1174 #define SMC_PUT_PKT_HDR(status, length) \
1175 do { \
1176 if (SMC_CAN_USE_32BIT) \
1177 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1178 else { \
1179 SMC_outw(status, ioaddr, DATA_REG); \
1180 SMC_outw(length, ioaddr, DATA_REG); \
1181 } \
1182 } while (0)
1183
1184 #define SMC_GET_PKT_HDR(status, length) \
1185 do { \
1186 if (SMC_CAN_USE_32BIT) { \
1187 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1188 (status) = __val & 0xffff; \
1189 (length) = __val >> 16; \
1190 } else { \
1191 (status) = SMC_inw(ioaddr, DATA_REG); \
1192 (length) = SMC_inw(ioaddr, DATA_REG); \
1193 } \
1194 } while (0)
1195
1196 #define SMC_PUSH_DATA(p, l) \
1197 do { \
1198 if (SMC_CAN_USE_32BIT) { \
1199 void *__ptr = (p); \
1200 int __len = (l); \
1201 void *__ioaddr = ioaddr; \
1202 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1203 __len -= 2; \
1204 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1205 __ptr += 2; \
1206 } \
1207 if (SMC_CAN_USE_DATACS && lp->datacs) \
1208 __ioaddr = lp->datacs; \
1209 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1210 if (__len & 2) { \
1211 __ptr += (__len & ~3); \
1212 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1213 } \
1214 } else if (SMC_CAN_USE_16BIT) \
1215 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1216 else if (SMC_CAN_USE_8BIT) \
1217 SMC_outsb(ioaddr, DATA_REG, p, l); \
1218 } while (0)
1219
1220 #define SMC_PULL_DATA(p, l) \
1221 do { \
1222 if (SMC_CAN_USE_32BIT) { \
1223 void *__ptr = (p); \
1224 int __len = (l); \
1225 void *__ioaddr = ioaddr; \
1226 if ((unsigned long)__ptr & 2) { \
1227 /* \
1228 * We want 32bit alignment here. \
1229 * Since some buses perform a full \
1230 * 32bit fetch even for 16bit data \
1231 * we can't use SMC_inw() here. \
1232 * Back both source (on-chip) and \
1233 * destination pointers of 2 bytes. \
1234 * This is possible since the call to \
1235 * SMC_GET_PKT_HDR() already advanced \
1236 * the source pointer of 4 bytes, and \
1237 * the skb_reserve(skb, 2) advanced \
1238 * the destination pointer of 2 bytes. \
1239 */ \
1240 __ptr -= 2; \
1241 __len += 2; \
1242 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1243 } \
1244 if (SMC_CAN_USE_DATACS && lp->datacs) \
1245 __ioaddr = lp->datacs; \
1246 __len += 2; \
1247 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1248 } else if (SMC_CAN_USE_16BIT) \
1249 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1250 else if (SMC_CAN_USE_8BIT) \
1251 SMC_insb(ioaddr, DATA_REG, p, l); \
1252 } while (0)
1253
1254 #endif /* _SMC91X_H_ */
Linux kernel - Deliverables
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