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[NET] smc91x: favor the use of SMC91X_USE_* instead of SMC_CAN_USE_*
[deliverable/linux.git] / drivers / net / smc91x.h
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK)
44
45 /* We can only do 16-bit reads and writes in the static memory space. */
46 #define SMC_CAN_USE_8BIT 0
47 #define SMC_CAN_USE_16BIT 1
48 #define SMC_CAN_USE_32BIT 0
49 #define SMC_NOWAIT 1
50
51 /* The first two address lines aren't connected... */
52 #define SMC_IO_SHIFT 2
53
54 #define SMC_inw(a, r) readw((a) + (r))
55 #define SMC_outw(v, a, r) writew(v, (a) + (r))
56 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
57 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
58 #define SMC_IRQ_FLAGS (-1) /* from resource */
59
60 #elif defined(CONFIG_BLACKFIN)
61
62 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
63 #define RPC_LSA_DEFAULT RPC_LED_100_10
64 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
65
66 # if defined (CONFIG_BFIN561_EZKIT)
67 #define SMC_CAN_USE_8BIT 0
68 #define SMC_CAN_USE_16BIT 1
69 #define SMC_CAN_USE_32BIT 1
70 #define SMC_IO_SHIFT 0
71 #define SMC_NOWAIT 1
72 #define SMC_USE_BFIN_DMA 0
73
74
75 #define SMC_inw(a, r) readw((a) + (r))
76 #define SMC_outw(v, a, r) writew(v, (a) + (r))
77 #define SMC_inl(a, r) readl((a) + (r))
78 #define SMC_outl(v, a, r) writel(v, (a) + (r))
79 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
80 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
81 # else
82 #define SMC_CAN_USE_8BIT 0
83 #define SMC_CAN_USE_16BIT 1
84 #define SMC_CAN_USE_32BIT 0
85 #define SMC_IO_SHIFT 0
86 #define SMC_NOWAIT 1
87 #define SMC_USE_BFIN_DMA 0
88
89
90 #define SMC_inw(a, r) readw((a) + (r))
91 #define SMC_outw(v, a, r) writew(v, (a) + (r))
92 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
93 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
94 # endif
95 /* check if the mac in reg is valid */
96 #define SMC_GET_MAC_ADDR(lp, addr) \
97 do { \
98 unsigned int __v; \
99 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
100 addr[0] = __v; addr[1] = __v >> 8; \
101 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
102 addr[2] = __v; addr[3] = __v >> 8; \
103 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
104 addr[4] = __v; addr[5] = __v >> 8; \
105 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
106 random_ether_addr(addr); \
107 } \
108 } while (0)
109 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
110
111 /* We can only do 16-bit reads and writes in the static memory space. */
112 #define SMC_CAN_USE_8BIT 0
113 #define SMC_CAN_USE_16BIT 1
114 #define SMC_CAN_USE_32BIT 0
115 #define SMC_NOWAIT 1
116
117 #define SMC_IO_SHIFT 0
118
119 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
120 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
121 #define SMC_insw(a, r, p, l) \
122 do { \
123 unsigned long __port = (a) + (r); \
124 u16 *__p = (u16 *)(p); \
125 int __l = (l); \
126 insw(__port, __p, __l); \
127 while (__l > 0) { \
128 *__p = swab16(*__p); \
129 __p++; \
130 __l--; \
131 } \
132 } while (0)
133 #define SMC_outsw(a, r, p, l) \
134 do { \
135 unsigned long __port = (a) + (r); \
136 u16 *__p = (u16 *)(p); \
137 int __l = (l); \
138 while (__l > 0) { \
139 /* Believe it or not, the swab isn't needed. */ \
140 outw( /* swab16 */ (*__p++), __port); \
141 __l--; \
142 } \
143 } while (0)
144 #define SMC_IRQ_FLAGS (0)
145
146 #elif defined(CONFIG_SA1100_PLEB)
147 /* We can only do 16-bit reads and writes in the static memory space. */
148 #define SMC_CAN_USE_8BIT 1
149 #define SMC_CAN_USE_16BIT 1
150 #define SMC_CAN_USE_32BIT 0
151 #define SMC_IO_SHIFT 0
152 #define SMC_NOWAIT 1
153
154 #define SMC_inb(a, r) readb((a) + (r))
155 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
156 #define SMC_inw(a, r) readw((a) + (r))
157 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
158 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
159 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
160 #define SMC_outw(v, a, r) writew(v, (a) + (r))
161 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
162
163 #define SMC_IRQ_FLAGS (-1)
164
165 #elif defined(CONFIG_SA1100_ASSABET)
166
167 #include <asm/arch/neponset.h>
168
169 /* We can only do 8-bit reads and writes in the static memory space. */
170 #define SMC_CAN_USE_8BIT 1
171 #define SMC_CAN_USE_16BIT 0
172 #define SMC_CAN_USE_32BIT 0
173 #define SMC_NOWAIT 1
174
175 /* The first two address lines aren't connected... */
176 #define SMC_IO_SHIFT 2
177
178 #define SMC_inb(a, r) readb((a) + (r))
179 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
180 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
181 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
182 #define SMC_IRQ_FLAGS (-1) /* from resource */
183
184 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
185
186 #define SMC_CAN_USE_8BIT 0
187 #define SMC_CAN_USE_16BIT 1
188 #define SMC_CAN_USE_32BIT 0
189 #define SMC_IO_SHIFT 0
190 #define SMC_NOWAIT 1
191
192 #define SMC_inw(a, r) readw((a) + (r))
193 #define SMC_outw(v, a, r) writew(v, (a) + (r))
194 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
195 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
196
197 #elif defined(CONFIG_ARCH_INNOKOM) || \
198 defined(CONFIG_MACH_MAINSTONE) || \
199 defined(CONFIG_ARCH_PXA_IDP) || \
200 defined(CONFIG_ARCH_RAMSES) || \
201 defined(CONFIG_ARCH_PCM027)
202
203 #define SMC_CAN_USE_8BIT 1
204 #define SMC_CAN_USE_16BIT 1
205 #define SMC_CAN_USE_32BIT 1
206 #define SMC_IO_SHIFT 0
207 #define SMC_NOWAIT 1
208 #define SMC_USE_PXA_DMA 1
209
210 #define SMC_inb(a, r) readb((a) + (r))
211 #define SMC_inw(a, r) readw((a) + (r))
212 #define SMC_inl(a, r) readl((a) + (r))
213 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
214 #define SMC_outl(v, a, r) writel(v, (a) + (r))
215 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
216 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
217 #define SMC_IRQ_FLAGS (-1) /* from resource */
218
219 /* We actually can't write halfwords properly if not word aligned */
220 static inline void
221 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
222 {
223 if (reg & 2) {
224 unsigned int v = val << 16;
225 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
226 writel(v, ioaddr + (reg & ~2));
227 } else {
228 writew(val, ioaddr + reg);
229 }
230 }
231
232 #elif defined(CONFIG_MACH_ZYLONITE)
233
234 #define SMC_CAN_USE_8BIT 1
235 #define SMC_CAN_USE_16BIT 1
236 #define SMC_CAN_USE_32BIT 0
237 #define SMC_IO_SHIFT 0
238 #define SMC_NOWAIT 1
239 #define SMC_USE_PXA_DMA 1
240 #define SMC_inb(a, r) readb((a) + (r))
241 #define SMC_inw(a, r) readw((a) + (r))
242 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
243 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
244 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
245 #define SMC_outw(v, a, r) writew(v, (a) + (r))
246 #define SMC_IRQ_FLAGS (-1) /* from resource */
247
248 #elif defined(CONFIG_ARCH_OMAP)
249
250 /* We can only do 16-bit reads and writes in the static memory space. */
251 #define SMC_CAN_USE_8BIT 0
252 #define SMC_CAN_USE_16BIT 1
253 #define SMC_CAN_USE_32BIT 0
254 #define SMC_IO_SHIFT 0
255 #define SMC_NOWAIT 1
256
257 #define SMC_inw(a, r) readw((a) + (r))
258 #define SMC_outw(v, a, r) writew(v, (a) + (r))
259 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
260 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
261 #define SMC_IRQ_FLAGS (-1) /* from resource */
262
263 #elif defined(CONFIG_SH_SH4202_MICRODEV)
264
265 #define SMC_CAN_USE_8BIT 0
266 #define SMC_CAN_USE_16BIT 1
267 #define SMC_CAN_USE_32BIT 0
268
269 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
270 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
271 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
272 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
273 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
274 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
275 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
276 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
277 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
278 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
279
280 #define SMC_IRQ_FLAGS (0)
281
282 #elif defined(CONFIG_ISA)
283
284 #define SMC_CAN_USE_8BIT 1
285 #define SMC_CAN_USE_16BIT 1
286 #define SMC_CAN_USE_32BIT 0
287
288 #define SMC_inb(a, r) inb((a) + (r))
289 #define SMC_inw(a, r) inw((a) + (r))
290 #define SMC_outb(v, a, r) outb(v, (a) + (r))
291 #define SMC_outw(v, a, r) outw(v, (a) + (r))
292 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
293 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
294
295 #elif defined(CONFIG_M32R)
296
297 #define SMC_CAN_USE_8BIT 0
298 #define SMC_CAN_USE_16BIT 1
299 #define SMC_CAN_USE_32BIT 0
300
301 #define SMC_inb(a, r) inb(((u32)a) + (r))
302 #define SMC_inw(a, r) inw(((u32)a) + (r))
303 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
304 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
305 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
306 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
307
308 #define SMC_IRQ_FLAGS (0)
309
310 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
311 #define RPC_LSB_DEFAULT RPC_LED_100_10
312
313 #elif defined(CONFIG_MACH_LPD79520) \
314 || defined(CONFIG_MACH_LPD7A400) \
315 || defined(CONFIG_MACH_LPD7A404)
316
317 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
318 * way that the CPU handles chip selects and the way that the SMC chip
319 * expects the chip select to operate. Refer to
320 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
321 * IOBARRIER is a byte, in order that we read the least-common
322 * denominator. It would be wasteful to read 32 bits from an 8-bit
323 * accessible region.
324 *
325 * There is no explicit protection against interrupts intervening
326 * between the writew and the IOBARRIER. In SMC ISR there is a
327 * preamble that performs an IOBARRIER in the extremely unlikely event
328 * that the driver interrupts itself between a writew to the chip an
329 * the IOBARRIER that follows *and* the cache is large enough that the
330 * first off-chip access while handing the interrupt is to the SMC
331 * chip. Other devices in the same address space as the SMC chip must
332 * be aware of the potential for trouble and perform a similar
333 * IOBARRIER on entry to their ISR.
334 */
335
336 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
337
338 #define SMC_CAN_USE_8BIT 0
339 #define SMC_CAN_USE_16BIT 1
340 #define SMC_CAN_USE_32BIT 0
341 #define SMC_NOWAIT 0
342 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
343
344 #define SMC_inw(a,r)\
345 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
346 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
347
348 #define SMC_insw LPD7_SMC_insw
349 static inline void LPD7_SMC_insw (unsigned char* a, int r,
350 unsigned char* p, int l)
351 {
352 unsigned short* ps = (unsigned short*) p;
353 while (l-- > 0) {
354 *ps++ = readw (a + r);
355 LPD7X_IOBARRIER;
356 }
357 }
358
359 #define SMC_outsw LPD7_SMC_outsw
360 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
361 unsigned char* p, int l)
362 {
363 unsigned short* ps = (unsigned short*) p;
364 while (l-- > 0) {
365 writew (*ps++, a + r);
366 LPD7X_IOBARRIER;
367 }
368 }
369
370 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
371
372 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
373 #define RPC_LSB_DEFAULT RPC_LED_100_10
374
375 #elif defined(CONFIG_SOC_AU1X00)
376
377 #include <au1xxx.h>
378
379 /* We can only do 16-bit reads and writes in the static memory space. */
380 #define SMC_CAN_USE_8BIT 0
381 #define SMC_CAN_USE_16BIT 1
382 #define SMC_CAN_USE_32BIT 0
383 #define SMC_IO_SHIFT 0
384 #define SMC_NOWAIT 1
385
386 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
387 #define SMC_insw(a, r, p, l) \
388 do { \
389 unsigned long _a = (unsigned long)((a) + (r)); \
390 int _l = (l); \
391 u16 *_p = (u16 *)(p); \
392 while (_l-- > 0) \
393 *_p++ = au_readw(_a); \
394 } while(0)
395 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
396 #define SMC_outsw(a, r, p, l) \
397 do { \
398 unsigned long _a = (unsigned long)((a) + (r)); \
399 int _l = (l); \
400 const u16 *_p = (const u16 *)(p); \
401 while (_l-- > 0) \
402 au_writew(*_p++ , _a); \
403 } while(0)
404
405 #define SMC_IRQ_FLAGS (0)
406
407 #elif defined(CONFIG_ARCH_VERSATILE)
408
409 #define SMC_CAN_USE_8BIT 1
410 #define SMC_CAN_USE_16BIT 1
411 #define SMC_CAN_USE_32BIT 1
412 #define SMC_NOWAIT 1
413
414 #define SMC_inb(a, r) readb((a) + (r))
415 #define SMC_inw(a, r) readw((a) + (r))
416 #define SMC_inl(a, r) readl((a) + (r))
417 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
418 #define SMC_outw(v, a, r) writew(v, (a) + (r))
419 #define SMC_outl(v, a, r) writel(v, (a) + (r))
420 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
421 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
422 #define SMC_IRQ_FLAGS (-1) /* from resource */
423
424 #elif defined(CONFIG_MN10300)
425
426 /*
427 * MN10300/AM33 configuration
428 */
429
430 #include <asm/unit/smc91111.h>
431
432 #else
433
434 /*
435 * Default configuration
436 */
437
438 #define SMC_CAN_USE_8BIT 1
439 #define SMC_CAN_USE_16BIT 1
440 #define SMC_CAN_USE_32BIT 1
441 #define SMC_NOWAIT 1
442
443 #define SMC_inb(a, r) readb((a) + (r))
444 #define SMC_inw(a, r) readw((a) + (r))
445 #define SMC_inl(a, r) readl((a) + (r))
446 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
447 #define SMC_outw(v, a, r) writew(v, (a) + (r))
448 #define SMC_outl(v, a, r) writel(v, (a) + (r))
449 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
450 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
451 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
452 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
453
454 #define RPC_LSA_DEFAULT RPC_LED_100_10
455 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
456
457 #endif
458
459
460 /* store this information for the driver.. */
461 struct smc_local {
462 /*
463 * If I have to wait until memory is available to send a
464 * packet, I will store the skbuff here, until I get the
465 * desired memory. Then, I'll send it out and free it.
466 */
467 struct sk_buff *pending_tx_skb;
468 struct tasklet_struct tx_task;
469
470 /* version/revision of the SMC91x chip */
471 int version;
472
473 /* Contains the current active transmission mode */
474 int tcr_cur_mode;
475
476 /* Contains the current active receive mode */
477 int rcr_cur_mode;
478
479 /* Contains the current active receive/phy mode */
480 int rpc_cur_mode;
481 int ctl_rfduplx;
482 int ctl_rspeed;
483
484 u32 msg_enable;
485 u32 phy_type;
486 struct mii_if_info mii;
487
488 /* work queue */
489 struct work_struct phy_configure;
490 struct net_device *dev;
491 int work_pending;
492
493 spinlock_t lock;
494
495 #ifdef SMC_USE_PXA_DMA
496 /* DMA needs the physical address of the chip */
497 u_long physaddr;
498 struct device *device;
499 #endif
500 void __iomem *base;
501 void __iomem *datacs;
502
503 struct smc91x_platdata cfg;
504 };
505
506 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
507 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
508 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
509
510 #ifdef SMC_USE_PXA_DMA
511 /*
512 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
513 * always happening in irq context so no need to worry about races. TX is
514 * different and probably not worth it for that reason, and not as critical
515 * as RX which can overrun memory and lose packets.
516 */
517 #include <linux/dma-mapping.h>
518 #include <asm/dma.h>
519 #include <asm/arch/pxa-regs.h>
520
521 #ifdef SMC_insl
522 #undef SMC_insl
523 #define SMC_insl(a, r, p, l) \
524 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
525 static inline void
526 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
527 u_char *buf, int len)
528 {
529 u_long physaddr = lp->physaddr;
530 dma_addr_t dmabuf;
531
532 /* fallback if no DMA available */
533 if (dma == (unsigned char)-1) {
534 readsl(ioaddr + reg, buf, len);
535 return;
536 }
537
538 /* 64 bit alignment is required for memory to memory DMA */
539 if ((long)buf & 4) {
540 *((u32 *)buf) = SMC_inl(ioaddr, reg);
541 buf += 4;
542 len--;
543 }
544
545 len *= 4;
546 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
547 DCSR(dma) = DCSR_NODESC;
548 DTADR(dma) = dmabuf;
549 DSADR(dma) = physaddr + reg;
550 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
551 DCMD_WIDTH4 | (DCMD_LENGTH & len));
552 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
553 while (!(DCSR(dma) & DCSR_STOPSTATE))
554 cpu_relax();
555 DCSR(dma) = 0;
556 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
557 }
558 #endif
559
560 #ifdef SMC_insw
561 #undef SMC_insw
562 #define SMC_insw(a, r, p, l) \
563 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
564 static inline void
565 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
566 u_char *buf, int len)
567 {
568 u_long physaddr = lp->physaddr;
569 dma_addr_t dmabuf;
570
571 /* fallback if no DMA available */
572 if (dma == (unsigned char)-1) {
573 readsw(ioaddr + reg, buf, len);
574 return;
575 }
576
577 /* 64 bit alignment is required for memory to memory DMA */
578 while ((long)buf & 6) {
579 *((u16 *)buf) = SMC_inw(ioaddr, reg);
580 buf += 2;
581 len--;
582 }
583
584 len *= 2;
585 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
586 DCSR(dma) = DCSR_NODESC;
587 DTADR(dma) = dmabuf;
588 DSADR(dma) = physaddr + reg;
589 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
590 DCMD_WIDTH2 | (DCMD_LENGTH & len));
591 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
592 while (!(DCSR(dma) & DCSR_STOPSTATE))
593 cpu_relax();
594 DCSR(dma) = 0;
595 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
596 }
597 #endif
598
599 static void
600 smc_pxa_dma_irq(int dma, void *dummy)
601 {
602 DCSR(dma) = 0;
603 }
604 #endif /* SMC_USE_PXA_DMA */
605
606
607 /*
608 * Everything a particular hardware setup needs should have been defined
609 * at this point. Add stubs for the undefined cases, mainly to avoid
610 * compilation warnings since they'll be optimized away, or to prevent buggy
611 * use of them.
612 */
613
614 #if ! SMC_CAN_USE_32BIT
615 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
616 #define SMC_outl(x, ioaddr, reg) BUG()
617 #define SMC_insl(a, r, p, l) BUG()
618 #define SMC_outsl(a, r, p, l) BUG()
619 #endif
620
621 #if !defined(SMC_insl) || !defined(SMC_outsl)
622 #define SMC_insl(a, r, p, l) BUG()
623 #define SMC_outsl(a, r, p, l) BUG()
624 #endif
625
626 #if ! SMC_CAN_USE_16BIT
627
628 /*
629 * Any 16-bit access is performed with two 8-bit accesses if the hardware
630 * can't do it directly. Most registers are 16-bit so those are mandatory.
631 */
632 #define SMC_outw(x, ioaddr, reg) \
633 do { \
634 unsigned int __val16 = (x); \
635 SMC_outb( __val16, ioaddr, reg ); \
636 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
637 } while (0)
638 #define SMC_inw(ioaddr, reg) \
639 ({ \
640 unsigned int __val16; \
641 __val16 = SMC_inb( ioaddr, reg ); \
642 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
643 __val16; \
644 })
645
646 #define SMC_insw(a, r, p, l) BUG()
647 #define SMC_outsw(a, r, p, l) BUG()
648
649 #endif
650
651 #if !defined(SMC_insw) || !defined(SMC_outsw)
652 #define SMC_insw(a, r, p, l) BUG()
653 #define SMC_outsw(a, r, p, l) BUG()
654 #endif
655
656 #if ! SMC_CAN_USE_8BIT
657 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
658 #define SMC_outb(x, ioaddr, reg) BUG()
659 #define SMC_insb(a, r, p, l) BUG()
660 #define SMC_outsb(a, r, p, l) BUG()
661 #endif
662
663 #if !defined(SMC_insb) || !defined(SMC_outsb)
664 #define SMC_insb(a, r, p, l) BUG()
665 #define SMC_outsb(a, r, p, l) BUG()
666 #endif
667
668 #ifndef SMC_CAN_USE_DATACS
669 #define SMC_CAN_USE_DATACS 0
670 #endif
671
672 #ifndef SMC_IO_SHIFT
673 #define SMC_IO_SHIFT 0
674 #endif
675
676 #ifndef SMC_IRQ_FLAGS
677 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
678 #endif
679
680 #ifndef SMC_INTERRUPT_PREAMBLE
681 #define SMC_INTERRUPT_PREAMBLE
682 #endif
683
684
685 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
686 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
687 #define SMC_DATA_EXTENT (4)
688
689 /*
690 . Bank Select Register:
691 .
692 . yyyy yyyy 0000 00xx
693 . xx = bank number
694 . yyyy yyyy = 0x33, for identification purposes.
695 */
696 #define BANK_SELECT (14 << SMC_IO_SHIFT)
697
698
699 // Transmit Control Register
700 /* BANK 0 */
701 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
702 #define TCR_ENABLE 0x0001 // When 1 we can transmit
703 #define TCR_LOOP 0x0002 // Controls output pin LBK
704 #define TCR_FORCOL 0x0004 // When 1 will force a collision
705 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
706 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
707 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
708 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
709 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
710 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
711 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
712
713 #define TCR_CLEAR 0 /* do NOTHING */
714 /* the default settings for the TCR register : */
715 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
716
717
718 // EPH Status Register
719 /* BANK 0 */
720 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
721 #define ES_TX_SUC 0x0001 // Last TX was successful
722 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
723 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
724 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
725 #define ES_16COL 0x0010 // 16 Collisions Reached
726 #define ES_SQET 0x0020 // Signal Quality Error Test
727 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
728 #define ES_TXDEFR 0x0080 // Transmit Deferred
729 #define ES_LATCOL 0x0200 // Late collision detected on last tx
730 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
731 #define ES_EXC_DEF 0x0800 // Excessive Deferral
732 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
733 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
734 #define ES_TXUNRN 0x8000 // Tx Underrun
735
736
737 // Receive Control Register
738 /* BANK 0 */
739 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
740 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
741 #define RCR_PRMS 0x0002 // Enable promiscuous mode
742 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
743 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
744 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
745 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
746 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
747 #define RCR_SOFTRST 0x8000 // resets the chip
748
749 /* the normal settings for the RCR register : */
750 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
751 #define RCR_CLEAR 0x0 // set it to a base state
752
753
754 // Counter Register
755 /* BANK 0 */
756 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
757
758
759 // Memory Information Register
760 /* BANK 0 */
761 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
762
763
764 // Receive/Phy Control Register
765 /* BANK 0 */
766 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
767 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
768 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
769 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
770 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
771 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
772 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
773 #define RPC_LED_RES (0x01) // LED = Reserved
774 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
775 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
776 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
777 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
778 #define RPC_LED_TX (0x06) // LED = TX packet occurred
779 #define RPC_LED_RX (0x07) // LED = RX packet occurred
780
781 #ifndef RPC_LSA_DEFAULT
782 #define RPC_LSA_DEFAULT RPC_LED_100
783 #endif
784 #ifndef RPC_LSB_DEFAULT
785 #define RPC_LSB_DEFAULT RPC_LED_FD
786 #endif
787
788 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
789
790
791 /* Bank 0 0x0C is reserved */
792
793 // Bank Select Register
794 /* All Banks */
795 #define BSR_REG 0x000E
796
797
798 // Configuration Reg
799 /* BANK 1 */
800 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
801 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
802 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
803 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
804 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
805
806 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
807 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
808
809
810 // Base Address Register
811 /* BANK 1 */
812 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
813
814
815 // Individual Address Registers
816 /* BANK 1 */
817 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
818 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
819 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
820
821
822 // General Purpose Register
823 /* BANK 1 */
824 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
825
826
827 // Control Register
828 /* BANK 1 */
829 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
830 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
831 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
832 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
833 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
834 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
835 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
836 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
837 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
838
839
840 // MMU Command Register
841 /* BANK 2 */
842 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
843 #define MC_BUSY 1 // When 1 the last release has not completed
844 #define MC_NOP (0<<5) // No Op
845 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
846 #define MC_RESET (2<<5) // Reset MMU to initial state
847 #define MC_REMOVE (3<<5) // Remove the current rx packet
848 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
849 #define MC_FREEPKT (5<<5) // Release packet in PNR register
850 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
851 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
852
853
854 // Packet Number Register
855 /* BANK 2 */
856 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
857
858
859 // Allocation Result Register
860 /* BANK 2 */
861 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
862 #define AR_FAILED 0x80 // Alocation Failed
863
864
865 // TX FIFO Ports Register
866 /* BANK 2 */
867 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
868 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
869
870 // RX FIFO Ports Register
871 /* BANK 2 */
872 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
873 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
874
875 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
876
877 // Pointer Register
878 /* BANK 2 */
879 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
880 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
881 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
882 #define PTR_READ 0x2000 // When 1 the operation is a read
883
884
885 // Data Register
886 /* BANK 2 */
887 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
888
889
890 // Interrupt Status/Acknowledge Register
891 /* BANK 2 */
892 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
893
894
895 // Interrupt Mask Register
896 /* BANK 2 */
897 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
898 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
899 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
900 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
901 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
902 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
903 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
904 #define IM_TX_INT 0x02 // Transmit Interrupt
905 #define IM_RCV_INT 0x01 // Receive Interrupt
906
907
908 // Multicast Table Registers
909 /* BANK 3 */
910 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
911 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
912 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
913 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
914
915
916 // Management Interface Register (MII)
917 /* BANK 3 */
918 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
919 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
920 #define MII_MDOE 0x0008 // MII Output Enable
921 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
922 #define MII_MDI 0x0002 // MII Input, pin MDI
923 #define MII_MDO 0x0001 // MII Output, pin MDO
924
925
926 // Revision Register
927 /* BANK 3 */
928 /* ( hi: chip id low: rev # ) */
929 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
930
931
932 // Early RCV Register
933 /* BANK 3 */
934 /* this is NOT on SMC9192 */
935 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
936 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
937 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
938
939
940 // External Register
941 /* BANK 7 */
942 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
943
944
945 #define CHIP_9192 3
946 #define CHIP_9194 4
947 #define CHIP_9195 5
948 #define CHIP_9196 6
949 #define CHIP_91100 7
950 #define CHIP_91100FD 8
951 #define CHIP_91111FD 9
952
953 static const char * chip_ids[ 16 ] = {
954 NULL, NULL, NULL,
955 /* 3 */ "SMC91C90/91C92",
956 /* 4 */ "SMC91C94",
957 /* 5 */ "SMC91C95",
958 /* 6 */ "SMC91C96",
959 /* 7 */ "SMC91C100",
960 /* 8 */ "SMC91C100FD",
961 /* 9 */ "SMC91C11xFD",
962 NULL, NULL, NULL,
963 NULL, NULL, NULL};
964
965
966 /*
967 . Receive status bits
968 */
969 #define RS_ALGNERR 0x8000
970 #define RS_BRODCAST 0x4000
971 #define RS_BADCRC 0x2000
972 #define RS_ODDFRAME 0x1000
973 #define RS_TOOLONG 0x0800
974 #define RS_TOOSHORT 0x0400
975 #define RS_MULTICAST 0x0001
976 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
977
978
979 /*
980 * PHY IDs
981 * LAN83C183 == LAN91C111 Internal PHY
982 */
983 #define PHY_LAN83C183 0x0016f840
984 #define PHY_LAN83C180 0x02821c50
985
986 /*
987 * PHY Register Addresses (LAN91C111 Internal PHY)
988 *
989 * Generic PHY registers can be found in <linux/mii.h>
990 *
991 * These phy registers are specific to our on-board phy.
992 */
993
994 // PHY Configuration Register 1
995 #define PHY_CFG1_REG 0x10
996 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
997 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
998 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
999 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1000 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1001 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1002 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1003 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1004 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1005 #define PHY_CFG1_TLVL_MASK 0x003C
1006 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1007
1008
1009 // PHY Configuration Register 2
1010 #define PHY_CFG2_REG 0x11
1011 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1012 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1013 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1014 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1015
1016 // PHY Status Output (and Interrupt status) Register
1017 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1018 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1019 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1020 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1021 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1022 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1023 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1024 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1025 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1026 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1027 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1028
1029 // PHY Interrupt/Status Mask Register
1030 #define PHY_MASK_REG 0x13 // Interrupt Mask
1031 // Uses the same bit definitions as PHY_INT_REG
1032
1033
1034 /*
1035 * SMC91C96 ethernet config and status registers.
1036 * These are in the "attribute" space.
1037 */
1038 #define ECOR 0x8000
1039 #define ECOR_RESET 0x80
1040 #define ECOR_LEVEL_IRQ 0x40
1041 #define ECOR_WR_ATTRIB 0x04
1042 #define ECOR_ENABLE 0x01
1043
1044 #define ECSR 0x8002
1045 #define ECSR_IOIS8 0x20
1046 #define ECSR_PWRDWN 0x04
1047 #define ECSR_INT 0x02
1048
1049 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1050
1051
1052 /*
1053 * Macros to abstract register access according to the data bus
1054 * capabilities. Please use those and not the in/out primitives.
1055 * Note: the following macros do *not* select the bank -- this must
1056 * be done separately as needed in the main code. The SMC_REG() macro
1057 * only uses the bank argument for debugging purposes (when enabled).
1058 *
1059 * Note: despite inline functions being safer, everything leading to this
1060 * should preferably be macros to let BUG() display the line number in
1061 * the core source code since we're interested in the top call site
1062 * not in any inline function location.
1063 */
1064
1065 #if SMC_DEBUG > 0
1066 #define SMC_REG(lp, reg, bank) \
1067 ({ \
1068 int __b = SMC_CURRENT_BANK(lp); \
1069 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1070 printk( "%s: bank reg screwed (0x%04x)\n", \
1071 CARDNAME, __b ); \
1072 BUG(); \
1073 } \
1074 reg<<SMC_IO_SHIFT; \
1075 })
1076 #else
1077 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1078 #endif
1079
1080 /*
1081 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1082 * aligned to a 32 bit boundary. I tell you that does exist!
1083 * Fortunately the affected register accesses can be easily worked around
1084 * since we can write zeroes to the preceeding 16 bits without adverse
1085 * effects and use a 32-bit access.
1086 *
1087 * Enforce it on any 32-bit capable setup for now.
1088 */
1089 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1090
1091 #define SMC_GET_PN(lp) \
1092 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1093 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1094
1095 #define SMC_SET_PN(lp, x) \
1096 do { \
1097 if (SMC_MUST_ALIGN_WRITE(lp)) \
1098 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1099 else if (SMC_8BIT(lp)) \
1100 SMC_outb(x, ioaddr, PN_REG(lp)); \
1101 else \
1102 SMC_outw(x, ioaddr, PN_REG(lp)); \
1103 } while (0)
1104
1105 #define SMC_GET_AR(lp) \
1106 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1107 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1108
1109 #define SMC_GET_TXFIFO(lp) \
1110 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1111 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1112
1113 #define SMC_GET_RXFIFO(lp) \
1114 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1115 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1116
1117 #define SMC_GET_INT(lp) \
1118 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1119 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1120
1121 #define SMC_ACK_INT(lp, x) \
1122 do { \
1123 if (SMC_8BIT(lp)) \
1124 SMC_outb(x, ioaddr, INT_REG(lp)); \
1125 else { \
1126 unsigned long __flags; \
1127 int __mask; \
1128 local_irq_save(__flags); \
1129 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1130 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1131 local_irq_restore(__flags); \
1132 } \
1133 } while (0)
1134
1135 #define SMC_GET_INT_MASK(lp) \
1136 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1137 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1138
1139 #define SMC_SET_INT_MASK(lp, x) \
1140 do { \
1141 if (SMC_8BIT(lp)) \
1142 SMC_outb(x, ioaddr, IM_REG(lp)); \
1143 else \
1144 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1145 } while (0)
1146
1147 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1148
1149 #define SMC_SELECT_BANK(lp, x) \
1150 do { \
1151 if (SMC_MUST_ALIGN_WRITE(lp)) \
1152 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1153 else \
1154 SMC_outw(x, ioaddr, BANK_SELECT); \
1155 } while (0)
1156
1157 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1158
1159 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1160
1161 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1162
1163 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1164
1165 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1166
1167 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1168
1169 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1170
1171 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1172
1173 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1174
1175 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1176
1177 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1178
1179 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1180
1181 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1182
1183 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1184
1185 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1186
1187 #define SMC_SET_PTR(lp, x) \
1188 do { \
1189 if (SMC_MUST_ALIGN_WRITE(lp)) \
1190 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1191 else \
1192 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1193 } while (0)
1194
1195 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1196
1197 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1198
1199 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1200
1201 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1202
1203 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1204
1205 #define SMC_SET_RPC(lp, x) \
1206 do { \
1207 if (SMC_MUST_ALIGN_WRITE(lp)) \
1208 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1209 else \
1210 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1211 } while (0)
1212
1213 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1214
1215 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1216
1217 #ifndef SMC_GET_MAC_ADDR
1218 #define SMC_GET_MAC_ADDR(lp, addr) \
1219 do { \
1220 unsigned int __v; \
1221 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1222 addr[0] = __v; addr[1] = __v >> 8; \
1223 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1224 addr[2] = __v; addr[3] = __v >> 8; \
1225 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1226 addr[4] = __v; addr[5] = __v >> 8; \
1227 } while (0)
1228 #endif
1229
1230 #define SMC_SET_MAC_ADDR(lp, addr) \
1231 do { \
1232 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1233 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1234 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1235 } while (0)
1236
1237 #define SMC_SET_MCAST(lp, x) \
1238 do { \
1239 const unsigned char *mt = (x); \
1240 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1241 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1242 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1243 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1244 } while (0)
1245
1246 #define SMC_PUT_PKT_HDR(lp, status, length) \
1247 do { \
1248 if (SMC_32BIT(lp)) \
1249 SMC_outl((status) | (length)<<16, ioaddr, \
1250 DATA_REG(lp)); \
1251 else { \
1252 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1253 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1254 } \
1255 } while (0)
1256
1257 #define SMC_GET_PKT_HDR(lp, status, length) \
1258 do { \
1259 if (SMC_32BIT(lp)) { \
1260 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1261 (status) = __val & 0xffff; \
1262 (length) = __val >> 16; \
1263 } else { \
1264 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1265 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1266 } \
1267 } while (0)
1268
1269 #define SMC_PUSH_DATA(lp, p, l) \
1270 do { \
1271 if (SMC_32BIT(lp)) { \
1272 void *__ptr = (p); \
1273 int __len = (l); \
1274 void __iomem *__ioaddr = ioaddr; \
1275 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1276 __len -= 2; \
1277 SMC_outw(*(u16 *)__ptr, ioaddr, \
1278 DATA_REG(lp)); \
1279 __ptr += 2; \
1280 } \
1281 if (SMC_CAN_USE_DATACS && lp->datacs) \
1282 __ioaddr = lp->datacs; \
1283 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1284 if (__len & 2) { \
1285 __ptr += (__len & ~3); \
1286 SMC_outw(*((u16 *)__ptr), ioaddr, \
1287 DATA_REG(lp)); \
1288 } \
1289 } else if (SMC_16BIT(lp)) \
1290 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1291 else if (SMC_8BIT(lp)) \
1292 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1293 } while (0)
1294
1295 #define SMC_PULL_DATA(lp, p, l) \
1296 do { \
1297 if (SMC_32BIT(lp)) { \
1298 void *__ptr = (p); \
1299 int __len = (l); \
1300 void __iomem *__ioaddr = ioaddr; \
1301 if ((unsigned long)__ptr & 2) { \
1302 /* \
1303 * We want 32bit alignment here. \
1304 * Since some buses perform a full \
1305 * 32bit fetch even for 16bit data \
1306 * we can't use SMC_inw() here. \
1307 * Back both source (on-chip) and \
1308 * destination pointers of 2 bytes. \
1309 * This is possible since the call to \
1310 * SMC_GET_PKT_HDR() already advanced \
1311 * the source pointer of 4 bytes, and \
1312 * the skb_reserve(skb, 2) advanced \
1313 * the destination pointer of 2 bytes. \
1314 */ \
1315 __ptr -= 2; \
1316 __len += 2; \
1317 SMC_SET_PTR(lp, \
1318 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1319 } \
1320 if (SMC_CAN_USE_DATACS && lp->datacs) \
1321 __ioaddr = lp->datacs; \
1322 __len += 2; \
1323 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1324 } else if (SMC_16BIT(lp)) \
1325 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1326 else if (SMC_8BIT(lp)) \
1327 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1328 } while (0)
1329
1330 #endif /* _SMC91X_H_ */
Linux kernel - Deliverables
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