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[NET]: Introduce and use print_mac() and DECLARE_MAC_BUF()
[deliverable/linux.git] / drivers / net / sundance.c
1 /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
2 /*
3 Written 1999-2000 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/sundance.html
19 [link no longer provides useful info -jgarzik]
20 Archives of the mailing list are still available at
21 http://www.beowulf.org/pipermail/netdrivers/
22
23 */
24
25 #define DRV_NAME "sundance"
26 #define DRV_VERSION "1.2"
27 #define DRV_RELDATE "11-Sep-2006"
28
29
30 /* The user-configurable values.
31 These may be modified when a driver module is loaded.*/
32 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
33 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
34 Typical is a 64 element hash table based on the Ethernet CRC. */
35 static const int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
38 Setting to > 1518 effectively disables this feature.
39 This chip can receive into offset buffers, so the Alpha does not
40 need a copy-align. */
41 static int rx_copybreak;
42 static int flowctrl=1;
43
44 /* media[] specifies the media type the NIC operates at.
45 autosense Autosensing active media.
46 10mbps_hd 10Mbps half duplex.
47 10mbps_fd 10Mbps full duplex.
48 100mbps_hd 100Mbps half duplex.
49 100mbps_fd 100Mbps full duplex.
50 0 Autosensing active media.
51 1 10Mbps half duplex.
52 2 10Mbps full duplex.
53 3 100Mbps half duplex.
54 4 100Mbps full duplex.
55 */
56 #define MAX_UNITS 8
57 static char *media[MAX_UNITS];
58
59
60 /* Operational parameters that are set at compile time. */
61
62 /* Keep the ring sizes a power of two for compile efficiency.
63 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
64 Making the Tx ring too large decreases the effectiveness of channel
65 bonding and packet priority, and more than 128 requires modifying the
66 Tx error recovery.
67 Large receive rings merely waste memory. */
68 #define TX_RING_SIZE 32
69 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */
70 #define RX_RING_SIZE 64
71 #define RX_BUDGET 32
72 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
73 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
74
75 /* Operational parameters that usually are not changed. */
76 /* Time in jiffies before concluding the transmitter is hung. */
77 #define TX_TIMEOUT (4*HZ)
78 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
79
80 /* Include files, designed to support most kernel versions 2.0.0 and later. */
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/string.h>
84 #include <linux/timer.h>
85 #include <linux/errno.h>
86 #include <linux/ioport.h>
87 #include <linux/slab.h>
88 #include <linux/interrupt.h>
89 #include <linux/pci.h>
90 #include <linux/netdevice.h>
91 #include <linux/etherdevice.h>
92 #include <linux/skbuff.h>
93 #include <linux/init.h>
94 #include <linux/bitops.h>
95 #include <asm/uaccess.h>
96 #include <asm/processor.h> /* Processor type for cache alignment. */
97 #include <asm/io.h>
98 #include <linux/delay.h>
99 #include <linux/spinlock.h>
100 #ifndef _COMPAT_WITH_OLD_KERNEL
101 #include <linux/crc32.h>
102 #include <linux/ethtool.h>
103 #include <linux/mii.h>
104 #else
105 #include "crc32.h"
106 #include "ethtool.h"
107 #include "mii.h"
108 #include "compat.h"
109 #endif
110
111 /* These identify the driver base version and may not be removed. */
112 static char version[] =
113 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
114
115 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
116 MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
117 MODULE_LICENSE("GPL");
118
119 module_param(debug, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param_array(media, charp, NULL, 0);
122 module_param(flowctrl, int, 0);
123 MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)");
124 MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames");
125 MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]");
126
127 /*
128 Theory of Operation
129
130 I. Board Compatibility
131
132 This driver is designed for the Sundance Technologies "Alta" ST201 chip.
133
134 II. Board-specific settings
135
136 III. Driver operation
137
138 IIIa. Ring buffers
139
140 This driver uses two statically allocated fixed-size descriptor lists
141 formed into rings by a branch from the final descriptor to the beginning of
142 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
143 Some chips explicitly use only 2^N sized rings, while others use a
144 'next descriptor' pointer that the driver forms into rings.
145
146 IIIb/c. Transmit/Receive Structure
147
148 This driver uses a zero-copy receive and transmit scheme.
149 The driver allocates full frame size skbuffs for the Rx ring buffers at
150 open() time and passes the skb->data field to the chip as receive data
151 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
152 a fresh skbuff is allocated and the frame is copied to the new skbuff.
153 When the incoming frame is larger, the skbuff is passed directly up the
154 protocol stack. Buffers consumed this way are replaced by newly allocated
155 skbuffs in a later phase of receives.
156
157 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
158 using a full-sized skbuff for small frames vs. the copying costs of larger
159 frames. New boards are typically used in generously configured machines
160 and the underfilled buffers have negligible impact compared to the benefit of
161 a single allocation size, so the default value of zero results in never
162 copying packets. When copying is done, the cost is usually mitigated by using
163 a combined copy/checksum routine. Copying also preloads the cache, which is
164 most useful with small frames.
165
166 A subtle aspect of the operation is that the IP header at offset 14 in an
167 ethernet frame isn't longword aligned for further processing.
168 Unaligned buffers are permitted by the Sundance hardware, so
169 frames are received into the skbuff at an offset of "+2", 16-byte aligning
170 the IP header.
171
172 IIId. Synchronization
173
174 The driver runs as two independent, single-threaded flows of control. One
175 is the send-packet routine, which enforces single-threaded use by the
176 dev->tbusy flag. The other thread is the interrupt handler, which is single
177 threaded by the hardware and interrupt handling software.
178
179 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
180 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
181 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
182 the 'lp->tx_full' flag.
183
184 The interrupt handler has exclusive control over the Rx ring and records stats
185 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
186 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
187 clears both the tx_full and tbusy flags.
188
189 IV. Notes
190
191 IVb. References
192
193 The Sundance ST201 datasheet, preliminary version.
194 The Kendin KS8723 datasheet, preliminary version.
195 The ICplus IP100 datasheet, preliminary version.
196 http://www.scyld.com/expert/100mbps.html
197 http://www.scyld.com/expert/NWay.html
198
199 IVc. Errata
200
201 */
202
203 /* Work-around for Kendin chip bugs. */
204 #ifndef CONFIG_SUNDANCE_MMIO
205 #define USE_IO_OPS 1
206 #endif
207
208 static const struct pci_device_id sundance_pci_tbl[] = {
209 { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
210 { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
211 { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
212 { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
213 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
214 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
215 { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
216 { }
217 };
218 MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
219
220 enum {
221 netdev_io_size = 128
222 };
223
224 struct pci_id_info {
225 const char *name;
226 };
227 static const struct pci_id_info pci_id_tbl[] __devinitdata = {
228 {"D-Link DFE-550TX FAST Ethernet Adapter"},
229 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
230 {"D-Link DFE-580TX 4 port Server Adapter"},
231 {"D-Link DFE-530TXS FAST Ethernet Adapter"},
232 {"D-Link DL10050-based FAST Ethernet Adapter"},
233 {"Sundance Technology Alta"},
234 {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
235 { } /* terminate list. */
236 };
237
238 /* This driver was written to use PCI memory space, however x86-oriented
239 hardware often uses I/O space accesses. */
240
241 /* Offsets to the device registers.
242 Unlike software-only systems, device drivers interact with complex hardware.
243 It's not useful to define symbolic names for every register bit in the
244 device. The name can only partially document the semantics and make
245 the driver longer and more difficult to read.
246 In general, only the important configuration values or bits changed
247 multiple times should be defined symbolically.
248 */
249 enum alta_offsets {
250 DMACtrl = 0x00,
251 TxListPtr = 0x04,
252 TxDMABurstThresh = 0x08,
253 TxDMAUrgentThresh = 0x09,
254 TxDMAPollPeriod = 0x0a,
255 RxDMAStatus = 0x0c,
256 RxListPtr = 0x10,
257 DebugCtrl0 = 0x1a,
258 DebugCtrl1 = 0x1c,
259 RxDMABurstThresh = 0x14,
260 RxDMAUrgentThresh = 0x15,
261 RxDMAPollPeriod = 0x16,
262 LEDCtrl = 0x1a,
263 ASICCtrl = 0x30,
264 EEData = 0x34,
265 EECtrl = 0x36,
266 FlashAddr = 0x40,
267 FlashData = 0x44,
268 TxStatus = 0x46,
269 TxFrameId = 0x47,
270 DownCounter = 0x18,
271 IntrClear = 0x4a,
272 IntrEnable = 0x4c,
273 IntrStatus = 0x4e,
274 MACCtrl0 = 0x50,
275 MACCtrl1 = 0x52,
276 StationAddr = 0x54,
277 MaxFrameSize = 0x5A,
278 RxMode = 0x5c,
279 MIICtrl = 0x5e,
280 MulticastFilter0 = 0x60,
281 MulticastFilter1 = 0x64,
282 RxOctetsLow = 0x68,
283 RxOctetsHigh = 0x6a,
284 TxOctetsLow = 0x6c,
285 TxOctetsHigh = 0x6e,
286 TxFramesOK = 0x70,
287 RxFramesOK = 0x72,
288 StatsCarrierError = 0x74,
289 StatsLateColl = 0x75,
290 StatsMultiColl = 0x76,
291 StatsOneColl = 0x77,
292 StatsTxDefer = 0x78,
293 RxMissed = 0x79,
294 StatsTxXSDefer = 0x7a,
295 StatsTxAbort = 0x7b,
296 StatsBcastTx = 0x7c,
297 StatsBcastRx = 0x7d,
298 StatsMcastTx = 0x7e,
299 StatsMcastRx = 0x7f,
300 /* Aliased and bogus values! */
301 RxStatus = 0x0c,
302 };
303 enum ASICCtrl_HiWord_bit {
304 GlobalReset = 0x0001,
305 RxReset = 0x0002,
306 TxReset = 0x0004,
307 DMAReset = 0x0008,
308 FIFOReset = 0x0010,
309 NetworkReset = 0x0020,
310 HostReset = 0x0040,
311 ResetBusy = 0x0400,
312 };
313
314 /* Bits in the interrupt status/mask registers. */
315 enum intr_status_bits {
316 IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
317 IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
318 IntrDrvRqst=0x0040,
319 StatsMax=0x0080, LinkChange=0x0100,
320 IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
321 };
322
323 /* Bits in the RxMode register. */
324 enum rx_mode_bits {
325 AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
326 AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
327 };
328 /* Bits in MACCtrl. */
329 enum mac_ctrl0_bits {
330 EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
331 EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
332 };
333 enum mac_ctrl1_bits {
334 StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
335 TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
336 RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
337 };
338
339 /* The Rx and Tx buffer descriptors. */
340 /* Note that using only 32 bit fields simplifies conversion to big-endian
341 architectures. */
342 struct netdev_desc {
343 u32 next_desc;
344 u32 status;
345 struct desc_frag { u32 addr, length; } frag[1];
346 };
347
348 /* Bits in netdev_desc.status */
349 enum desc_status_bits {
350 DescOwn=0x8000,
351 DescEndPacket=0x4000,
352 DescEndRing=0x2000,
353 LastFrag=0x80000000,
354 DescIntrOnTx=0x8000,
355 DescIntrOnDMADone=0x80000000,
356 DisableAlign = 0x00000001,
357 };
358
359 #define PRIV_ALIGN 15 /* Required alignment mask */
360 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
361 within the structure. */
362 #define MII_CNT 4
363 struct netdev_private {
364 /* Descriptor rings first for alignment. */
365 struct netdev_desc *rx_ring;
366 struct netdev_desc *tx_ring;
367 struct sk_buff* rx_skbuff[RX_RING_SIZE];
368 struct sk_buff* tx_skbuff[TX_RING_SIZE];
369 dma_addr_t tx_ring_dma;
370 dma_addr_t rx_ring_dma;
371 struct net_device_stats stats;
372 struct timer_list timer; /* Media monitoring timer. */
373 /* Frequently used values: keep some adjacent for cache effect. */
374 spinlock_t lock;
375 spinlock_t rx_lock; /* Group with Tx control cache line. */
376 int msg_enable;
377 int chip_id;
378 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
379 unsigned int rx_buf_sz; /* Based on MTU+slack. */
380 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
381 unsigned int cur_tx, dirty_tx;
382 /* These values are keep track of the transceiver/media in use. */
383 unsigned int flowctrl:1;
384 unsigned int default_port:4; /* Last dev->if_port value. */
385 unsigned int an_enable:1;
386 unsigned int speed;
387 struct tasklet_struct rx_tasklet;
388 struct tasklet_struct tx_tasklet;
389 int budget;
390 int cur_task;
391 /* Multicast and receive mode. */
392 spinlock_t mcastlock; /* SMP lock multicast updates. */
393 u16 mcast_filter[4];
394 /* MII transceiver section. */
395 struct mii_if_info mii_if;
396 int mii_preamble_required;
397 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
398 struct pci_dev *pci_dev;
399 void __iomem *base;
400 };
401
402 /* The station address location in the EEPROM. */
403 #define EEPROM_SA_OFFSET 0x10
404 #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
405 IntrDrvRqst | IntrTxDone | StatsMax | \
406 LinkChange)
407
408 static int change_mtu(struct net_device *dev, int new_mtu);
409 static int eeprom_read(void __iomem *ioaddr, int location);
410 static int mdio_read(struct net_device *dev, int phy_id, int location);
411 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
412 static int netdev_open(struct net_device *dev);
413 static void check_duplex(struct net_device *dev);
414 static void netdev_timer(unsigned long data);
415 static void tx_timeout(struct net_device *dev);
416 static void init_ring(struct net_device *dev);
417 static int start_tx(struct sk_buff *skb, struct net_device *dev);
418 static int reset_tx (struct net_device *dev);
419 static irqreturn_t intr_handler(int irq, void *dev_instance);
420 static void rx_poll(unsigned long data);
421 static void tx_poll(unsigned long data);
422 static void refill_rx (struct net_device *dev);
423 static void netdev_error(struct net_device *dev, int intr_status);
424 static void netdev_error(struct net_device *dev, int intr_status);
425 static void set_rx_mode(struct net_device *dev);
426 static int __set_mac_addr(struct net_device *dev);
427 static struct net_device_stats *get_stats(struct net_device *dev);
428 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
429 static int netdev_close(struct net_device *dev);
430 static const struct ethtool_ops ethtool_ops;
431
432 static void sundance_reset(struct net_device *dev, unsigned long reset_cmd)
433 {
434 struct netdev_private *np = netdev_priv(dev);
435 void __iomem *ioaddr = np->base + ASICCtrl;
436 int countdown;
437
438 /* ST201 documentation states ASICCtrl is a 32bit register */
439 iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr);
440 /* ST201 documentation states reset can take up to 1 ms */
441 countdown = 10 + 1;
442 while (ioread32 (ioaddr) & (ResetBusy << 16)) {
443 if (--countdown == 0) {
444 printk(KERN_WARNING "%s : reset not completed !!\n", dev->name);
445 break;
446 }
447 udelay(100);
448 }
449 }
450
451 static int __devinit sundance_probe1 (struct pci_dev *pdev,
452 const struct pci_device_id *ent)
453 {
454 struct net_device *dev;
455 struct netdev_private *np;
456 static int card_idx;
457 int chip_idx = ent->driver_data;
458 int irq;
459 int i;
460 void __iomem *ioaddr;
461 u16 mii_ctl;
462 void *ring_space;
463 dma_addr_t ring_dma;
464 #ifdef USE_IO_OPS
465 int bar = 0;
466 #else
467 int bar = 1;
468 #endif
469 int phy, phy_idx = 0;
470 DECLARE_MAC_BUF(mac);
471
472 /* when built into the kernel, we only print version if device is found */
473 #ifndef MODULE
474 static int printed_version;
475 if (!printed_version++)
476 printk(version);
477 #endif
478
479 if (pci_enable_device(pdev))
480 return -EIO;
481 pci_set_master(pdev);
482
483 irq = pdev->irq;
484
485 dev = alloc_etherdev(sizeof(*np));
486 if (!dev)
487 return -ENOMEM;
488 SET_NETDEV_DEV(dev, &pdev->dev);
489
490 if (pci_request_regions(pdev, DRV_NAME))
491 goto err_out_netdev;
492
493 ioaddr = pci_iomap(pdev, bar, netdev_io_size);
494 if (!ioaddr)
495 goto err_out_res;
496
497 for (i = 0; i < 3; i++)
498 ((u16 *)dev->dev_addr)[i] =
499 le16_to_cpu(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
500 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
501
502 dev->base_addr = (unsigned long)ioaddr;
503 dev->irq = irq;
504
505 np = netdev_priv(dev);
506 np->base = ioaddr;
507 np->pci_dev = pdev;
508 np->chip_id = chip_idx;
509 np->msg_enable = (1 << debug) - 1;
510 spin_lock_init(&np->lock);
511 tasklet_init(&np->rx_tasklet, rx_poll, (unsigned long)dev);
512 tasklet_init(&np->tx_tasklet, tx_poll, (unsigned long)dev);
513
514 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
515 if (!ring_space)
516 goto err_out_cleardev;
517 np->tx_ring = (struct netdev_desc *)ring_space;
518 np->tx_ring_dma = ring_dma;
519
520 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
521 if (!ring_space)
522 goto err_out_unmap_tx;
523 np->rx_ring = (struct netdev_desc *)ring_space;
524 np->rx_ring_dma = ring_dma;
525
526 np->mii_if.dev = dev;
527 np->mii_if.mdio_read = mdio_read;
528 np->mii_if.mdio_write = mdio_write;
529 np->mii_if.phy_id_mask = 0x1f;
530 np->mii_if.reg_num_mask = 0x1f;
531
532 /* The chip-specific entries in the device structure. */
533 dev->open = &netdev_open;
534 dev->hard_start_xmit = &start_tx;
535 dev->stop = &netdev_close;
536 dev->get_stats = &get_stats;
537 dev->set_multicast_list = &set_rx_mode;
538 dev->do_ioctl = &netdev_ioctl;
539 SET_ETHTOOL_OPS(dev, &ethtool_ops);
540 dev->tx_timeout = &tx_timeout;
541 dev->watchdog_timeo = TX_TIMEOUT;
542 dev->change_mtu = &change_mtu;
543 pci_set_drvdata(pdev, dev);
544
545 i = register_netdev(dev);
546 if (i)
547 goto err_out_unmap_rx;
548
549 printk(KERN_INFO "%s: %s at %p, %s, IRQ %d.\n",
550 dev->name, pci_id_tbl[chip_idx].name, ioaddr,
551 print_mac(mac, dev->dev_addr), irq);
552
553 np->phys[0] = 1; /* Default setting */
554 np->mii_preamble_required++;
555 /*
556 * It seems some phys doesn't deal well with address 0 being accessed
557 * first, so leave address zero to the end of the loop (32 & 31).
558 */
559 for (phy = 1; phy <= 32 && phy_idx < MII_CNT; phy++) {
560 int phyx = phy & 0x1f;
561 int mii_status = mdio_read(dev, phyx, MII_BMSR);
562 if (mii_status != 0xffff && mii_status != 0x0000) {
563 np->phys[phy_idx++] = phyx;
564 np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE);
565 if ((mii_status & 0x0040) == 0)
566 np->mii_preamble_required++;
567 printk(KERN_INFO "%s: MII PHY found at address %d, status "
568 "0x%4.4x advertising %4.4x.\n",
569 dev->name, phyx, mii_status, np->mii_if.advertising);
570 }
571 }
572 np->mii_preamble_required--;
573
574 if (phy_idx == 0) {
575 printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n",
576 dev->name, ioread32(ioaddr + ASICCtrl));
577 goto err_out_unregister;
578 }
579
580 np->mii_if.phy_id = np->phys[0];
581
582 /* Parse override configuration */
583 np->an_enable = 1;
584 if (card_idx < MAX_UNITS) {
585 if (media[card_idx] != NULL) {
586 np->an_enable = 0;
587 if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
588 strcmp (media[card_idx], "4") == 0) {
589 np->speed = 100;
590 np->mii_if.full_duplex = 1;
591 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
592 || strcmp (media[card_idx], "3") == 0) {
593 np->speed = 100;
594 np->mii_if.full_duplex = 0;
595 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
596 strcmp (media[card_idx], "2") == 0) {
597 np->speed = 10;
598 np->mii_if.full_duplex = 1;
599 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
600 strcmp (media[card_idx], "1") == 0) {
601 np->speed = 10;
602 np->mii_if.full_duplex = 0;
603 } else {
604 np->an_enable = 1;
605 }
606 }
607 if (flowctrl == 1)
608 np->flowctrl = 1;
609 }
610
611 /* Fibre PHY? */
612 if (ioread32 (ioaddr + ASICCtrl) & 0x80) {
613 /* Default 100Mbps Full */
614 if (np->an_enable) {
615 np->speed = 100;
616 np->mii_if.full_duplex = 1;
617 np->an_enable = 0;
618 }
619 }
620 /* Reset PHY */
621 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
622 mdelay (300);
623 /* If flow control enabled, we need to advertise it.*/
624 if (np->flowctrl)
625 mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400);
626 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
627 /* Force media type */
628 if (!np->an_enable) {
629 mii_ctl = 0;
630 mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0;
631 mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
632 mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
633 printk (KERN_INFO "Override speed=%d, %s duplex\n",
634 np->speed, np->mii_if.full_duplex ? "Full" : "Half");
635
636 }
637
638 /* Perhaps move the reset here? */
639 /* Reset the chip to erase previous misconfiguration. */
640 if (netif_msg_hw(np))
641 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
642 sundance_reset(dev, 0x00ff << 16);
643 if (netif_msg_hw(np))
644 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
645
646 card_idx++;
647 return 0;
648
649 err_out_unregister:
650 unregister_netdev(dev);
651 err_out_unmap_rx:
652 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
653 err_out_unmap_tx:
654 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
655 err_out_cleardev:
656 pci_set_drvdata(pdev, NULL);
657 pci_iounmap(pdev, ioaddr);
658 err_out_res:
659 pci_release_regions(pdev);
660 err_out_netdev:
661 free_netdev (dev);
662 return -ENODEV;
663 }
664
665 static int change_mtu(struct net_device *dev, int new_mtu)
666 {
667 if ((new_mtu < 68) || (new_mtu > 8191)) /* Set by RxDMAFrameLen */
668 return -EINVAL;
669 if (netif_running(dev))
670 return -EBUSY;
671 dev->mtu = new_mtu;
672 return 0;
673 }
674
675 #define eeprom_delay(ee_addr) ioread32(ee_addr)
676 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
677 static int __devinit eeprom_read(void __iomem *ioaddr, int location)
678 {
679 int boguscnt = 10000; /* Typical 1900 ticks. */
680 iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl);
681 do {
682 eeprom_delay(ioaddr + EECtrl);
683 if (! (ioread16(ioaddr + EECtrl) & 0x8000)) {
684 return ioread16(ioaddr + EEData);
685 }
686 } while (--boguscnt > 0);
687 return 0;
688 }
689
690 /* MII transceiver control section.
691 Read and write the MII registers using software-generated serial
692 MDIO protocol. See the MII specifications or DP83840A data sheet
693 for details.
694
695 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
696 met by back-to-back 33Mhz PCI cycles. */
697 #define mdio_delay() ioread8(mdio_addr)
698
699 enum mii_reg_bits {
700 MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
701 };
702 #define MDIO_EnbIn (0)
703 #define MDIO_WRITE0 (MDIO_EnbOutput)
704 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
705
706 /* Generate the preamble required for initial synchronization and
707 a few older transceivers. */
708 static void mdio_sync(void __iomem *mdio_addr)
709 {
710 int bits = 32;
711
712 /* Establish sync by sending at least 32 logic ones. */
713 while (--bits >= 0) {
714 iowrite8(MDIO_WRITE1, mdio_addr);
715 mdio_delay();
716 iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
717 mdio_delay();
718 }
719 }
720
721 static int mdio_read(struct net_device *dev, int phy_id, int location)
722 {
723 struct netdev_private *np = netdev_priv(dev);
724 void __iomem *mdio_addr = np->base + MIICtrl;
725 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
726 int i, retval = 0;
727
728 if (np->mii_preamble_required)
729 mdio_sync(mdio_addr);
730
731 /* Shift the read command bits out. */
732 for (i = 15; i >= 0; i--) {
733 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
734
735 iowrite8(dataval, mdio_addr);
736 mdio_delay();
737 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
738 mdio_delay();
739 }
740 /* Read the two transition, 16 data, and wire-idle bits. */
741 for (i = 19; i > 0; i--) {
742 iowrite8(MDIO_EnbIn, mdio_addr);
743 mdio_delay();
744 retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0);
745 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
746 mdio_delay();
747 }
748 return (retval>>1) & 0xffff;
749 }
750
751 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
752 {
753 struct netdev_private *np = netdev_priv(dev);
754 void __iomem *mdio_addr = np->base + MIICtrl;
755 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
756 int i;
757
758 if (np->mii_preamble_required)
759 mdio_sync(mdio_addr);
760
761 /* Shift the command bits out. */
762 for (i = 31; i >= 0; i--) {
763 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
764
765 iowrite8(dataval, mdio_addr);
766 mdio_delay();
767 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
768 mdio_delay();
769 }
770 /* Clear out extra bits. */
771 for (i = 2; i > 0; i--) {
772 iowrite8(MDIO_EnbIn, mdio_addr);
773 mdio_delay();
774 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
775 mdio_delay();
776 }
777 return;
778 }
779
780 static int netdev_open(struct net_device *dev)
781 {
782 struct netdev_private *np = netdev_priv(dev);
783 void __iomem *ioaddr = np->base;
784 unsigned long flags;
785 int i;
786
787 /* Do we need to reset the chip??? */
788
789 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
790 if (i)
791 return i;
792
793 if (netif_msg_ifup(np))
794 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
795 dev->name, dev->irq);
796 init_ring(dev);
797
798 iowrite32(np->rx_ring_dma, ioaddr + RxListPtr);
799 /* The Tx list pointer is written as packets are queued. */
800
801 /* Initialize other registers. */
802 __set_mac_addr(dev);
803 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
804 iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize);
805 #else
806 iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize);
807 #endif
808 if (dev->mtu > 2047)
809 iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl);
810
811 /* Configure the PCI bus bursts and FIFO thresholds. */
812
813 if (dev->if_port == 0)
814 dev->if_port = np->default_port;
815
816 spin_lock_init(&np->mcastlock);
817
818 set_rx_mode(dev);
819 iowrite16(0, ioaddr + IntrEnable);
820 iowrite16(0, ioaddr + DownCounter);
821 /* Set the chip to poll every N*320nsec. */
822 iowrite8(100, ioaddr + RxDMAPollPeriod);
823 iowrite8(127, ioaddr + TxDMAPollPeriod);
824 /* Fix DFE-580TX packet drop issue */
825 if (np->pci_dev->revision >= 0x14)
826 iowrite8(0x01, ioaddr + DebugCtrl1);
827 netif_start_queue(dev);
828
829 spin_lock_irqsave(&np->lock, flags);
830 reset_tx(dev);
831 spin_unlock_irqrestore(&np->lock, flags);
832
833 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
834
835 if (netif_msg_ifup(np))
836 printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
837 "MAC Control %x, %4.4x %4.4x.\n",
838 dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus),
839 ioread32(ioaddr + MACCtrl0),
840 ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0));
841
842 /* Set the timer to check for link beat. */
843 init_timer(&np->timer);
844 np->timer.expires = jiffies + 3*HZ;
845 np->timer.data = (unsigned long)dev;
846 np->timer.function = &netdev_timer; /* timer handler */
847 add_timer(&np->timer);
848
849 /* Enable interrupts by setting the interrupt mask. */
850 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
851
852 return 0;
853 }
854
855 static void check_duplex(struct net_device *dev)
856 {
857 struct netdev_private *np = netdev_priv(dev);
858 void __iomem *ioaddr = np->base;
859 int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
860 int negotiated = mii_lpa & np->mii_if.advertising;
861 int duplex;
862
863 /* Force media */
864 if (!np->an_enable || mii_lpa == 0xffff) {
865 if (np->mii_if.full_duplex)
866 iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex,
867 ioaddr + MACCtrl0);
868 return;
869 }
870
871 /* Autonegotiation */
872 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
873 if (np->mii_if.full_duplex != duplex) {
874 np->mii_if.full_duplex = duplex;
875 if (netif_msg_link(np))
876 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
877 "negotiated capability %4.4x.\n", dev->name,
878 duplex ? "full" : "half", np->phys[0], negotiated);
879 iowrite16(ioread16(ioaddr + MACCtrl0) | duplex ? 0x20 : 0, ioaddr + MACCtrl0);
880 }
881 }
882
883 static void netdev_timer(unsigned long data)
884 {
885 struct net_device *dev = (struct net_device *)data;
886 struct netdev_private *np = netdev_priv(dev);
887 void __iomem *ioaddr = np->base;
888 int next_tick = 10*HZ;
889
890 if (netif_msg_timer(np)) {
891 printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
892 "Tx %x Rx %x.\n",
893 dev->name, ioread16(ioaddr + IntrEnable),
894 ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
895 }
896 check_duplex(dev);
897 np->timer.expires = jiffies + next_tick;
898 add_timer(&np->timer);
899 }
900
901 static void tx_timeout(struct net_device *dev)
902 {
903 struct netdev_private *np = netdev_priv(dev);
904 void __iomem *ioaddr = np->base;
905 unsigned long flag;
906
907 netif_stop_queue(dev);
908 tasklet_disable(&np->tx_tasklet);
909 iowrite16(0, ioaddr + IntrEnable);
910 printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x "
911 "TxFrameId %2.2x,"
912 " resetting...\n", dev->name, ioread8(ioaddr + TxStatus),
913 ioread8(ioaddr + TxFrameId));
914
915 {
916 int i;
917 for (i=0; i<TX_RING_SIZE; i++) {
918 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
919 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
920 le32_to_cpu(np->tx_ring[i].next_desc),
921 le32_to_cpu(np->tx_ring[i].status),
922 (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff,
923 le32_to_cpu(np->tx_ring[i].frag[0].addr),
924 le32_to_cpu(np->tx_ring[i].frag[0].length));
925 }
926 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
927 ioread32(np->base + TxListPtr),
928 netif_queue_stopped(dev));
929 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
930 np->cur_tx, np->cur_tx % TX_RING_SIZE,
931 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
932 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
933 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
934 }
935 spin_lock_irqsave(&np->lock, flag);
936
937 /* Stop and restart the chip's Tx processes . */
938 reset_tx(dev);
939 spin_unlock_irqrestore(&np->lock, flag);
940
941 dev->if_port = 0;
942
943 dev->trans_start = jiffies;
944 np->stats.tx_errors++;
945 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
946 netif_wake_queue(dev);
947 }
948 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
949 tasklet_enable(&np->tx_tasklet);
950 }
951
952
953 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
954 static void init_ring(struct net_device *dev)
955 {
956 struct netdev_private *np = netdev_priv(dev);
957 int i;
958
959 np->cur_rx = np->cur_tx = 0;
960 np->dirty_rx = np->dirty_tx = 0;
961 np->cur_task = 0;
962
963 np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16);
964
965 /* Initialize all Rx descriptors. */
966 for (i = 0; i < RX_RING_SIZE; i++) {
967 np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma +
968 ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring));
969 np->rx_ring[i].status = 0;
970 np->rx_ring[i].frag[0].length = 0;
971 np->rx_skbuff[i] = NULL;
972 }
973
974 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
975 for (i = 0; i < RX_RING_SIZE; i++) {
976 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
977 np->rx_skbuff[i] = skb;
978 if (skb == NULL)
979 break;
980 skb->dev = dev; /* Mark as being used by this device. */
981 skb_reserve(skb, 2); /* 16 byte align the IP header. */
982 np->rx_ring[i].frag[0].addr = cpu_to_le32(
983 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz,
984 PCI_DMA_FROMDEVICE));
985 np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
986 }
987 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
988
989 for (i = 0; i < TX_RING_SIZE; i++) {
990 np->tx_skbuff[i] = NULL;
991 np->tx_ring[i].status = 0;
992 }
993 return;
994 }
995
996 static void tx_poll (unsigned long data)
997 {
998 struct net_device *dev = (struct net_device *)data;
999 struct netdev_private *np = netdev_priv(dev);
1000 unsigned head = np->cur_task % TX_RING_SIZE;
1001 struct netdev_desc *txdesc =
1002 &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE];
1003
1004 /* Chain the next pointer */
1005 for (; np->cur_tx - np->cur_task > 0; np->cur_task++) {
1006 int entry = np->cur_task % TX_RING_SIZE;
1007 txdesc = &np->tx_ring[entry];
1008 if (np->last_tx) {
1009 np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma +
1010 entry*sizeof(struct netdev_desc));
1011 }
1012 np->last_tx = txdesc;
1013 }
1014 /* Indicate the latest descriptor of tx ring */
1015 txdesc->status |= cpu_to_le32(DescIntrOnTx);
1016
1017 if (ioread32 (np->base + TxListPtr) == 0)
1018 iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc),
1019 np->base + TxListPtr);
1020 return;
1021 }
1022
1023 static int
1024 start_tx (struct sk_buff *skb, struct net_device *dev)
1025 {
1026 struct netdev_private *np = netdev_priv(dev);
1027 struct netdev_desc *txdesc;
1028 unsigned entry;
1029
1030 /* Calculate the next Tx descriptor entry. */
1031 entry = np->cur_tx % TX_RING_SIZE;
1032 np->tx_skbuff[entry] = skb;
1033 txdesc = &np->tx_ring[entry];
1034
1035 txdesc->next_desc = 0;
1036 txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign);
1037 txdesc->frag[0].addr = cpu_to_le32 (pci_map_single (np->pci_dev, skb->data,
1038 skb->len,
1039 PCI_DMA_TODEVICE));
1040 txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag);
1041
1042 /* Increment cur_tx before tasklet_schedule() */
1043 np->cur_tx++;
1044 mb();
1045 /* Schedule a tx_poll() task */
1046 tasklet_schedule(&np->tx_tasklet);
1047
1048 /* On some architectures: explicitly flush cache lines here. */
1049 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1
1050 && !netif_queue_stopped(dev)) {
1051 /* do nothing */
1052 } else {
1053 netif_stop_queue (dev);
1054 }
1055 dev->trans_start = jiffies;
1056 if (netif_msg_tx_queued(np)) {
1057 printk (KERN_DEBUG
1058 "%s: Transmit frame #%d queued in slot %d.\n",
1059 dev->name, np->cur_tx, entry);
1060 }
1061 return 0;
1062 }
1063
1064 /* Reset hardware tx and free all of tx buffers */
1065 static int
1066 reset_tx (struct net_device *dev)
1067 {
1068 struct netdev_private *np = netdev_priv(dev);
1069 void __iomem *ioaddr = np->base;
1070 struct sk_buff *skb;
1071 int i;
1072 int irq = in_interrupt();
1073
1074 /* Reset tx logic, TxListPtr will be cleaned */
1075 iowrite16 (TxDisable, ioaddr + MACCtrl1);
1076 sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
1077
1078 /* free all tx skbuff */
1079 for (i = 0; i < TX_RING_SIZE; i++) {
1080 np->tx_ring[i].next_desc = 0;
1081
1082 skb = np->tx_skbuff[i];
1083 if (skb) {
1084 pci_unmap_single(np->pci_dev,
1085 np->tx_ring[i].frag[0].addr, skb->len,
1086 PCI_DMA_TODEVICE);
1087 if (irq)
1088 dev_kfree_skb_irq (skb);
1089 else
1090 dev_kfree_skb (skb);
1091 np->tx_skbuff[i] = NULL;
1092 np->stats.tx_dropped++;
1093 }
1094 }
1095 np->cur_tx = np->dirty_tx = 0;
1096 np->cur_task = 0;
1097
1098 np->last_tx = NULL;
1099 iowrite8(127, ioaddr + TxDMAPollPeriod);
1100
1101 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
1102 return 0;
1103 }
1104
1105 /* The interrupt handler cleans up after the Tx thread,
1106 and schedule a Rx thread work */
1107 static irqreturn_t intr_handler(int irq, void *dev_instance)
1108 {
1109 struct net_device *dev = (struct net_device *)dev_instance;
1110 struct netdev_private *np = netdev_priv(dev);
1111 void __iomem *ioaddr = np->base;
1112 int hw_frame_id;
1113 int tx_cnt;
1114 int tx_status;
1115 int handled = 0;
1116 int i;
1117
1118
1119 do {
1120 int intr_status = ioread16(ioaddr + IntrStatus);
1121 iowrite16(intr_status, ioaddr + IntrStatus);
1122
1123 if (netif_msg_intr(np))
1124 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1125 dev->name, intr_status);
1126
1127 if (!(intr_status & DEFAULT_INTR))
1128 break;
1129
1130 handled = 1;
1131
1132 if (intr_status & (IntrRxDMADone)) {
1133 iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
1134 ioaddr + IntrEnable);
1135 if (np->budget < 0)
1136 np->budget = RX_BUDGET;
1137 tasklet_schedule(&np->rx_tasklet);
1138 }
1139 if (intr_status & (IntrTxDone | IntrDrvRqst)) {
1140 tx_status = ioread16 (ioaddr + TxStatus);
1141 for (tx_cnt=32; tx_status & 0x80; --tx_cnt) {
1142 if (netif_msg_tx_done(np))
1143 printk
1144 ("%s: Transmit status is %2.2x.\n",
1145 dev->name, tx_status);
1146 if (tx_status & 0x1e) {
1147 if (netif_msg_tx_err(np))
1148 printk("%s: Transmit error status %4.4x.\n",
1149 dev->name, tx_status);
1150 np->stats.tx_errors++;
1151 if (tx_status & 0x10)
1152 np->stats.tx_fifo_errors++;
1153 if (tx_status & 0x08)
1154 np->stats.collisions++;
1155 if (tx_status & 0x04)
1156 np->stats.tx_fifo_errors++;
1157 if (tx_status & 0x02)
1158 np->stats.tx_window_errors++;
1159
1160 /*
1161 ** This reset has been verified on
1162 ** DFE-580TX boards ! phdm@macqel.be.
1163 */
1164 if (tx_status & 0x10) { /* TxUnderrun */
1165 /* Restart Tx FIFO and transmitter */
1166 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
1167 /* No need to reset the Tx pointer here */
1168 }
1169 /* Restart the Tx. Need to make sure tx enabled */
1170 i = 10;
1171 do {
1172 iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
1173 if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
1174 break;
1175 mdelay(1);
1176 } while (--i);
1177 }
1178 /* Yup, this is a documentation bug. It cost me *hours*. */
1179 iowrite16 (0, ioaddr + TxStatus);
1180 if (tx_cnt < 0) {
1181 iowrite32(5000, ioaddr + DownCounter);
1182 break;
1183 }
1184 tx_status = ioread16 (ioaddr + TxStatus);
1185 }
1186 hw_frame_id = (tx_status >> 8) & 0xff;
1187 } else {
1188 hw_frame_id = ioread8(ioaddr + TxFrameId);
1189 }
1190
1191 if (np->pci_dev->revision >= 0x14) {
1192 spin_lock(&np->lock);
1193 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1194 int entry = np->dirty_tx % TX_RING_SIZE;
1195 struct sk_buff *skb;
1196 int sw_frame_id;
1197 sw_frame_id = (le32_to_cpu(
1198 np->tx_ring[entry].status) >> 2) & 0xff;
1199 if (sw_frame_id == hw_frame_id &&
1200 !(le32_to_cpu(np->tx_ring[entry].status)
1201 & 0x00010000))
1202 break;
1203 if (sw_frame_id == (hw_frame_id + 1) %
1204 TX_RING_SIZE)
1205 break;
1206 skb = np->tx_skbuff[entry];
1207 /* Free the original skb. */
1208 pci_unmap_single(np->pci_dev,
1209 np->tx_ring[entry].frag[0].addr,
1210 skb->len, PCI_DMA_TODEVICE);
1211 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1212 np->tx_skbuff[entry] = NULL;
1213 np->tx_ring[entry].frag[0].addr = 0;
1214 np->tx_ring[entry].frag[0].length = 0;
1215 }
1216 spin_unlock(&np->lock);
1217 } else {
1218 spin_lock(&np->lock);
1219 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1220 int entry = np->dirty_tx % TX_RING_SIZE;
1221 struct sk_buff *skb;
1222 if (!(le32_to_cpu(np->tx_ring[entry].status)
1223 & 0x00010000))
1224 break;
1225 skb = np->tx_skbuff[entry];
1226 /* Free the original skb. */
1227 pci_unmap_single(np->pci_dev,
1228 np->tx_ring[entry].frag[0].addr,
1229 skb->len, PCI_DMA_TODEVICE);
1230 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1231 np->tx_skbuff[entry] = NULL;
1232 np->tx_ring[entry].frag[0].addr = 0;
1233 np->tx_ring[entry].frag[0].length = 0;
1234 }
1235 spin_unlock(&np->lock);
1236 }
1237
1238 if (netif_queue_stopped(dev) &&
1239 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1240 /* The ring is no longer full, clear busy flag. */
1241 netif_wake_queue (dev);
1242 }
1243 /* Abnormal error summary/uncommon events handlers. */
1244 if (intr_status & (IntrPCIErr | LinkChange | StatsMax))
1245 netdev_error(dev, intr_status);
1246 } while (0);
1247 if (netif_msg_intr(np))
1248 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1249 dev->name, ioread16(ioaddr + IntrStatus));
1250 return IRQ_RETVAL(handled);
1251 }
1252
1253 static void rx_poll(unsigned long data)
1254 {
1255 struct net_device *dev = (struct net_device *)data;
1256 struct netdev_private *np = netdev_priv(dev);
1257 int entry = np->cur_rx % RX_RING_SIZE;
1258 int boguscnt = np->budget;
1259 void __iomem *ioaddr = np->base;
1260 int received = 0;
1261
1262 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1263 while (1) {
1264 struct netdev_desc *desc = &(np->rx_ring[entry]);
1265 u32 frame_status = le32_to_cpu(desc->status);
1266 int pkt_len;
1267
1268 if (--boguscnt < 0) {
1269 goto not_done;
1270 }
1271 if (!(frame_status & DescOwn))
1272 break;
1273 pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
1274 if (netif_msg_rx_status(np))
1275 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1276 frame_status);
1277 if (frame_status & 0x001f4000) {
1278 /* There was a error. */
1279 if (netif_msg_rx_err(np))
1280 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
1281 frame_status);
1282 np->stats.rx_errors++;
1283 if (frame_status & 0x00100000) np->stats.rx_length_errors++;
1284 if (frame_status & 0x00010000) np->stats.rx_fifo_errors++;
1285 if (frame_status & 0x00060000) np->stats.rx_frame_errors++;
1286 if (frame_status & 0x00080000) np->stats.rx_crc_errors++;
1287 if (frame_status & 0x00100000) {
1288 printk(KERN_WARNING "%s: Oversized Ethernet frame,"
1289 " status %8.8x.\n",
1290 dev->name, frame_status);
1291 }
1292 } else {
1293 struct sk_buff *skb;
1294 #ifndef final_version
1295 if (netif_msg_rx_status(np))
1296 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1297 ", bogus_cnt %d.\n",
1298 pkt_len, boguscnt);
1299 #endif
1300 /* Check if the packet is long enough to accept without copying
1301 to a minimally-sized skbuff. */
1302 if (pkt_len < rx_copybreak
1303 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1304 skb_reserve(skb, 2); /* 16 byte align the IP header */
1305 pci_dma_sync_single_for_cpu(np->pci_dev,
1306 desc->frag[0].addr,
1307 np->rx_buf_sz,
1308 PCI_DMA_FROMDEVICE);
1309
1310 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1311 pci_dma_sync_single_for_device(np->pci_dev,
1312 desc->frag[0].addr,
1313 np->rx_buf_sz,
1314 PCI_DMA_FROMDEVICE);
1315 skb_put(skb, pkt_len);
1316 } else {
1317 pci_unmap_single(np->pci_dev,
1318 desc->frag[0].addr,
1319 np->rx_buf_sz,
1320 PCI_DMA_FROMDEVICE);
1321 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1322 np->rx_skbuff[entry] = NULL;
1323 }
1324 skb->protocol = eth_type_trans(skb, dev);
1325 /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
1326 netif_rx(skb);
1327 dev->last_rx = jiffies;
1328 }
1329 entry = (entry + 1) % RX_RING_SIZE;
1330 received++;
1331 }
1332 np->cur_rx = entry;
1333 refill_rx (dev);
1334 np->budget -= received;
1335 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
1336 return;
1337
1338 not_done:
1339 np->cur_rx = entry;
1340 refill_rx (dev);
1341 if (!received)
1342 received = 1;
1343 np->budget -= received;
1344 if (np->budget <= 0)
1345 np->budget = RX_BUDGET;
1346 tasklet_schedule(&np->rx_tasklet);
1347 return;
1348 }
1349
1350 static void refill_rx (struct net_device *dev)
1351 {
1352 struct netdev_private *np = netdev_priv(dev);
1353 int entry;
1354 int cnt = 0;
1355
1356 /* Refill the Rx ring buffers. */
1357 for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0;
1358 np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) {
1359 struct sk_buff *skb;
1360 entry = np->dirty_rx % RX_RING_SIZE;
1361 if (np->rx_skbuff[entry] == NULL) {
1362 skb = dev_alloc_skb(np->rx_buf_sz);
1363 np->rx_skbuff[entry] = skb;
1364 if (skb == NULL)
1365 break; /* Better luck next round. */
1366 skb->dev = dev; /* Mark as being used by this device. */
1367 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1368 np->rx_ring[entry].frag[0].addr = cpu_to_le32(
1369 pci_map_single(np->pci_dev, skb->data,
1370 np->rx_buf_sz, PCI_DMA_FROMDEVICE));
1371 }
1372 /* Perhaps we need not reset this field. */
1373 np->rx_ring[entry].frag[0].length =
1374 cpu_to_le32(np->rx_buf_sz | LastFrag);
1375 np->rx_ring[entry].status = 0;
1376 cnt++;
1377 }
1378 return;
1379 }
1380 static void netdev_error(struct net_device *dev, int intr_status)
1381 {
1382 struct netdev_private *np = netdev_priv(dev);
1383 void __iomem *ioaddr = np->base;
1384 u16 mii_ctl, mii_advertise, mii_lpa;
1385 int speed;
1386
1387 if (intr_status & LinkChange) {
1388 if (np->an_enable) {
1389 mii_advertise = mdio_read (dev, np->phys[0], MII_ADVERTISE);
1390 mii_lpa= mdio_read (dev, np->phys[0], MII_LPA);
1391 mii_advertise &= mii_lpa;
1392 printk (KERN_INFO "%s: Link changed: ", dev->name);
1393 if (mii_advertise & ADVERTISE_100FULL) {
1394 np->speed = 100;
1395 printk ("100Mbps, full duplex\n");
1396 } else if (mii_advertise & ADVERTISE_100HALF) {
1397 np->speed = 100;
1398 printk ("100Mbps, half duplex\n");
1399 } else if (mii_advertise & ADVERTISE_10FULL) {
1400 np->speed = 10;
1401 printk ("10Mbps, full duplex\n");
1402 } else if (mii_advertise & ADVERTISE_10HALF) {
1403 np->speed = 10;
1404 printk ("10Mbps, half duplex\n");
1405 } else
1406 printk ("\n");
1407
1408 } else {
1409 mii_ctl = mdio_read (dev, np->phys[0], MII_BMCR);
1410 speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
1411 np->speed = speed;
1412 printk (KERN_INFO "%s: Link changed: %dMbps ,",
1413 dev->name, speed);
1414 printk ("%s duplex.\n", (mii_ctl & BMCR_FULLDPLX) ?
1415 "full" : "half");
1416 }
1417 check_duplex (dev);
1418 if (np->flowctrl && np->mii_if.full_duplex) {
1419 iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200,
1420 ioaddr + MulticastFilter1+2);
1421 iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl,
1422 ioaddr + MACCtrl0);
1423 }
1424 }
1425 if (intr_status & StatsMax) {
1426 get_stats(dev);
1427 }
1428 if (intr_status & IntrPCIErr) {
1429 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1430 dev->name, intr_status);
1431 /* We must do a global reset of DMA to continue. */
1432 }
1433 }
1434
1435 static struct net_device_stats *get_stats(struct net_device *dev)
1436 {
1437 struct netdev_private *np = netdev_priv(dev);
1438 void __iomem *ioaddr = np->base;
1439 int i;
1440
1441 /* We should lock this segment of code for SMP eventually, although
1442 the vulnerability window is very small and statistics are
1443 non-critical. */
1444 /* The chip only need report frame silently dropped. */
1445 np->stats.rx_missed_errors += ioread8(ioaddr + RxMissed);
1446 np->stats.tx_packets += ioread16(ioaddr + TxFramesOK);
1447 np->stats.rx_packets += ioread16(ioaddr + RxFramesOK);
1448 np->stats.collisions += ioread8(ioaddr + StatsLateColl);
1449 np->stats.collisions += ioread8(ioaddr + StatsMultiColl);
1450 np->stats.collisions += ioread8(ioaddr + StatsOneColl);
1451 np->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError);
1452 ioread8(ioaddr + StatsTxDefer);
1453 for (i = StatsTxDefer; i <= StatsMcastRx; i++)
1454 ioread8(ioaddr + i);
1455 np->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow);
1456 np->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16;
1457 np->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow);
1458 np->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16;
1459
1460 return &np->stats;
1461 }
1462
1463 static void set_rx_mode(struct net_device *dev)
1464 {
1465 struct netdev_private *np = netdev_priv(dev);
1466 void __iomem *ioaddr = np->base;
1467 u16 mc_filter[4]; /* Multicast hash filter */
1468 u32 rx_mode;
1469 int i;
1470
1471 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1472 memset(mc_filter, 0xff, sizeof(mc_filter));
1473 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
1474 } else if ((dev->mc_count > multicast_filter_limit)
1475 || (dev->flags & IFF_ALLMULTI)) {
1476 /* Too many to match, or accept all multicasts. */
1477 memset(mc_filter, 0xff, sizeof(mc_filter));
1478 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1479 } else if (dev->mc_count) {
1480 struct dev_mc_list *mclist;
1481 int bit;
1482 int index;
1483 int crc;
1484 memset (mc_filter, 0, sizeof (mc_filter));
1485 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1486 i++, mclist = mclist->next) {
1487 crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1488 for (index=0, bit=0; bit < 6; bit++, crc <<= 1)
1489 if (crc & 0x80000000) index |= 1 << bit;
1490 mc_filter[index/16] |= (1 << (index % 16));
1491 }
1492 rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
1493 } else {
1494 iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1495 return;
1496 }
1497 if (np->mii_if.full_duplex && np->flowctrl)
1498 mc_filter[3] |= 0x0200;
1499
1500 for (i = 0; i < 4; i++)
1501 iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
1502 iowrite8(rx_mode, ioaddr + RxMode);
1503 }
1504
1505 static int __set_mac_addr(struct net_device *dev)
1506 {
1507 struct netdev_private *np = netdev_priv(dev);
1508 u16 addr16;
1509
1510 addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8));
1511 iowrite16(addr16, np->base + StationAddr);
1512 addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8));
1513 iowrite16(addr16, np->base + StationAddr+2);
1514 addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8));
1515 iowrite16(addr16, np->base + StationAddr+4);
1516 return 0;
1517 }
1518
1519 static int check_if_running(struct net_device *dev)
1520 {
1521 if (!netif_running(dev))
1522 return -EINVAL;
1523 return 0;
1524 }
1525
1526 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1527 {
1528 struct netdev_private *np = netdev_priv(dev);
1529 strcpy(info->driver, DRV_NAME);
1530 strcpy(info->version, DRV_VERSION);
1531 strcpy(info->bus_info, pci_name(np->pci_dev));
1532 }
1533
1534 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1535 {
1536 struct netdev_private *np = netdev_priv(dev);
1537 spin_lock_irq(&np->lock);
1538 mii_ethtool_gset(&np->mii_if, ecmd);
1539 spin_unlock_irq(&np->lock);
1540 return 0;
1541 }
1542
1543 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1544 {
1545 struct netdev_private *np = netdev_priv(dev);
1546 int res;
1547 spin_lock_irq(&np->lock);
1548 res = mii_ethtool_sset(&np->mii_if, ecmd);
1549 spin_unlock_irq(&np->lock);
1550 return res;
1551 }
1552
1553 static int nway_reset(struct net_device *dev)
1554 {
1555 struct netdev_private *np = netdev_priv(dev);
1556 return mii_nway_restart(&np->mii_if);
1557 }
1558
1559 static u32 get_link(struct net_device *dev)
1560 {
1561 struct netdev_private *np = netdev_priv(dev);
1562 return mii_link_ok(&np->mii_if);
1563 }
1564
1565 static u32 get_msglevel(struct net_device *dev)
1566 {
1567 struct netdev_private *np = netdev_priv(dev);
1568 return np->msg_enable;
1569 }
1570
1571 static void set_msglevel(struct net_device *dev, u32 val)
1572 {
1573 struct netdev_private *np = netdev_priv(dev);
1574 np->msg_enable = val;
1575 }
1576
1577 static const struct ethtool_ops ethtool_ops = {
1578 .begin = check_if_running,
1579 .get_drvinfo = get_drvinfo,
1580 .get_settings = get_settings,
1581 .set_settings = set_settings,
1582 .nway_reset = nway_reset,
1583 .get_link = get_link,
1584 .get_msglevel = get_msglevel,
1585 .set_msglevel = set_msglevel,
1586 };
1587
1588 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1589 {
1590 struct netdev_private *np = netdev_priv(dev);
1591 void __iomem *ioaddr = np->base;
1592 int rc;
1593 int i;
1594
1595 if (!netif_running(dev))
1596 return -EINVAL;
1597
1598 spin_lock_irq(&np->lock);
1599 rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL);
1600 spin_unlock_irq(&np->lock);
1601 switch (cmd) {
1602 case SIOCDEVPRIVATE:
1603 for (i=0; i<TX_RING_SIZE; i++) {
1604 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
1605 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
1606 le32_to_cpu(np->tx_ring[i].next_desc),
1607 le32_to_cpu(np->tx_ring[i].status),
1608 (le32_to_cpu(np->tx_ring[i].status) >> 2)
1609 & 0xff,
1610 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1611 le32_to_cpu(np->tx_ring[i].frag[0].length));
1612 }
1613 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
1614 ioread32(np->base + TxListPtr),
1615 netif_queue_stopped(dev));
1616 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
1617 np->cur_tx, np->cur_tx % TX_RING_SIZE,
1618 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
1619 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
1620 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
1621 printk(KERN_DEBUG "TxStatus=%04x\n", ioread16(ioaddr + TxStatus));
1622 return 0;
1623 }
1624
1625
1626 return rc;
1627 }
1628
1629 static int netdev_close(struct net_device *dev)
1630 {
1631 struct netdev_private *np = netdev_priv(dev);
1632 void __iomem *ioaddr = np->base;
1633 struct sk_buff *skb;
1634 int i;
1635
1636 /* Wait and kill tasklet */
1637 tasklet_kill(&np->rx_tasklet);
1638 tasklet_kill(&np->tx_tasklet);
1639 np->cur_tx = 0;
1640 np->dirty_tx = 0;
1641 np->cur_task = 0;
1642 np->last_tx = NULL;
1643
1644 netif_stop_queue(dev);
1645
1646 if (netif_msg_ifdown(np)) {
1647 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
1648 "Rx %4.4x Int %2.2x.\n",
1649 dev->name, ioread8(ioaddr + TxStatus),
1650 ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus));
1651 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1652 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1653 }
1654
1655 /* Disable interrupts by clearing the interrupt mask. */
1656 iowrite16(0x0000, ioaddr + IntrEnable);
1657
1658 /* Disable Rx and Tx DMA for safely release resource */
1659 iowrite32(0x500, ioaddr + DMACtrl);
1660
1661 /* Stop the chip's Tx and Rx processes. */
1662 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1663
1664 for (i = 2000; i > 0; i--) {
1665 if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
1666 break;
1667 mdelay(1);
1668 }
1669
1670 iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
1671 ioaddr +ASICCtrl + 2);
1672
1673 for (i = 2000; i > 0; i--) {
1674 if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0)
1675 break;
1676 mdelay(1);
1677 }
1678
1679 #ifdef __i386__
1680 if (netif_msg_hw(np)) {
1681 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1682 (int)(np->tx_ring_dma));
1683 for (i = 0; i < TX_RING_SIZE; i++)
1684 printk(" #%d desc. %4.4x %8.8x %8.8x.\n",
1685 i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
1686 np->tx_ring[i].frag[0].length);
1687 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1688 (int)(np->rx_ring_dma));
1689 for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
1690 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1691 i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
1692 np->rx_ring[i].frag[0].length);
1693 }
1694 }
1695 #endif /* __i386__ debugging only */
1696
1697 free_irq(dev->irq, dev);
1698
1699 del_timer_sync(&np->timer);
1700
1701 /* Free all the skbuffs in the Rx queue. */
1702 for (i = 0; i < RX_RING_SIZE; i++) {
1703 np->rx_ring[i].status = 0;
1704 np->rx_ring[i].frag[0].addr = 0xBADF00D0; /* An invalid address. */
1705 skb = np->rx_skbuff[i];
1706 if (skb) {
1707 pci_unmap_single(np->pci_dev,
1708 np->rx_ring[i].frag[0].addr, np->rx_buf_sz,
1709 PCI_DMA_FROMDEVICE);
1710 dev_kfree_skb(skb);
1711 np->rx_skbuff[i] = NULL;
1712 }
1713 }
1714 for (i = 0; i < TX_RING_SIZE; i++) {
1715 np->tx_ring[i].next_desc = 0;
1716 skb = np->tx_skbuff[i];
1717 if (skb) {
1718 pci_unmap_single(np->pci_dev,
1719 np->tx_ring[i].frag[0].addr, skb->len,
1720 PCI_DMA_TODEVICE);
1721 dev_kfree_skb(skb);
1722 np->tx_skbuff[i] = NULL;
1723 }
1724 }
1725
1726 return 0;
1727 }
1728
1729 static void __devexit sundance_remove1 (struct pci_dev *pdev)
1730 {
1731 struct net_device *dev = pci_get_drvdata(pdev);
1732
1733 if (dev) {
1734 struct netdev_private *np = netdev_priv(dev);
1735
1736 unregister_netdev(dev);
1737 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
1738 np->rx_ring_dma);
1739 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
1740 np->tx_ring_dma);
1741 pci_iounmap(pdev, np->base);
1742 pci_release_regions(pdev);
1743 free_netdev(dev);
1744 pci_set_drvdata(pdev, NULL);
1745 }
1746 }
1747
1748 static struct pci_driver sundance_driver = {
1749 .name = DRV_NAME,
1750 .id_table = sundance_pci_tbl,
1751 .probe = sundance_probe1,
1752 .remove = __devexit_p(sundance_remove1),
1753 };
1754
1755 static int __init sundance_init(void)
1756 {
1757 /* when a module, this is printed whether or not devices are found in probe */
1758 #ifdef MODULE
1759 printk(version);
1760 #endif
1761 return pci_register_driver(&sundance_driver);
1762 }
1763
1764 static void __exit sundance_exit(void)
1765 {
1766 pci_unregister_driver(&sundance_driver);
1767 }
1768
1769 module_init(sundance_init);
1770 module_exit(sundance_exit);
1771
1772
Linux kernel - Deliverables
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