projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' into for-next
[deliverable/linux.git] / drivers / net / sungem.c
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 * TODO:
14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
19 *
20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
22 * call napi_disable() neither, thus force gem_poll() to keep a spinlock
23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/types.h>
39 #include <linux/fcntl.h>
40 #include <linux/interrupt.h>
41 #include <linux/ioport.h>
42 #include <linux/in.h>
43 #include <linux/sched.h>
44 #include <linux/string.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/errno.h>
48 #include <linux/pci.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/netdevice.h>
51 #include <linux/etherdevice.h>
52 #include <linux/skbuff.h>
53 #include <linux/mii.h>
54 #include <linux/ethtool.h>
55 #include <linux/crc32.h>
56 #include <linux/random.h>
57 #include <linux/workqueue.h>
58 #include <linux/if_vlan.h>
59 #include <linux/bitops.h>
60 #include <linux/mutex.h>
61 #include <linux/mm.h>
62 #include <linux/gfp.h>
63
64 #include <asm/system.h>
65 #include <asm/io.h>
66 #include <asm/byteorder.h>
67 #include <asm/uaccess.h>
68 #include <asm/irq.h>
69 #include <asm/prom.h>
70
71 #ifdef CONFIG_SPARC
72 #include <asm/idprom.h>
73 #endif
74
75 #ifdef CONFIG_PPC_PMAC
76 #include <asm/pci-bridge.h>
77 #include <asm/machdep.h>
78 #include <asm/pmac_feature.h>
79 #endif
80
81 #include "sungem_phy.h"
82 #include "sungem.h"
83
84 /* Stripping FCS is causing problems, disabled for now */
85 #undef STRIP_FCS
86
87 #define DEFAULT_MSG (NETIF_MSG_DRV | \
88 NETIF_MSG_PROBE | \
89 NETIF_MSG_LINK)
90
91 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
92 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
93 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
94 SUPPORTED_Pause | SUPPORTED_Autoneg)
95
96 #define DRV_NAME "sungem"
97 #define DRV_VERSION "0.98"
98 #define DRV_RELDATE "8/24/03"
99 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
100
101 static char version[] __devinitdata =
102 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
103
104 MODULE_AUTHOR(DRV_AUTHOR);
105 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
106 MODULE_LICENSE("GPL");
107
108 #define GEM_MODULE_NAME "gem"
109
110 static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl) = {
111 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
113
114 /* These models only differ from the original GEM in
115 * that their tx/rx fifos are of a different size and
116 * they only support 10/100 speeds. -DaveM
117 *
118 * Apple's GMAC does support gigabit on machines with
119 * the BCM54xx PHYs. -BenH
120 */
121 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
123 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
125 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
127 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
129 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
131 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
133 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
135 {0, }
136 };
137
138 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
139
140 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
141 {
142 u32 cmd;
143 int limit = 10000;
144
145 cmd = (1 << 30);
146 cmd |= (2 << 28);
147 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
148 cmd |= (reg << 18) & MIF_FRAME_REGAD;
149 cmd |= (MIF_FRAME_TAMSB);
150 writel(cmd, gp->regs + MIF_FRAME);
151
152 while (--limit) {
153 cmd = readl(gp->regs + MIF_FRAME);
154 if (cmd & MIF_FRAME_TALSB)
155 break;
156
157 udelay(10);
158 }
159
160 if (!limit)
161 cmd = 0xffff;
162
163 return cmd & MIF_FRAME_DATA;
164 }
165
166 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
167 {
168 struct gem *gp = netdev_priv(dev);
169 return __phy_read(gp, mii_id, reg);
170 }
171
172 static inline u16 phy_read(struct gem *gp, int reg)
173 {
174 return __phy_read(gp, gp->mii_phy_addr, reg);
175 }
176
177 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
178 {
179 u32 cmd;
180 int limit = 10000;
181
182 cmd = (1 << 30);
183 cmd |= (1 << 28);
184 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
185 cmd |= (reg << 18) & MIF_FRAME_REGAD;
186 cmd |= (MIF_FRAME_TAMSB);
187 cmd |= (val & MIF_FRAME_DATA);
188 writel(cmd, gp->regs + MIF_FRAME);
189
190 while (limit--) {
191 cmd = readl(gp->regs + MIF_FRAME);
192 if (cmd & MIF_FRAME_TALSB)
193 break;
194
195 udelay(10);
196 }
197 }
198
199 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
200 {
201 struct gem *gp = netdev_priv(dev);
202 __phy_write(gp, mii_id, reg, val & 0xffff);
203 }
204
205 static inline void phy_write(struct gem *gp, int reg, u16 val)
206 {
207 __phy_write(gp, gp->mii_phy_addr, reg, val);
208 }
209
210 static inline void gem_enable_ints(struct gem *gp)
211 {
212 /* Enable all interrupts but TXDONE */
213 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
214 }
215
216 static inline void gem_disable_ints(struct gem *gp)
217 {
218 /* Disable all interrupts, including TXDONE */
219 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
220 }
221
222 static void gem_get_cell(struct gem *gp)
223 {
224 BUG_ON(gp->cell_enabled < 0);
225 gp->cell_enabled++;
226 #ifdef CONFIG_PPC_PMAC
227 if (gp->cell_enabled == 1) {
228 mb();
229 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
230 udelay(10);
231 }
232 #endif /* CONFIG_PPC_PMAC */
233 }
234
235 /* Turn off the chip's clock */
236 static void gem_put_cell(struct gem *gp)
237 {
238 BUG_ON(gp->cell_enabled <= 0);
239 gp->cell_enabled--;
240 #ifdef CONFIG_PPC_PMAC
241 if (gp->cell_enabled == 0) {
242 mb();
243 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
244 udelay(10);
245 }
246 #endif /* CONFIG_PPC_PMAC */
247 }
248
249 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
250 {
251 if (netif_msg_intr(gp))
252 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
253 }
254
255 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
256 {
257 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
258 u32 pcs_miistat;
259
260 if (netif_msg_intr(gp))
261 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
262 gp->dev->name, pcs_istat);
263
264 if (!(pcs_istat & PCS_ISTAT_LSC)) {
265 netdev_err(dev, "PCS irq but no link status change???\n");
266 return 0;
267 }
268
269 /* The link status bit latches on zero, so you must
270 * read it twice in such a case to see a transition
271 * to the link being up.
272 */
273 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
274 if (!(pcs_miistat & PCS_MIISTAT_LS))
275 pcs_miistat |=
276 (readl(gp->regs + PCS_MIISTAT) &
277 PCS_MIISTAT_LS);
278
279 if (pcs_miistat & PCS_MIISTAT_ANC) {
280 /* The remote-fault indication is only valid
281 * when autoneg has completed.
282 */
283 if (pcs_miistat & PCS_MIISTAT_RF)
284 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
285 else
286 netdev_info(dev, "PCS AutoNEG complete\n");
287 }
288
289 if (pcs_miistat & PCS_MIISTAT_LS) {
290 netdev_info(dev, "PCS link is now up\n");
291 netif_carrier_on(gp->dev);
292 } else {
293 netdev_info(dev, "PCS link is now down\n");
294 netif_carrier_off(gp->dev);
295 /* If this happens and the link timer is not running,
296 * reset so we re-negotiate.
297 */
298 if (!timer_pending(&gp->link_timer))
299 return 1;
300 }
301
302 return 0;
303 }
304
305 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
306 {
307 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
308
309 if (netif_msg_intr(gp))
310 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
311 gp->dev->name, txmac_stat);
312
313 /* Defer timer expiration is quite normal,
314 * don't even log the event.
315 */
316 if ((txmac_stat & MAC_TXSTAT_DTE) &&
317 !(txmac_stat & ~MAC_TXSTAT_DTE))
318 return 0;
319
320 if (txmac_stat & MAC_TXSTAT_URUN) {
321 netdev_err(dev, "TX MAC xmit underrun\n");
322 dev->stats.tx_fifo_errors++;
323 }
324
325 if (txmac_stat & MAC_TXSTAT_MPE) {
326 netdev_err(dev, "TX MAC max packet size error\n");
327 dev->stats.tx_errors++;
328 }
329
330 /* The rest are all cases of one of the 16-bit TX
331 * counters expiring.
332 */
333 if (txmac_stat & MAC_TXSTAT_NCE)
334 dev->stats.collisions += 0x10000;
335
336 if (txmac_stat & MAC_TXSTAT_ECE) {
337 dev->stats.tx_aborted_errors += 0x10000;
338 dev->stats.collisions += 0x10000;
339 }
340
341 if (txmac_stat & MAC_TXSTAT_LCE) {
342 dev->stats.tx_aborted_errors += 0x10000;
343 dev->stats.collisions += 0x10000;
344 }
345
346 /* We do not keep track of MAC_TXSTAT_FCE and
347 * MAC_TXSTAT_PCE events.
348 */
349 return 0;
350 }
351
352 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
353 * so we do the following.
354 *
355 * If any part of the reset goes wrong, we return 1 and that causes the
356 * whole chip to be reset.
357 */
358 static int gem_rxmac_reset(struct gem *gp)
359 {
360 struct net_device *dev = gp->dev;
361 int limit, i;
362 u64 desc_dma;
363 u32 val;
364
365 /* First, reset & disable MAC RX. */
366 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
367 for (limit = 0; limit < 5000; limit++) {
368 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
369 break;
370 udelay(10);
371 }
372 if (limit == 5000) {
373 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
374 return 1;
375 }
376
377 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
378 gp->regs + MAC_RXCFG);
379 for (limit = 0; limit < 5000; limit++) {
380 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
381 break;
382 udelay(10);
383 }
384 if (limit == 5000) {
385 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
386 return 1;
387 }
388
389 /* Second, disable RX DMA. */
390 writel(0, gp->regs + RXDMA_CFG);
391 for (limit = 0; limit < 5000; limit++) {
392 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
393 break;
394 udelay(10);
395 }
396 if (limit == 5000) {
397 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
398 return 1;
399 }
400
401 udelay(5000);
402
403 /* Execute RX reset command. */
404 writel(gp->swrst_base | GREG_SWRST_RXRST,
405 gp->regs + GREG_SWRST);
406 for (limit = 0; limit < 5000; limit++) {
407 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
408 break;
409 udelay(10);
410 }
411 if (limit == 5000) {
412 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
413 return 1;
414 }
415
416 /* Refresh the RX ring. */
417 for (i = 0; i < RX_RING_SIZE; i++) {
418 struct gem_rxd *rxd = &gp->init_block->rxd[i];
419
420 if (gp->rx_skbs[i] == NULL) {
421 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
422 return 1;
423 }
424
425 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
426 }
427 gp->rx_new = gp->rx_old = 0;
428
429 /* Now we must reprogram the rest of RX unit. */
430 desc_dma = (u64) gp->gblock_dvma;
431 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
432 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
433 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
434 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
435 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
436 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
437 writel(val, gp->regs + RXDMA_CFG);
438 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
439 writel(((5 & RXDMA_BLANK_IPKTS) |
440 ((8 << 12) & RXDMA_BLANK_ITIME)),
441 gp->regs + RXDMA_BLANK);
442 else
443 writel(((5 & RXDMA_BLANK_IPKTS) |
444 ((4 << 12) & RXDMA_BLANK_ITIME)),
445 gp->regs + RXDMA_BLANK);
446 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
447 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
448 writel(val, gp->regs + RXDMA_PTHRESH);
449 val = readl(gp->regs + RXDMA_CFG);
450 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
451 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
452 val = readl(gp->regs + MAC_RXCFG);
453 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
454
455 return 0;
456 }
457
458 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
459 {
460 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
461 int ret = 0;
462
463 if (netif_msg_intr(gp))
464 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
465 gp->dev->name, rxmac_stat);
466
467 if (rxmac_stat & MAC_RXSTAT_OFLW) {
468 u32 smac = readl(gp->regs + MAC_SMACHINE);
469
470 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
471 dev->stats.rx_over_errors++;
472 dev->stats.rx_fifo_errors++;
473
474 ret = gem_rxmac_reset(gp);
475 }
476
477 if (rxmac_stat & MAC_RXSTAT_ACE)
478 dev->stats.rx_frame_errors += 0x10000;
479
480 if (rxmac_stat & MAC_RXSTAT_CCE)
481 dev->stats.rx_crc_errors += 0x10000;
482
483 if (rxmac_stat & MAC_RXSTAT_LCE)
484 dev->stats.rx_length_errors += 0x10000;
485
486 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
487 * events.
488 */
489 return ret;
490 }
491
492 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
493 {
494 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
495
496 if (netif_msg_intr(gp))
497 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
498 gp->dev->name, mac_cstat);
499
500 /* This interrupt is just for pause frame and pause
501 * tracking. It is useful for diagnostics and debug
502 * but probably by default we will mask these events.
503 */
504 if (mac_cstat & MAC_CSTAT_PS)
505 gp->pause_entered++;
506
507 if (mac_cstat & MAC_CSTAT_PRCV)
508 gp->pause_last_time_recvd = (mac_cstat >> 16);
509
510 return 0;
511 }
512
513 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
514 {
515 u32 mif_status = readl(gp->regs + MIF_STATUS);
516 u32 reg_val, changed_bits;
517
518 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
519 changed_bits = (mif_status & MIF_STATUS_STAT);
520
521 gem_handle_mif_event(gp, reg_val, changed_bits);
522
523 return 0;
524 }
525
526 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
527 {
528 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
529
530 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
531 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
532 netdev_err(dev, "PCI error [%04x]", pci_estat);
533
534 if (pci_estat & GREG_PCIESTAT_BADACK)
535 pr_cont(" <No ACK64# during ABS64 cycle>");
536 if (pci_estat & GREG_PCIESTAT_DTRTO)
537 pr_cont(" <Delayed transaction timeout>");
538 if (pci_estat & GREG_PCIESTAT_OTHER)
539 pr_cont(" <other>");
540 pr_cont("\n");
541 } else {
542 pci_estat |= GREG_PCIESTAT_OTHER;
543 netdev_err(dev, "PCI error\n");
544 }
545
546 if (pci_estat & GREG_PCIESTAT_OTHER) {
547 u16 pci_cfg_stat;
548
549 /* Interrogate PCI config space for the
550 * true cause.
551 */
552 pci_read_config_word(gp->pdev, PCI_STATUS,
553 &pci_cfg_stat);
554 netdev_err(dev, "Read PCI cfg space status [%04x]\n",
555 pci_cfg_stat);
556 if (pci_cfg_stat & PCI_STATUS_PARITY)
557 netdev_err(dev, "PCI parity error detected\n");
558 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
559 netdev_err(dev, "PCI target abort\n");
560 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
561 netdev_err(dev, "PCI master acks target abort\n");
562 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
563 netdev_err(dev, "PCI master abort\n");
564 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
565 netdev_err(dev, "PCI system error SERR#\n");
566 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
567 netdev_err(dev, "PCI parity error\n");
568
569 /* Write the error bits back to clear them. */
570 pci_cfg_stat &= (PCI_STATUS_PARITY |
571 PCI_STATUS_SIG_TARGET_ABORT |
572 PCI_STATUS_REC_TARGET_ABORT |
573 PCI_STATUS_REC_MASTER_ABORT |
574 PCI_STATUS_SIG_SYSTEM_ERROR |
575 PCI_STATUS_DETECTED_PARITY);
576 pci_write_config_word(gp->pdev,
577 PCI_STATUS, pci_cfg_stat);
578 }
579
580 /* For all PCI errors, we should reset the chip. */
581 return 1;
582 }
583
584 /* All non-normal interrupt conditions get serviced here.
585 * Returns non-zero if we should just exit the interrupt
586 * handler right now (ie. if we reset the card which invalidates
587 * all of the other original irq status bits).
588 */
589 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
590 {
591 if (gem_status & GREG_STAT_RXNOBUF) {
592 /* Frame arrived, no free RX buffers available. */
593 if (netif_msg_rx_err(gp))
594 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
595 gp->dev->name);
596 dev->stats.rx_dropped++;
597 }
598
599 if (gem_status & GREG_STAT_RXTAGERR) {
600 /* corrupt RX tag framing */
601 if (netif_msg_rx_err(gp))
602 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
603 gp->dev->name);
604 dev->stats.rx_errors++;
605
606 goto do_reset;
607 }
608
609 if (gem_status & GREG_STAT_PCS) {
610 if (gem_pcs_interrupt(dev, gp, gem_status))
611 goto do_reset;
612 }
613
614 if (gem_status & GREG_STAT_TXMAC) {
615 if (gem_txmac_interrupt(dev, gp, gem_status))
616 goto do_reset;
617 }
618
619 if (gem_status & GREG_STAT_RXMAC) {
620 if (gem_rxmac_interrupt(dev, gp, gem_status))
621 goto do_reset;
622 }
623
624 if (gem_status & GREG_STAT_MAC) {
625 if (gem_mac_interrupt(dev, gp, gem_status))
626 goto do_reset;
627 }
628
629 if (gem_status & GREG_STAT_MIF) {
630 if (gem_mif_interrupt(dev, gp, gem_status))
631 goto do_reset;
632 }
633
634 if (gem_status & GREG_STAT_PCIERR) {
635 if (gem_pci_interrupt(dev, gp, gem_status))
636 goto do_reset;
637 }
638
639 return 0;
640
641 do_reset:
642 gp->reset_task_pending = 1;
643 schedule_work(&gp->reset_task);
644
645 return 1;
646 }
647
648 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
649 {
650 int entry, limit;
651
652 if (netif_msg_intr(gp))
653 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
654 gp->dev->name, gem_status);
655
656 entry = gp->tx_old;
657 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
658 while (entry != limit) {
659 struct sk_buff *skb;
660 struct gem_txd *txd;
661 dma_addr_t dma_addr;
662 u32 dma_len;
663 int frag;
664
665 if (netif_msg_tx_done(gp))
666 printk(KERN_DEBUG "%s: tx done, slot %d\n",
667 gp->dev->name, entry);
668 skb = gp->tx_skbs[entry];
669 if (skb_shinfo(skb)->nr_frags) {
670 int last = entry + skb_shinfo(skb)->nr_frags;
671 int walk = entry;
672 int incomplete = 0;
673
674 last &= (TX_RING_SIZE - 1);
675 for (;;) {
676 walk = NEXT_TX(walk);
677 if (walk == limit)
678 incomplete = 1;
679 if (walk == last)
680 break;
681 }
682 if (incomplete)
683 break;
684 }
685 gp->tx_skbs[entry] = NULL;
686 dev->stats.tx_bytes += skb->len;
687
688 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
689 txd = &gp->init_block->txd[entry];
690
691 dma_addr = le64_to_cpu(txd->buffer);
692 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
693
694 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
695 entry = NEXT_TX(entry);
696 }
697
698 dev->stats.tx_packets++;
699 dev_kfree_skb_irq(skb);
700 }
701 gp->tx_old = entry;
702
703 if (netif_queue_stopped(dev) &&
704 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
705 netif_wake_queue(dev);
706 }
707
708 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
709 {
710 int cluster_start, curr, count, kick;
711
712 cluster_start = curr = (gp->rx_new & ~(4 - 1));
713 count = 0;
714 kick = -1;
715 wmb();
716 while (curr != limit) {
717 curr = NEXT_RX(curr);
718 if (++count == 4) {
719 struct gem_rxd *rxd =
720 &gp->init_block->rxd[cluster_start];
721 for (;;) {
722 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
723 rxd++;
724 cluster_start = NEXT_RX(cluster_start);
725 if (cluster_start == curr)
726 break;
727 }
728 kick = curr;
729 count = 0;
730 }
731 }
732 if (kick >= 0) {
733 mb();
734 writel(kick, gp->regs + RXDMA_KICK);
735 }
736 }
737
738 static int gem_rx(struct gem *gp, int work_to_do)
739 {
740 struct net_device *dev = gp->dev;
741 int entry, drops, work_done = 0;
742 u32 done;
743 __sum16 csum;
744
745 if (netif_msg_rx_status(gp))
746 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
747 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
748
749 entry = gp->rx_new;
750 drops = 0;
751 done = readl(gp->regs + RXDMA_DONE);
752 for (;;) {
753 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
754 struct sk_buff *skb;
755 u64 status = le64_to_cpu(rxd->status_word);
756 dma_addr_t dma_addr;
757 int len;
758
759 if ((status & RXDCTRL_OWN) != 0)
760 break;
761
762 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
763 break;
764
765 /* When writing back RX descriptor, GEM writes status
766 * then buffer address, possibly in separate transactions.
767 * If we don't wait for the chip to write both, we could
768 * post a new buffer to this descriptor then have GEM spam
769 * on the buffer address. We sync on the RX completion
770 * register to prevent this from happening.
771 */
772 if (entry == done) {
773 done = readl(gp->regs + RXDMA_DONE);
774 if (entry == done)
775 break;
776 }
777
778 /* We can now account for the work we're about to do */
779 work_done++;
780
781 skb = gp->rx_skbs[entry];
782
783 len = (status & RXDCTRL_BUFSZ) >> 16;
784 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
785 dev->stats.rx_errors++;
786 if (len < ETH_ZLEN)
787 dev->stats.rx_length_errors++;
788 if (len & RXDCTRL_BAD)
789 dev->stats.rx_crc_errors++;
790
791 /* We'll just return it to GEM. */
792 drop_it:
793 dev->stats.rx_dropped++;
794 goto next;
795 }
796
797 dma_addr = le64_to_cpu(rxd->buffer);
798 if (len > RX_COPY_THRESHOLD) {
799 struct sk_buff *new_skb;
800
801 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
802 if (new_skb == NULL) {
803 drops++;
804 goto drop_it;
805 }
806 pci_unmap_page(gp->pdev, dma_addr,
807 RX_BUF_ALLOC_SIZE(gp),
808 PCI_DMA_FROMDEVICE);
809 gp->rx_skbs[entry] = new_skb;
810 new_skb->dev = gp->dev;
811 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
812 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
813 virt_to_page(new_skb->data),
814 offset_in_page(new_skb->data),
815 RX_BUF_ALLOC_SIZE(gp),
816 PCI_DMA_FROMDEVICE));
817 skb_reserve(new_skb, RX_OFFSET);
818
819 /* Trim the original skb for the netif. */
820 skb_trim(skb, len);
821 } else {
822 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
823
824 if (copy_skb == NULL) {
825 drops++;
826 goto drop_it;
827 }
828
829 skb_reserve(copy_skb, 2);
830 skb_put(copy_skb, len);
831 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
832 skb_copy_from_linear_data(skb, copy_skb->data, len);
833 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
834
835 /* We'll reuse the original ring buffer. */
836 skb = copy_skb;
837 }
838
839 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
840 skb->csum = csum_unfold(csum);
841 skb->ip_summed = CHECKSUM_COMPLETE;
842 skb->protocol = eth_type_trans(skb, gp->dev);
843
844 netif_receive_skb(skb);
845
846 dev->stats.rx_packets++;
847 dev->stats.rx_bytes += len;
848
849 next:
850 entry = NEXT_RX(entry);
851 }
852
853 gem_post_rxds(gp, entry);
854
855 gp->rx_new = entry;
856
857 if (drops)
858 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
859
860 return work_done;
861 }
862
863 static int gem_poll(struct napi_struct *napi, int budget)
864 {
865 struct gem *gp = container_of(napi, struct gem, napi);
866 struct net_device *dev = gp->dev;
867 unsigned long flags;
868 int work_done;
869
870 /*
871 * NAPI locking nightmare: See comment at head of driver
872 */
873 spin_lock_irqsave(&gp->lock, flags);
874
875 work_done = 0;
876 do {
877 /* Handle anomalies */
878 if (gp->status & GREG_STAT_ABNORMAL) {
879 if (gem_abnormal_irq(dev, gp, gp->status))
880 break;
881 }
882
883 /* Run TX completion thread */
884 spin_lock(&gp->tx_lock);
885 gem_tx(dev, gp, gp->status);
886 spin_unlock(&gp->tx_lock);
887
888 spin_unlock_irqrestore(&gp->lock, flags);
889
890 /* Run RX thread. We don't use any locking here,
891 * code willing to do bad things - like cleaning the
892 * rx ring - must call napi_disable(), which
893 * schedule_timeout()'s if polling is already disabled.
894 */
895 work_done += gem_rx(gp, budget - work_done);
896
897 if (work_done >= budget)
898 return work_done;
899
900 spin_lock_irqsave(&gp->lock, flags);
901
902 gp->status = readl(gp->regs + GREG_STAT);
903 } while (gp->status & GREG_STAT_NAPI);
904
905 __napi_complete(napi);
906 gem_enable_ints(gp);
907
908 spin_unlock_irqrestore(&gp->lock, flags);
909
910 return work_done;
911 }
912
913 static irqreturn_t gem_interrupt(int irq, void *dev_id)
914 {
915 struct net_device *dev = dev_id;
916 struct gem *gp = netdev_priv(dev);
917 unsigned long flags;
918
919 /* Swallow interrupts when shutting the chip down, though
920 * that shouldn't happen, we should have done free_irq() at
921 * this point...
922 */
923 if (!gp->running)
924 return IRQ_HANDLED;
925
926 spin_lock_irqsave(&gp->lock, flags);
927
928 if (napi_schedule_prep(&gp->napi)) {
929 u32 gem_status = readl(gp->regs + GREG_STAT);
930
931 if (gem_status == 0) {
932 napi_enable(&gp->napi);
933 spin_unlock_irqrestore(&gp->lock, flags);
934 return IRQ_NONE;
935 }
936 gp->status = gem_status;
937 gem_disable_ints(gp);
938 __napi_schedule(&gp->napi);
939 }
940
941 spin_unlock_irqrestore(&gp->lock, flags);
942
943 /* If polling was disabled at the time we received that
944 * interrupt, we may return IRQ_HANDLED here while we
945 * should return IRQ_NONE. No big deal...
946 */
947 return IRQ_HANDLED;
948 }
949
950 #ifdef CONFIG_NET_POLL_CONTROLLER
951 static void gem_poll_controller(struct net_device *dev)
952 {
953 /* gem_interrupt is safe to reentrance so no need
954 * to disable_irq here.
955 */
956 gem_interrupt(dev->irq, dev);
957 }
958 #endif
959
960 static void gem_tx_timeout(struct net_device *dev)
961 {
962 struct gem *gp = netdev_priv(dev);
963
964 netdev_err(dev, "transmit timed out, resetting\n");
965 if (!gp->running) {
966 netdev_err(dev, "hrm.. hw not running !\n");
967 return;
968 }
969 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
970 readl(gp->regs + TXDMA_CFG),
971 readl(gp->regs + MAC_TXSTAT),
972 readl(gp->regs + MAC_TXCFG));
973 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
974 readl(gp->regs + RXDMA_CFG),
975 readl(gp->regs + MAC_RXSTAT),
976 readl(gp->regs + MAC_RXCFG));
977
978 spin_lock_irq(&gp->lock);
979 spin_lock(&gp->tx_lock);
980
981 gp->reset_task_pending = 1;
982 schedule_work(&gp->reset_task);
983
984 spin_unlock(&gp->tx_lock);
985 spin_unlock_irq(&gp->lock);
986 }
987
988 static __inline__ int gem_intme(int entry)
989 {
990 /* Algorithm: IRQ every 1/2 of descriptors. */
991 if (!(entry & ((TX_RING_SIZE>>1)-1)))
992 return 1;
993
994 return 0;
995 }
996
997 static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
998 struct net_device *dev)
999 {
1000 struct gem *gp = netdev_priv(dev);
1001 int entry;
1002 u64 ctrl;
1003 unsigned long flags;
1004
1005 ctrl = 0;
1006 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1007 const u64 csum_start_off = skb_checksum_start_offset(skb);
1008 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1009
1010 ctrl = (TXDCTRL_CENAB |
1011 (csum_start_off << 15) |
1012 (csum_stuff_off << 21));
1013 }
1014
1015 if (!spin_trylock_irqsave(&gp->tx_lock, flags)) {
1016 /* Tell upper layer to requeue */
1017 return NETDEV_TX_LOCKED;
1018 }
1019 /* We raced with gem_do_stop() */
1020 if (!gp->running) {
1021 spin_unlock_irqrestore(&gp->tx_lock, flags);
1022 return NETDEV_TX_BUSY;
1023 }
1024
1025 /* This is a hard error, log it. */
1026 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1027 netif_stop_queue(dev);
1028 spin_unlock_irqrestore(&gp->tx_lock, flags);
1029 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1030 return NETDEV_TX_BUSY;
1031 }
1032
1033 entry = gp->tx_new;
1034 gp->tx_skbs[entry] = skb;
1035
1036 if (skb_shinfo(skb)->nr_frags == 0) {
1037 struct gem_txd *txd = &gp->init_block->txd[entry];
1038 dma_addr_t mapping;
1039 u32 len;
1040
1041 len = skb->len;
1042 mapping = pci_map_page(gp->pdev,
1043 virt_to_page(skb->data),
1044 offset_in_page(skb->data),
1045 len, PCI_DMA_TODEVICE);
1046 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1047 if (gem_intme(entry))
1048 ctrl |= TXDCTRL_INTME;
1049 txd->buffer = cpu_to_le64(mapping);
1050 wmb();
1051 txd->control_word = cpu_to_le64(ctrl);
1052 entry = NEXT_TX(entry);
1053 } else {
1054 struct gem_txd *txd;
1055 u32 first_len;
1056 u64 intme;
1057 dma_addr_t first_mapping;
1058 int frag, first_entry = entry;
1059
1060 intme = 0;
1061 if (gem_intme(entry))
1062 intme |= TXDCTRL_INTME;
1063
1064 /* We must give this initial chunk to the device last.
1065 * Otherwise we could race with the device.
1066 */
1067 first_len = skb_headlen(skb);
1068 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1069 offset_in_page(skb->data),
1070 first_len, PCI_DMA_TODEVICE);
1071 entry = NEXT_TX(entry);
1072
1073 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1074 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1075 u32 len;
1076 dma_addr_t mapping;
1077 u64 this_ctrl;
1078
1079 len = this_frag->size;
1080 mapping = pci_map_page(gp->pdev,
1081 this_frag->page,
1082 this_frag->page_offset,
1083 len, PCI_DMA_TODEVICE);
1084 this_ctrl = ctrl;
1085 if (frag == skb_shinfo(skb)->nr_frags - 1)
1086 this_ctrl |= TXDCTRL_EOF;
1087
1088 txd = &gp->init_block->txd[entry];
1089 txd->buffer = cpu_to_le64(mapping);
1090 wmb();
1091 txd->control_word = cpu_to_le64(this_ctrl | len);
1092
1093 if (gem_intme(entry))
1094 intme |= TXDCTRL_INTME;
1095
1096 entry = NEXT_TX(entry);
1097 }
1098 txd = &gp->init_block->txd[first_entry];
1099 txd->buffer = cpu_to_le64(first_mapping);
1100 wmb();
1101 txd->control_word =
1102 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1103 }
1104
1105 gp->tx_new = entry;
1106 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1107 netif_stop_queue(dev);
1108
1109 if (netif_msg_tx_queued(gp))
1110 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1111 dev->name, entry, skb->len);
1112 mb();
1113 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1114 spin_unlock_irqrestore(&gp->tx_lock, flags);
1115
1116 dev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1117
1118 return NETDEV_TX_OK;
1119 }
1120
1121 static void gem_pcs_reset(struct gem *gp)
1122 {
1123 int limit;
1124 u32 val;
1125
1126 /* Reset PCS unit. */
1127 val = readl(gp->regs + PCS_MIICTRL);
1128 val |= PCS_MIICTRL_RST;
1129 writel(val, gp->regs + PCS_MIICTRL);
1130
1131 limit = 32;
1132 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1133 udelay(100);
1134 if (limit-- <= 0)
1135 break;
1136 }
1137 if (limit < 0)
1138 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1139 }
1140
1141 static void gem_pcs_reinit_adv(struct gem *gp)
1142 {
1143 u32 val;
1144
1145 /* Make sure PCS is disabled while changing advertisement
1146 * configuration.
1147 */
1148 val = readl(gp->regs + PCS_CFG);
1149 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1150 writel(val, gp->regs + PCS_CFG);
1151
1152 /* Advertise all capabilities except asymmetric
1153 * pause.
1154 */
1155 val = readl(gp->regs + PCS_MIIADV);
1156 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1157 PCS_MIIADV_SP | PCS_MIIADV_AP);
1158 writel(val, gp->regs + PCS_MIIADV);
1159
1160 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1161 * and re-enable PCS.
1162 */
1163 val = readl(gp->regs + PCS_MIICTRL);
1164 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1165 val &= ~PCS_MIICTRL_WB;
1166 writel(val, gp->regs + PCS_MIICTRL);
1167
1168 val = readl(gp->regs + PCS_CFG);
1169 val |= PCS_CFG_ENABLE;
1170 writel(val, gp->regs + PCS_CFG);
1171
1172 /* Make sure serialink loopback is off. The meaning
1173 * of this bit is logically inverted based upon whether
1174 * you are in Serialink or SERDES mode.
1175 */
1176 val = readl(gp->regs + PCS_SCTRL);
1177 if (gp->phy_type == phy_serialink)
1178 val &= ~PCS_SCTRL_LOOP;
1179 else
1180 val |= PCS_SCTRL_LOOP;
1181 writel(val, gp->regs + PCS_SCTRL);
1182 }
1183
1184 #define STOP_TRIES 32
1185
1186 /* Must be invoked under gp->lock and gp->tx_lock. */
1187 static void gem_reset(struct gem *gp)
1188 {
1189 int limit;
1190 u32 val;
1191
1192 /* Make sure we won't get any more interrupts */
1193 writel(0xffffffff, gp->regs + GREG_IMASK);
1194
1195 /* Reset the chip */
1196 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1197 gp->regs + GREG_SWRST);
1198
1199 limit = STOP_TRIES;
1200
1201 do {
1202 udelay(20);
1203 val = readl(gp->regs + GREG_SWRST);
1204 if (limit-- <= 0)
1205 break;
1206 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1207
1208 if (limit < 0)
1209 netdev_err(gp->dev, "SW reset is ghetto\n");
1210
1211 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1212 gem_pcs_reinit_adv(gp);
1213 }
1214
1215 /* Must be invoked under gp->lock and gp->tx_lock. */
1216 static void gem_start_dma(struct gem *gp)
1217 {
1218 u32 val;
1219
1220 /* We are ready to rock, turn everything on. */
1221 val = readl(gp->regs + TXDMA_CFG);
1222 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1223 val = readl(gp->regs + RXDMA_CFG);
1224 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1225 val = readl(gp->regs + MAC_TXCFG);
1226 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1227 val = readl(gp->regs + MAC_RXCFG);
1228 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1229
1230 (void) readl(gp->regs + MAC_RXCFG);
1231 udelay(100);
1232
1233 gem_enable_ints(gp);
1234
1235 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1236 }
1237
1238 /* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1239 * actually stopped before about 4ms tho ...
1240 */
1241 static void gem_stop_dma(struct gem *gp)
1242 {
1243 u32 val;
1244
1245 /* We are done rocking, turn everything off. */
1246 val = readl(gp->regs + TXDMA_CFG);
1247 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1248 val = readl(gp->regs + RXDMA_CFG);
1249 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1250 val = readl(gp->regs + MAC_TXCFG);
1251 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1252 val = readl(gp->regs + MAC_RXCFG);
1253 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1254
1255 (void) readl(gp->regs + MAC_RXCFG);
1256
1257 /* Need to wait a bit ... done by the caller */
1258 }
1259
1260
1261 /* Must be invoked under gp->lock and gp->tx_lock. */
1262 // XXX dbl check what that function should do when called on PCS PHY
1263 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1264 {
1265 u32 advertise, features;
1266 int autoneg;
1267 int speed;
1268 int duplex;
1269
1270 if (gp->phy_type != phy_mii_mdio0 &&
1271 gp->phy_type != phy_mii_mdio1)
1272 goto non_mii;
1273
1274 /* Setup advertise */
1275 if (found_mii_phy(gp))
1276 features = gp->phy_mii.def->features;
1277 else
1278 features = 0;
1279
1280 advertise = features & ADVERTISE_MASK;
1281 if (gp->phy_mii.advertising != 0)
1282 advertise &= gp->phy_mii.advertising;
1283
1284 autoneg = gp->want_autoneg;
1285 speed = gp->phy_mii.speed;
1286 duplex = gp->phy_mii.duplex;
1287
1288 /* Setup link parameters */
1289 if (!ep)
1290 goto start_aneg;
1291 if (ep->autoneg == AUTONEG_ENABLE) {
1292 advertise = ep->advertising;
1293 autoneg = 1;
1294 } else {
1295 autoneg = 0;
1296 speed = ethtool_cmd_speed(ep);
1297 duplex = ep->duplex;
1298 }
1299
1300 start_aneg:
1301 /* Sanitize settings based on PHY capabilities */
1302 if ((features & SUPPORTED_Autoneg) == 0)
1303 autoneg = 0;
1304 if (speed == SPEED_1000 &&
1305 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1306 speed = SPEED_100;
1307 if (speed == SPEED_100 &&
1308 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1309 speed = SPEED_10;
1310 if (duplex == DUPLEX_FULL &&
1311 !(features & (SUPPORTED_1000baseT_Full |
1312 SUPPORTED_100baseT_Full |
1313 SUPPORTED_10baseT_Full)))
1314 duplex = DUPLEX_HALF;
1315 if (speed == 0)
1316 speed = SPEED_10;
1317
1318 /* If we are asleep, we don't try to actually setup the PHY, we
1319 * just store the settings
1320 */
1321 if (gp->asleep) {
1322 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1323 gp->phy_mii.speed = speed;
1324 gp->phy_mii.duplex = duplex;
1325 return;
1326 }
1327
1328 /* Configure PHY & start aneg */
1329 gp->want_autoneg = autoneg;
1330 if (autoneg) {
1331 if (found_mii_phy(gp))
1332 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1333 gp->lstate = link_aneg;
1334 } else {
1335 if (found_mii_phy(gp))
1336 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1337 gp->lstate = link_force_ok;
1338 }
1339
1340 non_mii:
1341 gp->timer_ticks = 0;
1342 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1343 }
1344
1345 /* A link-up condition has occurred, initialize and enable the
1346 * rest of the chip.
1347 *
1348 * Must be invoked under gp->lock and gp->tx_lock.
1349 */
1350 static int gem_set_link_modes(struct gem *gp)
1351 {
1352 u32 val;
1353 int full_duplex, speed, pause;
1354
1355 full_duplex = 0;
1356 speed = SPEED_10;
1357 pause = 0;
1358
1359 if (found_mii_phy(gp)) {
1360 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1361 return 1;
1362 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1363 speed = gp->phy_mii.speed;
1364 pause = gp->phy_mii.pause;
1365 } else if (gp->phy_type == phy_serialink ||
1366 gp->phy_type == phy_serdes) {
1367 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1368
1369 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1370 full_duplex = 1;
1371 speed = SPEED_1000;
1372 }
1373
1374 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1375 speed, (full_duplex ? "full" : "half"));
1376
1377 if (!gp->running)
1378 return 0;
1379
1380 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1381 if (full_duplex) {
1382 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1383 } else {
1384 /* MAC_TXCFG_NBO must be zero. */
1385 }
1386 writel(val, gp->regs + MAC_TXCFG);
1387
1388 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1389 if (!full_duplex &&
1390 (gp->phy_type == phy_mii_mdio0 ||
1391 gp->phy_type == phy_mii_mdio1)) {
1392 val |= MAC_XIFCFG_DISE;
1393 } else if (full_duplex) {
1394 val |= MAC_XIFCFG_FLED;
1395 }
1396
1397 if (speed == SPEED_1000)
1398 val |= (MAC_XIFCFG_GMII);
1399
1400 writel(val, gp->regs + MAC_XIFCFG);
1401
1402 /* If gigabit and half-duplex, enable carrier extension
1403 * mode. Else, disable it.
1404 */
1405 if (speed == SPEED_1000 && !full_duplex) {
1406 val = readl(gp->regs + MAC_TXCFG);
1407 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1408
1409 val = readl(gp->regs + MAC_RXCFG);
1410 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1411 } else {
1412 val = readl(gp->regs + MAC_TXCFG);
1413 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1414
1415 val = readl(gp->regs + MAC_RXCFG);
1416 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1417 }
1418
1419 if (gp->phy_type == phy_serialink ||
1420 gp->phy_type == phy_serdes) {
1421 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1422
1423 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1424 pause = 1;
1425 }
1426
1427 if (netif_msg_link(gp)) {
1428 if (pause) {
1429 netdev_info(gp->dev,
1430 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1431 gp->rx_fifo_sz,
1432 gp->rx_pause_off,
1433 gp->rx_pause_on);
1434 } else {
1435 netdev_info(gp->dev, "Pause is disabled\n");
1436 }
1437 }
1438
1439 if (!full_duplex)
1440 writel(512, gp->regs + MAC_STIME);
1441 else
1442 writel(64, gp->regs + MAC_STIME);
1443 val = readl(gp->regs + MAC_MCCFG);
1444 if (pause)
1445 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1446 else
1447 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1448 writel(val, gp->regs + MAC_MCCFG);
1449
1450 gem_start_dma(gp);
1451
1452 return 0;
1453 }
1454
1455 /* Must be invoked under gp->lock and gp->tx_lock. */
1456 static int gem_mdio_link_not_up(struct gem *gp)
1457 {
1458 switch (gp->lstate) {
1459 case link_force_ret:
1460 netif_info(gp, link, gp->dev,
1461 "Autoneg failed again, keeping forced mode\n");
1462 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1463 gp->last_forced_speed, DUPLEX_HALF);
1464 gp->timer_ticks = 5;
1465 gp->lstate = link_force_ok;
1466 return 0;
1467 case link_aneg:
1468 /* We try forced modes after a failed aneg only on PHYs that don't
1469 * have "magic_aneg" bit set, which means they internally do the
1470 * while forced-mode thingy. On these, we just restart aneg
1471 */
1472 if (gp->phy_mii.def->magic_aneg)
1473 return 1;
1474 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1475 /* Try forced modes. */
1476 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1477 DUPLEX_HALF);
1478 gp->timer_ticks = 5;
1479 gp->lstate = link_force_try;
1480 return 0;
1481 case link_force_try:
1482 /* Downgrade from 100 to 10 Mbps if necessary.
1483 * If already at 10Mbps, warn user about the
1484 * situation every 10 ticks.
1485 */
1486 if (gp->phy_mii.speed == SPEED_100) {
1487 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1488 DUPLEX_HALF);
1489 gp->timer_ticks = 5;
1490 netif_info(gp, link, gp->dev,
1491 "switching to forced 10bt\n");
1492 return 0;
1493 } else
1494 return 1;
1495 default:
1496 return 0;
1497 }
1498 }
1499
1500 static void gem_link_timer(unsigned long data)
1501 {
1502 struct gem *gp = (struct gem *) data;
1503 int restart_aneg = 0;
1504
1505 if (gp->asleep)
1506 return;
1507
1508 spin_lock_irq(&gp->lock);
1509 spin_lock(&gp->tx_lock);
1510 gem_get_cell(gp);
1511
1512 /* If the reset task is still pending, we just
1513 * reschedule the link timer
1514 */
1515 if (gp->reset_task_pending)
1516 goto restart;
1517
1518 if (gp->phy_type == phy_serialink ||
1519 gp->phy_type == phy_serdes) {
1520 u32 val = readl(gp->regs + PCS_MIISTAT);
1521
1522 if (!(val & PCS_MIISTAT_LS))
1523 val = readl(gp->regs + PCS_MIISTAT);
1524
1525 if ((val & PCS_MIISTAT_LS) != 0) {
1526 if (gp->lstate == link_up)
1527 goto restart;
1528
1529 gp->lstate = link_up;
1530 netif_carrier_on(gp->dev);
1531 (void)gem_set_link_modes(gp);
1532 }
1533 goto restart;
1534 }
1535 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1536 /* Ok, here we got a link. If we had it due to a forced
1537 * fallback, and we were configured for autoneg, we do
1538 * retry a short autoneg pass. If you know your hub is
1539 * broken, use ethtool ;)
1540 */
1541 if (gp->lstate == link_force_try && gp->want_autoneg) {
1542 gp->lstate = link_force_ret;
1543 gp->last_forced_speed = gp->phy_mii.speed;
1544 gp->timer_ticks = 5;
1545 if (netif_msg_link(gp))
1546 netdev_info(gp->dev,
1547 "Got link after fallback, retrying autoneg once...\n");
1548 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1549 } else if (gp->lstate != link_up) {
1550 gp->lstate = link_up;
1551 netif_carrier_on(gp->dev);
1552 if (gem_set_link_modes(gp))
1553 restart_aneg = 1;
1554 }
1555 } else {
1556 /* If the link was previously up, we restart the
1557 * whole process
1558 */
1559 if (gp->lstate == link_up) {
1560 gp->lstate = link_down;
1561 netif_info(gp, link, gp->dev, "Link down\n");
1562 netif_carrier_off(gp->dev);
1563 gp->reset_task_pending = 1;
1564 schedule_work(&gp->reset_task);
1565 restart_aneg = 1;
1566 } else if (++gp->timer_ticks > 10) {
1567 if (found_mii_phy(gp))
1568 restart_aneg = gem_mdio_link_not_up(gp);
1569 else
1570 restart_aneg = 1;
1571 }
1572 }
1573 if (restart_aneg) {
1574 gem_begin_auto_negotiation(gp, NULL);
1575 goto out_unlock;
1576 }
1577 restart:
1578 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1579 out_unlock:
1580 gem_put_cell(gp);
1581 spin_unlock(&gp->tx_lock);
1582 spin_unlock_irq(&gp->lock);
1583 }
1584
1585 /* Must be invoked under gp->lock and gp->tx_lock. */
1586 static void gem_clean_rings(struct gem *gp)
1587 {
1588 struct gem_init_block *gb = gp->init_block;
1589 struct sk_buff *skb;
1590 int i;
1591 dma_addr_t dma_addr;
1592
1593 for (i = 0; i < RX_RING_SIZE; i++) {
1594 struct gem_rxd *rxd;
1595
1596 rxd = &gb->rxd[i];
1597 if (gp->rx_skbs[i] != NULL) {
1598 skb = gp->rx_skbs[i];
1599 dma_addr = le64_to_cpu(rxd->buffer);
1600 pci_unmap_page(gp->pdev, dma_addr,
1601 RX_BUF_ALLOC_SIZE(gp),
1602 PCI_DMA_FROMDEVICE);
1603 dev_kfree_skb_any(skb);
1604 gp->rx_skbs[i] = NULL;
1605 }
1606 rxd->status_word = 0;
1607 wmb();
1608 rxd->buffer = 0;
1609 }
1610
1611 for (i = 0; i < TX_RING_SIZE; i++) {
1612 if (gp->tx_skbs[i] != NULL) {
1613 struct gem_txd *txd;
1614 int frag;
1615
1616 skb = gp->tx_skbs[i];
1617 gp->tx_skbs[i] = NULL;
1618
1619 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1620 int ent = i & (TX_RING_SIZE - 1);
1621
1622 txd = &gb->txd[ent];
1623 dma_addr = le64_to_cpu(txd->buffer);
1624 pci_unmap_page(gp->pdev, dma_addr,
1625 le64_to_cpu(txd->control_word) &
1626 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1627
1628 if (frag != skb_shinfo(skb)->nr_frags)
1629 i++;
1630 }
1631 dev_kfree_skb_any(skb);
1632 }
1633 }
1634 }
1635
1636 /* Must be invoked under gp->lock and gp->tx_lock. */
1637 static void gem_init_rings(struct gem *gp)
1638 {
1639 struct gem_init_block *gb = gp->init_block;
1640 struct net_device *dev = gp->dev;
1641 int i;
1642 dma_addr_t dma_addr;
1643
1644 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1645
1646 gem_clean_rings(gp);
1647
1648 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1649 (unsigned)VLAN_ETH_FRAME_LEN);
1650
1651 for (i = 0; i < RX_RING_SIZE; i++) {
1652 struct sk_buff *skb;
1653 struct gem_rxd *rxd = &gb->rxd[i];
1654
1655 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1656 if (!skb) {
1657 rxd->buffer = 0;
1658 rxd->status_word = 0;
1659 continue;
1660 }
1661
1662 gp->rx_skbs[i] = skb;
1663 skb->dev = dev;
1664 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1665 dma_addr = pci_map_page(gp->pdev,
1666 virt_to_page(skb->data),
1667 offset_in_page(skb->data),
1668 RX_BUF_ALLOC_SIZE(gp),
1669 PCI_DMA_FROMDEVICE);
1670 rxd->buffer = cpu_to_le64(dma_addr);
1671 wmb();
1672 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1673 skb_reserve(skb, RX_OFFSET);
1674 }
1675
1676 for (i = 0; i < TX_RING_SIZE; i++) {
1677 struct gem_txd *txd = &gb->txd[i];
1678
1679 txd->control_word = 0;
1680 wmb();
1681 txd->buffer = 0;
1682 }
1683 wmb();
1684 }
1685
1686 /* Init PHY interface and start link poll state machine */
1687 static void gem_init_phy(struct gem *gp)
1688 {
1689 u32 mifcfg;
1690
1691 /* Revert MIF CFG setting done on stop_phy */
1692 mifcfg = readl(gp->regs + MIF_CFG);
1693 mifcfg &= ~MIF_CFG_BBMODE;
1694 writel(mifcfg, gp->regs + MIF_CFG);
1695
1696 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1697 int i;
1698
1699 /* Those delay sucks, the HW seem to love them though, I'll
1700 * serisouly consider breaking some locks here to be able
1701 * to schedule instead
1702 */
1703 for (i = 0; i < 3; i++) {
1704 #ifdef CONFIG_PPC_PMAC
1705 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1706 msleep(20);
1707 #endif
1708 /* Some PHYs used by apple have problem getting back to us,
1709 * we do an additional reset here
1710 */
1711 phy_write(gp, MII_BMCR, BMCR_RESET);
1712 msleep(20);
1713 if (phy_read(gp, MII_BMCR) != 0xffff)
1714 break;
1715 if (i == 2)
1716 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1717 }
1718 }
1719
1720 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1721 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1722 u32 val;
1723
1724 /* Init datapath mode register. */
1725 if (gp->phy_type == phy_mii_mdio0 ||
1726 gp->phy_type == phy_mii_mdio1) {
1727 val = PCS_DMODE_MGM;
1728 } else if (gp->phy_type == phy_serialink) {
1729 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1730 } else {
1731 val = PCS_DMODE_ESM;
1732 }
1733
1734 writel(val, gp->regs + PCS_DMODE);
1735 }
1736
1737 if (gp->phy_type == phy_mii_mdio0 ||
1738 gp->phy_type == phy_mii_mdio1) {
1739 // XXX check for errors
1740 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1741
1742 /* Init PHY */
1743 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1744 gp->phy_mii.def->ops->init(&gp->phy_mii);
1745 } else {
1746 gem_pcs_reset(gp);
1747 gem_pcs_reinit_adv(gp);
1748 }
1749
1750 /* Default aneg parameters */
1751 gp->timer_ticks = 0;
1752 gp->lstate = link_down;
1753 netif_carrier_off(gp->dev);
1754
1755 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1756 spin_lock_irq(&gp->lock);
1757 gem_begin_auto_negotiation(gp, NULL);
1758 spin_unlock_irq(&gp->lock);
1759 }
1760
1761 /* Must be invoked under gp->lock and gp->tx_lock. */
1762 static void gem_init_dma(struct gem *gp)
1763 {
1764 u64 desc_dma = (u64) gp->gblock_dvma;
1765 u32 val;
1766
1767 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1768 writel(val, gp->regs + TXDMA_CFG);
1769
1770 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1771 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1772 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1773
1774 writel(0, gp->regs + TXDMA_KICK);
1775
1776 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1777 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1778 writel(val, gp->regs + RXDMA_CFG);
1779
1780 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1781 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1782
1783 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1784
1785 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1786 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1787 writel(val, gp->regs + RXDMA_PTHRESH);
1788
1789 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1790 writel(((5 & RXDMA_BLANK_IPKTS) |
1791 ((8 << 12) & RXDMA_BLANK_ITIME)),
1792 gp->regs + RXDMA_BLANK);
1793 else
1794 writel(((5 & RXDMA_BLANK_IPKTS) |
1795 ((4 << 12) & RXDMA_BLANK_ITIME)),
1796 gp->regs + RXDMA_BLANK);
1797 }
1798
1799 /* Must be invoked under gp->lock and gp->tx_lock. */
1800 static u32 gem_setup_multicast(struct gem *gp)
1801 {
1802 u32 rxcfg = 0;
1803 int i;
1804
1805 if ((gp->dev->flags & IFF_ALLMULTI) ||
1806 (netdev_mc_count(gp->dev) > 256)) {
1807 for (i=0; i<16; i++)
1808 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1809 rxcfg |= MAC_RXCFG_HFE;
1810 } else if (gp->dev->flags & IFF_PROMISC) {
1811 rxcfg |= MAC_RXCFG_PROM;
1812 } else {
1813 u16 hash_table[16];
1814 u32 crc;
1815 struct netdev_hw_addr *ha;
1816 int i;
1817
1818 memset(hash_table, 0, sizeof(hash_table));
1819 netdev_for_each_mc_addr(ha, gp->dev) {
1820 char *addrs = ha->addr;
1821
1822 if (!(*addrs & 1))
1823 continue;
1824
1825 crc = ether_crc_le(6, addrs);
1826 crc >>= 24;
1827 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1828 }
1829 for (i=0; i<16; i++)
1830 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1831 rxcfg |= MAC_RXCFG_HFE;
1832 }
1833
1834 return rxcfg;
1835 }
1836
1837 /* Must be invoked under gp->lock and gp->tx_lock. */
1838 static void gem_init_mac(struct gem *gp)
1839 {
1840 unsigned char *e = &gp->dev->dev_addr[0];
1841
1842 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1843
1844 writel(0x00, gp->regs + MAC_IPG0);
1845 writel(0x08, gp->regs + MAC_IPG1);
1846 writel(0x04, gp->regs + MAC_IPG2);
1847 writel(0x40, gp->regs + MAC_STIME);
1848 writel(0x40, gp->regs + MAC_MINFSZ);
1849
1850 /* Ethernet payload + header + FCS + optional VLAN tag. */
1851 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1852
1853 writel(0x07, gp->regs + MAC_PASIZE);
1854 writel(0x04, gp->regs + MAC_JAMSIZE);
1855 writel(0x10, gp->regs + MAC_ATTLIM);
1856 writel(0x8808, gp->regs + MAC_MCTYPE);
1857
1858 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1859
1860 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1861 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1862 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1863
1864 writel(0, gp->regs + MAC_ADDR3);
1865 writel(0, gp->regs + MAC_ADDR4);
1866 writel(0, gp->regs + MAC_ADDR5);
1867
1868 writel(0x0001, gp->regs + MAC_ADDR6);
1869 writel(0xc200, gp->regs + MAC_ADDR7);
1870 writel(0x0180, gp->regs + MAC_ADDR8);
1871
1872 writel(0, gp->regs + MAC_AFILT0);
1873 writel(0, gp->regs + MAC_AFILT1);
1874 writel(0, gp->regs + MAC_AFILT2);
1875 writel(0, gp->regs + MAC_AF21MSK);
1876 writel(0, gp->regs + MAC_AF0MSK);
1877
1878 gp->mac_rx_cfg = gem_setup_multicast(gp);
1879 #ifdef STRIP_FCS
1880 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1881 #endif
1882 writel(0, gp->regs + MAC_NCOLL);
1883 writel(0, gp->regs + MAC_FASUCC);
1884 writel(0, gp->regs + MAC_ECOLL);
1885 writel(0, gp->regs + MAC_LCOLL);
1886 writel(0, gp->regs + MAC_DTIMER);
1887 writel(0, gp->regs + MAC_PATMPS);
1888 writel(0, gp->regs + MAC_RFCTR);
1889 writel(0, gp->regs + MAC_LERR);
1890 writel(0, gp->regs + MAC_AERR);
1891 writel(0, gp->regs + MAC_FCSERR);
1892 writel(0, gp->regs + MAC_RXCVERR);
1893
1894 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1895 * them once a link is established.
1896 */
1897 writel(0, gp->regs + MAC_TXCFG);
1898 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1899 writel(0, gp->regs + MAC_MCCFG);
1900 writel(0, gp->regs + MAC_XIFCFG);
1901
1902 /* Setup MAC interrupts. We want to get all of the interesting
1903 * counter expiration events, but we do not want to hear about
1904 * normal rx/tx as the DMA engine tells us that.
1905 */
1906 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1907 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1908
1909 /* Don't enable even the PAUSE interrupts for now, we
1910 * make no use of those events other than to record them.
1911 */
1912 writel(0xffffffff, gp->regs + MAC_MCMASK);
1913
1914 /* Don't enable GEM's WOL in normal operations
1915 */
1916 if (gp->has_wol)
1917 writel(0, gp->regs + WOL_WAKECSR);
1918 }
1919
1920 /* Must be invoked under gp->lock and gp->tx_lock. */
1921 static void gem_init_pause_thresholds(struct gem *gp)
1922 {
1923 u32 cfg;
1924
1925 /* Calculate pause thresholds. Setting the OFF threshold to the
1926 * full RX fifo size effectively disables PAUSE generation which
1927 * is what we do for 10/100 only GEMs which have FIFOs too small
1928 * to make real gains from PAUSE.
1929 */
1930 if (gp->rx_fifo_sz <= (2 * 1024)) {
1931 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1932 } else {
1933 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1934 int off = (gp->rx_fifo_sz - (max_frame * 2));
1935 int on = off - max_frame;
1936
1937 gp->rx_pause_off = off;
1938 gp->rx_pause_on = on;
1939 }
1940
1941
1942 /* Configure the chip "burst" DMA mode & enable some
1943 * HW bug fixes on Apple version
1944 */
1945 cfg = 0;
1946 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1947 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1948 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1949 cfg |= GREG_CFG_IBURST;
1950 #endif
1951 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1952 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1953 writel(cfg, gp->regs + GREG_CFG);
1954
1955 /* If Infinite Burst didn't stick, then use different
1956 * thresholds (and Apple bug fixes don't exist)
1957 */
1958 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1959 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1960 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1961 writel(cfg, gp->regs + GREG_CFG);
1962 }
1963 }
1964
1965 static int gem_check_invariants(struct gem *gp)
1966 {
1967 struct pci_dev *pdev = gp->pdev;
1968 u32 mif_cfg;
1969
1970 /* On Apple's sungem, we can't rely on registers as the chip
1971 * was been powered down by the firmware. The PHY is looked
1972 * up later on.
1973 */
1974 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1975 gp->phy_type = phy_mii_mdio0;
1976 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1977 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1978 gp->swrst_base = 0;
1979
1980 mif_cfg = readl(gp->regs + MIF_CFG);
1981 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1982 mif_cfg |= MIF_CFG_MDI0;
1983 writel(mif_cfg, gp->regs + MIF_CFG);
1984 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1985 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1986
1987 /* We hard-code the PHY address so we can properly bring it out of
1988 * reset later on, we can't really probe it at this point, though
1989 * that isn't an issue.
1990 */
1991 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1992 gp->mii_phy_addr = 1;
1993 else
1994 gp->mii_phy_addr = 0;
1995
1996 return 0;
1997 }
1998
1999 mif_cfg = readl(gp->regs + MIF_CFG);
2000
2001 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2002 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2003 /* One of the MII PHYs _must_ be present
2004 * as this chip has no gigabit PHY.
2005 */
2006 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2007 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2008 mif_cfg);
2009 return -1;
2010 }
2011 }
2012
2013 /* Determine initial PHY interface type guess. MDIO1 is the
2014 * external PHY and thus takes precedence over MDIO0.
2015 */
2016
2017 if (mif_cfg & MIF_CFG_MDI1) {
2018 gp->phy_type = phy_mii_mdio1;
2019 mif_cfg |= MIF_CFG_PSELECT;
2020 writel(mif_cfg, gp->regs + MIF_CFG);
2021 } else if (mif_cfg & MIF_CFG_MDI0) {
2022 gp->phy_type = phy_mii_mdio0;
2023 mif_cfg &= ~MIF_CFG_PSELECT;
2024 writel(mif_cfg, gp->regs + MIF_CFG);
2025 } else {
2026 #ifdef CONFIG_SPARC
2027 const char *p;
2028
2029 p = of_get_property(gp->of_node, "shared-pins", NULL);
2030 if (p && !strcmp(p, "serdes"))
2031 gp->phy_type = phy_serdes;
2032 else
2033 #endif
2034 gp->phy_type = phy_serialink;
2035 }
2036 if (gp->phy_type == phy_mii_mdio1 ||
2037 gp->phy_type == phy_mii_mdio0) {
2038 int i;
2039
2040 for (i = 0; i < 32; i++) {
2041 gp->mii_phy_addr = i;
2042 if (phy_read(gp, MII_BMCR) != 0xffff)
2043 break;
2044 }
2045 if (i == 32) {
2046 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2047 pr_err("RIO MII phy will not respond\n");
2048 return -1;
2049 }
2050 gp->phy_type = phy_serdes;
2051 }
2052 }
2053
2054 /* Fetch the FIFO configurations now too. */
2055 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2056 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2057
2058 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2059 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2060 if (gp->tx_fifo_sz != (9 * 1024) ||
2061 gp->rx_fifo_sz != (20 * 1024)) {
2062 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2063 gp->tx_fifo_sz, gp->rx_fifo_sz);
2064 return -1;
2065 }
2066 gp->swrst_base = 0;
2067 } else {
2068 if (gp->tx_fifo_sz != (2 * 1024) ||
2069 gp->rx_fifo_sz != (2 * 1024)) {
2070 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2071 gp->tx_fifo_sz, gp->rx_fifo_sz);
2072 return -1;
2073 }
2074 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2075 }
2076 }
2077
2078 return 0;
2079 }
2080
2081 /* Must be invoked under gp->lock and gp->tx_lock. */
2082 static void gem_reinit_chip(struct gem *gp)
2083 {
2084 /* Reset the chip */
2085 gem_reset(gp);
2086
2087 /* Make sure ints are disabled */
2088 gem_disable_ints(gp);
2089
2090 /* Allocate & setup ring buffers */
2091 gem_init_rings(gp);
2092
2093 /* Configure pause thresholds */
2094 gem_init_pause_thresholds(gp);
2095
2096 /* Init DMA & MAC engines */
2097 gem_init_dma(gp);
2098 gem_init_mac(gp);
2099 }
2100
2101
2102 /* Must be invoked with no lock held. */
2103 static void gem_stop_phy(struct gem *gp, int wol)
2104 {
2105 u32 mifcfg;
2106 unsigned long flags;
2107
2108 /* Let the chip settle down a bit, it seems that helps
2109 * for sleep mode on some models
2110 */
2111 msleep(10);
2112
2113 /* Make sure we aren't polling PHY status change. We
2114 * don't currently use that feature though
2115 */
2116 mifcfg = readl(gp->regs + MIF_CFG);
2117 mifcfg &= ~MIF_CFG_POLL;
2118 writel(mifcfg, gp->regs + MIF_CFG);
2119
2120 if (wol && gp->has_wol) {
2121 unsigned char *e = &gp->dev->dev_addr[0];
2122 u32 csr;
2123
2124 /* Setup wake-on-lan for MAGIC packet */
2125 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2126 gp->regs + MAC_RXCFG);
2127 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2128 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2129 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2130
2131 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2132 csr = WOL_WAKECSR_ENABLE;
2133 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2134 csr |= WOL_WAKECSR_MII;
2135 writel(csr, gp->regs + WOL_WAKECSR);
2136 } else {
2137 writel(0, gp->regs + MAC_RXCFG);
2138 (void)readl(gp->regs + MAC_RXCFG);
2139 /* Machine sleep will die in strange ways if we
2140 * dont wait a bit here, looks like the chip takes
2141 * some time to really shut down
2142 */
2143 msleep(10);
2144 }
2145
2146 writel(0, gp->regs + MAC_TXCFG);
2147 writel(0, gp->regs + MAC_XIFCFG);
2148 writel(0, gp->regs + TXDMA_CFG);
2149 writel(0, gp->regs + RXDMA_CFG);
2150
2151 if (!wol) {
2152 spin_lock_irqsave(&gp->lock, flags);
2153 spin_lock(&gp->tx_lock);
2154 gem_reset(gp);
2155 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2156 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2157 spin_unlock(&gp->tx_lock);
2158 spin_unlock_irqrestore(&gp->lock, flags);
2159
2160 /* No need to take the lock here */
2161
2162 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2163 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2164
2165 /* According to Apple, we must set the MDIO pins to this begnign
2166 * state or we may 1) eat more current, 2) damage some PHYs
2167 */
2168 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2169 writel(0, gp->regs + MIF_BBCLK);
2170 writel(0, gp->regs + MIF_BBDATA);
2171 writel(0, gp->regs + MIF_BBOENAB);
2172 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2173 (void) readl(gp->regs + MAC_XIFCFG);
2174 }
2175 }
2176
2177
2178 static int gem_do_start(struct net_device *dev)
2179 {
2180 struct gem *gp = netdev_priv(dev);
2181 unsigned long flags;
2182
2183 spin_lock_irqsave(&gp->lock, flags);
2184 spin_lock(&gp->tx_lock);
2185
2186 /* Enable the cell */
2187 gem_get_cell(gp);
2188
2189 /* Init & setup chip hardware */
2190 gem_reinit_chip(gp);
2191
2192 gp->running = 1;
2193
2194 napi_enable(&gp->napi);
2195
2196 if (gp->lstate == link_up) {
2197 netif_carrier_on(gp->dev);
2198 gem_set_link_modes(gp);
2199 }
2200
2201 netif_wake_queue(gp->dev);
2202
2203 spin_unlock(&gp->tx_lock);
2204 spin_unlock_irqrestore(&gp->lock, flags);
2205
2206 if (request_irq(gp->pdev->irq, gem_interrupt,
2207 IRQF_SHARED, dev->name, (void *)dev)) {
2208 netdev_err(dev, "failed to request irq !\n");
2209
2210 spin_lock_irqsave(&gp->lock, flags);
2211 spin_lock(&gp->tx_lock);
2212
2213 napi_disable(&gp->napi);
2214
2215 gp->running = 0;
2216 gem_reset(gp);
2217 gem_clean_rings(gp);
2218 gem_put_cell(gp);
2219
2220 spin_unlock(&gp->tx_lock);
2221 spin_unlock_irqrestore(&gp->lock, flags);
2222
2223 return -EAGAIN;
2224 }
2225
2226 return 0;
2227 }
2228
2229 static void gem_do_stop(struct net_device *dev, int wol)
2230 {
2231 struct gem *gp = netdev_priv(dev);
2232 unsigned long flags;
2233
2234 spin_lock_irqsave(&gp->lock, flags);
2235 spin_lock(&gp->tx_lock);
2236
2237 gp->running = 0;
2238
2239 /* Stop netif queue */
2240 netif_stop_queue(dev);
2241
2242 /* Make sure ints are disabled */
2243 gem_disable_ints(gp);
2244
2245 /* We can drop the lock now */
2246 spin_unlock(&gp->tx_lock);
2247 spin_unlock_irqrestore(&gp->lock, flags);
2248
2249 /* If we are going to sleep with WOL */
2250 gem_stop_dma(gp);
2251 msleep(10);
2252 if (!wol)
2253 gem_reset(gp);
2254 msleep(10);
2255
2256 /* Get rid of rings */
2257 gem_clean_rings(gp);
2258
2259 /* No irq needed anymore */
2260 free_irq(gp->pdev->irq, (void *) dev);
2261
2262 /* Cell not needed neither if no WOL */
2263 if (!wol) {
2264 spin_lock_irqsave(&gp->lock, flags);
2265 gem_put_cell(gp);
2266 spin_unlock_irqrestore(&gp->lock, flags);
2267 }
2268 }
2269
2270 static void gem_reset_task(struct work_struct *work)
2271 {
2272 struct gem *gp = container_of(work, struct gem, reset_task);
2273
2274 mutex_lock(&gp->pm_mutex);
2275
2276 if (gp->opened)
2277 napi_disable(&gp->napi);
2278
2279 spin_lock_irq(&gp->lock);
2280 spin_lock(&gp->tx_lock);
2281
2282 if (gp->running) {
2283 netif_stop_queue(gp->dev);
2284
2285 /* Reset the chip & rings */
2286 gem_reinit_chip(gp);
2287 if (gp->lstate == link_up)
2288 gem_set_link_modes(gp);
2289 netif_wake_queue(gp->dev);
2290 }
2291
2292 gp->reset_task_pending = 0;
2293
2294 spin_unlock(&gp->tx_lock);
2295 spin_unlock_irq(&gp->lock);
2296
2297 if (gp->opened)
2298 napi_enable(&gp->napi);
2299
2300 mutex_unlock(&gp->pm_mutex);
2301 }
2302
2303
2304 static int gem_open(struct net_device *dev)
2305 {
2306 struct gem *gp = netdev_priv(dev);
2307 int rc = 0;
2308
2309 mutex_lock(&gp->pm_mutex);
2310
2311 /* We need the cell enabled */
2312 if (!gp->asleep)
2313 rc = gem_do_start(dev);
2314 gp->opened = (rc == 0);
2315
2316 mutex_unlock(&gp->pm_mutex);
2317
2318 return rc;
2319 }
2320
2321 static int gem_close(struct net_device *dev)
2322 {
2323 struct gem *gp = netdev_priv(dev);
2324
2325 mutex_lock(&gp->pm_mutex);
2326
2327 napi_disable(&gp->napi);
2328
2329 gp->opened = 0;
2330 if (!gp->asleep)
2331 gem_do_stop(dev, 0);
2332
2333 mutex_unlock(&gp->pm_mutex);
2334
2335 return 0;
2336 }
2337
2338 #ifdef CONFIG_PM
2339 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2340 {
2341 struct net_device *dev = pci_get_drvdata(pdev);
2342 struct gem *gp = netdev_priv(dev);
2343 unsigned long flags;
2344
2345 mutex_lock(&gp->pm_mutex);
2346
2347 netdev_info(dev, "suspending, WakeOnLan %s\n",
2348 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
2349
2350 /* Keep the cell enabled during the entire operation */
2351 spin_lock_irqsave(&gp->lock, flags);
2352 spin_lock(&gp->tx_lock);
2353 gem_get_cell(gp);
2354 spin_unlock(&gp->tx_lock);
2355 spin_unlock_irqrestore(&gp->lock, flags);
2356
2357 /* If the driver is opened, we stop the MAC */
2358 if (gp->opened) {
2359 napi_disable(&gp->napi);
2360
2361 /* Stop traffic, mark us closed */
2362 netif_device_detach(dev);
2363
2364 /* Switch off MAC, remember WOL setting */
2365 gp->asleep_wol = gp->wake_on_lan;
2366 gem_do_stop(dev, gp->asleep_wol);
2367 } else
2368 gp->asleep_wol = 0;
2369
2370 /* Mark us asleep */
2371 gp->asleep = 1;
2372 wmb();
2373
2374 /* Stop the link timer */
2375 del_timer_sync(&gp->link_timer);
2376
2377 /* Now we release the mutex to not block the reset task who
2378 * can take it too. We are marked asleep, so there will be no
2379 * conflict here
2380 */
2381 mutex_unlock(&gp->pm_mutex);
2382
2383 /* Wait for the pending reset task to complete */
2384 flush_work_sync(&gp->reset_task);
2385
2386 /* Shut the PHY down eventually and setup WOL */
2387 gem_stop_phy(gp, gp->asleep_wol);
2388
2389 /* Make sure bus master is disabled */
2390 pci_disable_device(gp->pdev);
2391
2392 /* Release the cell, no need to take a lock at this point since
2393 * nothing else can happen now
2394 */
2395 gem_put_cell(gp);
2396
2397 return 0;
2398 }
2399
2400 static int gem_resume(struct pci_dev *pdev)
2401 {
2402 struct net_device *dev = pci_get_drvdata(pdev);
2403 struct gem *gp = netdev_priv(dev);
2404 unsigned long flags;
2405
2406 netdev_info(dev, "resuming\n");
2407
2408 mutex_lock(&gp->pm_mutex);
2409
2410 /* Keep the cell enabled during the entire operation, no need to
2411 * take a lock here tho since nothing else can happen while we are
2412 * marked asleep
2413 */
2414 gem_get_cell(gp);
2415
2416 /* Make sure PCI access and bus master are enabled */
2417 if (pci_enable_device(gp->pdev)) {
2418 netdev_err(dev, "Can't re-enable chip !\n");
2419 /* Put cell and forget it for now, it will be considered as
2420 * still asleep, a new sleep cycle may bring it back
2421 */
2422 gem_put_cell(gp);
2423 mutex_unlock(&gp->pm_mutex);
2424 return 0;
2425 }
2426 pci_set_master(gp->pdev);
2427
2428 /* Reset everything */
2429 gem_reset(gp);
2430
2431 /* Mark us woken up */
2432 gp->asleep = 0;
2433 wmb();
2434
2435 /* Bring the PHY back. Again, lock is useless at this point as
2436 * nothing can be happening until we restart the whole thing
2437 */
2438 gem_init_phy(gp);
2439
2440 /* If we were opened, bring everything back */
2441 if (gp->opened) {
2442 /* Restart MAC */
2443 gem_do_start(dev);
2444
2445 /* Re-attach net device */
2446 netif_device_attach(dev);
2447 }
2448
2449 spin_lock_irqsave(&gp->lock, flags);
2450 spin_lock(&gp->tx_lock);
2451
2452 /* If we had WOL enabled, the cell clock was never turned off during
2453 * sleep, so we end up beeing unbalanced. Fix that here
2454 */
2455 if (gp->asleep_wol)
2456 gem_put_cell(gp);
2457
2458 /* This function doesn't need to hold the cell, it will be held if the
2459 * driver is open by gem_do_start().
2460 */
2461 gem_put_cell(gp);
2462
2463 spin_unlock(&gp->tx_lock);
2464 spin_unlock_irqrestore(&gp->lock, flags);
2465
2466 mutex_unlock(&gp->pm_mutex);
2467
2468 return 0;
2469 }
2470 #endif /* CONFIG_PM */
2471
2472 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2473 {
2474 struct gem *gp = netdev_priv(dev);
2475
2476 spin_lock_irq(&gp->lock);
2477 spin_lock(&gp->tx_lock);
2478
2479 /* I have seen this being called while the PM was in progress,
2480 * so we shield against this
2481 */
2482 if (gp->running) {
2483 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2484 writel(0, gp->regs + MAC_FCSERR);
2485
2486 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2487 writel(0, gp->regs + MAC_AERR);
2488
2489 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2490 writel(0, gp->regs + MAC_LERR);
2491
2492 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2493 dev->stats.collisions +=
2494 (readl(gp->regs + MAC_ECOLL) +
2495 readl(gp->regs + MAC_LCOLL));
2496 writel(0, gp->regs + MAC_ECOLL);
2497 writel(0, gp->regs + MAC_LCOLL);
2498 }
2499
2500 spin_unlock(&gp->tx_lock);
2501 spin_unlock_irq(&gp->lock);
2502
2503 return &dev->stats;
2504 }
2505
2506 static int gem_set_mac_address(struct net_device *dev, void *addr)
2507 {
2508 struct sockaddr *macaddr = (struct sockaddr *) addr;
2509 struct gem *gp = netdev_priv(dev);
2510 unsigned char *e = &dev->dev_addr[0];
2511
2512 if (!is_valid_ether_addr(macaddr->sa_data))
2513 return -EADDRNOTAVAIL;
2514
2515 if (!netif_running(dev) || !netif_device_present(dev)) {
2516 /* We'll just catch it later when the
2517 * device is up'd or resumed.
2518 */
2519 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2520 return 0;
2521 }
2522
2523 mutex_lock(&gp->pm_mutex);
2524 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2525 if (gp->running) {
2526 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2527 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2528 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2529 }
2530 mutex_unlock(&gp->pm_mutex);
2531
2532 return 0;
2533 }
2534
2535 static void gem_set_multicast(struct net_device *dev)
2536 {
2537 struct gem *gp = netdev_priv(dev);
2538 u32 rxcfg, rxcfg_new;
2539 int limit = 10000;
2540
2541
2542 spin_lock_irq(&gp->lock);
2543 spin_lock(&gp->tx_lock);
2544
2545 if (!gp->running)
2546 goto bail;
2547
2548 netif_stop_queue(dev);
2549
2550 rxcfg = readl(gp->regs + MAC_RXCFG);
2551 rxcfg_new = gem_setup_multicast(gp);
2552 #ifdef STRIP_FCS
2553 rxcfg_new |= MAC_RXCFG_SFCS;
2554 #endif
2555 gp->mac_rx_cfg = rxcfg_new;
2556
2557 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2558 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2559 if (!limit--)
2560 break;
2561 udelay(10);
2562 }
2563
2564 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2565 rxcfg |= rxcfg_new;
2566
2567 writel(rxcfg, gp->regs + MAC_RXCFG);
2568
2569 netif_wake_queue(dev);
2570
2571 bail:
2572 spin_unlock(&gp->tx_lock);
2573 spin_unlock_irq(&gp->lock);
2574 }
2575
2576 /* Jumbo-grams don't seem to work :-( */
2577 #define GEM_MIN_MTU 68
2578 #if 1
2579 #define GEM_MAX_MTU 1500
2580 #else
2581 #define GEM_MAX_MTU 9000
2582 #endif
2583
2584 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2585 {
2586 struct gem *gp = netdev_priv(dev);
2587
2588 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2589 return -EINVAL;
2590
2591 if (!netif_running(dev) || !netif_device_present(dev)) {
2592 /* We'll just catch it later when the
2593 * device is up'd or resumed.
2594 */
2595 dev->mtu = new_mtu;
2596 return 0;
2597 }
2598
2599 mutex_lock(&gp->pm_mutex);
2600 spin_lock_irq(&gp->lock);
2601 spin_lock(&gp->tx_lock);
2602 dev->mtu = new_mtu;
2603 if (gp->running) {
2604 gem_reinit_chip(gp);
2605 if (gp->lstate == link_up)
2606 gem_set_link_modes(gp);
2607 }
2608 spin_unlock(&gp->tx_lock);
2609 spin_unlock_irq(&gp->lock);
2610 mutex_unlock(&gp->pm_mutex);
2611
2612 return 0;
2613 }
2614
2615 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2616 {
2617 struct gem *gp = netdev_priv(dev);
2618
2619 strcpy(info->driver, DRV_NAME);
2620 strcpy(info->version, DRV_VERSION);
2621 strcpy(info->bus_info, pci_name(gp->pdev));
2622 }
2623
2624 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2625 {
2626 struct gem *gp = netdev_priv(dev);
2627
2628 if (gp->phy_type == phy_mii_mdio0 ||
2629 gp->phy_type == phy_mii_mdio1) {
2630 if (gp->phy_mii.def)
2631 cmd->supported = gp->phy_mii.def->features;
2632 else
2633 cmd->supported = (SUPPORTED_10baseT_Half |
2634 SUPPORTED_10baseT_Full);
2635
2636 /* XXX hardcoded stuff for now */
2637 cmd->port = PORT_MII;
2638 cmd->transceiver = XCVR_EXTERNAL;
2639 cmd->phy_address = 0; /* XXX fixed PHYAD */
2640
2641 /* Return current PHY settings */
2642 spin_lock_irq(&gp->lock);
2643 cmd->autoneg = gp->want_autoneg;
2644 ethtool_cmd_speed_set(cmd, gp->phy_mii.speed);
2645 cmd->duplex = gp->phy_mii.duplex;
2646 cmd->advertising = gp->phy_mii.advertising;
2647
2648 /* If we started with a forced mode, we don't have a default
2649 * advertise set, we need to return something sensible so
2650 * userland can re-enable autoneg properly.
2651 */
2652 if (cmd->advertising == 0)
2653 cmd->advertising = cmd->supported;
2654 spin_unlock_irq(&gp->lock);
2655 } else { // XXX PCS ?
2656 cmd->supported =
2657 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2658 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2659 SUPPORTED_Autoneg);
2660 cmd->advertising = cmd->supported;
2661 ethtool_cmd_speed_set(cmd, 0);
2662 cmd->duplex = cmd->port = cmd->phy_address =
2663 cmd->transceiver = cmd->autoneg = 0;
2664
2665 /* serdes means usually a Fibre connector, with most fixed */
2666 if (gp->phy_type == phy_serdes) {
2667 cmd->port = PORT_FIBRE;
2668 cmd->supported = (SUPPORTED_1000baseT_Half |
2669 SUPPORTED_1000baseT_Full |
2670 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2671 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2672 cmd->advertising = cmd->supported;
2673 cmd->transceiver = XCVR_INTERNAL;
2674 if (gp->lstate == link_up)
2675 ethtool_cmd_speed_set(cmd, SPEED_1000);
2676 cmd->duplex = DUPLEX_FULL;
2677 cmd->autoneg = 1;
2678 }
2679 }
2680 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2681
2682 return 0;
2683 }
2684
2685 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2686 {
2687 struct gem *gp = netdev_priv(dev);
2688 u32 speed = ethtool_cmd_speed(cmd);
2689
2690 /* Verify the settings we care about. */
2691 if (cmd->autoneg != AUTONEG_ENABLE &&
2692 cmd->autoneg != AUTONEG_DISABLE)
2693 return -EINVAL;
2694
2695 if (cmd->autoneg == AUTONEG_ENABLE &&
2696 cmd->advertising == 0)
2697 return -EINVAL;
2698
2699 if (cmd->autoneg == AUTONEG_DISABLE &&
2700 ((speed != SPEED_1000 &&
2701 speed != SPEED_100 &&
2702 speed != SPEED_10) ||
2703 (cmd->duplex != DUPLEX_HALF &&
2704 cmd->duplex != DUPLEX_FULL)))
2705 return -EINVAL;
2706
2707 /* Apply settings and restart link process. */
2708 spin_lock_irq(&gp->lock);
2709 gem_get_cell(gp);
2710 gem_begin_auto_negotiation(gp, cmd);
2711 gem_put_cell(gp);
2712 spin_unlock_irq(&gp->lock);
2713
2714 return 0;
2715 }
2716
2717 static int gem_nway_reset(struct net_device *dev)
2718 {
2719 struct gem *gp = netdev_priv(dev);
2720
2721 if (!gp->want_autoneg)
2722 return -EINVAL;
2723
2724 /* Restart link process. */
2725 spin_lock_irq(&gp->lock);
2726 gem_get_cell(gp);
2727 gem_begin_auto_negotiation(gp, NULL);
2728 gem_put_cell(gp);
2729 spin_unlock_irq(&gp->lock);
2730
2731 return 0;
2732 }
2733
2734 static u32 gem_get_msglevel(struct net_device *dev)
2735 {
2736 struct gem *gp = netdev_priv(dev);
2737 return gp->msg_enable;
2738 }
2739
2740 static void gem_set_msglevel(struct net_device *dev, u32 value)
2741 {
2742 struct gem *gp = netdev_priv(dev);
2743 gp->msg_enable = value;
2744 }
2745
2746
2747 /* Add more when I understand how to program the chip */
2748 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2749
2750 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2751
2752 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2753 {
2754 struct gem *gp = netdev_priv(dev);
2755
2756 /* Add more when I understand how to program the chip */
2757 if (gp->has_wol) {
2758 wol->supported = WOL_SUPPORTED_MASK;
2759 wol->wolopts = gp->wake_on_lan;
2760 } else {
2761 wol->supported = 0;
2762 wol->wolopts = 0;
2763 }
2764 }
2765
2766 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2767 {
2768 struct gem *gp = netdev_priv(dev);
2769
2770 if (!gp->has_wol)
2771 return -EOPNOTSUPP;
2772 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2773 return 0;
2774 }
2775
2776 static const struct ethtool_ops gem_ethtool_ops = {
2777 .get_drvinfo = gem_get_drvinfo,
2778 .get_link = ethtool_op_get_link,
2779 .get_settings = gem_get_settings,
2780 .set_settings = gem_set_settings,
2781 .nway_reset = gem_nway_reset,
2782 .get_msglevel = gem_get_msglevel,
2783 .set_msglevel = gem_set_msglevel,
2784 .get_wol = gem_get_wol,
2785 .set_wol = gem_set_wol,
2786 };
2787
2788 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2789 {
2790 struct gem *gp = netdev_priv(dev);
2791 struct mii_ioctl_data *data = if_mii(ifr);
2792 int rc = -EOPNOTSUPP;
2793 unsigned long flags;
2794
2795 /* Hold the PM mutex while doing ioctl's or we may collide
2796 * with power management.
2797 */
2798 mutex_lock(&gp->pm_mutex);
2799
2800 spin_lock_irqsave(&gp->lock, flags);
2801 gem_get_cell(gp);
2802 spin_unlock_irqrestore(&gp->lock, flags);
2803
2804 switch (cmd) {
2805 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2806 data->phy_id = gp->mii_phy_addr;
2807 /* Fallthrough... */
2808
2809 case SIOCGMIIREG: /* Read MII PHY register. */
2810 if (!gp->running)
2811 rc = -EAGAIN;
2812 else {
2813 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2814 data->reg_num & 0x1f);
2815 rc = 0;
2816 }
2817 break;
2818
2819 case SIOCSMIIREG: /* Write MII PHY register. */
2820 if (!gp->running)
2821 rc = -EAGAIN;
2822 else {
2823 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2824 data->val_in);
2825 rc = 0;
2826 }
2827 break;
2828 };
2829
2830 spin_lock_irqsave(&gp->lock, flags);
2831 gem_put_cell(gp);
2832 spin_unlock_irqrestore(&gp->lock, flags);
2833
2834 mutex_unlock(&gp->pm_mutex);
2835
2836 return rc;
2837 }
2838
2839 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2840 /* Fetch MAC address from vital product data of PCI ROM. */
2841 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2842 {
2843 int this_offset;
2844
2845 for (this_offset = 0x20; this_offset < len; this_offset++) {
2846 void __iomem *p = rom_base + this_offset;
2847 int i;
2848
2849 if (readb(p + 0) != 0x90 ||
2850 readb(p + 1) != 0x00 ||
2851 readb(p + 2) != 0x09 ||
2852 readb(p + 3) != 0x4e ||
2853 readb(p + 4) != 0x41 ||
2854 readb(p + 5) != 0x06)
2855 continue;
2856
2857 this_offset += 6;
2858 p += 6;
2859
2860 for (i = 0; i < 6; i++)
2861 dev_addr[i] = readb(p + i);
2862 return 1;
2863 }
2864 return 0;
2865 }
2866
2867 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2868 {
2869 size_t size;
2870 void __iomem *p = pci_map_rom(pdev, &size);
2871
2872 if (p) {
2873 int found;
2874
2875 found = readb(p) == 0x55 &&
2876 readb(p + 1) == 0xaa &&
2877 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2878 pci_unmap_rom(pdev, p);
2879 if (found)
2880 return;
2881 }
2882
2883 /* Sun MAC prefix then 3 random bytes. */
2884 dev_addr[0] = 0x08;
2885 dev_addr[1] = 0x00;
2886 dev_addr[2] = 0x20;
2887 get_random_bytes(dev_addr + 3, 3);
2888 }
2889 #endif /* not Sparc and not PPC */
2890
2891 static int __devinit gem_get_device_address(struct gem *gp)
2892 {
2893 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2894 struct net_device *dev = gp->dev;
2895 const unsigned char *addr;
2896
2897 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2898 if (addr == NULL) {
2899 #ifdef CONFIG_SPARC
2900 addr = idprom->id_ethaddr;
2901 #else
2902 printk("\n");
2903 pr_err("%s: can't get mac-address\n", dev->name);
2904 return -1;
2905 #endif
2906 }
2907 memcpy(dev->dev_addr, addr, 6);
2908 #else
2909 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2910 #endif
2911 return 0;
2912 }
2913
2914 static void gem_remove_one(struct pci_dev *pdev)
2915 {
2916 struct net_device *dev = pci_get_drvdata(pdev);
2917
2918 if (dev) {
2919 struct gem *gp = netdev_priv(dev);
2920
2921 unregister_netdev(dev);
2922
2923 /* Stop the link timer */
2924 del_timer_sync(&gp->link_timer);
2925
2926 /* We shouldn't need any locking here */
2927 gem_get_cell(gp);
2928
2929 /* Cancel reset task */
2930 cancel_work_sync(&gp->reset_task);
2931
2932 /* Shut the PHY down */
2933 gem_stop_phy(gp, 0);
2934
2935 gem_put_cell(gp);
2936
2937 /* Make sure bus master is disabled */
2938 pci_disable_device(gp->pdev);
2939
2940 /* Free resources */
2941 pci_free_consistent(pdev,
2942 sizeof(struct gem_init_block),
2943 gp->init_block,
2944 gp->gblock_dvma);
2945 iounmap(gp->regs);
2946 pci_release_regions(pdev);
2947 free_netdev(dev);
2948
2949 pci_set_drvdata(pdev, NULL);
2950 }
2951 }
2952
2953 static const struct net_device_ops gem_netdev_ops = {
2954 .ndo_open = gem_open,
2955 .ndo_stop = gem_close,
2956 .ndo_start_xmit = gem_start_xmit,
2957 .ndo_get_stats = gem_get_stats,
2958 .ndo_set_multicast_list = gem_set_multicast,
2959 .ndo_do_ioctl = gem_ioctl,
2960 .ndo_tx_timeout = gem_tx_timeout,
2961 .ndo_change_mtu = gem_change_mtu,
2962 .ndo_validate_addr = eth_validate_addr,
2963 .ndo_set_mac_address = gem_set_mac_address,
2964 #ifdef CONFIG_NET_POLL_CONTROLLER
2965 .ndo_poll_controller = gem_poll_controller,
2966 #endif
2967 };
2968
2969 static int __devinit gem_init_one(struct pci_dev *pdev,
2970 const struct pci_device_id *ent)
2971 {
2972 unsigned long gemreg_base, gemreg_len;
2973 struct net_device *dev;
2974 struct gem *gp;
2975 int err, pci_using_dac;
2976
2977 printk_once(KERN_INFO "%s", version);
2978
2979 /* Apple gmac note: during probe, the chip is powered up by
2980 * the arch code to allow the code below to work (and to let
2981 * the chip be probed on the config space. It won't stay powered
2982 * up until the interface is brought up however, so we can't rely
2983 * on register configuration done at this point.
2984 */
2985 err = pci_enable_device(pdev);
2986 if (err) {
2987 pr_err("Cannot enable MMIO operation, aborting\n");
2988 return err;
2989 }
2990 pci_set_master(pdev);
2991
2992 /* Configure DMA attributes. */
2993
2994 /* All of the GEM documentation states that 64-bit DMA addressing
2995 * is fully supported and should work just fine. However the
2996 * front end for RIO based GEMs is different and only supports
2997 * 32-bit addressing.
2998 *
2999 * For now we assume the various PPC GEMs are 32-bit only as well.
3000 */
3001 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
3002 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
3003 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3004 pci_using_dac = 1;
3005 } else {
3006 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3007 if (err) {
3008 pr_err("No usable DMA configuration, aborting\n");
3009 goto err_disable_device;
3010 }
3011 pci_using_dac = 0;
3012 }
3013
3014 gemreg_base = pci_resource_start(pdev, 0);
3015 gemreg_len = pci_resource_len(pdev, 0);
3016
3017 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3018 pr_err("Cannot find proper PCI device base address, aborting\n");
3019 err = -ENODEV;
3020 goto err_disable_device;
3021 }
3022
3023 dev = alloc_etherdev(sizeof(*gp));
3024 if (!dev) {
3025 pr_err("Etherdev alloc failed, aborting\n");
3026 err = -ENOMEM;
3027 goto err_disable_device;
3028 }
3029 SET_NETDEV_DEV(dev, &pdev->dev);
3030
3031 gp = netdev_priv(dev);
3032
3033 err = pci_request_regions(pdev, DRV_NAME);
3034 if (err) {
3035 pr_err("Cannot obtain PCI resources, aborting\n");
3036 goto err_out_free_netdev;
3037 }
3038
3039 gp->pdev = pdev;
3040 dev->base_addr = (long) pdev;
3041 gp->dev = dev;
3042
3043 gp->msg_enable = DEFAULT_MSG;
3044
3045 spin_lock_init(&gp->lock);
3046 spin_lock_init(&gp->tx_lock);
3047 mutex_init(&gp->pm_mutex);
3048
3049 init_timer(&gp->link_timer);
3050 gp->link_timer.function = gem_link_timer;
3051 gp->link_timer.data = (unsigned long) gp;
3052
3053 INIT_WORK(&gp->reset_task, gem_reset_task);
3054
3055 gp->lstate = link_down;
3056 gp->timer_ticks = 0;
3057 netif_carrier_off(dev);
3058
3059 gp->regs = ioremap(gemreg_base, gemreg_len);
3060 if (!gp->regs) {
3061 pr_err("Cannot map device registers, aborting\n");
3062 err = -EIO;
3063 goto err_out_free_res;
3064 }
3065
3066 /* On Apple, we want a reference to the Open Firmware device-tree
3067 * node. We use it for clock control.
3068 */
3069 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
3070 gp->of_node = pci_device_to_OF_node(pdev);
3071 #endif
3072
3073 /* Only Apple version supports WOL afaik */
3074 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3075 gp->has_wol = 1;
3076
3077 /* Make sure cell is enabled */
3078 gem_get_cell(gp);
3079
3080 /* Make sure everything is stopped and in init state */
3081 gem_reset(gp);
3082
3083 /* Fill up the mii_phy structure (even if we won't use it) */
3084 gp->phy_mii.dev = dev;
3085 gp->phy_mii.mdio_read = _phy_read;
3086 gp->phy_mii.mdio_write = _phy_write;
3087 #ifdef CONFIG_PPC_PMAC
3088 gp->phy_mii.platform_data = gp->of_node;
3089 #endif
3090 /* By default, we start with autoneg */
3091 gp->want_autoneg = 1;
3092
3093 /* Check fifo sizes, PHY type, etc... */
3094 if (gem_check_invariants(gp)) {
3095 err = -ENODEV;
3096 goto err_out_iounmap;
3097 }
3098
3099 /* It is guaranteed that the returned buffer will be at least
3100 * PAGE_SIZE aligned.
3101 */
3102 gp->init_block = (struct gem_init_block *)
3103 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3104 &gp->gblock_dvma);
3105 if (!gp->init_block) {
3106 pr_err("Cannot allocate init block, aborting\n");
3107 err = -ENOMEM;
3108 goto err_out_iounmap;
3109 }
3110
3111 if (gem_get_device_address(gp))
3112 goto err_out_free_consistent;
3113
3114 dev->netdev_ops = &gem_netdev_ops;
3115 netif_napi_add(dev, &gp->napi, gem_poll, 64);
3116 dev->ethtool_ops = &gem_ethtool_ops;
3117 dev->watchdog_timeo = 5 * HZ;
3118 dev->irq = pdev->irq;
3119 dev->dma = 0;
3120
3121 /* Set that now, in case PM kicks in now */
3122 pci_set_drvdata(pdev, dev);
3123
3124 /* Detect & init PHY, start autoneg, we release the cell now
3125 * too, it will be managed by whoever needs it
3126 */
3127 gem_init_phy(gp);
3128
3129 spin_lock_irq(&gp->lock);
3130 gem_put_cell(gp);
3131 spin_unlock_irq(&gp->lock);
3132
3133 /* Register with kernel */
3134 if (register_netdev(dev)) {
3135 pr_err("Cannot register net device, aborting\n");
3136 err = -ENOMEM;
3137 goto err_out_free_consistent;
3138 }
3139
3140 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3141 dev->dev_addr);
3142
3143 if (gp->phy_type == phy_mii_mdio0 ||
3144 gp->phy_type == phy_mii_mdio1)
3145 netdev_info(dev, "Found %s PHY\n",
3146 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3147
3148 /* GEM can do it all... */
3149 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
3150 dev->features |= dev->hw_features | NETIF_F_RXCSUM | NETIF_F_LLTX;
3151 if (pci_using_dac)
3152 dev->features |= NETIF_F_HIGHDMA;
3153
3154 return 0;
3155
3156 err_out_free_consistent:
3157 gem_remove_one(pdev);
3158 err_out_iounmap:
3159 gem_put_cell(gp);
3160 iounmap(gp->regs);
3161
3162 err_out_free_res:
3163 pci_release_regions(pdev);
3164
3165 err_out_free_netdev:
3166 free_netdev(dev);
3167 err_disable_device:
3168 pci_disable_device(pdev);
3169 return err;
3170
3171 }
3172
3173
3174 static struct pci_driver gem_driver = {
3175 .name = GEM_MODULE_NAME,
3176 .id_table = gem_pci_tbl,
3177 .probe = gem_init_one,
3178 .remove = gem_remove_one,
3179 #ifdef CONFIG_PM
3180 .suspend = gem_suspend,
3181 .resume = gem_resume,
3182 #endif /* CONFIG_PM */
3183 };
3184
3185 static int __init gem_init(void)
3186 {
3187 return pci_register_driver(&gem_driver);
3188 }
3189
3190 static void __exit gem_cleanup(void)
3191 {
3192 pci_unregister_driver(&gem_driver);
3193 }
3194
3195 module_init(gem_init);
3196 module_exit(gem_cleanup);
Linux kernel - Deliverables
This page took 0.093049 seconds and 6 git commands to generate.